FastISel.cpp revision 7e1e31f467d87c834d8baf673929865907901313
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/CodeGen/DwarfWriter.h" 51#include "llvm/Analysis/DebugInfo.h" 52#include "llvm/Target/TargetData.h" 53#include "llvm/Target/TargetInstrInfo.h" 54#include "llvm/Target/TargetLowering.h" 55#include "llvm/Target/TargetMachine.h" 56#include "SelectionDAGBuild.h" 57using namespace llvm; 58 59unsigned FastISel::getRegForValue(Value *V) { 60 MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 61 // Don't handle non-simple values in FastISel. 62 if (!RealVT.isSimple()) 63 return 0; 64 65 // Ignore illegal types. We must do this before looking up the value 66 // in ValueMap because Arguments are given virtual registers regardless 67 // of whether FastISel can handle them. 68 MVT::SimpleValueType VT = RealVT.getSimpleVT(); 69 if (!TLI.isTypeLegal(VT)) { 70 // Promote MVT::i1 to a legal type though, because it's common and easy. 71 if (VT == MVT::i1) 72 VT = TLI.getTypeToTransformTo(VT).getSimpleVT(); 73 else 74 return 0; 75 } 76 77 // Look up the value to see if we already have a register for it. We 78 // cache values defined by Instructions across blocks, and other values 79 // only locally. This is because Instructions already have the SSA 80 // def-dominatess-use requirement enforced. 81 if (ValueMap.count(V)) 82 return ValueMap[V]; 83 unsigned Reg = LocalValueMap[V]; 84 if (Reg != 0) 85 return Reg; 86 87 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 88 if (CI->getValue().getActiveBits() <= 64) 89 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 90 } else if (isa<AllocaInst>(V)) { 91 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 92 } else if (isa<ConstantPointerNull>(V)) { 93 // Translate this as an integer zero so that it can be 94 // local-CSE'd with actual integer zeros. 95 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType())); 96 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 97 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 98 99 if (!Reg) { 100 const APFloat &Flt = CF->getValueAPF(); 101 MVT IntVT = TLI.getPointerTy(); 102 103 uint64_t x[2]; 104 uint32_t IntBitWidth = IntVT.getSizeInBits(); 105 bool isExact; 106 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 107 APFloat::rmTowardZero, &isExact); 108 if (isExact) { 109 APInt IntVal(IntBitWidth, 2, x); 110 111 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal)); 112 if (IntegerReg != 0) 113 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 114 } 115 } 116 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 117 if (!SelectOperator(CE, CE->getOpcode())) return 0; 118 Reg = LocalValueMap[CE]; 119 } else if (isa<UndefValue>(V)) { 120 Reg = createResultReg(TLI.getRegClassFor(VT)); 121 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); 122 } 123 124 // If target-independent code couldn't handle the value, give target-specific 125 // code a try. 126 if (!Reg && isa<Constant>(V)) 127 Reg = TargetMaterializeConstant(cast<Constant>(V)); 128 129 // Don't cache constant materializations in the general ValueMap. 130 // To do so would require tracking what uses they dominate. 131 if (Reg != 0) 132 LocalValueMap[V] = Reg; 133 return Reg; 134} 135 136unsigned FastISel::lookUpRegForValue(Value *V) { 137 // Look up the value to see if we already have a register for it. We 138 // cache values defined by Instructions across blocks, and other values 139 // only locally. This is because Instructions already have the SSA 140 // def-dominatess-use requirement enforced. 141 if (ValueMap.count(V)) 142 return ValueMap[V]; 143 return LocalValueMap[V]; 144} 145 146/// UpdateValueMap - Update the value map to include the new mapping for this 147/// instruction, or insert an extra copy to get the result in a previous 148/// determined register. 149/// NOTE: This is only necessary because we might select a block that uses 150/// a value before we select the block that defines the value. It might be 151/// possible to fix this by selecting blocks in reverse postorder. 152unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) { 153 if (!isa<Instruction>(I)) { 154 LocalValueMap[I] = Reg; 155 return Reg; 156 } 157 158 unsigned &AssignedReg = ValueMap[I]; 159 if (AssignedReg == 0) 160 AssignedReg = Reg; 161 else if (Reg != AssignedReg) { 162 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); 163 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg, 164 Reg, RegClass, RegClass); 165 } 166 return AssignedReg; 167} 168 169unsigned FastISel::getRegForGEPIndex(Value *Idx) { 170 unsigned IdxN = getRegForValue(Idx); 171 if (IdxN == 0) 172 // Unhandled operand. Halt "fast" selection and bail. 173 return 0; 174 175 // If the index is smaller or larger than intptr_t, truncate or extend it. 176 MVT PtrVT = TLI.getPointerTy(); 177 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); 178 if (IdxVT.bitsLT(PtrVT)) 179 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 180 ISD::SIGN_EXTEND, IdxN); 181 else if (IdxVT.bitsGT(PtrVT)) 182 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 183 ISD::TRUNCATE, IdxN); 184 return IdxN; 185} 186 187/// SelectBinaryOp - Select and emit code for a binary operator instruction, 188/// which has an opcode which directly corresponds to the given ISD opcode. 189/// 190bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { 191 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); 192 if (VT == MVT::Other || !VT.isSimple()) 193 // Unhandled type. Halt "fast" selection and bail. 194 return false; 195 196 // We only handle legal types. For example, on x86-32 the instruction 197 // selector contains all of the 64-bit instructions from x86-64, 198 // under the assumption that i64 won't be used if the target doesn't 199 // support it. 200 if (!TLI.isTypeLegal(VT)) { 201 // MVT::i1 is special. Allow AND, OR, or XOR because they 202 // don't require additional zeroing, which makes them easy. 203 if (VT == MVT::i1 && 204 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 205 ISDOpcode == ISD::XOR)) 206 VT = TLI.getTypeToTransformTo(VT); 207 else 208 return false; 209 } 210 211 unsigned Op0 = getRegForValue(I->getOperand(0)); 212 if (Op0 == 0) 213 // Unhandled operand. Halt "fast" selection and bail. 214 return false; 215 216 // Check if the second operand is a constant and handle it appropriately. 217 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 218 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 219 ISDOpcode, Op0, CI->getZExtValue()); 220 if (ResultReg != 0) { 221 // We successfully emitted code for the given LLVM Instruction. 222 UpdateValueMap(I, ResultReg); 223 return true; 224 } 225 } 226 227 // Check if the second operand is a constant float. 228 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 229 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 230 ISDOpcode, Op0, CF); 231 if (ResultReg != 0) { 232 // We successfully emitted code for the given LLVM Instruction. 233 UpdateValueMap(I, ResultReg); 234 return true; 235 } 236 } 237 238 unsigned Op1 = getRegForValue(I->getOperand(1)); 239 if (Op1 == 0) 240 // Unhandled operand. Halt "fast" selection and bail. 241 return false; 242 243 // Now we have both operands in registers. Emit the instruction. 244 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 245 ISDOpcode, Op0, Op1); 246 if (ResultReg == 0) 247 // Target-specific code wasn't able to find a machine opcode for 248 // the given ISD opcode and type. Halt "fast" selection and bail. 249 return false; 250 251 // We successfully emitted code for the given LLVM Instruction. 252 UpdateValueMap(I, ResultReg); 253 return true; 254} 255 256bool FastISel::SelectGetElementPtr(User *I) { 257 unsigned N = getRegForValue(I->getOperand(0)); 258 if (N == 0) 259 // Unhandled operand. Halt "fast" selection and bail. 260 return false; 261 262 const Type *Ty = I->getOperand(0)->getType(); 263 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT(); 264 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 265 OI != E; ++OI) { 266 Value *Idx = *OI; 267 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 268 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 269 if (Field) { 270 // N = N + Offset 271 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 272 // FIXME: This can be optimized by combining the add with a 273 // subsequent one. 274 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 275 if (N == 0) 276 // Unhandled operand. Halt "fast" selection and bail. 277 return false; 278 } 279 Ty = StTy->getElementType(Field); 280 } else { 281 Ty = cast<SequentialType>(Ty)->getElementType(); 282 283 // If this is a constant subscript, handle it quickly. 284 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 285 if (CI->getZExtValue() == 0) continue; 286 uint64_t Offs = 287 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 288 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 289 if (N == 0) 290 // Unhandled operand. Halt "fast" selection and bail. 291 return false; 292 continue; 293 } 294 295 // N = N + Idx * ElementSize; 296 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 297 unsigned IdxN = getRegForGEPIndex(Idx); 298 if (IdxN == 0) 299 // Unhandled operand. Halt "fast" selection and bail. 300 return false; 301 302 if (ElementSize != 1) { 303 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 304 if (IdxN == 0) 305 // Unhandled operand. Halt "fast" selection and bail. 306 return false; 307 } 308 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 309 if (N == 0) 310 // Unhandled operand. Halt "fast" selection and bail. 311 return false; 312 } 313 } 314 315 // We successfully emitted code for the given LLVM Instruction. 316 UpdateValueMap(I, N); 317 return true; 318} 319 320bool FastISel::SelectCall(User *I) { 321 Function *F = cast<CallInst>(I)->getCalledFunction(); 322 if (!F) return false; 323 324 unsigned IID = F->getIntrinsicID(); 325 switch (IID) { 326 default: break; 327 case Intrinsic::dbg_stoppoint: { 328 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); 329 if (isValidDebugInfoIntrinsic(*SPI, CodeGenOpt::None)) 330 setCurDebugLoc(ExtractDebugLocation(*SPI, MF.getDebugLocInfo())); 331 return true; 332 } 333 case Intrinsic::dbg_region_start: { 334 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I); 335 if (isValidDebugInfoIntrinsic(*RSI, CodeGenOpt::None) && DW 336 && DW->ShouldEmitDwarfDebug()) { 337 unsigned ID = 338 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext())); 339 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 340 BuildMI(MBB, DL, II).addImm(ID); 341 } 342 return true; 343 } 344 case Intrinsic::dbg_region_end: { 345 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I); 346 if (isValidDebugInfoIntrinsic(*REI, CodeGenOpt::None) && DW 347 && DW->ShouldEmitDwarfDebug()) { 348 unsigned ID = 0; 349 DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext())); 350 if (isInlinedFnEnd(*REI, MF.getFunction())) { 351 // This is end of an inlined function. 352 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 353 ID = DW->RecordInlinedFnEnd(Subprogram); 354 if (ID) 355 // Returned ID is 0 if this is unbalanced "end of inlined 356 // scope". This could happen if optimizer eats dbg intrinsics 357 // or "beginning of inlined scope" is not recoginized due to 358 // missing location info. In such cases, ignore this region.end. 359 BuildMI(MBB, DL, II).addImm(ID); 360 } else { 361 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 362 ID = DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext())); 363 BuildMI(MBB, DL, II).addImm(ID); 364 } 365 } 366 return true; 367 } 368 case Intrinsic::dbg_func_start: { 369 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); 370 if (!isValidDebugInfoIntrinsic(*FSI, CodeGenOpt::None) || !DW 371 || !DW->ShouldEmitDwarfDebug()) 372 return true; 373 374 if (isInlinedFnStart(*FSI, MF.getFunction())) { 375 // This is a beginning of an inlined function. 376 377 // If llvm.dbg.func.start is seen in a new block before any 378 // llvm.dbg.stoppoint intrinsic then the location info is unknown. 379 // FIXME : Why DebugLoc is reset at the beginning of each block ? 380 DebugLoc PrevLoc = DL; 381 if (PrevLoc.isUnknown()) 382 return true; 383 // Record the source line. 384 setCurDebugLoc(ExtractDebugLocation(*FSI, MF.getDebugLocInfo())); 385 386 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc); 387 DISubprogram SP(cast<GlobalVariable>(FSI->getSubprogram())); 388 unsigned LabelID = DW->RecordInlinedFnStart(SP, 389 DICompileUnit(PrevLocTpl.CompileUnit), 390 PrevLocTpl.Line, 391 PrevLocTpl.Col); 392 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 393 BuildMI(MBB, DL, II).addImm(LabelID); 394 return true; 395 } 396 397 // This is a beginning of a new function. 398 MF.setDefaultDebugLoc(ExtractDebugLocation(*FSI, MF.getDebugLocInfo())); 399 400 // llvm.dbg.func_start also defines beginning of function scope. 401 DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram())); 402 return true; 403 } 404 case Intrinsic::dbg_declare: { 405 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 406 if (!isValidDebugInfoIntrinsic(*DI, CodeGenOpt::None) || !DW 407 || !DW->ShouldEmitDwarfDebug()) 408 return true; 409 410 Value *Variable = DI->getVariable(); 411 Value *Address = DI->getAddress(); 412 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 413 Address = BCI->getOperand(0); 414 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 415 // Don't handle byval struct arguments or VLAs, for example. 416 if (!AI) break; 417 DenseMap<const AllocaInst*, int>::iterator SI = 418 StaticAllocaMap.find(AI); 419 if (SI == StaticAllocaMap.end()) break; // VLAs. 420 int FI = SI->second; 421 422 // Determine the debug globalvariable. 423 GlobalValue *GV = cast<GlobalVariable>(Variable); 424 425 // Build the DECLARE instruction. 426 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE); 427 MachineInstr *DeclareMI 428 = BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV); 429 DIVariable DV(cast<GlobalVariable>(GV)); 430 DW->RecordVariableScope(DV, DeclareMI); 431 return true; 432 } 433 case Intrinsic::eh_exception: { 434 MVT VT = TLI.getValueType(I->getType()); 435 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 436 default: break; 437 case TargetLowering::Expand: { 438 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!"); 439 unsigned Reg = TLI.getExceptionAddressRegister(); 440 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 441 unsigned ResultReg = createResultReg(RC); 442 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 443 Reg, RC, RC); 444 assert(InsertedCopy && "Can't copy address registers!"); 445 InsertedCopy = InsertedCopy; 446 UpdateValueMap(I, ResultReg); 447 return true; 448 } 449 } 450 break; 451 } 452 case Intrinsic::eh_selector_i32: 453 case Intrinsic::eh_selector_i64: { 454 MVT VT = TLI.getValueType(I->getType()); 455 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 456 default: break; 457 case TargetLowering::Expand: { 458 MVT VT = (IID == Intrinsic::eh_selector_i32 ? 459 MVT::i32 : MVT::i64); 460 461 if (MMI) { 462 if (MBB->isLandingPad()) 463 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 464 else { 465#ifndef NDEBUG 466 CatchInfoLost.insert(cast<CallInst>(I)); 467#endif 468 // FIXME: Mark exception selector register as live in. Hack for PR1508. 469 unsigned Reg = TLI.getExceptionSelectorRegister(); 470 if (Reg) MBB->addLiveIn(Reg); 471 } 472 473 unsigned Reg = TLI.getExceptionSelectorRegister(); 474 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 475 unsigned ResultReg = createResultReg(RC); 476 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 477 Reg, RC, RC); 478 assert(InsertedCopy && "Can't copy address registers!"); 479 InsertedCopy = InsertedCopy; 480 UpdateValueMap(I, ResultReg); 481 } else { 482 unsigned ResultReg = 483 getRegForValue(Constant::getNullValue(I->getType())); 484 UpdateValueMap(I, ResultReg); 485 } 486 return true; 487 } 488 } 489 break; 490 } 491 } 492 return false; 493} 494 495bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { 496 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 497 MVT DstVT = TLI.getValueType(I->getType()); 498 499 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 500 DstVT == MVT::Other || !DstVT.isSimple()) 501 // Unhandled type. Halt "fast" selection and bail. 502 return false; 503 504 // Check if the destination type is legal. Or as a special case, 505 // it may be i1 if we're doing a truncate because that's 506 // easy and somewhat common. 507 if (!TLI.isTypeLegal(DstVT)) 508 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 509 // Unhandled type. Halt "fast" selection and bail. 510 return false; 511 512 // Check if the source operand is legal. Or as a special case, 513 // it may be i1 if we're doing zero-extension because that's 514 // easy and somewhat common. 515 if (!TLI.isTypeLegal(SrcVT)) 516 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 517 // Unhandled type. Halt "fast" selection and bail. 518 return false; 519 520 unsigned InputReg = getRegForValue(I->getOperand(0)); 521 if (!InputReg) 522 // Unhandled operand. Halt "fast" selection and bail. 523 return false; 524 525 // If the operand is i1, arrange for the high bits in the register to be zero. 526 if (SrcVT == MVT::i1) { 527 SrcVT = TLI.getTypeToTransformTo(SrcVT); 528 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 529 if (!InputReg) 530 return false; 531 } 532 // If the result is i1, truncate to the target's type for i1 first. 533 if (DstVT == MVT::i1) 534 DstVT = TLI.getTypeToTransformTo(DstVT); 535 536 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 537 DstVT.getSimpleVT(), 538 Opcode, 539 InputReg); 540 if (!ResultReg) 541 return false; 542 543 UpdateValueMap(I, ResultReg); 544 return true; 545} 546 547bool FastISel::SelectBitCast(User *I) { 548 // If the bitcast doesn't change the type, just use the operand value. 549 if (I->getType() == I->getOperand(0)->getType()) { 550 unsigned Reg = getRegForValue(I->getOperand(0)); 551 if (Reg == 0) 552 return false; 553 UpdateValueMap(I, Reg); 554 return true; 555 } 556 557 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 558 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 559 MVT DstVT = TLI.getValueType(I->getType()); 560 561 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 562 DstVT == MVT::Other || !DstVT.isSimple() || 563 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 564 // Unhandled type. Halt "fast" selection and bail. 565 return false; 566 567 unsigned Op0 = getRegForValue(I->getOperand(0)); 568 if (Op0 == 0) 569 // Unhandled operand. Halt "fast" selection and bail. 570 return false; 571 572 // First, try to perform the bitcast by inserting a reg-reg copy. 573 unsigned ResultReg = 0; 574 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 575 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 576 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 577 ResultReg = createResultReg(DstClass); 578 579 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 580 Op0, DstClass, SrcClass); 581 if (!InsertedCopy) 582 ResultReg = 0; 583 } 584 585 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 586 if (!ResultReg) 587 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 588 ISD::BIT_CONVERT, Op0); 589 590 if (!ResultReg) 591 return false; 592 593 UpdateValueMap(I, ResultReg); 594 return true; 595} 596 597bool 598FastISel::SelectInstruction(Instruction *I) { 599 return SelectOperator(I, I->getOpcode()); 600} 601 602/// FastEmitBranch - Emit an unconditional branch to the given block, 603/// unless it is the immediate (fall-through) successor, and update 604/// the CFG. 605void 606FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 607 MachineFunction::iterator NextMBB = 608 next(MachineFunction::iterator(MBB)); 609 610 if (MBB->isLayoutSuccessor(MSucc)) { 611 // The unconditional fall-through case, which needs no instructions. 612 } else { 613 // The unconditional branch case. 614 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 615 } 616 MBB->addSuccessor(MSucc); 617} 618 619bool 620FastISel::SelectOperator(User *I, unsigned Opcode) { 621 switch (Opcode) { 622 case Instruction::Add: 623 return SelectBinaryOp(I, ISD::ADD); 624 case Instruction::FAdd: 625 return SelectBinaryOp(I, ISD::FADD); 626 case Instruction::Sub: 627 return SelectBinaryOp(I, ISD::SUB); 628 case Instruction::FSub: 629 return SelectBinaryOp(I, ISD::FSUB); 630 case Instruction::Mul: 631 return SelectBinaryOp(I, ISD::MUL); 632 case Instruction::FMul: 633 return SelectBinaryOp(I, ISD::FMUL); 634 case Instruction::SDiv: 635 return SelectBinaryOp(I, ISD::SDIV); 636 case Instruction::UDiv: 637 return SelectBinaryOp(I, ISD::UDIV); 638 case Instruction::FDiv: 639 return SelectBinaryOp(I, ISD::FDIV); 640 case Instruction::SRem: 641 return SelectBinaryOp(I, ISD::SREM); 642 case Instruction::URem: 643 return SelectBinaryOp(I, ISD::UREM); 644 case Instruction::FRem: 645 return SelectBinaryOp(I, ISD::FREM); 646 case Instruction::Shl: 647 return SelectBinaryOp(I, ISD::SHL); 648 case Instruction::LShr: 649 return SelectBinaryOp(I, ISD::SRL); 650 case Instruction::AShr: 651 return SelectBinaryOp(I, ISD::SRA); 652 case Instruction::And: 653 return SelectBinaryOp(I, ISD::AND); 654 case Instruction::Or: 655 return SelectBinaryOp(I, ISD::OR); 656 case Instruction::Xor: 657 return SelectBinaryOp(I, ISD::XOR); 658 659 case Instruction::GetElementPtr: 660 return SelectGetElementPtr(I); 661 662 case Instruction::Br: { 663 BranchInst *BI = cast<BranchInst>(I); 664 665 if (BI->isUnconditional()) { 666 BasicBlock *LLVMSucc = BI->getSuccessor(0); 667 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 668 FastEmitBranch(MSucc); 669 return true; 670 } 671 672 // Conditional branches are not handed yet. 673 // Halt "fast" selection and bail. 674 return false; 675 } 676 677 case Instruction::Unreachable: 678 // Nothing to emit. 679 return true; 680 681 case Instruction::PHI: 682 // PHI nodes are already emitted. 683 return true; 684 685 case Instruction::Alloca: 686 // FunctionLowering has the static-sized case covered. 687 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 688 return true; 689 690 // Dynamic-sized alloca is not handled yet. 691 return false; 692 693 case Instruction::Call: 694 return SelectCall(I); 695 696 case Instruction::BitCast: 697 return SelectBitCast(I); 698 699 case Instruction::FPToSI: 700 return SelectCast(I, ISD::FP_TO_SINT); 701 case Instruction::ZExt: 702 return SelectCast(I, ISD::ZERO_EXTEND); 703 case Instruction::SExt: 704 return SelectCast(I, ISD::SIGN_EXTEND); 705 case Instruction::Trunc: 706 return SelectCast(I, ISD::TRUNCATE); 707 case Instruction::SIToFP: 708 return SelectCast(I, ISD::SINT_TO_FP); 709 710 case Instruction::IntToPtr: // Deliberate fall-through. 711 case Instruction::PtrToInt: { 712 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 713 MVT DstVT = TLI.getValueType(I->getType()); 714 if (DstVT.bitsGT(SrcVT)) 715 return SelectCast(I, ISD::ZERO_EXTEND); 716 if (DstVT.bitsLT(SrcVT)) 717 return SelectCast(I, ISD::TRUNCATE); 718 unsigned Reg = getRegForValue(I->getOperand(0)); 719 if (Reg == 0) return false; 720 UpdateValueMap(I, Reg); 721 return true; 722 } 723 724 default: 725 // Unhandled instruction. Halt "fast" selection and bail. 726 return false; 727 } 728} 729 730FastISel::FastISel(MachineFunction &mf, 731 MachineModuleInfo *mmi, 732 DwarfWriter *dw, 733 DenseMap<const Value *, unsigned> &vm, 734 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 735 DenseMap<const AllocaInst *, int> &am 736#ifndef NDEBUG 737 , SmallSet<Instruction*, 8> &cil 738#endif 739 ) 740 : MBB(0), 741 ValueMap(vm), 742 MBBMap(bm), 743 StaticAllocaMap(am), 744#ifndef NDEBUG 745 CatchInfoLost(cil), 746#endif 747 MF(mf), 748 MMI(mmi), 749 DW(dw), 750 MRI(MF.getRegInfo()), 751 MFI(*MF.getFrameInfo()), 752 MCP(*MF.getConstantPool()), 753 TM(MF.getTarget()), 754 TD(*TM.getTargetData()), 755 TII(*TM.getInstrInfo()), 756 TLI(*TM.getTargetLowering()) { 757} 758 759FastISel::~FastISel() {} 760 761unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, 762 ISD::NodeType) { 763 return 0; 764} 765 766unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType, 767 ISD::NodeType, unsigned /*Op0*/) { 768 return 0; 769} 770 771unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, 772 ISD::NodeType, unsigned /*Op0*/, 773 unsigned /*Op0*/) { 774 return 0; 775} 776 777unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType, 778 ISD::NodeType, uint64_t /*Imm*/) { 779 return 0; 780} 781 782unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType, 783 ISD::NodeType, ConstantFP * /*FPImm*/) { 784 return 0; 785} 786 787unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType, 788 ISD::NodeType, unsigned /*Op0*/, 789 uint64_t /*Imm*/) { 790 return 0; 791} 792 793unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType, 794 ISD::NodeType, unsigned /*Op0*/, 795 ConstantFP * /*FPImm*/) { 796 return 0; 797} 798 799unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, 800 ISD::NodeType, 801 unsigned /*Op0*/, unsigned /*Op1*/, 802 uint64_t /*Imm*/) { 803 return 0; 804} 805 806/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 807/// to emit an instruction with an immediate operand using FastEmit_ri. 808/// If that fails, it materializes the immediate into a register and try 809/// FastEmit_rr instead. 810unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 811 unsigned Op0, uint64_t Imm, 812 MVT::SimpleValueType ImmType) { 813 // First check if immediate type is legal. If not, we can't use the ri form. 814 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 815 if (ResultReg != 0) 816 return ResultReg; 817 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 818 if (MaterialReg == 0) 819 return 0; 820 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 821} 822 823/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 824/// to emit an instruction with a floating-point immediate operand using 825/// FastEmit_rf. If that fails, it materializes the immediate into a register 826/// and try FastEmit_rr instead. 827unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 828 unsigned Op0, ConstantFP *FPImm, 829 MVT::SimpleValueType ImmType) { 830 // First check if immediate type is legal. If not, we can't use the rf form. 831 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 832 if (ResultReg != 0) 833 return ResultReg; 834 835 // Materialize the constant in a register. 836 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 837 if (MaterialReg == 0) { 838 // If the target doesn't have a way to directly enter a floating-point 839 // value into a register, use an alternate approach. 840 // TODO: The current approach only supports floating-point constants 841 // that can be constructed by conversion from integer values. This should 842 // be replaced by code that creates a load from a constant-pool entry, 843 // which will require some target-specific work. 844 const APFloat &Flt = FPImm->getValueAPF(); 845 MVT IntVT = TLI.getPointerTy(); 846 847 uint64_t x[2]; 848 uint32_t IntBitWidth = IntVT.getSizeInBits(); 849 bool isExact; 850 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 851 APFloat::rmTowardZero, &isExact); 852 if (!isExact) 853 return 0; 854 APInt IntVal(IntBitWidth, 2, x); 855 856 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 857 ISD::Constant, IntVal.getZExtValue()); 858 if (IntegerReg == 0) 859 return 0; 860 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 861 ISD::SINT_TO_FP, IntegerReg); 862 if (MaterialReg == 0) 863 return 0; 864 } 865 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 866} 867 868unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 869 return MRI.createVirtualRegister(RC); 870} 871 872unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 873 const TargetRegisterClass* RC) { 874 unsigned ResultReg = createResultReg(RC); 875 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 876 877 BuildMI(MBB, DL, II, ResultReg); 878 return ResultReg; 879} 880 881unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 882 const TargetRegisterClass *RC, 883 unsigned Op0) { 884 unsigned ResultReg = createResultReg(RC); 885 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 886 887 if (II.getNumDefs() >= 1) 888 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 889 else { 890 BuildMI(MBB, DL, II).addReg(Op0); 891 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 892 II.ImplicitDefs[0], RC, RC); 893 if (!InsertedCopy) 894 ResultReg = 0; 895 } 896 897 return ResultReg; 898} 899 900unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 901 const TargetRegisterClass *RC, 902 unsigned Op0, unsigned Op1) { 903 unsigned ResultReg = createResultReg(RC); 904 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 905 906 if (II.getNumDefs() >= 1) 907 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 908 else { 909 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 910 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 911 II.ImplicitDefs[0], RC, RC); 912 if (!InsertedCopy) 913 ResultReg = 0; 914 } 915 return ResultReg; 916} 917 918unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 919 const TargetRegisterClass *RC, 920 unsigned Op0, uint64_t Imm) { 921 unsigned ResultReg = createResultReg(RC); 922 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 923 924 if (II.getNumDefs() >= 1) 925 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 926 else { 927 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 928 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 929 II.ImplicitDefs[0], RC, RC); 930 if (!InsertedCopy) 931 ResultReg = 0; 932 } 933 return ResultReg; 934} 935 936unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 937 const TargetRegisterClass *RC, 938 unsigned Op0, ConstantFP *FPImm) { 939 unsigned ResultReg = createResultReg(RC); 940 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 941 942 if (II.getNumDefs() >= 1) 943 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 944 else { 945 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 946 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 947 II.ImplicitDefs[0], RC, RC); 948 if (!InsertedCopy) 949 ResultReg = 0; 950 } 951 return ResultReg; 952} 953 954unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 955 const TargetRegisterClass *RC, 956 unsigned Op0, unsigned Op1, uint64_t Imm) { 957 unsigned ResultReg = createResultReg(RC); 958 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 959 960 if (II.getNumDefs() >= 1) 961 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 962 else { 963 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 964 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 965 II.ImplicitDefs[0], RC, RC); 966 if (!InsertedCopy) 967 ResultReg = 0; 968 } 969 return ResultReg; 970} 971 972unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 973 const TargetRegisterClass *RC, 974 uint64_t Imm) { 975 unsigned ResultReg = createResultReg(RC); 976 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 977 978 if (II.getNumDefs() >= 1) 979 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 980 else { 981 BuildMI(MBB, DL, II).addImm(Imm); 982 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 983 II.ImplicitDefs[0], RC, RC); 984 if (!InsertedCopy) 985 ResultReg = 0; 986 } 987 return ResultReg; 988} 989 990unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT, 991 unsigned Op0, uint32_t Idx) { 992 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 993 994 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 995 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); 996 997 if (II.getNumDefs() >= 1) 998 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 999 else { 1000 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 1001 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1002 II.ImplicitDefs[0], RC, RC); 1003 if (!InsertedCopy) 1004 ResultReg = 0; 1005 } 1006 return ResultReg; 1007} 1008 1009/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1010/// with all but the least significant bit set to zero. 1011unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) { 1012 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 1013} 1014