FastISel.cpp revision 895213e6bfa31d95d7dc01b388c859f8b61a2ec1 
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the implementation of the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Instructions.h"
15#include "llvm/CodeGen/FastISel.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/Target/TargetData.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/Target/TargetLowering.h"
21#include "llvm/Target/TargetMachine.h"
22using namespace llvm;
23
24/// SelectBinaryOp - Select and emit code for a binary operator instruction,
25/// which has an opcode which directly corresponds to the given ISD opcode.
26///
27bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
28                              DenseMap<const Value*, unsigned> &ValueMap) {
29  MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
30  if (VT == MVT::Other || !VT.isSimple())
31    // Unhandled type. Halt "fast" selection and bail.
32    return false;
33
34  unsigned Op0 = ValueMap[I->getOperand(0)];
35  if (Op0 == 0)
36    // Unhandled operand. Halt "fast" selection and bail.
37    return false;
38
39  // Check if the second operand is a constant and handle it appropriately.
40  if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
41    unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
42                                      CI->getZExtValue(), VT.getSimpleVT());
43    if (ResultReg == 0)
44      // Target-specific code wasn't able to find a machine opcode for
45      // the given ISD opcode and type. Halt "fast" selection and bail.
46      return false;
47
48    // We successfully emitted code for the given LLVM Instruction.
49    ValueMap[I] = ResultReg;
50    return true;
51  }
52
53  unsigned Op1 = ValueMap[I->getOperand(1)];
54  if (Op1 == 0)
55    // Unhandled operand. Halt "fast" selection and bail.
56    return false;
57
58  unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISDOpcode, Op0, Op1);
59  if (ResultReg == 0)
60    // Target-specific code wasn't able to find a machine opcode for
61    // the given ISD opcode and type. Halt "fast" selection and bail.
62    return false;
63
64  // We successfully emitted code for the given LLVM Instruction.
65  ValueMap[I] = ResultReg;
66  return true;
67}
68
69bool FastISel::SelectGetElementPtr(Instruction *I,
70                                   DenseMap<const Value*, unsigned> &ValueMap) {
71  unsigned N = ValueMap[I->getOperand(0)];
72  if (N == 0)
73    // Unhandled operand. Halt "fast" selection and bail.
74    return false;
75
76  const Type *Ty = I->getOperand(0)->getType();
77  MVT VT = MVT::getMVT(Ty, /*HandleUnknown=*/false);
78  for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
79       OI != E; ++OI) {
80    Value *Idx = *OI;
81    if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
82      unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
83      if (Field) {
84        // N = N + Offset
85        uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
86        // FIXME: This can be optimized by combining the add with a
87        // subsequent one.
88        N = FastEmit_ri_(VT.getSimpleVT(), ISD::ADD, N, Offs, VT.getSimpleVT());
89        if (N == 0)
90          // Unhandled operand. Halt "fast" selection and bail.
91          return false;
92      }
93      Ty = StTy->getElementType(Field);
94    } else {
95      Ty = cast<SequentialType>(Ty)->getElementType();
96
97      // If this is a constant subscript, handle it quickly.
98      if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
99        if (CI->getZExtValue() == 0) continue;
100        uint64_t Offs =
101          TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
102        N = FastEmit_ri_(VT.getSimpleVT(), ISD::ADD, N, Offs, VT.getSimpleVT());
103        if (N == 0)
104          // Unhandled operand. Halt "fast" selection and bail.
105          return false;
106        continue;
107      }
108
109      // N = N + Idx * ElementSize;
110      uint64_t ElementSize = TD.getABITypeSize(Ty);
111      unsigned IdxN = ValueMap[Idx];
112      if (IdxN == 0)
113        // Unhandled operand. Halt "fast" selection and bail.
114        return false;
115
116      // If the index is smaller or larger than intptr_t, truncate or extend
117      // it.
118      MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
119      if (IdxVT.bitsLT(VT))
120        IdxN = FastEmit_r(VT.getSimpleVT(), ISD::SIGN_EXTEND, IdxN);
121      else if (IdxVT.bitsGT(VT))
122        IdxN = FastEmit_r(VT.getSimpleVT(), ISD::TRUNCATE, IdxN);
123      if (IdxN == 0)
124        // Unhandled operand. Halt "fast" selection and bail.
125        return false;
126
127      // FIXME: If multiple is power of two, turn it into a shift. The
128      // optimization should be in FastEmit_ri?
129      IdxN = FastEmit_ri_(VT.getSimpleVT(), ISD::MUL, IdxN,
130                          ElementSize, VT.getSimpleVT());
131      if (IdxN == 0)
132        // Unhandled operand. Halt "fast" selection and bail.
133        return false;
134      N = FastEmit_rr(VT.getSimpleVT(), ISD::ADD, N, IdxN);
135      if (N == 0)
136        // Unhandled operand. Halt "fast" selection and bail.
137        return false;
138    }
139  }
140
141  // We successfully emitted code for the given LLVM Instruction.
142  ValueMap[I] = N;
143  return true;
144}
145
146BasicBlock::iterator
147FastISel::SelectInstructions(BasicBlock::iterator Begin,
148                             BasicBlock::iterator End,
149                             DenseMap<const Value*, unsigned> &ValueMap,
150                             MachineBasicBlock *mbb) {
151  MBB = mbb;
152  BasicBlock::iterator I = Begin;
153
154  for (; I != End; ++I) {
155    switch (I->getOpcode()) {
156    case Instruction::Add: {
157      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
158      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
159    }
160    case Instruction::Sub: {
161      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
162      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
163    }
164    case Instruction::Mul: {
165      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
166      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
167    }
168    case Instruction::SDiv:
169      if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
170    case Instruction::UDiv:
171      if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
172    case Instruction::FDiv:
173      if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
174    case Instruction::SRem:
175      if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
176    case Instruction::URem:
177      if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
178    case Instruction::FRem:
179      if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
180    case Instruction::Shl:
181      if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
182    case Instruction::LShr:
183      if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
184    case Instruction::AShr:
185      if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
186    case Instruction::And:
187      if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
188    case Instruction::Or:
189      if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
190    case Instruction::Xor:
191      if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
192
193    case Instruction::GetElementPtr:
194      if (!SelectGetElementPtr(I, ValueMap)) return I;
195      break;
196
197    case Instruction::Br: {
198      BranchInst *BI = cast<BranchInst>(I);
199
200      // For now, check for and handle just the most trivial case: an
201      // unconditional fall-through branch.
202      if (BI->isUnconditional()) {
203         MachineFunction::iterator NextMBB =
204           next(MachineFunction::iterator(MBB));
205         if (NextMBB != MF.end() &&
206             NextMBB->getBasicBlock() == BI->getSuccessor(0)) {
207          MBB->addSuccessor(NextMBB);
208          break;
209        }
210      }
211
212      // Something more complicated. Halt "fast" selection and bail.
213      return I;
214    }
215    default:
216      // Unhandled instruction. Halt "fast" selection and bail.
217      return I;
218    }
219  }
220
221  return I;
222}
223
224FastISel::FastISel(MachineFunction &mf)
225  : MF(mf), MRI(mf.getRegInfo()),
226    TD(*mf.getTarget().getTargetData()),
227    TII(*mf.getTarget().getInstrInfo()),
228    TLI(*mf.getTarget().getTargetLowering()) {
229}
230
231FastISel::~FastISel() {}
232
233unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
234  return 0;
235}
236
237unsigned FastISel::FastEmit_r(MVT::SimpleValueType, ISD::NodeType,
238                              unsigned /*Op0*/) {
239  return 0;
240}
241
242unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
243                               unsigned /*Op0*/, unsigned /*Op0*/) {
244  return 0;
245}
246
247unsigned FastISel::FastEmit_i(MVT::SimpleValueType, uint64_t /*Imm*/) {
248  return 0;
249}
250
251unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, ISD::NodeType,
252                               unsigned /*Op0*/, uint64_t /*Imm*/) {
253  return 0;
254}
255
256unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, ISD::NodeType,
257                                unsigned /*Op0*/, unsigned /*Op1*/,
258                                uint64_t /*Imm*/) {
259  return 0;
260}
261
262/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
263/// to emit an instruction with an immediate operand using FastEmit_ri.
264/// If that fails, it materializes the immediate into a register and try
265/// FastEmit_rr instead.
266unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
267                                unsigned Op0, uint64_t Imm,
268                                MVT::SimpleValueType ImmType) {
269  unsigned ResultReg = 0;
270  // First check if immediate type is legal. If not, we can't use the ri form.
271  if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
272    ResultReg = FastEmit_ri(VT, Opcode, Op0, Imm);
273  if (ResultReg != 0)
274    return ResultReg;
275  unsigned MaterialReg = FastEmit_i(ImmType, Imm);
276  if (MaterialReg == 0)
277    return 0;
278  return FastEmit_rr(VT, Opcode, Op0, MaterialReg);
279}
280
281unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
282  return MRI.createVirtualRegister(RC);
283}
284
285unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
286                                 const TargetRegisterClass* RC) {
287  unsigned ResultReg = createResultReg(RC);
288  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
289
290  BuildMI(MBB, II, ResultReg);
291  return ResultReg;
292}
293
294unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
295                                  const TargetRegisterClass *RC,
296                                  unsigned Op0) {
297  unsigned ResultReg = createResultReg(RC);
298  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
299
300  BuildMI(MBB, II, ResultReg).addReg(Op0);
301  return ResultReg;
302}
303
304unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
305                                   const TargetRegisterClass *RC,
306                                   unsigned Op0, unsigned Op1) {
307  unsigned ResultReg = createResultReg(RC);
308  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
309
310  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
311  return ResultReg;
312}
313
314unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
315                                   const TargetRegisterClass *RC,
316                                   unsigned Op0, uint64_t Imm) {
317  unsigned ResultReg = createResultReg(RC);
318  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
319
320  BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
321  return ResultReg;
322}
323
324unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
325                                    const TargetRegisterClass *RC,
326                                    unsigned Op0, unsigned Op1, uint64_t Imm) {
327  unsigned ResultReg = createResultReg(RC);
328  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
329
330  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
331  return ResultReg;
332}
333