FastISel.cpp revision 95a87fdc33d8f0dff5ffb35839c4369619db0577 
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the implementation of the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Instructions.h"
15#include "llvm/CodeGen/FastISel.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/Target/TargetData.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/Target/TargetLowering.h"
21#include "llvm/Target/TargetMachine.h"
22using namespace llvm;
23
24// Don't cache constant materializations.  To do so would require
25// tracking what uses they dominate.  Non-constants, however, already
26// have the SSA def-doms-use requirement enforced, so we can cache their
27// computations.
28unsigned FastISel::getRegForValue(Value *V,
29                                  DenseMap<const Value*, unsigned> &ValueMap) {
30  if (ValueMap.count(V))
31    return ValueMap[V];
32
33  MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
34  if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
35    if (CI->getValue().getActiveBits() > 64)
36      return 0;
37    // Don't cache constant materializations.  To do so would require
38    // tracking what uses they dominate.
39    return FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
40  } else if (isa<ConstantPointerNull>(V)) {
41    return FastEmit_i(VT, VT, ISD::Constant, 0);
42  } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
43    unsigned Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
44
45    if (!Reg) {
46      const APFloat &Flt = CF->getValueAPF();
47      MVT IntVT = TLI.getPointerTy();
48
49      uint64_t x[2];
50      uint32_t IntBitWidth = IntVT.getSizeInBits();
51      if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
52                               APFloat::rmTowardZero) != APFloat::opOK)
53        return 0;
54      APInt IntVal(IntBitWidth, 2, x);
55
56      unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
57                                       ISD::Constant, IntVal.getZExtValue());
58      if (IntegerReg == 0)
59        return 0;
60      Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
61      if (Reg == 0)
62        return 0;
63    }
64
65    return Reg;
66  } else if (isa<UndefValue>(V)) {
67    unsigned Reg = createResultReg(TLI.getRegClassFor(VT));
68    BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
69    return Reg;
70  }
71}
72
73/// UpdateValueMap - Update the value map to include the new mapping for this
74/// instruction, or insert an extra copy to get the result in a previous
75/// determined register.
76/// NOTE: This is only necessary because we might select a block that uses
77/// a value before we select the block that defines the value.  It might be
78/// possible to fix this by selecting blocks in reverse postorder.
79void FastISel::UpdateValueMap(Instruction* I, unsigned Reg,
80                              DenseMap<const Value*, unsigned> &ValueMap) {
81  if (!ValueMap.count(I))
82    ValueMap[I] = Reg;
83  else
84     TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
85                      Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
86}
87
88/// SelectBinaryOp - Select and emit code for a binary operator instruction,
89/// which has an opcode which directly corresponds to the given ISD opcode.
90///
91bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
92                              DenseMap<const Value*, unsigned> &ValueMap) {
93  MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
94  if (VT == MVT::Other || !VT.isSimple())
95    // Unhandled type. Halt "fast" selection and bail.
96    return false;
97  // We only handle legal types. For example, on x86-32 the instruction
98  // selector contains all of the 64-bit instructions from x86-64,
99  // under the assumption that i64 won't be used if the target doesn't
100  // support it.
101  if (!TLI.isTypeLegal(VT))
102    return false;
103
104  unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
105  if (Op0 == 0)
106    // Unhandled operand. Halt "fast" selection and bail.
107    return false;
108
109  // Check if the second operand is a constant and handle it appropriately.
110  if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
111    unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
112                                     ISDOpcode, Op0, CI->getZExtValue());
113    if (ResultReg != 0) {
114      // We successfully emitted code for the given LLVM Instruction.
115      UpdateValueMap(I, ResultReg, ValueMap);
116      return true;
117    }
118  }
119
120  // Check if the second operand is a constant float.
121  if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
122    unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
123                                     ISDOpcode, Op0, CF);
124    if (ResultReg != 0) {
125      // We successfully emitted code for the given LLVM Instruction.
126      UpdateValueMap(I, ResultReg, ValueMap);
127      return true;
128    }
129  }
130
131  unsigned Op1 = getRegForValue(I->getOperand(1), ValueMap);
132  if (Op1 == 0)
133    // Unhandled operand. Halt "fast" selection and bail.
134    return false;
135
136  // Now we have both operands in registers. Emit the instruction.
137  unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
138                                   ISDOpcode, Op0, Op1);
139  if (ResultReg == 0)
140    // Target-specific code wasn't able to find a machine opcode for
141    // the given ISD opcode and type. Halt "fast" selection and bail.
142    return false;
143
144  // We successfully emitted code for the given LLVM Instruction.
145  UpdateValueMap(I, ResultReg, ValueMap);
146  return true;
147}
148
149bool FastISel::SelectGetElementPtr(Instruction *I,
150                                   DenseMap<const Value*, unsigned> &ValueMap) {
151  unsigned N = getRegForValue(I->getOperand(0), ValueMap);
152  if (N == 0)
153    // Unhandled operand. Halt "fast" selection and bail.
154    return false;
155
156  const Type *Ty = I->getOperand(0)->getType();
157  MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
158  for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
159       OI != E; ++OI) {
160    Value *Idx = *OI;
161    if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
162      unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
163      if (Field) {
164        // N = N + Offset
165        uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
166        // FIXME: This can be optimized by combining the add with a
167        // subsequent one.
168        N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
169        if (N == 0)
170          // Unhandled operand. Halt "fast" selection and bail.
171          return false;
172      }
173      Ty = StTy->getElementType(Field);
174    } else {
175      Ty = cast<SequentialType>(Ty)->getElementType();
176
177      // If this is a constant subscript, handle it quickly.
178      if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
179        if (CI->getZExtValue() == 0) continue;
180        uint64_t Offs =
181          TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
182        N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
183        if (N == 0)
184          // Unhandled operand. Halt "fast" selection and bail.
185          return false;
186        continue;
187      }
188
189      // N = N + Idx * ElementSize;
190      uint64_t ElementSize = TD.getABITypeSize(Ty);
191      unsigned IdxN = getRegForValue(Idx, ValueMap);
192      if (IdxN == 0)
193        // Unhandled operand. Halt "fast" selection and bail.
194        return false;
195
196      // If the index is smaller or larger than intptr_t, truncate or extend
197      // it.
198      MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
199      if (IdxVT.bitsLT(VT))
200        IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
201      else if (IdxVT.bitsGT(VT))
202        IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
203      if (IdxN == 0)
204        // Unhandled operand. Halt "fast" selection and bail.
205        return false;
206
207      if (ElementSize != 1) {
208        IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
209        if (IdxN == 0)
210          // Unhandled operand. Halt "fast" selection and bail.
211          return false;
212      }
213      N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
214      if (N == 0)
215        // Unhandled operand. Halt "fast" selection and bail.
216        return false;
217    }
218  }
219
220  // We successfully emitted code for the given LLVM Instruction.
221  UpdateValueMap(I, N, ValueMap);
222  return true;
223}
224
225bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode,
226                          DenseMap<const Value*, unsigned> &ValueMap) {
227  MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
228  MVT DstVT = TLI.getValueType(I->getType());
229
230  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
231      DstVT == MVT::Other || !DstVT.isSimple() ||
232      !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
233    // Unhandled type. Halt "fast" selection and bail.
234    return false;
235
236  unsigned InputReg = getRegForValue(I->getOperand(0), ValueMap);
237  if (!InputReg)
238    // Unhandled operand.  Halt "fast" selection and bail.
239    return false;
240
241  unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
242                                  DstVT.getSimpleVT(),
243                                  Opcode,
244                                  InputReg);
245  if (!ResultReg)
246    return false;
247
248  UpdateValueMap(I, ResultReg, ValueMap);
249  return true;
250}
251
252bool FastISel::SelectBitCast(Instruction *I,
253                             DenseMap<const Value*, unsigned> &ValueMap) {
254  // If the bitcast doesn't change the type, just use the operand value.
255  if (I->getType() == I->getOperand(0)->getType()) {
256    unsigned Reg = getRegForValue(I->getOperand(0), ValueMap);
257    if (Reg == 0)
258      return false;
259    UpdateValueMap(I, Reg, ValueMap);
260    return true;
261  }
262
263  // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
264  MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
265  MVT DstVT = TLI.getValueType(I->getType());
266
267  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
268      DstVT == MVT::Other || !DstVT.isSimple() ||
269      !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
270    // Unhandled type. Halt "fast" selection and bail.
271    return false;
272
273  unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
274  if (Op0 == 0)
275    // Unhandled operand. Halt "fast" selection and bail.
276    return false;
277
278  // First, try to perform the bitcast by inserting a reg-reg copy.
279  unsigned ResultReg = 0;
280  if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
281    TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
282    TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
283    ResultReg = createResultReg(DstClass);
284
285    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
286                                         Op0, DstClass, SrcClass);
287    if (!InsertedCopy)
288      ResultReg = 0;
289  }
290
291  // If the reg-reg copy failed, select a BIT_CONVERT opcode.
292  if (!ResultReg)
293    ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
294                           ISD::BIT_CONVERT, Op0);
295
296  if (!ResultReg)
297    return false;
298
299  UpdateValueMap(I, ResultReg, ValueMap);
300  return true;
301}
302
303BasicBlock::iterator
304FastISel::SelectInstructions(BasicBlock::iterator Begin,
305                             BasicBlock::iterator End,
306                             DenseMap<const Value*, unsigned> &ValueMap,
307                             DenseMap<const BasicBlock*,
308                                      MachineBasicBlock *> &MBBMap,
309                             MachineBasicBlock *mbb) {
310  MBB = mbb;
311  BasicBlock::iterator I = Begin;
312
313  for (; I != End; ++I) {
314    switch (I->getOpcode()) {
315    case Instruction::Add: {
316      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
317      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
318    }
319    case Instruction::Sub: {
320      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
321      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
322    }
323    case Instruction::Mul: {
324      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
325      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
326    }
327    case Instruction::SDiv:
328      if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
329    case Instruction::UDiv:
330      if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
331    case Instruction::FDiv:
332      if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
333    case Instruction::SRem:
334      if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
335    case Instruction::URem:
336      if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
337    case Instruction::FRem:
338      if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
339    case Instruction::Shl:
340      if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
341    case Instruction::LShr:
342      if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
343    case Instruction::AShr:
344      if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
345    case Instruction::And:
346      if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
347    case Instruction::Or:
348      if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
349    case Instruction::Xor:
350      if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
351
352    case Instruction::GetElementPtr:
353      if (!SelectGetElementPtr(I, ValueMap)) return I;
354      break;
355
356    case Instruction::Br: {
357      BranchInst *BI = cast<BranchInst>(I);
358
359      if (BI->isUnconditional()) {
360        MachineFunction::iterator NextMBB =
361           next(MachineFunction::iterator(MBB));
362        BasicBlock *LLVMSucc = BI->getSuccessor(0);
363        MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
364
365        if (NextMBB != MF.end() && MSucc == NextMBB) {
366          // The unconditional fall-through case, which needs no instructions.
367        } else {
368          // The unconditional branch case.
369          TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
370        }
371        MBB->addSuccessor(MSucc);
372        break;
373      }
374
375      // Conditional branches are not handed yet.
376      // Halt "fast" selection and bail.
377      return I;
378    }
379
380    case Instruction::PHI:
381      // PHI nodes are already emitted.
382      break;
383
384    case Instruction::BitCast:
385      if (!SelectBitCast(I, ValueMap)) return I; break;
386
387    case Instruction::FPToSI:
388      if (!SelectCast(I, ISD::FP_TO_SINT, ValueMap)) return I;
389      break;
390    case Instruction::ZExt:
391      if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
392      break;
393    case Instruction::SExt:
394      if (!SelectCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
395      break;
396    case Instruction::Trunc:
397      if (!SelectCast(I, ISD::TRUNCATE, ValueMap)) return I;
398      break;
399    case Instruction::SIToFP:
400      if (!SelectCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
401      break;
402
403    case Instruction::IntToPtr: // Deliberate fall-through.
404    case Instruction::PtrToInt: {
405      MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
406      MVT DstVT = TLI.getValueType(I->getType());
407      if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
408        if (ValueMap[I->getOperand(0)]) {
409          UpdateValueMap(I, ValueMap[I->getOperand(0)], ValueMap);
410          break;
411        } else
412          // Unhandled operand
413          return I;
414      } else if (DstVT.bitsGT(SrcVT)) {
415        if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
416        break;
417      } else {
418        // TODO: Handle SrcVT > DstVT, where truncation is needed.
419        return I;
420      }
421    }
422
423    default:
424      // Unhandled instruction. Halt "fast" selection and bail.
425      return I;
426    }
427  }
428
429  return I;
430}
431
432FastISel::FastISel(MachineFunction &mf)
433  : MF(mf),
434    MRI(mf.getRegInfo()),
435    TM(mf.getTarget()),
436    TD(*TM.getTargetData()),
437    TII(*TM.getInstrInfo()),
438    TLI(*TM.getTargetLowering()) {
439}
440
441FastISel::~FastISel() {}
442
443unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
444                             ISD::NodeType) {
445  return 0;
446}
447
448unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
449                              ISD::NodeType, unsigned /*Op0*/) {
450  return 0;
451}
452
453unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
454                               ISD::NodeType, unsigned /*Op0*/,
455                               unsigned /*Op0*/) {
456  return 0;
457}
458
459unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
460                              ISD::NodeType, uint64_t /*Imm*/) {
461  return 0;
462}
463
464unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
465                              ISD::NodeType, ConstantFP * /*FPImm*/) {
466  return 0;
467}
468
469unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
470                               ISD::NodeType, unsigned /*Op0*/,
471                               uint64_t /*Imm*/) {
472  return 0;
473}
474
475unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
476                               ISD::NodeType, unsigned /*Op0*/,
477                               ConstantFP * /*FPImm*/) {
478  return 0;
479}
480
481unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
482                                ISD::NodeType,
483                                unsigned /*Op0*/, unsigned /*Op1*/,
484                                uint64_t /*Imm*/) {
485  return 0;
486}
487
488/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
489/// to emit an instruction with an immediate operand using FastEmit_ri.
490/// If that fails, it materializes the immediate into a register and try
491/// FastEmit_rr instead.
492unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
493                                unsigned Op0, uint64_t Imm,
494                                MVT::SimpleValueType ImmType) {
495  // First check if immediate type is legal. If not, we can't use the ri form.
496  unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
497  if (ResultReg != 0)
498    return ResultReg;
499  unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
500  if (MaterialReg == 0)
501    return 0;
502  return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
503}
504
505/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
506/// to emit an instruction with a floating-point immediate operand using
507/// FastEmit_rf. If that fails, it materializes the immediate into a register
508/// and try FastEmit_rr instead.
509unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
510                                unsigned Op0, ConstantFP *FPImm,
511                                MVT::SimpleValueType ImmType) {
512  // First check if immediate type is legal. If not, we can't use the rf form.
513  unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
514  if (ResultReg != 0)
515    return ResultReg;
516
517  // Materialize the constant in a register.
518  unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
519  if (MaterialReg == 0) {
520    // If the target doesn't have a way to directly enter a floating-point
521    // value into a register, use an alternate approach.
522    // TODO: The current approach only supports floating-point constants
523    // that can be constructed by conversion from integer values. This should
524    // be replaced by code that creates a load from a constant-pool entry,
525    // which will require some target-specific work.
526    const APFloat &Flt = FPImm->getValueAPF();
527    MVT IntVT = TLI.getPointerTy();
528
529    uint64_t x[2];
530    uint32_t IntBitWidth = IntVT.getSizeInBits();
531    if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
532                             APFloat::rmTowardZero) != APFloat::opOK)
533      return 0;
534    APInt IntVal(IntBitWidth, 2, x);
535
536    unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
537                                     ISD::Constant, IntVal.getZExtValue());
538    if (IntegerReg == 0)
539      return 0;
540    MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
541                             ISD::SINT_TO_FP, IntegerReg);
542    if (MaterialReg == 0)
543      return 0;
544  }
545  return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
546}
547
548unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
549  return MRI.createVirtualRegister(RC);
550}
551
552unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
553                                 const TargetRegisterClass* RC) {
554  unsigned ResultReg = createResultReg(RC);
555  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
556
557  BuildMI(MBB, II, ResultReg);
558  return ResultReg;
559}
560
561unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
562                                  const TargetRegisterClass *RC,
563                                  unsigned Op0) {
564  unsigned ResultReg = createResultReg(RC);
565  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
566
567  BuildMI(MBB, II, ResultReg).addReg(Op0);
568  return ResultReg;
569}
570
571unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
572                                   const TargetRegisterClass *RC,
573                                   unsigned Op0, unsigned Op1) {
574  unsigned ResultReg = createResultReg(RC);
575  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
576
577  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
578  return ResultReg;
579}
580
581unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
582                                   const TargetRegisterClass *RC,
583                                   unsigned Op0, uint64_t Imm) {
584  unsigned ResultReg = createResultReg(RC);
585  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
586
587  BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
588  return ResultReg;
589}
590
591unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
592                                   const TargetRegisterClass *RC,
593                                   unsigned Op0, ConstantFP *FPImm) {
594  unsigned ResultReg = createResultReg(RC);
595  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
596
597  BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
598  return ResultReg;
599}
600
601unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
602                                    const TargetRegisterClass *RC,
603                                    unsigned Op0, unsigned Op1, uint64_t Imm) {
604  unsigned ResultReg = createResultReg(RC);
605  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
606
607  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
608  return ResultReg;
609}
610
611unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
612                                  const TargetRegisterClass *RC,
613                                  uint64_t Imm) {
614  unsigned ResultReg = createResultReg(RC);
615  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
616
617  BuildMI(MBB, II, ResultReg).addImm(Imm);
618  return ResultReg;
619}
620
621unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
622  const TargetRegisterClass* RC = MRI.getRegClass(Op0);
623  const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
624
625  unsigned ResultReg = createResultReg(SRC);
626  const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
627
628  BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);
629  return ResultReg;
630}
631