FastISel.cpp revision 9ecc0c73c371ddf95184b9b75a66d92c17160ad7 
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the implementation of the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Instructions.h"
15#include "llvm/CodeGen/FastISel.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/Target/TargetData.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/Target/TargetLowering.h"
21#include "llvm/Target/TargetMachine.h"
22using namespace llvm;
23
24// Don't cache constant materializations.  To do so would require
25// tracking what uses they dominate.  Non-constants, however, already
26// have the SSA def-doms-use requirement enforced, so we can cache their
27// computations.
28unsigned FastISel::getRegForValue(Value *V,
29                                  DenseMap<const Value*, unsigned> &ValueMap) {
30  if (ValueMap.count(V))
31    return ValueMap[V];
32
33  MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
34  if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
35    if (CI->getValue().getActiveBits() > 64)
36      return 0;
37    // Don't cache constant materializations.  To do so would require
38    // tracking what uses they dominate.
39    return FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
40  } else if (isa<ConstantPointerNull>(V)) {
41    return FastEmit_i(VT, VT, ISD::Constant, 0);
42  } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
43    unsigned Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
44
45    if (!Reg) {
46      const APFloat &Flt = CF->getValueAPF();
47      MVT IntVT = TLI.getPointerTy();
48
49      uint64_t x[2];
50      uint32_t IntBitWidth = IntVT.getSizeInBits();
51      if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
52                               APFloat::rmTowardZero) != APFloat::opOK)
53        return 0;
54      APInt IntVal(IntBitWidth, 2, x);
55
56      unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
57                                       ISD::Constant, IntVal.getZExtValue());
58      if (IntegerReg == 0)
59        return 0;
60      Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
61      if (Reg == 0)
62        return 0;
63    }
64
65    return Reg;
66  } else if (isa<UndefValue>(V)) {
67    unsigned Reg = createResultReg(TLI.getRegClassFor(VT));
68    BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
69    return Reg;
70  }
71
72  return 0;
73}
74
75/// UpdateValueMap - Update the value map to include the new mapping for this
76/// instruction, or insert an extra copy to get the result in a previous
77/// determined register.
78/// NOTE: This is only necessary because we might select a block that uses
79/// a value before we select the block that defines the value.  It might be
80/// possible to fix this by selecting blocks in reverse postorder.
81void FastISel::UpdateValueMap(Instruction* I, unsigned Reg,
82                              DenseMap<const Value*, unsigned> &ValueMap) {
83  if (!ValueMap.count(I))
84    ValueMap[I] = Reg;
85  else
86     TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
87                      Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
88}
89
90/// SelectBinaryOp - Select and emit code for a binary operator instruction,
91/// which has an opcode which directly corresponds to the given ISD opcode.
92///
93bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
94                              DenseMap<const Value*, unsigned> &ValueMap) {
95  MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
96  if (VT == MVT::Other || !VT.isSimple())
97    // Unhandled type. Halt "fast" selection and bail.
98    return false;
99  // We only handle legal types. For example, on x86-32 the instruction
100  // selector contains all of the 64-bit instructions from x86-64,
101  // under the assumption that i64 won't be used if the target doesn't
102  // support it.
103  if (!TLI.isTypeLegal(VT))
104    return false;
105
106  unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
107  if (Op0 == 0)
108    // Unhandled operand. Halt "fast" selection and bail.
109    return false;
110
111  // Check if the second operand is a constant and handle it appropriately.
112  if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
113    unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
114                                     ISDOpcode, Op0, CI->getZExtValue());
115    if (ResultReg != 0) {
116      // We successfully emitted code for the given LLVM Instruction.
117      UpdateValueMap(I, ResultReg, ValueMap);
118      return true;
119    }
120  }
121
122  // Check if the second operand is a constant float.
123  if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
124    unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
125                                     ISDOpcode, Op0, CF);
126    if (ResultReg != 0) {
127      // We successfully emitted code for the given LLVM Instruction.
128      UpdateValueMap(I, ResultReg, ValueMap);
129      return true;
130    }
131  }
132
133  unsigned Op1 = getRegForValue(I->getOperand(1), ValueMap);
134  if (Op1 == 0)
135    // Unhandled operand. Halt "fast" selection and bail.
136    return false;
137
138  // Now we have both operands in registers. Emit the instruction.
139  unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
140                                   ISDOpcode, Op0, Op1);
141  if (ResultReg == 0)
142    // Target-specific code wasn't able to find a machine opcode for
143    // the given ISD opcode and type. Halt "fast" selection and bail.
144    return false;
145
146  // We successfully emitted code for the given LLVM Instruction.
147  UpdateValueMap(I, ResultReg, ValueMap);
148  return true;
149}
150
151bool FastISel::SelectGetElementPtr(Instruction *I,
152                                   DenseMap<const Value*, unsigned> &ValueMap) {
153  unsigned N = getRegForValue(I->getOperand(0), ValueMap);
154  if (N == 0)
155    // Unhandled operand. Halt "fast" selection and bail.
156    return false;
157
158  const Type *Ty = I->getOperand(0)->getType();
159  MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
160  for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
161       OI != E; ++OI) {
162    Value *Idx = *OI;
163    if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
164      unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
165      if (Field) {
166        // N = N + Offset
167        uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
168        // FIXME: This can be optimized by combining the add with a
169        // subsequent one.
170        N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
171        if (N == 0)
172          // Unhandled operand. Halt "fast" selection and bail.
173          return false;
174      }
175      Ty = StTy->getElementType(Field);
176    } else {
177      Ty = cast<SequentialType>(Ty)->getElementType();
178
179      // If this is a constant subscript, handle it quickly.
180      if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
181        if (CI->getZExtValue() == 0) continue;
182        uint64_t Offs =
183          TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
184        N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
185        if (N == 0)
186          // Unhandled operand. Halt "fast" selection and bail.
187          return false;
188        continue;
189      }
190
191      // N = N + Idx * ElementSize;
192      uint64_t ElementSize = TD.getABITypeSize(Ty);
193      unsigned IdxN = getRegForValue(Idx, ValueMap);
194      if (IdxN == 0)
195        // Unhandled operand. Halt "fast" selection and bail.
196        return false;
197
198      // If the index is smaller or larger than intptr_t, truncate or extend
199      // it.
200      MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
201      if (IdxVT.bitsLT(VT))
202        IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
203      else if (IdxVT.bitsGT(VT))
204        IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
205      if (IdxN == 0)
206        // Unhandled operand. Halt "fast" selection and bail.
207        return false;
208
209      if (ElementSize != 1) {
210        IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
211        if (IdxN == 0)
212          // Unhandled operand. Halt "fast" selection and bail.
213          return false;
214      }
215      N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
216      if (N == 0)
217        // Unhandled operand. Halt "fast" selection and bail.
218        return false;
219    }
220  }
221
222  // We successfully emitted code for the given LLVM Instruction.
223  UpdateValueMap(I, N, ValueMap);
224  return true;
225}
226
227bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode,
228                          DenseMap<const Value*, unsigned> &ValueMap) {
229  MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
230  MVT DstVT = TLI.getValueType(I->getType());
231
232  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
233      DstVT == MVT::Other || !DstVT.isSimple() ||
234      !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
235    // Unhandled type. Halt "fast" selection and bail.
236    return false;
237
238  unsigned InputReg = getRegForValue(I->getOperand(0), ValueMap);
239  if (!InputReg)
240    // Unhandled operand.  Halt "fast" selection and bail.
241    return false;
242
243  unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
244                                  DstVT.getSimpleVT(),
245                                  Opcode,
246                                  InputReg);
247  if (!ResultReg)
248    return false;
249
250  UpdateValueMap(I, ResultReg, ValueMap);
251  return true;
252}
253
254bool FastISel::SelectBitCast(Instruction *I,
255                             DenseMap<const Value*, unsigned> &ValueMap) {
256  // If the bitcast doesn't change the type, just use the operand value.
257  if (I->getType() == I->getOperand(0)->getType()) {
258    unsigned Reg = getRegForValue(I->getOperand(0), ValueMap);
259    if (Reg == 0)
260      return false;
261    UpdateValueMap(I, Reg, ValueMap);
262    return true;
263  }
264
265  // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
266  MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
267  MVT DstVT = TLI.getValueType(I->getType());
268
269  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
270      DstVT == MVT::Other || !DstVT.isSimple() ||
271      !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
272    // Unhandled type. Halt "fast" selection and bail.
273    return false;
274
275  unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
276  if (Op0 == 0)
277    // Unhandled operand. Halt "fast" selection and bail.
278    return false;
279
280  // First, try to perform the bitcast by inserting a reg-reg copy.
281  unsigned ResultReg = 0;
282  if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
283    TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
284    TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
285    ResultReg = createResultReg(DstClass);
286
287    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
288                                         Op0, DstClass, SrcClass);
289    if (!InsertedCopy)
290      ResultReg = 0;
291  }
292
293  // If the reg-reg copy failed, select a BIT_CONVERT opcode.
294  if (!ResultReg)
295    ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
296                           ISD::BIT_CONVERT, Op0);
297
298  if (!ResultReg)
299    return false;
300
301  UpdateValueMap(I, ResultReg, ValueMap);
302  return true;
303}
304
305BasicBlock::iterator
306FastISel::SelectInstructions(BasicBlock::iterator Begin,
307                             BasicBlock::iterator End,
308                             DenseMap<const Value*, unsigned> &ValueMap,
309                             DenseMap<const BasicBlock*,
310                                      MachineBasicBlock *> &MBBMap,
311                             MachineBasicBlock *mbb) {
312  MBB = mbb;
313  BasicBlock::iterator I = Begin;
314
315  for (; I != End; ++I) {
316    switch (I->getOpcode()) {
317    case Instruction::Add: {
318      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
319      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
320    }
321    case Instruction::Sub: {
322      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
323      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
324    }
325    case Instruction::Mul: {
326      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
327      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
328    }
329    case Instruction::SDiv:
330      if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
331    case Instruction::UDiv:
332      if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
333    case Instruction::FDiv:
334      if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
335    case Instruction::SRem:
336      if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
337    case Instruction::URem:
338      if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
339    case Instruction::FRem:
340      if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
341    case Instruction::Shl:
342      if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
343    case Instruction::LShr:
344      if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
345    case Instruction::AShr:
346      if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
347    case Instruction::And:
348      if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
349    case Instruction::Or:
350      if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
351    case Instruction::Xor:
352      if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
353
354    case Instruction::GetElementPtr:
355      if (!SelectGetElementPtr(I, ValueMap)) return I;
356      break;
357
358    case Instruction::Br: {
359      BranchInst *BI = cast<BranchInst>(I);
360
361      if (BI->isUnconditional()) {
362        MachineFunction::iterator NextMBB =
363           next(MachineFunction::iterator(MBB));
364        BasicBlock *LLVMSucc = BI->getSuccessor(0);
365        MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
366
367        if (NextMBB != MF.end() && MSucc == NextMBB) {
368          // The unconditional fall-through case, which needs no instructions.
369        } else {
370          // The unconditional branch case.
371          TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
372        }
373        MBB->addSuccessor(MSucc);
374        break;
375      }
376
377      // Conditional branches are not handed yet.
378      // Halt "fast" selection and bail.
379      return I;
380    }
381
382    case Instruction::PHI:
383      // PHI nodes are already emitted.
384      break;
385
386    case Instruction::BitCast:
387      if (!SelectBitCast(I, ValueMap)) return I; break;
388
389    case Instruction::FPToSI:
390      if (!SelectCast(I, ISD::FP_TO_SINT, ValueMap)) return I;
391      break;
392    case Instruction::ZExt:
393      if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
394      break;
395    case Instruction::SExt:
396      if (!SelectCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
397      break;
398    case Instruction::Trunc:
399      if (!SelectCast(I, ISD::TRUNCATE, ValueMap)) return I;
400      break;
401    case Instruction::SIToFP:
402      if (!SelectCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
403      break;
404
405    case Instruction::IntToPtr: // Deliberate fall-through.
406    case Instruction::PtrToInt: {
407      MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
408      MVT DstVT = TLI.getValueType(I->getType());
409      if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
410        if (ValueMap[I->getOperand(0)]) {
411          UpdateValueMap(I, ValueMap[I->getOperand(0)], ValueMap);
412          break;
413        } else
414          // Unhandled operand
415          return I;
416      } else if (DstVT.bitsGT(SrcVT)) {
417        if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
418        break;
419      } else {
420        // TODO: Handle SrcVT > DstVT, where truncation is needed.
421        return I;
422      }
423    }
424
425    default:
426      // Unhandled instruction. Halt "fast" selection and bail.
427      return I;
428    }
429  }
430
431  return I;
432}
433
434FastISel::FastISel(MachineFunction &mf)
435  : MF(mf),
436    MRI(mf.getRegInfo()),
437    TM(mf.getTarget()),
438    TD(*TM.getTargetData()),
439    TII(*TM.getInstrInfo()),
440    TLI(*TM.getTargetLowering()) {
441}
442
443FastISel::~FastISel() {}
444
445unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
446                             ISD::NodeType) {
447  return 0;
448}
449
450unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
451                              ISD::NodeType, unsigned /*Op0*/) {
452  return 0;
453}
454
455unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
456                               ISD::NodeType, unsigned /*Op0*/,
457                               unsigned /*Op0*/) {
458  return 0;
459}
460
461unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
462                              ISD::NodeType, uint64_t /*Imm*/) {
463  return 0;
464}
465
466unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
467                              ISD::NodeType, ConstantFP * /*FPImm*/) {
468  return 0;
469}
470
471unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
472                               ISD::NodeType, unsigned /*Op0*/,
473                               uint64_t /*Imm*/) {
474  return 0;
475}
476
477unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
478                               ISD::NodeType, unsigned /*Op0*/,
479                               ConstantFP * /*FPImm*/) {
480  return 0;
481}
482
483unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
484                                ISD::NodeType,
485                                unsigned /*Op0*/, unsigned /*Op1*/,
486                                uint64_t /*Imm*/) {
487  return 0;
488}
489
490/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
491/// to emit an instruction with an immediate operand using FastEmit_ri.
492/// If that fails, it materializes the immediate into a register and try
493/// FastEmit_rr instead.
494unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
495                                unsigned Op0, uint64_t Imm,
496                                MVT::SimpleValueType ImmType) {
497  // First check if immediate type is legal. If not, we can't use the ri form.
498  unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
499  if (ResultReg != 0)
500    return ResultReg;
501  unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
502  if (MaterialReg == 0)
503    return 0;
504  return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
505}
506
507/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
508/// to emit an instruction with a floating-point immediate operand using
509/// FastEmit_rf. If that fails, it materializes the immediate into a register
510/// and try FastEmit_rr instead.
511unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
512                                unsigned Op0, ConstantFP *FPImm,
513                                MVT::SimpleValueType ImmType) {
514  // First check if immediate type is legal. If not, we can't use the rf form.
515  unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
516  if (ResultReg != 0)
517    return ResultReg;
518
519  // Materialize the constant in a register.
520  unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
521  if (MaterialReg == 0) {
522    // If the target doesn't have a way to directly enter a floating-point
523    // value into a register, use an alternate approach.
524    // TODO: The current approach only supports floating-point constants
525    // that can be constructed by conversion from integer values. This should
526    // be replaced by code that creates a load from a constant-pool entry,
527    // which will require some target-specific work.
528    const APFloat &Flt = FPImm->getValueAPF();
529    MVT IntVT = TLI.getPointerTy();
530
531    uint64_t x[2];
532    uint32_t IntBitWidth = IntVT.getSizeInBits();
533    if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
534                             APFloat::rmTowardZero) != APFloat::opOK)
535      return 0;
536    APInt IntVal(IntBitWidth, 2, x);
537
538    unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
539                                     ISD::Constant, IntVal.getZExtValue());
540    if (IntegerReg == 0)
541      return 0;
542    MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
543                             ISD::SINT_TO_FP, IntegerReg);
544    if (MaterialReg == 0)
545      return 0;
546  }
547  return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
548}
549
550unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
551  return MRI.createVirtualRegister(RC);
552}
553
554unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
555                                 const TargetRegisterClass* RC) {
556  unsigned ResultReg = createResultReg(RC);
557  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
558
559  BuildMI(MBB, II, ResultReg);
560  return ResultReg;
561}
562
563unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
564                                  const TargetRegisterClass *RC,
565                                  unsigned Op0) {
566  unsigned ResultReg = createResultReg(RC);
567  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
568
569  BuildMI(MBB, II, ResultReg).addReg(Op0);
570  return ResultReg;
571}
572
573unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
574                                   const TargetRegisterClass *RC,
575                                   unsigned Op0, unsigned Op1) {
576  unsigned ResultReg = createResultReg(RC);
577  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
578
579  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
580  return ResultReg;
581}
582
583unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
584                                   const TargetRegisterClass *RC,
585                                   unsigned Op0, uint64_t Imm) {
586  unsigned ResultReg = createResultReg(RC);
587  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
588
589  BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
590  return ResultReg;
591}
592
593unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
594                                   const TargetRegisterClass *RC,
595                                   unsigned Op0, ConstantFP *FPImm) {
596  unsigned ResultReg = createResultReg(RC);
597  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
598
599  BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
600  return ResultReg;
601}
602
603unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
604                                    const TargetRegisterClass *RC,
605                                    unsigned Op0, unsigned Op1, uint64_t Imm) {
606  unsigned ResultReg = createResultReg(RC);
607  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
608
609  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
610  return ResultReg;
611}
612
613unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
614                                  const TargetRegisterClass *RC,
615                                  uint64_t Imm) {
616  unsigned ResultReg = createResultReg(RC);
617  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
618
619  BuildMI(MBB, II, ResultReg).addImm(Imm);
620  return ResultReg;
621}
622
623unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
624  const TargetRegisterClass* RC = MRI.getRegClass(Op0);
625  const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
626
627  unsigned ResultReg = createResultReg(SRC);
628  const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
629
630  BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);
631  return ResultReg;
632}
633