FastISel.cpp revision aa5656c6b9161608005cf8dc85027c160a925e58
1//===-- FastISel.cpp - Implementation of the FastISel class ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#define DEBUG_TYPE "isel" 43#include "llvm/Function.h" 44#include "llvm/GlobalVariable.h" 45#include "llvm/Instructions.h" 46#include "llvm/IntrinsicInst.h" 47#include "llvm/Operator.h" 48#include "llvm/CodeGen/Analysis.h" 49#include "llvm/CodeGen/FastISel.h" 50#include "llvm/CodeGen/FunctionLoweringInfo.h" 51#include "llvm/CodeGen/MachineInstrBuilder.h" 52#include "llvm/CodeGen/MachineModuleInfo.h" 53#include "llvm/CodeGen/MachineRegisterInfo.h" 54#include "llvm/Analysis/DebugInfo.h" 55#include "llvm/Analysis/Loads.h" 56#include "llvm/Target/TargetData.h" 57#include "llvm/Target/TargetInstrInfo.h" 58#include "llvm/Target/TargetLowering.h" 59#include "llvm/Target/TargetMachine.h" 60#include "llvm/Support/ErrorHandling.h" 61#include "llvm/Support/Debug.h" 62#include "llvm/ADT/Statistic.h" 63using namespace llvm; 64 65STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by " 66 "target-independent selector"); 67STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by " 68 "target-specific selector"); 69 70/// startNewBlock - Set the current block to which generated machine 71/// instructions will be appended, and clear the local CSE map. 72/// 73void FastISel::startNewBlock() { 74 LocalValueMap.clear(); 75 76 EmitStartPt = 0; 77 78 // Advance the emit start point past any EH_LABEL instructions. 79 MachineBasicBlock::iterator 80 I = FuncInfo.MBB->begin(), E = FuncInfo.MBB->end(); 81 while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) { 82 EmitStartPt = I; 83 ++I; 84 } 85 LastLocalValue = EmitStartPt; 86} 87 88void FastISel::flushLocalValueMap() { 89 LocalValueMap.clear(); 90 LastLocalValue = EmitStartPt; 91 recomputeInsertPt(); 92} 93 94bool FastISel::hasTrivialKill(const Value *V) const { 95 // Don't consider constants or arguments to have trivial kills. 96 const Instruction *I = dyn_cast<Instruction>(V); 97 if (!I) 98 return false; 99 100 // No-op casts are trivially coalesced by fast-isel. 101 if (const CastInst *Cast = dyn_cast<CastInst>(I)) 102 if (Cast->isNoopCast(TD.getIntPtrType(Cast->getContext())) && 103 !hasTrivialKill(Cast->getOperand(0))) 104 return false; 105 106 // GEPs with all zero indices are trivially coalesced by fast-isel. 107 if (const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(I)) 108 if (GEP->hasAllZeroIndices() && !hasTrivialKill(GEP->getOperand(0))) 109 return false; 110 111 // Only instructions with a single use in the same basic block are considered 112 // to have trivial kills. 113 return I->hasOneUse() && 114 !(I->getOpcode() == Instruction::BitCast || 115 I->getOpcode() == Instruction::PtrToInt || 116 I->getOpcode() == Instruction::IntToPtr) && 117 cast<Instruction>(*I->use_begin())->getParent() == I->getParent(); 118} 119 120unsigned FastISel::getRegForValue(const Value *V) { 121 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 122 // Don't handle non-simple values in FastISel. 123 if (!RealVT.isSimple()) 124 return 0; 125 126 // Ignore illegal types. We must do this before looking up the value 127 // in ValueMap because Arguments are given virtual registers regardless 128 // of whether FastISel can handle them. 129 MVT VT = RealVT.getSimpleVT(); 130 if (!TLI.isTypeLegal(VT)) { 131 // Handle integer promotions, though, because they're common and easy. 132 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) 133 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); 134 else 135 return 0; 136 } 137 138 // Look up the value to see if we already have a register for it. We 139 // cache values defined by Instructions across blocks, and other values 140 // only locally. This is because Instructions already have the SSA 141 // def-dominates-use requirement enforced. 142 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V); 143 if (I != FuncInfo.ValueMap.end()) 144 return I->second; 145 146 unsigned Reg = LocalValueMap[V]; 147 if (Reg != 0) 148 return Reg; 149 150 // In bottom-up mode, just create the virtual register which will be used 151 // to hold the value. It will be materialized later. 152 if (isa<Instruction>(V) && 153 (!isa<AllocaInst>(V) || 154 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V)))) 155 return FuncInfo.InitializeRegForValue(V); 156 157 SavePoint SaveInsertPt = enterLocalValueArea(); 158 159 // Materialize the value in a register. Emit any instructions in the 160 // local value area. 161 Reg = materializeRegForValue(V, VT); 162 163 leaveLocalValueArea(SaveInsertPt); 164 165 return Reg; 166} 167 168/// materializeRegForValue - Helper for getRegForValue. This function is 169/// called when the value isn't already available in a register and must 170/// be materialized with new instructions. 171unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) { 172 unsigned Reg = 0; 173 174 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 175 if (CI->getValue().getActiveBits() <= 64) 176 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 177 } else if (isa<AllocaInst>(V)) { 178 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 179 } else if (isa<ConstantPointerNull>(V)) { 180 // Translate this as an integer zero so that it can be 181 // local-CSE'd with actual integer zeros. 182 Reg = 183 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext()))); 184 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 185 if (CF->isNullValue()) { 186 Reg = TargetMaterializeFloatZero(CF); 187 } else { 188 // Try to emit the constant directly. 189 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 190 } 191 192 if (!Reg) { 193 // Try to emit the constant by using an integer constant with a cast. 194 const APFloat &Flt = CF->getValueAPF(); 195 EVT IntVT = TLI.getPointerTy(); 196 197 uint64_t x[2]; 198 uint32_t IntBitWidth = IntVT.getSizeInBits(); 199 bool isExact; 200 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 201 APFloat::rmTowardZero, &isExact); 202 if (isExact) { 203 APInt IntVal(IntBitWidth, x); 204 205 unsigned IntegerReg = 206 getRegForValue(ConstantInt::get(V->getContext(), IntVal)); 207 if (IntegerReg != 0) 208 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, 209 IntegerReg, /*Kill=*/false); 210 } 211 } 212 } else if (const Operator *Op = dyn_cast<Operator>(V)) { 213 if (!SelectOperator(Op, Op->getOpcode())) 214 if (!isa<Instruction>(Op) || 215 !TargetSelectInstruction(cast<Instruction>(Op))) 216 return 0; 217 Reg = lookUpRegForValue(Op); 218 } else if (isa<UndefValue>(V)) { 219 Reg = createResultReg(TLI.getRegClassFor(VT)); 220 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 221 TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 222 } 223 224 // If target-independent code couldn't handle the value, give target-specific 225 // code a try. 226 if (!Reg && isa<Constant>(V)) 227 Reg = TargetMaterializeConstant(cast<Constant>(V)); 228 229 // Don't cache constant materializations in the general ValueMap. 230 // To do so would require tracking what uses they dominate. 231 if (Reg != 0) { 232 LocalValueMap[V] = Reg; 233 LastLocalValue = MRI.getVRegDef(Reg); 234 } 235 return Reg; 236} 237 238unsigned FastISel::lookUpRegForValue(const Value *V) { 239 // Look up the value to see if we already have a register for it. We 240 // cache values defined by Instructions across blocks, and other values 241 // only locally. This is because Instructions already have the SSA 242 // def-dominates-use requirement enforced. 243 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V); 244 if (I != FuncInfo.ValueMap.end()) 245 return I->second; 246 return LocalValueMap[V]; 247} 248 249/// UpdateValueMap - Update the value map to include the new mapping for this 250/// instruction, or insert an extra copy to get the result in a previous 251/// determined register. 252/// NOTE: This is only necessary because we might select a block that uses 253/// a value before we select the block that defines the value. It might be 254/// possible to fix this by selecting blocks in reverse postorder. 255void FastISel::UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) { 256 if (!isa<Instruction>(I)) { 257 LocalValueMap[I] = Reg; 258 return; 259 } 260 261 unsigned &AssignedReg = FuncInfo.ValueMap[I]; 262 if (AssignedReg == 0) 263 // Use the new register. 264 AssignedReg = Reg; 265 else if (Reg != AssignedReg) { 266 // Arrange for uses of AssignedReg to be replaced by uses of Reg. 267 for (unsigned i = 0; i < NumRegs; i++) 268 FuncInfo.RegFixups[AssignedReg+i] = Reg+i; 269 270 AssignedReg = Reg; 271 } 272} 273 274std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) { 275 unsigned IdxN = getRegForValue(Idx); 276 if (IdxN == 0) 277 // Unhandled operand. Halt "fast" selection and bail. 278 return std::pair<unsigned, bool>(0, false); 279 280 bool IdxNIsKill = hasTrivialKill(Idx); 281 282 // If the index is smaller or larger than intptr_t, truncate or extend it. 283 MVT PtrVT = TLI.getPointerTy(); 284 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); 285 if (IdxVT.bitsLT(PtrVT)) { 286 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, 287 IdxN, IdxNIsKill); 288 IdxNIsKill = true; 289 } 290 else if (IdxVT.bitsGT(PtrVT)) { 291 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, 292 IdxN, IdxNIsKill); 293 IdxNIsKill = true; 294 } 295 return std::pair<unsigned, bool>(IdxN, IdxNIsKill); 296} 297 298void FastISel::recomputeInsertPt() { 299 if (getLastLocalValue()) { 300 FuncInfo.InsertPt = getLastLocalValue(); 301 FuncInfo.MBB = FuncInfo.InsertPt->getParent(); 302 ++FuncInfo.InsertPt; 303 } else 304 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI(); 305 306 // Now skip past any EH_LABELs, which must remain at the beginning. 307 while (FuncInfo.InsertPt != FuncInfo.MBB->end() && 308 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL) 309 ++FuncInfo.InsertPt; 310} 311 312FastISel::SavePoint FastISel::enterLocalValueArea() { 313 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt; 314 DebugLoc OldDL = DL; 315 recomputeInsertPt(); 316 DL = DebugLoc(); 317 SavePoint SP = { OldInsertPt, OldDL }; 318 return SP; 319} 320 321void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) { 322 if (FuncInfo.InsertPt != FuncInfo.MBB->begin()) 323 LastLocalValue = llvm::prior(FuncInfo.InsertPt); 324 325 // Restore the previous insert position. 326 FuncInfo.InsertPt = OldInsertPt.InsertPt; 327 DL = OldInsertPt.DL; 328} 329 330/// SelectBinaryOp - Select and emit code for a binary operator instruction, 331/// which has an opcode which directly corresponds to the given ISD opcode. 332/// 333bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) { 334 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); 335 if (VT == MVT::Other || !VT.isSimple()) 336 // Unhandled type. Halt "fast" selection and bail. 337 return false; 338 339 // We only handle legal types. For example, on x86-32 the instruction 340 // selector contains all of the 64-bit instructions from x86-64, 341 // under the assumption that i64 won't be used if the target doesn't 342 // support it. 343 if (!TLI.isTypeLegal(VT)) { 344 // MVT::i1 is special. Allow AND, OR, or XOR because they 345 // don't require additional zeroing, which makes them easy. 346 if (VT == MVT::i1 && 347 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 348 ISDOpcode == ISD::XOR)) 349 VT = TLI.getTypeToTransformTo(I->getContext(), VT); 350 else 351 return false; 352 } 353 354 // Check if the first operand is a constant, and handle it as "ri". At -O0, 355 // we don't have anything that canonicalizes operand order. 356 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(0))) 357 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) { 358 unsigned Op1 = getRegForValue(I->getOperand(1)); 359 if (Op1 == 0) return false; 360 361 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); 362 363 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, 364 Op1IsKill, CI->getZExtValue(), 365 VT.getSimpleVT()); 366 if (ResultReg == 0) return false; 367 368 // We successfully emitted code for the given LLVM Instruction. 369 UpdateValueMap(I, ResultReg); 370 return true; 371 } 372 373 374 unsigned Op0 = getRegForValue(I->getOperand(0)); 375 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail. 376 return false; 377 378 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 379 380 // Check if the second operand is a constant and handle it appropriately. 381 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 382 uint64_t Imm = CI->getZExtValue(); 383 384 // Transform "sdiv exact X, 8" -> "sra X, 3". 385 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) && 386 cast<BinaryOperator>(I)->isExact() && 387 isPowerOf2_64(Imm)) { 388 Imm = Log2_64(Imm); 389 ISDOpcode = ISD::SRA; 390 } 391 392 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, 393 Op0IsKill, Imm, VT.getSimpleVT()); 394 if (ResultReg == 0) return false; 395 396 // We successfully emitted code for the given LLVM Instruction. 397 UpdateValueMap(I, ResultReg); 398 return true; 399 } 400 401 // Check if the second operand is a constant float. 402 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 403 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 404 ISDOpcode, Op0, Op0IsKill, CF); 405 if (ResultReg != 0) { 406 // We successfully emitted code for the given LLVM Instruction. 407 UpdateValueMap(I, ResultReg); 408 return true; 409 } 410 } 411 412 unsigned Op1 = getRegForValue(I->getOperand(1)); 413 if (Op1 == 0) 414 // Unhandled operand. Halt "fast" selection and bail. 415 return false; 416 417 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); 418 419 // Now we have both operands in registers. Emit the instruction. 420 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 421 ISDOpcode, 422 Op0, Op0IsKill, 423 Op1, Op1IsKill); 424 if (ResultReg == 0) 425 // Target-specific code wasn't able to find a machine opcode for 426 // the given ISD opcode and type. Halt "fast" selection and bail. 427 return false; 428 429 // We successfully emitted code for the given LLVM Instruction. 430 UpdateValueMap(I, ResultReg); 431 return true; 432} 433 434bool FastISel::SelectGetElementPtr(const User *I) { 435 unsigned N = getRegForValue(I->getOperand(0)); 436 if (N == 0) 437 // Unhandled operand. Halt "fast" selection and bail. 438 return false; 439 440 bool NIsKill = hasTrivialKill(I->getOperand(0)); 441 442 // Keep a running tab of the total offset to coalesce multiple N = N + Offset 443 // into a single N = N + TotalOffset. 444 uint64_t TotalOffs = 0; 445 // FIXME: What's a good SWAG number for MaxOffs? 446 uint64_t MaxOffs = 2048; 447 Type *Ty = I->getOperand(0)->getType(); 448 MVT VT = TLI.getPointerTy(); 449 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1, 450 E = I->op_end(); OI != E; ++OI) { 451 const Value *Idx = *OI; 452 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 453 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 454 if (Field) { 455 // N = N + Offset 456 TotalOffs += TD.getStructLayout(StTy)->getElementOffset(Field); 457 if (TotalOffs >= MaxOffs) { 458 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT); 459 if (N == 0) 460 // Unhandled operand. Halt "fast" selection and bail. 461 return false; 462 NIsKill = true; 463 TotalOffs = 0; 464 } 465 } 466 Ty = StTy->getElementType(Field); 467 } else { 468 Ty = cast<SequentialType>(Ty)->getElementType(); 469 470 // If this is a constant subscript, handle it quickly. 471 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 472 if (CI->isZero()) continue; 473 // N = N + Offset 474 TotalOffs += 475 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 476 if (TotalOffs >= MaxOffs) { 477 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT); 478 if (N == 0) 479 // Unhandled operand. Halt "fast" selection and bail. 480 return false; 481 NIsKill = true; 482 TotalOffs = 0; 483 } 484 continue; 485 } 486 if (TotalOffs) { 487 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT); 488 if (N == 0) 489 // Unhandled operand. Halt "fast" selection and bail. 490 return false; 491 NIsKill = true; 492 TotalOffs = 0; 493 } 494 495 // N = N + Idx * ElementSize; 496 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 497 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx); 498 unsigned IdxN = Pair.first; 499 bool IdxNIsKill = Pair.second; 500 if (IdxN == 0) 501 // Unhandled operand. Halt "fast" selection and bail. 502 return false; 503 504 if (ElementSize != 1) { 505 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT); 506 if (IdxN == 0) 507 // Unhandled operand. Halt "fast" selection and bail. 508 return false; 509 IdxNIsKill = true; 510 } 511 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill); 512 if (N == 0) 513 // Unhandled operand. Halt "fast" selection and bail. 514 return false; 515 } 516 } 517 if (TotalOffs) { 518 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT); 519 if (N == 0) 520 // Unhandled operand. Halt "fast" selection and bail. 521 return false; 522 } 523 524 // We successfully emitted code for the given LLVM Instruction. 525 UpdateValueMap(I, N); 526 return true; 527} 528 529bool FastISel::SelectCall(const User *I) { 530 const CallInst *Call = cast<CallInst>(I); 531 532 // Handle simple inline asms. 533 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledValue())) { 534 // Don't attempt to handle constraints. 535 if (!IA->getConstraintString().empty()) 536 return false; 537 538 unsigned ExtraInfo = 0; 539 if (IA->hasSideEffects()) 540 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 541 if (IA->isAlignStack()) 542 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 543 544 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 545 TII.get(TargetOpcode::INLINEASM)) 546 .addExternalSymbol(IA->getAsmString().c_str()) 547 .addImm(ExtraInfo); 548 return true; 549 } 550 551 const Function *F = Call->getCalledFunction(); 552 if (!F) return false; 553 554 // Handle selected intrinsic function calls. 555 switch (F->getIntrinsicID()) { 556 default: break; 557 case Intrinsic::dbg_declare: { 558 const DbgDeclareInst *DI = cast<DbgDeclareInst>(Call); 559 if (!DIVariable(DI->getVariable()).Verify() || 560 !FuncInfo.MF->getMMI().hasDebugInfo()) 561 return true; 562 563 const Value *Address = DI->getAddress(); 564 if (!Address || isa<UndefValue>(Address) || isa<AllocaInst>(Address)) 565 return true; 566 567 unsigned Reg = 0; 568 unsigned Offset = 0; 569 if (const Argument *Arg = dyn_cast<Argument>(Address)) { 570 // Some arguments' frame index is recorded during argument lowering. 571 Offset = FuncInfo.getArgumentFrameIndex(Arg); 572 if (Offset) 573 Reg = TRI.getFrameRegister(*FuncInfo.MF); 574 } 575 if (!Reg) 576 Reg = getRegForValue(Address); 577 578 if (Reg) 579 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 580 TII.get(TargetOpcode::DBG_VALUE)) 581 .addReg(Reg, RegState::Debug).addImm(Offset) 582 .addMetadata(DI->getVariable()); 583 return true; 584 } 585 case Intrinsic::dbg_value: { 586 // This form of DBG_VALUE is target-independent. 587 const DbgValueInst *DI = cast<DbgValueInst>(Call); 588 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 589 const Value *V = DI->getValue(); 590 if (!V) { 591 // Currently the optimizer can produce this; insert an undef to 592 // help debugging. Probably the optimizer should not do this. 593 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 594 .addReg(0U).addImm(DI->getOffset()) 595 .addMetadata(DI->getVariable()); 596 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 597 if (CI->getBitWidth() > 64) 598 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 599 .addCImm(CI).addImm(DI->getOffset()) 600 .addMetadata(DI->getVariable()); 601 else 602 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 603 .addImm(CI->getZExtValue()).addImm(DI->getOffset()) 604 .addMetadata(DI->getVariable()); 605 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 606 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 607 .addFPImm(CF).addImm(DI->getOffset()) 608 .addMetadata(DI->getVariable()); 609 } else if (unsigned Reg = lookUpRegForValue(V)) { 610 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 611 .addReg(Reg, RegState::Debug).addImm(DI->getOffset()) 612 .addMetadata(DI->getVariable()); 613 } else { 614 // We can't yet handle anything else here because it would require 615 // generating code, thus altering codegen because of debug info. 616 DEBUG(dbgs() << "Dropping debug info for " << DI); 617 } 618 return true; 619 } 620 case Intrinsic::eh_exception: { 621 EVT VT = TLI.getValueType(Call->getType()); 622 if (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)!=TargetLowering::Expand) 623 break; 624 625 assert(FuncInfo.MBB->isLandingPad() && 626 "Call to eh.exception not in landing pad!"); 627 unsigned Reg = TLI.getExceptionAddressRegister(); 628 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 629 unsigned ResultReg = createResultReg(RC); 630 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 631 ResultReg).addReg(Reg); 632 UpdateValueMap(Call, ResultReg); 633 return true; 634 } 635 case Intrinsic::eh_selector: { 636 EVT VT = TLI.getValueType(Call->getType()); 637 if (TLI.getOperationAction(ISD::EHSELECTION, VT) != TargetLowering::Expand) 638 break; 639 if (FuncInfo.MBB->isLandingPad()) 640 AddCatchInfo(*Call, &FuncInfo.MF->getMMI(), FuncInfo.MBB); 641 else { 642#ifndef NDEBUG 643 FuncInfo.CatchInfoLost.insert(Call); 644#endif 645 // FIXME: Mark exception selector register as live in. Hack for PR1508. 646 unsigned Reg = TLI.getExceptionSelectorRegister(); 647 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 648 } 649 650 unsigned Reg = TLI.getExceptionSelectorRegister(); 651 EVT SrcVT = TLI.getPointerTy(); 652 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); 653 unsigned ResultReg = createResultReg(RC); 654 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 655 ResultReg).addReg(Reg); 656 657 bool ResultRegIsKill = hasTrivialKill(Call); 658 659 // Cast the register to the type of the selector. 660 if (SrcVT.bitsGT(MVT::i32)) 661 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE, 662 ResultReg, ResultRegIsKill); 663 else if (SrcVT.bitsLT(MVT::i32)) 664 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, 665 ISD::SIGN_EXTEND, ResultReg, ResultRegIsKill); 666 if (ResultReg == 0) 667 // Unhandled operand. Halt "fast" selection and bail. 668 return false; 669 670 UpdateValueMap(Call, ResultReg); 671 672 return true; 673 } 674 case Intrinsic::objectsize: { 675 ConstantInt *CI = cast<ConstantInt>(Call->getArgOperand(1)); 676 unsigned long long Res = CI->isZero() ? -1ULL : 0; 677 Constant *ResCI = ConstantInt::get(Call->getType(), Res); 678 unsigned ResultReg = getRegForValue(ResCI); 679 if (ResultReg == 0) 680 return false; 681 UpdateValueMap(Call, ResultReg); 682 return true; 683 } 684 } 685 686 // Usually, it does not make sense to initialize a value, 687 // make an unrelated function call and use the value, because 688 // it tends to be spilled on the stack. So, we move the pointer 689 // to the last local value to the beginning of the block, so that 690 // all the values which have already been materialized, 691 // appear after the call. It also makes sense to skip intrinsics 692 // since they tend to be inlined. 693 if (!isa<IntrinsicInst>(F)) 694 flushLocalValueMap(); 695 696 // An arbitrary call. Bail. 697 return false; 698} 699 700bool FastISel::SelectCast(const User *I, unsigned Opcode) { 701 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 702 EVT DstVT = TLI.getValueType(I->getType()); 703 704 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 705 DstVT == MVT::Other || !DstVT.isSimple()) 706 // Unhandled type. Halt "fast" selection and bail. 707 return false; 708 709 // Check if the destination type is legal. 710 if (!TLI.isTypeLegal(DstVT)) 711 return false; 712 713 // Check if the source operand is legal. 714 if (!TLI.isTypeLegal(SrcVT)) 715 return false; 716 717 unsigned InputReg = getRegForValue(I->getOperand(0)); 718 if (!InputReg) 719 // Unhandled operand. Halt "fast" selection and bail. 720 return false; 721 722 bool InputRegIsKill = hasTrivialKill(I->getOperand(0)); 723 724 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 725 DstVT.getSimpleVT(), 726 Opcode, 727 InputReg, InputRegIsKill); 728 if (!ResultReg) 729 return false; 730 731 UpdateValueMap(I, ResultReg); 732 return true; 733} 734 735bool FastISel::SelectBitCast(const User *I) { 736 // If the bitcast doesn't change the type, just use the operand value. 737 if (I->getType() == I->getOperand(0)->getType()) { 738 unsigned Reg = getRegForValue(I->getOperand(0)); 739 if (Reg == 0) 740 return false; 741 UpdateValueMap(I, Reg); 742 return true; 743 } 744 745 // Bitcasts of other values become reg-reg copies or BITCAST operators. 746 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 747 EVT DstVT = TLI.getValueType(I->getType()); 748 749 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 750 DstVT == MVT::Other || !DstVT.isSimple() || 751 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 752 // Unhandled type. Halt "fast" selection and bail. 753 return false; 754 755 unsigned Op0 = getRegForValue(I->getOperand(0)); 756 if (Op0 == 0) 757 // Unhandled operand. Halt "fast" selection and bail. 758 return false; 759 760 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 761 762 // First, try to perform the bitcast by inserting a reg-reg copy. 763 unsigned ResultReg = 0; 764 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 765 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 766 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 767 // Don't attempt a cross-class copy. It will likely fail. 768 if (SrcClass == DstClass) { 769 ResultReg = createResultReg(DstClass); 770 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 771 ResultReg).addReg(Op0); 772 } 773 } 774 775 // If the reg-reg copy failed, select a BITCAST opcode. 776 if (!ResultReg) 777 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 778 ISD::BITCAST, Op0, Op0IsKill); 779 780 if (!ResultReg) 781 return false; 782 783 UpdateValueMap(I, ResultReg); 784 return true; 785} 786 787bool 788FastISel::SelectInstruction(const Instruction *I) { 789 // Just before the terminator instruction, insert instructions to 790 // feed PHI nodes in successor blocks. 791 if (isa<TerminatorInst>(I)) 792 if (!HandlePHINodesInSuccessorBlocks(I->getParent())) 793 return false; 794 795 DL = I->getDebugLoc(); 796 797 // First, try doing target-independent selection. 798 if (SelectOperator(I, I->getOpcode())) { 799 ++NumFastIselSuccessIndependent; 800 DL = DebugLoc(); 801 return true; 802 } 803 804 // Next, try calling the target to attempt to handle the instruction. 805 if (TargetSelectInstruction(I)) { 806 ++NumFastIselSuccessTarget; 807 DL = DebugLoc(); 808 return true; 809 } 810 811 DL = DebugLoc(); 812 return false; 813} 814 815/// FastEmitBranch - Emit an unconditional branch to the given block, 816/// unless it is the immediate (fall-through) successor, and update 817/// the CFG. 818void 819FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) { 820 if (FuncInfo.MBB->isLayoutSuccessor(MSucc)) { 821 // The unconditional fall-through case, which needs no instructions. 822 } else { 823 // The unconditional branch case. 824 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL, 825 SmallVector<MachineOperand, 0>(), DL); 826 } 827 FuncInfo.MBB->addSuccessor(MSucc); 828} 829 830/// SelectFNeg - Emit an FNeg operation. 831/// 832bool 833FastISel::SelectFNeg(const User *I) { 834 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); 835 if (OpReg == 0) return false; 836 837 bool OpRegIsKill = hasTrivialKill(I); 838 839 // If the target has ISD::FNEG, use it. 840 EVT VT = TLI.getValueType(I->getType()); 841 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), 842 ISD::FNEG, OpReg, OpRegIsKill); 843 if (ResultReg != 0) { 844 UpdateValueMap(I, ResultReg); 845 return true; 846 } 847 848 // Bitcast the value to integer, twiddle the sign bit with xor, 849 // and then bitcast it back to floating-point. 850 if (VT.getSizeInBits() > 64) return false; 851 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); 852 if (!TLI.isTypeLegal(IntVT)) 853 return false; 854 855 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), 856 ISD::BITCAST, OpReg, OpRegIsKill); 857 if (IntReg == 0) 858 return false; 859 860 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, 861 IntReg, /*Kill=*/true, 862 UINT64_C(1) << (VT.getSizeInBits()-1), 863 IntVT.getSimpleVT()); 864 if (IntResultReg == 0) 865 return false; 866 867 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), 868 ISD::BITCAST, IntResultReg, /*Kill=*/true); 869 if (ResultReg == 0) 870 return false; 871 872 UpdateValueMap(I, ResultReg); 873 return true; 874} 875 876bool 877FastISel::SelectExtractValue(const User *U) { 878 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U); 879 if (!EVI) 880 return false; 881 882 // Make sure we only try to handle extracts with a legal result. But also 883 // allow i1 because it's easy. 884 EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true); 885 if (!RealVT.isSimple()) 886 return false; 887 MVT VT = RealVT.getSimpleVT(); 888 if (!TLI.isTypeLegal(VT) && VT != MVT::i1) 889 return false; 890 891 const Value *Op0 = EVI->getOperand(0); 892 Type *AggTy = Op0->getType(); 893 894 // Get the base result register. 895 unsigned ResultReg; 896 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0); 897 if (I != FuncInfo.ValueMap.end()) 898 ResultReg = I->second; 899 else if (isa<Instruction>(Op0)) 900 ResultReg = FuncInfo.InitializeRegForValue(Op0); 901 else 902 return false; // fast-isel can't handle aggregate constants at the moment 903 904 // Get the actual result register, which is an offset from the base register. 905 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices()); 906 907 SmallVector<EVT, 4> AggValueVTs; 908 ComputeValueVTs(TLI, AggTy, AggValueVTs); 909 910 for (unsigned i = 0; i < VTIndex; i++) 911 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]); 912 913 UpdateValueMap(EVI, ResultReg); 914 return true; 915} 916 917bool 918FastISel::SelectOperator(const User *I, unsigned Opcode) { 919 switch (Opcode) { 920 case Instruction::Add: 921 return SelectBinaryOp(I, ISD::ADD); 922 case Instruction::FAdd: 923 return SelectBinaryOp(I, ISD::FADD); 924 case Instruction::Sub: 925 return SelectBinaryOp(I, ISD::SUB); 926 case Instruction::FSub: 927 // FNeg is currently represented in LLVM IR as a special case of FSub. 928 if (BinaryOperator::isFNeg(I)) 929 return SelectFNeg(I); 930 return SelectBinaryOp(I, ISD::FSUB); 931 case Instruction::Mul: 932 return SelectBinaryOp(I, ISD::MUL); 933 case Instruction::FMul: 934 return SelectBinaryOp(I, ISD::FMUL); 935 case Instruction::SDiv: 936 return SelectBinaryOp(I, ISD::SDIV); 937 case Instruction::UDiv: 938 return SelectBinaryOp(I, ISD::UDIV); 939 case Instruction::FDiv: 940 return SelectBinaryOp(I, ISD::FDIV); 941 case Instruction::SRem: 942 return SelectBinaryOp(I, ISD::SREM); 943 case Instruction::URem: 944 return SelectBinaryOp(I, ISD::UREM); 945 case Instruction::FRem: 946 return SelectBinaryOp(I, ISD::FREM); 947 case Instruction::Shl: 948 return SelectBinaryOp(I, ISD::SHL); 949 case Instruction::LShr: 950 return SelectBinaryOp(I, ISD::SRL); 951 case Instruction::AShr: 952 return SelectBinaryOp(I, ISD::SRA); 953 case Instruction::And: 954 return SelectBinaryOp(I, ISD::AND); 955 case Instruction::Or: 956 return SelectBinaryOp(I, ISD::OR); 957 case Instruction::Xor: 958 return SelectBinaryOp(I, ISD::XOR); 959 960 case Instruction::GetElementPtr: 961 return SelectGetElementPtr(I); 962 963 case Instruction::Br: { 964 const BranchInst *BI = cast<BranchInst>(I); 965 966 if (BI->isUnconditional()) { 967 const BasicBlock *LLVMSucc = BI->getSuccessor(0); 968 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc]; 969 FastEmitBranch(MSucc, BI->getDebugLoc()); 970 return true; 971 } 972 973 // Conditional branches are not handed yet. 974 // Halt "fast" selection and bail. 975 return false; 976 } 977 978 case Instruction::Unreachable: 979 // Nothing to emit. 980 return true; 981 982 case Instruction::Alloca: 983 // FunctionLowering has the static-sized case covered. 984 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I))) 985 return true; 986 987 // Dynamic-sized alloca is not handled yet. 988 return false; 989 990 case Instruction::Call: 991 return SelectCall(I); 992 993 case Instruction::BitCast: 994 return SelectBitCast(I); 995 996 case Instruction::FPToSI: 997 return SelectCast(I, ISD::FP_TO_SINT); 998 case Instruction::ZExt: 999 return SelectCast(I, ISD::ZERO_EXTEND); 1000 case Instruction::SExt: 1001 return SelectCast(I, ISD::SIGN_EXTEND); 1002 case Instruction::Trunc: 1003 return SelectCast(I, ISD::TRUNCATE); 1004 case Instruction::SIToFP: 1005 return SelectCast(I, ISD::SINT_TO_FP); 1006 1007 case Instruction::IntToPtr: // Deliberate fall-through. 1008 case Instruction::PtrToInt: { 1009 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 1010 EVT DstVT = TLI.getValueType(I->getType()); 1011 if (DstVT.bitsGT(SrcVT)) 1012 return SelectCast(I, ISD::ZERO_EXTEND); 1013 if (DstVT.bitsLT(SrcVT)) 1014 return SelectCast(I, ISD::TRUNCATE); 1015 unsigned Reg = getRegForValue(I->getOperand(0)); 1016 if (Reg == 0) return false; 1017 UpdateValueMap(I, Reg); 1018 return true; 1019 } 1020 1021 case Instruction::ExtractValue: 1022 return SelectExtractValue(I); 1023 1024 case Instruction::PHI: 1025 llvm_unreachable("FastISel shouldn't visit PHI nodes!"); 1026 1027 default: 1028 // Unhandled instruction. Halt "fast" selection and bail. 1029 return false; 1030 } 1031} 1032 1033FastISel::FastISel(FunctionLoweringInfo &funcInfo) 1034 : FuncInfo(funcInfo), 1035 MRI(FuncInfo.MF->getRegInfo()), 1036 MFI(*FuncInfo.MF->getFrameInfo()), 1037 MCP(*FuncInfo.MF->getConstantPool()), 1038 TM(FuncInfo.MF->getTarget()), 1039 TD(*TM.getTargetData()), 1040 TII(*TM.getInstrInfo()), 1041 TLI(*TM.getTargetLowering()), 1042 TRI(*TM.getRegisterInfo()) { 1043} 1044 1045FastISel::~FastISel() {} 1046 1047unsigned FastISel::FastEmit_(MVT, MVT, 1048 unsigned) { 1049 return 0; 1050} 1051 1052unsigned FastISel::FastEmit_r(MVT, MVT, 1053 unsigned, 1054 unsigned /*Op0*/, bool /*Op0IsKill*/) { 1055 return 0; 1056} 1057 1058unsigned FastISel::FastEmit_rr(MVT, MVT, 1059 unsigned, 1060 unsigned /*Op0*/, bool /*Op0IsKill*/, 1061 unsigned /*Op1*/, bool /*Op1IsKill*/) { 1062 return 0; 1063} 1064 1065unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) { 1066 return 0; 1067} 1068 1069unsigned FastISel::FastEmit_f(MVT, MVT, 1070 unsigned, const ConstantFP * /*FPImm*/) { 1071 return 0; 1072} 1073 1074unsigned FastISel::FastEmit_ri(MVT, MVT, 1075 unsigned, 1076 unsigned /*Op0*/, bool /*Op0IsKill*/, 1077 uint64_t /*Imm*/) { 1078 return 0; 1079} 1080 1081unsigned FastISel::FastEmit_rf(MVT, MVT, 1082 unsigned, 1083 unsigned /*Op0*/, bool /*Op0IsKill*/, 1084 const ConstantFP * /*FPImm*/) { 1085 return 0; 1086} 1087 1088unsigned FastISel::FastEmit_rri(MVT, MVT, 1089 unsigned, 1090 unsigned /*Op0*/, bool /*Op0IsKill*/, 1091 unsigned /*Op1*/, bool /*Op1IsKill*/, 1092 uint64_t /*Imm*/) { 1093 return 0; 1094} 1095 1096/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 1097/// to emit an instruction with an immediate operand using FastEmit_ri. 1098/// If that fails, it materializes the immediate into a register and try 1099/// FastEmit_rr instead. 1100unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode, 1101 unsigned Op0, bool Op0IsKill, 1102 uint64_t Imm, MVT ImmType) { 1103 // If this is a multiply by a power of two, emit this as a shift left. 1104 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) { 1105 Opcode = ISD::SHL; 1106 Imm = Log2_64(Imm); 1107 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) { 1108 // div x, 8 -> srl x, 3 1109 Opcode = ISD::SRL; 1110 Imm = Log2_64(Imm); 1111 } 1112 1113 // Horrible hack (to be removed), check to make sure shift amounts are 1114 // in-range. 1115 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) && 1116 Imm >= VT.getSizeInBits()) 1117 return 0; 1118 1119 // First check if immediate type is legal. If not, we can't use the ri form. 1120 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); 1121 if (ResultReg != 0) 1122 return ResultReg; 1123 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 1124 if (MaterialReg == 0) { 1125 // This is a bit ugly/slow, but failing here means falling out of 1126 // fast-isel, which would be very slow. 1127 IntegerType *ITy = IntegerType::get(FuncInfo.Fn->getContext(), 1128 VT.getSizeInBits()); 1129 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm)); 1130 } 1131 return FastEmit_rr(VT, VT, Opcode, 1132 Op0, Op0IsKill, 1133 MaterialReg, /*Kill=*/true); 1134} 1135 1136unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 1137 return MRI.createVirtualRegister(RC); 1138} 1139 1140unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 1141 const TargetRegisterClass* RC) { 1142 unsigned ResultReg = createResultReg(RC); 1143 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1144 1145 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg); 1146 return ResultReg; 1147} 1148 1149unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 1150 const TargetRegisterClass *RC, 1151 unsigned Op0, bool Op0IsKill) { 1152 unsigned ResultReg = createResultReg(RC); 1153 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1154 1155 if (II.getNumDefs() >= 1) 1156 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1157 .addReg(Op0, Op0IsKill * RegState::Kill); 1158 else { 1159 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1160 .addReg(Op0, Op0IsKill * RegState::Kill); 1161 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1162 ResultReg).addReg(II.ImplicitDefs[0]); 1163 } 1164 1165 return ResultReg; 1166} 1167 1168unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 1169 const TargetRegisterClass *RC, 1170 unsigned Op0, bool Op0IsKill, 1171 unsigned Op1, bool Op1IsKill) { 1172 unsigned ResultReg = createResultReg(RC); 1173 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1174 1175 if (II.getNumDefs() >= 1) 1176 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1177 .addReg(Op0, Op0IsKill * RegState::Kill) 1178 .addReg(Op1, Op1IsKill * RegState::Kill); 1179 else { 1180 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1181 .addReg(Op0, Op0IsKill * RegState::Kill) 1182 .addReg(Op1, Op1IsKill * RegState::Kill); 1183 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1184 ResultReg).addReg(II.ImplicitDefs[0]); 1185 } 1186 return ResultReg; 1187} 1188 1189unsigned FastISel::FastEmitInst_rrr(unsigned MachineInstOpcode, 1190 const TargetRegisterClass *RC, 1191 unsigned Op0, bool Op0IsKill, 1192 unsigned Op1, bool Op1IsKill, 1193 unsigned Op2, bool Op2IsKill) { 1194 unsigned ResultReg = createResultReg(RC); 1195 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1196 1197 if (II.getNumDefs() >= 1) 1198 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1199 .addReg(Op0, Op0IsKill * RegState::Kill) 1200 .addReg(Op1, Op1IsKill * RegState::Kill) 1201 .addReg(Op2, Op2IsKill * RegState::Kill); 1202 else { 1203 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1204 .addReg(Op0, Op0IsKill * RegState::Kill) 1205 .addReg(Op1, Op1IsKill * RegState::Kill) 1206 .addReg(Op2, Op2IsKill * RegState::Kill); 1207 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1208 ResultReg).addReg(II.ImplicitDefs[0]); 1209 } 1210 return ResultReg; 1211} 1212 1213unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 1214 const TargetRegisterClass *RC, 1215 unsigned Op0, bool Op0IsKill, 1216 uint64_t Imm) { 1217 unsigned ResultReg = createResultReg(RC); 1218 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1219 1220 if (II.getNumDefs() >= 1) 1221 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1222 .addReg(Op0, Op0IsKill * RegState::Kill) 1223 .addImm(Imm); 1224 else { 1225 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1226 .addReg(Op0, Op0IsKill * RegState::Kill) 1227 .addImm(Imm); 1228 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1229 ResultReg).addReg(II.ImplicitDefs[0]); 1230 } 1231 return ResultReg; 1232} 1233 1234unsigned FastISel::FastEmitInst_rii(unsigned MachineInstOpcode, 1235 const TargetRegisterClass *RC, 1236 unsigned Op0, bool Op0IsKill, 1237 uint64_t Imm1, uint64_t Imm2) { 1238 unsigned ResultReg = createResultReg(RC); 1239 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1240 1241 if (II.getNumDefs() >= 1) 1242 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1243 .addReg(Op0, Op0IsKill * RegState::Kill) 1244 .addImm(Imm1) 1245 .addImm(Imm2); 1246 else { 1247 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1248 .addReg(Op0, Op0IsKill * RegState::Kill) 1249 .addImm(Imm1) 1250 .addImm(Imm2); 1251 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1252 ResultReg).addReg(II.ImplicitDefs[0]); 1253 } 1254 return ResultReg; 1255} 1256 1257unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 1258 const TargetRegisterClass *RC, 1259 unsigned Op0, bool Op0IsKill, 1260 const ConstantFP *FPImm) { 1261 unsigned ResultReg = createResultReg(RC); 1262 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1263 1264 if (II.getNumDefs() >= 1) 1265 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1266 .addReg(Op0, Op0IsKill * RegState::Kill) 1267 .addFPImm(FPImm); 1268 else { 1269 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1270 .addReg(Op0, Op0IsKill * RegState::Kill) 1271 .addFPImm(FPImm); 1272 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1273 ResultReg).addReg(II.ImplicitDefs[0]); 1274 } 1275 return ResultReg; 1276} 1277 1278unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 1279 const TargetRegisterClass *RC, 1280 unsigned Op0, bool Op0IsKill, 1281 unsigned Op1, bool Op1IsKill, 1282 uint64_t Imm) { 1283 unsigned ResultReg = createResultReg(RC); 1284 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1285 1286 if (II.getNumDefs() >= 1) 1287 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1288 .addReg(Op0, Op0IsKill * RegState::Kill) 1289 .addReg(Op1, Op1IsKill * RegState::Kill) 1290 .addImm(Imm); 1291 else { 1292 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1293 .addReg(Op0, Op0IsKill * RegState::Kill) 1294 .addReg(Op1, Op1IsKill * RegState::Kill) 1295 .addImm(Imm); 1296 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1297 ResultReg).addReg(II.ImplicitDefs[0]); 1298 } 1299 return ResultReg; 1300} 1301 1302unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 1303 const TargetRegisterClass *RC, 1304 uint64_t Imm) { 1305 unsigned ResultReg = createResultReg(RC); 1306 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1307 1308 if (II.getNumDefs() >= 1) 1309 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm); 1310 else { 1311 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm); 1312 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1313 ResultReg).addReg(II.ImplicitDefs[0]); 1314 } 1315 return ResultReg; 1316} 1317 1318unsigned FastISel::FastEmitInst_ii(unsigned MachineInstOpcode, 1319 const TargetRegisterClass *RC, 1320 uint64_t Imm1, uint64_t Imm2) { 1321 unsigned ResultReg = createResultReg(RC); 1322 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1323 1324 if (II.getNumDefs() >= 1) 1325 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1326 .addImm(Imm1).addImm(Imm2); 1327 else { 1328 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm1).addImm(Imm2); 1329 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1330 ResultReg).addReg(II.ImplicitDefs[0]); 1331 } 1332 return ResultReg; 1333} 1334 1335unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, 1336 unsigned Op0, bool Op0IsKill, 1337 uint32_t Idx) { 1338 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1339 assert(TargetRegisterInfo::isVirtualRegister(Op0) && 1340 "Cannot yet extract from physregs"); 1341 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 1342 DL, TII.get(TargetOpcode::COPY), ResultReg) 1343 .addReg(Op0, getKillRegState(Op0IsKill), Idx); 1344 return ResultReg; 1345} 1346 1347/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1348/// with all but the least significant bit set to zero. 1349unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) { 1350 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1); 1351} 1352 1353/// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks. 1354/// Emit code to ensure constants are copied into registers when needed. 1355/// Remember the virtual registers that need to be added to the Machine PHI 1356/// nodes as input. We cannot just directly add them, because expansion 1357/// might result in multiple MBB's for one BB. As such, the start of the 1358/// BB might correspond to a different MBB than the end. 1359bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 1360 const TerminatorInst *TI = LLVMBB->getTerminator(); 1361 1362 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 1363 unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size(); 1364 1365 // Check successor nodes' PHI nodes that expect a constant to be available 1366 // from this block. 1367 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 1368 const BasicBlock *SuccBB = TI->getSuccessor(succ); 1369 if (!isa<PHINode>(SuccBB->begin())) continue; 1370 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 1371 1372 // If this terminator has multiple identical successors (common for 1373 // switches), only handle each succ once. 1374 if (!SuccsHandled.insert(SuccMBB)) continue; 1375 1376 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 1377 1378 // At this point we know that there is a 1-1 correspondence between LLVM PHI 1379 // nodes and Machine PHI nodes, but the incoming operands have not been 1380 // emitted yet. 1381 for (BasicBlock::const_iterator I = SuccBB->begin(); 1382 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 1383 1384 // Ignore dead phi's. 1385 if (PN->use_empty()) continue; 1386 1387 // Only handle legal types. Two interesting things to note here. First, 1388 // by bailing out early, we may leave behind some dead instructions, 1389 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its 1390 // own moves. Second, this check is necessary because FastISel doesn't 1391 // use CreateRegs to create registers, so it always creates 1392 // exactly one register for each non-void instruction. 1393 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true); 1394 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) { 1395 // Promote MVT::i1. 1396 if (VT == MVT::i1) 1397 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT); 1398 else { 1399 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1400 return false; 1401 } 1402 } 1403 1404 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 1405 1406 // Set the DebugLoc for the copy. Prefer the location of the operand 1407 // if there is one; use the location of the PHI otherwise. 1408 DL = PN->getDebugLoc(); 1409 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp)) 1410 DL = Inst->getDebugLoc(); 1411 1412 unsigned Reg = getRegForValue(PHIOp); 1413 if (Reg == 0) { 1414 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1415 return false; 1416 } 1417 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg)); 1418 DL = DebugLoc(); 1419 } 1420 } 1421 1422 return true; 1423} 1424