FastISel.cpp revision ad368ac2b5f303050e9aaa357e2b806fae38f81b 
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the implementation of the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Instructions.h"
15#include "llvm/CodeGen/FastISel.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/Target/TargetData.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/Target/TargetLowering.h"
21#include "llvm/Target/TargetMachine.h"
22using namespace llvm;
23
24unsigned FastISel::getRegForValue(Value *V, DenseMap<const Value*, unsigned> &ValueMap) {
25  unsigned &Reg = ValueMap[V];
26  if (Reg != 0)
27    return Reg;
28
29  MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
30  if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
31    if (CI->getValue().getActiveBits() > 64)
32      return 0;
33    Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
34  } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
35    Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
36
37    if (!Reg) {
38      const APFloat &Flt = CF->getValueAPF();
39      MVT IntVT = TLI.getPointerTy();
40
41      uint64_t x[2];
42      uint32_t IntBitWidth = IntVT.getSizeInBits();
43      if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
44                               APFloat::rmTowardZero) != APFloat::opOK)
45        return 0;
46      APInt IntVal(IntBitWidth, 2, x);
47
48      unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
49                                       ISD::Constant, IntVal.getZExtValue());
50      if (IntegerReg == 0)
51        return 0;
52      Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
53      if (Reg == 0)
54        return 0;
55    }
56  }
57
58  return Reg;
59}
60
61/// SelectBinaryOp - Select and emit code for a binary operator instruction,
62/// which has an opcode which directly corresponds to the given ISD opcode.
63///
64bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
65                              DenseMap<const Value*, unsigned> &ValueMap) {
66  MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
67  if (VT == MVT::Other || !VT.isSimple())
68    // Unhandled type. Halt "fast" selection and bail.
69    return false;
70  // We only handle legal types. For example, on x86-32 the instruction
71  // selector contains all of the 64-bit instructions from x86-64,
72  // under the assumption that i64 won't be used if the target doesn't
73  // support it.
74  if (!TLI.isTypeLegal(VT))
75    return false;
76
77  unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
78  if (Op0 == 0)
79    // Unhandled operand. Halt "fast" selection and bail.
80    return false;
81
82  // Check if the second operand is a constant and handle it appropriately.
83  if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
84    unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
85                                     ISDOpcode, Op0, CI->getZExtValue());
86    if (ResultReg != 0) {
87      // We successfully emitted code for the given LLVM Instruction.
88      ValueMap[I] = ResultReg;
89      return true;
90    }
91  }
92
93  // Check if the second operand is a constant float.
94  if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
95    unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
96                                     ISDOpcode, Op0, CF);
97    if (ResultReg != 0) {
98      // We successfully emitted code for the given LLVM Instruction.
99      ValueMap[I] = ResultReg;
100      return true;
101    }
102  }
103
104  unsigned Op1 = getRegForValue(I->getOperand(1), ValueMap);
105  if (Op1 == 0)
106    // Unhandled operand. Halt "fast" selection and bail.
107    return false;
108
109  // Now we have both operands in registers. Emit the instruction.
110  unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
111                                   ISDOpcode, Op0, Op1);
112  if (ResultReg == 0)
113    // Target-specific code wasn't able to find a machine opcode for
114    // the given ISD opcode and type. Halt "fast" selection and bail.
115    return false;
116
117  // We successfully emitted code for the given LLVM Instruction.
118  ValueMap[I] = ResultReg;
119  return true;
120}
121
122bool FastISel::SelectGetElementPtr(Instruction *I,
123                                   DenseMap<const Value*, unsigned> &ValueMap) {
124  unsigned N = getRegForValue(I->getOperand(0), ValueMap);
125  if (N == 0)
126    // Unhandled operand. Halt "fast" selection and bail.
127    return false;
128
129  const Type *Ty = I->getOperand(0)->getType();
130  MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
131  for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
132       OI != E; ++OI) {
133    Value *Idx = *OI;
134    if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
135      unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
136      if (Field) {
137        // N = N + Offset
138        uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
139        // FIXME: This can be optimized by combining the add with a
140        // subsequent one.
141        N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
142        if (N == 0)
143          // Unhandled operand. Halt "fast" selection and bail.
144          return false;
145      }
146      Ty = StTy->getElementType(Field);
147    } else {
148      Ty = cast<SequentialType>(Ty)->getElementType();
149
150      // If this is a constant subscript, handle it quickly.
151      if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
152        if (CI->getZExtValue() == 0) continue;
153        uint64_t Offs =
154          TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
155        N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
156        if (N == 0)
157          // Unhandled operand. Halt "fast" selection and bail.
158          return false;
159        continue;
160      }
161
162      // N = N + Idx * ElementSize;
163      uint64_t ElementSize = TD.getABITypeSize(Ty);
164      unsigned IdxN = getRegForValue(Idx, ValueMap);
165      if (IdxN == 0)
166        // Unhandled operand. Halt "fast" selection and bail.
167        return false;
168
169      // If the index is smaller or larger than intptr_t, truncate or extend
170      // it.
171      MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
172      if (IdxVT.bitsLT(VT))
173        IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
174      else if (IdxVT.bitsGT(VT))
175        IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
176      if (IdxN == 0)
177        // Unhandled operand. Halt "fast" selection and bail.
178        return false;
179
180      if (ElementSize != 1) {
181        IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
182        if (IdxN == 0)
183          // Unhandled operand. Halt "fast" selection and bail.
184          return false;
185      }
186      N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
187      if (N == 0)
188        // Unhandled operand. Halt "fast" selection and bail.
189        return false;
190    }
191  }
192
193  // We successfully emitted code for the given LLVM Instruction.
194  ValueMap[I] = N;
195  return true;
196}
197
198bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode,
199                          DenseMap<const Value*, unsigned> &ValueMap) {
200  MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
201  MVT DstVT = MVT::getMVT(I->getType());
202
203  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
204      DstVT == MVT::Other || !DstVT.isSimple() ||
205      !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
206    // Unhandled type. Halt "fast" selection and bail.
207    return false;
208
209  unsigned InputReg = getRegForValue(I->getOperand(0), ValueMap);
210  if (!InputReg)
211    // Unhandled operand.  Halt "fast" selection and bail.
212    return false;
213
214  unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
215                                  DstVT.getSimpleVT(),
216                                  Opcode,
217                                  InputReg);
218  if (!ResultReg)
219    return false;
220
221  ValueMap[I] = ResultReg;
222  return true;
223}
224
225bool FastISel::SelectBitCast(Instruction *I,
226                             DenseMap<const Value*, unsigned> &ValueMap) {
227  // If the bitcast doesn't change the type, just use the operand value.
228  if (I->getType() == I->getOperand(0)->getType()) {
229    ValueMap[I] = getRegForValue(I->getOperand(0), ValueMap);
230    return true;
231  }
232
233  // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
234  MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
235  MVT DstVT = MVT::getMVT(I->getType());
236
237  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
238      DstVT == MVT::Other || !DstVT.isSimple() ||
239      !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
240    // Unhandled type. Halt "fast" selection and bail.
241    return false;
242
243  unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
244  if (Op0 == 0)
245    // Unhandled operand. Halt "fast" selection and bail.
246    return false;
247
248  // First, try to perform the bitcast by inserting a reg-reg copy.
249  unsigned ResultReg = 0;
250  if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
251    TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
252    TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
253    ResultReg = createResultReg(DstClass);
254
255    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
256                                         Op0, DstClass, SrcClass);
257    if (!InsertedCopy)
258      ResultReg = 0;
259  }
260
261  // If the reg-reg copy failed, select a BIT_CONVERT opcode.
262  if (!ResultReg)
263    ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
264                           ISD::BIT_CONVERT, Op0);
265
266  if (!ResultReg)
267    return false;
268
269  ValueMap[I] = ResultReg;
270  return true;
271}
272
273BasicBlock::iterator
274FastISel::SelectInstructions(BasicBlock::iterator Begin,
275                             BasicBlock::iterator End,
276                             DenseMap<const Value*, unsigned> &ValueMap,
277                             DenseMap<const BasicBlock*,
278                                      MachineBasicBlock *> &MBBMap,
279                             MachineBasicBlock *mbb) {
280  MBB = mbb;
281  BasicBlock::iterator I = Begin;
282
283  for (; I != End; ++I) {
284    switch (I->getOpcode()) {
285    case Instruction::Add: {
286      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
287      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
288    }
289    case Instruction::Sub: {
290      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
291      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
292    }
293    case Instruction::Mul: {
294      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
295      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
296    }
297    case Instruction::SDiv:
298      if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
299    case Instruction::UDiv:
300      if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
301    case Instruction::FDiv:
302      if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
303    case Instruction::SRem:
304      if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
305    case Instruction::URem:
306      if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
307    case Instruction::FRem:
308      if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
309    case Instruction::Shl:
310      if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
311    case Instruction::LShr:
312      if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
313    case Instruction::AShr:
314      if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
315    case Instruction::And:
316      if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
317    case Instruction::Or:
318      if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
319    case Instruction::Xor:
320      if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
321
322    case Instruction::GetElementPtr:
323      if (!SelectGetElementPtr(I, ValueMap)) return I;
324      break;
325
326    case Instruction::Br: {
327      BranchInst *BI = cast<BranchInst>(I);
328
329      if (BI->isUnconditional()) {
330        MachineFunction::iterator NextMBB =
331           next(MachineFunction::iterator(MBB));
332        BasicBlock *LLVMSucc = BI->getSuccessor(0);
333        MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
334
335        if (NextMBB != MF.end() && MSucc == NextMBB) {
336          // The unconditional fall-through case, which needs no instructions.
337        } else {
338          // The unconditional branch case.
339          TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
340        }
341        MBB->addSuccessor(MSucc);
342        break;
343      }
344
345      // Conditional branches are not handed yet.
346      // Halt "fast" selection and bail.
347      return I;
348    }
349
350    case Instruction::PHI:
351      // PHI nodes are already emitted.
352      break;
353
354    case Instruction::BitCast:
355      if (!SelectBitCast(I, ValueMap)) return I; break;
356
357    case Instruction::FPToSI:
358      if (!SelectCast(I, ISD::FP_TO_SINT, ValueMap)) return I;
359      break;
360    case Instruction::ZExt:
361      if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
362      break;
363    case Instruction::SExt:
364      if (!SelectCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
365      break;
366    case Instruction::SIToFP:
367      if (!SelectCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
368      break;
369
370    case Instruction::IntToPtr: // Deliberate fall-through.
371    case Instruction::PtrToInt: {
372      MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
373      MVT DstVT = TLI.getValueType(I->getType());
374      if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
375        if (ValueMap[I->getOperand(0)]) {
376          ValueMap[I] = ValueMap[I->getOperand(0)];
377          break;
378        } else
379          // Unhandled operand
380          return I;
381      } else if (DstVT.bitsGT(SrcVT)) {
382        if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
383        break;
384      } else {
385        // TODO: Handle SrcVT > DstVT, where truncation is needed.
386        return I;
387      }
388    }
389
390    default:
391      // Unhandled instruction. Halt "fast" selection and bail.
392      return I;
393    }
394  }
395
396  return I;
397}
398
399FastISel::FastISel(MachineFunction &mf)
400  : MF(mf),
401    MRI(mf.getRegInfo()),
402    TM(mf.getTarget()),
403    TD(*TM.getTargetData()),
404    TII(*TM.getInstrInfo()),
405    TLI(*TM.getTargetLowering()) {
406}
407
408FastISel::~FastISel() {}
409
410unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, ISD::NodeType) {
411  return 0;
412}
413
414unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
415                              ISD::NodeType, unsigned /*Op0*/) {
416  return 0;
417}
418
419unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
420                               ISD::NodeType, unsigned /*Op0*/,
421                               unsigned /*Op0*/) {
422  return 0;
423}
424
425unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
426                              ISD::NodeType, uint64_t /*Imm*/) {
427  return 0;
428}
429
430unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
431                              ISD::NodeType, ConstantFP * /*FPImm*/) {
432  return 0;
433}
434
435unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
436                               ISD::NodeType, unsigned /*Op0*/,
437                               uint64_t /*Imm*/) {
438  return 0;
439}
440
441unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
442                               ISD::NodeType, unsigned /*Op0*/,
443                               ConstantFP * /*FPImm*/) {
444  return 0;
445}
446
447unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
448                                ISD::NodeType,
449                                unsigned /*Op0*/, unsigned /*Op1*/,
450                                uint64_t /*Imm*/) {
451  return 0;
452}
453
454/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
455/// to emit an instruction with an immediate operand using FastEmit_ri.
456/// If that fails, it materializes the immediate into a register and try
457/// FastEmit_rr instead.
458unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
459                                unsigned Op0, uint64_t Imm,
460                                MVT::SimpleValueType ImmType) {
461  unsigned ResultReg = 0;
462  // First check if immediate type is legal. If not, we can't use the ri form.
463  if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
464    ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
465  if (ResultReg != 0)
466    return ResultReg;
467  unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
468  if (MaterialReg == 0)
469    return 0;
470  return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
471}
472
473/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
474/// to emit an instruction with a floating-point immediate operand using
475/// FastEmit_rf. If that fails, it materializes the immediate into a register
476/// and try FastEmit_rr instead.
477unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
478                                unsigned Op0, ConstantFP *FPImm,
479                                MVT::SimpleValueType ImmType) {
480  unsigned ResultReg = 0;
481  // First check if immediate type is legal. If not, we can't use the rf form.
482  if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
483    ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
484  if (ResultReg != 0)
485    return ResultReg;
486
487  // Materialize the constant in a register.
488  unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
489  if (MaterialReg == 0) {
490    // If the target doesn't have a way to directly enter a floating-point
491    // value into a register, use an alternate approach.
492    // TODO: The current approach only supports floating-point constants
493    // that can be constructed by conversion from integer values. This should
494    // be replaced by code that creates a load from a constant-pool entry,
495    // which will require some target-specific work.
496    const APFloat &Flt = FPImm->getValueAPF();
497    MVT IntVT = TLI.getPointerTy();
498
499    uint64_t x[2];
500    uint32_t IntBitWidth = IntVT.getSizeInBits();
501    if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
502                             APFloat::rmTowardZero) != APFloat::opOK)
503      return 0;
504    APInt IntVal(IntBitWidth, 2, x);
505
506    unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
507                                     ISD::Constant, IntVal.getZExtValue());
508    if (IntegerReg == 0)
509      return 0;
510    MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
511                             ISD::SINT_TO_FP, IntegerReg);
512    if (MaterialReg == 0)
513      return 0;
514  }
515  return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
516}
517
518unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
519  return MRI.createVirtualRegister(RC);
520}
521
522unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
523                                 const TargetRegisterClass* RC) {
524  unsigned ResultReg = createResultReg(RC);
525  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
526
527  BuildMI(MBB, II, ResultReg);
528  return ResultReg;
529}
530
531unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
532                                  const TargetRegisterClass *RC,
533                                  unsigned Op0) {
534  unsigned ResultReg = createResultReg(RC);
535  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
536
537  BuildMI(MBB, II, ResultReg).addReg(Op0);
538  return ResultReg;
539}
540
541unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
542                                   const TargetRegisterClass *RC,
543                                   unsigned Op0, unsigned Op1) {
544  unsigned ResultReg = createResultReg(RC);
545  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
546
547  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
548  return ResultReg;
549}
550
551unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
552                                   const TargetRegisterClass *RC,
553                                   unsigned Op0, uint64_t Imm) {
554  unsigned ResultReg = createResultReg(RC);
555  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
556
557  BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
558  return ResultReg;
559}
560
561unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
562                                   const TargetRegisterClass *RC,
563                                   unsigned Op0, ConstantFP *FPImm) {
564  unsigned ResultReg = createResultReg(RC);
565  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
566
567  BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
568  return ResultReg;
569}
570
571unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
572                                    const TargetRegisterClass *RC,
573                                    unsigned Op0, unsigned Op1, uint64_t Imm) {
574  unsigned ResultReg = createResultReg(RC);
575  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
576
577  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
578  return ResultReg;
579}
580
581unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
582                                  const TargetRegisterClass *RC,
583                                  uint64_t Imm) {
584  unsigned ResultReg = createResultReg(RC);
585  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
586
587  BuildMI(MBB, II, ResultReg).addImm(Imm);
588  return ResultReg;
589}
590