FastISel.cpp revision b2c1c2be5dbabbbcf75ef4868c57426a64b8db6a
1//===-- FastISel.cpp - Implementation of the FastISel class ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/FunctionLoweringInfo.h" 48#include "llvm/CodeGen/MachineInstrBuilder.h" 49#include "llvm/CodeGen/MachineModuleInfo.h" 50#include "llvm/CodeGen/MachineRegisterInfo.h" 51#include "llvm/Analysis/DebugInfo.h" 52#include "llvm/Analysis/Loads.h" 53#include "llvm/Target/TargetData.h" 54#include "llvm/Target/TargetInstrInfo.h" 55#include "llvm/Target/TargetLowering.h" 56#include "llvm/Target/TargetMachine.h" 57#include "llvm/Support/ErrorHandling.h" 58using namespace llvm; 59 60/// startNewBlock - Set the current block to which generated machine 61/// instructions will be appended, and clear the local CSE map. 62/// 63void FastISel::startNewBlock() { 64 LocalValueMap.clear(); 65 66 // Start out as null, meaining no local-value instructions have 67 // been emitted. 68 LastLocalValue = 0; 69 70 // Advance the last local value past any EH_LABEL instructions. 71 MachineBasicBlock::iterator 72 I = FuncInfo.MBB->begin(), E = FuncInfo.MBB->end(); 73 while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) { 74 LastLocalValue = I; 75 ++I; 76 } 77} 78 79bool FastISel::hasTrivialKill(const Value *V) const { 80 // Don't consider constants or arguments to have trivial kills. 81 const Instruction *I = dyn_cast<Instruction>(V); 82 if (!I) 83 return false; 84 85 // No-op casts are trivially coalesced by fast-isel. 86 if (const CastInst *Cast = dyn_cast<CastInst>(I)) 87 if (Cast->isNoopCast(TD.getIntPtrType(Cast->getContext())) && 88 !hasTrivialKill(Cast->getOperand(0))) 89 return false; 90 91 // Only instructions with a single use in the same basic block are considered 92 // to have trivial kills. 93 return I->hasOneUse() && 94 !(I->getOpcode() == Instruction::BitCast || 95 I->getOpcode() == Instruction::PtrToInt || 96 I->getOpcode() == Instruction::IntToPtr) && 97 cast<Instruction>(I->use_begin())->getParent() == I->getParent(); 98} 99 100unsigned FastISel::getRegForValue(const Value *V) { 101 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 102 // Don't handle non-simple values in FastISel. 103 if (!RealVT.isSimple()) 104 return 0; 105 106 // Ignore illegal types. We must do this before looking up the value 107 // in ValueMap because Arguments are given virtual registers regardless 108 // of whether FastISel can handle them. 109 MVT VT = RealVT.getSimpleVT(); 110 if (!TLI.isTypeLegal(VT)) { 111 // Promote MVT::i1 to a legal type though, because it's common and easy. 112 if (VT == MVT::i1) 113 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); 114 else 115 return 0; 116 } 117 118 // Look up the value to see if we already have a register for it. We 119 // cache values defined by Instructions across blocks, and other values 120 // only locally. This is because Instructions already have the SSA 121 // def-dominates-use requirement enforced. 122 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V); 123 if (I != FuncInfo.ValueMap.end()) { 124 unsigned Reg = I->second; 125 return Reg; 126 } 127 unsigned Reg = LocalValueMap[V]; 128 if (Reg != 0) 129 return Reg; 130 131 // In bottom-up mode, just create the virtual register which will be used 132 // to hold the value. It will be materialized later. 133 if (isa<Instruction>(V) && 134 (!isa<AllocaInst>(V) || 135 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V)))) 136 return FuncInfo.InitializeRegForValue(V); 137 138 SavePoint SaveInsertPt = enterLocalValueArea(); 139 140 // Materialize the value in a register. Emit any instructions in the 141 // local value area. 142 Reg = materializeRegForValue(V, VT); 143 144 leaveLocalValueArea(SaveInsertPt); 145 146 return Reg; 147} 148 149/// materializeRegForValue - Helper for getRegForVale. This function is 150/// called when the value isn't already available in a register and must 151/// be materialized with new instructions. 152unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) { 153 unsigned Reg = 0; 154 155 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 156 if (CI->getValue().getActiveBits() <= 64) 157 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 158 } else if (isa<AllocaInst>(V)) { 159 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 160 } else if (isa<ConstantPointerNull>(V)) { 161 // Translate this as an integer zero so that it can be 162 // local-CSE'd with actual integer zeros. 163 Reg = 164 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext()))); 165 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 166 // Try to emit the constant directly. 167 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 168 169 if (!Reg) { 170 // Try to emit the constant by using an integer constant with a cast. 171 const APFloat &Flt = CF->getValueAPF(); 172 EVT IntVT = TLI.getPointerTy(); 173 174 uint64_t x[2]; 175 uint32_t IntBitWidth = IntVT.getSizeInBits(); 176 bool isExact; 177 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 178 APFloat::rmTowardZero, &isExact); 179 if (isExact) { 180 APInt IntVal(IntBitWidth, 2, x); 181 182 unsigned IntegerReg = 183 getRegForValue(ConstantInt::get(V->getContext(), IntVal)); 184 if (IntegerReg != 0) 185 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, 186 IntegerReg, /*Kill=*/false); 187 } 188 } 189 } else if (const Operator *Op = dyn_cast<Operator>(V)) { 190 if (!SelectOperator(Op, Op->getOpcode())) 191 if (!isa<Instruction>(Op) || 192 !TargetSelectInstruction(cast<Instruction>(Op))) 193 return 0; 194 Reg = lookUpRegForValue(Op); 195 } else if (isa<UndefValue>(V)) { 196 Reg = createResultReg(TLI.getRegClassFor(VT)); 197 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 198 TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 199 } 200 201 // If target-independent code couldn't handle the value, give target-specific 202 // code a try. 203 if (!Reg && isa<Constant>(V)) 204 Reg = TargetMaterializeConstant(cast<Constant>(V)); 205 206 // Don't cache constant materializations in the general ValueMap. 207 // To do so would require tracking what uses they dominate. 208 if (Reg != 0) { 209 LocalValueMap[V] = Reg; 210 LastLocalValue = MRI.getVRegDef(Reg); 211 } 212 return Reg; 213} 214 215unsigned FastISel::lookUpRegForValue(const Value *V) { 216 // Look up the value to see if we already have a register for it. We 217 // cache values defined by Instructions across blocks, and other values 218 // only locally. This is because Instructions already have the SSA 219 // def-dominates-use requirement enforced. 220 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V); 221 if (I != FuncInfo.ValueMap.end()) 222 return I->second; 223 return LocalValueMap[V]; 224} 225 226/// UpdateValueMap - Update the value map to include the new mapping for this 227/// instruction, or insert an extra copy to get the result in a previous 228/// determined register. 229/// NOTE: This is only necessary because we might select a block that uses 230/// a value before we select the block that defines the value. It might be 231/// possible to fix this by selecting blocks in reverse postorder. 232unsigned FastISel::UpdateValueMap(const Value *I, unsigned Reg) { 233 if (!isa<Instruction>(I)) { 234 LocalValueMap[I] = Reg; 235 return Reg; 236 } 237 238 unsigned &AssignedReg = FuncInfo.ValueMap[I]; 239 if (AssignedReg == 0) 240 // Use the new register. 241 AssignedReg = Reg; 242 else if (Reg != AssignedReg) { 243 // Arrange for uses of AssignedReg to be replaced by uses of Reg. 244 FuncInfo.RegFixups[AssignedReg] = Reg; 245 246 AssignedReg = Reg; 247 } 248 249 return AssignedReg; 250} 251 252std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) { 253 unsigned IdxN = getRegForValue(Idx); 254 if (IdxN == 0) 255 // Unhandled operand. Halt "fast" selection and bail. 256 return std::pair<unsigned, bool>(0, false); 257 258 bool IdxNIsKill = hasTrivialKill(Idx); 259 260 // If the index is smaller or larger than intptr_t, truncate or extend it. 261 MVT PtrVT = TLI.getPointerTy(); 262 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); 263 if (IdxVT.bitsLT(PtrVT)) { 264 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, 265 IdxN, IdxNIsKill); 266 IdxNIsKill = true; 267 } 268 else if (IdxVT.bitsGT(PtrVT)) { 269 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, 270 IdxN, IdxNIsKill); 271 IdxNIsKill = true; 272 } 273 return std::pair<unsigned, bool>(IdxN, IdxNIsKill); 274} 275 276void FastISel::recomputeInsertPt() { 277 if (getLastLocalValue()) { 278 FuncInfo.InsertPt = getLastLocalValue(); 279 ++FuncInfo.InsertPt; 280 } else 281 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI(); 282 283 // Now skip past any EH_LABELs, which must remain at the beginning. 284 while (FuncInfo.InsertPt != FuncInfo.MBB->end() && 285 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL) 286 ++FuncInfo.InsertPt; 287} 288 289FastISel::SavePoint FastISel::enterLocalValueArea() { 290 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt; 291 DebugLoc OldDL = DL; 292 recomputeInsertPt(); 293 DL = DebugLoc(); 294 SavePoint SP = { OldInsertPt, OldDL }; 295 return SP; 296} 297 298void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) { 299 if (FuncInfo.InsertPt != FuncInfo.MBB->begin()) 300 LastLocalValue = llvm::prior(FuncInfo.InsertPt); 301 302 // Restore the previous insert position. 303 FuncInfo.InsertPt = OldInsertPt.InsertPt; 304 DL = OldInsertPt.DL; 305} 306 307/// SelectBinaryOp - Select and emit code for a binary operator instruction, 308/// which has an opcode which directly corresponds to the given ISD opcode. 309/// 310bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) { 311 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); 312 if (VT == MVT::Other || !VT.isSimple()) 313 // Unhandled type. Halt "fast" selection and bail. 314 return false; 315 316 // We only handle legal types. For example, on x86-32 the instruction 317 // selector contains all of the 64-bit instructions from x86-64, 318 // under the assumption that i64 won't be used if the target doesn't 319 // support it. 320 if (!TLI.isTypeLegal(VT)) { 321 // MVT::i1 is special. Allow AND, OR, or XOR because they 322 // don't require additional zeroing, which makes them easy. 323 if (VT == MVT::i1 && 324 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 325 ISDOpcode == ISD::XOR)) 326 VT = TLI.getTypeToTransformTo(I->getContext(), VT); 327 else 328 return false; 329 } 330 331 unsigned Op0 = getRegForValue(I->getOperand(0)); 332 if (Op0 == 0) 333 // Unhandled operand. Halt "fast" selection and bail. 334 return false; 335 336 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 337 338 // Check if the second operand is a constant and handle it appropriately. 339 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 340 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 341 ISDOpcode, Op0, Op0IsKill, 342 CI->getZExtValue()); 343 if (ResultReg != 0) { 344 // We successfully emitted code for the given LLVM Instruction. 345 UpdateValueMap(I, ResultReg); 346 return true; 347 } 348 } 349 350 // Check if the second operand is a constant float. 351 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 352 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 353 ISDOpcode, Op0, Op0IsKill, CF); 354 if (ResultReg != 0) { 355 // We successfully emitted code for the given LLVM Instruction. 356 UpdateValueMap(I, ResultReg); 357 return true; 358 } 359 } 360 361 unsigned Op1 = getRegForValue(I->getOperand(1)); 362 if (Op1 == 0) 363 // Unhandled operand. Halt "fast" selection and bail. 364 return false; 365 366 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); 367 368 // Now we have both operands in registers. Emit the instruction. 369 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 370 ISDOpcode, 371 Op0, Op0IsKill, 372 Op1, Op1IsKill); 373 if (ResultReg == 0) 374 // Target-specific code wasn't able to find a machine opcode for 375 // the given ISD opcode and type. Halt "fast" selection and bail. 376 return false; 377 378 // We successfully emitted code for the given LLVM Instruction. 379 UpdateValueMap(I, ResultReg); 380 return true; 381} 382 383bool FastISel::SelectGetElementPtr(const User *I) { 384 unsigned N = getRegForValue(I->getOperand(0)); 385 if (N == 0) 386 // Unhandled operand. Halt "fast" selection and bail. 387 return false; 388 389 bool NIsKill = hasTrivialKill(I->getOperand(0)); 390 391 const Type *Ty = I->getOperand(0)->getType(); 392 MVT VT = TLI.getPointerTy(); 393 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1, 394 E = I->op_end(); OI != E; ++OI) { 395 const Value *Idx = *OI; 396 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 397 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 398 if (Field) { 399 // N = N + Offset 400 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 401 // FIXME: This can be optimized by combining the add with a 402 // subsequent one. 403 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT); 404 if (N == 0) 405 // Unhandled operand. Halt "fast" selection and bail. 406 return false; 407 NIsKill = true; 408 } 409 Ty = StTy->getElementType(Field); 410 } else { 411 Ty = cast<SequentialType>(Ty)->getElementType(); 412 413 // If this is a constant subscript, handle it quickly. 414 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 415 if (CI->isZero()) continue; 416 uint64_t Offs = 417 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 418 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT); 419 if (N == 0) 420 // Unhandled operand. Halt "fast" selection and bail. 421 return false; 422 NIsKill = true; 423 continue; 424 } 425 426 // N = N + Idx * ElementSize; 427 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 428 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx); 429 unsigned IdxN = Pair.first; 430 bool IdxNIsKill = Pair.second; 431 if (IdxN == 0) 432 // Unhandled operand. Halt "fast" selection and bail. 433 return false; 434 435 if (ElementSize != 1) { 436 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT); 437 if (IdxN == 0) 438 // Unhandled operand. Halt "fast" selection and bail. 439 return false; 440 IdxNIsKill = true; 441 } 442 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill); 443 if (N == 0) 444 // Unhandled operand. Halt "fast" selection and bail. 445 return false; 446 } 447 } 448 449 // We successfully emitted code for the given LLVM Instruction. 450 UpdateValueMap(I, N); 451 return true; 452} 453 454bool FastISel::SelectCall(const User *I) { 455 const Function *F = cast<CallInst>(I)->getCalledFunction(); 456 if (!F) return false; 457 458 // Handle selected intrinsic function calls. 459 unsigned IID = F->getIntrinsicID(); 460 switch (IID) { 461 default: break; 462 case Intrinsic::dbg_declare: { 463 const DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 464 if (!DIVariable(DI->getVariable()).Verify() || 465 !FuncInfo.MF->getMMI().hasDebugInfo()) 466 return true; 467 468 const Value *Address = DI->getAddress(); 469 if (!Address) 470 return true; 471 if (isa<UndefValue>(Address)) 472 return true; 473 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 474 // Don't handle byval struct arguments or VLAs, for example. 475 if (!AI) 476 // Building the map above is target independent. Generating DBG_VALUE 477 // inline is target dependent; do this now. 478 (void)TargetSelectInstruction(cast<Instruction>(I)); 479 return true; 480 } 481 case Intrinsic::dbg_value: { 482 // This form of DBG_VALUE is target-independent. 483 const DbgValueInst *DI = cast<DbgValueInst>(I); 484 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 485 const Value *V = DI->getValue(); 486 if (!V) { 487 // Currently the optimizer can produce this; insert an undef to 488 // help debugging. Probably the optimizer should not do this. 489 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 490 .addReg(0U).addImm(DI->getOffset()) 491 .addMetadata(DI->getVariable()); 492 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 493 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 494 .addImm(CI->getZExtValue()).addImm(DI->getOffset()) 495 .addMetadata(DI->getVariable()); 496 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 497 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 498 .addFPImm(CF).addImm(DI->getOffset()) 499 .addMetadata(DI->getVariable()); 500 } else if (unsigned Reg = lookUpRegForValue(V)) { 501 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 502 .addReg(Reg, RegState::Debug).addImm(DI->getOffset()) 503 .addMetadata(DI->getVariable()); 504 } else { 505 // We can't yet handle anything else here because it would require 506 // generating code, thus altering codegen because of debug info. 507 // Insert an undef so we can see what we dropped. 508 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 509 .addReg(0U).addImm(DI->getOffset()) 510 .addMetadata(DI->getVariable()); 511 } 512 return true; 513 } 514 case Intrinsic::eh_exception: { 515 EVT VT = TLI.getValueType(I->getType()); 516 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 517 default: break; 518 case TargetLowering::Expand: { 519 assert(FuncInfo.MBB->isLandingPad() && 520 "Call to eh.exception not in landing pad!"); 521 unsigned Reg = TLI.getExceptionAddressRegister(); 522 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 523 unsigned ResultReg = createResultReg(RC); 524 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 525 ResultReg).addReg(Reg); 526 UpdateValueMap(I, ResultReg); 527 return true; 528 } 529 } 530 break; 531 } 532 case Intrinsic::eh_selector: { 533 EVT VT = TLI.getValueType(I->getType()); 534 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 535 default: break; 536 case TargetLowering::Expand: { 537 if (FuncInfo.MBB->isLandingPad()) 538 AddCatchInfo(*cast<CallInst>(I), &FuncInfo.MF->getMMI(), FuncInfo.MBB); 539 else { 540#ifndef NDEBUG 541 FuncInfo.CatchInfoLost.insert(cast<CallInst>(I)); 542#endif 543 // FIXME: Mark exception selector register as live in. Hack for PR1508. 544 unsigned Reg = TLI.getExceptionSelectorRegister(); 545 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 546 } 547 548 unsigned Reg = TLI.getExceptionSelectorRegister(); 549 EVT SrcVT = TLI.getPointerTy(); 550 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); 551 unsigned ResultReg = createResultReg(RC); 552 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 553 ResultReg).addReg(Reg); 554 555 bool ResultRegIsKill = hasTrivialKill(I); 556 557 // Cast the register to the type of the selector. 558 if (SrcVT.bitsGT(MVT::i32)) 559 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE, 560 ResultReg, ResultRegIsKill); 561 else if (SrcVT.bitsLT(MVT::i32)) 562 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, 563 ISD::SIGN_EXTEND, ResultReg, ResultRegIsKill); 564 if (ResultReg == 0) 565 // Unhandled operand. Halt "fast" selection and bail. 566 return false; 567 568 UpdateValueMap(I, ResultReg); 569 570 return true; 571 } 572 } 573 break; 574 } 575 } 576 577 // An arbitrary call. Bail. 578 return false; 579} 580 581bool FastISel::SelectCast(const User *I, unsigned Opcode) { 582 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 583 EVT DstVT = TLI.getValueType(I->getType()); 584 585 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 586 DstVT == MVT::Other || !DstVT.isSimple()) 587 // Unhandled type. Halt "fast" selection and bail. 588 return false; 589 590 // Check if the destination type is legal. Or as a special case, 591 // it may be i1 if we're doing a truncate because that's 592 // easy and somewhat common. 593 if (!TLI.isTypeLegal(DstVT)) 594 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 595 // Unhandled type. Halt "fast" selection and bail. 596 return false; 597 598 // Check if the source operand is legal. Or as a special case, 599 // it may be i1 if we're doing zero-extension because that's 600 // easy and somewhat common. 601 if (!TLI.isTypeLegal(SrcVT)) 602 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 603 // Unhandled type. Halt "fast" selection and bail. 604 return false; 605 606 unsigned InputReg = getRegForValue(I->getOperand(0)); 607 if (!InputReg) 608 // Unhandled operand. Halt "fast" selection and bail. 609 return false; 610 611 bool InputRegIsKill = hasTrivialKill(I->getOperand(0)); 612 613 // If the operand is i1, arrange for the high bits in the register to be zero. 614 if (SrcVT == MVT::i1) { 615 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT); 616 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg, InputRegIsKill); 617 if (!InputReg) 618 return false; 619 InputRegIsKill = true; 620 } 621 // If the result is i1, truncate to the target's type for i1 first. 622 if (DstVT == MVT::i1) 623 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT); 624 625 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 626 DstVT.getSimpleVT(), 627 Opcode, 628 InputReg, InputRegIsKill); 629 if (!ResultReg) 630 return false; 631 632 UpdateValueMap(I, ResultReg); 633 return true; 634} 635 636bool FastISel::SelectBitCast(const User *I) { 637 // If the bitcast doesn't change the type, just use the operand value. 638 if (I->getType() == I->getOperand(0)->getType()) { 639 unsigned Reg = getRegForValue(I->getOperand(0)); 640 if (Reg == 0) 641 return false; 642 UpdateValueMap(I, Reg); 643 return true; 644 } 645 646 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 647 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 648 EVT DstVT = TLI.getValueType(I->getType()); 649 650 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 651 DstVT == MVT::Other || !DstVT.isSimple() || 652 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 653 // Unhandled type. Halt "fast" selection and bail. 654 return false; 655 656 unsigned Op0 = getRegForValue(I->getOperand(0)); 657 if (Op0 == 0) 658 // Unhandled operand. Halt "fast" selection and bail. 659 return false; 660 661 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 662 663 // First, try to perform the bitcast by inserting a reg-reg copy. 664 unsigned ResultReg = 0; 665 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 666 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 667 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 668 // Don't attempt a cross-class copy. It will likely fail. 669 if (SrcClass == DstClass) { 670 ResultReg = createResultReg(DstClass); 671 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 672 ResultReg).addReg(Op0); 673 } 674 } 675 676 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 677 if (!ResultReg) 678 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 679 ISD::BIT_CONVERT, Op0, Op0IsKill); 680 681 if (!ResultReg) 682 return false; 683 684 UpdateValueMap(I, ResultReg); 685 return true; 686} 687 688bool 689FastISel::SelectInstruction(const Instruction *I) { 690 // Just before the terminator instruction, insert instructions to 691 // feed PHI nodes in successor blocks. 692 if (isa<TerminatorInst>(I)) 693 if (!HandlePHINodesInSuccessorBlocks(I->getParent())) 694 return false; 695 696 DL = I->getDebugLoc(); 697 698 // First, try doing target-independent selection. 699 if (SelectOperator(I, I->getOpcode())) { 700 DL = DebugLoc(); 701 return true; 702 } 703 704 // Next, try calling the target to attempt to handle the instruction. 705 if (TargetSelectInstruction(I)) { 706 DL = DebugLoc(); 707 return true; 708 } 709 710 DL = DebugLoc(); 711 return false; 712} 713 714/// FastEmitBranch - Emit an unconditional branch to the given block, 715/// unless it is the immediate (fall-through) successor, and update 716/// the CFG. 717void 718FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) { 719 if (FuncInfo.MBB->isLayoutSuccessor(MSucc)) { 720 // The unconditional fall-through case, which needs no instructions. 721 } else { 722 // The unconditional branch case. 723 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL, 724 SmallVector<MachineOperand, 0>(), DL); 725 } 726 FuncInfo.MBB->addSuccessor(MSucc); 727} 728 729/// SelectFNeg - Emit an FNeg operation. 730/// 731bool 732FastISel::SelectFNeg(const User *I) { 733 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); 734 if (OpReg == 0) return false; 735 736 bool OpRegIsKill = hasTrivialKill(I); 737 738 // If the target has ISD::FNEG, use it. 739 EVT VT = TLI.getValueType(I->getType()); 740 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), 741 ISD::FNEG, OpReg, OpRegIsKill); 742 if (ResultReg != 0) { 743 UpdateValueMap(I, ResultReg); 744 return true; 745 } 746 747 // Bitcast the value to integer, twiddle the sign bit with xor, 748 // and then bitcast it back to floating-point. 749 if (VT.getSizeInBits() > 64) return false; 750 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); 751 if (!TLI.isTypeLegal(IntVT)) 752 return false; 753 754 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), 755 ISD::BIT_CONVERT, OpReg, OpRegIsKill); 756 if (IntReg == 0) 757 return false; 758 759 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, 760 IntReg, /*Kill=*/true, 761 UINT64_C(1) << (VT.getSizeInBits()-1), 762 IntVT.getSimpleVT()); 763 if (IntResultReg == 0) 764 return false; 765 766 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), 767 ISD::BIT_CONVERT, IntResultReg, /*Kill=*/true); 768 if (ResultReg == 0) 769 return false; 770 771 UpdateValueMap(I, ResultReg); 772 return true; 773} 774 775bool 776FastISel::SelectOperator(const User *I, unsigned Opcode) { 777 switch (Opcode) { 778 case Instruction::Add: 779 return SelectBinaryOp(I, ISD::ADD); 780 case Instruction::FAdd: 781 return SelectBinaryOp(I, ISD::FADD); 782 case Instruction::Sub: 783 return SelectBinaryOp(I, ISD::SUB); 784 case Instruction::FSub: 785 // FNeg is currently represented in LLVM IR as a special case of FSub. 786 if (BinaryOperator::isFNeg(I)) 787 return SelectFNeg(I); 788 return SelectBinaryOp(I, ISD::FSUB); 789 case Instruction::Mul: 790 return SelectBinaryOp(I, ISD::MUL); 791 case Instruction::FMul: 792 return SelectBinaryOp(I, ISD::FMUL); 793 case Instruction::SDiv: 794 return SelectBinaryOp(I, ISD::SDIV); 795 case Instruction::UDiv: 796 return SelectBinaryOp(I, ISD::UDIV); 797 case Instruction::FDiv: 798 return SelectBinaryOp(I, ISD::FDIV); 799 case Instruction::SRem: 800 return SelectBinaryOp(I, ISD::SREM); 801 case Instruction::URem: 802 return SelectBinaryOp(I, ISD::UREM); 803 case Instruction::FRem: 804 return SelectBinaryOp(I, ISD::FREM); 805 case Instruction::Shl: 806 return SelectBinaryOp(I, ISD::SHL); 807 case Instruction::LShr: 808 return SelectBinaryOp(I, ISD::SRL); 809 case Instruction::AShr: 810 return SelectBinaryOp(I, ISD::SRA); 811 case Instruction::And: 812 return SelectBinaryOp(I, ISD::AND); 813 case Instruction::Or: 814 return SelectBinaryOp(I, ISD::OR); 815 case Instruction::Xor: 816 return SelectBinaryOp(I, ISD::XOR); 817 818 case Instruction::GetElementPtr: 819 return SelectGetElementPtr(I); 820 821 case Instruction::Br: { 822 const BranchInst *BI = cast<BranchInst>(I); 823 824 if (BI->isUnconditional()) { 825 const BasicBlock *LLVMSucc = BI->getSuccessor(0); 826 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc]; 827 FastEmitBranch(MSucc, BI->getDebugLoc()); 828 return true; 829 } 830 831 // Conditional branches are not handed yet. 832 // Halt "fast" selection and bail. 833 return false; 834 } 835 836 case Instruction::Unreachable: 837 // Nothing to emit. 838 return true; 839 840 case Instruction::Alloca: 841 // FunctionLowering has the static-sized case covered. 842 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I))) 843 return true; 844 845 // Dynamic-sized alloca is not handled yet. 846 return false; 847 848 case Instruction::Call: 849 return SelectCall(I); 850 851 case Instruction::BitCast: 852 return SelectBitCast(I); 853 854 case Instruction::FPToSI: 855 return SelectCast(I, ISD::FP_TO_SINT); 856 case Instruction::ZExt: 857 return SelectCast(I, ISD::ZERO_EXTEND); 858 case Instruction::SExt: 859 return SelectCast(I, ISD::SIGN_EXTEND); 860 case Instruction::Trunc: 861 return SelectCast(I, ISD::TRUNCATE); 862 case Instruction::SIToFP: 863 return SelectCast(I, ISD::SINT_TO_FP); 864 865 case Instruction::IntToPtr: // Deliberate fall-through. 866 case Instruction::PtrToInt: { 867 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 868 EVT DstVT = TLI.getValueType(I->getType()); 869 if (DstVT.bitsGT(SrcVT)) 870 return SelectCast(I, ISD::ZERO_EXTEND); 871 if (DstVT.bitsLT(SrcVT)) 872 return SelectCast(I, ISD::TRUNCATE); 873 unsigned Reg = getRegForValue(I->getOperand(0)); 874 if (Reg == 0) return false; 875 UpdateValueMap(I, Reg); 876 return true; 877 } 878 879 case Instruction::PHI: 880 llvm_unreachable("FastISel shouldn't visit PHI nodes!"); 881 882 default: 883 // Unhandled instruction. Halt "fast" selection and bail. 884 return false; 885 } 886} 887 888FastISel::FastISel(FunctionLoweringInfo &funcInfo) 889 : FuncInfo(funcInfo), 890 MRI(FuncInfo.MF->getRegInfo()), 891 MFI(*FuncInfo.MF->getFrameInfo()), 892 MCP(*FuncInfo.MF->getConstantPool()), 893 TM(FuncInfo.MF->getTarget()), 894 TD(*TM.getTargetData()), 895 TII(*TM.getInstrInfo()), 896 TLI(*TM.getTargetLowering()), 897 TRI(*TM.getRegisterInfo()) { 898} 899 900FastISel::~FastISel() {} 901 902unsigned FastISel::FastEmit_(MVT, MVT, 903 unsigned) { 904 return 0; 905} 906 907unsigned FastISel::FastEmit_r(MVT, MVT, 908 unsigned, 909 unsigned /*Op0*/, bool /*Op0IsKill*/) { 910 return 0; 911} 912 913unsigned FastISel::FastEmit_rr(MVT, MVT, 914 unsigned, 915 unsigned /*Op0*/, bool /*Op0IsKill*/, 916 unsigned /*Op1*/, bool /*Op1IsKill*/) { 917 return 0; 918} 919 920unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) { 921 return 0; 922} 923 924unsigned FastISel::FastEmit_f(MVT, MVT, 925 unsigned, const ConstantFP * /*FPImm*/) { 926 return 0; 927} 928 929unsigned FastISel::FastEmit_ri(MVT, MVT, 930 unsigned, 931 unsigned /*Op0*/, bool /*Op0IsKill*/, 932 uint64_t /*Imm*/) { 933 return 0; 934} 935 936unsigned FastISel::FastEmit_rf(MVT, MVT, 937 unsigned, 938 unsigned /*Op0*/, bool /*Op0IsKill*/, 939 const ConstantFP * /*FPImm*/) { 940 return 0; 941} 942 943unsigned FastISel::FastEmit_rri(MVT, MVT, 944 unsigned, 945 unsigned /*Op0*/, bool /*Op0IsKill*/, 946 unsigned /*Op1*/, bool /*Op1IsKill*/, 947 uint64_t /*Imm*/) { 948 return 0; 949} 950 951/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 952/// to emit an instruction with an immediate operand using FastEmit_ri. 953/// If that fails, it materializes the immediate into a register and try 954/// FastEmit_rr instead. 955unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode, 956 unsigned Op0, bool Op0IsKill, 957 uint64_t Imm, MVT ImmType) { 958 // First check if immediate type is legal. If not, we can't use the ri form. 959 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); 960 if (ResultReg != 0) 961 return ResultReg; 962 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 963 if (MaterialReg == 0) 964 return 0; 965 return FastEmit_rr(VT, VT, Opcode, 966 Op0, Op0IsKill, 967 MaterialReg, /*Kill=*/true); 968} 969 970/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 971/// to emit an instruction with a floating-point immediate operand using 972/// FastEmit_rf. If that fails, it materializes the immediate into a register 973/// and try FastEmit_rr instead. 974unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode, 975 unsigned Op0, bool Op0IsKill, 976 const ConstantFP *FPImm, MVT ImmType) { 977 // First check if immediate type is legal. If not, we can't use the rf form. 978 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, Op0IsKill, FPImm); 979 if (ResultReg != 0) 980 return ResultReg; 981 982 // Materialize the constant in a register. 983 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 984 if (MaterialReg == 0) { 985 // If the target doesn't have a way to directly enter a floating-point 986 // value into a register, use an alternate approach. 987 // TODO: The current approach only supports floating-point constants 988 // that can be constructed by conversion from integer values. This should 989 // be replaced by code that creates a load from a constant-pool entry, 990 // which will require some target-specific work. 991 const APFloat &Flt = FPImm->getValueAPF(); 992 EVT IntVT = TLI.getPointerTy(); 993 994 uint64_t x[2]; 995 uint32_t IntBitWidth = IntVT.getSizeInBits(); 996 bool isExact; 997 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 998 APFloat::rmTowardZero, &isExact); 999 if (!isExact) 1000 return 0; 1001 APInt IntVal(IntBitWidth, 2, x); 1002 1003 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 1004 ISD::Constant, IntVal.getZExtValue()); 1005 if (IntegerReg == 0) 1006 return 0; 1007 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 1008 ISD::SINT_TO_FP, IntegerReg, /*Kill=*/true); 1009 if (MaterialReg == 0) 1010 return 0; 1011 } 1012 return FastEmit_rr(VT, VT, Opcode, 1013 Op0, Op0IsKill, 1014 MaterialReg, /*Kill=*/true); 1015} 1016 1017unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 1018 return MRI.createVirtualRegister(RC); 1019} 1020 1021unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 1022 const TargetRegisterClass* RC) { 1023 unsigned ResultReg = createResultReg(RC); 1024 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1025 1026 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg); 1027 return ResultReg; 1028} 1029 1030unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 1031 const TargetRegisterClass *RC, 1032 unsigned Op0, bool Op0IsKill) { 1033 unsigned ResultReg = createResultReg(RC); 1034 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1035 1036 if (II.getNumDefs() >= 1) 1037 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1038 .addReg(Op0, Op0IsKill * RegState::Kill); 1039 else { 1040 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1041 .addReg(Op0, Op0IsKill * RegState::Kill); 1042 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1043 ResultReg).addReg(II.ImplicitDefs[0]); 1044 } 1045 1046 return ResultReg; 1047} 1048 1049unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 1050 const TargetRegisterClass *RC, 1051 unsigned Op0, bool Op0IsKill, 1052 unsigned Op1, bool Op1IsKill) { 1053 unsigned ResultReg = createResultReg(RC); 1054 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1055 1056 if (II.getNumDefs() >= 1) 1057 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1058 .addReg(Op0, Op0IsKill * RegState::Kill) 1059 .addReg(Op1, Op1IsKill * RegState::Kill); 1060 else { 1061 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1062 .addReg(Op0, Op0IsKill * RegState::Kill) 1063 .addReg(Op1, Op1IsKill * RegState::Kill); 1064 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1065 ResultReg).addReg(II.ImplicitDefs[0]); 1066 } 1067 return ResultReg; 1068} 1069 1070unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 1071 const TargetRegisterClass *RC, 1072 unsigned Op0, bool Op0IsKill, 1073 uint64_t Imm) { 1074 unsigned ResultReg = createResultReg(RC); 1075 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1076 1077 if (II.getNumDefs() >= 1) 1078 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1079 .addReg(Op0, Op0IsKill * RegState::Kill) 1080 .addImm(Imm); 1081 else { 1082 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1083 .addReg(Op0, Op0IsKill * RegState::Kill) 1084 .addImm(Imm); 1085 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1086 ResultReg).addReg(II.ImplicitDefs[0]); 1087 } 1088 return ResultReg; 1089} 1090 1091unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 1092 const TargetRegisterClass *RC, 1093 unsigned Op0, bool Op0IsKill, 1094 const ConstantFP *FPImm) { 1095 unsigned ResultReg = createResultReg(RC); 1096 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1097 1098 if (II.getNumDefs() >= 1) 1099 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1100 .addReg(Op0, Op0IsKill * RegState::Kill) 1101 .addFPImm(FPImm); 1102 else { 1103 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1104 .addReg(Op0, Op0IsKill * RegState::Kill) 1105 .addFPImm(FPImm); 1106 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1107 ResultReg).addReg(II.ImplicitDefs[0]); 1108 } 1109 return ResultReg; 1110} 1111 1112unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 1113 const TargetRegisterClass *RC, 1114 unsigned Op0, bool Op0IsKill, 1115 unsigned Op1, bool Op1IsKill, 1116 uint64_t Imm) { 1117 unsigned ResultReg = createResultReg(RC); 1118 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1119 1120 if (II.getNumDefs() >= 1) 1121 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1122 .addReg(Op0, Op0IsKill * RegState::Kill) 1123 .addReg(Op1, Op1IsKill * RegState::Kill) 1124 .addImm(Imm); 1125 else { 1126 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1127 .addReg(Op0, Op0IsKill * RegState::Kill) 1128 .addReg(Op1, Op1IsKill * RegState::Kill) 1129 .addImm(Imm); 1130 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1131 ResultReg).addReg(II.ImplicitDefs[0]); 1132 } 1133 return ResultReg; 1134} 1135 1136unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 1137 const TargetRegisterClass *RC, 1138 uint64_t Imm) { 1139 unsigned ResultReg = createResultReg(RC); 1140 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1141 1142 if (II.getNumDefs() >= 1) 1143 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm); 1144 else { 1145 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm); 1146 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1147 ResultReg).addReg(II.ImplicitDefs[0]); 1148 } 1149 return ResultReg; 1150} 1151 1152unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, 1153 unsigned Op0, bool Op0IsKill, 1154 uint32_t Idx) { 1155 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1156 assert(TargetRegisterInfo::isVirtualRegister(Op0) && 1157 "Cannot yet extract from physregs"); 1158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 1159 DL, TII.get(TargetOpcode::COPY), ResultReg) 1160 .addReg(Op0, getKillRegState(Op0IsKill), Idx); 1161 return ResultReg; 1162} 1163 1164/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1165/// with all but the least significant bit set to zero. 1166unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) { 1167 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1); 1168} 1169 1170/// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks. 1171/// Emit code to ensure constants are copied into registers when needed. 1172/// Remember the virtual registers that need to be added to the Machine PHI 1173/// nodes as input. We cannot just directly add them, because expansion 1174/// might result in multiple MBB's for one BB. As such, the start of the 1175/// BB might correspond to a different MBB than the end. 1176bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 1177 const TerminatorInst *TI = LLVMBB->getTerminator(); 1178 1179 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 1180 unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size(); 1181 1182 // Check successor nodes' PHI nodes that expect a constant to be available 1183 // from this block. 1184 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 1185 const BasicBlock *SuccBB = TI->getSuccessor(succ); 1186 if (!isa<PHINode>(SuccBB->begin())) continue; 1187 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 1188 1189 // If this terminator has multiple identical successors (common for 1190 // switches), only handle each succ once. 1191 if (!SuccsHandled.insert(SuccMBB)) continue; 1192 1193 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 1194 1195 // At this point we know that there is a 1-1 correspondence between LLVM PHI 1196 // nodes and Machine PHI nodes, but the incoming operands have not been 1197 // emitted yet. 1198 for (BasicBlock::const_iterator I = SuccBB->begin(); 1199 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 1200 1201 // Ignore dead phi's. 1202 if (PN->use_empty()) continue; 1203 1204 // Only handle legal types. Two interesting things to note here. First, 1205 // by bailing out early, we may leave behind some dead instructions, 1206 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its 1207 // own moves. Second, this check is necessary becuase FastISel doesn't 1208 // use CreateRegs to create registers, so it always creates 1209 // exactly one register for each non-void instruction. 1210 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true); 1211 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) { 1212 // Promote MVT::i1. 1213 if (VT == MVT::i1) 1214 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT); 1215 else { 1216 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1217 return false; 1218 } 1219 } 1220 1221 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 1222 1223 // Set the DebugLoc for the copy. Prefer the location of the operand 1224 // if there is one; use the location of the PHI otherwise. 1225 DL = PN->getDebugLoc(); 1226 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp)) 1227 DL = Inst->getDebugLoc(); 1228 1229 unsigned Reg = getRegForValue(PHIOp); 1230 if (Reg == 0) { 1231 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1232 return false; 1233 } 1234 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg)); 1235 DL = DebugLoc(); 1236 } 1237 } 1238 1239 return true; 1240} 1241