FastISel.cpp revision be8cc2a3dedeb7685f07e68cdc4b9502eb97eb2b
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/CodeGen/DebugLoc.h" 51#include "llvm/CodeGen/DwarfWriter.h" 52#include "llvm/Analysis/DebugInfo.h" 53#include "llvm/Target/TargetData.h" 54#include "llvm/Target/TargetInstrInfo.h" 55#include "llvm/Target/TargetLowering.h" 56#include "llvm/Target/TargetMachine.h" 57#include "SelectionDAGBuild.h" 58using namespace llvm; 59 60unsigned FastISel::getRegForValue(Value *V) { 61 MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 62 // Don't handle non-simple values in FastISel. 63 if (!RealVT.isSimple()) 64 return 0; 65 66 // Ignore illegal types. We must do this before looking up the value 67 // in ValueMap because Arguments are given virtual registers regardless 68 // of whether FastISel can handle them. 69 MVT::SimpleValueType VT = RealVT.getSimpleVT(); 70 if (!TLI.isTypeLegal(VT)) { 71 // Promote MVT::i1 to a legal type though, because it's common and easy. 72 if (VT == MVT::i1) 73 VT = TLI.getTypeToTransformTo(VT).getSimpleVT(); 74 else 75 return 0; 76 } 77 78 // Look up the value to see if we already have a register for it. We 79 // cache values defined by Instructions across blocks, and other values 80 // only locally. This is because Instructions already have the SSA 81 // def-dominatess-use requirement enforced. 82 if (ValueMap.count(V)) 83 return ValueMap[V]; 84 unsigned Reg = LocalValueMap[V]; 85 if (Reg != 0) 86 return Reg; 87 88 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 89 if (CI->getValue().getActiveBits() <= 64) 90 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 91 } else if (isa<AllocaInst>(V)) { 92 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 93 } else if (isa<ConstantPointerNull>(V)) { 94 // Translate this as an integer zero so that it can be 95 // local-CSE'd with actual integer zeros. 96 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType())); 97 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 98 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 99 100 if (!Reg) { 101 const APFloat &Flt = CF->getValueAPF(); 102 MVT IntVT = TLI.getPointerTy(); 103 104 uint64_t x[2]; 105 uint32_t IntBitWidth = IntVT.getSizeInBits(); 106 bool isExact; 107 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 108 APFloat::rmTowardZero, &isExact); 109 if (isExact) { 110 APInt IntVal(IntBitWidth, 2, x); 111 112 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal)); 113 if (IntegerReg != 0) 114 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 115 } 116 } 117 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 118 if (!SelectOperator(CE, CE->getOpcode())) return 0; 119 Reg = LocalValueMap[CE]; 120 } else if (isa<UndefValue>(V)) { 121 Reg = createResultReg(TLI.getRegClassFor(VT)); 122 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); 123 } 124 125 // If target-independent code couldn't handle the value, give target-specific 126 // code a try. 127 if (!Reg && isa<Constant>(V)) 128 Reg = TargetMaterializeConstant(cast<Constant>(V)); 129 130 // Don't cache constant materializations in the general ValueMap. 131 // To do so would require tracking what uses they dominate. 132 if (Reg != 0) 133 LocalValueMap[V] = Reg; 134 return Reg; 135} 136 137unsigned FastISel::lookUpRegForValue(Value *V) { 138 // Look up the value to see if we already have a register for it. We 139 // cache values defined by Instructions across blocks, and other values 140 // only locally. This is because Instructions already have the SSA 141 // def-dominatess-use requirement enforced. 142 if (ValueMap.count(V)) 143 return ValueMap[V]; 144 return LocalValueMap[V]; 145} 146 147/// UpdateValueMap - Update the value map to include the new mapping for this 148/// instruction, or insert an extra copy to get the result in a previous 149/// determined register. 150/// NOTE: This is only necessary because we might select a block that uses 151/// a value before we select the block that defines the value. It might be 152/// possible to fix this by selecting blocks in reverse postorder. 153unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) { 154 if (!isa<Instruction>(I)) { 155 LocalValueMap[I] = Reg; 156 return Reg; 157 } 158 159 unsigned &AssignedReg = ValueMap[I]; 160 if (AssignedReg == 0) 161 AssignedReg = Reg; 162 else if (Reg != AssignedReg) { 163 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); 164 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg, 165 Reg, RegClass, RegClass); 166 } 167 return AssignedReg; 168} 169 170unsigned FastISel::getRegForGEPIndex(Value *Idx) { 171 unsigned IdxN = getRegForValue(Idx); 172 if (IdxN == 0) 173 // Unhandled operand. Halt "fast" selection and bail. 174 return 0; 175 176 // If the index is smaller or larger than intptr_t, truncate or extend it. 177 MVT PtrVT = TLI.getPointerTy(); 178 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); 179 if (IdxVT.bitsLT(PtrVT)) 180 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 181 ISD::SIGN_EXTEND, IdxN); 182 else if (IdxVT.bitsGT(PtrVT)) 183 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 184 ISD::TRUNCATE, IdxN); 185 return IdxN; 186} 187 188/// SelectBinaryOp - Select and emit code for a binary operator instruction, 189/// which has an opcode which directly corresponds to the given ISD opcode. 190/// 191bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { 192 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); 193 if (VT == MVT::Other || !VT.isSimple()) 194 // Unhandled type. Halt "fast" selection and bail. 195 return false; 196 197 // We only handle legal types. For example, on x86-32 the instruction 198 // selector contains all of the 64-bit instructions from x86-64, 199 // under the assumption that i64 won't be used if the target doesn't 200 // support it. 201 if (!TLI.isTypeLegal(VT)) { 202 // MVT::i1 is special. Allow AND, OR, or XOR because they 203 // don't require additional zeroing, which makes them easy. 204 if (VT == MVT::i1 && 205 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 206 ISDOpcode == ISD::XOR)) 207 VT = TLI.getTypeToTransformTo(VT); 208 else 209 return false; 210 } 211 212 unsigned Op0 = getRegForValue(I->getOperand(0)); 213 if (Op0 == 0) 214 // Unhandled operand. Halt "fast" selection and bail. 215 return false; 216 217 // Check if the second operand is a constant and handle it appropriately. 218 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 219 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 220 ISDOpcode, Op0, CI->getZExtValue()); 221 if (ResultReg != 0) { 222 // We successfully emitted code for the given LLVM Instruction. 223 UpdateValueMap(I, ResultReg); 224 return true; 225 } 226 } 227 228 // Check if the second operand is a constant float. 229 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 230 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 231 ISDOpcode, Op0, CF); 232 if (ResultReg != 0) { 233 // We successfully emitted code for the given LLVM Instruction. 234 UpdateValueMap(I, ResultReg); 235 return true; 236 } 237 } 238 239 unsigned Op1 = getRegForValue(I->getOperand(1)); 240 if (Op1 == 0) 241 // Unhandled operand. Halt "fast" selection and bail. 242 return false; 243 244 // Now we have both operands in registers. Emit the instruction. 245 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 246 ISDOpcode, Op0, Op1); 247 if (ResultReg == 0) 248 // Target-specific code wasn't able to find a machine opcode for 249 // the given ISD opcode and type. Halt "fast" selection and bail. 250 return false; 251 252 // We successfully emitted code for the given LLVM Instruction. 253 UpdateValueMap(I, ResultReg); 254 return true; 255} 256 257bool FastISel::SelectGetElementPtr(User *I) { 258 unsigned N = getRegForValue(I->getOperand(0)); 259 if (N == 0) 260 // Unhandled operand. Halt "fast" selection and bail. 261 return false; 262 263 const Type *Ty = I->getOperand(0)->getType(); 264 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT(); 265 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 266 OI != E; ++OI) { 267 Value *Idx = *OI; 268 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 269 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 270 if (Field) { 271 // N = N + Offset 272 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 273 // FIXME: This can be optimized by combining the add with a 274 // subsequent one. 275 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 276 if (N == 0) 277 // Unhandled operand. Halt "fast" selection and bail. 278 return false; 279 } 280 Ty = StTy->getElementType(Field); 281 } else { 282 Ty = cast<SequentialType>(Ty)->getElementType(); 283 284 // If this is a constant subscript, handle it quickly. 285 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 286 if (CI->getZExtValue() == 0) continue; 287 uint64_t Offs = 288 TD.getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 289 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 290 if (N == 0) 291 // Unhandled operand. Halt "fast" selection and bail. 292 return false; 293 continue; 294 } 295 296 // N = N + Idx * ElementSize; 297 uint64_t ElementSize = TD.getTypePaddedSize(Ty); 298 unsigned IdxN = getRegForGEPIndex(Idx); 299 if (IdxN == 0) 300 // Unhandled operand. Halt "fast" selection and bail. 301 return false; 302 303 if (ElementSize != 1) { 304 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 305 if (IdxN == 0) 306 // Unhandled operand. Halt "fast" selection and bail. 307 return false; 308 } 309 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 310 if (N == 0) 311 // Unhandled operand. Halt "fast" selection and bail. 312 return false; 313 } 314 } 315 316 // We successfully emitted code for the given LLVM Instruction. 317 UpdateValueMap(I, N); 318 return true; 319} 320 321bool FastISel::SelectCall(User *I) { 322 Function *F = cast<CallInst>(I)->getCalledFunction(); 323 if (!F) return false; 324 325 unsigned IID = F->getIntrinsicID(); 326 switch (IID) { 327 default: break; 328 case Intrinsic::dbg_stoppoint: { 329 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); 330 if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) { 331 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext())); 332 std::string Dir, FN; 333 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir), 334 CU.getFilename(FN)); 335 unsigned Line = SPI->getLine(); 336 unsigned Col = SPI->getColumn(); 337 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); 338 unsigned Idx = MF.getOrCreateDebugLocID(SrcFile, Line, Col); 339 setCurDebugLoc(DebugLoc::get(Idx)); 340 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 341 BuildMI(MBB, DL, II).addImm(ID); 342 } 343 return true; 344 } 345 case Intrinsic::dbg_region_start: { 346 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I); 347 if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) { 348 unsigned ID = 349 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext())); 350 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 351 BuildMI(MBB, DL, II).addImm(ID); 352 } 353 return true; 354 } 355 case Intrinsic::dbg_region_end: { 356 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I); 357 if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) { 358 unsigned ID = 0; 359 DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext())); 360 if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) { 361 // This is end of an inlined function. 362 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 363 ID = DW->RecordInlinedFnEnd(Subprogram); 364 if (ID) 365 // Returned ID is 0 if this is unbalanced "end of inlined 366 // scope". This could happen if optimizer eats dbg intrinsics 367 // or "beginning of inlined scope" is not recoginized due to 368 // missing location info. In such cases, do ignore this region.end. 369 BuildMI(MBB, DL, II).addImm(ID); 370 } else { 371 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 372 ID = DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext())); 373 BuildMI(MBB, DL, II).addImm(ID); 374 } 375 } 376 return true; 377 } 378 case Intrinsic::dbg_func_start: { 379 if (!DW) return true; 380 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); 381 Value *SP = FSI->getSubprogram(); 382 383 if (DW->ValidDebugInfo(SP, 0)) { 384 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what 385 // (most?) gdb expects. 386 DebugLoc PrevLoc = DL; 387 DISubprogram Subprogram(cast<GlobalVariable>(SP)); 388 DICompileUnit CompileUnit = Subprogram.getCompileUnit(); 389 std::string Dir, FN; 390 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir), 391 CompileUnit.getFilename(FN)); 392 393 if (!Subprogram.describes(MF.getFunction())) { 394 // This is a beginning of an inlined function. 395 396 // If llvm.dbg.func.start is seen in a new block before any 397 // llvm.dbg.stoppoint intrinsic then the location info is unknown. 398 // FIXME : Why DebugLoc is reset at the beginning of each block ? 399 if (PrevLoc.isUnknown()) 400 return true; 401 // Record the source line. 402 unsigned Line = Subprogram.getLineNumber(); 403 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); 404 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0))); 405 406 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 407 BuildMI(MBB, DL, II).addImm(LabelID); 408 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc); 409 DW->RecordInlinedFnStart(FSI, Subprogram, LabelID, 410 PrevLocTpl.Src, 411 PrevLocTpl.Line, 412 PrevLocTpl.Col); 413 } else { 414 // Record the source line. 415 unsigned Line = Subprogram.getLineNumber(); 416 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0))); 417 DW->RecordSourceLine(Line, 0, SrcFile); 418 // llvm.dbg.func_start also defines beginning of function scope. 419 DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram())); 420 } 421 } 422 423 return true; 424 } 425 case Intrinsic::dbg_declare: { 426 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 427 Value *Variable = DI->getVariable(); 428 if (DW && DW->ValidDebugInfo(Variable, 0)) { 429 // Determine the address of the declared object. 430 Value *Address = DI->getAddress(); 431 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 432 Address = BCI->getOperand(0); 433 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 434 // Don't handle byval struct arguments or VLAs, for example. 435 if (!AI) break; 436 DenseMap<const AllocaInst*, int>::iterator SI = 437 StaticAllocaMap.find(AI); 438 if (SI == StaticAllocaMap.end()) break; // VLAs. 439 int FI = SI->second; 440 441 // Determine the debug globalvariable. 442 GlobalValue *GV = cast<GlobalVariable>(Variable); 443 444 // Build the DECLARE instruction. 445 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE); 446 MachineInstr *DeclareMI 447 = BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV); 448 DIVariable DV(cast<GlobalVariable>(GV)); 449 if (!DV.isNull()) { 450 // This is a local variable 451 DW->RecordVariableScope(DV, DeclareMI); 452 } 453 } 454 return true; 455 } 456 case Intrinsic::eh_exception: { 457 MVT VT = TLI.getValueType(I->getType()); 458 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 459 default: break; 460 case TargetLowering::Expand: { 461 if (!MBB->isLandingPad()) { 462 // FIXME: Mark exception register as live in. Hack for PR1508. 463 unsigned Reg = TLI.getExceptionAddressRegister(); 464 if (Reg) MBB->addLiveIn(Reg); 465 } 466 unsigned Reg = TLI.getExceptionAddressRegister(); 467 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 468 unsigned ResultReg = createResultReg(RC); 469 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 470 Reg, RC, RC); 471 assert(InsertedCopy && "Can't copy address registers!"); 472 InsertedCopy = InsertedCopy; 473 UpdateValueMap(I, ResultReg); 474 return true; 475 } 476 } 477 break; 478 } 479 case Intrinsic::eh_selector_i32: 480 case Intrinsic::eh_selector_i64: { 481 MVT VT = TLI.getValueType(I->getType()); 482 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 483 default: break; 484 case TargetLowering::Expand: { 485 MVT VT = (IID == Intrinsic::eh_selector_i32 ? 486 MVT::i32 : MVT::i64); 487 488 if (MMI) { 489 if (MBB->isLandingPad()) 490 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 491 else { 492#ifndef NDEBUG 493 CatchInfoLost.insert(cast<CallInst>(I)); 494#endif 495 // FIXME: Mark exception selector register as live in. Hack for PR1508. 496 unsigned Reg = TLI.getExceptionSelectorRegister(); 497 if (Reg) MBB->addLiveIn(Reg); 498 } 499 500 unsigned Reg = TLI.getExceptionSelectorRegister(); 501 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 502 unsigned ResultReg = createResultReg(RC); 503 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 504 Reg, RC, RC); 505 assert(InsertedCopy && "Can't copy address registers!"); 506 InsertedCopy = InsertedCopy; 507 UpdateValueMap(I, ResultReg); 508 } else { 509 unsigned ResultReg = 510 getRegForValue(Constant::getNullValue(I->getType())); 511 UpdateValueMap(I, ResultReg); 512 } 513 return true; 514 } 515 } 516 break; 517 } 518 } 519 return false; 520} 521 522bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { 523 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 524 MVT DstVT = TLI.getValueType(I->getType()); 525 526 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 527 DstVT == MVT::Other || !DstVT.isSimple()) 528 // Unhandled type. Halt "fast" selection and bail. 529 return false; 530 531 // Check if the destination type is legal. Or as a special case, 532 // it may be i1 if we're doing a truncate because that's 533 // easy and somewhat common. 534 if (!TLI.isTypeLegal(DstVT)) 535 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 536 // Unhandled type. Halt "fast" selection and bail. 537 return false; 538 539 // Check if the source operand is legal. Or as a special case, 540 // it may be i1 if we're doing zero-extension because that's 541 // easy and somewhat common. 542 if (!TLI.isTypeLegal(SrcVT)) 543 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 544 // Unhandled type. Halt "fast" selection and bail. 545 return false; 546 547 unsigned InputReg = getRegForValue(I->getOperand(0)); 548 if (!InputReg) 549 // Unhandled operand. Halt "fast" selection and bail. 550 return false; 551 552 // If the operand is i1, arrange for the high bits in the register to be zero. 553 if (SrcVT == MVT::i1) { 554 SrcVT = TLI.getTypeToTransformTo(SrcVT); 555 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 556 if (!InputReg) 557 return false; 558 } 559 // If the result is i1, truncate to the target's type for i1 first. 560 if (DstVT == MVT::i1) 561 DstVT = TLI.getTypeToTransformTo(DstVT); 562 563 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 564 DstVT.getSimpleVT(), 565 Opcode, 566 InputReg); 567 if (!ResultReg) 568 return false; 569 570 UpdateValueMap(I, ResultReg); 571 return true; 572} 573 574bool FastISel::SelectBitCast(User *I) { 575 // If the bitcast doesn't change the type, just use the operand value. 576 if (I->getType() == I->getOperand(0)->getType()) { 577 unsigned Reg = getRegForValue(I->getOperand(0)); 578 if (Reg == 0) 579 return false; 580 UpdateValueMap(I, Reg); 581 return true; 582 } 583 584 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 585 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 586 MVT DstVT = TLI.getValueType(I->getType()); 587 588 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 589 DstVT == MVT::Other || !DstVT.isSimple() || 590 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 591 // Unhandled type. Halt "fast" selection and bail. 592 return false; 593 594 unsigned Op0 = getRegForValue(I->getOperand(0)); 595 if (Op0 == 0) 596 // Unhandled operand. Halt "fast" selection and bail. 597 return false; 598 599 // First, try to perform the bitcast by inserting a reg-reg copy. 600 unsigned ResultReg = 0; 601 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 602 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 603 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 604 ResultReg = createResultReg(DstClass); 605 606 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 607 Op0, DstClass, SrcClass); 608 if (!InsertedCopy) 609 ResultReg = 0; 610 } 611 612 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 613 if (!ResultReg) 614 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 615 ISD::BIT_CONVERT, Op0); 616 617 if (!ResultReg) 618 return false; 619 620 UpdateValueMap(I, ResultReg); 621 return true; 622} 623 624bool 625FastISel::SelectInstruction(Instruction *I) { 626 return SelectOperator(I, I->getOpcode()); 627} 628 629/// FastEmitBranch - Emit an unconditional branch to the given block, 630/// unless it is the immediate (fall-through) successor, and update 631/// the CFG. 632void 633FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 634 MachineFunction::iterator NextMBB = 635 next(MachineFunction::iterator(MBB)); 636 637 if (MBB->isLayoutSuccessor(MSucc)) { 638 // The unconditional fall-through case, which needs no instructions. 639 } else { 640 // The unconditional branch case. 641 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 642 } 643 MBB->addSuccessor(MSucc); 644} 645 646bool 647FastISel::SelectOperator(User *I, unsigned Opcode) { 648 switch (Opcode) { 649 case Instruction::Add: { 650 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD; 651 return SelectBinaryOp(I, Opc); 652 } 653 case Instruction::Sub: { 654 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB; 655 return SelectBinaryOp(I, Opc); 656 } 657 case Instruction::Mul: { 658 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL; 659 return SelectBinaryOp(I, Opc); 660 } 661 case Instruction::SDiv: 662 return SelectBinaryOp(I, ISD::SDIV); 663 case Instruction::UDiv: 664 return SelectBinaryOp(I, ISD::UDIV); 665 case Instruction::FDiv: 666 return SelectBinaryOp(I, ISD::FDIV); 667 case Instruction::SRem: 668 return SelectBinaryOp(I, ISD::SREM); 669 case Instruction::URem: 670 return SelectBinaryOp(I, ISD::UREM); 671 case Instruction::FRem: 672 return SelectBinaryOp(I, ISD::FREM); 673 case Instruction::Shl: 674 return SelectBinaryOp(I, ISD::SHL); 675 case Instruction::LShr: 676 return SelectBinaryOp(I, ISD::SRL); 677 case Instruction::AShr: 678 return SelectBinaryOp(I, ISD::SRA); 679 case Instruction::And: 680 return SelectBinaryOp(I, ISD::AND); 681 case Instruction::Or: 682 return SelectBinaryOp(I, ISD::OR); 683 case Instruction::Xor: 684 return SelectBinaryOp(I, ISD::XOR); 685 686 case Instruction::GetElementPtr: 687 return SelectGetElementPtr(I); 688 689 case Instruction::Br: { 690 BranchInst *BI = cast<BranchInst>(I); 691 692 if (BI->isUnconditional()) { 693 BasicBlock *LLVMSucc = BI->getSuccessor(0); 694 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 695 FastEmitBranch(MSucc); 696 return true; 697 } 698 699 // Conditional branches are not handed yet. 700 // Halt "fast" selection and bail. 701 return false; 702 } 703 704 case Instruction::Unreachable: 705 // Nothing to emit. 706 return true; 707 708 case Instruction::PHI: 709 // PHI nodes are already emitted. 710 return true; 711 712 case Instruction::Alloca: 713 // FunctionLowering has the static-sized case covered. 714 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 715 return true; 716 717 // Dynamic-sized alloca is not handled yet. 718 return false; 719 720 case Instruction::Call: 721 return SelectCall(I); 722 723 case Instruction::BitCast: 724 return SelectBitCast(I); 725 726 case Instruction::FPToSI: 727 return SelectCast(I, ISD::FP_TO_SINT); 728 case Instruction::ZExt: 729 return SelectCast(I, ISD::ZERO_EXTEND); 730 case Instruction::SExt: 731 return SelectCast(I, ISD::SIGN_EXTEND); 732 case Instruction::Trunc: 733 return SelectCast(I, ISD::TRUNCATE); 734 case Instruction::SIToFP: 735 return SelectCast(I, ISD::SINT_TO_FP); 736 737 case Instruction::IntToPtr: // Deliberate fall-through. 738 case Instruction::PtrToInt: { 739 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 740 MVT DstVT = TLI.getValueType(I->getType()); 741 if (DstVT.bitsGT(SrcVT)) 742 return SelectCast(I, ISD::ZERO_EXTEND); 743 if (DstVT.bitsLT(SrcVT)) 744 return SelectCast(I, ISD::TRUNCATE); 745 unsigned Reg = getRegForValue(I->getOperand(0)); 746 if (Reg == 0) return false; 747 UpdateValueMap(I, Reg); 748 return true; 749 } 750 751 default: 752 // Unhandled instruction. Halt "fast" selection and bail. 753 return false; 754 } 755} 756 757FastISel::FastISel(MachineFunction &mf, 758 MachineModuleInfo *mmi, 759 DwarfWriter *dw, 760 DenseMap<const Value *, unsigned> &vm, 761 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 762 DenseMap<const AllocaInst *, int> &am 763#ifndef NDEBUG 764 , SmallSet<Instruction*, 8> &cil 765#endif 766 ) 767 : MBB(0), 768 ValueMap(vm), 769 MBBMap(bm), 770 StaticAllocaMap(am), 771#ifndef NDEBUG 772 CatchInfoLost(cil), 773#endif 774 MF(mf), 775 MMI(mmi), 776 DW(dw), 777 MRI(MF.getRegInfo()), 778 MFI(*MF.getFrameInfo()), 779 MCP(*MF.getConstantPool()), 780 TM(MF.getTarget()), 781 TD(*TM.getTargetData()), 782 TII(*TM.getInstrInfo()), 783 TLI(*TM.getTargetLowering()) { 784} 785 786FastISel::~FastISel() {} 787 788unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, 789 ISD::NodeType) { 790 return 0; 791} 792 793unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType, 794 ISD::NodeType, unsigned /*Op0*/) { 795 return 0; 796} 797 798unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, 799 ISD::NodeType, unsigned /*Op0*/, 800 unsigned /*Op0*/) { 801 return 0; 802} 803 804unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType, 805 ISD::NodeType, uint64_t /*Imm*/) { 806 return 0; 807} 808 809unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType, 810 ISD::NodeType, ConstantFP * /*FPImm*/) { 811 return 0; 812} 813 814unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType, 815 ISD::NodeType, unsigned /*Op0*/, 816 uint64_t /*Imm*/) { 817 return 0; 818} 819 820unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType, 821 ISD::NodeType, unsigned /*Op0*/, 822 ConstantFP * /*FPImm*/) { 823 return 0; 824} 825 826unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, 827 ISD::NodeType, 828 unsigned /*Op0*/, unsigned /*Op1*/, 829 uint64_t /*Imm*/) { 830 return 0; 831} 832 833/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 834/// to emit an instruction with an immediate operand using FastEmit_ri. 835/// If that fails, it materializes the immediate into a register and try 836/// FastEmit_rr instead. 837unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 838 unsigned Op0, uint64_t Imm, 839 MVT::SimpleValueType ImmType) { 840 // First check if immediate type is legal. If not, we can't use the ri form. 841 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 842 if (ResultReg != 0) 843 return ResultReg; 844 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 845 if (MaterialReg == 0) 846 return 0; 847 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 848} 849 850/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 851/// to emit an instruction with a floating-point immediate operand using 852/// FastEmit_rf. If that fails, it materializes the immediate into a register 853/// and try FastEmit_rr instead. 854unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 855 unsigned Op0, ConstantFP *FPImm, 856 MVT::SimpleValueType ImmType) { 857 // First check if immediate type is legal. If not, we can't use the rf form. 858 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 859 if (ResultReg != 0) 860 return ResultReg; 861 862 // Materialize the constant in a register. 863 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 864 if (MaterialReg == 0) { 865 // If the target doesn't have a way to directly enter a floating-point 866 // value into a register, use an alternate approach. 867 // TODO: The current approach only supports floating-point constants 868 // that can be constructed by conversion from integer values. This should 869 // be replaced by code that creates a load from a constant-pool entry, 870 // which will require some target-specific work. 871 const APFloat &Flt = FPImm->getValueAPF(); 872 MVT IntVT = TLI.getPointerTy(); 873 874 uint64_t x[2]; 875 uint32_t IntBitWidth = IntVT.getSizeInBits(); 876 bool isExact; 877 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 878 APFloat::rmTowardZero, &isExact); 879 if (!isExact) 880 return 0; 881 APInt IntVal(IntBitWidth, 2, x); 882 883 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 884 ISD::Constant, IntVal.getZExtValue()); 885 if (IntegerReg == 0) 886 return 0; 887 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 888 ISD::SINT_TO_FP, IntegerReg); 889 if (MaterialReg == 0) 890 return 0; 891 } 892 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 893} 894 895unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 896 return MRI.createVirtualRegister(RC); 897} 898 899unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 900 const TargetRegisterClass* RC) { 901 unsigned ResultReg = createResultReg(RC); 902 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 903 904 BuildMI(MBB, DL, II, ResultReg); 905 return ResultReg; 906} 907 908unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 909 const TargetRegisterClass *RC, 910 unsigned Op0) { 911 unsigned ResultReg = createResultReg(RC); 912 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 913 914 if (II.getNumDefs() >= 1) 915 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 916 else { 917 BuildMI(MBB, DL, II).addReg(Op0); 918 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 919 II.ImplicitDefs[0], RC, RC); 920 if (!InsertedCopy) 921 ResultReg = 0; 922 } 923 924 return ResultReg; 925} 926 927unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 928 const TargetRegisterClass *RC, 929 unsigned Op0, unsigned Op1) { 930 unsigned ResultReg = createResultReg(RC); 931 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 932 933 if (II.getNumDefs() >= 1) 934 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 935 else { 936 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 937 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 938 II.ImplicitDefs[0], RC, RC); 939 if (!InsertedCopy) 940 ResultReg = 0; 941 } 942 return ResultReg; 943} 944 945unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 946 const TargetRegisterClass *RC, 947 unsigned Op0, uint64_t Imm) { 948 unsigned ResultReg = createResultReg(RC); 949 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 950 951 if (II.getNumDefs() >= 1) 952 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 953 else { 954 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 955 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 956 II.ImplicitDefs[0], RC, RC); 957 if (!InsertedCopy) 958 ResultReg = 0; 959 } 960 return ResultReg; 961} 962 963unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 964 const TargetRegisterClass *RC, 965 unsigned Op0, ConstantFP *FPImm) { 966 unsigned ResultReg = createResultReg(RC); 967 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 968 969 if (II.getNumDefs() >= 1) 970 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 971 else { 972 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 973 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 974 II.ImplicitDefs[0], RC, RC); 975 if (!InsertedCopy) 976 ResultReg = 0; 977 } 978 return ResultReg; 979} 980 981unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 982 const TargetRegisterClass *RC, 983 unsigned Op0, unsigned Op1, uint64_t Imm) { 984 unsigned ResultReg = createResultReg(RC); 985 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 986 987 if (II.getNumDefs() >= 1) 988 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 989 else { 990 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 991 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 992 II.ImplicitDefs[0], RC, RC); 993 if (!InsertedCopy) 994 ResultReg = 0; 995 } 996 return ResultReg; 997} 998 999unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 1000 const TargetRegisterClass *RC, 1001 uint64_t Imm) { 1002 unsigned ResultReg = createResultReg(RC); 1003 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1004 1005 if (II.getNumDefs() >= 1) 1006 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 1007 else { 1008 BuildMI(MBB, DL, II).addImm(Imm); 1009 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1010 II.ImplicitDefs[0], RC, RC); 1011 if (!InsertedCopy) 1012 ResultReg = 0; 1013 } 1014 return ResultReg; 1015} 1016 1017unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT, 1018 unsigned Op0, uint32_t Idx) { 1019 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 1020 1021 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1022 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); 1023 1024 if (II.getNumDefs() >= 1) 1025 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 1026 else { 1027 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 1028 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1029 II.ImplicitDefs[0], RC, RC); 1030 if (!InsertedCopy) 1031 ResultReg = 0; 1032 } 1033 return ResultReg; 1034} 1035 1036/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1037/// with all but the least significant bit set to zero. 1038unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) { 1039 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 1040} 1041