FastISel.cpp revision c5040ab6065d5c569a1af0848b6e672b22b174b7
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/CodeGen/DwarfWriter.h" 51#include "llvm/Analysis/DebugInfo.h" 52#include "llvm/Target/TargetData.h" 53#include "llvm/Target/TargetInstrInfo.h" 54#include "llvm/Target/TargetLowering.h" 55#include "llvm/Target/TargetMachine.h" 56#include "SelectionDAGBuild.h" 57using namespace llvm; 58 59unsigned FastISel::getRegForValue(Value *V) { 60 MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 61 // Don't handle non-simple values in FastISel. 62 if (!RealVT.isSimple()) 63 return 0; 64 65 // Ignore illegal types. We must do this before looking up the value 66 // in ValueMap because Arguments are given virtual registers regardless 67 // of whether FastISel can handle them. 68 MVT::SimpleValueType VT = RealVT.getSimpleVT(); 69 if (!TLI.isTypeLegal(VT)) { 70 // Promote MVT::i1 to a legal type though, because it's common and easy. 71 if (VT == MVT::i1) 72 VT = TLI.getTypeToTransformTo(VT).getSimpleVT(); 73 else 74 return 0; 75 } 76 77 // Look up the value to see if we already have a register for it. We 78 // cache values defined by Instructions across blocks, and other values 79 // only locally. This is because Instructions already have the SSA 80 // def-dominatess-use requirement enforced. 81 if (ValueMap.count(V)) 82 return ValueMap[V]; 83 unsigned Reg = LocalValueMap[V]; 84 if (Reg != 0) 85 return Reg; 86 87 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 88 if (CI->getValue().getActiveBits() <= 64) 89 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 90 } else if (isa<AllocaInst>(V)) { 91 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 92 } else if (isa<ConstantPointerNull>(V)) { 93 // Translate this as an integer zero so that it can be 94 // local-CSE'd with actual integer zeros. 95 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType())); 96 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 97 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 98 99 if (!Reg) { 100 const APFloat &Flt = CF->getValueAPF(); 101 MVT IntVT = TLI.getPointerTy(); 102 103 uint64_t x[2]; 104 uint32_t IntBitWidth = IntVT.getSizeInBits(); 105 bool isExact; 106 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 107 APFloat::rmTowardZero, &isExact); 108 if (isExact) { 109 APInt IntVal(IntBitWidth, 2, x); 110 111 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal)); 112 if (IntegerReg != 0) 113 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 114 } 115 } 116 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 117 if (!SelectOperator(CE, CE->getOpcode())) return 0; 118 Reg = LocalValueMap[CE]; 119 } else if (isa<UndefValue>(V)) { 120 Reg = createResultReg(TLI.getRegClassFor(VT)); 121 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); 122 } 123 124 // If target-independent code couldn't handle the value, give target-specific 125 // code a try. 126 if (!Reg && isa<Constant>(V)) 127 Reg = TargetMaterializeConstant(cast<Constant>(V)); 128 129 // Don't cache constant materializations in the general ValueMap. 130 // To do so would require tracking what uses they dominate. 131 if (Reg != 0) 132 LocalValueMap[V] = Reg; 133 return Reg; 134} 135 136unsigned FastISel::lookUpRegForValue(Value *V) { 137 // Look up the value to see if we already have a register for it. We 138 // cache values defined by Instructions across blocks, and other values 139 // only locally. This is because Instructions already have the SSA 140 // def-dominatess-use requirement enforced. 141 if (ValueMap.count(V)) 142 return ValueMap[V]; 143 return LocalValueMap[V]; 144} 145 146/// UpdateValueMap - Update the value map to include the new mapping for this 147/// instruction, or insert an extra copy to get the result in a previous 148/// determined register. 149/// NOTE: This is only necessary because we might select a block that uses 150/// a value before we select the block that defines the value. It might be 151/// possible to fix this by selecting blocks in reverse postorder. 152unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) { 153 if (!isa<Instruction>(I)) { 154 LocalValueMap[I] = Reg; 155 return Reg; 156 } 157 158 unsigned &AssignedReg = ValueMap[I]; 159 if (AssignedReg == 0) 160 AssignedReg = Reg; 161 else { 162 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); 163 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg, 164 Reg, RegClass, RegClass); 165 } 166 return AssignedReg; 167} 168 169unsigned FastISel::getRegForGEPIndex(Value *Idx) { 170 unsigned IdxN = getRegForValue(Idx); 171 if (IdxN == 0) 172 // Unhandled operand. Halt "fast" selection and bail. 173 return 0; 174 175 // If the index is smaller or larger than intptr_t, truncate or extend it. 176 MVT PtrVT = TLI.getPointerTy(); 177 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); 178 if (IdxVT.bitsLT(PtrVT)) 179 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 180 ISD::SIGN_EXTEND, IdxN); 181 else if (IdxVT.bitsGT(PtrVT)) 182 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 183 ISD::TRUNCATE, IdxN); 184 return IdxN; 185} 186 187/// SelectBinaryOp - Select and emit code for a binary operator instruction, 188/// which has an opcode which directly corresponds to the given ISD opcode. 189/// 190bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { 191 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); 192 if (VT == MVT::Other || !VT.isSimple()) 193 // Unhandled type. Halt "fast" selection and bail. 194 return false; 195 196 // We only handle legal types. For example, on x86-32 the instruction 197 // selector contains all of the 64-bit instructions from x86-64, 198 // under the assumption that i64 won't be used if the target doesn't 199 // support it. 200 if (!TLI.isTypeLegal(VT)) { 201 // MVT::i1 is special. Allow AND, OR, or XOR because they 202 // don't require additional zeroing, which makes them easy. 203 if (VT == MVT::i1 && 204 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 205 ISDOpcode == ISD::XOR)) 206 VT = TLI.getTypeToTransformTo(VT); 207 else 208 return false; 209 } 210 211 unsigned Op0 = getRegForValue(I->getOperand(0)); 212 if (Op0 == 0) 213 // Unhandled operand. Halt "fast" selection and bail. 214 return false; 215 216 // Check if the second operand is a constant and handle it appropriately. 217 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 218 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 219 ISDOpcode, Op0, CI->getZExtValue()); 220 if (ResultReg != 0) { 221 // We successfully emitted code for the given LLVM Instruction. 222 UpdateValueMap(I, ResultReg); 223 return true; 224 } 225 } 226 227 // Check if the second operand is a constant float. 228 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 229 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 230 ISDOpcode, Op0, CF); 231 if (ResultReg != 0) { 232 // We successfully emitted code for the given LLVM Instruction. 233 UpdateValueMap(I, ResultReg); 234 return true; 235 } 236 } 237 238 unsigned Op1 = getRegForValue(I->getOperand(1)); 239 if (Op1 == 0) 240 // Unhandled operand. Halt "fast" selection and bail. 241 return false; 242 243 // Now we have both operands in registers. Emit the instruction. 244 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 245 ISDOpcode, Op0, Op1); 246 if (ResultReg == 0) 247 // Target-specific code wasn't able to find a machine opcode for 248 // the given ISD opcode and type. Halt "fast" selection and bail. 249 return false; 250 251 // We successfully emitted code for the given LLVM Instruction. 252 UpdateValueMap(I, ResultReg); 253 return true; 254} 255 256bool FastISel::SelectGetElementPtr(User *I) { 257 unsigned N = getRegForValue(I->getOperand(0)); 258 if (N == 0) 259 // Unhandled operand. Halt "fast" selection and bail. 260 return false; 261 262 const Type *Ty = I->getOperand(0)->getType(); 263 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT(); 264 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 265 OI != E; ++OI) { 266 Value *Idx = *OI; 267 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 268 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 269 if (Field) { 270 // N = N + Offset 271 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 272 // FIXME: This can be optimized by combining the add with a 273 // subsequent one. 274 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 275 if (N == 0) 276 // Unhandled operand. Halt "fast" selection and bail. 277 return false; 278 } 279 Ty = StTy->getElementType(Field); 280 } else { 281 Ty = cast<SequentialType>(Ty)->getElementType(); 282 283 // If this is a constant subscript, handle it quickly. 284 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 285 if (CI->getZExtValue() == 0) continue; 286 uint64_t Offs = 287 TD.getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 288 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 289 if (N == 0) 290 // Unhandled operand. Halt "fast" selection and bail. 291 return false; 292 continue; 293 } 294 295 // N = N + Idx * ElementSize; 296 uint64_t ElementSize = TD.getTypePaddedSize(Ty); 297 unsigned IdxN = getRegForGEPIndex(Idx); 298 if (IdxN == 0) 299 // Unhandled operand. Halt "fast" selection and bail. 300 return false; 301 302 if (ElementSize != 1) { 303 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 304 if (IdxN == 0) 305 // Unhandled operand. Halt "fast" selection and bail. 306 return false; 307 } 308 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 309 if (N == 0) 310 // Unhandled operand. Halt "fast" selection and bail. 311 return false; 312 } 313 } 314 315 // We successfully emitted code for the given LLVM Instruction. 316 UpdateValueMap(I, N); 317 return true; 318} 319 320bool FastISel::SelectCall(User *I) { 321 Function *F = cast<CallInst>(I)->getCalledFunction(); 322 if (!F) return false; 323 324 unsigned IID = F->getIntrinsicID(); 325 switch (IID) { 326 default: break; 327 case Intrinsic::dbg_stoppoint: { 328 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); 329 if (DW && DW->ValidDebugInfo(SPI->getContext())) { 330 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext())); 331 std::string Dir, FN; 332 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir), 333 CU.getFilename(FN)); 334 unsigned Line = SPI->getLine(); 335 unsigned Col = SPI->getColumn(); 336 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); 337 unsigned Idx = MF.getOrCreateDebugLocID(SrcFile, Line, Col); 338 setCurDebugLoc(DebugLoc::get(Idx)); 339 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 340 BuildMI(MBB, DL, II).addImm(ID); 341 } 342 return true; 343 } 344 case Intrinsic::dbg_region_start: { 345 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I); 346 if (DW && DW->ValidDebugInfo(RSI->getContext())) { 347 unsigned ID = 348 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext())); 349 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 350 BuildMI(MBB, DL, II).addImm(ID); 351 } 352 return true; 353 } 354 case Intrinsic::dbg_region_end: { 355 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I); 356 if (DW && DW->ValidDebugInfo(REI->getContext())) { 357 unsigned ID = 358 DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext())); 359 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 360 BuildMI(MBB, DL, II).addImm(ID); 361 } 362 return true; 363 } 364 case Intrinsic::dbg_func_start: { 365 if (!DW) return true; 366 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); 367 Value *SP = FSI->getSubprogram(); 368 369 if (DW->ValidDebugInfo(SP)) { 370 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what 371 // (most?) gdb expects. 372 DISubprogram Subprogram(cast<GlobalVariable>(SP)); 373 DICompileUnit CompileUnit = Subprogram.getCompileUnit(); 374 std::string Dir, FN; 375 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir), 376 CompileUnit.getFilename(FN)); 377 378 // Record the source line. 379 unsigned Line = Subprogram.getLineNumber(); 380 DW->RecordSourceLine(Line, 0, SrcFile); 381 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0))); 382 383 // llvm.dbg.func_start also defines beginning of function scope. 384 DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram())); 385 } 386 387 return true; 388 } 389 case Intrinsic::dbg_declare: { 390 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 391 Value *Variable = DI->getVariable(); 392 if (DW && DW->ValidDebugInfo(Variable)) { 393 // Determine the address of the declared object. 394 Value *Address = DI->getAddress(); 395 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 396 Address = BCI->getOperand(0); 397 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 398 // Don't handle byval struct arguments or VLAs, for example. 399 if (!AI) break; 400 DenseMap<const AllocaInst*, int>::iterator SI = 401 StaticAllocaMap.find(AI); 402 if (SI == StaticAllocaMap.end()) break; // VLAs. 403 int FI = SI->second; 404 405 // Determine the debug globalvariable. 406 GlobalValue *GV = cast<GlobalVariable>(Variable); 407 408 // Build the DECLARE instruction. 409 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE); 410 BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV); 411 } 412 return true; 413 } 414 case Intrinsic::eh_exception: { 415 MVT VT = TLI.getValueType(I->getType()); 416 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 417 default: break; 418 case TargetLowering::Expand: { 419 if (!MBB->isLandingPad()) { 420 // FIXME: Mark exception register as live in. Hack for PR1508. 421 unsigned Reg = TLI.getExceptionAddressRegister(); 422 if (Reg) MBB->addLiveIn(Reg); 423 } 424 unsigned Reg = TLI.getExceptionAddressRegister(); 425 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 426 unsigned ResultReg = createResultReg(RC); 427 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 428 Reg, RC, RC); 429 assert(InsertedCopy && "Can't copy address registers!"); 430 InsertedCopy = InsertedCopy; 431 UpdateValueMap(I, ResultReg); 432 return true; 433 } 434 } 435 break; 436 } 437 case Intrinsic::eh_selector_i32: 438 case Intrinsic::eh_selector_i64: { 439 MVT VT = TLI.getValueType(I->getType()); 440 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 441 default: break; 442 case TargetLowering::Expand: { 443 MVT VT = (IID == Intrinsic::eh_selector_i32 ? 444 MVT::i32 : MVT::i64); 445 446 if (MMI) { 447 if (MBB->isLandingPad()) 448 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 449 else { 450#ifndef NDEBUG 451 CatchInfoLost.insert(cast<CallInst>(I)); 452#endif 453 // FIXME: Mark exception selector register as live in. Hack for PR1508. 454 unsigned Reg = TLI.getExceptionSelectorRegister(); 455 if (Reg) MBB->addLiveIn(Reg); 456 } 457 458 unsigned Reg = TLI.getExceptionSelectorRegister(); 459 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 460 unsigned ResultReg = createResultReg(RC); 461 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 462 Reg, RC, RC); 463 assert(InsertedCopy && "Can't copy address registers!"); 464 InsertedCopy = InsertedCopy; 465 UpdateValueMap(I, ResultReg); 466 } else { 467 unsigned ResultReg = 468 getRegForValue(Constant::getNullValue(I->getType())); 469 UpdateValueMap(I, ResultReg); 470 } 471 return true; 472 } 473 } 474 break; 475 } 476 } 477 return false; 478} 479 480bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { 481 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 482 MVT DstVT = TLI.getValueType(I->getType()); 483 484 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 485 DstVT == MVT::Other || !DstVT.isSimple()) 486 // Unhandled type. Halt "fast" selection and bail. 487 return false; 488 489 // Check if the destination type is legal. Or as a special case, 490 // it may be i1 if we're doing a truncate because that's 491 // easy and somewhat common. 492 if (!TLI.isTypeLegal(DstVT)) 493 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 494 // Unhandled type. Halt "fast" selection and bail. 495 return false; 496 497 // Check if the source operand is legal. Or as a special case, 498 // it may be i1 if we're doing zero-extension because that's 499 // easy and somewhat common. 500 if (!TLI.isTypeLegal(SrcVT)) 501 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 502 // Unhandled type. Halt "fast" selection and bail. 503 return false; 504 505 unsigned InputReg = getRegForValue(I->getOperand(0)); 506 if (!InputReg) 507 // Unhandled operand. Halt "fast" selection and bail. 508 return false; 509 510 // If the operand is i1, arrange for the high bits in the register to be zero. 511 if (SrcVT == MVT::i1) { 512 SrcVT = TLI.getTypeToTransformTo(SrcVT); 513 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 514 if (!InputReg) 515 return false; 516 } 517 // If the result is i1, truncate to the target's type for i1 first. 518 if (DstVT == MVT::i1) 519 DstVT = TLI.getTypeToTransformTo(DstVT); 520 521 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 522 DstVT.getSimpleVT(), 523 Opcode, 524 InputReg); 525 if (!ResultReg) 526 return false; 527 528 UpdateValueMap(I, ResultReg); 529 return true; 530} 531 532bool FastISel::SelectBitCast(User *I) { 533 // If the bitcast doesn't change the type, just use the operand value. 534 if (I->getType() == I->getOperand(0)->getType()) { 535 unsigned Reg = getRegForValue(I->getOperand(0)); 536 if (Reg == 0) 537 return false; 538 UpdateValueMap(I, Reg); 539 return true; 540 } 541 542 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 543 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 544 MVT DstVT = TLI.getValueType(I->getType()); 545 546 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 547 DstVT == MVT::Other || !DstVT.isSimple() || 548 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 549 // Unhandled type. Halt "fast" selection and bail. 550 return false; 551 552 unsigned Op0 = getRegForValue(I->getOperand(0)); 553 if (Op0 == 0) 554 // Unhandled operand. Halt "fast" selection and bail. 555 return false; 556 557 // First, try to perform the bitcast by inserting a reg-reg copy. 558 unsigned ResultReg = 0; 559 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 560 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 561 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 562 ResultReg = createResultReg(DstClass); 563 564 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 565 Op0, DstClass, SrcClass); 566 if (!InsertedCopy) 567 ResultReg = 0; 568 } 569 570 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 571 if (!ResultReg) 572 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 573 ISD::BIT_CONVERT, Op0); 574 575 if (!ResultReg) 576 return false; 577 578 UpdateValueMap(I, ResultReg); 579 return true; 580} 581 582bool 583FastISel::SelectInstruction(Instruction *I) { 584 return SelectOperator(I, I->getOpcode()); 585} 586 587/// FastEmitBranch - Emit an unconditional branch to the given block, 588/// unless it is the immediate (fall-through) successor, and update 589/// the CFG. 590void 591FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 592 MachineFunction::iterator NextMBB = 593 next(MachineFunction::iterator(MBB)); 594 595 if (MBB->isLayoutSuccessor(MSucc)) { 596 // The unconditional fall-through case, which needs no instructions. 597 } else { 598 // The unconditional branch case. 599 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 600 } 601 MBB->addSuccessor(MSucc); 602} 603 604bool 605FastISel::SelectOperator(User *I, unsigned Opcode) { 606 switch (Opcode) { 607 case Instruction::Add: { 608 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD; 609 return SelectBinaryOp(I, Opc); 610 } 611 case Instruction::Sub: { 612 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB; 613 return SelectBinaryOp(I, Opc); 614 } 615 case Instruction::Mul: { 616 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL; 617 return SelectBinaryOp(I, Opc); 618 } 619 case Instruction::SDiv: 620 return SelectBinaryOp(I, ISD::SDIV); 621 case Instruction::UDiv: 622 return SelectBinaryOp(I, ISD::UDIV); 623 case Instruction::FDiv: 624 return SelectBinaryOp(I, ISD::FDIV); 625 case Instruction::SRem: 626 return SelectBinaryOp(I, ISD::SREM); 627 case Instruction::URem: 628 return SelectBinaryOp(I, ISD::UREM); 629 case Instruction::FRem: 630 return SelectBinaryOp(I, ISD::FREM); 631 case Instruction::Shl: 632 return SelectBinaryOp(I, ISD::SHL); 633 case Instruction::LShr: 634 return SelectBinaryOp(I, ISD::SRL); 635 case Instruction::AShr: 636 return SelectBinaryOp(I, ISD::SRA); 637 case Instruction::And: 638 return SelectBinaryOp(I, ISD::AND); 639 case Instruction::Or: 640 return SelectBinaryOp(I, ISD::OR); 641 case Instruction::Xor: 642 return SelectBinaryOp(I, ISD::XOR); 643 644 case Instruction::GetElementPtr: 645 return SelectGetElementPtr(I); 646 647 case Instruction::Br: { 648 BranchInst *BI = cast<BranchInst>(I); 649 650 if (BI->isUnconditional()) { 651 BasicBlock *LLVMSucc = BI->getSuccessor(0); 652 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 653 FastEmitBranch(MSucc); 654 return true; 655 } 656 657 // Conditional branches are not handed yet. 658 // Halt "fast" selection and bail. 659 return false; 660 } 661 662 case Instruction::Unreachable: 663 // Nothing to emit. 664 return true; 665 666 case Instruction::PHI: 667 // PHI nodes are already emitted. 668 return true; 669 670 case Instruction::Alloca: 671 // FunctionLowering has the static-sized case covered. 672 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 673 return true; 674 675 // Dynamic-sized alloca is not handled yet. 676 return false; 677 678 case Instruction::Call: 679 return SelectCall(I); 680 681 case Instruction::BitCast: 682 return SelectBitCast(I); 683 684 case Instruction::FPToSI: 685 return SelectCast(I, ISD::FP_TO_SINT); 686 case Instruction::ZExt: 687 return SelectCast(I, ISD::ZERO_EXTEND); 688 case Instruction::SExt: 689 return SelectCast(I, ISD::SIGN_EXTEND); 690 case Instruction::Trunc: 691 return SelectCast(I, ISD::TRUNCATE); 692 case Instruction::SIToFP: 693 return SelectCast(I, ISD::SINT_TO_FP); 694 695 case Instruction::IntToPtr: // Deliberate fall-through. 696 case Instruction::PtrToInt: { 697 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 698 MVT DstVT = TLI.getValueType(I->getType()); 699 if (DstVT.bitsGT(SrcVT)) 700 return SelectCast(I, ISD::ZERO_EXTEND); 701 if (DstVT.bitsLT(SrcVT)) 702 return SelectCast(I, ISD::TRUNCATE); 703 unsigned Reg = getRegForValue(I->getOperand(0)); 704 if (Reg == 0) return false; 705 UpdateValueMap(I, Reg); 706 return true; 707 } 708 709 default: 710 // Unhandled instruction. Halt "fast" selection and bail. 711 return false; 712 } 713} 714 715FastISel::FastISel(MachineFunction &mf, 716 MachineModuleInfo *mmi, 717 DwarfWriter *dw, 718 DenseMap<const Value *, unsigned> &vm, 719 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 720 DenseMap<const AllocaInst *, int> &am 721#ifndef NDEBUG 722 , SmallSet<Instruction*, 8> &cil 723#endif 724 ) 725 : MBB(0), 726 ValueMap(vm), 727 MBBMap(bm), 728 StaticAllocaMap(am), 729#ifndef NDEBUG 730 CatchInfoLost(cil), 731#endif 732 MF(mf), 733 MMI(mmi), 734 DW(dw), 735 MRI(MF.getRegInfo()), 736 MFI(*MF.getFrameInfo()), 737 MCP(*MF.getConstantPool()), 738 TM(MF.getTarget()), 739 TD(*TM.getTargetData()), 740 TII(*TM.getInstrInfo()), 741 TLI(*TM.getTargetLowering()) { 742} 743 744FastISel::~FastISel() {} 745 746unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, 747 ISD::NodeType) { 748 return 0; 749} 750 751unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType, 752 ISD::NodeType, unsigned /*Op0*/) { 753 return 0; 754} 755 756unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, 757 ISD::NodeType, unsigned /*Op0*/, 758 unsigned /*Op0*/) { 759 return 0; 760} 761 762unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType, 763 ISD::NodeType, uint64_t /*Imm*/) { 764 return 0; 765} 766 767unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType, 768 ISD::NodeType, ConstantFP * /*FPImm*/) { 769 return 0; 770} 771 772unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType, 773 ISD::NodeType, unsigned /*Op0*/, 774 uint64_t /*Imm*/) { 775 return 0; 776} 777 778unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType, 779 ISD::NodeType, unsigned /*Op0*/, 780 ConstantFP * /*FPImm*/) { 781 return 0; 782} 783 784unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, 785 ISD::NodeType, 786 unsigned /*Op0*/, unsigned /*Op1*/, 787 uint64_t /*Imm*/) { 788 return 0; 789} 790 791/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 792/// to emit an instruction with an immediate operand using FastEmit_ri. 793/// If that fails, it materializes the immediate into a register and try 794/// FastEmit_rr instead. 795unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 796 unsigned Op0, uint64_t Imm, 797 MVT::SimpleValueType ImmType) { 798 // First check if immediate type is legal. If not, we can't use the ri form. 799 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 800 if (ResultReg != 0) 801 return ResultReg; 802 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 803 if (MaterialReg == 0) 804 return 0; 805 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 806} 807 808/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 809/// to emit an instruction with a floating-point immediate operand using 810/// FastEmit_rf. If that fails, it materializes the immediate into a register 811/// and try FastEmit_rr instead. 812unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 813 unsigned Op0, ConstantFP *FPImm, 814 MVT::SimpleValueType ImmType) { 815 // First check if immediate type is legal. If not, we can't use the rf form. 816 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 817 if (ResultReg != 0) 818 return ResultReg; 819 820 // Materialize the constant in a register. 821 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 822 if (MaterialReg == 0) { 823 // If the target doesn't have a way to directly enter a floating-point 824 // value into a register, use an alternate approach. 825 // TODO: The current approach only supports floating-point constants 826 // that can be constructed by conversion from integer values. This should 827 // be replaced by code that creates a load from a constant-pool entry, 828 // which will require some target-specific work. 829 const APFloat &Flt = FPImm->getValueAPF(); 830 MVT IntVT = TLI.getPointerTy(); 831 832 uint64_t x[2]; 833 uint32_t IntBitWidth = IntVT.getSizeInBits(); 834 bool isExact; 835 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 836 APFloat::rmTowardZero, &isExact); 837 if (!isExact) 838 return 0; 839 APInt IntVal(IntBitWidth, 2, x); 840 841 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 842 ISD::Constant, IntVal.getZExtValue()); 843 if (IntegerReg == 0) 844 return 0; 845 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 846 ISD::SINT_TO_FP, IntegerReg); 847 if (MaterialReg == 0) 848 return 0; 849 } 850 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 851} 852 853unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 854 return MRI.createVirtualRegister(RC); 855} 856 857unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 858 const TargetRegisterClass* RC) { 859 unsigned ResultReg = createResultReg(RC); 860 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 861 862 BuildMI(MBB, DL, II, ResultReg); 863 return ResultReg; 864} 865 866unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 867 const TargetRegisterClass *RC, 868 unsigned Op0) { 869 unsigned ResultReg = createResultReg(RC); 870 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 871 872 if (II.getNumDefs() >= 1) 873 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 874 else { 875 BuildMI(MBB, DL, II).addReg(Op0); 876 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 877 II.ImplicitDefs[0], RC, RC); 878 if (!InsertedCopy) 879 ResultReg = 0; 880 } 881 882 return ResultReg; 883} 884 885unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 886 const TargetRegisterClass *RC, 887 unsigned Op0, unsigned Op1) { 888 unsigned ResultReg = createResultReg(RC); 889 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 890 891 if (II.getNumDefs() >= 1) 892 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 893 else { 894 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 895 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 896 II.ImplicitDefs[0], RC, RC); 897 if (!InsertedCopy) 898 ResultReg = 0; 899 } 900 return ResultReg; 901} 902 903unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 904 const TargetRegisterClass *RC, 905 unsigned Op0, uint64_t Imm) { 906 unsigned ResultReg = createResultReg(RC); 907 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 908 909 if (II.getNumDefs() >= 1) 910 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 911 else { 912 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 913 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 914 II.ImplicitDefs[0], RC, RC); 915 if (!InsertedCopy) 916 ResultReg = 0; 917 } 918 return ResultReg; 919} 920 921unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 922 const TargetRegisterClass *RC, 923 unsigned Op0, ConstantFP *FPImm) { 924 unsigned ResultReg = createResultReg(RC); 925 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 926 927 if (II.getNumDefs() >= 1) 928 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 929 else { 930 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 931 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 932 II.ImplicitDefs[0], RC, RC); 933 if (!InsertedCopy) 934 ResultReg = 0; 935 } 936 return ResultReg; 937} 938 939unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 940 const TargetRegisterClass *RC, 941 unsigned Op0, unsigned Op1, uint64_t Imm) { 942 unsigned ResultReg = createResultReg(RC); 943 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 944 945 if (II.getNumDefs() >= 1) 946 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 947 else { 948 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 949 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 950 II.ImplicitDefs[0], RC, RC); 951 if (!InsertedCopy) 952 ResultReg = 0; 953 } 954 return ResultReg; 955} 956 957unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 958 const TargetRegisterClass *RC, 959 uint64_t Imm) { 960 unsigned ResultReg = createResultReg(RC); 961 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 962 963 if (II.getNumDefs() >= 1) 964 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 965 else { 966 BuildMI(MBB, DL, II).addImm(Imm); 967 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 968 II.ImplicitDefs[0], RC, RC); 969 if (!InsertedCopy) 970 ResultReg = 0; 971 } 972 return ResultReg; 973} 974 975unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT, 976 unsigned Op0, uint32_t Idx) { 977 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 978 979 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 980 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); 981 982 if (II.getNumDefs() >= 1) 983 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 984 else { 985 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 986 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 987 II.ImplicitDefs[0], RC, RC); 988 if (!InsertedCopy) 989 ResultReg = 0; 990 } 991 return ResultReg; 992} 993 994/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 995/// with all but the least significant bit set to zero. 996unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) { 997 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 998} 999