FastISel.cpp revision da8e3ccd1b8cf437ce008849bf877bdb3a5090be
1//===-- FastISel.cpp - Implementation of the FastISel class ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/FunctionLoweringInfo.h" 48#include "llvm/CodeGen/MachineInstrBuilder.h" 49#include "llvm/CodeGen/MachineModuleInfo.h" 50#include "llvm/CodeGen/MachineRegisterInfo.h" 51#include "llvm/Analysis/DebugInfo.h" 52#include "llvm/Analysis/Loads.h" 53#include "llvm/Target/TargetData.h" 54#include "llvm/Target/TargetInstrInfo.h" 55#include "llvm/Target/TargetLowering.h" 56#include "llvm/Target/TargetMachine.h" 57#include "llvm/Support/ErrorHandling.h" 58using namespace llvm; 59 60/// startNewBlock - Set the current block to which generated machine 61/// instructions will be appended, and clear the local CSE map. 62/// 63void FastISel::startNewBlock() { 64 LocalValueMap.clear(); 65 66 // Start out as null, meaining no local-value instructions have 67 // been emitted. 68 LastLocalValue = 0; 69 70 // Advance the last local value past any EH_LABEL instructions. 71 MachineBasicBlock::iterator 72 I = FuncInfo.MBB->begin(), E = FuncInfo.MBB->end(); 73 while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) { 74 LastLocalValue = I; 75 ++I; 76 } 77} 78 79bool FastISel::hasTrivialKill(const Value *V) const { 80 // Don't consider constants or arguments to have trivial kills. 81 const Instruction *I = dyn_cast<Instruction>(V); 82 if (!I) 83 return false; 84 85 // No-op casts are trivially coalesced by fast-isel. 86 if (const CastInst *Cast = dyn_cast<CastInst>(I)) 87 if (Cast->isNoopCast(TD.getIntPtrType(Cast->getContext())) && 88 !hasTrivialKill(Cast->getOperand(0))) 89 return false; 90 91 // Only instructions with a single use in the same basic block are considered 92 // to have trivial kills. 93 return I->hasOneUse() && 94 !(I->getOpcode() == Instruction::BitCast || 95 I->getOpcode() == Instruction::PtrToInt || 96 I->getOpcode() == Instruction::IntToPtr) && 97 cast<Instruction>(I->use_begin())->getParent() == I->getParent(); 98} 99 100unsigned FastISel::getRegForValue(const Value *V) { 101 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 102 // Don't handle non-simple values in FastISel. 103 if (!RealVT.isSimple()) 104 return 0; 105 106 // Ignore illegal types. We must do this before looking up the value 107 // in ValueMap because Arguments are given virtual registers regardless 108 // of whether FastISel can handle them. 109 MVT VT = RealVT.getSimpleVT(); 110 if (!TLI.isTypeLegal(VT)) { 111 // Promote MVT::i1 to a legal type though, because it's common and easy. 112 if (VT == MVT::i1) 113 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); 114 else 115 return 0; 116 } 117 118 // Look up the value to see if we already have a register for it. We 119 // cache values defined by Instructions across blocks, and other values 120 // only locally. This is because Instructions already have the SSA 121 // def-dominates-use requirement enforced. 122 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V); 123 if (I != FuncInfo.ValueMap.end()) { 124 unsigned Reg = I->second; 125 return Reg; 126 } 127 unsigned Reg = LocalValueMap[V]; 128 if (Reg != 0) 129 return Reg; 130 131 // In bottom-up mode, just create the virtual register which will be used 132 // to hold the value. It will be materialized later. 133 if (isa<Instruction>(V) && 134 (!isa<AllocaInst>(V) || 135 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V)))) 136 return FuncInfo.InitializeRegForValue(V); 137 138 MachineBasicBlock::iterator SaveInsertPt = enterLocalValueArea(); 139 140 // Materialize the value in a register. Emit any instructions in the 141 // local value area. 142 Reg = materializeRegForValue(V, VT); 143 144 leaveLocalValueArea(SaveInsertPt); 145 146 return Reg; 147} 148 149/// materializeRegForValue - Helper for getRegForVale. This function is 150/// called when the value isn't already available in a register and must 151/// be materialized with new instructions. 152unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) { 153 unsigned Reg = 0; 154 155 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 156 if (CI->getValue().getActiveBits() <= 64) 157 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 158 } else if (isa<AllocaInst>(V)) { 159 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 160 } else if (isa<ConstantPointerNull>(V)) { 161 // Translate this as an integer zero so that it can be 162 // local-CSE'd with actual integer zeros. 163 Reg = 164 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext()))); 165 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 166 // Try to emit the constant directly. 167 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 168 169 if (!Reg) { 170 // Try to emit the constant by using an integer constant with a cast. 171 const APFloat &Flt = CF->getValueAPF(); 172 EVT IntVT = TLI.getPointerTy(); 173 174 uint64_t x[2]; 175 uint32_t IntBitWidth = IntVT.getSizeInBits(); 176 bool isExact; 177 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 178 APFloat::rmTowardZero, &isExact); 179 if (isExact) { 180 APInt IntVal(IntBitWidth, 2, x); 181 182 unsigned IntegerReg = 183 getRegForValue(ConstantInt::get(V->getContext(), IntVal)); 184 if (IntegerReg != 0) 185 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, 186 IntegerReg, /*Kill=*/false); 187 } 188 } 189 } else if (const Operator *Op = dyn_cast<Operator>(V)) { 190 if (!SelectOperator(Op, Op->getOpcode())) 191 if (!isa<Instruction>(Op) || 192 !TargetSelectInstruction(cast<Instruction>(Op))) 193 return 0; 194 Reg = lookUpRegForValue(Op); 195 } else if (isa<UndefValue>(V)) { 196 Reg = createResultReg(TLI.getRegClassFor(VT)); 197 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 198 TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 199 } 200 201 // If target-independent code couldn't handle the value, give target-specific 202 // code a try. 203 if (!Reg && isa<Constant>(V)) 204 Reg = TargetMaterializeConstant(cast<Constant>(V)); 205 206 // Don't cache constant materializations in the general ValueMap. 207 // To do so would require tracking what uses they dominate. 208 if (Reg != 0) { 209 LocalValueMap[V] = Reg; 210 LastLocalValue = MRI.getVRegDef(Reg); 211 } 212 return Reg; 213} 214 215unsigned FastISel::lookUpRegForValue(const Value *V) { 216 // Look up the value to see if we already have a register for it. We 217 // cache values defined by Instructions across blocks, and other values 218 // only locally. This is because Instructions already have the SSA 219 // def-dominates-use requirement enforced. 220 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V); 221 if (I != FuncInfo.ValueMap.end()) 222 return I->second; 223 return LocalValueMap[V]; 224} 225 226/// UpdateValueMap - Update the value map to include the new mapping for this 227/// instruction, or insert an extra copy to get the result in a previous 228/// determined register. 229/// NOTE: This is only necessary because we might select a block that uses 230/// a value before we select the block that defines the value. It might be 231/// possible to fix this by selecting blocks in reverse postorder. 232unsigned FastISel::UpdateValueMap(const Value *I, unsigned Reg) { 233 if (!isa<Instruction>(I)) { 234 LocalValueMap[I] = Reg; 235 return Reg; 236 } 237 238 unsigned &AssignedReg = FuncInfo.ValueMap[I]; 239 if (AssignedReg == 0) 240 // Use the new register. 241 AssignedReg = Reg; 242 else if (Reg != AssignedReg) { 243 // Arrange for uses of AssignedReg to be replaced by uses of Reg. 244 FuncInfo.RegFixups[AssignedReg] = Reg; 245 246 AssignedReg = Reg; 247 } 248 249 return AssignedReg; 250} 251 252std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) { 253 unsigned IdxN = getRegForValue(Idx); 254 if (IdxN == 0) 255 // Unhandled operand. Halt "fast" selection and bail. 256 return std::pair<unsigned, bool>(0, false); 257 258 bool IdxNIsKill = hasTrivialKill(Idx); 259 260 // If the index is smaller or larger than intptr_t, truncate or extend it. 261 MVT PtrVT = TLI.getPointerTy(); 262 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); 263 if (IdxVT.bitsLT(PtrVT)) { 264 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, 265 IdxN, IdxNIsKill); 266 IdxNIsKill = true; 267 } 268 else if (IdxVT.bitsGT(PtrVT)) { 269 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, 270 IdxN, IdxNIsKill); 271 IdxNIsKill = true; 272 } 273 return std::pair<unsigned, bool>(IdxN, IdxNIsKill); 274} 275 276void FastISel::recomputeInsertPt() { 277 if (getLastLocalValue()) { 278 FuncInfo.InsertPt = getLastLocalValue(); 279 ++FuncInfo.InsertPt; 280 } else 281 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI(); 282 283 // Now skip past any EH_LABELs, which must remain at the beginning. 284 while (FuncInfo.InsertPt != FuncInfo.MBB->end() && 285 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL) 286 ++FuncInfo.InsertPt; 287} 288 289MachineBasicBlock::iterator FastISel::enterLocalValueArea() { 290 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt; 291 recomputeInsertPt(); 292 return OldInsertPt; 293} 294 295void FastISel::leaveLocalValueArea(MachineBasicBlock::iterator OldInsertPt) { 296 if (FuncInfo.InsertPt != FuncInfo.MBB->begin()) 297 LastLocalValue = llvm::prior(FuncInfo.InsertPt); 298 299 // Restore the previous insert position. 300 FuncInfo.InsertPt = OldInsertPt; 301} 302 303/// SelectBinaryOp - Select and emit code for a binary operator instruction, 304/// which has an opcode which directly corresponds to the given ISD opcode. 305/// 306bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) { 307 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); 308 if (VT == MVT::Other || !VT.isSimple()) 309 // Unhandled type. Halt "fast" selection and bail. 310 return false; 311 312 // We only handle legal types. For example, on x86-32 the instruction 313 // selector contains all of the 64-bit instructions from x86-64, 314 // under the assumption that i64 won't be used if the target doesn't 315 // support it. 316 if (!TLI.isTypeLegal(VT)) { 317 // MVT::i1 is special. Allow AND, OR, or XOR because they 318 // don't require additional zeroing, which makes them easy. 319 if (VT == MVT::i1 && 320 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 321 ISDOpcode == ISD::XOR)) 322 VT = TLI.getTypeToTransformTo(I->getContext(), VT); 323 else 324 return false; 325 } 326 327 unsigned Op0 = getRegForValue(I->getOperand(0)); 328 if (Op0 == 0) 329 // Unhandled operand. Halt "fast" selection and bail. 330 return false; 331 332 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 333 334 // Check if the second operand is a constant and handle it appropriately. 335 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 336 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 337 ISDOpcode, Op0, Op0IsKill, 338 CI->getZExtValue()); 339 if (ResultReg != 0) { 340 // We successfully emitted code for the given LLVM Instruction. 341 UpdateValueMap(I, ResultReg); 342 return true; 343 } 344 } 345 346 // Check if the second operand is a constant float. 347 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 348 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 349 ISDOpcode, Op0, Op0IsKill, CF); 350 if (ResultReg != 0) { 351 // We successfully emitted code for the given LLVM Instruction. 352 UpdateValueMap(I, ResultReg); 353 return true; 354 } 355 } 356 357 unsigned Op1 = getRegForValue(I->getOperand(1)); 358 if (Op1 == 0) 359 // Unhandled operand. Halt "fast" selection and bail. 360 return false; 361 362 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); 363 364 // Now we have both operands in registers. Emit the instruction. 365 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 366 ISDOpcode, 367 Op0, Op0IsKill, 368 Op1, Op1IsKill); 369 if (ResultReg == 0) 370 // Target-specific code wasn't able to find a machine opcode for 371 // the given ISD opcode and type. Halt "fast" selection and bail. 372 return false; 373 374 // We successfully emitted code for the given LLVM Instruction. 375 UpdateValueMap(I, ResultReg); 376 return true; 377} 378 379bool FastISel::SelectGetElementPtr(const User *I) { 380 unsigned N = getRegForValue(I->getOperand(0)); 381 if (N == 0) 382 // Unhandled operand. Halt "fast" selection and bail. 383 return false; 384 385 bool NIsKill = hasTrivialKill(I->getOperand(0)); 386 387 const Type *Ty = I->getOperand(0)->getType(); 388 MVT VT = TLI.getPointerTy(); 389 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1, 390 E = I->op_end(); OI != E; ++OI) { 391 const Value *Idx = *OI; 392 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 393 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 394 if (Field) { 395 // N = N + Offset 396 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 397 // FIXME: This can be optimized by combining the add with a 398 // subsequent one. 399 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT); 400 if (N == 0) 401 // Unhandled operand. Halt "fast" selection and bail. 402 return false; 403 NIsKill = true; 404 } 405 Ty = StTy->getElementType(Field); 406 } else { 407 Ty = cast<SequentialType>(Ty)->getElementType(); 408 409 // If this is a constant subscript, handle it quickly. 410 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 411 if (CI->isZero()) continue; 412 uint64_t Offs = 413 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 414 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT); 415 if (N == 0) 416 // Unhandled operand. Halt "fast" selection and bail. 417 return false; 418 NIsKill = true; 419 continue; 420 } 421 422 // N = N + Idx * ElementSize; 423 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 424 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx); 425 unsigned IdxN = Pair.first; 426 bool IdxNIsKill = Pair.second; 427 if (IdxN == 0) 428 // Unhandled operand. Halt "fast" selection and bail. 429 return false; 430 431 if (ElementSize != 1) { 432 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT); 433 if (IdxN == 0) 434 // Unhandled operand. Halt "fast" selection and bail. 435 return false; 436 IdxNIsKill = true; 437 } 438 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill); 439 if (N == 0) 440 // Unhandled operand. Halt "fast" selection and bail. 441 return false; 442 } 443 } 444 445 // We successfully emitted code for the given LLVM Instruction. 446 UpdateValueMap(I, N); 447 return true; 448} 449 450bool FastISel::SelectCall(const User *I) { 451 const Function *F = cast<CallInst>(I)->getCalledFunction(); 452 if (!F) return false; 453 454 // Handle selected intrinsic function calls. 455 unsigned IID = F->getIntrinsicID(); 456 switch (IID) { 457 default: break; 458 case Intrinsic::dbg_declare: { 459 const DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 460 if (!DIVariable(DI->getVariable()).Verify() || 461 !FuncInfo.MF->getMMI().hasDebugInfo()) 462 return true; 463 464 const Value *Address = DI->getAddress(); 465 if (!Address) 466 return true; 467 if (isa<UndefValue>(Address)) 468 return true; 469 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 470 // Don't handle byval struct arguments or VLAs, for example. 471 // Note that if we have a byval struct argument, fast ISel is turned off; 472 // those are handled in SelectionDAGBuilder. 473 if (AI) { 474 DenseMap<const AllocaInst*, int>::iterator SI = 475 FuncInfo.StaticAllocaMap.find(AI); 476 if (SI == FuncInfo.StaticAllocaMap.end()) break; // VLAs. 477 int FI = SI->second; 478 if (!DI->getDebugLoc().isUnknown()) 479 FuncInfo.MF->getMMI().setVariableDbgInfo(DI->getVariable(), 480 FI, DI->getDebugLoc()); 481 } else 482 // Building the map above is target independent. Generating DBG_VALUE 483 // inline is target dependent; do this now. 484 (void)TargetSelectInstruction(cast<Instruction>(I)); 485 return true; 486 } 487 case Intrinsic::dbg_value: { 488 // This form of DBG_VALUE is target-independent. 489 const DbgValueInst *DI = cast<DbgValueInst>(I); 490 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 491 const Value *V = DI->getValue(); 492 if (!V) { 493 // Currently the optimizer can produce this; insert an undef to 494 // help debugging. Probably the optimizer should not do this. 495 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 496 .addReg(0U).addImm(DI->getOffset()) 497 .addMetadata(DI->getVariable()); 498 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 499 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 500 .addImm(CI->getZExtValue()).addImm(DI->getOffset()) 501 .addMetadata(DI->getVariable()); 502 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 503 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 504 .addFPImm(CF).addImm(DI->getOffset()) 505 .addMetadata(DI->getVariable()); 506 } else if (unsigned Reg = lookUpRegForValue(V)) { 507 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 508 .addReg(Reg, RegState::Debug).addImm(DI->getOffset()) 509 .addMetadata(DI->getVariable()); 510 } else { 511 // We can't yet handle anything else here because it would require 512 // generating code, thus altering codegen because of debug info. 513 // Insert an undef so we can see what we dropped. 514 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 515 .addReg(0U).addImm(DI->getOffset()) 516 .addMetadata(DI->getVariable()); 517 } 518 return true; 519 } 520 case Intrinsic::eh_exception: { 521 EVT VT = TLI.getValueType(I->getType()); 522 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 523 default: break; 524 case TargetLowering::Expand: { 525 assert(FuncInfo.MBB->isLandingPad() && 526 "Call to eh.exception not in landing pad!"); 527 unsigned Reg = TLI.getExceptionAddressRegister(); 528 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 529 unsigned ResultReg = createResultReg(RC); 530 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 531 ResultReg).addReg(Reg); 532 UpdateValueMap(I, ResultReg); 533 return true; 534 } 535 } 536 break; 537 } 538 case Intrinsic::eh_selector: { 539 EVT VT = TLI.getValueType(I->getType()); 540 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 541 default: break; 542 case TargetLowering::Expand: { 543 if (FuncInfo.MBB->isLandingPad()) 544 AddCatchInfo(*cast<CallInst>(I), &FuncInfo.MF->getMMI(), FuncInfo.MBB); 545 else { 546#ifndef NDEBUG 547 FuncInfo.CatchInfoLost.insert(cast<CallInst>(I)); 548#endif 549 // FIXME: Mark exception selector register as live in. Hack for PR1508. 550 unsigned Reg = TLI.getExceptionSelectorRegister(); 551 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 552 } 553 554 unsigned Reg = TLI.getExceptionSelectorRegister(); 555 EVT SrcVT = TLI.getPointerTy(); 556 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); 557 unsigned ResultReg = createResultReg(RC); 558 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 559 ResultReg).addReg(Reg); 560 561 bool ResultRegIsKill = hasTrivialKill(I); 562 563 // Cast the register to the type of the selector. 564 if (SrcVT.bitsGT(MVT::i32)) 565 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE, 566 ResultReg, ResultRegIsKill); 567 else if (SrcVT.bitsLT(MVT::i32)) 568 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, 569 ISD::SIGN_EXTEND, ResultReg, ResultRegIsKill); 570 if (ResultReg == 0) 571 // Unhandled operand. Halt "fast" selection and bail. 572 return false; 573 574 UpdateValueMap(I, ResultReg); 575 576 return true; 577 } 578 } 579 break; 580 } 581 } 582 583 // An arbitrary call. Bail. 584 return false; 585} 586 587bool FastISel::SelectCast(const User *I, unsigned Opcode) { 588 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 589 EVT DstVT = TLI.getValueType(I->getType()); 590 591 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 592 DstVT == MVT::Other || !DstVT.isSimple()) 593 // Unhandled type. Halt "fast" selection and bail. 594 return false; 595 596 // Check if the destination type is legal. Or as a special case, 597 // it may be i1 if we're doing a truncate because that's 598 // easy and somewhat common. 599 if (!TLI.isTypeLegal(DstVT)) 600 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 601 // Unhandled type. Halt "fast" selection and bail. 602 return false; 603 604 // Check if the source operand is legal. Or as a special case, 605 // it may be i1 if we're doing zero-extension because that's 606 // easy and somewhat common. 607 if (!TLI.isTypeLegal(SrcVT)) 608 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 609 // Unhandled type. Halt "fast" selection and bail. 610 return false; 611 612 unsigned InputReg = getRegForValue(I->getOperand(0)); 613 if (!InputReg) 614 // Unhandled operand. Halt "fast" selection and bail. 615 return false; 616 617 bool InputRegIsKill = hasTrivialKill(I->getOperand(0)); 618 619 // If the operand is i1, arrange for the high bits in the register to be zero. 620 if (SrcVT == MVT::i1) { 621 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT); 622 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg, InputRegIsKill); 623 if (!InputReg) 624 return false; 625 InputRegIsKill = true; 626 } 627 // If the result is i1, truncate to the target's type for i1 first. 628 if (DstVT == MVT::i1) 629 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT); 630 631 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 632 DstVT.getSimpleVT(), 633 Opcode, 634 InputReg, InputRegIsKill); 635 if (!ResultReg) 636 return false; 637 638 UpdateValueMap(I, ResultReg); 639 return true; 640} 641 642bool FastISel::SelectBitCast(const User *I) { 643 // If the bitcast doesn't change the type, just use the operand value. 644 if (I->getType() == I->getOperand(0)->getType()) { 645 unsigned Reg = getRegForValue(I->getOperand(0)); 646 if (Reg == 0) 647 return false; 648 UpdateValueMap(I, Reg); 649 return true; 650 } 651 652 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 653 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 654 EVT DstVT = TLI.getValueType(I->getType()); 655 656 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 657 DstVT == MVT::Other || !DstVT.isSimple() || 658 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 659 // Unhandled type. Halt "fast" selection and bail. 660 return false; 661 662 unsigned Op0 = getRegForValue(I->getOperand(0)); 663 if (Op0 == 0) 664 // Unhandled operand. Halt "fast" selection and bail. 665 return false; 666 667 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 668 669 // First, try to perform the bitcast by inserting a reg-reg copy. 670 unsigned ResultReg = 0; 671 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 672 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 673 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 674 ResultReg = createResultReg(DstClass); 675 676 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt, 677 ResultReg, Op0, 678 DstClass, SrcClass, DL); 679 if (!InsertedCopy) 680 ResultReg = 0; 681 } 682 683 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 684 if (!ResultReg) 685 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 686 ISD::BIT_CONVERT, Op0, Op0IsKill); 687 688 if (!ResultReg) 689 return false; 690 691 UpdateValueMap(I, ResultReg); 692 return true; 693} 694 695bool 696FastISel::SelectInstruction(const Instruction *I) { 697 // Just before the terminator instruction, insert instructions to 698 // feed PHI nodes in successor blocks. 699 if (isa<TerminatorInst>(I)) 700 if (!HandlePHINodesInSuccessorBlocks(I->getParent())) 701 return false; 702 703 DL = I->getDebugLoc(); 704 705 // First, try doing target-independent selection. 706 if (SelectOperator(I, I->getOpcode())) { 707 DL = DebugLoc(); 708 return true; 709 } 710 711 // Next, try calling the target to attempt to handle the instruction. 712 if (TargetSelectInstruction(I)) { 713 DL = DebugLoc(); 714 return true; 715 } 716 717 DL = DebugLoc(); 718 return false; 719} 720 721/// FastEmitBranch - Emit an unconditional branch to the given block, 722/// unless it is the immediate (fall-through) successor, and update 723/// the CFG. 724void 725FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) { 726 if (FuncInfo.MBB->isLayoutSuccessor(MSucc)) { 727 // The unconditional fall-through case, which needs no instructions. 728 } else { 729 // The unconditional branch case. 730 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL, 731 SmallVector<MachineOperand, 0>(), DL); 732 } 733 FuncInfo.MBB->addSuccessor(MSucc); 734} 735 736/// SelectFNeg - Emit an FNeg operation. 737/// 738bool 739FastISel::SelectFNeg(const User *I) { 740 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); 741 if (OpReg == 0) return false; 742 743 bool OpRegIsKill = hasTrivialKill(I); 744 745 // If the target has ISD::FNEG, use it. 746 EVT VT = TLI.getValueType(I->getType()); 747 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), 748 ISD::FNEG, OpReg, OpRegIsKill); 749 if (ResultReg != 0) { 750 UpdateValueMap(I, ResultReg); 751 return true; 752 } 753 754 // Bitcast the value to integer, twiddle the sign bit with xor, 755 // and then bitcast it back to floating-point. 756 if (VT.getSizeInBits() > 64) return false; 757 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); 758 if (!TLI.isTypeLegal(IntVT)) 759 return false; 760 761 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), 762 ISD::BIT_CONVERT, OpReg, OpRegIsKill); 763 if (IntReg == 0) 764 return false; 765 766 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, 767 IntReg, /*Kill=*/true, 768 UINT64_C(1) << (VT.getSizeInBits()-1), 769 IntVT.getSimpleVT()); 770 if (IntResultReg == 0) 771 return false; 772 773 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), 774 ISD::BIT_CONVERT, IntResultReg, /*Kill=*/true); 775 if (ResultReg == 0) 776 return false; 777 778 UpdateValueMap(I, ResultReg); 779 return true; 780} 781 782bool 783FastISel::SelectLoad(const User *I) { 784 LoadInst *LI = const_cast<LoadInst *>(cast<LoadInst>(I)); 785 786 // For a load from an alloca, make a limited effort to find the value 787 // already available in a register, avoiding redundant loads. 788 if (!LI->isVolatile() && isa<AllocaInst>(LI->getPointerOperand())) { 789 BasicBlock::iterator ScanFrom = LI; 790 if (const Value *V = FindAvailableLoadedValue(LI->getPointerOperand(), 791 LI->getParent(), ScanFrom)) { 792 if (!V->use_empty() && 793 (!isa<Instruction>(V) || 794 cast<Instruction>(V)->getParent() == LI->getParent() || 795 (isa<AllocaInst>(V) && 796 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V)))) && 797 (!isa<Argument>(V) || 798 LI->getParent() == &LI->getParent()->getParent()->getEntryBlock())) { 799 unsigned ResultReg = getRegForValue(V); 800 if (ResultReg != 0) { 801 UpdateValueMap(I, ResultReg); 802 return true; 803 } 804 } 805 } 806 } 807 808 return false; 809} 810 811bool 812FastISel::SelectOperator(const User *I, unsigned Opcode) { 813 switch (Opcode) { 814 case Instruction::Load: 815 return SelectLoad(I); 816 case Instruction::Add: 817 return SelectBinaryOp(I, ISD::ADD); 818 case Instruction::FAdd: 819 return SelectBinaryOp(I, ISD::FADD); 820 case Instruction::Sub: 821 return SelectBinaryOp(I, ISD::SUB); 822 case Instruction::FSub: 823 // FNeg is currently represented in LLVM IR as a special case of FSub. 824 if (BinaryOperator::isFNeg(I)) 825 return SelectFNeg(I); 826 return SelectBinaryOp(I, ISD::FSUB); 827 case Instruction::Mul: 828 return SelectBinaryOp(I, ISD::MUL); 829 case Instruction::FMul: 830 return SelectBinaryOp(I, ISD::FMUL); 831 case Instruction::SDiv: 832 return SelectBinaryOp(I, ISD::SDIV); 833 case Instruction::UDiv: 834 return SelectBinaryOp(I, ISD::UDIV); 835 case Instruction::FDiv: 836 return SelectBinaryOp(I, ISD::FDIV); 837 case Instruction::SRem: 838 return SelectBinaryOp(I, ISD::SREM); 839 case Instruction::URem: 840 return SelectBinaryOp(I, ISD::UREM); 841 case Instruction::FRem: 842 return SelectBinaryOp(I, ISD::FREM); 843 case Instruction::Shl: 844 return SelectBinaryOp(I, ISD::SHL); 845 case Instruction::LShr: 846 return SelectBinaryOp(I, ISD::SRL); 847 case Instruction::AShr: 848 return SelectBinaryOp(I, ISD::SRA); 849 case Instruction::And: 850 return SelectBinaryOp(I, ISD::AND); 851 case Instruction::Or: 852 return SelectBinaryOp(I, ISD::OR); 853 case Instruction::Xor: 854 return SelectBinaryOp(I, ISD::XOR); 855 856 case Instruction::GetElementPtr: 857 return SelectGetElementPtr(I); 858 859 case Instruction::Br: { 860 const BranchInst *BI = cast<BranchInst>(I); 861 862 if (BI->isUnconditional()) { 863 const BasicBlock *LLVMSucc = BI->getSuccessor(0); 864 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc]; 865 FastEmitBranch(MSucc, BI->getDebugLoc()); 866 return true; 867 } 868 869 // Conditional branches are not handed yet. 870 // Halt "fast" selection and bail. 871 return false; 872 } 873 874 case Instruction::Unreachable: 875 // Nothing to emit. 876 return true; 877 878 case Instruction::Alloca: 879 // FunctionLowering has the static-sized case covered. 880 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I))) 881 return true; 882 883 // Dynamic-sized alloca is not handled yet. 884 return false; 885 886 case Instruction::Call: 887 return SelectCall(I); 888 889 case Instruction::BitCast: 890 return SelectBitCast(I); 891 892 case Instruction::FPToSI: 893 return SelectCast(I, ISD::FP_TO_SINT); 894 case Instruction::ZExt: 895 return SelectCast(I, ISD::ZERO_EXTEND); 896 case Instruction::SExt: 897 return SelectCast(I, ISD::SIGN_EXTEND); 898 case Instruction::Trunc: 899 return SelectCast(I, ISD::TRUNCATE); 900 case Instruction::SIToFP: 901 return SelectCast(I, ISD::SINT_TO_FP); 902 903 case Instruction::IntToPtr: // Deliberate fall-through. 904 case Instruction::PtrToInt: { 905 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 906 EVT DstVT = TLI.getValueType(I->getType()); 907 if (DstVT.bitsGT(SrcVT)) 908 return SelectCast(I, ISD::ZERO_EXTEND); 909 if (DstVT.bitsLT(SrcVT)) 910 return SelectCast(I, ISD::TRUNCATE); 911 unsigned Reg = getRegForValue(I->getOperand(0)); 912 if (Reg == 0) return false; 913 UpdateValueMap(I, Reg); 914 return true; 915 } 916 917 case Instruction::PHI: 918 llvm_unreachable("FastISel shouldn't visit PHI nodes!"); 919 920 default: 921 // Unhandled instruction. Halt "fast" selection and bail. 922 return false; 923 } 924} 925 926FastISel::FastISel(FunctionLoweringInfo &funcInfo) 927 : FuncInfo(funcInfo), 928 MRI(FuncInfo.MF->getRegInfo()), 929 MFI(*FuncInfo.MF->getFrameInfo()), 930 MCP(*FuncInfo.MF->getConstantPool()), 931 TM(FuncInfo.MF->getTarget()), 932 TD(*TM.getTargetData()), 933 TII(*TM.getInstrInfo()), 934 TLI(*TM.getTargetLowering()), 935 TRI(*TM.getRegisterInfo()) { 936} 937 938FastISel::~FastISel() {} 939 940unsigned FastISel::FastEmit_(MVT, MVT, 941 unsigned) { 942 return 0; 943} 944 945unsigned FastISel::FastEmit_r(MVT, MVT, 946 unsigned, 947 unsigned /*Op0*/, bool /*Op0IsKill*/) { 948 return 0; 949} 950 951unsigned FastISel::FastEmit_rr(MVT, MVT, 952 unsigned, 953 unsigned /*Op0*/, bool /*Op0IsKill*/, 954 unsigned /*Op1*/, bool /*Op1IsKill*/) { 955 return 0; 956} 957 958unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) { 959 return 0; 960} 961 962unsigned FastISel::FastEmit_f(MVT, MVT, 963 unsigned, const ConstantFP * /*FPImm*/) { 964 return 0; 965} 966 967unsigned FastISel::FastEmit_ri(MVT, MVT, 968 unsigned, 969 unsigned /*Op0*/, bool /*Op0IsKill*/, 970 uint64_t /*Imm*/) { 971 return 0; 972} 973 974unsigned FastISel::FastEmit_rf(MVT, MVT, 975 unsigned, 976 unsigned /*Op0*/, bool /*Op0IsKill*/, 977 const ConstantFP * /*FPImm*/) { 978 return 0; 979} 980 981unsigned FastISel::FastEmit_rri(MVT, MVT, 982 unsigned, 983 unsigned /*Op0*/, bool /*Op0IsKill*/, 984 unsigned /*Op1*/, bool /*Op1IsKill*/, 985 uint64_t /*Imm*/) { 986 return 0; 987} 988 989/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 990/// to emit an instruction with an immediate operand using FastEmit_ri. 991/// If that fails, it materializes the immediate into a register and try 992/// FastEmit_rr instead. 993unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode, 994 unsigned Op0, bool Op0IsKill, 995 uint64_t Imm, MVT ImmType) { 996 // First check if immediate type is legal. If not, we can't use the ri form. 997 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); 998 if (ResultReg != 0) 999 return ResultReg; 1000 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 1001 if (MaterialReg == 0) 1002 return 0; 1003 return FastEmit_rr(VT, VT, Opcode, 1004 Op0, Op0IsKill, 1005 MaterialReg, /*Kill=*/true); 1006} 1007 1008/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 1009/// to emit an instruction with a floating-point immediate operand using 1010/// FastEmit_rf. If that fails, it materializes the immediate into a register 1011/// and try FastEmit_rr instead. 1012unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode, 1013 unsigned Op0, bool Op0IsKill, 1014 const ConstantFP *FPImm, MVT ImmType) { 1015 // First check if immediate type is legal. If not, we can't use the rf form. 1016 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, Op0IsKill, FPImm); 1017 if (ResultReg != 0) 1018 return ResultReg; 1019 1020 // Materialize the constant in a register. 1021 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 1022 if (MaterialReg == 0) { 1023 // If the target doesn't have a way to directly enter a floating-point 1024 // value into a register, use an alternate approach. 1025 // TODO: The current approach only supports floating-point constants 1026 // that can be constructed by conversion from integer values. This should 1027 // be replaced by code that creates a load from a constant-pool entry, 1028 // which will require some target-specific work. 1029 const APFloat &Flt = FPImm->getValueAPF(); 1030 EVT IntVT = TLI.getPointerTy(); 1031 1032 uint64_t x[2]; 1033 uint32_t IntBitWidth = IntVT.getSizeInBits(); 1034 bool isExact; 1035 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 1036 APFloat::rmTowardZero, &isExact); 1037 if (!isExact) 1038 return 0; 1039 APInt IntVal(IntBitWidth, 2, x); 1040 1041 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 1042 ISD::Constant, IntVal.getZExtValue()); 1043 if (IntegerReg == 0) 1044 return 0; 1045 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 1046 ISD::SINT_TO_FP, IntegerReg, /*Kill=*/true); 1047 if (MaterialReg == 0) 1048 return 0; 1049 } 1050 return FastEmit_rr(VT, VT, Opcode, 1051 Op0, Op0IsKill, 1052 MaterialReg, /*Kill=*/true); 1053} 1054 1055unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 1056 return MRI.createVirtualRegister(RC); 1057} 1058 1059unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 1060 const TargetRegisterClass* RC) { 1061 unsigned ResultReg = createResultReg(RC); 1062 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1063 1064 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg); 1065 return ResultReg; 1066} 1067 1068unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 1069 const TargetRegisterClass *RC, 1070 unsigned Op0, bool Op0IsKill) { 1071 unsigned ResultReg = createResultReg(RC); 1072 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1073 1074 if (II.getNumDefs() >= 1) 1075 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1076 .addReg(Op0, Op0IsKill * RegState::Kill); 1077 else { 1078 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1079 .addReg(Op0, Op0IsKill * RegState::Kill); 1080 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1081 ResultReg).addReg(II.ImplicitDefs[0]); 1082 } 1083 1084 return ResultReg; 1085} 1086 1087unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 1088 const TargetRegisterClass *RC, 1089 unsigned Op0, bool Op0IsKill, 1090 unsigned Op1, bool Op1IsKill) { 1091 unsigned ResultReg = createResultReg(RC); 1092 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1093 1094 if (II.getNumDefs() >= 1) 1095 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1096 .addReg(Op0, Op0IsKill * RegState::Kill) 1097 .addReg(Op1, Op1IsKill * RegState::Kill); 1098 else { 1099 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1100 .addReg(Op0, Op0IsKill * RegState::Kill) 1101 .addReg(Op1, Op1IsKill * RegState::Kill); 1102 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1103 ResultReg).addReg(II.ImplicitDefs[0]); 1104 } 1105 return ResultReg; 1106} 1107 1108unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 1109 const TargetRegisterClass *RC, 1110 unsigned Op0, bool Op0IsKill, 1111 uint64_t Imm) { 1112 unsigned ResultReg = createResultReg(RC); 1113 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1114 1115 if (II.getNumDefs() >= 1) 1116 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1117 .addReg(Op0, Op0IsKill * RegState::Kill) 1118 .addImm(Imm); 1119 else { 1120 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1121 .addReg(Op0, Op0IsKill * RegState::Kill) 1122 .addImm(Imm); 1123 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1124 ResultReg).addReg(II.ImplicitDefs[0]); 1125 } 1126 return ResultReg; 1127} 1128 1129unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 1130 const TargetRegisterClass *RC, 1131 unsigned Op0, bool Op0IsKill, 1132 const ConstantFP *FPImm) { 1133 unsigned ResultReg = createResultReg(RC); 1134 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1135 1136 if (II.getNumDefs() >= 1) 1137 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1138 .addReg(Op0, Op0IsKill * RegState::Kill) 1139 .addFPImm(FPImm); 1140 else { 1141 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1142 .addReg(Op0, Op0IsKill * RegState::Kill) 1143 .addFPImm(FPImm); 1144 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1145 ResultReg).addReg(II.ImplicitDefs[0]); 1146 } 1147 return ResultReg; 1148} 1149 1150unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 1151 const TargetRegisterClass *RC, 1152 unsigned Op0, bool Op0IsKill, 1153 unsigned Op1, bool Op1IsKill, 1154 uint64_t Imm) { 1155 unsigned ResultReg = createResultReg(RC); 1156 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1157 1158 if (II.getNumDefs() >= 1) 1159 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1160 .addReg(Op0, Op0IsKill * RegState::Kill) 1161 .addReg(Op1, Op1IsKill * RegState::Kill) 1162 .addImm(Imm); 1163 else { 1164 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1165 .addReg(Op0, Op0IsKill * RegState::Kill) 1166 .addReg(Op1, Op1IsKill * RegState::Kill) 1167 .addImm(Imm); 1168 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1169 ResultReg).addReg(II.ImplicitDefs[0]); 1170 } 1171 return ResultReg; 1172} 1173 1174unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 1175 const TargetRegisterClass *RC, 1176 uint64_t Imm) { 1177 unsigned ResultReg = createResultReg(RC); 1178 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1179 1180 if (II.getNumDefs() >= 1) 1181 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm); 1182 else { 1183 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm); 1184 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1185 ResultReg).addReg(II.ImplicitDefs[0]); 1186 } 1187 return ResultReg; 1188} 1189 1190unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, 1191 unsigned Op0, bool Op0IsKill, 1192 uint32_t Idx) { 1193 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1194 assert(TargetRegisterInfo::isVirtualRegister(Op0) && 1195 "Cannot yet extract from physregs"); 1196 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 1197 DL, TII.get(TargetOpcode::COPY), ResultReg) 1198 .addReg(Op0, getKillRegState(Op0IsKill), Idx); 1199 return ResultReg; 1200} 1201 1202/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1203/// with all but the least significant bit set to zero. 1204unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) { 1205 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1); 1206} 1207 1208/// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks. 1209/// Emit code to ensure constants are copied into registers when needed. 1210/// Remember the virtual registers that need to be added to the Machine PHI 1211/// nodes as input. We cannot just directly add them, because expansion 1212/// might result in multiple MBB's for one BB. As such, the start of the 1213/// BB might correspond to a different MBB than the end. 1214bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 1215 const TerminatorInst *TI = LLVMBB->getTerminator(); 1216 1217 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 1218 unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size(); 1219 1220 // Check successor nodes' PHI nodes that expect a constant to be available 1221 // from this block. 1222 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 1223 const BasicBlock *SuccBB = TI->getSuccessor(succ); 1224 if (!isa<PHINode>(SuccBB->begin())) continue; 1225 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 1226 1227 // If this terminator has multiple identical successors (common for 1228 // switches), only handle each succ once. 1229 if (!SuccsHandled.insert(SuccMBB)) continue; 1230 1231 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 1232 1233 // At this point we know that there is a 1-1 correspondence between LLVM PHI 1234 // nodes and Machine PHI nodes, but the incoming operands have not been 1235 // emitted yet. 1236 for (BasicBlock::const_iterator I = SuccBB->begin(); 1237 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 1238 1239 // Ignore dead phi's. 1240 if (PN->use_empty()) continue; 1241 1242 // Only handle legal types. Two interesting things to note here. First, 1243 // by bailing out early, we may leave behind some dead instructions, 1244 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its 1245 // own moves. Second, this check is necessary becuase FastISel doesn't 1246 // use CreateRegs to create registers, so it always creates 1247 // exactly one register for each non-void instruction. 1248 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true); 1249 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) { 1250 // Promote MVT::i1. 1251 if (VT == MVT::i1) 1252 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT); 1253 else { 1254 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1255 return false; 1256 } 1257 } 1258 1259 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 1260 1261 // Set the DebugLoc for the copy. Prefer the location of the operand 1262 // if there is one; use the location of the PHI otherwise. 1263 DL = PN->getDebugLoc(); 1264 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp)) 1265 DL = Inst->getDebugLoc(); 1266 1267 unsigned Reg = getRegForValue(PHIOp); 1268 if (Reg == 0) { 1269 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1270 return false; 1271 } 1272 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg)); 1273 DL = DebugLoc(); 1274 } 1275 } 1276 1277 return true; 1278} 1279