FastISel.cpp revision ed00d01712c891c40d5bac5ece79e787c67b6a63
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/Target/TargetData.h" 51#include "llvm/Target/TargetInstrInfo.h" 52#include "llvm/Target/TargetLowering.h" 53#include "llvm/Target/TargetMachine.h" 54#include "SelectionDAGBuild.h" 55using namespace llvm; 56 57unsigned FastISel::getRegForValue(Value *V) { 58 // Look up the value to see if we already have a register for it. We 59 // cache values defined by Instructions across blocks, and other values 60 // only locally. This is because Instructions already have the SSA 61 // def-dominatess-use requirement enforced. 62 if (ValueMap.count(V)) 63 return ValueMap[V]; 64 unsigned Reg = LocalValueMap[V]; 65 if (Reg != 0) 66 return Reg; 67 68 MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT(); 69 70 // Ignore illegal types. 71 if (!TLI.isTypeLegal(VT)) { 72 // Promote MVT::i1 to a legal type though, because it's common and easy. 73 if (VT == MVT::i1) 74 VT = TLI.getTypeToTransformTo(VT).getSimpleVT(); 75 else 76 return 0; 77 } 78 79 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 80 if (CI->getValue().getActiveBits() <= 64) 81 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 82 } else if (isa<AllocaInst>(V)) { 83 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 84 } else if (isa<ConstantPointerNull>(V)) { 85 // Translate this as an integer zero so that it can be 86 // local-CSE'd with actual integer zeros. 87 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType())); 88 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 89 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 90 91 if (!Reg) { 92 const APFloat &Flt = CF->getValueAPF(); 93 MVT IntVT = TLI.getPointerTy(); 94 95 uint64_t x[2]; 96 uint32_t IntBitWidth = IntVT.getSizeInBits(); 97 bool isExact; 98 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 99 APFloat::rmTowardZero, &isExact); 100 if (isExact) { 101 APInt IntVal(IntBitWidth, 2, x); 102 103 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal)); 104 if (IntegerReg != 0) 105 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 106 } 107 } 108 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 109 if (!SelectOperator(CE, CE->getOpcode())) return 0; 110 Reg = LocalValueMap[CE]; 111 } else if (isa<UndefValue>(V)) { 112 Reg = createResultReg(TLI.getRegClassFor(VT)); 113 BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); 114 } 115 116 // If target-independent code couldn't handle the value, give target-specific 117 // code a try. 118 if (!Reg && isa<Constant>(V)) 119 Reg = TargetMaterializeConstant(cast<Constant>(V)); 120 121 // Don't cache constant materializations in the general ValueMap. 122 // To do so would require tracking what uses they dominate. 123 if (Reg != 0) 124 LocalValueMap[V] = Reg; 125 return Reg; 126} 127 128unsigned FastISel::lookUpRegForValue(Value *V) { 129 // Look up the value to see if we already have a register for it. We 130 // cache values defined by Instructions across blocks, and other values 131 // only locally. This is because Instructions already have the SSA 132 // def-dominatess-use requirement enforced. 133 if (ValueMap.count(V)) 134 return ValueMap[V]; 135 return LocalValueMap[V]; 136} 137 138/// UpdateValueMap - Update the value map to include the new mapping for this 139/// instruction, or insert an extra copy to get the result in a previous 140/// determined register. 141/// NOTE: This is only necessary because we might select a block that uses 142/// a value before we select the block that defines the value. It might be 143/// possible to fix this by selecting blocks in reverse postorder. 144void FastISel::UpdateValueMap(Value* I, unsigned Reg) { 145 if (!isa<Instruction>(I)) { 146 LocalValueMap[I] = Reg; 147 return; 148 } 149 if (!ValueMap.count(I)) 150 ValueMap[I] = Reg; 151 else 152 TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I], 153 Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg)); 154} 155 156/// SelectBinaryOp - Select and emit code for a binary operator instruction, 157/// which has an opcode which directly corresponds to the given ISD opcode. 158/// 159bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { 160 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); 161 if (VT == MVT::Other || !VT.isSimple()) 162 // Unhandled type. Halt "fast" selection and bail. 163 return false; 164 165 // We only handle legal types. For example, on x86-32 the instruction 166 // selector contains all of the 64-bit instructions from x86-64, 167 // under the assumption that i64 won't be used if the target doesn't 168 // support it. 169 if (!TLI.isTypeLegal(VT)) { 170 // MVT::i1 is special. Allow AND, OR, or XOR because they 171 // don't require additional zeroing, which makes them easy. 172 if (VT == MVT::i1 && 173 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 174 ISDOpcode == ISD::XOR)) 175 VT = TLI.getTypeToTransformTo(VT); 176 else 177 return false; 178 } 179 180 unsigned Op0 = getRegForValue(I->getOperand(0)); 181 if (Op0 == 0) 182 // Unhandled operand. Halt "fast" selection and bail. 183 return false; 184 185 // Check if the second operand is a constant and handle it appropriately. 186 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 187 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 188 ISDOpcode, Op0, CI->getZExtValue()); 189 if (ResultReg != 0) { 190 // We successfully emitted code for the given LLVM Instruction. 191 UpdateValueMap(I, ResultReg); 192 return true; 193 } 194 } 195 196 // Check if the second operand is a constant float. 197 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 198 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 199 ISDOpcode, Op0, CF); 200 if (ResultReg != 0) { 201 // We successfully emitted code for the given LLVM Instruction. 202 UpdateValueMap(I, ResultReg); 203 return true; 204 } 205 } 206 207 unsigned Op1 = getRegForValue(I->getOperand(1)); 208 if (Op1 == 0) 209 // Unhandled operand. Halt "fast" selection and bail. 210 return false; 211 212 // Now we have both operands in registers. Emit the instruction. 213 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 214 ISDOpcode, Op0, Op1); 215 if (ResultReg == 0) 216 // Target-specific code wasn't able to find a machine opcode for 217 // the given ISD opcode and type. Halt "fast" selection and bail. 218 return false; 219 220 // We successfully emitted code for the given LLVM Instruction. 221 UpdateValueMap(I, ResultReg); 222 return true; 223} 224 225bool FastISel::SelectGetElementPtr(User *I) { 226 unsigned N = getRegForValue(I->getOperand(0)); 227 if (N == 0) 228 // Unhandled operand. Halt "fast" selection and bail. 229 return false; 230 231 const Type *Ty = I->getOperand(0)->getType(); 232 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT(); 233 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 234 OI != E; ++OI) { 235 Value *Idx = *OI; 236 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 237 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 238 if (Field) { 239 // N = N + Offset 240 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 241 // FIXME: This can be optimized by combining the add with a 242 // subsequent one. 243 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 244 if (N == 0) 245 // Unhandled operand. Halt "fast" selection and bail. 246 return false; 247 } 248 Ty = StTy->getElementType(Field); 249 } else { 250 Ty = cast<SequentialType>(Ty)->getElementType(); 251 252 // If this is a constant subscript, handle it quickly. 253 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 254 if (CI->getZExtValue() == 0) continue; 255 uint64_t Offs = 256 TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 257 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 258 if (N == 0) 259 // Unhandled operand. Halt "fast" selection and bail. 260 return false; 261 continue; 262 } 263 264 // N = N + Idx * ElementSize; 265 uint64_t ElementSize = TD.getABITypeSize(Ty); 266 unsigned IdxN = getRegForValue(Idx); 267 if (IdxN == 0) 268 // Unhandled operand. Halt "fast" selection and bail. 269 return false; 270 271 // If the index is smaller or larger than intptr_t, truncate or extend 272 // it. 273 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); 274 if (IdxVT.bitsLT(VT)) 275 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN); 276 else if (IdxVT.bitsGT(VT)) 277 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN); 278 if (IdxN == 0) 279 // Unhandled operand. Halt "fast" selection and bail. 280 return false; 281 282 if (ElementSize != 1) { 283 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 284 if (IdxN == 0) 285 // Unhandled operand. Halt "fast" selection and bail. 286 return false; 287 } 288 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 289 if (N == 0) 290 // Unhandled operand. Halt "fast" selection and bail. 291 return false; 292 } 293 } 294 295 // We successfully emitted code for the given LLVM Instruction. 296 UpdateValueMap(I, N); 297 return true; 298} 299 300bool FastISel::SelectCall(User *I) { 301 Function *F = cast<CallInst>(I)->getCalledFunction(); 302 if (!F) return false; 303 304 unsigned IID = F->getIntrinsicID(); 305 switch (IID) { 306 default: break; 307 case Intrinsic::dbg_stoppoint: { 308 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); 309 if (MMI && SPI->getContext() && MMI->Verify(SPI->getContext())) { 310 DebugInfoDesc *DD = MMI->getDescFor(SPI->getContext()); 311 assert(DD && "Not a debug information descriptor"); 312 const CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 313 unsigned SrcFile = MMI->RecordSource(CompileUnit); 314 unsigned Line = SPI->getLine(); 315 unsigned Col = SPI->getColumn(); 316 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); 317 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 318 BuildMI(MBB, II).addImm(ID); 319 } 320 return true; 321 } 322 case Intrinsic::dbg_region_start: { 323 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I); 324 if (MMI && RSI->getContext() && MMI->Verify(RSI->getContext())) { 325 unsigned ID = MMI->RecordRegionStart(RSI->getContext()); 326 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 327 BuildMI(MBB, II).addImm(ID); 328 } 329 return true; 330 } 331 case Intrinsic::dbg_region_end: { 332 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I); 333 if (MMI && REI->getContext() && MMI->Verify(REI->getContext())) { 334 unsigned ID = MMI->RecordRegionEnd(REI->getContext()); 335 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 336 BuildMI(MBB, II).addImm(ID); 337 } 338 return true; 339 } 340 case Intrinsic::dbg_func_start: { 341 if (!MMI) return true; 342 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); 343 Value *SP = FSI->getSubprogram(); 344 if (SP && MMI->Verify(SP)) { 345 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is 346 // what (most?) gdb expects. 347 DebugInfoDesc *DD = MMI->getDescFor(SP); 348 assert(DD && "Not a debug information descriptor"); 349 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD); 350 const CompileUnitDesc *CompileUnit = Subprogram->getFile(); 351 unsigned SrcFile = MMI->RecordSource(CompileUnit); 352 // Record the source line but does not create a label for the normal 353 // function start. It will be emitted at asm emission time. However, 354 // create a label if this is a beginning of inlined function. 355 unsigned LabelID = MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile); 356 if (MMI->getSourceLines().size() != 1) { 357 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 358 BuildMI(MBB, II).addImm(LabelID); 359 } 360 } 361 return true; 362 } 363 case Intrinsic::dbg_declare: { 364 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 365 Value *Variable = DI->getVariable(); 366 if (MMI && Variable && MMI->Verify(Variable)) { 367 // Determine the address of the declared object. 368 Value *Address = DI->getAddress(); 369 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 370 Address = BCI->getOperand(0); 371 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 372 // Don't handle byval struct arguments, for example. 373 if (!AI) break; 374 DenseMap<const AllocaInst*, int>::iterator SI = 375 StaticAllocaMap.find(AI); 376 assert(SI != StaticAllocaMap.end() && "Invalid dbg.declare!"); 377 int FI = SI->second; 378 379 // Determine the debug globalvariable. 380 GlobalValue *GV = cast<GlobalVariable>(Variable); 381 382 // Build the DECLARE instruction. 383 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE); 384 BuildMI(MBB, II).addFrameIndex(FI).addGlobalAddress(GV); 385 } 386 return true; 387 } 388 case Intrinsic::eh_exception: { 389 MVT VT = TLI.getValueType(I->getType()); 390 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 391 default: break; 392 case TargetLowering::Expand: { 393 if (!MBB->isLandingPad()) { 394 // FIXME: Mark exception register as live in. Hack for PR1508. 395 unsigned Reg = TLI.getExceptionAddressRegister(); 396 if (Reg) MBB->addLiveIn(Reg); 397 } 398 unsigned Reg = TLI.getExceptionAddressRegister(); 399 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 400 unsigned ResultReg = createResultReg(RC); 401 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 402 Reg, RC, RC); 403 assert(InsertedCopy && "Can't copy address registers!"); 404 UpdateValueMap(I, ResultReg); 405 return true; 406 } 407 } 408 break; 409 } 410 case Intrinsic::eh_selector_i32: 411 case Intrinsic::eh_selector_i64: { 412 MVT VT = TLI.getValueType(I->getType()); 413 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 414 default: break; 415 case TargetLowering::Expand: { 416 MVT VT = (IID == Intrinsic::eh_selector_i32 ? 417 MVT::i32 : MVT::i64); 418 419 if (MMI) { 420 if (MBB->isLandingPad()) 421 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 422 else { 423#ifndef NDEBUG 424 CatchInfoLost.insert(cast<CallInst>(I)); 425#endif 426 // FIXME: Mark exception selector register as live in. Hack for PR1508. 427 unsigned Reg = TLI.getExceptionSelectorRegister(); 428 if (Reg) MBB->addLiveIn(Reg); 429 } 430 431 unsigned Reg = TLI.getExceptionSelectorRegister(); 432 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 433 unsigned ResultReg = createResultReg(RC); 434 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 435 Reg, RC, RC); 436 assert(InsertedCopy && "Can't copy address registers!"); 437 UpdateValueMap(I, ResultReg); 438 } else { 439 unsigned ResultReg = 440 getRegForValue(Constant::getNullValue(I->getType())); 441 UpdateValueMap(I, ResultReg); 442 } 443 return true; 444 } 445 } 446 break; 447 } 448 } 449 return false; 450} 451 452bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { 453 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 454 MVT DstVT = TLI.getValueType(I->getType()); 455 456 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 457 DstVT == MVT::Other || !DstVT.isSimple() || 458 !TLI.isTypeLegal(DstVT)) 459 // Unhandled type. Halt "fast" selection and bail. 460 return false; 461 462 // Check if the source operand is legal. Or as a special case, 463 // it may be i1 if we're doing zero-extension because that's 464 // trivially easy and somewhat common. 465 if (!TLI.isTypeLegal(SrcVT)) { 466 if (SrcVT == MVT::i1 && Opcode == ISD::ZERO_EXTEND) 467 SrcVT = TLI.getTypeToTransformTo(SrcVT); 468 else 469 // Unhandled type. Halt "fast" selection and bail. 470 return false; 471 } 472 473 unsigned InputReg = getRegForValue(I->getOperand(0)); 474 if (!InputReg) 475 // Unhandled operand. Halt "fast" selection and bail. 476 return false; 477 478 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 479 DstVT.getSimpleVT(), 480 Opcode, 481 InputReg); 482 if (!ResultReg) 483 return false; 484 485 UpdateValueMap(I, ResultReg); 486 return true; 487} 488 489bool FastISel::SelectBitCast(User *I) { 490 // If the bitcast doesn't change the type, just use the operand value. 491 if (I->getType() == I->getOperand(0)->getType()) { 492 unsigned Reg = getRegForValue(I->getOperand(0)); 493 if (Reg == 0) 494 return false; 495 UpdateValueMap(I, Reg); 496 return true; 497 } 498 499 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 500 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 501 MVT DstVT = TLI.getValueType(I->getType()); 502 503 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 504 DstVT == MVT::Other || !DstVT.isSimple() || 505 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 506 // Unhandled type. Halt "fast" selection and bail. 507 return false; 508 509 unsigned Op0 = getRegForValue(I->getOperand(0)); 510 if (Op0 == 0) 511 // Unhandled operand. Halt "fast" selection and bail. 512 return false; 513 514 // First, try to perform the bitcast by inserting a reg-reg copy. 515 unsigned ResultReg = 0; 516 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 517 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 518 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 519 ResultReg = createResultReg(DstClass); 520 521 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 522 Op0, DstClass, SrcClass); 523 if (!InsertedCopy) 524 ResultReg = 0; 525 } 526 527 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 528 if (!ResultReg) 529 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 530 ISD::BIT_CONVERT, Op0); 531 532 if (!ResultReg) 533 return false; 534 535 UpdateValueMap(I, ResultReg); 536 return true; 537} 538 539bool 540FastISel::SelectInstruction(Instruction *I) { 541 return SelectOperator(I, I->getOpcode()); 542} 543 544/// FastEmitBranch - Emit an unconditional branch to the given block, 545/// unless it is the immediate (fall-through) successor, and update 546/// the CFG. 547void 548FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 549 MachineFunction::iterator NextMBB = 550 next(MachineFunction::iterator(MBB)); 551 552 if (MBB->isLayoutSuccessor(MSucc)) { 553 // The unconditional fall-through case, which needs no instructions. 554 } else { 555 // The unconditional branch case. 556 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 557 } 558 MBB->addSuccessor(MSucc); 559} 560 561bool 562FastISel::SelectOperator(User *I, unsigned Opcode) { 563 switch (Opcode) { 564 case Instruction::Add: { 565 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD; 566 return SelectBinaryOp(I, Opc); 567 } 568 case Instruction::Sub: { 569 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB; 570 return SelectBinaryOp(I, Opc); 571 } 572 case Instruction::Mul: { 573 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL; 574 return SelectBinaryOp(I, Opc); 575 } 576 case Instruction::SDiv: 577 return SelectBinaryOp(I, ISD::SDIV); 578 case Instruction::UDiv: 579 return SelectBinaryOp(I, ISD::UDIV); 580 case Instruction::FDiv: 581 return SelectBinaryOp(I, ISD::FDIV); 582 case Instruction::SRem: 583 return SelectBinaryOp(I, ISD::SREM); 584 case Instruction::URem: 585 return SelectBinaryOp(I, ISD::UREM); 586 case Instruction::FRem: 587 return SelectBinaryOp(I, ISD::FREM); 588 case Instruction::Shl: 589 return SelectBinaryOp(I, ISD::SHL); 590 case Instruction::LShr: 591 return SelectBinaryOp(I, ISD::SRL); 592 case Instruction::AShr: 593 return SelectBinaryOp(I, ISD::SRA); 594 case Instruction::And: 595 return SelectBinaryOp(I, ISD::AND); 596 case Instruction::Or: 597 return SelectBinaryOp(I, ISD::OR); 598 case Instruction::Xor: 599 return SelectBinaryOp(I, ISD::XOR); 600 601 case Instruction::GetElementPtr: 602 return SelectGetElementPtr(I); 603 604 case Instruction::Br: { 605 BranchInst *BI = cast<BranchInst>(I); 606 607 if (BI->isUnconditional()) { 608 BasicBlock *LLVMSucc = BI->getSuccessor(0); 609 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 610 FastEmitBranch(MSucc); 611 return true; 612 } 613 614 // Conditional branches are not handed yet. 615 // Halt "fast" selection and bail. 616 return false; 617 } 618 619 case Instruction::Unreachable: 620 // Nothing to emit. 621 return true; 622 623 case Instruction::PHI: 624 // PHI nodes are already emitted. 625 return true; 626 627 case Instruction::Alloca: 628 // FunctionLowering has the static-sized case covered. 629 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 630 return true; 631 632 // Dynamic-sized alloca is not handled yet. 633 return false; 634 635 case Instruction::Call: 636 return SelectCall(I); 637 638 case Instruction::BitCast: 639 return SelectBitCast(I); 640 641 case Instruction::FPToSI: 642 return SelectCast(I, ISD::FP_TO_SINT); 643 case Instruction::ZExt: 644 return SelectCast(I, ISD::ZERO_EXTEND); 645 case Instruction::SExt: 646 return SelectCast(I, ISD::SIGN_EXTEND); 647 case Instruction::Trunc: 648 return SelectCast(I, ISD::TRUNCATE); 649 case Instruction::SIToFP: 650 return SelectCast(I, ISD::SINT_TO_FP); 651 652 case Instruction::IntToPtr: // Deliberate fall-through. 653 case Instruction::PtrToInt: { 654 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 655 MVT DstVT = TLI.getValueType(I->getType()); 656 if (DstVT.bitsGT(SrcVT)) 657 return SelectCast(I, ISD::ZERO_EXTEND); 658 if (DstVT.bitsLT(SrcVT)) 659 return SelectCast(I, ISD::TRUNCATE); 660 unsigned Reg = getRegForValue(I->getOperand(0)); 661 if (Reg == 0) return false; 662 UpdateValueMap(I, Reg); 663 return true; 664 } 665 666 default: 667 // Unhandled instruction. Halt "fast" selection and bail. 668 return false; 669 } 670} 671 672FastISel::FastISel(MachineFunction &mf, 673 MachineModuleInfo *mmi, 674 DenseMap<const Value *, unsigned> &vm, 675 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 676 DenseMap<const AllocaInst *, int> &am 677#ifndef NDEBUG 678 , SmallSet<Instruction*, 8> &cil 679#endif 680 ) 681 : MBB(0), 682 ValueMap(vm), 683 MBBMap(bm), 684 StaticAllocaMap(am), 685#ifndef NDEBUG 686 CatchInfoLost(cil), 687#endif 688 MF(mf), 689 MMI(mmi), 690 MRI(MF.getRegInfo()), 691 MFI(*MF.getFrameInfo()), 692 MCP(*MF.getConstantPool()), 693 TM(MF.getTarget()), 694 TD(*TM.getTargetData()), 695 TII(*TM.getInstrInfo()), 696 TLI(*TM.getTargetLowering()) { 697} 698 699FastISel::~FastISel() {} 700 701unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, 702 ISD::NodeType) { 703 return 0; 704} 705 706unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType, 707 ISD::NodeType, unsigned /*Op0*/) { 708 return 0; 709} 710 711unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, 712 ISD::NodeType, unsigned /*Op0*/, 713 unsigned /*Op0*/) { 714 return 0; 715} 716 717unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType, 718 ISD::NodeType, uint64_t /*Imm*/) { 719 return 0; 720} 721 722unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType, 723 ISD::NodeType, ConstantFP * /*FPImm*/) { 724 return 0; 725} 726 727unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType, 728 ISD::NodeType, unsigned /*Op0*/, 729 uint64_t /*Imm*/) { 730 return 0; 731} 732 733unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType, 734 ISD::NodeType, unsigned /*Op0*/, 735 ConstantFP * /*FPImm*/) { 736 return 0; 737} 738 739unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, 740 ISD::NodeType, 741 unsigned /*Op0*/, unsigned /*Op1*/, 742 uint64_t /*Imm*/) { 743 return 0; 744} 745 746/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 747/// to emit an instruction with an immediate operand using FastEmit_ri. 748/// If that fails, it materializes the immediate into a register and try 749/// FastEmit_rr instead. 750unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 751 unsigned Op0, uint64_t Imm, 752 MVT::SimpleValueType ImmType) { 753 // First check if immediate type is legal. If not, we can't use the ri form. 754 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 755 if (ResultReg != 0) 756 return ResultReg; 757 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 758 if (MaterialReg == 0) 759 return 0; 760 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 761} 762 763/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 764/// to emit an instruction with a floating-point immediate operand using 765/// FastEmit_rf. If that fails, it materializes the immediate into a register 766/// and try FastEmit_rr instead. 767unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 768 unsigned Op0, ConstantFP *FPImm, 769 MVT::SimpleValueType ImmType) { 770 // First check if immediate type is legal. If not, we can't use the rf form. 771 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 772 if (ResultReg != 0) 773 return ResultReg; 774 775 // Materialize the constant in a register. 776 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 777 if (MaterialReg == 0) { 778 // If the target doesn't have a way to directly enter a floating-point 779 // value into a register, use an alternate approach. 780 // TODO: The current approach only supports floating-point constants 781 // that can be constructed by conversion from integer values. This should 782 // be replaced by code that creates a load from a constant-pool entry, 783 // which will require some target-specific work. 784 const APFloat &Flt = FPImm->getValueAPF(); 785 MVT IntVT = TLI.getPointerTy(); 786 787 uint64_t x[2]; 788 uint32_t IntBitWidth = IntVT.getSizeInBits(); 789 bool isExact; 790 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 791 APFloat::rmTowardZero, &isExact); 792 if (!isExact) 793 return 0; 794 APInt IntVal(IntBitWidth, 2, x); 795 796 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 797 ISD::Constant, IntVal.getZExtValue()); 798 if (IntegerReg == 0) 799 return 0; 800 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 801 ISD::SINT_TO_FP, IntegerReg); 802 if (MaterialReg == 0) 803 return 0; 804 } 805 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 806} 807 808unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 809 return MRI.createVirtualRegister(RC); 810} 811 812unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 813 const TargetRegisterClass* RC) { 814 unsigned ResultReg = createResultReg(RC); 815 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 816 817 BuildMI(MBB, II, ResultReg); 818 return ResultReg; 819} 820 821unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 822 const TargetRegisterClass *RC, 823 unsigned Op0) { 824 unsigned ResultReg = createResultReg(RC); 825 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 826 827 if (II.getNumDefs() >= 1) 828 BuildMI(MBB, II, ResultReg).addReg(Op0); 829 else { 830 BuildMI(MBB, II).addReg(Op0); 831 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 832 II.ImplicitDefs[0], RC, RC); 833 if (!InsertedCopy) 834 ResultReg = 0; 835 } 836 837 return ResultReg; 838} 839 840unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 841 const TargetRegisterClass *RC, 842 unsigned Op0, unsigned Op1) { 843 unsigned ResultReg = createResultReg(RC); 844 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 845 846 if (II.getNumDefs() >= 1) 847 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1); 848 else { 849 BuildMI(MBB, II).addReg(Op0).addReg(Op1); 850 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 851 II.ImplicitDefs[0], RC, RC); 852 if (!InsertedCopy) 853 ResultReg = 0; 854 } 855 return ResultReg; 856} 857 858unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 859 const TargetRegisterClass *RC, 860 unsigned Op0, uint64_t Imm) { 861 unsigned ResultReg = createResultReg(RC); 862 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 863 864 if (II.getNumDefs() >= 1) 865 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm); 866 else { 867 BuildMI(MBB, II).addReg(Op0).addImm(Imm); 868 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 869 II.ImplicitDefs[0], RC, RC); 870 if (!InsertedCopy) 871 ResultReg = 0; 872 } 873 return ResultReg; 874} 875 876unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 877 const TargetRegisterClass *RC, 878 unsigned Op0, ConstantFP *FPImm) { 879 unsigned ResultReg = createResultReg(RC); 880 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 881 882 if (II.getNumDefs() >= 1) 883 BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm); 884 else { 885 BuildMI(MBB, II).addReg(Op0).addFPImm(FPImm); 886 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 887 II.ImplicitDefs[0], RC, RC); 888 if (!InsertedCopy) 889 ResultReg = 0; 890 } 891 return ResultReg; 892} 893 894unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 895 const TargetRegisterClass *RC, 896 unsigned Op0, unsigned Op1, uint64_t Imm) { 897 unsigned ResultReg = createResultReg(RC); 898 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 899 900 if (II.getNumDefs() >= 1) 901 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 902 else { 903 BuildMI(MBB, II).addReg(Op0).addReg(Op1).addImm(Imm); 904 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 905 II.ImplicitDefs[0], RC, RC); 906 if (!InsertedCopy) 907 ResultReg = 0; 908 } 909 return ResultReg; 910} 911 912unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 913 const TargetRegisterClass *RC, 914 uint64_t Imm) { 915 unsigned ResultReg = createResultReg(RC); 916 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 917 918 if (II.getNumDefs() >= 1) 919 BuildMI(MBB, II, ResultReg).addImm(Imm); 920 else { 921 BuildMI(MBB, II).addImm(Imm); 922 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 923 II.ImplicitDefs[0], RC, RC); 924 if (!InsertedCopy) 925 ResultReg = 0; 926 } 927 return ResultReg; 928} 929 930unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) { 931 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 932 const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1); 933 934 unsigned ResultReg = createResultReg(SRC); 935 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); 936 937 if (II.getNumDefs() >= 1) 938 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx); 939 else { 940 BuildMI(MBB, II).addReg(Op0).addImm(Idx); 941 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 942 II.ImplicitDefs[0], RC, RC); 943 if (!InsertedCopy) 944 ResultReg = 0; 945 } 946 return ResultReg; 947} 948