FastISel.cpp revision f93cf79505f07cb97597fbc5955462ad7670ca5c 
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the implementation of the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Instructions.h"
15#include "llvm/CodeGen/FastISel.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/Target/TargetData.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/Target/TargetLowering.h"
21#include "llvm/Target/TargetMachine.h"
22using namespace llvm;
23
24/// SelectBinaryOp - Select and emit code for a binary operator instruction,
25/// which has an opcode which directly corresponds to the given ISD opcode.
26///
27bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
28                              DenseMap<const Value*, unsigned> &ValueMap) {
29  MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
30  if (VT == MVT::Other || !VT.isSimple())
31    // Unhandled type. Halt "fast" selection and bail.
32    return false;
33
34  unsigned Op0 = ValueMap[I->getOperand(0)];
35  if (Op0 == 0)
36    // Unhandled operand. Halt "fast" selection and bail.
37    return false;
38
39  // Check if the second operand is a constant and handle it appropriately.
40  if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
41    unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
42                                      CI->getZExtValue(), VT.getSimpleVT());
43    if (ResultReg == 0)
44      // Target-specific code wasn't able to find a machine opcode for
45      // the given ISD opcode and type. Halt "fast" selection and bail.
46      return false;
47
48    // We successfully emitted code for the given LLVM Instruction.
49    ValueMap[I] = ResultReg;
50    return true;
51  }
52
53  unsigned Op1 = ValueMap[I->getOperand(1)];
54  if (Op1 == 0)
55    // Unhandled operand. Halt "fast" selection and bail.
56    return false;
57
58  unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISDOpcode, Op0, Op1);
59  if (ResultReg == 0)
60    // Target-specific code wasn't able to find a machine opcode for
61    // the given ISD opcode and type. Halt "fast" selection and bail.
62    return false;
63
64  // We successfully emitted code for the given LLVM Instruction.
65  ValueMap[I] = ResultReg;
66  return true;
67}
68
69bool FastISel::SelectGetElementPtr(Instruction *I,
70                                   DenseMap<const Value*, unsigned> &ValueMap) {
71  unsigned N = ValueMap[I->getOperand(0)];
72  if (N == 0)
73    // Unhandled operand. Halt "fast" selection and bail.
74    return false;
75
76  const Type *Ty = I->getOperand(0)->getType();
77  MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
78  for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
79       OI != E; ++OI) {
80    Value *Idx = *OI;
81    if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
82      unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
83      if (Field) {
84        // N = N + Offset
85        uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
86        // FIXME: This can be optimized by combining the add with a
87        // subsequent one.
88        N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
89        if (N == 0)
90          // Unhandled operand. Halt "fast" selection and bail.
91          return false;
92      }
93      Ty = StTy->getElementType(Field);
94    } else {
95      Ty = cast<SequentialType>(Ty)->getElementType();
96
97      // If this is a constant subscript, handle it quickly.
98      if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
99        if (CI->getZExtValue() == 0) continue;
100        uint64_t Offs =
101          TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
102        N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
103        if (N == 0)
104          // Unhandled operand. Halt "fast" selection and bail.
105          return false;
106        continue;
107      }
108
109      // N = N + Idx * ElementSize;
110      uint64_t ElementSize = TD.getABITypeSize(Ty);
111      unsigned IdxN = ValueMap[Idx];
112      if (IdxN == 0)
113        // Unhandled operand. Halt "fast" selection and bail.
114        return false;
115
116      // If the index is smaller or larger than intptr_t, truncate or extend
117      // it.
118      MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
119      if (IdxVT.bitsLT(VT))
120        IdxN = FastEmit_r(VT, ISD::SIGN_EXTEND, IdxN);
121      else if (IdxVT.bitsGT(VT))
122        IdxN = FastEmit_r(VT, ISD::TRUNCATE, IdxN);
123      if (IdxN == 0)
124        // Unhandled operand. Halt "fast" selection and bail.
125        return false;
126
127      if (ElementSize != 1)
128        IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
129      if (IdxN == 0)
130        // Unhandled operand. Halt "fast" selection and bail.
131        return false;
132      N = FastEmit_rr(VT, ISD::ADD, N, IdxN);
133      if (N == 0)
134        // Unhandled operand. Halt "fast" selection and bail.
135        return false;
136    }
137  }
138
139  // We successfully emitted code for the given LLVM Instruction.
140  ValueMap[I] = N;
141  return true;
142}
143
144BasicBlock::iterator
145FastISel::SelectInstructions(BasicBlock::iterator Begin,
146                             BasicBlock::iterator End,
147                             DenseMap<const Value*, unsigned> &ValueMap,
148                             MachineBasicBlock *mbb) {
149  MBB = mbb;
150  BasicBlock::iterator I = Begin;
151
152  for (; I != End; ++I) {
153    switch (I->getOpcode()) {
154    case Instruction::Add: {
155      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
156      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
157    }
158    case Instruction::Sub: {
159      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
160      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
161    }
162    case Instruction::Mul: {
163      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
164      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
165    }
166    case Instruction::SDiv:
167      if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
168    case Instruction::UDiv:
169      if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
170    case Instruction::FDiv:
171      if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
172    case Instruction::SRem:
173      if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
174    case Instruction::URem:
175      if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
176    case Instruction::FRem:
177      if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
178    case Instruction::Shl:
179      if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
180    case Instruction::LShr:
181      if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
182    case Instruction::AShr:
183      if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
184    case Instruction::And:
185      if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
186    case Instruction::Or:
187      if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
188    case Instruction::Xor:
189      if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
190
191    case Instruction::GetElementPtr:
192      if (!SelectGetElementPtr(I, ValueMap)) return I;
193      break;
194
195    case Instruction::Br: {
196      BranchInst *BI = cast<BranchInst>(I);
197
198      // For now, check for and handle just the most trivial case: an
199      // unconditional fall-through branch.
200      if (BI->isUnconditional()) {
201         MachineFunction::iterator NextMBB =
202           next(MachineFunction::iterator(MBB));
203         if (NextMBB != MF.end() &&
204             NextMBB->getBasicBlock() == BI->getSuccessor(0)) {
205          MBB->addSuccessor(NextMBB);
206          break;
207        }
208      }
209
210      // Something more complicated. Halt "fast" selection and bail.
211      return I;
212    }
213    default:
214      // Unhandled instruction. Halt "fast" selection and bail.
215      return I;
216    }
217  }
218
219  return I;
220}
221
222FastISel::FastISel(MachineFunction &mf)
223  : MF(mf), MRI(mf.getRegInfo()),
224    TD(*mf.getTarget().getTargetData()),
225    TII(*mf.getTarget().getInstrInfo()),
226    TLI(*mf.getTarget().getTargetLowering()) {
227}
228
229FastISel::~FastISel() {}
230
231unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
232  return 0;
233}
234
235unsigned FastISel::FastEmit_r(MVT::SimpleValueType, ISD::NodeType,
236                              unsigned /*Op0*/) {
237  return 0;
238}
239
240unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
241                               unsigned /*Op0*/, unsigned /*Op0*/) {
242  return 0;
243}
244
245unsigned FastISel::FastEmit_i(MVT::SimpleValueType, uint64_t /*Imm*/) {
246  return 0;
247}
248
249unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, ISD::NodeType,
250                               unsigned /*Op0*/, uint64_t /*Imm*/) {
251  return 0;
252}
253
254unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, ISD::NodeType,
255                                unsigned /*Op0*/, unsigned /*Op1*/,
256                                uint64_t /*Imm*/) {
257  return 0;
258}
259
260/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
261/// to emit an instruction with an immediate operand using FastEmit_ri.
262/// If that fails, it materializes the immediate into a register and try
263/// FastEmit_rr instead.
264unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
265                                unsigned Op0, uint64_t Imm,
266                                MVT::SimpleValueType ImmType) {
267  unsigned ResultReg = 0;
268  // First check if immediate type is legal. If not, we can't use the ri form.
269  if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
270    ResultReg = FastEmit_ri(VT, Opcode, Op0, Imm);
271  if (ResultReg != 0)
272    return ResultReg;
273  unsigned MaterialReg = FastEmit_i(ImmType, Imm);
274  if (MaterialReg == 0)
275    return 0;
276  return FastEmit_rr(VT, Opcode, Op0, MaterialReg);
277}
278
279unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
280  return MRI.createVirtualRegister(RC);
281}
282
283unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
284                                 const TargetRegisterClass* RC) {
285  unsigned ResultReg = createResultReg(RC);
286  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
287
288  BuildMI(MBB, II, ResultReg);
289  return ResultReg;
290}
291
292unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
293                                  const TargetRegisterClass *RC,
294                                  unsigned Op0) {
295  unsigned ResultReg = createResultReg(RC);
296  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
297
298  BuildMI(MBB, II, ResultReg).addReg(Op0);
299  return ResultReg;
300}
301
302unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
303                                   const TargetRegisterClass *RC,
304                                   unsigned Op0, unsigned Op1) {
305  unsigned ResultReg = createResultReg(RC);
306  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
307
308  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
309  return ResultReg;
310}
311
312unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
313                                   const TargetRegisterClass *RC,
314                                   unsigned Op0, uint64_t Imm) {
315  unsigned ResultReg = createResultReg(RC);
316  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
317
318  BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
319  return ResultReg;
320}
321
322unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
323                                    const TargetRegisterClass *RC,
324                                    unsigned Op0, unsigned Op1, uint64_t Imm) {
325  unsigned ResultReg = createResultReg(RC);
326  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
327
328  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
329  return ResultReg;
330}
331