FastISel.cpp revision fb8fc280c2ca288e1aeceedbff0b91ec44c00791
1//===-- FastISel.cpp - Implementation of the FastISel class ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/Analysis/DebugInfo.h" 51#include "llvm/Target/TargetData.h" 52#include "llvm/Target/TargetInstrInfo.h" 53#include "llvm/Target/TargetLowering.h" 54#include "llvm/Target/TargetMachine.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "FunctionLoweringInfo.h" 57using namespace llvm; 58 59bool FastISel::hasTrivialKill(const Value *V) const { 60 // Don't consider constants or arguments to have trivial kills. 61 const Instruction *I = dyn_cast<Instruction>(V); 62 if (!I) 63 return false; 64 65 // No-op casts are trivially coalesced by fast-isel. 66 if (const CastInst *Cast = dyn_cast<CastInst>(I)) 67 if (Cast->isNoopCast(TD.getIntPtrType(Cast->getContext())) && 68 !hasTrivialKill(Cast->getOperand(0))) 69 return false; 70 71 // Only instructions with a single use in the same basic block are considered 72 // to have trivial kills. 73 return I->hasOneUse() && 74 !(I->getOpcode() == Instruction::BitCast || 75 I->getOpcode() == Instruction::PtrToInt || 76 I->getOpcode() == Instruction::IntToPtr) && 77 cast<Instruction>(I->use_begin())->getParent() == I->getParent(); 78} 79 80unsigned FastISel::getRegForValue(const Value *V) { 81 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 82 // Don't handle non-simple values in FastISel. 83 if (!RealVT.isSimple()) 84 return 0; 85 86 // Ignore illegal types. We must do this before looking up the value 87 // in ValueMap because Arguments are given virtual registers regardless 88 // of whether FastISel can handle them. 89 MVT VT = RealVT.getSimpleVT(); 90 if (!TLI.isTypeLegal(VT)) { 91 // Promote MVT::i1 to a legal type though, because it's common and easy. 92 if (VT == MVT::i1) 93 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); 94 else 95 return 0; 96 } 97 98 // Look up the value to see if we already have a register for it. We 99 // cache values defined by Instructions across blocks, and other values 100 // only locally. This is because Instructions already have the SSA 101 // def-dominates-use requirement enforced. 102 DenseMap<const Value *, unsigned>::iterator I = ValueMap.find(V); 103 if (I != ValueMap.end()) 104 return I->second; 105 unsigned Reg = LocalValueMap[V]; 106 if (Reg != 0) 107 return Reg; 108 109 // In bottom-up mode, just create the virtual register which will be used 110 // to hold the value. It will be materialized later. 111 if (IsBottomUp) { 112 Reg = createResultReg(TLI.getRegClassFor(VT)); 113 if (isa<Instruction>(V)) 114 ValueMap[V] = Reg; 115 else 116 LocalValueMap[V] = Reg; 117 return Reg; 118 } 119 120 return materializeRegForValue(V, VT); 121} 122 123/// materializeRegForValue - Helper for getRegForVale. This function is 124/// called when the value isn't already available in a register and must 125/// be materialized with new instructions. 126unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) { 127 unsigned Reg = 0; 128 129 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 130 if (CI->getValue().getActiveBits() <= 64) 131 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 132 } else if (isa<AllocaInst>(V)) { 133 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 134 } else if (isa<ConstantPointerNull>(V)) { 135 // Translate this as an integer zero so that it can be 136 // local-CSE'd with actual integer zeros. 137 Reg = 138 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext()))); 139 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 140 // Try to emit the constant directly. 141 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 142 143 if (!Reg) { 144 // Try to emit the constant by using an integer constant with a cast. 145 const APFloat &Flt = CF->getValueAPF(); 146 EVT IntVT = TLI.getPointerTy(); 147 148 uint64_t x[2]; 149 uint32_t IntBitWidth = IntVT.getSizeInBits(); 150 bool isExact; 151 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 152 APFloat::rmTowardZero, &isExact); 153 if (isExact) { 154 APInt IntVal(IntBitWidth, 2, x); 155 156 unsigned IntegerReg = 157 getRegForValue(ConstantInt::get(V->getContext(), IntVal)); 158 if (IntegerReg != 0) 159 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, 160 IntegerReg, /*Kill=*/false); 161 } 162 } 163 } else if (const Operator *Op = dyn_cast<Operator>(V)) { 164 if (!SelectOperator(Op, Op->getOpcode())) return 0; 165 Reg = lookUpRegForValue(Op); 166 } else if (isa<UndefValue>(V)) { 167 Reg = createResultReg(TLI.getRegClassFor(VT)); 168 BuildMI(MBB, DL, TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 169 } 170 171 // If target-independent code couldn't handle the value, give target-specific 172 // code a try. 173 if (!Reg && isa<Constant>(V)) 174 Reg = TargetMaterializeConstant(cast<Constant>(V)); 175 176 // Don't cache constant materializations in the general ValueMap. 177 // To do so would require tracking what uses they dominate. 178 if (Reg != 0) 179 LocalValueMap[V] = Reg; 180 return Reg; 181} 182 183unsigned FastISel::lookUpRegForValue(const Value *V) { 184 // Look up the value to see if we already have a register for it. We 185 // cache values defined by Instructions across blocks, and other values 186 // only locally. This is because Instructions already have the SSA 187 // def-dominates-use requirement enforced. 188 if (ValueMap.count(V)) 189 return ValueMap[V]; 190 return LocalValueMap[V]; 191} 192 193/// UpdateValueMap - Update the value map to include the new mapping for this 194/// instruction, or insert an extra copy to get the result in a previous 195/// determined register. 196/// NOTE: This is only necessary because we might select a block that uses 197/// a value before we select the block that defines the value. It might be 198/// possible to fix this by selecting blocks in reverse postorder. 199unsigned FastISel::UpdateValueMap(const Value *I, unsigned Reg) { 200 if (!isa<Instruction>(I)) { 201 LocalValueMap[I] = Reg; 202 return Reg; 203 } 204 205 unsigned &AssignedReg = ValueMap[I]; 206 if (AssignedReg == 0) 207 AssignedReg = Reg; 208 else if (Reg != AssignedReg) { 209 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); 210 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg, 211 Reg, RegClass, RegClass, DL); 212 } 213 return AssignedReg; 214} 215 216std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) { 217 unsigned IdxN = getRegForValue(Idx); 218 if (IdxN == 0) 219 // Unhandled operand. Halt "fast" selection and bail. 220 return std::pair<unsigned, bool>(0, false); 221 222 bool IdxNIsKill = hasTrivialKill(Idx); 223 224 // If the index is smaller or larger than intptr_t, truncate or extend it. 225 MVT PtrVT = TLI.getPointerTy(); 226 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); 227 if (IdxVT.bitsLT(PtrVT)) { 228 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, 229 IdxN, IdxNIsKill); 230 IdxNIsKill = true; 231 } 232 else if (IdxVT.bitsGT(PtrVT)) { 233 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, 234 IdxN, IdxNIsKill); 235 IdxNIsKill = true; 236 } 237 return std::pair<unsigned, bool>(IdxN, IdxNIsKill); 238} 239 240/// SelectBinaryOp - Select and emit code for a binary operator instruction, 241/// which has an opcode which directly corresponds to the given ISD opcode. 242/// 243bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) { 244 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); 245 if (VT == MVT::Other || !VT.isSimple()) 246 // Unhandled type. Halt "fast" selection and bail. 247 return false; 248 249 // We only handle legal types. For example, on x86-32 the instruction 250 // selector contains all of the 64-bit instructions from x86-64, 251 // under the assumption that i64 won't be used if the target doesn't 252 // support it. 253 if (!TLI.isTypeLegal(VT)) { 254 // MVT::i1 is special. Allow AND, OR, or XOR because they 255 // don't require additional zeroing, which makes them easy. 256 if (VT == MVT::i1 && 257 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 258 ISDOpcode == ISD::XOR)) 259 VT = TLI.getTypeToTransformTo(I->getContext(), VT); 260 else 261 return false; 262 } 263 264 unsigned Op0 = getRegForValue(I->getOperand(0)); 265 if (Op0 == 0) 266 // Unhandled operand. Halt "fast" selection and bail. 267 return false; 268 269 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 270 271 // Check if the second operand is a constant and handle it appropriately. 272 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 273 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 274 ISDOpcode, Op0, Op0IsKill, 275 CI->getZExtValue()); 276 if (ResultReg != 0) { 277 // We successfully emitted code for the given LLVM Instruction. 278 UpdateValueMap(I, ResultReg); 279 return true; 280 } 281 } 282 283 // Check if the second operand is a constant float. 284 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 285 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 286 ISDOpcode, Op0, Op0IsKill, CF); 287 if (ResultReg != 0) { 288 // We successfully emitted code for the given LLVM Instruction. 289 UpdateValueMap(I, ResultReg); 290 return true; 291 } 292 } 293 294 unsigned Op1 = getRegForValue(I->getOperand(1)); 295 if (Op1 == 0) 296 // Unhandled operand. Halt "fast" selection and bail. 297 return false; 298 299 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); 300 301 // Now we have both operands in registers. Emit the instruction. 302 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 303 ISDOpcode, 304 Op0, Op0IsKill, 305 Op1, Op1IsKill); 306 if (ResultReg == 0) 307 // Target-specific code wasn't able to find a machine opcode for 308 // the given ISD opcode and type. Halt "fast" selection and bail. 309 return false; 310 311 // We successfully emitted code for the given LLVM Instruction. 312 UpdateValueMap(I, ResultReg); 313 return true; 314} 315 316bool FastISel::SelectGetElementPtr(const User *I) { 317 unsigned N = getRegForValue(I->getOperand(0)); 318 if (N == 0) 319 // Unhandled operand. Halt "fast" selection and bail. 320 return false; 321 322 bool NIsKill = hasTrivialKill(I->getOperand(0)); 323 324 const Type *Ty = I->getOperand(0)->getType(); 325 MVT VT = TLI.getPointerTy(); 326 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1, 327 E = I->op_end(); OI != E; ++OI) { 328 const Value *Idx = *OI; 329 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 330 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 331 if (Field) { 332 // N = N + Offset 333 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 334 // FIXME: This can be optimized by combining the add with a 335 // subsequent one. 336 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT); 337 if (N == 0) 338 // Unhandled operand. Halt "fast" selection and bail. 339 return false; 340 NIsKill = true; 341 } 342 Ty = StTy->getElementType(Field); 343 } else { 344 Ty = cast<SequentialType>(Ty)->getElementType(); 345 346 // If this is a constant subscript, handle it quickly. 347 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 348 if (CI->isZero()) continue; 349 uint64_t Offs = 350 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 351 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT); 352 if (N == 0) 353 // Unhandled operand. Halt "fast" selection and bail. 354 return false; 355 NIsKill = true; 356 continue; 357 } 358 359 // N = N + Idx * ElementSize; 360 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 361 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx); 362 unsigned IdxN = Pair.first; 363 bool IdxNIsKill = Pair.second; 364 if (IdxN == 0) 365 // Unhandled operand. Halt "fast" selection and bail. 366 return false; 367 368 if (ElementSize != 1) { 369 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT); 370 if (IdxN == 0) 371 // Unhandled operand. Halt "fast" selection and bail. 372 return false; 373 IdxNIsKill = true; 374 } 375 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill); 376 if (N == 0) 377 // Unhandled operand. Halt "fast" selection and bail. 378 return false; 379 } 380 } 381 382 // We successfully emitted code for the given LLVM Instruction. 383 UpdateValueMap(I, N); 384 return true; 385} 386 387bool FastISel::SelectCall(const User *I) { 388 const Function *F = cast<CallInst>(I)->getCalledFunction(); 389 if (!F) return false; 390 391 // Handle selected intrinsic function calls. 392 unsigned IID = F->getIntrinsicID(); 393 switch (IID) { 394 default: break; 395 case Intrinsic::dbg_declare: { 396 const DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 397 if (!DIVariable(DI->getVariable()).Verify() || 398 !MF.getMMI().hasDebugInfo()) 399 return true; 400 401 const Value *Address = DI->getAddress(); 402 if (!Address) 403 return true; 404 if (isa<UndefValue>(Address)) 405 return true; 406 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 407 // Don't handle byval struct arguments or VLAs, for example. 408 // Note that if we have a byval struct argument, fast ISel is turned off; 409 // those are handled in SelectionDAGBuilder. 410 if (AI) { 411 DenseMap<const AllocaInst*, int>::iterator SI = 412 StaticAllocaMap.find(AI); 413 if (SI == StaticAllocaMap.end()) break; // VLAs. 414 int FI = SI->second; 415 if (!DI->getDebugLoc().isUnknown()) 416 MF.getMMI().setVariableDbgInfo(DI->getVariable(), FI, DI->getDebugLoc()); 417 } else 418 // Building the map above is target independent. Generating DBG_VALUE 419 // inline is target dependent; do this now. 420 (void)TargetSelectInstruction(cast<Instruction>(I)); 421 return true; 422 } 423 case Intrinsic::dbg_value: { 424 // This form of DBG_VALUE is target-independent. 425 const DbgValueInst *DI = cast<DbgValueInst>(I); 426 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 427 const Value *V = DI->getValue(); 428 if (!V) { 429 // Currently the optimizer can produce this; insert an undef to 430 // help debugging. Probably the optimizer should not do this. 431 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()). 432 addMetadata(DI->getVariable()); 433 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 434 BuildMI(MBB, DL, II).addImm(CI->getZExtValue()).addImm(DI->getOffset()). 435 addMetadata(DI->getVariable()); 436 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 437 BuildMI(MBB, DL, II).addFPImm(CF).addImm(DI->getOffset()). 438 addMetadata(DI->getVariable()); 439 } else if (unsigned Reg = lookUpRegForValue(V)) { 440 BuildMI(MBB, DL, II).addReg(Reg, RegState::Debug).addImm(DI->getOffset()). 441 addMetadata(DI->getVariable()); 442 } else { 443 // We can't yet handle anything else here because it would require 444 // generating code, thus altering codegen because of debug info. 445 // Insert an undef so we can see what we dropped. 446 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()). 447 addMetadata(DI->getVariable()); 448 } 449 return true; 450 } 451 case Intrinsic::eh_exception: { 452 EVT VT = TLI.getValueType(I->getType()); 453 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 454 default: break; 455 case TargetLowering::Expand: { 456 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!"); 457 unsigned Reg = TLI.getExceptionAddressRegister(); 458 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 459 unsigned ResultReg = createResultReg(RC); 460 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 461 Reg, RC, RC, DL); 462 assert(InsertedCopy && "Can't copy address registers!"); 463 InsertedCopy = InsertedCopy; 464 UpdateValueMap(I, ResultReg); 465 return true; 466 } 467 } 468 break; 469 } 470 case Intrinsic::eh_selector: { 471 EVT VT = TLI.getValueType(I->getType()); 472 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 473 default: break; 474 case TargetLowering::Expand: { 475 if (MBB->isLandingPad()) 476 AddCatchInfo(*cast<CallInst>(I), &MF.getMMI(), MBB); 477 else { 478#ifndef NDEBUG 479 CatchInfoLost.insert(cast<CallInst>(I)); 480#endif 481 // FIXME: Mark exception selector register as live in. Hack for PR1508. 482 unsigned Reg = TLI.getExceptionSelectorRegister(); 483 if (Reg) MBB->addLiveIn(Reg); 484 } 485 486 unsigned Reg = TLI.getExceptionSelectorRegister(); 487 EVT SrcVT = TLI.getPointerTy(); 488 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); 489 unsigned ResultReg = createResultReg(RC); 490 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg, 491 RC, RC, DL); 492 assert(InsertedCopy && "Can't copy address registers!"); 493 InsertedCopy = InsertedCopy; 494 495 bool ResultRegIsKill = hasTrivialKill(I); 496 497 // Cast the register to the type of the selector. 498 if (SrcVT.bitsGT(MVT::i32)) 499 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE, 500 ResultReg, ResultRegIsKill); 501 else if (SrcVT.bitsLT(MVT::i32)) 502 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, 503 ISD::SIGN_EXTEND, ResultReg, ResultRegIsKill); 504 if (ResultReg == 0) 505 // Unhandled operand. Halt "fast" selection and bail. 506 return false; 507 508 UpdateValueMap(I, ResultReg); 509 510 return true; 511 } 512 } 513 break; 514 } 515 } 516 517 // An arbitrary call. Bail. 518 return false; 519} 520 521bool FastISel::SelectCast(const User *I, unsigned Opcode) { 522 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 523 EVT DstVT = TLI.getValueType(I->getType()); 524 525 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 526 DstVT == MVT::Other || !DstVT.isSimple()) 527 // Unhandled type. Halt "fast" selection and bail. 528 return false; 529 530 // Check if the destination type is legal. Or as a special case, 531 // it may be i1 if we're doing a truncate because that's 532 // easy and somewhat common. 533 if (!TLI.isTypeLegal(DstVT)) 534 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 535 // Unhandled type. Halt "fast" selection and bail. 536 return false; 537 538 // Check if the source operand is legal. Or as a special case, 539 // it may be i1 if we're doing zero-extension because that's 540 // easy and somewhat common. 541 if (!TLI.isTypeLegal(SrcVT)) 542 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 543 // Unhandled type. Halt "fast" selection and bail. 544 return false; 545 546 unsigned InputReg = getRegForValue(I->getOperand(0)); 547 if (!InputReg) 548 // Unhandled operand. Halt "fast" selection and bail. 549 return false; 550 551 bool InputRegIsKill = hasTrivialKill(I->getOperand(0)); 552 553 // If the operand is i1, arrange for the high bits in the register to be zero. 554 if (SrcVT == MVT::i1) { 555 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT); 556 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg, InputRegIsKill); 557 if (!InputReg) 558 return false; 559 InputRegIsKill = true; 560 } 561 // If the result is i1, truncate to the target's type for i1 first. 562 if (DstVT == MVT::i1) 563 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT); 564 565 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 566 DstVT.getSimpleVT(), 567 Opcode, 568 InputReg, InputRegIsKill); 569 if (!ResultReg) 570 return false; 571 572 UpdateValueMap(I, ResultReg); 573 return true; 574} 575 576bool FastISel::SelectBitCast(const User *I) { 577 // If the bitcast doesn't change the type, just use the operand value. 578 if (I->getType() == I->getOperand(0)->getType()) { 579 unsigned Reg = getRegForValue(I->getOperand(0)); 580 if (Reg == 0) 581 return false; 582 UpdateValueMap(I, Reg); 583 return true; 584 } 585 586 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 587 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 588 EVT DstVT = TLI.getValueType(I->getType()); 589 590 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 591 DstVT == MVT::Other || !DstVT.isSimple() || 592 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 593 // Unhandled type. Halt "fast" selection and bail. 594 return false; 595 596 unsigned Op0 = getRegForValue(I->getOperand(0)); 597 if (Op0 == 0) 598 // Unhandled operand. Halt "fast" selection and bail. 599 return false; 600 601 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 602 603 // First, try to perform the bitcast by inserting a reg-reg copy. 604 unsigned ResultReg = 0; 605 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 606 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 607 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 608 ResultReg = createResultReg(DstClass); 609 610 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 611 Op0, DstClass, SrcClass, DL); 612 if (!InsertedCopy) 613 ResultReg = 0; 614 } 615 616 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 617 if (!ResultReg) 618 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 619 ISD::BIT_CONVERT, Op0, Op0IsKill); 620 621 if (!ResultReg) 622 return false; 623 624 UpdateValueMap(I, ResultReg); 625 return true; 626} 627 628bool 629FastISel::SelectInstruction(const Instruction *I) { 630 // Just before the terminator instruction, insert instructions to 631 // feed PHI nodes in successor blocks. 632 if (isa<TerminatorInst>(I)) 633 if (!HandlePHINodesInSuccessorBlocks(I->getParent())) 634 return false; 635 636 DL = I->getDebugLoc(); 637 638 // First, try doing target-independent selection. 639 if (SelectOperator(I, I->getOpcode())) { 640 DL = DebugLoc(); 641 return true; 642 } 643 644 // Next, try calling the target to attempt to handle the instruction. 645 if (TargetSelectInstruction(I)) { 646 DL = DebugLoc(); 647 return true; 648 } 649 650 DL = DebugLoc(); 651 return false; 652} 653 654/// FastEmitBranch - Emit an unconditional branch to the given block, 655/// unless it is the immediate (fall-through) successor, and update 656/// the CFG. 657void 658FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) { 659 if (MBB->isLayoutSuccessor(MSucc)) { 660 // The unconditional fall-through case, which needs no instructions. 661 } else { 662 // The unconditional branch case. 663 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>(), DL); 664 } 665 MBB->addSuccessor(MSucc); 666} 667 668/// SelectFNeg - Emit an FNeg operation. 669/// 670bool 671FastISel::SelectFNeg(const User *I) { 672 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); 673 if (OpReg == 0) return false; 674 675 bool OpRegIsKill = hasTrivialKill(I); 676 677 // If the target has ISD::FNEG, use it. 678 EVT VT = TLI.getValueType(I->getType()); 679 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), 680 ISD::FNEG, OpReg, OpRegIsKill); 681 if (ResultReg != 0) { 682 UpdateValueMap(I, ResultReg); 683 return true; 684 } 685 686 // Bitcast the value to integer, twiddle the sign bit with xor, 687 // and then bitcast it back to floating-point. 688 if (VT.getSizeInBits() > 64) return false; 689 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); 690 if (!TLI.isTypeLegal(IntVT)) 691 return false; 692 693 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), 694 ISD::BIT_CONVERT, OpReg, OpRegIsKill); 695 if (IntReg == 0) 696 return false; 697 698 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, 699 IntReg, /*Kill=*/true, 700 UINT64_C(1) << (VT.getSizeInBits()-1), 701 IntVT.getSimpleVT()); 702 if (IntResultReg == 0) 703 return false; 704 705 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), 706 ISD::BIT_CONVERT, IntResultReg, /*Kill=*/true); 707 if (ResultReg == 0) 708 return false; 709 710 UpdateValueMap(I, ResultReg); 711 return true; 712} 713 714bool 715FastISel::SelectOperator(const User *I, unsigned Opcode) { 716 switch (Opcode) { 717 case Instruction::Add: 718 return SelectBinaryOp(I, ISD::ADD); 719 case Instruction::FAdd: 720 return SelectBinaryOp(I, ISD::FADD); 721 case Instruction::Sub: 722 return SelectBinaryOp(I, ISD::SUB); 723 case Instruction::FSub: 724 // FNeg is currently represented in LLVM IR as a special case of FSub. 725 if (BinaryOperator::isFNeg(I)) 726 return SelectFNeg(I); 727 return SelectBinaryOp(I, ISD::FSUB); 728 case Instruction::Mul: 729 return SelectBinaryOp(I, ISD::MUL); 730 case Instruction::FMul: 731 return SelectBinaryOp(I, ISD::FMUL); 732 case Instruction::SDiv: 733 return SelectBinaryOp(I, ISD::SDIV); 734 case Instruction::UDiv: 735 return SelectBinaryOp(I, ISD::UDIV); 736 case Instruction::FDiv: 737 return SelectBinaryOp(I, ISD::FDIV); 738 case Instruction::SRem: 739 return SelectBinaryOp(I, ISD::SREM); 740 case Instruction::URem: 741 return SelectBinaryOp(I, ISD::UREM); 742 case Instruction::FRem: 743 return SelectBinaryOp(I, ISD::FREM); 744 case Instruction::Shl: 745 return SelectBinaryOp(I, ISD::SHL); 746 case Instruction::LShr: 747 return SelectBinaryOp(I, ISD::SRL); 748 case Instruction::AShr: 749 return SelectBinaryOp(I, ISD::SRA); 750 case Instruction::And: 751 return SelectBinaryOp(I, ISD::AND); 752 case Instruction::Or: 753 return SelectBinaryOp(I, ISD::OR); 754 case Instruction::Xor: 755 return SelectBinaryOp(I, ISD::XOR); 756 757 case Instruction::GetElementPtr: 758 return SelectGetElementPtr(I); 759 760 case Instruction::Br: { 761 const BranchInst *BI = cast<BranchInst>(I); 762 763 if (BI->isUnconditional()) { 764 const BasicBlock *LLVMSucc = BI->getSuccessor(0); 765 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 766 FastEmitBranch(MSucc, BI->getDebugLoc()); 767 return true; 768 } 769 770 // Conditional branches are not handed yet. 771 // Halt "fast" selection and bail. 772 return false; 773 } 774 775 case Instruction::Unreachable: 776 // Nothing to emit. 777 return true; 778 779 case Instruction::Alloca: 780 // FunctionLowering has the static-sized case covered. 781 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 782 return true; 783 784 // Dynamic-sized alloca is not handled yet. 785 return false; 786 787 case Instruction::Call: 788 return SelectCall(I); 789 790 case Instruction::BitCast: 791 return SelectBitCast(I); 792 793 case Instruction::FPToSI: 794 return SelectCast(I, ISD::FP_TO_SINT); 795 case Instruction::ZExt: 796 return SelectCast(I, ISD::ZERO_EXTEND); 797 case Instruction::SExt: 798 return SelectCast(I, ISD::SIGN_EXTEND); 799 case Instruction::Trunc: 800 return SelectCast(I, ISD::TRUNCATE); 801 case Instruction::SIToFP: 802 return SelectCast(I, ISD::SINT_TO_FP); 803 804 case Instruction::IntToPtr: // Deliberate fall-through. 805 case Instruction::PtrToInt: { 806 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 807 EVT DstVT = TLI.getValueType(I->getType()); 808 if (DstVT.bitsGT(SrcVT)) 809 return SelectCast(I, ISD::ZERO_EXTEND); 810 if (DstVT.bitsLT(SrcVT)) 811 return SelectCast(I, ISD::TRUNCATE); 812 unsigned Reg = getRegForValue(I->getOperand(0)); 813 if (Reg == 0) return false; 814 UpdateValueMap(I, Reg); 815 return true; 816 } 817 818 case Instruction::PHI: 819 llvm_unreachable("FastISel shouldn't visit PHI nodes!"); 820 821 default: 822 // Unhandled instruction. Halt "fast" selection and bail. 823 return false; 824 } 825} 826 827FastISel::FastISel(MachineFunction &mf, 828 DenseMap<const Value *, unsigned> &vm, 829 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 830 DenseMap<const AllocaInst *, int> &am, 831 std::vector<std::pair<MachineInstr*, unsigned> > &pn 832#ifndef NDEBUG 833 , SmallSet<const Instruction *, 8> &cil 834#endif 835 ) 836 : MBB(0), 837 ValueMap(vm), 838 MBBMap(bm), 839 StaticAllocaMap(am), 840 PHINodesToUpdate(pn), 841#ifndef NDEBUG 842 CatchInfoLost(cil), 843#endif 844 MF(mf), 845 MRI(MF.getRegInfo()), 846 MFI(*MF.getFrameInfo()), 847 MCP(*MF.getConstantPool()), 848 TM(MF.getTarget()), 849 TD(*TM.getTargetData()), 850 TII(*TM.getInstrInfo()), 851 TLI(*TM.getTargetLowering()), 852 TRI(*TM.getRegisterInfo()), 853 IsBottomUp(false) { 854} 855 856FastISel::~FastISel() {} 857 858unsigned FastISel::FastEmit_(MVT, MVT, 859 unsigned) { 860 return 0; 861} 862 863unsigned FastISel::FastEmit_r(MVT, MVT, 864 unsigned, 865 unsigned /*Op0*/, bool /*Op0IsKill*/) { 866 return 0; 867} 868 869unsigned FastISel::FastEmit_rr(MVT, MVT, 870 unsigned, 871 unsigned /*Op0*/, bool /*Op0IsKill*/, 872 unsigned /*Op1*/, bool /*Op1IsKill*/) { 873 return 0; 874} 875 876unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) { 877 return 0; 878} 879 880unsigned FastISel::FastEmit_f(MVT, MVT, 881 unsigned, const ConstantFP * /*FPImm*/) { 882 return 0; 883} 884 885unsigned FastISel::FastEmit_ri(MVT, MVT, 886 unsigned, 887 unsigned /*Op0*/, bool /*Op0IsKill*/, 888 uint64_t /*Imm*/) { 889 return 0; 890} 891 892unsigned FastISel::FastEmit_rf(MVT, MVT, 893 unsigned, 894 unsigned /*Op0*/, bool /*Op0IsKill*/, 895 const ConstantFP * /*FPImm*/) { 896 return 0; 897} 898 899unsigned FastISel::FastEmit_rri(MVT, MVT, 900 unsigned, 901 unsigned /*Op0*/, bool /*Op0IsKill*/, 902 unsigned /*Op1*/, bool /*Op1IsKill*/, 903 uint64_t /*Imm*/) { 904 return 0; 905} 906 907/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 908/// to emit an instruction with an immediate operand using FastEmit_ri. 909/// If that fails, it materializes the immediate into a register and try 910/// FastEmit_rr instead. 911unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode, 912 unsigned Op0, bool Op0IsKill, 913 uint64_t Imm, MVT ImmType) { 914 // First check if immediate type is legal. If not, we can't use the ri form. 915 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); 916 if (ResultReg != 0) 917 return ResultReg; 918 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 919 if (MaterialReg == 0) 920 return 0; 921 return FastEmit_rr(VT, VT, Opcode, 922 Op0, Op0IsKill, 923 MaterialReg, /*Kill=*/true); 924} 925 926/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 927/// to emit an instruction with a floating-point immediate operand using 928/// FastEmit_rf. If that fails, it materializes the immediate into a register 929/// and try FastEmit_rr instead. 930unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode, 931 unsigned Op0, bool Op0IsKill, 932 const ConstantFP *FPImm, MVT ImmType) { 933 // First check if immediate type is legal. If not, we can't use the rf form. 934 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, Op0IsKill, FPImm); 935 if (ResultReg != 0) 936 return ResultReg; 937 938 // Materialize the constant in a register. 939 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 940 if (MaterialReg == 0) { 941 // If the target doesn't have a way to directly enter a floating-point 942 // value into a register, use an alternate approach. 943 // TODO: The current approach only supports floating-point constants 944 // that can be constructed by conversion from integer values. This should 945 // be replaced by code that creates a load from a constant-pool entry, 946 // which will require some target-specific work. 947 const APFloat &Flt = FPImm->getValueAPF(); 948 EVT IntVT = TLI.getPointerTy(); 949 950 uint64_t x[2]; 951 uint32_t IntBitWidth = IntVT.getSizeInBits(); 952 bool isExact; 953 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 954 APFloat::rmTowardZero, &isExact); 955 if (!isExact) 956 return 0; 957 APInt IntVal(IntBitWidth, 2, x); 958 959 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 960 ISD::Constant, IntVal.getZExtValue()); 961 if (IntegerReg == 0) 962 return 0; 963 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 964 ISD::SINT_TO_FP, IntegerReg, /*Kill=*/true); 965 if (MaterialReg == 0) 966 return 0; 967 } 968 return FastEmit_rr(VT, VT, Opcode, 969 Op0, Op0IsKill, 970 MaterialReg, /*Kill=*/true); 971} 972 973unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 974 return MRI.createVirtualRegister(RC); 975} 976 977unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 978 const TargetRegisterClass* RC) { 979 unsigned ResultReg = createResultReg(RC); 980 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 981 982 BuildMI(MBB, DL, II, ResultReg); 983 return ResultReg; 984} 985 986unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 987 const TargetRegisterClass *RC, 988 unsigned Op0, bool Op0IsKill) { 989 unsigned ResultReg = createResultReg(RC); 990 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 991 992 if (II.getNumDefs() >= 1) 993 BuildMI(MBB, DL, II, ResultReg).addReg(Op0, Op0IsKill * RegState::Kill); 994 else { 995 BuildMI(MBB, DL, II).addReg(Op0, Op0IsKill * RegState::Kill); 996 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 997 II.ImplicitDefs[0], RC, RC, DL); 998 if (!InsertedCopy) 999 ResultReg = 0; 1000 } 1001 1002 return ResultReg; 1003} 1004 1005unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 1006 const TargetRegisterClass *RC, 1007 unsigned Op0, bool Op0IsKill, 1008 unsigned Op1, bool Op1IsKill) { 1009 unsigned ResultReg = createResultReg(RC); 1010 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1011 1012 if (II.getNumDefs() >= 1) 1013 BuildMI(MBB, DL, II, ResultReg) 1014 .addReg(Op0, Op0IsKill * RegState::Kill) 1015 .addReg(Op1, Op1IsKill * RegState::Kill); 1016 else { 1017 BuildMI(MBB, DL, II) 1018 .addReg(Op0, Op0IsKill * RegState::Kill) 1019 .addReg(Op1, Op1IsKill * RegState::Kill); 1020 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1021 II.ImplicitDefs[0], RC, RC, DL); 1022 if (!InsertedCopy) 1023 ResultReg = 0; 1024 } 1025 return ResultReg; 1026} 1027 1028unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 1029 const TargetRegisterClass *RC, 1030 unsigned Op0, bool Op0IsKill, 1031 uint64_t Imm) { 1032 unsigned ResultReg = createResultReg(RC); 1033 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1034 1035 if (II.getNumDefs() >= 1) 1036 BuildMI(MBB, DL, II, ResultReg) 1037 .addReg(Op0, Op0IsKill * RegState::Kill) 1038 .addImm(Imm); 1039 else { 1040 BuildMI(MBB, DL, II) 1041 .addReg(Op0, Op0IsKill * RegState::Kill) 1042 .addImm(Imm); 1043 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1044 II.ImplicitDefs[0], RC, RC, DL); 1045 if (!InsertedCopy) 1046 ResultReg = 0; 1047 } 1048 return ResultReg; 1049} 1050 1051unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 1052 const TargetRegisterClass *RC, 1053 unsigned Op0, bool Op0IsKill, 1054 const ConstantFP *FPImm) { 1055 unsigned ResultReg = createResultReg(RC); 1056 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1057 1058 if (II.getNumDefs() >= 1) 1059 BuildMI(MBB, DL, II, ResultReg) 1060 .addReg(Op0, Op0IsKill * RegState::Kill) 1061 .addFPImm(FPImm); 1062 else { 1063 BuildMI(MBB, DL, II) 1064 .addReg(Op0, Op0IsKill * RegState::Kill) 1065 .addFPImm(FPImm); 1066 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1067 II.ImplicitDefs[0], RC, RC, DL); 1068 if (!InsertedCopy) 1069 ResultReg = 0; 1070 } 1071 return ResultReg; 1072} 1073 1074unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 1075 const TargetRegisterClass *RC, 1076 unsigned Op0, bool Op0IsKill, 1077 unsigned Op1, bool Op1IsKill, 1078 uint64_t Imm) { 1079 unsigned ResultReg = createResultReg(RC); 1080 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1081 1082 if (II.getNumDefs() >= 1) 1083 BuildMI(MBB, DL, II, ResultReg) 1084 .addReg(Op0, Op0IsKill * RegState::Kill) 1085 .addReg(Op1, Op1IsKill * RegState::Kill) 1086 .addImm(Imm); 1087 else { 1088 BuildMI(MBB, DL, II) 1089 .addReg(Op0, Op0IsKill * RegState::Kill) 1090 .addReg(Op1, Op1IsKill * RegState::Kill) 1091 .addImm(Imm); 1092 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1093 II.ImplicitDefs[0], RC, RC, DL); 1094 if (!InsertedCopy) 1095 ResultReg = 0; 1096 } 1097 return ResultReg; 1098} 1099 1100unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 1101 const TargetRegisterClass *RC, 1102 uint64_t Imm) { 1103 unsigned ResultReg = createResultReg(RC); 1104 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1105 1106 if (II.getNumDefs() >= 1) 1107 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 1108 else { 1109 BuildMI(MBB, DL, II).addImm(Imm); 1110 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1111 II.ImplicitDefs[0], RC, RC, DL); 1112 if (!InsertedCopy) 1113 ResultReg = 0; 1114 } 1115 return ResultReg; 1116} 1117 1118unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, 1119 unsigned Op0, bool Op0IsKill, 1120 uint32_t Idx) { 1121 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 1122 1123 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1124 const TargetInstrDesc &II = TII.get(TargetOpcode::EXTRACT_SUBREG); 1125 1126 if (II.getNumDefs() >= 1) 1127 BuildMI(MBB, DL, II, ResultReg) 1128 .addReg(Op0, Op0IsKill * RegState::Kill) 1129 .addImm(Idx); 1130 else { 1131 BuildMI(MBB, DL, II) 1132 .addReg(Op0, Op0IsKill * RegState::Kill) 1133 .addImm(Idx); 1134 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1135 II.ImplicitDefs[0], RC, RC, DL); 1136 if (!InsertedCopy) 1137 ResultReg = 0; 1138 } 1139 return ResultReg; 1140} 1141 1142/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1143/// with all but the least significant bit set to zero. 1144unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) { 1145 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1); 1146} 1147 1148/// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks. 1149/// Emit code to ensure constants are copied into registers when needed. 1150/// Remember the virtual registers that need to be added to the Machine PHI 1151/// nodes as input. We cannot just directly add them, because expansion 1152/// might result in multiple MBB's for one BB. As such, the start of the 1153/// BB might correspond to a different MBB than the end. 1154bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 1155 const TerminatorInst *TI = LLVMBB->getTerminator(); 1156 1157 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 1158 unsigned OrigNumPHINodesToUpdate = PHINodesToUpdate.size(); 1159 1160 // Check successor nodes' PHI nodes that expect a constant to be available 1161 // from this block. 1162 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 1163 const BasicBlock *SuccBB = TI->getSuccessor(succ); 1164 if (!isa<PHINode>(SuccBB->begin())) continue; 1165 MachineBasicBlock *SuccMBB = MBBMap[SuccBB]; 1166 1167 // If this terminator has multiple identical successors (common for 1168 // switches), only handle each succ once. 1169 if (!SuccsHandled.insert(SuccMBB)) continue; 1170 1171 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 1172 1173 // At this point we know that there is a 1-1 correspondence between LLVM PHI 1174 // nodes and Machine PHI nodes, but the incoming operands have not been 1175 // emitted yet. 1176 for (BasicBlock::const_iterator I = SuccBB->begin(); 1177 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 1178 1179 // Ignore dead phi's. 1180 if (PN->use_empty()) continue; 1181 1182 // Only handle legal types. Two interesting things to note here. First, 1183 // by bailing out early, we may leave behind some dead instructions, 1184 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its 1185 // own moves. Second, this check is necessary becuase FastISel doesn't 1186 // use CreateRegForValue to create registers, so it always creates 1187 // exactly one register for each non-void instruction. 1188 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true); 1189 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) { 1190 // Promote MVT::i1. 1191 if (VT == MVT::i1) 1192 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT); 1193 else { 1194 PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1195 return false; 1196 } 1197 } 1198 1199 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 1200 1201 // Set the DebugLoc for the copy. Prefer the location of the operand 1202 // if there is one; use the location of the PHI otherwise. 1203 DL = PN->getDebugLoc(); 1204 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp)) 1205 DL = Inst->getDebugLoc(); 1206 1207 unsigned Reg = getRegForValue(PHIOp); 1208 if (Reg == 0) { 1209 PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1210 return false; 1211 } 1212 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg)); 1213 DL = DebugLoc(); 1214 } 1215 } 1216 1217 return true; 1218} 1219