FastISel.cpp revision fc1df34dea6dae98d823f9cf95afbb364201ec97
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the implementation of the FastISel class.
11//
12// "Fast" instruction selection is designed to emit very poor code quickly.
13// Also, it is not designed to be able to do much lowering, so most illegal
14// types (e.g. i64 on 32-bit targets) and operations are not supported.  It is
15// also not intended to be able to do much optimization, except in a few cases
16// where doing optimizations reduces overall compile time.  For example, folding
17// constants into immediate fields is often done, because it's cheap and it
18// reduces the number of instructions later phases have to examine.
19//
20// "Fast" instruction selection is able to fail gracefully and transfer
21// control to the SelectionDAG selector for operations that it doesn't
22// support.  In many cases, this allows us to avoid duplicating a lot of
23// the complicated lowering logic that SelectionDAG currently has.
24//
25// The intended use for "fast" instruction selection is "-O0" mode
26// compilation, where the quality of the generated code is irrelevant when
27// weighed against the speed at which the code can be generated.  Also,
28// at -O0, the LLVM optimizers are not running, and this makes the
29// compile time of codegen a much higher portion of the overall compile
30// time.  Despite its limitations, "fast" instruction selection is able to
31// handle enough code on its own to provide noticeable overall speedups
32// in -O0 compiles.
33//
34// Basic operations are supported in a target-independent way, by reading
35// the same instruction descriptions that the SelectionDAG selector reads,
36// and identifying simple arithmetic operations that can be directly selected
37// from simple operators.  More complicated operations currently require
38// target-specific code.
39//
40//===----------------------------------------------------------------------===//
41
42#include "llvm/Function.h"
43#include "llvm/GlobalVariable.h"
44#include "llvm/Instructions.h"
45#include "llvm/IntrinsicInst.h"
46#include "llvm/CodeGen/FastISel.h"
47#include "llvm/CodeGen/MachineInstrBuilder.h"
48#include "llvm/CodeGen/MachineModuleInfo.h"
49#include "llvm/CodeGen/MachineRegisterInfo.h"
50#include "llvm/CodeGen/DwarfWriter.h"
51#include "llvm/Analysis/DebugInfo.h"
52#include "llvm/Target/TargetData.h"
53#include "llvm/Target/TargetInstrInfo.h"
54#include "llvm/Target/TargetLowering.h"
55#include "llvm/Target/TargetMachine.h"
56#include "SelectionDAGBuild.h"
57using namespace llvm;
58
59unsigned FastISel::getRegForValue(Value *V) {
60  EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
61  // Don't handle non-simple values in FastISel.
62  if (!RealVT.isSimple())
63    return 0;
64
65  // Ignore illegal types. We must do this before looking up the value
66  // in ValueMap because Arguments are given virtual registers regardless
67  // of whether FastISel can handle them.
68  MVT VT = RealVT.getSimpleVT();
69  if (!TLI.isTypeLegal(VT)) {
70    // Promote MVT::i1 to a legal type though, because it's common and easy.
71    if (VT == MVT::i1)
72      VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
73    else
74      return 0;
75  }
76
77  // Look up the value to see if we already have a register for it. We
78  // cache values defined by Instructions across blocks, and other values
79  // only locally. This is because Instructions already have the SSA
80  // def-dominatess-use requirement enforced.
81  if (ValueMap.count(V))
82    return ValueMap[V];
83  unsigned Reg = LocalValueMap[V];
84  if (Reg != 0)
85    return Reg;
86
87  if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
88    if (CI->getValue().getActiveBits() <= 64)
89      Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
90  } else if (isa<AllocaInst>(V)) {
91    Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
92  } else if (isa<ConstantPointerNull>(V)) {
93    // Translate this as an integer zero so that it can be
94    // local-CSE'd with actual integer zeros.
95    Reg =
96      getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
97  } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
98    Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
99
100    if (!Reg) {
101      const APFloat &Flt = CF->getValueAPF();
102      EVT IntVT = TLI.getPointerTy();
103
104      uint64_t x[2];
105      uint32_t IntBitWidth = IntVT.getSizeInBits();
106      bool isExact;
107      (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
108                                APFloat::rmTowardZero, &isExact);
109      if (isExact) {
110        APInt IntVal(IntBitWidth, 2, x);
111
112        unsigned IntegerReg =
113          getRegForValue(ConstantInt::get(V->getContext(), IntVal));
114        if (IntegerReg != 0)
115          Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
116      }
117    }
118  } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
119    if (!SelectOperator(CE, CE->getOpcode())) return 0;
120    Reg = LocalValueMap[CE];
121  } else if (isa<UndefValue>(V)) {
122    Reg = createResultReg(TLI.getRegClassFor(VT));
123    BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
124  }
125
126  // If target-independent code couldn't handle the value, give target-specific
127  // code a try.
128  if (!Reg && isa<Constant>(V))
129    Reg = TargetMaterializeConstant(cast<Constant>(V));
130
131  // Don't cache constant materializations in the general ValueMap.
132  // To do so would require tracking what uses they dominate.
133  if (Reg != 0)
134    LocalValueMap[V] = Reg;
135  return Reg;
136}
137
138unsigned FastISel::lookUpRegForValue(Value *V) {
139  // Look up the value to see if we already have a register for it. We
140  // cache values defined by Instructions across blocks, and other values
141  // only locally. This is because Instructions already have the SSA
142  // def-dominatess-use requirement enforced.
143  if (ValueMap.count(V))
144    return ValueMap[V];
145  return LocalValueMap[V];
146}
147
148/// UpdateValueMap - Update the value map to include the new mapping for this
149/// instruction, or insert an extra copy to get the result in a previous
150/// determined register.
151/// NOTE: This is only necessary because we might select a block that uses
152/// a value before we select the block that defines the value.  It might be
153/// possible to fix this by selecting blocks in reverse postorder.
154unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
155  if (!isa<Instruction>(I)) {
156    LocalValueMap[I] = Reg;
157    return Reg;
158  }
159
160  unsigned &AssignedReg = ValueMap[I];
161  if (AssignedReg == 0)
162    AssignedReg = Reg;
163  else if (Reg != AssignedReg) {
164    const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
165    TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
166                     Reg, RegClass, RegClass);
167  }
168  return AssignedReg;
169}
170
171unsigned FastISel::getRegForGEPIndex(Value *Idx) {
172  unsigned IdxN = getRegForValue(Idx);
173  if (IdxN == 0)
174    // Unhandled operand. Halt "fast" selection and bail.
175    return 0;
176
177  // If the index is smaller or larger than intptr_t, truncate or extend it.
178  MVT PtrVT = TLI.getPointerTy();
179  EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
180  if (IdxVT.bitsLT(PtrVT))
181    IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
182  else if (IdxVT.bitsGT(PtrVT))
183    IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN);
184  return IdxN;
185}
186
187/// SelectBinaryOp - Select and emit code for a binary operator instruction,
188/// which has an opcode which directly corresponds to the given ISD opcode.
189///
190bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
191  EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
192  if (VT == MVT::Other || !VT.isSimple())
193    // Unhandled type. Halt "fast" selection and bail.
194    return false;
195
196  // We only handle legal types. For example, on x86-32 the instruction
197  // selector contains all of the 64-bit instructions from x86-64,
198  // under the assumption that i64 won't be used if the target doesn't
199  // support it.
200  if (!TLI.isTypeLegal(VT)) {
201    // MVT::i1 is special. Allow AND, OR, or XOR because they
202    // don't require additional zeroing, which makes them easy.
203    if (VT == MVT::i1 &&
204        (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
205         ISDOpcode == ISD::XOR))
206      VT = TLI.getTypeToTransformTo(I->getContext(), VT);
207    else
208      return false;
209  }
210
211  unsigned Op0 = getRegForValue(I->getOperand(0));
212  if (Op0 == 0)
213    // Unhandled operand. Halt "fast" selection and bail.
214    return false;
215
216  // Check if the second operand is a constant and handle it appropriately.
217  if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
218    unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
219                                     ISDOpcode, Op0, CI->getZExtValue());
220    if (ResultReg != 0) {
221      // We successfully emitted code for the given LLVM Instruction.
222      UpdateValueMap(I, ResultReg);
223      return true;
224    }
225  }
226
227  // Check if the second operand is a constant float.
228  if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
229    unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
230                                     ISDOpcode, Op0, CF);
231    if (ResultReg != 0) {
232      // We successfully emitted code for the given LLVM Instruction.
233      UpdateValueMap(I, ResultReg);
234      return true;
235    }
236  }
237
238  unsigned Op1 = getRegForValue(I->getOperand(1));
239  if (Op1 == 0)
240    // Unhandled operand. Halt "fast" selection and bail.
241    return false;
242
243  // Now we have both operands in registers. Emit the instruction.
244  unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
245                                   ISDOpcode, Op0, Op1);
246  if (ResultReg == 0)
247    // Target-specific code wasn't able to find a machine opcode for
248    // the given ISD opcode and type. Halt "fast" selection and bail.
249    return false;
250
251  // We successfully emitted code for the given LLVM Instruction.
252  UpdateValueMap(I, ResultReg);
253  return true;
254}
255
256bool FastISel::SelectGetElementPtr(User *I) {
257  unsigned N = getRegForValue(I->getOperand(0));
258  if (N == 0)
259    // Unhandled operand. Halt "fast" selection and bail.
260    return false;
261
262  const Type *Ty = I->getOperand(0)->getType();
263  MVT VT = TLI.getPointerTy();
264  for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
265       OI != E; ++OI) {
266    Value *Idx = *OI;
267    if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
268      unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
269      if (Field) {
270        // N = N + Offset
271        uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
272        // FIXME: This can be optimized by combining the add with a
273        // subsequent one.
274        N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
275        if (N == 0)
276          // Unhandled operand. Halt "fast" selection and bail.
277          return false;
278      }
279      Ty = StTy->getElementType(Field);
280    } else {
281      Ty = cast<SequentialType>(Ty)->getElementType();
282
283      // If this is a constant subscript, handle it quickly.
284      if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
285        if (CI->getZExtValue() == 0) continue;
286        uint64_t Offs =
287          TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
288        N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
289        if (N == 0)
290          // Unhandled operand. Halt "fast" selection and bail.
291          return false;
292        continue;
293      }
294
295      // N = N + Idx * ElementSize;
296      uint64_t ElementSize = TD.getTypeAllocSize(Ty);
297      unsigned IdxN = getRegForGEPIndex(Idx);
298      if (IdxN == 0)
299        // Unhandled operand. Halt "fast" selection and bail.
300        return false;
301
302      if (ElementSize != 1) {
303        IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
304        if (IdxN == 0)
305          // Unhandled operand. Halt "fast" selection and bail.
306          return false;
307      }
308      N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
309      if (N == 0)
310        // Unhandled operand. Halt "fast" selection and bail.
311        return false;
312    }
313  }
314
315  // We successfully emitted code for the given LLVM Instruction.
316  UpdateValueMap(I, N);
317  return true;
318}
319
320bool FastISel::SelectCall(User *I) {
321  Function *F = cast<CallInst>(I)->getCalledFunction();
322  if (!F) return false;
323
324  unsigned IID = F->getIntrinsicID();
325  switch (IID) {
326  default: break;
327  case Intrinsic::dbg_stoppoint: {
328    DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
329    if (isValidDebugInfoIntrinsic(*SPI, CodeGenOpt::None))
330      setCurDebugLoc(ExtractDebugLocation(*SPI, MF.getDebugLocInfo()));
331    return true;
332  }
333  case Intrinsic::dbg_region_start: {
334    DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
335    if (isValidDebugInfoIntrinsic(*RSI, CodeGenOpt::None) && DW
336        && DW->ShouldEmitDwarfDebug()) {
337      unsigned ID =
338        DW->RecordRegionStart(RSI->getContext());
339      const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
340      BuildMI(MBB, DL, II).addImm(ID);
341    }
342    return true;
343  }
344  case Intrinsic::dbg_region_end: {
345    DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
346    if (isValidDebugInfoIntrinsic(*REI, CodeGenOpt::None) && DW
347        && DW->ShouldEmitDwarfDebug()) {
348     unsigned ID = 0;
349     DISubprogram Subprogram(REI->getContext());
350     if (isInlinedFnEnd(*REI, MF.getFunction())) {
351        // This is end of an inlined function.
352        const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
353        ID = DW->RecordInlinedFnEnd(Subprogram);
354        if (ID)
355          // Returned ID is 0 if this is unbalanced "end of inlined
356          // scope". This could happen if optimizer eats dbg intrinsics
357          // or "beginning of inlined scope" is not recoginized due to
358          // missing location info. In such cases, ignore this region.end.
359          BuildMI(MBB, DL, II).addImm(ID);
360      } else {
361        const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
362        ID =  DW->RecordRegionEnd(REI->getContext());
363        BuildMI(MBB, DL, II).addImm(ID);
364      }
365    }
366    return true;
367  }
368  case Intrinsic::dbg_func_start: {
369    DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
370    if (!isValidDebugInfoIntrinsic(*FSI, CodeGenOpt::None) || !DW
371        || !DW->ShouldEmitDwarfDebug())
372      return true;
373
374    if (isInlinedFnStart(*FSI, MF.getFunction())) {
375      // This is a beginning of an inlined function.
376
377      // If llvm.dbg.func.start is seen in a new block before any
378      // llvm.dbg.stoppoint intrinsic then the location info is unknown.
379      // FIXME : Why DebugLoc is reset at the beginning of each block ?
380      DebugLoc PrevLoc = DL;
381      if (PrevLoc.isUnknown())
382        return true;
383      // Record the source line.
384      setCurDebugLoc(ExtractDebugLocation(*FSI, MF.getDebugLocInfo()));
385
386      DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
387      DISubprogram SP(FSI->getSubprogram());
388      unsigned LabelID =
389        DW->RecordInlinedFnStart(SP,DICompileUnit(PrevLocTpl.Scope),
390                                 PrevLocTpl.Line, PrevLocTpl.Col);
391      const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
392      BuildMI(MBB, DL, II).addImm(LabelID);
393      return true;
394    }
395
396    // This is a beginning of a new function.
397    MF.setDefaultDebugLoc(ExtractDebugLocation(*FSI, MF.getDebugLocInfo()));
398
399    // llvm.dbg.func_start also defines beginning of function scope.
400    DW->RecordRegionStart(FSI->getSubprogram());
401    return true;
402  }
403  case Intrinsic::dbg_declare: {
404    DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
405    if (!isValidDebugInfoIntrinsic(*DI, CodeGenOpt::None) || !DW
406        || !DW->ShouldEmitDwarfDebug())
407      return true;
408
409    Value *Address = DI->getAddress();
410    if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
411      Address = BCI->getOperand(0);
412    AllocaInst *AI = dyn_cast<AllocaInst>(Address);
413    // Don't handle byval struct arguments or VLAs, for example.
414    if (!AI) break;
415    DenseMap<const AllocaInst*, int>::iterator SI =
416      StaticAllocaMap.find(AI);
417    if (SI == StaticAllocaMap.end()) break; // VLAs.
418    int FI = SI->second;
419    if (MMI)
420      MMI->setVariableDbgInfo(DI->getVariable(), FI);
421#ifndef ATTACH_DEBUG_INFO_TO_AN_INSN
422    DW->RecordVariable(DI->getVariable(), FI);
423#endif
424    return true;
425  }
426  case Intrinsic::eh_exception: {
427    EVT VT = TLI.getValueType(I->getType());
428    switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
429    default: break;
430    case TargetLowering::Expand: {
431      assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
432      unsigned Reg = TLI.getExceptionAddressRegister();
433      const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
434      unsigned ResultReg = createResultReg(RC);
435      bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
436                                           Reg, RC, RC);
437      assert(InsertedCopy && "Can't copy address registers!");
438      InsertedCopy = InsertedCopy;
439      UpdateValueMap(I, ResultReg);
440      return true;
441    }
442    }
443    break;
444  }
445  case Intrinsic::eh_selector_i32:
446  case Intrinsic::eh_selector_i64: {
447    EVT VT = TLI.getValueType(I->getType());
448    switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
449    default: break;
450    case TargetLowering::Expand: {
451      EVT VT = (IID == Intrinsic::eh_selector_i32 ?
452                           MVT::i32 : MVT::i64);
453
454      if (MMI) {
455        if (MBB->isLandingPad())
456          AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
457        else {
458#ifndef NDEBUG
459          CatchInfoLost.insert(cast<CallInst>(I));
460#endif
461          // FIXME: Mark exception selector register as live in.  Hack for PR1508.
462          unsigned Reg = TLI.getExceptionSelectorRegister();
463          if (Reg) MBB->addLiveIn(Reg);
464        }
465
466        unsigned Reg = TLI.getExceptionSelectorRegister();
467        const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
468        unsigned ResultReg = createResultReg(RC);
469        bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
470                                             Reg, RC, RC);
471        assert(InsertedCopy && "Can't copy address registers!");
472        InsertedCopy = InsertedCopy;
473        UpdateValueMap(I, ResultReg);
474      } else {
475        unsigned ResultReg =
476          getRegForValue(Constant::getNullValue(I->getType()));
477        UpdateValueMap(I, ResultReg);
478      }
479      return true;
480    }
481    }
482    break;
483  }
484  }
485  return false;
486}
487
488bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
489  EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
490  EVT DstVT = TLI.getValueType(I->getType());
491
492  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
493      DstVT == MVT::Other || !DstVT.isSimple())
494    // Unhandled type. Halt "fast" selection and bail.
495    return false;
496
497  // Check if the destination type is legal. Or as a special case,
498  // it may be i1 if we're doing a truncate because that's
499  // easy and somewhat common.
500  if (!TLI.isTypeLegal(DstVT))
501    if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
502      // Unhandled type. Halt "fast" selection and bail.
503      return false;
504
505  // Check if the source operand is legal. Or as a special case,
506  // it may be i1 if we're doing zero-extension because that's
507  // easy and somewhat common.
508  if (!TLI.isTypeLegal(SrcVT))
509    if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
510      // Unhandled type. Halt "fast" selection and bail.
511      return false;
512
513  unsigned InputReg = getRegForValue(I->getOperand(0));
514  if (!InputReg)
515    // Unhandled operand.  Halt "fast" selection and bail.
516    return false;
517
518  // If the operand is i1, arrange for the high bits in the register to be zero.
519  if (SrcVT == MVT::i1) {
520   SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT);
521   InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
522   if (!InputReg)
523     return false;
524  }
525  // If the result is i1, truncate to the target's type for i1 first.
526  if (DstVT == MVT::i1)
527    DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT);
528
529  unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
530                                  DstVT.getSimpleVT(),
531                                  Opcode,
532                                  InputReg);
533  if (!ResultReg)
534    return false;
535
536  UpdateValueMap(I, ResultReg);
537  return true;
538}
539
540bool FastISel::SelectBitCast(User *I) {
541  // If the bitcast doesn't change the type, just use the operand value.
542  if (I->getType() == I->getOperand(0)->getType()) {
543    unsigned Reg = getRegForValue(I->getOperand(0));
544    if (Reg == 0)
545      return false;
546    UpdateValueMap(I, Reg);
547    return true;
548  }
549
550  // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
551  EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
552  EVT DstVT = TLI.getValueType(I->getType());
553
554  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
555      DstVT == MVT::Other || !DstVT.isSimple() ||
556      !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
557    // Unhandled type. Halt "fast" selection and bail.
558    return false;
559
560  unsigned Op0 = getRegForValue(I->getOperand(0));
561  if (Op0 == 0)
562    // Unhandled operand. Halt "fast" selection and bail.
563    return false;
564
565  // First, try to perform the bitcast by inserting a reg-reg copy.
566  unsigned ResultReg = 0;
567  if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
568    TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
569    TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
570    ResultReg = createResultReg(DstClass);
571
572    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
573                                         Op0, DstClass, SrcClass);
574    if (!InsertedCopy)
575      ResultReg = 0;
576  }
577
578  // If the reg-reg copy failed, select a BIT_CONVERT opcode.
579  if (!ResultReg)
580    ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
581                           ISD::BIT_CONVERT, Op0);
582
583  if (!ResultReg)
584    return false;
585
586  UpdateValueMap(I, ResultReg);
587  return true;
588}
589
590bool
591FastISel::SelectInstruction(Instruction *I) {
592  return SelectOperator(I, I->getOpcode());
593}
594
595/// FastEmitBranch - Emit an unconditional branch to the given block,
596/// unless it is the immediate (fall-through) successor, and update
597/// the CFG.
598void
599FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
600  MachineFunction::iterator NextMBB =
601     next(MachineFunction::iterator(MBB));
602
603  if (MBB->isLayoutSuccessor(MSucc)) {
604    // The unconditional fall-through case, which needs no instructions.
605  } else {
606    // The unconditional branch case.
607    TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
608  }
609  MBB->addSuccessor(MSucc);
610}
611
612/// SelectFNeg - Emit an FNeg operation.
613///
614bool
615FastISel::SelectFNeg(User *I) {
616  unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
617  if (OpReg == 0) return false;
618
619  // If the target has ISD::FNEG, use it.
620  EVT VT = TLI.getValueType(I->getType());
621  unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
622                                  ISD::FNEG, OpReg);
623  if (ResultReg != 0) {
624    UpdateValueMap(I, ResultReg);
625    return true;
626  }
627
628  // Bitcast the value to integer, twiddle the sign bit with xor,
629  // and then bitcast it back to floating-point.
630  if (VT.getSizeInBits() > 64) return false;
631  EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
632  if (!TLI.isTypeLegal(IntVT))
633    return false;
634
635  unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
636                               ISD::BIT_CONVERT, OpReg);
637  if (IntReg == 0)
638    return false;
639
640  unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg,
641                                       UINT64_C(1) << (VT.getSizeInBits()-1),
642                                       IntVT.getSimpleVT());
643  if (IntResultReg == 0)
644    return false;
645
646  ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
647                         ISD::BIT_CONVERT, IntResultReg);
648  if (ResultReg == 0)
649    return false;
650
651  UpdateValueMap(I, ResultReg);
652  return true;
653}
654
655bool
656FastISel::SelectOperator(User *I, unsigned Opcode) {
657  switch (Opcode) {
658  case Instruction::Add:
659    return SelectBinaryOp(I, ISD::ADD);
660  case Instruction::FAdd:
661    return SelectBinaryOp(I, ISD::FADD);
662  case Instruction::Sub:
663    return SelectBinaryOp(I, ISD::SUB);
664  case Instruction::FSub:
665    // FNeg is currently represented in LLVM IR as a special case of FSub.
666    if (BinaryOperator::isFNeg(I))
667      return SelectFNeg(I);
668    return SelectBinaryOp(I, ISD::FSUB);
669  case Instruction::Mul:
670    return SelectBinaryOp(I, ISD::MUL);
671  case Instruction::FMul:
672    return SelectBinaryOp(I, ISD::FMUL);
673  case Instruction::SDiv:
674    return SelectBinaryOp(I, ISD::SDIV);
675  case Instruction::UDiv:
676    return SelectBinaryOp(I, ISD::UDIV);
677  case Instruction::FDiv:
678    return SelectBinaryOp(I, ISD::FDIV);
679  case Instruction::SRem:
680    return SelectBinaryOp(I, ISD::SREM);
681  case Instruction::URem:
682    return SelectBinaryOp(I, ISD::UREM);
683  case Instruction::FRem:
684    return SelectBinaryOp(I, ISD::FREM);
685  case Instruction::Shl:
686    return SelectBinaryOp(I, ISD::SHL);
687  case Instruction::LShr:
688    return SelectBinaryOp(I, ISD::SRL);
689  case Instruction::AShr:
690    return SelectBinaryOp(I, ISD::SRA);
691  case Instruction::And:
692    return SelectBinaryOp(I, ISD::AND);
693  case Instruction::Or:
694    return SelectBinaryOp(I, ISD::OR);
695  case Instruction::Xor:
696    return SelectBinaryOp(I, ISD::XOR);
697
698  case Instruction::GetElementPtr:
699    return SelectGetElementPtr(I);
700
701  case Instruction::Br: {
702    BranchInst *BI = cast<BranchInst>(I);
703
704    if (BI->isUnconditional()) {
705      BasicBlock *LLVMSucc = BI->getSuccessor(0);
706      MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
707      FastEmitBranch(MSucc);
708      return true;
709    }
710
711    // Conditional branches are not handed yet.
712    // Halt "fast" selection and bail.
713    return false;
714  }
715
716  case Instruction::Unreachable:
717    // Nothing to emit.
718    return true;
719
720  case Instruction::PHI:
721    // PHI nodes are already emitted.
722    return true;
723
724  case Instruction::Alloca:
725    // FunctionLowering has the static-sized case covered.
726    if (StaticAllocaMap.count(cast<AllocaInst>(I)))
727      return true;
728
729    // Dynamic-sized alloca is not handled yet.
730    return false;
731
732  case Instruction::Call:
733    return SelectCall(I);
734
735  case Instruction::BitCast:
736    return SelectBitCast(I);
737
738  case Instruction::FPToSI:
739    return SelectCast(I, ISD::FP_TO_SINT);
740  case Instruction::ZExt:
741    return SelectCast(I, ISD::ZERO_EXTEND);
742  case Instruction::SExt:
743    return SelectCast(I, ISD::SIGN_EXTEND);
744  case Instruction::Trunc:
745    return SelectCast(I, ISD::TRUNCATE);
746  case Instruction::SIToFP:
747    return SelectCast(I, ISD::SINT_TO_FP);
748
749  case Instruction::IntToPtr: // Deliberate fall-through.
750  case Instruction::PtrToInt: {
751    EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
752    EVT DstVT = TLI.getValueType(I->getType());
753    if (DstVT.bitsGT(SrcVT))
754      return SelectCast(I, ISD::ZERO_EXTEND);
755    if (DstVT.bitsLT(SrcVT))
756      return SelectCast(I, ISD::TRUNCATE);
757    unsigned Reg = getRegForValue(I->getOperand(0));
758    if (Reg == 0) return false;
759    UpdateValueMap(I, Reg);
760    return true;
761  }
762
763  default:
764    // Unhandled instruction. Halt "fast" selection and bail.
765    return false;
766  }
767}
768
769FastISel::FastISel(MachineFunction &mf,
770                   MachineModuleInfo *mmi,
771                   DwarfWriter *dw,
772                   DenseMap<const Value *, unsigned> &vm,
773                   DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
774                   DenseMap<const AllocaInst *, int> &am
775#ifndef NDEBUG
776                   , SmallSet<Instruction*, 8> &cil
777#endif
778                   )
779  : MBB(0),
780    ValueMap(vm),
781    MBBMap(bm),
782    StaticAllocaMap(am),
783#ifndef NDEBUG
784    CatchInfoLost(cil),
785#endif
786    MF(mf),
787    MMI(mmi),
788    DW(dw),
789    MRI(MF.getRegInfo()),
790    MFI(*MF.getFrameInfo()),
791    MCP(*MF.getConstantPool()),
792    TM(MF.getTarget()),
793    TD(*TM.getTargetData()),
794    TII(*TM.getInstrInfo()),
795    TLI(*TM.getTargetLowering()) {
796}
797
798FastISel::~FastISel() {}
799
800unsigned FastISel::FastEmit_(MVT, MVT,
801                             ISD::NodeType) {
802  return 0;
803}
804
805unsigned FastISel::FastEmit_r(MVT, MVT,
806                              ISD::NodeType, unsigned /*Op0*/) {
807  return 0;
808}
809
810unsigned FastISel::FastEmit_rr(MVT, MVT,
811                               ISD::NodeType, unsigned /*Op0*/,
812                               unsigned /*Op0*/) {
813  return 0;
814}
815
816unsigned FastISel::FastEmit_i(MVT, MVT, ISD::NodeType, uint64_t /*Imm*/) {
817  return 0;
818}
819
820unsigned FastISel::FastEmit_f(MVT, MVT,
821                              ISD::NodeType, ConstantFP * /*FPImm*/) {
822  return 0;
823}
824
825unsigned FastISel::FastEmit_ri(MVT, MVT,
826                               ISD::NodeType, unsigned /*Op0*/,
827                               uint64_t /*Imm*/) {
828  return 0;
829}
830
831unsigned FastISel::FastEmit_rf(MVT, MVT,
832                               ISD::NodeType, unsigned /*Op0*/,
833                               ConstantFP * /*FPImm*/) {
834  return 0;
835}
836
837unsigned FastISel::FastEmit_rri(MVT, MVT,
838                                ISD::NodeType,
839                                unsigned /*Op0*/, unsigned /*Op1*/,
840                                uint64_t /*Imm*/) {
841  return 0;
842}
843
844/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
845/// to emit an instruction with an immediate operand using FastEmit_ri.
846/// If that fails, it materializes the immediate into a register and try
847/// FastEmit_rr instead.
848unsigned FastISel::FastEmit_ri_(MVT VT, ISD::NodeType Opcode,
849                                unsigned Op0, uint64_t Imm,
850                                MVT ImmType) {
851  // First check if immediate type is legal. If not, we can't use the ri form.
852  unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
853  if (ResultReg != 0)
854    return ResultReg;
855  unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
856  if (MaterialReg == 0)
857    return 0;
858  return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
859}
860
861/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
862/// to emit an instruction with a floating-point immediate operand using
863/// FastEmit_rf. If that fails, it materializes the immediate into a register
864/// and try FastEmit_rr instead.
865unsigned FastISel::FastEmit_rf_(MVT VT, ISD::NodeType Opcode,
866                                unsigned Op0, ConstantFP *FPImm,
867                                MVT ImmType) {
868  // First check if immediate type is legal. If not, we can't use the rf form.
869  unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
870  if (ResultReg != 0)
871    return ResultReg;
872
873  // Materialize the constant in a register.
874  unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
875  if (MaterialReg == 0) {
876    // If the target doesn't have a way to directly enter a floating-point
877    // value into a register, use an alternate approach.
878    // TODO: The current approach only supports floating-point constants
879    // that can be constructed by conversion from integer values. This should
880    // be replaced by code that creates a load from a constant-pool entry,
881    // which will require some target-specific work.
882    const APFloat &Flt = FPImm->getValueAPF();
883    EVT IntVT = TLI.getPointerTy();
884
885    uint64_t x[2];
886    uint32_t IntBitWidth = IntVT.getSizeInBits();
887    bool isExact;
888    (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
889                             APFloat::rmTowardZero, &isExact);
890    if (!isExact)
891      return 0;
892    APInt IntVal(IntBitWidth, 2, x);
893
894    unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
895                                     ISD::Constant, IntVal.getZExtValue());
896    if (IntegerReg == 0)
897      return 0;
898    MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
899                             ISD::SINT_TO_FP, IntegerReg);
900    if (MaterialReg == 0)
901      return 0;
902  }
903  return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
904}
905
906unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
907  return MRI.createVirtualRegister(RC);
908}
909
910unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
911                                 const TargetRegisterClass* RC) {
912  unsigned ResultReg = createResultReg(RC);
913  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
914
915  BuildMI(MBB, DL, II, ResultReg);
916  return ResultReg;
917}
918
919unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
920                                  const TargetRegisterClass *RC,
921                                  unsigned Op0) {
922  unsigned ResultReg = createResultReg(RC);
923  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
924
925  if (II.getNumDefs() >= 1)
926    BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
927  else {
928    BuildMI(MBB, DL, II).addReg(Op0);
929    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
930                                         II.ImplicitDefs[0], RC, RC);
931    if (!InsertedCopy)
932      ResultReg = 0;
933  }
934
935  return ResultReg;
936}
937
938unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
939                                   const TargetRegisterClass *RC,
940                                   unsigned Op0, unsigned Op1) {
941  unsigned ResultReg = createResultReg(RC);
942  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
943
944  if (II.getNumDefs() >= 1)
945    BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
946  else {
947    BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
948    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
949                                         II.ImplicitDefs[0], RC, RC);
950    if (!InsertedCopy)
951      ResultReg = 0;
952  }
953  return ResultReg;
954}
955
956unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
957                                   const TargetRegisterClass *RC,
958                                   unsigned Op0, uint64_t Imm) {
959  unsigned ResultReg = createResultReg(RC);
960  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
961
962  if (II.getNumDefs() >= 1)
963    BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
964  else {
965    BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
966    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
967                                         II.ImplicitDefs[0], RC, RC);
968    if (!InsertedCopy)
969      ResultReg = 0;
970  }
971  return ResultReg;
972}
973
974unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
975                                   const TargetRegisterClass *RC,
976                                   unsigned Op0, ConstantFP *FPImm) {
977  unsigned ResultReg = createResultReg(RC);
978  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
979
980  if (II.getNumDefs() >= 1)
981    BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
982  else {
983    BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
984    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
985                                         II.ImplicitDefs[0], RC, RC);
986    if (!InsertedCopy)
987      ResultReg = 0;
988  }
989  return ResultReg;
990}
991
992unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
993                                    const TargetRegisterClass *RC,
994                                    unsigned Op0, unsigned Op1, uint64_t Imm) {
995  unsigned ResultReg = createResultReg(RC);
996  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
997
998  if (II.getNumDefs() >= 1)
999    BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
1000  else {
1001    BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
1002    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1003                                         II.ImplicitDefs[0], RC, RC);
1004    if (!InsertedCopy)
1005      ResultReg = 0;
1006  }
1007  return ResultReg;
1008}
1009
1010unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
1011                                  const TargetRegisterClass *RC,
1012                                  uint64_t Imm) {
1013  unsigned ResultReg = createResultReg(RC);
1014  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1015
1016  if (II.getNumDefs() >= 1)
1017    BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
1018  else {
1019    BuildMI(MBB, DL, II).addImm(Imm);
1020    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1021                                         II.ImplicitDefs[0], RC, RC);
1022    if (!InsertedCopy)
1023      ResultReg = 0;
1024  }
1025  return ResultReg;
1026}
1027
1028unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
1029                                              unsigned Op0, uint32_t Idx) {
1030  const TargetRegisterClass* RC = MRI.getRegClass(Op0);
1031
1032  unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1033  const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
1034
1035  if (II.getNumDefs() >= 1)
1036    BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
1037  else {
1038    BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
1039    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1040                                         II.ImplicitDefs[0], RC, RC);
1041    if (!InsertedCopy)
1042      ResultReg = 0;
1043  }
1044  return ResultReg;
1045}
1046
1047/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1048/// with all but the least significant bit set to zero.
1049unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) {
1050  return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
1051}
1052