InstrEmitter.cpp revision 3a401bcd04e3a04eea9e91649e1a820ff7cc60c1
1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the Emit routines for the SelectionDAG class, which creates 11// MachineInstrs based on the decisions of the SelectionDAG instruction 12// selection. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "instr-emitter" 17#include "InstrEmitter.h" 18#include "SDNodeDbgValue.h" 19#include "llvm/CodeGen/MachineConstantPool.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetInstrInfo.h" 26#include "llvm/Target/TargetLowering.h" 27#include "llvm/ADT/Statistic.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31using namespace llvm; 32 33/// CountResults - The results of target nodes have register or immediate 34/// operands first, then an optional chain, and optional flag operands (which do 35/// not go into the resulting MachineInstr). 36unsigned InstrEmitter::CountResults(SDNode *Node) { 37 unsigned N = Node->getNumValues(); 38 while (N && Node->getValueType(N - 1) == MVT::Flag) 39 --N; 40 if (N && Node->getValueType(N - 1) == MVT::Other) 41 --N; // Skip over chain result. 42 return N; 43} 44 45/// CountOperands - The inputs to target nodes have any actual inputs first, 46/// followed by an optional chain operand, then an optional flag operand. 47/// Compute the number of actual operands that will go into the resulting 48/// MachineInstr. 49unsigned InstrEmitter::CountOperands(SDNode *Node) { 50 unsigned N = Node->getNumOperands(); 51 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) 52 --N; 53 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 54 --N; // Ignore chain if it exists. 55 return N; 56} 57 58/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 59/// implicit physical register output. 60void InstrEmitter:: 61EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 62 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 63 unsigned VRBase = 0; 64 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 65 // Just use the input register directly! 66 SDValue Op(Node, ResNo); 67 if (IsClone) 68 VRBaseMap.erase(Op); 69 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 70 isNew = isNew; // Silence compiler warning. 71 assert(isNew && "Node emitted out of order - early"); 72 return; 73 } 74 75 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 76 // the CopyToReg'd destination register instead of creating a new vreg. 77 bool MatchReg = true; 78 const TargetRegisterClass *UseRC = NULL; 79 if (!IsClone && !IsCloned) 80 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 81 UI != E; ++UI) { 82 SDNode *User = *UI; 83 bool Match = true; 84 if (User->getOpcode() == ISD::CopyToReg && 85 User->getOperand(2).getNode() == Node && 86 User->getOperand(2).getResNo() == ResNo) { 87 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 88 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 89 VRBase = DestReg; 90 Match = false; 91 } else if (DestReg != SrcReg) 92 Match = false; 93 } else { 94 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 95 SDValue Op = User->getOperand(i); 96 if (Op.getNode() != Node || Op.getResNo() != ResNo) 97 continue; 98 EVT VT = Node->getValueType(Op.getResNo()); 99 if (VT == MVT::Other || VT == MVT::Flag) 100 continue; 101 Match = false; 102 if (User->isMachineOpcode()) { 103 const TargetInstrDesc &II = TII->get(User->getMachineOpcode()); 104 const TargetRegisterClass *RC = 0; 105 if (i+II.getNumDefs() < II.getNumOperands()) 106 RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI); 107 if (!UseRC) 108 UseRC = RC; 109 else if (RC) { 110 const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC); 111 // If multiple uses expect disjoint register classes, we emit 112 // copies in AddRegisterOperand. 113 if (ComRC) 114 UseRC = ComRC; 115 } 116 } 117 } 118 } 119 MatchReg &= Match; 120 if (VRBase) 121 break; 122 } 123 124 EVT VT = Node->getValueType(ResNo); 125 const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 126 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT); 127 128 // Figure out the register class to create for the destreg. 129 if (VRBase) { 130 DstRC = MRI->getRegClass(VRBase); 131 } else if (UseRC) { 132 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 133 DstRC = UseRC; 134 } else { 135 DstRC = TLI->getRegClassFor(VT); 136 } 137 138 // If all uses are reading from the src physical register and copying the 139 // register is either impossible or very expensive, then don't create a copy. 140 if (MatchReg && SrcRC->getCopyCost() < 0) { 141 VRBase = SrcReg; 142 } else { 143 // Create the reg, emit the copy. 144 VRBase = MRI->createVirtualRegister(DstRC); 145 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg, 146 DstRC, SrcRC); 147 148 assert(Emitted && "Unable to issue a copy instruction!\n"); 149 (void) Emitted; 150 } 151 152 SDValue Op(Node, ResNo); 153 if (IsClone) 154 VRBaseMap.erase(Op); 155 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 156 isNew = isNew; // Silence compiler warning. 157 assert(isNew && "Node emitted out of order - early"); 158} 159 160/// getDstOfCopyToRegUse - If the only use of the specified result number of 161/// node is a CopyToReg, return its destination register. Return 0 otherwise. 162unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 163 unsigned ResNo) const { 164 if (!Node->hasOneUse()) 165 return 0; 166 167 SDNode *User = *Node->use_begin(); 168 if (User->getOpcode() == ISD::CopyToReg && 169 User->getOperand(2).getNode() == Node && 170 User->getOperand(2).getResNo() == ResNo) { 171 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 172 if (TargetRegisterInfo::isVirtualRegister(Reg)) 173 return Reg; 174 } 175 return 0; 176} 177 178void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 179 const TargetInstrDesc &II, 180 bool IsClone, bool IsCloned, 181 DenseMap<SDValue, unsigned> &VRBaseMap) { 182 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 183 "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 184 185 for (unsigned i = 0; i < II.getNumDefs(); ++i) { 186 // If the specific node value is only used by a CopyToReg and the dest reg 187 // is a vreg in the same register class, use the CopyToReg'd destination 188 // register instead of creating a new vreg. 189 unsigned VRBase = 0; 190 const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI); 191 if (II.OpInfo[i].isOptionalDef()) { 192 // Optional def must be a physical register. 193 unsigned NumResults = CountResults(Node); 194 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 195 assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 196 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 197 } 198 199 if (!VRBase && !IsClone && !IsCloned) 200 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 201 UI != E; ++UI) { 202 SDNode *User = *UI; 203 if (User->getOpcode() == ISD::CopyToReg && 204 User->getOperand(2).getNode() == Node && 205 User->getOperand(2).getResNo() == i) { 206 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 207 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 208 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 209 if (RegRC == RC) { 210 VRBase = Reg; 211 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 212 break; 213 } 214 } 215 } 216 } 217 218 // Create the result registers for this node and add the result regs to 219 // the machine instruction. 220 if (VRBase == 0) { 221 assert(RC && "Isn't a register operand!"); 222 VRBase = MRI->createVirtualRegister(RC); 223 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 224 } 225 226 SDValue Op(Node, i); 227 if (IsClone) 228 VRBaseMap.erase(Op); 229 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 230 isNew = isNew; // Silence compiler warning. 231 assert(isNew && "Node emitted out of order - early"); 232 } 233} 234 235/// getVR - Return the virtual register corresponding to the specified result 236/// of the specified node. 237unsigned InstrEmitter::getVR(SDValue Op, 238 DenseMap<SDValue, unsigned> &VRBaseMap) { 239 if (Op.isMachineOpcode() && 240 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 241 // Add an IMPLICIT_DEF instruction before every use. 242 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 243 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc 244 // does not include operand register class info. 245 if (!VReg) { 246 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); 247 VReg = MRI->createVirtualRegister(RC); 248 } 249 BuildMI(MBB, Op.getDebugLoc(), 250 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 251 return VReg; 252 } 253 254 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 255 assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 256 return I->second; 257} 258 259 260/// AddRegisterOperand - Add the specified register as an operand to the 261/// specified machine instr. Insert register copies if the register is 262/// not in the required register class. 263void 264InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, 265 unsigned IIOpNum, 266 const TargetInstrDesc *II, 267 DenseMap<SDValue, unsigned> &VRBaseMap, 268 bool IsDebug) { 269 assert(Op.getValueType() != MVT::Other && 270 Op.getValueType() != MVT::Flag && 271 "Chain and flag operands should occur at end of operand list!"); 272 // Get/emit the operand. 273 unsigned VReg = getVR(Op, VRBaseMap); 274 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 275 276 const TargetInstrDesc &TID = MI->getDesc(); 277 bool isOptDef = IIOpNum < TID.getNumOperands() && 278 TID.OpInfo[IIOpNum].isOptionalDef(); 279 280 // If the instruction requires a register in a different class, create 281 // a new virtual register and copy the value into it. 282 if (II) { 283 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 284 const TargetRegisterClass *DstRC = 0; 285 if (IIOpNum < II->getNumOperands()) 286 DstRC = II->OpInfo[IIOpNum].getRegClass(TRI); 287 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && 288 "Don't have operand info for this instruction!"); 289 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) { 290 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 291 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 292 DstRC, SrcRC); 293 assert(Emitted && "Unable to issue a copy instruction!\n"); 294 (void) Emitted; 295 VReg = NewVReg; 296 } 297 } 298 299 // If this value has only one use, that use is a kill. This is a 300 // conservative approximation. Tied operands are never killed, so we need 301 // to check that. And that means we need to determine the index of the 302 // operand. 303 unsigned Idx = MI->getNumOperands(); 304 while (Idx > 0 && 305 MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit()) 306 --Idx; 307 bool isTied = MI->getDesc().getOperandConstraint(Idx, TOI::TIED_TO) != -1; 308 bool isKill = Op.hasOneUse() && !isTied && !IsDebug; 309 310 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, 311 false/*isImp*/, isKill, 312 false/*isDead*/, false/*isUndef*/, 313 false/*isEarlyClobber*/, 314 0/*SubReg*/, IsDebug)); 315} 316 317/// AddOperand - Add the specified operand to the specified machine instr. II 318/// specifies the instruction information for the node, and IIOpNum is the 319/// operand number (in the II) that we are adding. IIOpNum and II are used for 320/// assertions only. 321void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, 322 unsigned IIOpNum, 323 const TargetInstrDesc *II, 324 DenseMap<SDValue, unsigned> &VRBaseMap, 325 bool IsDebug) { 326 if (Op.isMachineOpcode()) { 327 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug); 328 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 329 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 330 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 331 const ConstantFP *CFP = F->getConstantFPValue(); 332 MI->addOperand(MachineOperand::CreateFPImm(CFP)); 333 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 334 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); 335 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 336 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 337 TGA->getTargetFlags())); 338 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 339 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock())); 340 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 341 MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); 342 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 343 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(), 344 JT->getTargetFlags())); 345 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 346 int Offset = CP->getOffset(); 347 unsigned Align = CP->getAlignment(); 348 const Type *Type = CP->getType(); 349 // MachineConstantPool wants an explicit alignment. 350 if (Align == 0) { 351 Align = TM->getTargetData()->getPrefTypeAlignment(Type); 352 if (Align == 0) { 353 // Alignment of vector types. FIXME! 354 Align = TM->getTargetData()->getTypeAllocSize(Type); 355 } 356 } 357 358 unsigned Idx; 359 MachineConstantPool *MCP = MF->getConstantPool(); 360 if (CP->isMachineConstantPoolEntry()) 361 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 362 else 363 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 364 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, 365 CP->getTargetFlags())); 366 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 367 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 368 ES->getTargetFlags())); 369 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 370 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(), 371 BA->getTargetFlags())); 372 } else { 373 assert(Op.getValueType() != MVT::Other && 374 Op.getValueType() != MVT::Flag && 375 "Chain and flag operands should occur at end of operand list!"); 376 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug); 377 } 378} 379 380/// getSuperRegisterRegClass - Returns the register class of a superreg A whose 381/// "SubIdx"'th sub-register class is the specified register class and whose 382/// type matches the specified type. 383static const TargetRegisterClass* 384getSuperRegisterRegClass(const TargetRegisterClass *TRC, 385 unsigned SubIdx, EVT VT) { 386 // Pick the register class of the superegister for this type 387 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), 388 E = TRC->superregclasses_end(); I != E; ++I) 389 if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC) 390 return *I; 391 assert(false && "Couldn't find the register class"); 392 return 0; 393} 394 395/// EmitSubregNode - Generate machine code for subreg nodes. 396/// 397void InstrEmitter::EmitSubregNode(SDNode *Node, 398 DenseMap<SDValue, unsigned> &VRBaseMap){ 399 unsigned VRBase = 0; 400 unsigned Opc = Node->getMachineOpcode(); 401 402 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 403 // the CopyToReg'd destination register instead of creating a new vreg. 404 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 405 UI != E; ++UI) { 406 SDNode *User = *UI; 407 if (User->getOpcode() == ISD::CopyToReg && 408 User->getOperand(2).getNode() == Node) { 409 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 410 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 411 VRBase = DestReg; 412 break; 413 } 414 } 415 } 416 417 if (Opc == TargetOpcode::EXTRACT_SUBREG) { 418 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 419 420 // Create the extract_subreg machine instruction. 421 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 422 TII->get(TargetOpcode::EXTRACT_SUBREG)); 423 424 // Figure out the register class to create for the destreg. 425 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 426 const TargetRegisterClass *TRC = MRI->getRegClass(VReg); 427 const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx); 428 assert(SRC && "Invalid subregister index in EXTRACT_SUBREG"); 429 430 // Figure out the register class to create for the destreg. 431 // Note that if we're going to directly use an existing register, 432 // it must be precisely the required class, and not a subclass 433 // thereof. 434 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 435 // Create the reg 436 assert(SRC && "Couldn't find source register class"); 437 VRBase = MRI->createVirtualRegister(SRC); 438 } 439 440 // Add def, source, and subreg index 441 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 442 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); 443 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 444 MBB->insert(InsertPos, MI); 445 } else if (Opc == TargetOpcode::INSERT_SUBREG || 446 Opc == TargetOpcode::SUBREG_TO_REG) { 447 SDValue N0 = Node->getOperand(0); 448 SDValue N1 = Node->getOperand(1); 449 SDValue N2 = Node->getOperand(2); 450 unsigned SubReg = getVR(N1, VRBaseMap); 451 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 452 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 453 const TargetRegisterClass *SRC = 454 getSuperRegisterRegClass(TRC, SubIdx, 455 Node->getValueType(0)); 456 457 // Figure out the register class to create for the destreg. 458 // Note that if we're going to directly use an existing register, 459 // it must be precisely the required class, and not a subclass 460 // thereof. 461 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 462 // Create the reg 463 assert(SRC && "Couldn't find source register class"); 464 VRBase = MRI->createVirtualRegister(SRC); 465 } 466 467 // Create the insert_subreg or subreg_to_reg machine instruction. 468 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc)); 469 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 470 471 // If creating a subreg_to_reg, then the first input operand 472 // is an implicit value immediate, otherwise it's a register 473 if (Opc == TargetOpcode::SUBREG_TO_REG) { 474 const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 475 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 476 } else 477 AddOperand(MI, N0, 0, 0, VRBaseMap); 478 // Add the subregster being inserted 479 AddOperand(MI, N1, 0, 0, VRBaseMap); 480 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 481 MBB->insert(InsertPos, MI); 482 } else 483 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 484 485 SDValue Op(Node, 0); 486 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 487 isNew = isNew; // Silence compiler warning. 488 assert(isNew && "Node emitted out of order - early"); 489} 490 491/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 492/// COPY_TO_REGCLASS is just a normal copy, except that the destination 493/// register is constrained to be in a particular register class. 494/// 495void 496InstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 497 DenseMap<SDValue, unsigned> &VRBaseMap) { 498 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 499 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 500 501 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 502 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx); 503 504 // Create the new VReg in the destination class and emit a copy. 505 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 506 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 507 DstRC, SrcRC); 508 assert(Emitted && 509 "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n"); 510 (void) Emitted; 511 512 SDValue Op(Node, 0); 513 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 514 isNew = isNew; // Silence compiler warning. 515 assert(isNew && "Node emitted out of order - early"); 516} 517 518/// EmitDbgValue - Generate machine instruction for a dbg_value node. 519/// 520MachineInstr * 521InstrEmitter::EmitDbgValue(SDDbgValue *SD, 522 DenseMap<SDValue, unsigned> &VRBaseMap) { 523 uint64_t Offset = SD->getOffset(); 524 MDNode* MDPtr = SD->getMDPtr(); 525 DebugLoc DL = SD->getDebugLoc(); 526 527 if (SD->getKind() == SDDbgValue::FRAMEIX) { 528 // Stack address; this needs to be lowered in target-dependent fashion. 529 // EmitTargetCodeForFrameDebugValue is responsible for allocation. 530 unsigned FrameIx = SD->getFrameIx(); 531 return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL); 532 } 533 // Otherwise, we're going to create an instruction here. 534 const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 535 MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 536 if (SD->getKind() == SDDbgValue::SDNODE) { 537 SDNode *Node = SD->getSDNode(); 538 SDValue Op = SDValue(Node, SD->getResNo()); 539 // It's possible we replaced this SDNode with other(s) and therefore 540 // didn't generate code for it. It's better to catch these cases where 541 // they happen and transfer the debug info, but trying to guarantee that 542 // in all cases would be very fragile; this is a safeguard for any 543 // that were missed. 544 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 545 if (I==VRBaseMap.end()) 546 MIB.addReg(0U); // undef 547 else 548 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 549 true /*IsDebug*/); 550 } else if (SD->getKind() == SDDbgValue::CONST) { 551 const Value *V = SD->getConst(); 552 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 553 MIB.addImm(CI->getSExtValue()); 554 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 555 MIB.addFPImm(CF); 556 } else { 557 // Could be an Undef. In any case insert an Undef so we can see what we 558 // dropped. 559 MIB.addReg(0U); 560 } 561 } else { 562 // Insert an Undef so we can see what we dropped. 563 MIB.addReg(0U); 564 } 565 566 MIB.addImm(Offset).addMetadata(MDPtr); 567 return &*MIB; 568} 569 570/// EmitMachineNode - Generate machine code for a target-specific node and 571/// needed dependencies. 572/// 573void InstrEmitter:: 574EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 575 DenseMap<SDValue, unsigned> &VRBaseMap) { 576 unsigned Opc = Node->getMachineOpcode(); 577 578 // Handle subreg insert/extract specially 579 if (Opc == TargetOpcode::EXTRACT_SUBREG || 580 Opc == TargetOpcode::INSERT_SUBREG || 581 Opc == TargetOpcode::SUBREG_TO_REG) { 582 EmitSubregNode(Node, VRBaseMap); 583 return; 584 } 585 586 // Handle COPY_TO_REGCLASS specially. 587 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 588 EmitCopyToRegClassNode(Node, VRBaseMap); 589 return; 590 } 591 592 if (Opc == TargetOpcode::IMPLICIT_DEF) 593 // We want a unique VR for each IMPLICIT_DEF use. 594 return; 595 596 const TargetInstrDesc &II = TII->get(Opc); 597 unsigned NumResults = CountResults(Node); 598 unsigned NodeOperands = CountOperands(Node); 599 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; 600#ifndef NDEBUG 601 unsigned NumMIOperands = NodeOperands + NumResults; 602 if (II.isVariadic()) 603 assert(NumMIOperands >= II.getNumOperands() && 604 "Too few operands for a variadic node!"); 605 else 606 assert(NumMIOperands >= II.getNumOperands() && 607 NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() && 608 "#operands for dag node doesn't match .td file!"); 609#endif 610 611 // Create the new machine instruction. 612 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II); 613 614 // Add result register values for things that are defined by this 615 // instruction. 616 if (NumResults) 617 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap); 618 619 // Emit all of the actual operands of this instruction, adding them to the 620 // instruction as appropriate. 621 bool HasOptPRefs = II.getNumDefs() > NumResults; 622 assert((!HasOptPRefs || !HasPhysRegOuts) && 623 "Unable to cope with optional defs and phys regs defs!"); 624 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 625 for (unsigned i = NumSkip; i != NodeOperands; ++i) 626 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 627 VRBaseMap); 628 629 // Transfer all of the memory reference descriptions of this instruction. 630 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 631 cast<MachineSDNode>(Node)->memoperands_end()); 632 633 if (II.usesCustomInsertionHook()) { 634 // Insert this instruction into the basic block using a target 635 // specific inserter which may returns a new basic block. 636 MBB = TLI->EmitInstrWithCustomInserter(MI, MBB); 637 InsertPos = MBB->end(); 638 return; 639 } 640 641 MBB->insert(InsertPos, MI); 642 643 // Additional results must be an physical register def. 644 if (HasPhysRegOuts) { 645 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 646 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 647 if (Node->hasAnyUseOfValue(i)) 648 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 649 // If there are no uses, mark the register as dead now, so that 650 // MachineLICM/Sink can see that it's dead. Don't do this if the 651 // node has a Flag value, for the benefit of targets still using 652 // Flag for values in physregs. 653 else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 654 MI->addRegisterDead(Reg, TRI); 655 } 656 } 657 658 // If the instruction has implicit defs and the node doesn't, mark the 659 // implicit def as dead. If the node has any flag outputs, we don't do this 660 // because we don't know what implicit defs are being used by flagged nodes. 661 if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 662 if (const unsigned *IDList = II.getImplicitDefs()) { 663 for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs(); 664 i != e; ++i) 665 MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI); 666 } 667} 668 669/// EmitSpecialNode - Generate machine code for a target-independent node and 670/// needed dependencies. 671void InstrEmitter:: 672EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 673 DenseMap<SDValue, unsigned> &VRBaseMap) { 674 switch (Node->getOpcode()) { 675 default: 676#ifndef NDEBUG 677 Node->dump(); 678#endif 679 llvm_unreachable("This target-independent node should have been selected!"); 680 break; 681 case ISD::EntryToken: 682 llvm_unreachable("EntryToken should have been excluded from the schedule!"); 683 break; 684 case ISD::MERGE_VALUES: 685 case ISD::TokenFactor: // fall thru 686 break; 687 case ISD::CopyToReg: { 688 unsigned SrcReg; 689 SDValue SrcVal = Node->getOperand(2); 690 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 691 SrcReg = R->getReg(); 692 else 693 SrcReg = getVR(SrcVal, VRBaseMap); 694 695 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 696 if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 697 break; 698 699 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0; 700 // Get the register classes of the src/dst. 701 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) 702 SrcTRC = MRI->getRegClass(SrcReg); 703 else 704 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType()); 705 706 if (TargetRegisterInfo::isVirtualRegister(DestReg)) 707 DstTRC = MRI->getRegClass(DestReg); 708 else 709 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg, 710 Node->getOperand(1).getValueType()); 711 712 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg, 713 DstTRC, SrcTRC); 714 assert(Emitted && "Unable to issue a copy instruction!\n"); 715 (void) Emitted; 716 break; 717 } 718 case ISD::CopyFromReg: { 719 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 720 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 721 break; 722 } 723 case ISD::EH_LABEL: { 724 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 725 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 726 TII->get(TargetOpcode::EH_LABEL)).addSym(S); 727 break; 728 } 729 730 case ISD::INLINEASM: { 731 unsigned NumOps = Node->getNumOperands(); 732 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag) 733 --NumOps; // Ignore the flag operand. 734 735 // Create the inline asm machine instruction. 736 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 737 TII->get(TargetOpcode::INLINEASM)); 738 739 // Add the asm string as an external symbol operand. 740 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 741 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 742 MI->addOperand(MachineOperand::CreateES(AsmStr)); 743 744 // Add all of the operand registers to the instruction. 745 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 746 unsigned Flags = 747 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 748 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 749 750 MI->addOperand(MachineOperand::CreateImm(Flags)); 751 ++i; // Skip the ID value. 752 753 switch (InlineAsm::getKind(Flags)) { 754 default: llvm_unreachable("Bad flags!"); 755 case InlineAsm::Kind_RegDef: 756 for (; NumVals; --NumVals, ++i) { 757 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 758 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 759 } 760 break; 761 case InlineAsm::Kind_RegDefEarlyClobber: 762 for (; NumVals; --NumVals, ++i) { 763 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 764 MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false, 765 false, false, true)); 766 } 767 break; 768 case InlineAsm::Kind_RegUse: // Use of register. 769 case InlineAsm::Kind_Imm: // Immediate. 770 case InlineAsm::Kind_Mem: // Addressing mode. 771 // The addressing mode has been selected, just add all of the 772 // operands to the machine instruction. 773 for (; NumVals; --NumVals, ++i) 774 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap); 775 break; 776 } 777 } 778 779 // Get the mdnode from the asm if it exists and add it to the instruction. 780 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 781 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 782 if (MD) 783 MI->addOperand(MachineOperand::CreateMetadata(MD)); 784 785 MBB->insert(InsertPos, MI); 786 break; 787 } 788 } 789} 790 791/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 792/// at the given position in the given block. 793InstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 794 MachineBasicBlock::iterator insertpos) 795 : MF(mbb->getParent()), 796 MRI(&MF->getRegInfo()), 797 TM(&MF->getTarget()), 798 TII(TM->getInstrInfo()), 799 TRI(TM->getRegisterInfo()), 800 TLI(TM->getTargetLowering()), 801 MBB(mbb), InsertPos(insertpos) { 802} 803