InstrEmitter.cpp revision 3be2ceb2bec76f6d38f0d51f1045ad6700c6f453
1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the Emit routines for the SelectionDAG class, which creates 11// MachineInstrs based on the decisions of the SelectionDAG instruction 12// selection. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "instr-emitter" 17#include "InstrEmitter.h" 18#include "SDNodeDbgValue.h" 19#include "llvm/CodeGen/MachineConstantPool.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetInstrInfo.h" 26#include "llvm/Target/TargetLowering.h" 27#include "llvm/ADT/Statistic.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31using namespace llvm; 32 33/// CountResults - The results of target nodes have register or immediate 34/// operands first, then an optional chain, and optional flag operands (which do 35/// not go into the resulting MachineInstr). 36unsigned InstrEmitter::CountResults(SDNode *Node) { 37 unsigned N = Node->getNumValues(); 38 while (N && Node->getValueType(N - 1) == MVT::Flag) 39 --N; 40 if (N && Node->getValueType(N - 1) == MVT::Other) 41 --N; // Skip over chain result. 42 return N; 43} 44 45/// CountOperands - The inputs to target nodes have any actual inputs first, 46/// followed by an optional chain operand, then an optional flag operand. 47/// Compute the number of actual operands that will go into the resulting 48/// MachineInstr. 49unsigned InstrEmitter::CountOperands(SDNode *Node) { 50 unsigned N = Node->getNumOperands(); 51 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) 52 --N; 53 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 54 --N; // Ignore chain if it exists. 55 return N; 56} 57 58/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 59/// implicit physical register output. 60void InstrEmitter:: 61EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 62 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 63 unsigned VRBase = 0; 64 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 65 // Just use the input register directly! 66 SDValue Op(Node, ResNo); 67 if (IsClone) 68 VRBaseMap.erase(Op); 69 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 70 isNew = isNew; // Silence compiler warning. 71 assert(isNew && "Node emitted out of order - early"); 72 return; 73 } 74 75 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 76 // the CopyToReg'd destination register instead of creating a new vreg. 77 bool MatchReg = true; 78 const TargetRegisterClass *UseRC = NULL; 79 if (!IsClone && !IsCloned) 80 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 81 UI != E; ++UI) { 82 SDNode *User = *UI; 83 bool Match = true; 84 if (User->getOpcode() == ISD::CopyToReg && 85 User->getOperand(2).getNode() == Node && 86 User->getOperand(2).getResNo() == ResNo) { 87 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 88 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 89 VRBase = DestReg; 90 Match = false; 91 } else if (DestReg != SrcReg) 92 Match = false; 93 } else { 94 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 95 SDValue Op = User->getOperand(i); 96 if (Op.getNode() != Node || Op.getResNo() != ResNo) 97 continue; 98 EVT VT = Node->getValueType(Op.getResNo()); 99 if (VT == MVT::Other || VT == MVT::Flag) 100 continue; 101 Match = false; 102 if (User->isMachineOpcode()) { 103 const TargetInstrDesc &II = TII->get(User->getMachineOpcode()); 104 const TargetRegisterClass *RC = 0; 105 if (i+II.getNumDefs() < II.getNumOperands()) 106 RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI); 107 if (!UseRC) 108 UseRC = RC; 109 else if (RC) { 110 const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC); 111 // If multiple uses expect disjoint register classes, we emit 112 // copies in AddRegisterOperand. 113 if (ComRC) 114 UseRC = ComRC; 115 } 116 } 117 } 118 } 119 MatchReg &= Match; 120 if (VRBase) 121 break; 122 } 123 124 EVT VT = Node->getValueType(ResNo); 125 const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 126 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT); 127 128 // Figure out the register class to create for the destreg. 129 if (VRBase) { 130 DstRC = MRI->getRegClass(VRBase); 131 } else if (UseRC) { 132 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 133 DstRC = UseRC; 134 } else { 135 DstRC = TLI->getRegClassFor(VT); 136 } 137 138 // If all uses are reading from the src physical register and copying the 139 // register is either impossible or very expensive, then don't create a copy. 140 if (MatchReg && SrcRC->getCopyCost() < 0) { 141 VRBase = SrcReg; 142 } else { 143 // Create the reg, emit the copy. 144 VRBase = MRI->createVirtualRegister(DstRC); 145 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg, 146 DstRC, SrcRC, Node->getDebugLoc()); 147 148 assert(Emitted && "Unable to issue a copy instruction!\n"); 149 (void) Emitted; 150 } 151 152 SDValue Op(Node, ResNo); 153 if (IsClone) 154 VRBaseMap.erase(Op); 155 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 156 isNew = isNew; // Silence compiler warning. 157 assert(isNew && "Node emitted out of order - early"); 158} 159 160/// getDstOfCopyToRegUse - If the only use of the specified result number of 161/// node is a CopyToReg, return its destination register. Return 0 otherwise. 162unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 163 unsigned ResNo) const { 164 if (!Node->hasOneUse()) 165 return 0; 166 167 SDNode *User = *Node->use_begin(); 168 if (User->getOpcode() == ISD::CopyToReg && 169 User->getOperand(2).getNode() == Node && 170 User->getOperand(2).getResNo() == ResNo) { 171 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 172 if (TargetRegisterInfo::isVirtualRegister(Reg)) 173 return Reg; 174 } 175 return 0; 176} 177 178void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 179 const TargetInstrDesc &II, 180 bool IsClone, bool IsCloned, 181 DenseMap<SDValue, unsigned> &VRBaseMap) { 182 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 183 "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 184 185 for (unsigned i = 0; i < II.getNumDefs(); ++i) { 186 // If the specific node value is only used by a CopyToReg and the dest reg 187 // is a vreg in the same register class, use the CopyToReg'd destination 188 // register instead of creating a new vreg. 189 unsigned VRBase = 0; 190 const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI); 191 if (II.OpInfo[i].isOptionalDef()) { 192 // Optional def must be a physical register. 193 unsigned NumResults = CountResults(Node); 194 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 195 assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 196 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 197 } 198 199 if (!VRBase && !IsClone && !IsCloned) 200 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 201 UI != E; ++UI) { 202 SDNode *User = *UI; 203 if (User->getOpcode() == ISD::CopyToReg && 204 User->getOperand(2).getNode() == Node && 205 User->getOperand(2).getResNo() == i) { 206 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 207 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 208 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 209 if (RegRC == RC) { 210 VRBase = Reg; 211 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 212 break; 213 } 214 } 215 } 216 } 217 218 // Create the result registers for this node and add the result regs to 219 // the machine instruction. 220 if (VRBase == 0) { 221 assert(RC && "Isn't a register operand!"); 222 VRBase = MRI->createVirtualRegister(RC); 223 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 224 } 225 226 SDValue Op(Node, i); 227 if (IsClone) 228 VRBaseMap.erase(Op); 229 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 230 isNew = isNew; // Silence compiler warning. 231 assert(isNew && "Node emitted out of order - early"); 232 } 233} 234 235/// getVR - Return the virtual register corresponding to the specified result 236/// of the specified node. 237unsigned InstrEmitter::getVR(SDValue Op, 238 DenseMap<SDValue, unsigned> &VRBaseMap) { 239 if (Op.isMachineOpcode() && 240 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 241 // Add an IMPLICIT_DEF instruction before every use. 242 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 243 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc 244 // does not include operand register class info. 245 if (!VReg) { 246 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); 247 VReg = MRI->createVirtualRegister(RC); 248 } 249 BuildMI(MBB, Op.getDebugLoc(), 250 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 251 return VReg; 252 } 253 254 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 255 assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 256 return I->second; 257} 258 259 260/// AddRegisterOperand - Add the specified register as an operand to the 261/// specified machine instr. Insert register copies if the register is 262/// not in the required register class. 263void 264InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, 265 unsigned IIOpNum, 266 const TargetInstrDesc *II, 267 DenseMap<SDValue, unsigned> &VRBaseMap, 268 bool IsDebug) { 269 assert(Op.getValueType() != MVT::Other && 270 Op.getValueType() != MVT::Flag && 271 "Chain and flag operands should occur at end of operand list!"); 272 // Get/emit the operand. 273 unsigned VReg = getVR(Op, VRBaseMap); 274 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 275 276 const TargetInstrDesc &TID = MI->getDesc(); 277 bool isOptDef = IIOpNum < TID.getNumOperands() && 278 TID.OpInfo[IIOpNum].isOptionalDef(); 279 280 // If the instruction requires a register in a different class, create 281 // a new virtual register and copy the value into it. 282 if (II) { 283 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 284 const TargetRegisterClass *DstRC = 0; 285 if (IIOpNum < II->getNumOperands()) 286 DstRC = II->OpInfo[IIOpNum].getRegClass(TRI); 287 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && 288 "Don't have operand info for this instruction!"); 289 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) { 290 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 291 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 292 DstRC, SrcRC, Op.getNode()->getDebugLoc()); 293 assert(Emitted && "Unable to issue a copy instruction!\n"); 294 (void) Emitted; 295 VReg = NewVReg; 296 } 297 } 298 299 // If this value has only one use, that use is a kill. This is a 300 // conservative approximation. Tied operands are never killed, so we need 301 // to check that. And that means we need to determine the index of the 302 // operand. 303 unsigned Idx = MI->getNumOperands(); 304 while (Idx > 0 && 305 MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit()) 306 --Idx; 307 bool isTied = MI->getDesc().getOperandConstraint(Idx, TOI::TIED_TO) != -1; 308 bool isKill = Op.hasOneUse() && !isTied && !IsDebug; 309 310 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, 311 false/*isImp*/, isKill, 312 false/*isDead*/, false/*isUndef*/, 313 false/*isEarlyClobber*/, 314 0/*SubReg*/, IsDebug)); 315} 316 317/// AddOperand - Add the specified operand to the specified machine instr. II 318/// specifies the instruction information for the node, and IIOpNum is the 319/// operand number (in the II) that we are adding. IIOpNum and II are used for 320/// assertions only. 321void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, 322 unsigned IIOpNum, 323 const TargetInstrDesc *II, 324 DenseMap<SDValue, unsigned> &VRBaseMap, 325 bool IsDebug) { 326 if (Op.isMachineOpcode()) { 327 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug); 328 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 329 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 330 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 331 const ConstantFP *CFP = F->getConstantFPValue(); 332 MI->addOperand(MachineOperand::CreateFPImm(CFP)); 333 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 334 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); 335 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 336 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 337 TGA->getTargetFlags())); 338 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 339 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock())); 340 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 341 MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); 342 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 343 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(), 344 JT->getTargetFlags())); 345 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 346 int Offset = CP->getOffset(); 347 unsigned Align = CP->getAlignment(); 348 const Type *Type = CP->getType(); 349 // MachineConstantPool wants an explicit alignment. 350 if (Align == 0) { 351 Align = TM->getTargetData()->getPrefTypeAlignment(Type); 352 if (Align == 0) { 353 // Alignment of vector types. FIXME! 354 Align = TM->getTargetData()->getTypeAllocSize(Type); 355 } 356 } 357 358 unsigned Idx; 359 MachineConstantPool *MCP = MF->getConstantPool(); 360 if (CP->isMachineConstantPoolEntry()) 361 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 362 else 363 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 364 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, 365 CP->getTargetFlags())); 366 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 367 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 368 ES->getTargetFlags())); 369 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 370 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(), 371 BA->getTargetFlags())); 372 } else { 373 assert(Op.getValueType() != MVT::Other && 374 Op.getValueType() != MVT::Flag && 375 "Chain and flag operands should occur at end of operand list!"); 376 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug); 377 } 378} 379 380/// getSuperRegisterRegClass - Returns the register class of a superreg A whose 381/// "SubIdx"'th sub-register class is the specified register class and whose 382/// type matches the specified type. 383static const TargetRegisterClass* 384getSuperRegisterRegClass(const TargetRegisterClass *TRC, 385 unsigned SubIdx, EVT VT) { 386 // Pick the register class of the superegister for this type 387 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), 388 E = TRC->superregclasses_end(); I != E; ++I) 389 if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC) 390 return *I; 391 assert(false && "Couldn't find the register class"); 392 return 0; 393} 394 395/// EmitSubregNode - Generate machine code for subreg nodes. 396/// 397void InstrEmitter::EmitSubregNode(SDNode *Node, 398 DenseMap<SDValue, unsigned> &VRBaseMap){ 399 unsigned VRBase = 0; 400 unsigned Opc = Node->getMachineOpcode(); 401 402 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 403 // the CopyToReg'd destination register instead of creating a new vreg. 404 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 405 UI != E; ++UI) { 406 SDNode *User = *UI; 407 if (User->getOpcode() == ISD::CopyToReg && 408 User->getOperand(2).getNode() == Node) { 409 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 410 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 411 VRBase = DestReg; 412 break; 413 } 414 } 415 } 416 417 if (Opc == TargetOpcode::EXTRACT_SUBREG) { 418 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 419 420 // Create the extract_subreg machine instruction. 421 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 422 TII->get(TargetOpcode::EXTRACT_SUBREG)); 423 424 // Figure out the register class to create for the destreg. 425 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 426 const TargetRegisterClass *TRC = MRI->getRegClass(VReg); 427 const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx); 428 assert(SRC && "Invalid subregister index in EXTRACT_SUBREG"); 429 430 // Figure out the register class to create for the destreg. 431 // Note that if we're going to directly use an existing register, 432 // it must be precisely the required class, and not a subclass 433 // thereof. 434 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 435 // Create the reg 436 assert(SRC && "Couldn't find source register class"); 437 VRBase = MRI->createVirtualRegister(SRC); 438 } 439 440 // Add def, source, and subreg index 441 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 442 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); 443 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 444 MBB->insert(InsertPos, MI); 445 } else if (Opc == TargetOpcode::INSERT_SUBREG || 446 Opc == TargetOpcode::SUBREG_TO_REG) { 447 SDValue N0 = Node->getOperand(0); 448 SDValue N1 = Node->getOperand(1); 449 SDValue N2 = Node->getOperand(2); 450 unsigned SubReg = getVR(N1, VRBaseMap); 451 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 452 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 453 const TargetRegisterClass *SRC = 454 getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0)); 455 456 // Figure out the register class to create for the destreg. 457 // Note that if we're going to directly use an existing register, 458 // it must be precisely the required class, and not a subclass 459 // thereof. 460 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 461 // Create the reg 462 assert(SRC && "Couldn't find source register class"); 463 VRBase = MRI->createVirtualRegister(SRC); 464 } 465 466 // Create the insert_subreg or subreg_to_reg machine instruction. 467 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc)); 468 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 469 470 // If creating a subreg_to_reg, then the first input operand 471 // is an implicit value immediate, otherwise it's a register 472 if (Opc == TargetOpcode::SUBREG_TO_REG) { 473 const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 474 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 475 } else 476 AddOperand(MI, N0, 0, 0, VRBaseMap); 477 // Add the subregster being inserted 478 AddOperand(MI, N1, 0, 0, VRBaseMap); 479 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 480 MBB->insert(InsertPos, MI); 481 } else 482 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 483 484 SDValue Op(Node, 0); 485 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 486 isNew = isNew; // Silence compiler warning. 487 assert(isNew && "Node emitted out of order - early"); 488} 489 490/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 491/// COPY_TO_REGCLASS is just a normal copy, except that the destination 492/// register is constrained to be in a particular register class. 493/// 494void 495InstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 496 DenseMap<SDValue, unsigned> &VRBaseMap) { 497 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 498 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 499 500 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 501 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx); 502 503 // Create the new VReg in the destination class and emit a copy. 504 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 505 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 506 DstRC, SrcRC, Node->getDebugLoc()); 507 assert(Emitted && 508 "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n"); 509 (void) Emitted; 510 511 SDValue Op(Node, 0); 512 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 513 isNew = isNew; // Silence compiler warning. 514 assert(isNew && "Node emitted out of order - early"); 515} 516 517/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 518/// 519void InstrEmitter::EmitRegSequence(SDNode *Node, 520 DenseMap<SDValue, unsigned> &VRBaseMap) { 521 const TargetRegisterClass *RC = TLI->getRegClassFor(Node->getValueType(0)); 522 unsigned NewVReg = MRI->createVirtualRegister(RC); 523 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 524 TII->get(TargetOpcode::REG_SEQUENCE), NewVReg); 525 unsigned NumOps = Node->getNumOperands(); 526 assert((NumOps & 1) == 0 && 527 "REG_SEQUENCE must have an even number of operands!"); 528 const TargetInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 529 for (unsigned i = 0; i != NumOps; ++i) { 530 SDValue Op = Node->getOperand(i); 531#ifndef NDEBUG 532 if (i & 1) { 533 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 534 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 535 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 536 const TargetRegisterClass *SRC = 537 getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0)); 538 assert(SRC == RC && "Invalid subregister index in REG_SEQUENCE"); 539 } 540#endif 541 AddOperand(MI, Op, i+1, &II, VRBaseMap); 542 } 543 544 MBB->insert(InsertPos, MI); 545 SDValue Op(Node, 0); 546 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 547 isNew = isNew; // Silence compiler warning. 548 assert(isNew && "Node emitted out of order - early"); 549} 550 551/// EmitDbgValue - Generate machine instruction for a dbg_value node. 552/// 553MachineInstr * 554InstrEmitter::EmitDbgValue(SDDbgValue *SD, 555 DenseMap<SDValue, unsigned> &VRBaseMap) { 556 uint64_t Offset = SD->getOffset(); 557 MDNode* MDPtr = SD->getMDPtr(); 558 DebugLoc DL = SD->getDebugLoc(); 559 560 if (SD->getKind() == SDDbgValue::FRAMEIX) { 561 // Stack address; this needs to be lowered in target-dependent fashion. 562 // EmitTargetCodeForFrameDebugValue is responsible for allocation. 563 unsigned FrameIx = SD->getFrameIx(); 564 return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL); 565 } 566 // Otherwise, we're going to create an instruction here. 567 const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 568 MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 569 if (SD->getKind() == SDDbgValue::SDNODE) { 570 SDNode *Node = SD->getSDNode(); 571 SDValue Op = SDValue(Node, SD->getResNo()); 572 // It's possible we replaced this SDNode with other(s) and therefore 573 // didn't generate code for it. It's better to catch these cases where 574 // they happen and transfer the debug info, but trying to guarantee that 575 // in all cases would be very fragile; this is a safeguard for any 576 // that were missed. 577 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 578 if (I==VRBaseMap.end()) 579 MIB.addReg(0U); // undef 580 else 581 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 582 true /*IsDebug*/); 583 } else if (SD->getKind() == SDDbgValue::CONST) { 584 const Value *V = SD->getConst(); 585 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 586 // FIXME: SDDbgValues aren't updated with legalization, so it's possible 587 // to have i128 values in them at this point. As a crude workaround, just 588 // drop the debug info if this happens. 589 if (!CI->getValue().isSignedIntN(64)) 590 MIB.addReg(0U); 591 else 592 MIB.addImm(CI->getSExtValue()); 593 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 594 MIB.addFPImm(CF); 595 } else { 596 // Could be an Undef. In any case insert an Undef so we can see what we 597 // dropped. 598 MIB.addReg(0U); 599 } 600 } else { 601 // Insert an Undef so we can see what we dropped. 602 MIB.addReg(0U); 603 } 604 605 MIB.addImm(Offset).addMetadata(MDPtr); 606 return &*MIB; 607} 608 609/// EmitMachineNode - Generate machine code for a target-specific node and 610/// needed dependencies. 611/// 612void InstrEmitter:: 613EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 614 DenseMap<SDValue, unsigned> &VRBaseMap) { 615 unsigned Opc = Node->getMachineOpcode(); 616 617 // Handle subreg insert/extract specially 618 if (Opc == TargetOpcode::EXTRACT_SUBREG || 619 Opc == TargetOpcode::INSERT_SUBREG || 620 Opc == TargetOpcode::SUBREG_TO_REG) { 621 EmitSubregNode(Node, VRBaseMap); 622 return; 623 } 624 625 // Handle COPY_TO_REGCLASS specially. 626 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 627 EmitCopyToRegClassNode(Node, VRBaseMap); 628 return; 629 } 630 631 // Handle REG_SEQUENCE specially. 632 if (Opc == TargetOpcode::REG_SEQUENCE) { 633 EmitRegSequence(Node, VRBaseMap); 634 return; 635 } 636 637 if (Opc == TargetOpcode::IMPLICIT_DEF) 638 // We want a unique VR for each IMPLICIT_DEF use. 639 return; 640 641 const TargetInstrDesc &II = TII->get(Opc); 642 unsigned NumResults = CountResults(Node); 643 unsigned NodeOperands = CountOperands(Node); 644 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; 645#ifndef NDEBUG 646 unsigned NumMIOperands = NodeOperands + NumResults; 647 if (II.isVariadic()) 648 assert(NumMIOperands >= II.getNumOperands() && 649 "Too few operands for a variadic node!"); 650 else 651 assert(NumMIOperands >= II.getNumOperands() && 652 NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() && 653 "#operands for dag node doesn't match .td file!"); 654#endif 655 656 // Create the new machine instruction. 657 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II); 658 659 // Add result register values for things that are defined by this 660 // instruction. 661 if (NumResults) 662 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap); 663 664 // Emit all of the actual operands of this instruction, adding them to the 665 // instruction as appropriate. 666 bool HasOptPRefs = II.getNumDefs() > NumResults; 667 assert((!HasOptPRefs || !HasPhysRegOuts) && 668 "Unable to cope with optional defs and phys regs defs!"); 669 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 670 for (unsigned i = NumSkip; i != NodeOperands; ++i) 671 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 672 VRBaseMap); 673 674 // Transfer all of the memory reference descriptions of this instruction. 675 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 676 cast<MachineSDNode>(Node)->memoperands_end()); 677 678 if (II.usesCustomInsertionHook()) { 679 // Insert this instruction into the basic block using a target 680 // specific inserter which may returns a new basic block. 681 MBB = TLI->EmitInstrWithCustomInserter(MI, MBB); 682 InsertPos = MBB->end(); 683 return; 684 } 685 686 MBB->insert(InsertPos, MI); 687 688 // Additional results must be an physical register def. 689 if (HasPhysRegOuts) { 690 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 691 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 692 if (Node->hasAnyUseOfValue(i)) 693 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 694 // If there are no uses, mark the register as dead now, so that 695 // MachineLICM/Sink can see that it's dead. Don't do this if the 696 // node has a Flag value, for the benefit of targets still using 697 // Flag for values in physregs. 698 else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 699 MI->addRegisterDead(Reg, TRI); 700 } 701 } 702 703 // If the instruction has implicit defs and the node doesn't, mark the 704 // implicit def as dead. If the node has any flag outputs, we don't do this 705 // because we don't know what implicit defs are being used by flagged nodes. 706 if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 707 if (const unsigned *IDList = II.getImplicitDefs()) { 708 for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs(); 709 i != e; ++i) 710 MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI); 711 } 712} 713 714/// EmitSpecialNode - Generate machine code for a target-independent node and 715/// needed dependencies. 716void InstrEmitter:: 717EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 718 DenseMap<SDValue, unsigned> &VRBaseMap) { 719 switch (Node->getOpcode()) { 720 default: 721#ifndef NDEBUG 722 Node->dump(); 723#endif 724 llvm_unreachable("This target-independent node should have been selected!"); 725 break; 726 case ISD::EntryToken: 727 llvm_unreachable("EntryToken should have been excluded from the schedule!"); 728 break; 729 case ISD::MERGE_VALUES: 730 case ISD::TokenFactor: // fall thru 731 break; 732 case ISD::CopyToReg: { 733 unsigned SrcReg; 734 SDValue SrcVal = Node->getOperand(2); 735 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 736 SrcReg = R->getReg(); 737 else 738 SrcReg = getVR(SrcVal, VRBaseMap); 739 740 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 741 if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 742 break; 743 744 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0; 745 // Get the register classes of the src/dst. 746 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) 747 SrcTRC = MRI->getRegClass(SrcReg); 748 else 749 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType()); 750 751 if (TargetRegisterInfo::isVirtualRegister(DestReg)) 752 DstTRC = MRI->getRegClass(DestReg); 753 else 754 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg, 755 Node->getOperand(1).getValueType()); 756 757 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg, 758 DstTRC, SrcTRC, Node->getDebugLoc()); 759 assert(Emitted && "Unable to issue a copy instruction!\n"); 760 (void) Emitted; 761 break; 762 } 763 case ISD::CopyFromReg: { 764 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 765 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 766 break; 767 } 768 case ISD::EH_LABEL: { 769 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 770 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 771 TII->get(TargetOpcode::EH_LABEL)).addSym(S); 772 break; 773 } 774 775 case ISD::INLINEASM: { 776 unsigned NumOps = Node->getNumOperands(); 777 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag) 778 --NumOps; // Ignore the flag operand. 779 780 // Create the inline asm machine instruction. 781 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 782 TII->get(TargetOpcode::INLINEASM)); 783 784 // Add the asm string as an external symbol operand. 785 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 786 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 787 MI->addOperand(MachineOperand::CreateES(AsmStr)); 788 789 // Add all of the operand registers to the instruction. 790 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 791 unsigned Flags = 792 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 793 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 794 795 MI->addOperand(MachineOperand::CreateImm(Flags)); 796 ++i; // Skip the ID value. 797 798 switch (InlineAsm::getKind(Flags)) { 799 default: llvm_unreachable("Bad flags!"); 800 case InlineAsm::Kind_RegDef: 801 for (; NumVals; --NumVals, ++i) { 802 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 803 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 804 } 805 break; 806 case InlineAsm::Kind_RegDefEarlyClobber: 807 for (; NumVals; --NumVals, ++i) { 808 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 809 MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false, 810 false, false, true)); 811 } 812 break; 813 case InlineAsm::Kind_RegUse: // Use of register. 814 case InlineAsm::Kind_Imm: // Immediate. 815 case InlineAsm::Kind_Mem: // Addressing mode. 816 // The addressing mode has been selected, just add all of the 817 // operands to the machine instruction. 818 for (; NumVals; --NumVals, ++i) 819 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap); 820 break; 821 } 822 } 823 824 // Get the mdnode from the asm if it exists and add it to the instruction. 825 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 826 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 827 if (MD) 828 MI->addOperand(MachineOperand::CreateMetadata(MD)); 829 830 MBB->insert(InsertPos, MI); 831 break; 832 } 833 } 834} 835 836/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 837/// at the given position in the given block. 838InstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 839 MachineBasicBlock::iterator insertpos) 840 : MF(mbb->getParent()), 841 MRI(&MF->getRegInfo()), 842 TM(&MF->getTarget()), 843 TII(TM->getInstrInfo()), 844 TRI(TM->getRegisterInfo()), 845 TLI(TM->getTargetLowering()), 846 MBB(mbb), InsertPos(insertpos) { 847} 848