InstrEmitter.cpp revision c00090b16b2b35f2d042d965945c4246d13321b5
1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the Emit routines for the SelectionDAG class, which creates 11// MachineInstrs based on the decisions of the SelectionDAG instruction 12// selection. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "instr-emitter" 17#include "InstrEmitter.h" 18#include "SDNodeDbgValue.h" 19#include "llvm/ADT/Statistic.h" 20#include "llvm/CodeGen/MachineConstantPool.h" 21#include "llvm/CodeGen/MachineFunction.h" 22#include "llvm/CodeGen/MachineInstrBuilder.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/CodeGen/StackMaps.h" 25#include "llvm/IR/DataLayout.h" 26#include "llvm/Support/Debug.h" 27#include "llvm/Support/ErrorHandling.h" 28#include "llvm/Support/MathExtras.h" 29#include "llvm/Target/TargetInstrInfo.h" 30#include "llvm/Target/TargetLowering.h" 31#include "llvm/Target/TargetMachine.h" 32using namespace llvm; 33 34/// MinRCSize - Smallest register class we allow when constraining virtual 35/// registers. If satisfying all register class constraints would require 36/// using a smaller register class, emit a COPY to a new virtual register 37/// instead. 38const unsigned MinRCSize = 4; 39 40/// CountResults - The results of target nodes have register or immediate 41/// operands first, then an optional chain, and optional glue operands (which do 42/// not go into the resulting MachineInstr). 43unsigned InstrEmitter::CountResults(SDNode *Node) { 44 unsigned N = Node->getNumValues(); 45 while (N && Node->getValueType(N - 1) == MVT::Glue) 46 --N; 47 if (N && Node->getValueType(N - 1) == MVT::Other) 48 --N; // Skip over chain result. 49 return N; 50} 51 52/// countOperands - The inputs to target nodes have any actual inputs first, 53/// followed by an optional chain operand, then an optional glue operand. 54/// Compute the number of actual operands that will go into the resulting 55/// MachineInstr. 56/// 57/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding 58/// the chain and glue. These operands may be implicit on the machine instr. 59static unsigned countOperands(SDNode *Node, unsigned NumExpUses, 60 unsigned &NumImpUses) { 61 unsigned N = Node->getNumOperands(); 62 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 63 --N; 64 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 65 --N; // Ignore chain if it exists. 66 67 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses. 68 NumImpUses = N - NumExpUses; 69 for (unsigned I = N; I > NumExpUses; --I) { 70 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1))) 71 continue; 72 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1))) 73 if (TargetRegisterInfo::isPhysicalRegister(RN->getReg())) 74 continue; 75 NumImpUses = N - I; 76 break; 77 } 78 79 return N; 80} 81 82/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 83/// implicit physical register output. 84void InstrEmitter:: 85EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 86 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 87 unsigned VRBase = 0; 88 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 89 // Just use the input register directly! 90 SDValue Op(Node, ResNo); 91 if (IsClone) 92 VRBaseMap.erase(Op); 93 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 94 (void)isNew; // Silence compiler warning. 95 assert(isNew && "Node emitted out of order - early"); 96 return; 97 } 98 99 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 100 // the CopyToReg'd destination register instead of creating a new vreg. 101 bool MatchReg = true; 102 const TargetRegisterClass *UseRC = NULL; 103 MVT VT = Node->getSimpleValueType(ResNo); 104 105 // Stick to the preferred register classes for legal types. 106 if (TLI->isTypeLegal(VT)) 107 UseRC = TLI->getRegClassFor(VT); 108 109 if (!IsClone && !IsCloned) 110 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 111 UI != E; ++UI) { 112 SDNode *User = *UI; 113 bool Match = true; 114 if (User->getOpcode() == ISD::CopyToReg && 115 User->getOperand(2).getNode() == Node && 116 User->getOperand(2).getResNo() == ResNo) { 117 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 118 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 119 VRBase = DestReg; 120 Match = false; 121 } else if (DestReg != SrcReg) 122 Match = false; 123 } else { 124 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 125 SDValue Op = User->getOperand(i); 126 if (Op.getNode() != Node || Op.getResNo() != ResNo) 127 continue; 128 MVT VT = Node->getSimpleValueType(Op.getResNo()); 129 if (VT == MVT::Other || VT == MVT::Glue) 130 continue; 131 Match = false; 132 if (User->isMachineOpcode()) { 133 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); 134 const TargetRegisterClass *RC = 0; 135 if (i+II.getNumDefs() < II.getNumOperands()) { 136 RC = TRI->getAllocatableClass( 137 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); 138 } 139 if (!UseRC) 140 UseRC = RC; 141 else if (RC) { 142 const TargetRegisterClass *ComRC = 143 TRI->getCommonSubClass(UseRC, RC); 144 // If multiple uses expect disjoint register classes, we emit 145 // copies in AddRegisterOperand. 146 if (ComRC) 147 UseRC = ComRC; 148 } 149 } 150 } 151 } 152 MatchReg &= Match; 153 if (VRBase) 154 break; 155 } 156 157 const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 158 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 159 160 // Figure out the register class to create for the destreg. 161 if (VRBase) { 162 DstRC = MRI->getRegClass(VRBase); 163 } else if (UseRC) { 164 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 165 DstRC = UseRC; 166 } else { 167 DstRC = TLI->getRegClassFor(VT); 168 } 169 170 // If all uses are reading from the src physical register and copying the 171 // register is either impossible or very expensive, then don't create a copy. 172 if (MatchReg && SrcRC->getCopyCost() < 0) { 173 VRBase = SrcReg; 174 } else { 175 // Create the reg, emit the copy. 176 VRBase = MRI->createVirtualRegister(DstRC); 177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 178 VRBase).addReg(SrcReg); 179 } 180 181 SDValue Op(Node, ResNo); 182 if (IsClone) 183 VRBaseMap.erase(Op); 184 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 185 (void)isNew; // Silence compiler warning. 186 assert(isNew && "Node emitted out of order - early"); 187} 188 189/// getDstOfCopyToRegUse - If the only use of the specified result number of 190/// node is a CopyToReg, return its destination register. Return 0 otherwise. 191unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 192 unsigned ResNo) const { 193 if (!Node->hasOneUse()) 194 return 0; 195 196 SDNode *User = *Node->use_begin(); 197 if (User->getOpcode() == ISD::CopyToReg && 198 User->getOperand(2).getNode() == Node && 199 User->getOperand(2).getResNo() == ResNo) { 200 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 201 if (TargetRegisterInfo::isVirtualRegister(Reg)) 202 return Reg; 203 } 204 return 0; 205} 206 207void InstrEmitter::CreateVirtualRegisters(SDNode *Node, 208 MachineInstrBuilder &MIB, 209 const MCInstrDesc &II, 210 bool IsClone, bool IsCloned, 211 DenseMap<SDValue, unsigned> &VRBaseMap) { 212 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 213 "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 214 215 unsigned NumResults = CountResults(Node); 216 for (unsigned i = 0; i < II.getNumDefs(); ++i) { 217 // If the specific node value is only used by a CopyToReg and the dest reg 218 // is a vreg in the same register class, use the CopyToReg'd destination 219 // register instead of creating a new vreg. 220 unsigned VRBase = 0; 221 const TargetRegisterClass *RC = 222 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 223 // If the register class is unknown for the given definition, then try to 224 // infer one from the value type. 225 if (!RC && i < NumResults) 226 RC = TLI->getRegClassFor(Node->getSimpleValueType(i)); 227 if (II.OpInfo[i].isOptionalDef()) { 228 // Optional def must be a physical register. 229 unsigned NumResults = CountResults(Node); 230 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 231 assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 232 MIB.addReg(VRBase, RegState::Define); 233 } 234 235 if (!VRBase && !IsClone && !IsCloned) 236 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 237 UI != E; ++UI) { 238 SDNode *User = *UI; 239 if (User->getOpcode() == ISD::CopyToReg && 240 User->getOperand(2).getNode() == Node && 241 User->getOperand(2).getResNo() == i) { 242 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 243 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 244 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 245 if (RegRC == RC) { 246 VRBase = Reg; 247 MIB.addReg(VRBase, RegState::Define); 248 break; 249 } 250 } 251 } 252 } 253 254 // Create the result registers for this node and add the result regs to 255 // the machine instruction. 256 if (VRBase == 0) { 257 assert(RC && "Isn't a register operand!"); 258 VRBase = MRI->createVirtualRegister(RC); 259 MIB.addReg(VRBase, RegState::Define); 260 } 261 262 SDValue Op(Node, i); 263 if (IsClone) 264 VRBaseMap.erase(Op); 265 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 266 (void)isNew; // Silence compiler warning. 267 assert(isNew && "Node emitted out of order - early"); 268 } 269} 270 271/// getVR - Return the virtual register corresponding to the specified result 272/// of the specified node. 273unsigned InstrEmitter::getVR(SDValue Op, 274 DenseMap<SDValue, unsigned> &VRBaseMap) { 275 if (Op.isMachineOpcode() && 276 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 277 // Add an IMPLICIT_DEF instruction before every use. 278 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 279 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc 280 // does not include operand register class info. 281 if (!VReg) { 282 const TargetRegisterClass *RC = 283 TLI->getRegClassFor(Op.getSimpleValueType()); 284 VReg = MRI->createVirtualRegister(RC); 285 } 286 BuildMI(*MBB, InsertPos, Op.getDebugLoc(), 287 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 288 return VReg; 289 } 290 291 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 292 assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 293 return I->second; 294} 295 296 297/// AddRegisterOperand - Add the specified register as an operand to the 298/// specified machine instr. Insert register copies if the register is 299/// not in the required register class. 300void 301InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, 302 SDValue Op, 303 unsigned IIOpNum, 304 const MCInstrDesc *II, 305 DenseMap<SDValue, unsigned> &VRBaseMap, 306 bool IsDebug, bool IsClone, bool IsCloned) { 307 assert(Op.getValueType() != MVT::Other && 308 Op.getValueType() != MVT::Glue && 309 "Chain and glue operands should occur at end of operand list!"); 310 // Get/emit the operand. 311 unsigned VReg = getVR(Op, VRBaseMap); 312 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 313 314 const MCInstrDesc &MCID = MIB->getDesc(); 315 bool isOptDef = IIOpNum < MCID.getNumOperands() && 316 MCID.OpInfo[IIOpNum].isOptionalDef(); 317 318 // If the instruction requires a register in a different class, create 319 // a new virtual register and copy the value into it, but first attempt to 320 // shrink VReg's register class within reason. For example, if VReg == GR32 321 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP. 322 if (II) { 323 const TargetRegisterClass *DstRC = 0; 324 if (IIOpNum < II->getNumOperands()) 325 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); 326 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { 327 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 328 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), 329 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 330 VReg = NewVReg; 331 } 332 } 333 334 // If this value has only one use, that use is a kill. This is a 335 // conservative approximation. InstrEmitter does trivial coalescing 336 // with CopyFromReg nodes, so don't emit kill flags for them. 337 // Avoid kill flags on Schedule cloned nodes, since there will be 338 // multiple uses. 339 // Tied operands are never killed, so we need to check that. And that 340 // means we need to determine the index of the operand. 341 bool isKill = Op.hasOneUse() && 342 Op.getNode()->getOpcode() != ISD::CopyFromReg && 343 !IsDebug && 344 !(IsClone || IsCloned); 345 if (isKill) { 346 unsigned Idx = MIB->getNumOperands(); 347 while (Idx > 0 && 348 MIB->getOperand(Idx-1).isReg() && 349 MIB->getOperand(Idx-1).isImplicit()) 350 --Idx; 351 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; 352 if (isTied) 353 isKill = false; 354 } 355 356 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | 357 getDebugRegState(IsDebug)); 358} 359 360/// AddOperand - Add the specified operand to the specified machine instr. II 361/// specifies the instruction information for the node, and IIOpNum is the 362/// operand number (in the II) that we are adding. 363void InstrEmitter::AddOperand(MachineInstrBuilder &MIB, 364 SDValue Op, 365 unsigned IIOpNum, 366 const MCInstrDesc *II, 367 DenseMap<SDValue, unsigned> &VRBaseMap, 368 bool IsDebug, bool IsClone, bool IsCloned) { 369 if (Op.isMachineOpcode()) { 370 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap, 371 IsDebug, IsClone, IsCloned); 372 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 373 MIB.addImm(C->getSExtValue()); 374 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 375 MIB.addFPImm(F->getConstantFPValue()); 376 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 377 // Turn additional physreg operands into implicit uses on non-variadic 378 // instructions. This is used by call and return instructions passing 379 // arguments in registers. 380 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic()); 381 MIB.addReg(R->getReg(), getImplRegState(Imp)); 382 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) { 383 MIB.addRegMask(RM->getRegMask()); 384 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 385 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(), 386 TGA->getTargetFlags()); 387 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 388 MIB.addMBB(BBNode->getBasicBlock()); 389 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 390 MIB.addFrameIndex(FI->getIndex()); 391 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 392 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags()); 393 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 394 int Offset = CP->getOffset(); 395 unsigned Align = CP->getAlignment(); 396 Type *Type = CP->getType(); 397 // MachineConstantPool wants an explicit alignment. 398 if (Align == 0) { 399 Align = TM->getDataLayout()->getPrefTypeAlignment(Type); 400 if (Align == 0) { 401 // Alignment of vector types. FIXME! 402 Align = TM->getDataLayout()->getTypeAllocSize(Type); 403 } 404 } 405 406 unsigned Idx; 407 MachineConstantPool *MCP = MF->getConstantPool(); 408 if (CP->isMachineConstantPoolEntry()) 409 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 410 else 411 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 412 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags()); 413 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 414 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags()); 415 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 416 MIB.addBlockAddress(BA->getBlockAddress(), 417 BA->getOffset(), 418 BA->getTargetFlags()); 419 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) { 420 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags()); 421 } else { 422 assert(Op.getValueType() != MVT::Other && 423 Op.getValueType() != MVT::Glue && 424 "Chain and glue operands should occur at end of operand list!"); 425 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap, 426 IsDebug, IsClone, IsCloned); 427 } 428} 429 430unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, 431 MVT VT, DebugLoc DL) { 432 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); 433 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); 434 435 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg 436 // within reason. 437 if (RC && RC != VRC) 438 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); 439 440 // VReg has been adjusted. It can be used with SubIdx operands now. 441 if (RC) 442 return VReg; 443 444 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual 445 // register instead. 446 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); 447 assert(RC && "No legal register class for VT supports that SubIdx"); 448 unsigned NewReg = MRI->createVirtualRegister(RC); 449 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) 450 .addReg(VReg); 451 return NewReg; 452} 453 454/// EmitSubregNode - Generate machine code for subreg nodes. 455/// 456void InstrEmitter::EmitSubregNode(SDNode *Node, 457 DenseMap<SDValue, unsigned> &VRBaseMap, 458 bool IsClone, bool IsCloned) { 459 unsigned VRBase = 0; 460 unsigned Opc = Node->getMachineOpcode(); 461 462 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 463 // the CopyToReg'd destination register instead of creating a new vreg. 464 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 465 UI != E; ++UI) { 466 SDNode *User = *UI; 467 if (User->getOpcode() == ISD::CopyToReg && 468 User->getOperand(2).getNode() == Node) { 469 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 470 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 471 VRBase = DestReg; 472 break; 473 } 474 } 475 } 476 477 if (Opc == TargetOpcode::EXTRACT_SUBREG) { 478 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no 479 // constraints on the %dst register, COPY can target all legal register 480 // classes. 481 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 482 const TargetRegisterClass *TRC = 483 TLI->getRegClassFor(Node->getSimpleValueType(0)); 484 485 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 486 MachineInstr *DefMI = MRI->getVRegDef(VReg); 487 unsigned SrcReg, DstReg, DefSubIdx; 488 if (DefMI && 489 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && 490 SubIdx == DefSubIdx && 491 TRC == MRI->getRegClass(SrcReg)) { 492 // Optimize these: 493 // r1025 = s/zext r1024, 4 494 // r1026 = extract_subreg r1025, 4 495 // to a copy 496 // r1026 = copy r1024 497 VRBase = MRI->createVirtualRegister(TRC); 498 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 499 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); 500 MRI->clearKillFlags(SrcReg); 501 } else { 502 // VReg may not support a SubIdx sub-register, and we may need to 503 // constrain its register class or issue a COPY to a compatible register 504 // class. 505 VReg = ConstrainForSubReg(VReg, SubIdx, 506 Node->getOperand(0).getSimpleValueType(), 507 Node->getDebugLoc()); 508 509 // Create the destreg if it is missing. 510 if (VRBase == 0) 511 VRBase = MRI->createVirtualRegister(TRC); 512 513 // Create the extract_subreg machine instruction. 514 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 515 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); 516 } 517 } else if (Opc == TargetOpcode::INSERT_SUBREG || 518 Opc == TargetOpcode::SUBREG_TO_REG) { 519 SDValue N0 = Node->getOperand(0); 520 SDValue N1 = Node->getOperand(1); 521 SDValue N2 = Node->getOperand(2); 522 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 523 524 // Figure out the register class to create for the destreg. It should be 525 // the largest legal register class supporting SubIdx sub-registers. 526 // RegisterCoalescer will constrain it further if it decides to eliminate 527 // the INSERT_SUBREG instruction. 528 // 529 // %dst = INSERT_SUBREG %src, %sub, SubIdx 530 // 531 // is lowered by TwoAddressInstructionPass to: 532 // 533 // %dst = COPY %src 534 // %dst:SubIdx = COPY %sub 535 // 536 // There is no constraint on the %src register class. 537 // 538 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0)); 539 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); 540 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG"); 541 542 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) 543 VRBase = MRI->createVirtualRegister(SRC); 544 545 // Create the insert_subreg or subreg_to_reg machine instruction. 546 MachineInstrBuilder MIB = 547 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase); 548 549 // If creating a subreg_to_reg, then the first input operand 550 // is an implicit value immediate, otherwise it's a register 551 if (Opc == TargetOpcode::SUBREG_TO_REG) { 552 const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 553 MIB.addImm(SD->getZExtValue()); 554 } else 555 AddOperand(MIB, N0, 0, 0, VRBaseMap, /*IsDebug=*/false, 556 IsClone, IsCloned); 557 // Add the subregster being inserted 558 AddOperand(MIB, N1, 0, 0, VRBaseMap, /*IsDebug=*/false, 559 IsClone, IsCloned); 560 MIB.addImm(SubIdx); 561 MBB->insert(InsertPos, MIB); 562 } else 563 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 564 565 SDValue Op(Node, 0); 566 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 567 (void)isNew; // Silence compiler warning. 568 assert(isNew && "Node emitted out of order - early"); 569} 570 571/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 572/// COPY_TO_REGCLASS is just a normal copy, except that the destination 573/// register is constrained to be in a particular register class. 574/// 575void 576InstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 577 DenseMap<SDValue, unsigned> &VRBaseMap) { 578 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 579 580 // Create the new VReg in the destination class and emit a copy. 581 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 582 const TargetRegisterClass *DstRC = 583 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); 584 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 585 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 586 NewVReg).addReg(VReg); 587 588 SDValue Op(Node, 0); 589 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 590 (void)isNew; // Silence compiler warning. 591 assert(isNew && "Node emitted out of order - early"); 592} 593 594/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 595/// 596void InstrEmitter::EmitRegSequence(SDNode *Node, 597 DenseMap<SDValue, unsigned> &VRBaseMap, 598 bool IsClone, bool IsCloned) { 599 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue(); 600 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); 601 unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC)); 602 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 603 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg); 604 unsigned NumOps = Node->getNumOperands(); 605 assert((NumOps & 1) == 1 && 606 "REG_SEQUENCE must have an odd number of operands!"); 607 for (unsigned i = 1; i != NumOps; ++i) { 608 SDValue Op = Node->getOperand(i); 609 if ((i & 1) == 0) { 610 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1)); 611 // Skip physical registers as they don't have a vreg to get and we'll 612 // insert copies for them in TwoAddressInstructionPass anyway. 613 if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 614 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 615 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 616 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 617 const TargetRegisterClass *SRC = 618 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); 619 if (SRC && SRC != RC) { 620 MRI->setRegClass(NewVReg, SRC); 621 RC = SRC; 622 } 623 } 624 } 625 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false, 626 IsClone, IsCloned); 627 } 628 629 MBB->insert(InsertPos, MIB); 630 SDValue Op(Node, 0); 631 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 632 (void)isNew; // Silence compiler warning. 633 assert(isNew && "Node emitted out of order - early"); 634} 635 636/// EmitDbgValue - Generate machine instruction for a dbg_value node. 637/// 638MachineInstr * 639InstrEmitter::EmitDbgValue(SDDbgValue *SD, 640 DenseMap<SDValue, unsigned> &VRBaseMap) { 641 uint64_t Offset = SD->getOffset(); 642 MDNode* MDPtr = SD->getMDPtr(); 643 DebugLoc DL = SD->getDebugLoc(); 644 645 if (SD->getKind() == SDDbgValue::FRAMEIX) { 646 // Stack address; this needs to be lowered in target-dependent fashion. 647 // EmitTargetCodeForFrameDebugValue is responsible for allocation. 648 return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE)) 649 .addFrameIndex(SD->getFrameIx()).addImm(Offset).addMetadata(MDPtr); 650 } 651 // Otherwise, we're going to create an instruction here. 652 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 653 MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 654 if (SD->getKind() == SDDbgValue::SDNODE) { 655 SDNode *Node = SD->getSDNode(); 656 SDValue Op = SDValue(Node, SD->getResNo()); 657 // It's possible we replaced this SDNode with other(s) and therefore 658 // didn't generate code for it. It's better to catch these cases where 659 // they happen and transfer the debug info, but trying to guarantee that 660 // in all cases would be very fragile; this is a safeguard for any 661 // that were missed. 662 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 663 if (I==VRBaseMap.end()) 664 MIB.addReg(0U); // undef 665 else 666 AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 667 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false); 668 } else if (SD->getKind() == SDDbgValue::CONST) { 669 const Value *V = SD->getConst(); 670 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 671 if (CI->getBitWidth() > 64) 672 MIB.addCImm(CI); 673 else 674 MIB.addImm(CI->getSExtValue()); 675 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 676 MIB.addFPImm(CF); 677 } else { 678 // Could be an Undef. In any case insert an Undef so we can see what we 679 // dropped. 680 MIB.addReg(0U); 681 } 682 } else { 683 // Insert an Undef so we can see what we dropped. 684 MIB.addReg(0U); 685 } 686 687 if (Offset != 0) // Indirect addressing. 688 MIB.addImm(Offset); 689 else 690 MIB.addReg(0U, RegState::Debug); 691 692 MIB.addMetadata(MDPtr); 693 694 return &*MIB; 695} 696 697/// EmitMachineNode - Generate machine code for a target-specific node and 698/// needed dependencies. 699/// 700void InstrEmitter:: 701EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 702 DenseMap<SDValue, unsigned> &VRBaseMap) { 703 unsigned Opc = Node->getMachineOpcode(); 704 705 // Handle subreg insert/extract specially 706 if (Opc == TargetOpcode::EXTRACT_SUBREG || 707 Opc == TargetOpcode::INSERT_SUBREG || 708 Opc == TargetOpcode::SUBREG_TO_REG) { 709 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned); 710 return; 711 } 712 713 // Handle COPY_TO_REGCLASS specially. 714 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 715 EmitCopyToRegClassNode(Node, VRBaseMap); 716 return; 717 } 718 719 // Handle REG_SEQUENCE specially. 720 if (Opc == TargetOpcode::REG_SEQUENCE) { 721 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned); 722 return; 723 } 724 725 if (Opc == TargetOpcode::IMPLICIT_DEF) 726 // We want a unique VR for each IMPLICIT_DEF use. 727 return; 728 729 const MCInstrDesc &II = TII->get(Opc); 730 unsigned NumResults = CountResults(Node); 731 unsigned NumDefs = II.getNumDefs(); 732 const uint16_t *ScratchRegs = NULL; 733 734 // Handle PATCHPOINT specially and then use the generic code. 735 if (Opc == TargetOpcode::PATCHPOINT) { 736 unsigned CC = Node->getConstantOperandVal(PatchPointOpers::CCPos); 737 NumDefs = NumResults; 738 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC); 739 } 740 741 unsigned NumImpUses = 0; 742 unsigned NodeOperands = 743 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses); 744 bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=0; 745#ifndef NDEBUG 746 unsigned NumMIOperands = NodeOperands + NumResults; 747 if (II.isVariadic()) 748 assert(NumMIOperands >= II.getNumOperands() && 749 "Too few operands for a variadic node!"); 750 else 751 assert(NumMIOperands >= II.getNumOperands() && 752 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + 753 NumImpUses && 754 "#operands for dag node doesn't match .td file!"); 755#endif 756 757 // Create the new machine instruction. 758 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II); 759 760 // Add result register values for things that are defined by this 761 // instruction. 762 if (NumResults) 763 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap); 764 765 // Emit all of the actual operands of this instruction, adding them to the 766 // instruction as appropriate. 767 bool HasOptPRefs = NumDefs > NumResults; 768 assert((!HasOptPRefs || !HasPhysRegOuts) && 769 "Unable to cope with optional defs and phys regs defs!"); 770 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0; 771 for (unsigned i = NumSkip; i != NodeOperands; ++i) 772 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II, 773 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned); 774 775 // Add scratch registers as implicit def and early clobber 776 if (ScratchRegs) 777 for (unsigned i = 0; ScratchRegs[i]; ++i) 778 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | 779 RegState::EarlyClobber); 780 781 // Transfer all of the memory reference descriptions of this instruction. 782 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 783 cast<MachineSDNode>(Node)->memoperands_end()); 784 785 // Insert the instruction into position in the block. This needs to 786 // happen before any custom inserter hook is called so that the 787 // hook knows where in the block to insert the replacement code. 788 MBB->insert(InsertPos, MIB); 789 790 // The MachineInstr may also define physregs instead of virtregs. These 791 // physreg values can reach other instructions in different ways: 792 // 793 // 1. When there is a use of a Node value beyond the explicitly defined 794 // virtual registers, we emit a CopyFromReg for one of the implicitly 795 // defined physregs. This only happens when HasPhysRegOuts is true. 796 // 797 // 2. A CopyFromReg reading a physreg may be glued to this instruction. 798 // 799 // 3. A glued instruction may implicitly use a physreg. 800 // 801 // 4. A glued instruction may use a RegisterSDNode operand. 802 // 803 // Collect all the used physreg defs, and make sure that any unused physreg 804 // defs are marked as dead. 805 SmallVector<unsigned, 8> UsedRegs; 806 807 // Additional results must be physical register defs. 808 if (HasPhysRegOuts) { 809 for (unsigned i = NumDefs; i < NumResults; ++i) { 810 unsigned Reg = II.getImplicitDefs()[i - NumDefs]; 811 if (!Node->hasAnyUseOfValue(i)) 812 continue; 813 // This implicitly defined physreg has a use. 814 UsedRegs.push_back(Reg); 815 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 816 } 817 } 818 819 // Scan the glue chain for any used physregs. 820 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) { 821 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) { 822 if (F->getOpcode() == ISD::CopyFromReg) { 823 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); 824 continue; 825 } else if (F->getOpcode() == ISD::CopyToReg) { 826 // Skip CopyToReg nodes that are internal to the glue chain. 827 continue; 828 } 829 // Collect declared implicit uses. 830 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); 831 UsedRegs.append(MCID.getImplicitUses(), 832 MCID.getImplicitUses() + MCID.getNumImplicitUses()); 833 // In addition to declared implicit uses, we must also check for 834 // direct RegisterSDNode operands. 835 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i) 836 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) { 837 unsigned Reg = R->getReg(); 838 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 839 UsedRegs.push_back(Reg); 840 } 841 } 842 } 843 844 // Finally mark unused registers as dead. 845 if (!UsedRegs.empty() || II.getImplicitDefs()) 846 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI); 847 848 // Run post-isel target hook to adjust this instruction if needed. 849#ifdef NDEBUG 850 if (II.hasPostISelHook()) 851#endif 852 TLI->AdjustInstrPostInstrSelection(MIB, Node); 853} 854 855/// EmitSpecialNode - Generate machine code for a target-independent node and 856/// needed dependencies. 857void InstrEmitter:: 858EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 859 DenseMap<SDValue, unsigned> &VRBaseMap) { 860 switch (Node->getOpcode()) { 861 default: 862#ifndef NDEBUG 863 Node->dump(); 864#endif 865 llvm_unreachable("This target-independent node should have been selected!"); 866 case ISD::EntryToken: 867 llvm_unreachable("EntryToken should have been excluded from the schedule!"); 868 case ISD::MERGE_VALUES: 869 case ISD::TokenFactor: // fall thru 870 break; 871 case ISD::CopyToReg: { 872 unsigned SrcReg; 873 SDValue SrcVal = Node->getOperand(2); 874 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 875 SrcReg = R->getReg(); 876 else 877 SrcReg = getVR(SrcVal, VRBaseMap); 878 879 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 880 if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 881 break; 882 883 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 884 DestReg).addReg(SrcReg); 885 break; 886 } 887 case ISD::CopyFromReg: { 888 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 889 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 890 break; 891 } 892 case ISD::EH_LABEL: { 893 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 894 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 895 TII->get(TargetOpcode::EH_LABEL)).addSym(S); 896 break; 897 } 898 899 case ISD::LIFETIME_START: 900 case ISD::LIFETIME_END: { 901 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ? 902 TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END; 903 904 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1)); 905 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp)) 906 .addFrameIndex(FI->getIndex()); 907 break; 908 } 909 910 case ISD::INLINEASM: { 911 unsigned NumOps = Node->getNumOperands(); 912 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 913 --NumOps; // Ignore the glue operand. 914 915 // Create the inline asm machine instruction. 916 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), 917 TII->get(TargetOpcode::INLINEASM)); 918 919 // Add the asm string as an external symbol operand. 920 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 921 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 922 MIB.addExternalSymbol(AsmStr); 923 924 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore 925 // bits. 926 int64_t ExtraInfo = 927 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))-> 928 getZExtValue(); 929 MIB.addImm(ExtraInfo); 930 931 // Remember to operand index of the group flags. 932 SmallVector<unsigned, 8> GroupIdx; 933 934 // Add all of the operand registers to the instruction. 935 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 936 unsigned Flags = 937 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 938 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 939 940 GroupIdx.push_back(MIB->getNumOperands()); 941 MIB.addImm(Flags); 942 ++i; // Skip the ID value. 943 944 switch (InlineAsm::getKind(Flags)) { 945 default: llvm_unreachable("Bad flags!"); 946 case InlineAsm::Kind_RegDef: 947 for (unsigned j = 0; j != NumVals; ++j, ++i) { 948 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 949 // FIXME: Add dead flags for physical and virtual registers defined. 950 // For now, mark physical register defs as implicit to help fast 951 // regalloc. This makes inline asm look a lot like calls. 952 MIB.addReg(Reg, RegState::Define | 953 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg))); 954 } 955 break; 956 case InlineAsm::Kind_RegDefEarlyClobber: 957 case InlineAsm::Kind_Clobber: 958 for (unsigned j = 0; j != NumVals; ++j, ++i) { 959 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 960 MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber | 961 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg))); 962 } 963 break; 964 case InlineAsm::Kind_RegUse: // Use of register. 965 case InlineAsm::Kind_Imm: // Immediate. 966 case InlineAsm::Kind_Mem: // Addressing mode. 967 // The addressing mode has been selected, just add all of the 968 // operands to the machine instruction. 969 for (unsigned j = 0; j != NumVals; ++j, ++i) 970 AddOperand(MIB, Node->getOperand(i), 0, 0, VRBaseMap, 971 /*IsDebug=*/false, IsClone, IsCloned); 972 973 // Manually set isTied bits. 974 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) { 975 unsigned DefGroup = 0; 976 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) { 977 unsigned DefIdx = GroupIdx[DefGroup] + 1; 978 unsigned UseIdx = GroupIdx.back() + 1; 979 for (unsigned j = 0; j != NumVals; ++j) 980 MIB->tieOperands(DefIdx + j, UseIdx + j); 981 } 982 } 983 break; 984 } 985 } 986 987 // Get the mdnode from the asm if it exists and add it to the instruction. 988 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 989 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 990 if (MD) 991 MIB.addMetadata(MD); 992 993 MBB->insert(InsertPos, MIB); 994 break; 995 } 996 } 997} 998 999/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 1000/// at the given position in the given block. 1001InstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 1002 MachineBasicBlock::iterator insertpos) 1003 : MF(mbb->getParent()), 1004 MRI(&MF->getRegInfo()), 1005 TM(&MF->getTarget()), 1006 TII(TM->getInstrInfo()), 1007 TRI(TM->getRegisterInfo()), 1008 TLI(TM->getTargetLowering()), 1009 MBB(mbb), InsertPos(insertpos) { 1010} 1011