LegalizeDAG.cpp revision 01ff7216dd7829d4094754086baf28aa2d7149ac
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineConstantPool.h" 16#include "llvm/CodeGen/MachineFunction.h" 17#include "llvm/CodeGen/MachineFrameInfo.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/Constants.h" 22#include <iostream> 23using namespace llvm; 24 25//===----------------------------------------------------------------------===// 26/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 27/// hacks on it until the target machine can handle it. This involves 28/// eliminating value sizes the machine cannot handle (promoting small sizes to 29/// large sizes or splitting up large values into small values) as well as 30/// eliminating operations the machine cannot handle. 31/// 32/// This code also does a small amount of optimization and recognition of idioms 33/// as part of its processing. For example, if a target does not support a 34/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 35/// will attempt merge setcc and brc instructions into brcc's. 36/// 37namespace { 38class SelectionDAGLegalize { 39 TargetLowering &TLI; 40 SelectionDAG &DAG; 41 42 /// LegalizeAction - This enum indicates what action we should take for each 43 /// value type the can occur in the program. 44 enum LegalizeAction { 45 Legal, // The target natively supports this value type. 46 Promote, // This should be promoted to the next larger type. 47 Expand, // This integer type should be broken into smaller pieces. 48 }; 49 50 /// ValueTypeActions - This is a bitvector that contains two bits for each 51 /// value type, where the two bits correspond to the LegalizeAction enum. 52 /// This can be queried with "getTypeAction(VT)". 53 unsigned ValueTypeActions; 54 55 /// NeedsAnotherIteration - This is set when we expand a large integer 56 /// operation into smaller integer operations, but the smaller operations are 57 /// not set. This occurs only rarely in practice, for targets that don't have 58 /// 32-bit or larger integer registers. 59 bool NeedsAnotherIteration; 60 61 /// LegalizedNodes - For nodes that are of legal width, and that have more 62 /// than one use, this map indicates what regularized operand to use. This 63 /// allows us to avoid legalizing the same thing more than once. 64 std::map<SDOperand, SDOperand> LegalizedNodes; 65 66 /// PromotedNodes - For nodes that are below legal width, and that have more 67 /// than one use, this map indicates what promoted value to use. This allows 68 /// us to avoid promoting the same thing more than once. 69 std::map<SDOperand, SDOperand> PromotedNodes; 70 71 /// ExpandedNodes - For nodes that need to be expanded, and which have more 72 /// than one use, this map indicates which which operands are the expanded 73 /// version of the input. This allows us to avoid expanding the same node 74 /// more than once. 75 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 76 77 void AddLegalizedOperand(SDOperand From, SDOperand To) { 78 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second; 79 assert(isNew && "Got into the map somehow?"); 80 } 81 void AddPromotedOperand(SDOperand From, SDOperand To) { 82 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 83 assert(isNew && "Got into the map somehow?"); 84 } 85 86public: 87 88 SelectionDAGLegalize(SelectionDAG &DAG); 89 90 /// Run - While there is still lowering to do, perform a pass over the DAG. 91 /// Most regularization can be done in a single pass, but targets that require 92 /// large values to be split into registers multiple times (e.g. i64 -> 4x 93 /// i16) require iteration for these values (the first iteration will demote 94 /// to i32, the second will demote to i16). 95 void Run() { 96 do { 97 NeedsAnotherIteration = false; 98 LegalizeDAG(); 99 } while (NeedsAnotherIteration); 100 } 101 102 /// getTypeAction - Return how we should legalize values of this type, either 103 /// it is already legal or we need to expand it into multiple registers of 104 /// smaller integer type, or we need to promote it to a larger type. 105 LegalizeAction getTypeAction(MVT::ValueType VT) const { 106 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 107 } 108 109 /// isTypeLegal - Return true if this type is legal on this target. 110 /// 111 bool isTypeLegal(MVT::ValueType VT) const { 112 return getTypeAction(VT) == Legal; 113 } 114 115private: 116 void LegalizeDAG(); 117 118 SDOperand LegalizeOp(SDOperand O); 119 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 120 SDOperand PromoteOp(SDOperand O); 121 122 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 123 SDOperand &Hi); 124 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 125 SDOperand Source); 126 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 127 SDOperand &Lo, SDOperand &Hi); 128 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 129 SDOperand &Lo, SDOperand &Hi); 130 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 131 SDOperand &Lo, SDOperand &Hi); 132 133 SDOperand getIntPtrConstant(uint64_t Val) { 134 return DAG.getConstant(Val, TLI.getPointerTy()); 135 } 136}; 137} 138 139 140SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 141 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 142 ValueTypeActions(TLI.getValueTypeActions()) { 143 assert(MVT::LAST_VALUETYPE <= 16 && 144 "Too many value types for ValueTypeActions to hold!"); 145} 146 147void SelectionDAGLegalize::LegalizeDAG() { 148 SDOperand OldRoot = DAG.getRoot(); 149 SDOperand NewRoot = LegalizeOp(OldRoot); 150 DAG.setRoot(NewRoot); 151 152 ExpandedNodes.clear(); 153 LegalizedNodes.clear(); 154 PromotedNodes.clear(); 155 156 // Remove dead nodes now. 157 DAG.RemoveDeadNodes(OldRoot.Val); 158} 159 160SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 161 assert(getTypeAction(Op.getValueType()) == Legal && 162 "Caller should expand or promote operands that are not legal!"); 163 164 // If this operation defines any values that cannot be represented in a 165 // register on this target, make sure to expand or promote them. 166 if (Op.Val->getNumValues() > 1) { 167 for (unsigned i = 0, e = Op.Val->getNumValues(); i != e; ++i) 168 switch (getTypeAction(Op.Val->getValueType(i))) { 169 case Legal: break; // Nothing to do. 170 case Expand: { 171 SDOperand T1, T2; 172 ExpandOp(Op.getValue(i), T1, T2); 173 assert(LegalizedNodes.count(Op) && 174 "Expansion didn't add legal operands!"); 175 return LegalizedNodes[Op]; 176 } 177 case Promote: 178 PromoteOp(Op.getValue(i)); 179 assert(LegalizedNodes.count(Op) && 180 "Expansion didn't add legal operands!"); 181 return LegalizedNodes[Op]; 182 } 183 } 184 185 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 186 if (I != LegalizedNodes.end()) return I->second; 187 188 SDOperand Tmp1, Tmp2, Tmp3; 189 190 SDOperand Result = Op; 191 SDNode *Node = Op.Val; 192 193 switch (Node->getOpcode()) { 194 default: 195 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 196 assert(0 && "Do not know how to legalize this operator!"); 197 abort(); 198 case ISD::EntryToken: 199 case ISD::FrameIndex: 200 case ISD::GlobalAddress: 201 case ISD::ExternalSymbol: 202 case ISD::ConstantPool: // Nothing to do. 203 assert(getTypeAction(Node->getValueType(0)) == Legal && 204 "This must be legal!"); 205 break; 206 case ISD::CopyFromReg: 207 Tmp1 = LegalizeOp(Node->getOperand(0)); 208 if (Tmp1 != Node->getOperand(0)) 209 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), 210 Node->getValueType(0), Tmp1); 211 else 212 Result = Op.getValue(0); 213 214 // Since CopyFromReg produces two values, make sure to remember that we 215 // legalized both of them. 216 AddLegalizedOperand(Op.getValue(0), Result); 217 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 218 return Result.getValue(Op.ResNo); 219 case ISD::ImplicitDef: 220 Tmp1 = LegalizeOp(Node->getOperand(0)); 221 if (Tmp1 != Node->getOperand(0)) 222 Result = DAG.getImplicitDef(Tmp1, cast<RegSDNode>(Node)->getReg()); 223 break; 224 case ISD::UNDEF: { 225 MVT::ValueType VT = Op.getValueType(); 226 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 227 default: assert(0 && "This action is not supported yet!"); 228 case TargetLowering::Expand: 229 case TargetLowering::Promote: 230 if (MVT::isInteger(VT)) 231 Result = DAG.getConstant(0, VT); 232 else if (MVT::isFloatingPoint(VT)) 233 Result = DAG.getConstantFP(0, VT); 234 else 235 assert(0 && "Unknown value type!"); 236 break; 237 case TargetLowering::Legal: 238 break; 239 } 240 break; 241 } 242 case ISD::Constant: 243 // We know we don't need to expand constants here, constants only have one 244 // value and we check that it is fine above. 245 246 // FIXME: Maybe we should handle things like targets that don't support full 247 // 32-bit immediates? 248 break; 249 case ISD::ConstantFP: { 250 // Spill FP immediates to the constant pool if the target cannot directly 251 // codegen them. Targets often have some immediate values that can be 252 // efficiently generated into an FP register without a load. We explicitly 253 // leave these constants as ConstantFP nodes for the target to deal with. 254 255 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 256 257 // Check to see if this FP immediate is already legal. 258 bool isLegal = false; 259 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 260 E = TLI.legal_fpimm_end(); I != E; ++I) 261 if (CFP->isExactlyValue(*I)) { 262 isLegal = true; 263 break; 264 } 265 266 if (!isLegal) { 267 // Otherwise we need to spill the constant to memory. 268 MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool(); 269 270 bool Extend = false; 271 272 // If a FP immediate is precise when represented as a float, we put it 273 // into the constant pool as a float, even if it's is statically typed 274 // as a double. 275 MVT::ValueType VT = CFP->getValueType(0); 276 bool isDouble = VT == MVT::f64; 277 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 278 Type::FloatTy, CFP->getValue()); 279 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 280 // Only do this if the target has a native EXTLOAD instruction from 281 // f32. 282 TLI.getOperationAction(ISD::EXTLOAD, 283 MVT::f32) == TargetLowering::Legal) { 284 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 285 VT = MVT::f32; 286 Extend = true; 287 } 288 289 SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(LLVMC), 290 TLI.getPointerTy()); 291 if (Extend) { 292 Result = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), CPIdx, 293 MVT::f32); 294 } else { 295 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx); 296 } 297 } 298 break; 299 } 300 case ISD::TokenFactor: { 301 std::vector<SDOperand> Ops; 302 bool Changed = false; 303 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 304 SDOperand Op = Node->getOperand(i); 305 // Fold single-use TokenFactor nodes into this token factor as we go. 306 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 307 Changed = true; 308 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 309 Ops.push_back(LegalizeOp(Op.getOperand(j))); 310 } else { 311 Ops.push_back(LegalizeOp(Op)); // Legalize the operands 312 Changed |= Ops[i] != Op; 313 } 314 } 315 if (Changed) 316 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 317 break; 318 } 319 320 case ISD::ADJCALLSTACKDOWN: 321 case ISD::ADJCALLSTACKUP: 322 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 323 // There is no need to legalize the size argument (Operand #1) 324 if (Tmp1 != Node->getOperand(0)) 325 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 326 Node->getOperand(1)); 327 break; 328 case ISD::DYNAMIC_STACKALLOC: 329 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 330 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 331 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 332 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 333 Tmp3 != Node->getOperand(2)) 334 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, Node->getValueType(0), 335 Tmp1, Tmp2, Tmp3); 336 else 337 Result = Op.getValue(0); 338 339 // Since this op produces two values, make sure to remember that we 340 // legalized both of them. 341 AddLegalizedOperand(SDOperand(Node, 0), Result); 342 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 343 return Result.getValue(Op.ResNo); 344 345 case ISD::CALL: { 346 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 347 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 348 349 bool Changed = false; 350 std::vector<SDOperand> Ops; 351 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 352 Ops.push_back(LegalizeOp(Node->getOperand(i))); 353 Changed |= Ops.back() != Node->getOperand(i); 354 } 355 356 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 357 std::vector<MVT::ValueType> RetTyVTs; 358 RetTyVTs.reserve(Node->getNumValues()); 359 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 360 RetTyVTs.push_back(Node->getValueType(i)); 361 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops), 0); 362 } else { 363 Result = Result.getValue(0); 364 } 365 // Since calls produce multiple values, make sure to remember that we 366 // legalized all of them. 367 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 368 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 369 return Result.getValue(Op.ResNo); 370 } 371 case ISD::BR: 372 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 373 if (Tmp1 != Node->getOperand(0)) 374 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 375 break; 376 377 case ISD::BRCOND: 378 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 379 380 switch (getTypeAction(Node->getOperand(1).getValueType())) { 381 case Expand: assert(0 && "It's impossible to expand bools"); 382 case Legal: 383 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 384 break; 385 case Promote: 386 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 387 break; 388 } 389 // Basic block destination (Op#2) is always legal. 390 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 391 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 392 Node->getOperand(2)); 393 break; 394 case ISD::BRCONDTWOWAY: 395 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 396 switch (getTypeAction(Node->getOperand(1).getValueType())) { 397 case Expand: assert(0 && "It's impossible to expand bools"); 398 case Legal: 399 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 400 break; 401 case Promote: 402 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 403 break; 404 } 405 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 406 // pair. 407 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 408 case TargetLowering::Promote: 409 default: assert(0 && "This action is not supported yet!"); 410 case TargetLowering::Legal: 411 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 412 std::vector<SDOperand> Ops; 413 Ops.push_back(Tmp1); 414 Ops.push_back(Tmp2); 415 Ops.push_back(Node->getOperand(2)); 416 Ops.push_back(Node->getOperand(3)); 417 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 418 } 419 break; 420 case TargetLowering::Expand: 421 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 422 Node->getOperand(2)); 423 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 424 break; 425 } 426 break; 427 428 case ISD::LOAD: 429 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 430 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 431 if (Tmp1 != Node->getOperand(0) || 432 Tmp2 != Node->getOperand(1)) 433 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2); 434 else 435 Result = SDOperand(Node, 0); 436 437 // Since loads produce two values, make sure to remember that we legalized 438 // both of them. 439 AddLegalizedOperand(SDOperand(Node, 0), Result); 440 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 441 return Result.getValue(Op.ResNo); 442 443 case ISD::EXTLOAD: 444 case ISD::SEXTLOAD: 445 case ISD::ZEXTLOAD: { 446 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 447 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 448 449 MVT::ValueType SrcVT = cast<MVTSDNode>(Node)->getExtraValueType(); 450 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 451 case TargetLowering::Promote: 452 default: assert(0 && "This action is not supported yet!"); 453 case TargetLowering::Legal: 454 if (Tmp1 != Node->getOperand(0) || 455 Tmp2 != Node->getOperand(1)) 456 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), 457 Tmp1, Tmp2, SrcVT); 458 else 459 Result = SDOperand(Node, 0); 460 461 // Since loads produce two values, make sure to remember that we legalized 462 // both of them. 463 AddLegalizedOperand(SDOperand(Node, 0), Result); 464 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 465 return Result.getValue(Op.ResNo); 466 break; 467 case TargetLowering::Expand: 468 assert(Node->getOpcode() != ISD::EXTLOAD && 469 "EXTLOAD should always be supported!"); 470 // Turn the unsupported load into an EXTLOAD followed by an explicit 471 // zero/sign extend inreg. 472 Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0), 473 Tmp1, Tmp2, SrcVT); 474 unsigned ExtOp = Node->getOpcode() == ISD::SEXTLOAD ? 475 ISD::SIGN_EXTEND_INREG : ISD::ZERO_EXTEND_INREG; 476 SDOperand ValRes = DAG.getNode(ExtOp, Result.getValueType(), 477 Result, SrcVT); 478 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 479 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 480 if (Op.ResNo) 481 return Result.getValue(1); 482 return ValRes; 483 } 484 assert(0 && "Unreachable"); 485 } 486 case ISD::EXTRACT_ELEMENT: 487 // Get both the low and high parts. 488 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 489 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 490 Result = Tmp2; // 1 -> Hi 491 else 492 Result = Tmp1; // 0 -> Lo 493 break; 494 495 case ISD::CopyToReg: 496 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 497 498 switch (getTypeAction(Node->getOperand(1).getValueType())) { 499 case Legal: 500 // Legalize the incoming value (must be legal). 501 Tmp2 = LegalizeOp(Node->getOperand(1)); 502 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 503 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg()); 504 break; 505 case Promote: 506 Tmp2 = PromoteOp(Node->getOperand(1)); 507 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg()); 508 break; 509 case Expand: 510 SDOperand Lo, Hi; 511 ExpandOp(Node->getOperand(1), Lo, Hi); 512 unsigned Reg = cast<RegSDNode>(Node)->getReg(); 513 Lo = DAG.getCopyToReg(Tmp1, Lo, Reg); 514 Hi = DAG.getCopyToReg(Tmp1, Hi, Reg+1); 515 // Note that the copytoreg nodes are independent of each other. 516 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 517 assert(isTypeLegal(Result.getValueType()) && 518 "Cannot expand multiple times yet (i64 -> i16)"); 519 break; 520 } 521 break; 522 523 case ISD::RET: 524 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 525 switch (Node->getNumOperands()) { 526 case 2: // ret val 527 switch (getTypeAction(Node->getOperand(1).getValueType())) { 528 case Legal: 529 Tmp2 = LegalizeOp(Node->getOperand(1)); 530 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 531 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 532 break; 533 case Expand: { 534 SDOperand Lo, Hi; 535 ExpandOp(Node->getOperand(1), Lo, Hi); 536 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 537 break; 538 } 539 case Promote: 540 Tmp2 = PromoteOp(Node->getOperand(1)); 541 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 542 break; 543 } 544 break; 545 case 1: // ret void 546 if (Tmp1 != Node->getOperand(0)) 547 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 548 break; 549 default: { // ret <values> 550 std::vector<SDOperand> NewValues; 551 NewValues.push_back(Tmp1); 552 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 553 switch (getTypeAction(Node->getOperand(i).getValueType())) { 554 case Legal: 555 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 556 break; 557 case Expand: { 558 SDOperand Lo, Hi; 559 ExpandOp(Node->getOperand(i), Lo, Hi); 560 NewValues.push_back(Lo); 561 NewValues.push_back(Hi); 562 break; 563 } 564 case Promote: 565 assert(0 && "Can't promote multiple return value yet!"); 566 } 567 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 568 break; 569 } 570 } 571 break; 572 case ISD::STORE: 573 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 574 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 575 576 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 577 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 578 if (CFP->getValueType(0) == MVT::f32) { 579 union { 580 unsigned I; 581 float F; 582 } V; 583 V.F = CFP->getValue(); 584 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 585 DAG.getConstant(V.I, MVT::i32), Tmp2); 586 } else { 587 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 588 union { 589 uint64_t I; 590 double F; 591 } V; 592 V.F = CFP->getValue(); 593 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 594 DAG.getConstant(V.I, MVT::i64), Tmp2); 595 } 596 Node = Result.Val; 597 } 598 599 switch (getTypeAction(Node->getOperand(1).getValueType())) { 600 case Legal: { 601 SDOperand Val = LegalizeOp(Node->getOperand(1)); 602 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 603 Tmp2 != Node->getOperand(2)) 604 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2); 605 break; 606 } 607 case Promote: 608 // Truncate the value and store the result. 609 Tmp3 = PromoteOp(Node->getOperand(1)); 610 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 611 Node->getOperand(1).getValueType()); 612 break; 613 614 case Expand: 615 SDOperand Lo, Hi; 616 ExpandOp(Node->getOperand(1), Lo, Hi); 617 618 if (!TLI.isLittleEndian()) 619 std::swap(Lo, Hi); 620 621 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2); 622 623 unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 624 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 625 getIntPtrConstant(IncrementSize)); 626 assert(isTypeLegal(Tmp2.getValueType()) && 627 "Pointers must be legal!"); 628 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2); 629 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 630 break; 631 } 632 break; 633 case ISD::PCMARKER: 634 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 635 if (Tmp1 != Node->getOperand(0)) 636 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 637 break; 638 case ISD::TRUNCSTORE: 639 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 640 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 641 642 switch (getTypeAction(Node->getOperand(1).getValueType())) { 643 case Legal: 644 Tmp2 = LegalizeOp(Node->getOperand(1)); 645 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 646 Tmp3 != Node->getOperand(2)) 647 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 648 cast<MVTSDNode>(Node)->getExtraValueType()); 649 break; 650 case Promote: 651 case Expand: 652 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 653 } 654 break; 655 case ISD::SELECT: 656 switch (getTypeAction(Node->getOperand(0).getValueType())) { 657 case Expand: assert(0 && "It's impossible to expand bools"); 658 case Legal: 659 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 660 break; 661 case Promote: 662 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 663 break; 664 } 665 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 666 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 667 668 switch (TLI.getOperationAction(Node->getOpcode(), Tmp2.getValueType())) { 669 default: assert(0 && "This action is not supported yet!"); 670 case TargetLowering::Legal: 671 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 672 Tmp3 != Node->getOperand(2)) 673 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 674 Tmp1, Tmp2, Tmp3); 675 break; 676 case TargetLowering::Promote: { 677 MVT::ValueType NVT = 678 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 679 unsigned ExtOp, TruncOp; 680 if (MVT::isInteger(Tmp2.getValueType())) { 681 ExtOp = ISD::ZERO_EXTEND; 682 TruncOp = ISD::TRUNCATE; 683 } else { 684 ExtOp = ISD::FP_EXTEND; 685 TruncOp = ISD::FP_ROUND; 686 } 687 // Promote each of the values to the new type. 688 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 689 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 690 // Perform the larger operation, then round down. 691 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 692 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 693 break; 694 } 695 } 696 break; 697 case ISD::SETCC: 698 switch (getTypeAction(Node->getOperand(0).getValueType())) { 699 case Legal: 700 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 701 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 702 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 703 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 704 Node->getValueType(0), Tmp1, Tmp2); 705 break; 706 case Promote: 707 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 708 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 709 710 // If this is an FP compare, the operands have already been extended. 711 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 712 MVT::ValueType VT = Node->getOperand(0).getValueType(); 713 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 714 715 // Otherwise, we have to insert explicit sign or zero extends. Note 716 // that we could insert sign extends for ALL conditions, but zero extend 717 // is cheaper on many machines (an AND instead of two shifts), so prefer 718 // it. 719 switch (cast<SetCCSDNode>(Node)->getCondition()) { 720 default: assert(0 && "Unknown integer comparison!"); 721 case ISD::SETEQ: 722 case ISD::SETNE: 723 case ISD::SETUGE: 724 case ISD::SETUGT: 725 case ISD::SETULE: 726 case ISD::SETULT: 727 // ALL of these operations will work if we either sign or zero extend 728 // the operands (including the unsigned comparisons!). Zero extend is 729 // usually a simpler/cheaper operation, so prefer it. 730 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp1, VT); 731 Tmp2 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp2, VT); 732 break; 733 case ISD::SETGE: 734 case ISD::SETGT: 735 case ISD::SETLT: 736 case ISD::SETLE: 737 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 738 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT); 739 break; 740 } 741 742 } 743 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 744 Node->getValueType(0), Tmp1, Tmp2); 745 break; 746 case Expand: 747 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 748 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 749 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 750 switch (cast<SetCCSDNode>(Node)->getCondition()) { 751 case ISD::SETEQ: 752 case ISD::SETNE: 753 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 754 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 755 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 756 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 757 Node->getValueType(0), Tmp1, 758 DAG.getConstant(0, Tmp1.getValueType())); 759 break; 760 default: 761 // FIXME: This generated code sucks. 762 ISD::CondCode LowCC; 763 switch (cast<SetCCSDNode>(Node)->getCondition()) { 764 default: assert(0 && "Unknown integer setcc!"); 765 case ISD::SETLT: 766 case ISD::SETULT: LowCC = ISD::SETULT; break; 767 case ISD::SETGT: 768 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 769 case ISD::SETLE: 770 case ISD::SETULE: LowCC = ISD::SETULE; break; 771 case ISD::SETGE: 772 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 773 } 774 775 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 776 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 777 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 778 779 // NOTE: on targets without efficient SELECT of bools, we can always use 780 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 781 Tmp1 = DAG.getSetCC(LowCC, Node->getValueType(0), LHSLo, RHSLo); 782 Tmp2 = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 783 Node->getValueType(0), LHSHi, RHSHi); 784 Result = DAG.getSetCC(ISD::SETEQ, Node->getValueType(0), LHSHi, RHSHi); 785 Result = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 786 Result, Tmp1, Tmp2); 787 break; 788 } 789 } 790 break; 791 792 case ISD::MEMSET: 793 case ISD::MEMCPY: 794 case ISD::MEMMOVE: { 795 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 796 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 797 798 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 799 switch (getTypeAction(Node->getOperand(2).getValueType())) { 800 case Expand: assert(0 && "Cannot expand a byte!"); 801 case Legal: 802 Tmp3 = LegalizeOp(Node->getOperand(2)); 803 break; 804 case Promote: 805 Tmp3 = PromoteOp(Node->getOperand(2)); 806 break; 807 } 808 } else { 809 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 810 } 811 812 SDOperand Tmp4; 813 switch (getTypeAction(Node->getOperand(3).getValueType())) { 814 case Expand: assert(0 && "Cannot expand this yet!"); 815 case Legal: 816 Tmp4 = LegalizeOp(Node->getOperand(3)); 817 break; 818 case Promote: 819 Tmp4 = PromoteOp(Node->getOperand(3)); 820 break; 821 } 822 823 SDOperand Tmp5; 824 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 825 case Expand: assert(0 && "Cannot expand this yet!"); 826 case Legal: 827 Tmp5 = LegalizeOp(Node->getOperand(4)); 828 break; 829 case Promote: 830 Tmp5 = PromoteOp(Node->getOperand(4)); 831 break; 832 } 833 834 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 835 default: assert(0 && "This action not implemented for this operation!"); 836 case TargetLowering::Legal: 837 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 838 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 839 Tmp5 != Node->getOperand(4)) { 840 std::vector<SDOperand> Ops; 841 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 842 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 843 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 844 } 845 break; 846 case TargetLowering::Expand: { 847 // Otherwise, the target does not support this operation. Lower the 848 // operation to an explicit libcall as appropriate. 849 MVT::ValueType IntPtr = TLI.getPointerTy(); 850 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 851 std::vector<std::pair<SDOperand, const Type*> > Args; 852 853 const char *FnName = 0; 854 if (Node->getOpcode() == ISD::MEMSET) { 855 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 856 // Extend the ubyte argument to be an int value for the call. 857 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 858 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 859 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 860 861 FnName = "memset"; 862 } else if (Node->getOpcode() == ISD::MEMCPY || 863 Node->getOpcode() == ISD::MEMMOVE) { 864 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 865 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 866 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 867 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 868 } else { 869 assert(0 && "Unknown op!"); 870 } 871 std::pair<SDOperand,SDOperand> CallResult = 872 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, 873 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 874 Result = LegalizeOp(CallResult.second); 875 break; 876 } 877 case TargetLowering::Custom: 878 std::vector<SDOperand> Ops; 879 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 880 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 881 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 882 Result = TLI.LowerOperation(Result); 883 Result = LegalizeOp(Result); 884 break; 885 } 886 break; 887 } 888 case ISD::ADD_PARTS: 889 case ISD::SUB_PARTS: 890 case ISD::SHL_PARTS: 891 case ISD::SRA_PARTS: 892 case ISD::SRL_PARTS: { 893 std::vector<SDOperand> Ops; 894 bool Changed = false; 895 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 896 Ops.push_back(LegalizeOp(Node->getOperand(i))); 897 Changed |= Ops.back() != Node->getOperand(i); 898 } 899 if (Changed) 900 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 901 902 // Since these produce multiple values, make sure to remember that we 903 // legalized all of them. 904 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 905 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 906 return Result.getValue(Op.ResNo); 907 } 908 909 // Binary operators 910 case ISD::ADD: 911 case ISD::SUB: 912 case ISD::MUL: 913 case ISD::UDIV: 914 case ISD::SDIV: 915 case ISD::AND: 916 case ISD::OR: 917 case ISD::XOR: 918 case ISD::SHL: 919 case ISD::SRL: 920 case ISD::SRA: 921 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 922 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 923 if (Tmp1 != Node->getOperand(0) || 924 Tmp2 != Node->getOperand(1)) 925 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 926 break; 927 928 case ISD::UREM: 929 case ISD::SREM: 930 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 931 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 932 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 933 case TargetLowering::Legal: 934 if (Tmp1 != Node->getOperand(0) || 935 Tmp2 != Node->getOperand(1)) 936 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 937 Tmp2); 938 break; 939 case TargetLowering::Promote: 940 case TargetLowering::Custom: 941 assert(0 && "Cannot promote/custom handle this yet!"); 942 case TargetLowering::Expand: { 943 MVT::ValueType VT = Node->getValueType(0); 944 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 945 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 946 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 947 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 948 } 949 break; 950 } 951 break; 952 953 // Unary operators 954 case ISD::FABS: 955 case ISD::FNEG: 956 Tmp1 = LegalizeOp(Node->getOperand(0)); 957 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 958 case TargetLowering::Legal: 959 if (Tmp1 != Node->getOperand(0)) 960 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 961 break; 962 case TargetLowering::Promote: 963 case TargetLowering::Custom: 964 assert(0 && "Cannot promote/custom handle this yet!"); 965 case TargetLowering::Expand: 966 if (Node->getOpcode() == ISD::FNEG) { 967 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 968 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 969 Result = LegalizeOp(DAG.getNode(ISD::SUB, Node->getValueType(0), 970 Tmp2, Tmp1)); 971 } else if (Node->getOpcode() == ISD::FABS) { 972 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 973 MVT::ValueType VT = Node->getValueType(0); 974 Tmp2 = DAG.getConstantFP(0.0, VT); 975 Tmp2 = DAG.getSetCC(ISD::SETUGT, TLI.getSetCCResultTy(), Tmp1, Tmp2); 976 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 977 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 978 Result = LegalizeOp(Result); 979 } else { 980 assert(0 && "Unreachable!"); 981 } 982 break; 983 } 984 break; 985 986 // Conversion operators. The source and destination have different types. 987 case ISD::ZERO_EXTEND: 988 case ISD::SIGN_EXTEND: 989 case ISD::TRUNCATE: 990 case ISD::FP_EXTEND: 991 case ISD::FP_ROUND: 992 case ISD::FP_TO_SINT: 993 case ISD::FP_TO_UINT: 994 case ISD::SINT_TO_FP: 995 case ISD::UINT_TO_FP: 996 switch (getTypeAction(Node->getOperand(0).getValueType())) { 997 case Legal: 998 Tmp1 = LegalizeOp(Node->getOperand(0)); 999 if (Tmp1 != Node->getOperand(0)) 1000 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1001 break; 1002 case Expand: 1003 if (Node->getOpcode() == ISD::SINT_TO_FP || 1004 Node->getOpcode() == ISD::UINT_TO_FP) { 1005 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 1006 Node->getValueType(0), Node->getOperand(0)); 1007 Result = LegalizeOp(Result); 1008 break; 1009 } else if (Node->getOpcode() == ISD::TRUNCATE) { 1010 // In the expand case, we must be dealing with a truncate, because 1011 // otherwise the result would be larger than the source. 1012 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1013 1014 // Since the result is legal, we should just be able to truncate the low 1015 // part of the source. 1016 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 1017 break; 1018 } 1019 assert(0 && "Shouldn't need to expand other operators here!"); 1020 1021 case Promote: 1022 switch (Node->getOpcode()) { 1023 case ISD::ZERO_EXTEND: 1024 Result = PromoteOp(Node->getOperand(0)); 1025 // NOTE: Any extend would work here... 1026 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result); 1027 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Op.getValueType(), 1028 Result, Node->getOperand(0).getValueType()); 1029 break; 1030 case ISD::SIGN_EXTEND: 1031 Result = PromoteOp(Node->getOperand(0)); 1032 // NOTE: Any extend would work here... 1033 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result); 1034 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1035 Result, Node->getOperand(0).getValueType()); 1036 break; 1037 case ISD::TRUNCATE: 1038 Result = PromoteOp(Node->getOperand(0)); 1039 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 1040 break; 1041 case ISD::FP_EXTEND: 1042 Result = PromoteOp(Node->getOperand(0)); 1043 if (Result.getValueType() != Op.getValueType()) 1044 // Dynamically dead while we have only 2 FP types. 1045 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 1046 break; 1047 case ISD::FP_ROUND: 1048 case ISD::FP_TO_SINT: 1049 case ISD::FP_TO_UINT: 1050 Result = PromoteOp(Node->getOperand(0)); 1051 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 1052 break; 1053 case ISD::SINT_TO_FP: 1054 Result = PromoteOp(Node->getOperand(0)); 1055 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1056 Result, Node->getOperand(0).getValueType()); 1057 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 1058 break; 1059 case ISD::UINT_TO_FP: 1060 Result = PromoteOp(Node->getOperand(0)); 1061 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Result.getValueType(), 1062 Result, Node->getOperand(0).getValueType()); 1063 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 1064 break; 1065 } 1066 } 1067 break; 1068 case ISD::FP_ROUND_INREG: 1069 case ISD::SIGN_EXTEND_INREG: 1070 case ISD::ZERO_EXTEND_INREG: { 1071 Tmp1 = LegalizeOp(Node->getOperand(0)); 1072 MVT::ValueType ExtraVT = cast<MVTSDNode>(Node)->getExtraValueType(); 1073 1074 // If this operation is not supported, convert it to a shl/shr or load/store 1075 // pair. 1076 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 1077 default: assert(0 && "This action not supported for this op yet!"); 1078 case TargetLowering::Legal: 1079 if (Tmp1 != Node->getOperand(0)) 1080 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 1081 ExtraVT); 1082 break; 1083 case TargetLowering::Expand: 1084 // If this is an integer extend and shifts are supported, do that. 1085 if (Node->getOpcode() == ISD::ZERO_EXTEND_INREG) { 1086 // NOTE: we could fall back on load/store here too for targets without 1087 // AND. However, it is doubtful that any exist. 1088 // AND out the appropriate bits. 1089 SDOperand Mask = 1090 DAG.getConstant((1ULL << MVT::getSizeInBits(ExtraVT))-1, 1091 Node->getValueType(0)); 1092 Result = DAG.getNode(ISD::AND, Node->getValueType(0), 1093 Node->getOperand(0), Mask); 1094 } else if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 1095 // NOTE: we could fall back on load/store here too for targets without 1096 // SAR. However, it is doubtful that any exist. 1097 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 1098 MVT::getSizeInBits(ExtraVT); 1099 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 1100 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 1101 Node->getOperand(0), ShiftCst); 1102 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 1103 Result, ShiftCst); 1104 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 1105 // The only way we can lower this is to turn it into a STORETRUNC, 1106 // EXTLOAD pair, targetting a temporary location (a stack slot). 1107 1108 // NOTE: there is a choice here between constantly creating new stack 1109 // slots and always reusing the same one. We currently always create 1110 // new ones, as reuse may inhibit scheduling. 1111 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 1112 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 1113 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 1114 MachineFunction &MF = DAG.getMachineFunction(); 1115 int SSFI = 1116 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 1117 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 1118 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 1119 Node->getOperand(0), StackSlot, ExtraVT); 1120 Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0), 1121 Result, StackSlot, ExtraVT); 1122 } else { 1123 assert(0 && "Unknown op"); 1124 } 1125 Result = LegalizeOp(Result); 1126 break; 1127 } 1128 break; 1129 } 1130 } 1131 1132 if (!Op.Val->hasOneUse()) 1133 AddLegalizedOperand(Op, Result); 1134 1135 return Result; 1136} 1137 1138/// PromoteOp - Given an operation that produces a value in an invalid type, 1139/// promote it to compute the value into a larger type. The produced value will 1140/// have the correct bits for the low portion of the register, but no guarantee 1141/// is made about the top bits: it may be zero, sign-extended, or garbage. 1142SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 1143 MVT::ValueType VT = Op.getValueType(); 1144 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1145 assert(getTypeAction(VT) == Promote && 1146 "Caller should expand or legalize operands that are not promotable!"); 1147 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 1148 "Cannot promote to smaller type!"); 1149 1150 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 1151 if (I != PromotedNodes.end()) return I->second; 1152 1153 SDOperand Tmp1, Tmp2, Tmp3; 1154 1155 SDOperand Result; 1156 SDNode *Node = Op.Val; 1157 1158 // Promotion needs an optimization step to clean up after it, and is not 1159 // careful to avoid operations the target does not support. Make sure that 1160 // all generated operations are legalized in the next iteration. 1161 NeedsAnotherIteration = true; 1162 1163 switch (Node->getOpcode()) { 1164 default: 1165 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 1166 assert(0 && "Do not know how to promote this operator!"); 1167 abort(); 1168 case ISD::UNDEF: 1169 Result = DAG.getNode(ISD::UNDEF, NVT); 1170 break; 1171 case ISD::Constant: 1172 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 1173 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 1174 break; 1175 case ISD::ConstantFP: 1176 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 1177 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 1178 break; 1179 case ISD::CopyFromReg: 1180 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), NVT, 1181 Node->getOperand(0)); 1182 // Remember that we legalized the chain. 1183 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1184 break; 1185 1186 case ISD::SETCC: 1187 assert(getTypeAction(TLI.getSetCCResultTy()) == Legal && 1188 "SetCC type is not legal??"); 1189 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 1190 TLI.getSetCCResultTy(), Node->getOperand(0), 1191 Node->getOperand(1)); 1192 Result = LegalizeOp(Result); 1193 break; 1194 1195 case ISD::TRUNCATE: 1196 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1197 case Legal: 1198 Result = LegalizeOp(Node->getOperand(0)); 1199 assert(Result.getValueType() >= NVT && 1200 "This truncation doesn't make sense!"); 1201 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 1202 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 1203 break; 1204 case Promote: 1205 // The truncation is not required, because we don't guarantee anything 1206 // about high bits anyway. 1207 Result = PromoteOp(Node->getOperand(0)); 1208 break; 1209 case Expand: 1210 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1211 // Truncate the low part of the expanded value to the result type 1212 Result = DAG.getNode(ISD::TRUNCATE, VT, Tmp1); 1213 } 1214 break; 1215 case ISD::SIGN_EXTEND: 1216 case ISD::ZERO_EXTEND: 1217 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1218 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 1219 case Legal: 1220 // Input is legal? Just do extend all the way to the larger type. 1221 Result = LegalizeOp(Node->getOperand(0)); 1222 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 1223 break; 1224 case Promote: 1225 // Promote the reg if it's smaller. 1226 Result = PromoteOp(Node->getOperand(0)); 1227 // The high bits are not guaranteed to be anything. Insert an extend. 1228 if (Node->getOpcode() == ISD::SIGN_EXTEND) 1229 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 1230 Node->getOperand(0).getValueType()); 1231 else 1232 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Result, 1233 Node->getOperand(0).getValueType()); 1234 break; 1235 } 1236 break; 1237 1238 case ISD::FP_EXTEND: 1239 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 1240 case ISD::FP_ROUND: 1241 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1242 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 1243 case Promote: assert(0 && "Unreachable with 2 FP types!"); 1244 case Legal: 1245 // Input is legal? Do an FP_ROUND_INREG. 1246 Result = LegalizeOp(Node->getOperand(0)); 1247 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1248 break; 1249 } 1250 break; 1251 1252 case ISD::SINT_TO_FP: 1253 case ISD::UINT_TO_FP: 1254 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1255 case Legal: 1256 Result = LegalizeOp(Node->getOperand(0)); 1257 // No extra round required here. 1258 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 1259 break; 1260 1261 case Promote: 1262 Result = PromoteOp(Node->getOperand(0)); 1263 if (Node->getOpcode() == ISD::SINT_TO_FP) 1264 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1265 Result, Node->getOperand(0).getValueType()); 1266 else 1267 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Result.getValueType(), 1268 Result, Node->getOperand(0).getValueType()); 1269 // No extra round required here. 1270 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 1271 break; 1272 case Expand: 1273 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 1274 Node->getOperand(0)); 1275 Result = LegalizeOp(Result); 1276 1277 // Round if we cannot tolerate excess precision. 1278 if (NoExcessFPPrecision) 1279 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1280 break; 1281 } 1282 break; 1283 1284 case ISD::FP_TO_SINT: 1285 case ISD::FP_TO_UINT: 1286 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1287 case Legal: 1288 Tmp1 = LegalizeOp(Node->getOperand(0)); 1289 break; 1290 case Promote: 1291 // The input result is prerounded, so we don't have to do anything 1292 // special. 1293 Tmp1 = PromoteOp(Node->getOperand(0)); 1294 break; 1295 case Expand: 1296 assert(0 && "not implemented"); 1297 } 1298 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 1299 break; 1300 1301 case ISD::FABS: 1302 case ISD::FNEG: 1303 Tmp1 = PromoteOp(Node->getOperand(0)); 1304 assert(Tmp1.getValueType() == NVT); 1305 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 1306 // NOTE: we do not have to do any extra rounding here for 1307 // NoExcessFPPrecision, because we know the input will have the appropriate 1308 // precision, and these operations don't modify precision at all. 1309 break; 1310 1311 case ISD::AND: 1312 case ISD::OR: 1313 case ISD::XOR: 1314 case ISD::ADD: 1315 case ISD::SUB: 1316 case ISD::MUL: 1317 // The input may have strange things in the top bits of the registers, but 1318 // these operations don't care. They may have wierd bits going out, but 1319 // that too is okay if they are integer operations. 1320 Tmp1 = PromoteOp(Node->getOperand(0)); 1321 Tmp2 = PromoteOp(Node->getOperand(1)); 1322 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 1323 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1324 1325 // However, if this is a floating point operation, they will give excess 1326 // precision that we may not be able to tolerate. If we DO allow excess 1327 // precision, just leave it, otherwise excise it. 1328 // FIXME: Why would we need to round FP ops more than integer ones? 1329 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 1330 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 1331 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1332 break; 1333 1334 case ISD::SDIV: 1335 case ISD::SREM: 1336 // These operators require that their input be sign extended. 1337 Tmp1 = PromoteOp(Node->getOperand(0)); 1338 Tmp2 = PromoteOp(Node->getOperand(1)); 1339 if (MVT::isInteger(NVT)) { 1340 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 1341 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT); 1342 } 1343 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1344 1345 // Perform FP_ROUND: this is probably overly pessimistic. 1346 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 1347 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1348 break; 1349 1350 case ISD::UDIV: 1351 case ISD::UREM: 1352 // These operators require that their input be zero extended. 1353 Tmp1 = PromoteOp(Node->getOperand(0)); 1354 Tmp2 = PromoteOp(Node->getOperand(1)); 1355 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 1356 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp1, VT); 1357 Tmp2 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp2, VT); 1358 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1359 break; 1360 1361 case ISD::SHL: 1362 Tmp1 = PromoteOp(Node->getOperand(0)); 1363 Tmp2 = LegalizeOp(Node->getOperand(1)); 1364 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 1365 break; 1366 case ISD::SRA: 1367 // The input value must be properly sign extended. 1368 Tmp1 = PromoteOp(Node->getOperand(0)); 1369 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 1370 Tmp2 = LegalizeOp(Node->getOperand(1)); 1371 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 1372 break; 1373 case ISD::SRL: 1374 // The input value must be properly zero extended. 1375 Tmp1 = PromoteOp(Node->getOperand(0)); 1376 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp1, VT); 1377 Tmp2 = LegalizeOp(Node->getOperand(1)); 1378 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 1379 break; 1380 case ISD::LOAD: 1381 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1382 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1383 // FIXME: When the DAG combiner exists, change this to use EXTLOAD! 1384 if (MVT::isInteger(NVT)) 1385 Result = DAG.getNode(ISD::ZEXTLOAD, NVT, Tmp1, Tmp2, VT); 1386 else 1387 Result = DAG.getNode(ISD::EXTLOAD, NVT, Tmp1, Tmp2, VT); 1388 1389 // Remember that we legalized the chain. 1390 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1391 break; 1392 case ISD::SELECT: 1393 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1394 case Expand: assert(0 && "It's impossible to expand bools"); 1395 case Legal: 1396 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 1397 break; 1398 case Promote: 1399 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1400 break; 1401 } 1402 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 1403 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 1404 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 1405 break; 1406 case ISD::CALL: { 1407 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1408 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 1409 1410 std::vector<SDOperand> Ops; 1411 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 1412 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1413 1414 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 1415 "Can only promote single result calls"); 1416 std::vector<MVT::ValueType> RetTyVTs; 1417 RetTyVTs.reserve(2); 1418 RetTyVTs.push_back(NVT); 1419 RetTyVTs.push_back(MVT::Other); 1420 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops); 1421 Result = SDOperand(NC, 0); 1422 1423 // Insert the new chain mapping. 1424 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1425 break; 1426 } 1427 } 1428 1429 assert(Result.Val && "Didn't set a result!"); 1430 AddPromotedOperand(Op, Result); 1431 return Result; 1432} 1433 1434/// ExpandAddSub - Find a clever way to expand this add operation into 1435/// subcomponents. 1436void SelectionDAGLegalize:: 1437ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 1438 SDOperand &Lo, SDOperand &Hi) { 1439 // Expand the subcomponents. 1440 SDOperand LHSL, LHSH, RHSL, RHSH; 1441 ExpandOp(LHS, LHSL, LHSH); 1442 ExpandOp(RHS, RHSL, RHSH); 1443 1444 // Convert this add to the appropriate ADDC pair. The low part has no carry 1445 // in. 1446 std::vector<SDOperand> Ops; 1447 Ops.push_back(LHSL); 1448 Ops.push_back(LHSH); 1449 Ops.push_back(RHSL); 1450 Ops.push_back(RHSH); 1451 Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops); 1452 Hi = Lo.getValue(1); 1453} 1454 1455void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 1456 SDOperand Op, SDOperand Amt, 1457 SDOperand &Lo, SDOperand &Hi) { 1458 // Expand the subcomponents. 1459 SDOperand LHSL, LHSH; 1460 ExpandOp(Op, LHSL, LHSH); 1461 1462 std::vector<SDOperand> Ops; 1463 Ops.push_back(LHSL); 1464 Ops.push_back(LHSH); 1465 Ops.push_back(Amt); 1466 Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops); 1467 Hi = Lo.getValue(1); 1468} 1469 1470 1471/// ExpandShift - Try to find a clever way to expand this shift operation out to 1472/// smaller elements. If we can't find a way that is more efficient than a 1473/// libcall on this target, return false. Otherwise, return true with the 1474/// low-parts expanded into Lo and Hi. 1475bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 1476 SDOperand &Lo, SDOperand &Hi) { 1477 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 1478 "This is not a shift!"); 1479 1480 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 1481 SDOperand ShAmt = LegalizeOp(Amt); 1482 MVT::ValueType ShTy = ShAmt.getValueType(); 1483 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 1484 unsigned NVTBits = MVT::getSizeInBits(NVT); 1485 1486 // Handle the case when Amt is an immediate. Other cases are currently broken 1487 // and are disabled. 1488 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 1489 unsigned Cst = CN->getValue(); 1490 // Expand the incoming operand to be shifted, so that we have its parts 1491 SDOperand InL, InH; 1492 ExpandOp(Op, InL, InH); 1493 switch(Opc) { 1494 case ISD::SHL: 1495 if (Cst > VTBits) { 1496 Lo = DAG.getConstant(0, NVT); 1497 Hi = DAG.getConstant(0, NVT); 1498 } else if (Cst > NVTBits) { 1499 Lo = DAG.getConstant(0, NVT); 1500 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 1501 } else { 1502 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 1503 Hi = DAG.getNode(ISD::OR, NVT, 1504 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 1505 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 1506 } 1507 return true; 1508 case ISD::SRL: 1509 if (Cst > VTBits) { 1510 Lo = DAG.getConstant(0, NVT); 1511 Hi = DAG.getConstant(0, NVT); 1512 } else if (Cst > NVTBits) { 1513 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 1514 Hi = DAG.getConstant(0, NVT); 1515 } else { 1516 Lo = DAG.getNode(ISD::OR, NVT, 1517 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 1518 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 1519 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 1520 } 1521 return true; 1522 case ISD::SRA: 1523 if (Cst > VTBits) { 1524 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 1525 DAG.getConstant(NVTBits-1, ShTy)); 1526 } else if (Cst > NVTBits) { 1527 Lo = DAG.getNode(ISD::SRA, NVT, InH, 1528 DAG.getConstant(Cst-NVTBits, ShTy)); 1529 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1530 DAG.getConstant(NVTBits-1, ShTy)); 1531 } else { 1532 Lo = DAG.getNode(ISD::OR, NVT, 1533 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 1534 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 1535 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 1536 } 1537 return true; 1538 } 1539 } 1540 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 1541 // so disable it for now. Currently targets are handling this via SHL_PARTS 1542 // and friends. 1543 return false; 1544 1545 // If we have an efficient select operation (or if the selects will all fold 1546 // away), lower to some complex code, otherwise just emit the libcall. 1547 if (TLI.getOperationAction(ISD::SELECT, NVT) != TargetLowering::Legal && 1548 !isa<ConstantSDNode>(Amt)) 1549 return false; 1550 1551 SDOperand InL, InH; 1552 ExpandOp(Op, InL, InH); 1553 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 1554 DAG.getConstant(NVTBits, ShTy), ShAmt); 1555 1556 // Compare the unmasked shift amount against 32. 1557 SDOperand Cond = DAG.getSetCC(ISD::SETGE, TLI.getSetCCResultTy(), ShAmt, 1558 DAG.getConstant(NVTBits, ShTy)); 1559 1560 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 1561 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 1562 DAG.getConstant(NVTBits-1, ShTy)); 1563 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 1564 DAG.getConstant(NVTBits-1, ShTy)); 1565 } 1566 1567 if (Opc == ISD::SHL) { 1568 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 1569 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 1570 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 1571 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 1572 1573 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 1574 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 1575 } else { 1576 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 1577 DAG.getSetCC(ISD::SETEQ, 1578 TLI.getSetCCResultTy(), NAmt, 1579 DAG.getConstant(32, ShTy)), 1580 DAG.getConstant(0, NVT), 1581 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 1582 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 1583 HiLoPart, 1584 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 1585 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 1586 1587 SDOperand HiPart; 1588 if (Opc == ISD::SRA) 1589 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 1590 DAG.getConstant(NVTBits-1, ShTy)); 1591 else 1592 HiPart = DAG.getConstant(0, NVT); 1593 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 1594 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 1595 } 1596 return true; 1597} 1598 1599/// FindLatestAdjCallStackDown - Scan up the dag to find the latest (highest 1600/// NodeDepth) node that is an AdjCallStackDown operation and occurs later than 1601/// Found. 1602static void FindLatestAdjCallStackDown(SDNode *Node, SDNode *&Found) { 1603 if (Node->getNodeDepth() <= Found->getNodeDepth()) return; 1604 1605 // If we found an ADJCALLSTACKDOWN, we already know this node occurs later 1606 // than the Found node. Just remember this node and return. 1607 if (Node->getOpcode() == ISD::ADJCALLSTACKDOWN) { 1608 Found = Node; 1609 return; 1610 } 1611 1612 // Otherwise, scan the operands of Node to see if any of them is a call. 1613 assert(Node->getNumOperands() != 0 && 1614 "All leaves should have depth equal to the entry node!"); 1615 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 1616 FindLatestAdjCallStackDown(Node->getOperand(i).Val, Found); 1617 1618 // Tail recurse for the last iteration. 1619 FindLatestAdjCallStackDown(Node->getOperand(Node->getNumOperands()-1).Val, 1620 Found); 1621} 1622 1623 1624/// FindEarliestAdjCallStackUp - Scan down the dag to find the earliest (lowest 1625/// NodeDepth) node that is an AdjCallStackUp operation and occurs more recent 1626/// than Found. 1627static void FindEarliestAdjCallStackUp(SDNode *Node, SDNode *&Found) { 1628 if (Found && Node->getNodeDepth() >= Found->getNodeDepth()) return; 1629 1630 // If we found an ADJCALLSTACKUP, we already know this node occurs earlier 1631 // than the Found node. Just remember this node and return. 1632 if (Node->getOpcode() == ISD::ADJCALLSTACKUP) { 1633 Found = Node; 1634 return; 1635 } 1636 1637 // Otherwise, scan the operands of Node to see if any of them is a call. 1638 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 1639 if (UI == E) return; 1640 for (--E; UI != E; ++UI) 1641 FindEarliestAdjCallStackUp(*UI, Found); 1642 1643 // Tail recurse for the last iteration. 1644 FindEarliestAdjCallStackUp(*UI, Found); 1645} 1646 1647/// FindAdjCallStackUp - Given a chained node that is part of a call sequence, 1648/// find the ADJCALLSTACKUP node that terminates the call sequence. 1649static SDNode *FindAdjCallStackUp(SDNode *Node) { 1650 if (Node->getOpcode() == ISD::ADJCALLSTACKUP) 1651 return Node; 1652 if (Node->use_empty()) 1653 return 0; // No adjcallstackup 1654 1655 if (Node->hasOneUse()) // Simple case, only has one user to check. 1656 return FindAdjCallStackUp(*Node->use_begin()); 1657 1658 SDOperand TheChain(Node, Node->getNumValues()-1); 1659 assert(TheChain.getValueType() == MVT::Other && "Is not a token chain!"); 1660 1661 for (SDNode::use_iterator UI = Node->use_begin(), 1662 E = Node->use_end(); ; ++UI) { 1663 assert(UI != E && "Didn't find a user of the tokchain, no ADJCALLSTACKUP!"); 1664 1665 // Make sure to only follow users of our token chain. 1666 SDNode *User = *UI; 1667 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 1668 if (User->getOperand(i) == TheChain) 1669 return FindAdjCallStackUp(User); 1670 } 1671 assert(0 && "Unreachable"); 1672 abort(); 1673} 1674 1675/// FindInputOutputChains - If we are replacing an operation with a call we need 1676/// to find the call that occurs before and the call that occurs after it to 1677/// properly serialize the calls in the block. 1678static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 1679 SDOperand Entry) { 1680 SDNode *LatestAdjCallStackDown = Entry.Val; 1681 FindLatestAdjCallStackDown(OpNode, LatestAdjCallStackDown); 1682 //std::cerr << "Found node: "; LatestAdjCallStackDown->dump(); std::cerr <<"\n"; 1683 1684 SDNode *LatestAdjCallStackUp = FindAdjCallStackUp(LatestAdjCallStackDown); 1685 1686 1687 SDNode *EarliestAdjCallStackUp = 0; 1688 FindEarliestAdjCallStackUp(OpNode, EarliestAdjCallStackUp); 1689 1690 if (EarliestAdjCallStackUp) { 1691 //std::cerr << "Found node: "; 1692 //EarliestAdjCallStackUp->dump(); std::cerr <<"\n"; 1693 } 1694 1695 return SDOperand(LatestAdjCallStackUp, 0); 1696} 1697 1698 1699 1700// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1701// does not fit into a register, return the lo part and set the hi part to the 1702// by-reg argument. If it does fit into a single register, return the result 1703// and leave the Hi part unset. 1704SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 1705 SDOperand &Hi) { 1706 SDNode *OutChain; 1707 SDOperand InChain = FindInputOutputChains(Node, OutChain, 1708 DAG.getEntryNode()); 1709 if (InChain.Val == 0) 1710 InChain = DAG.getEntryNode(); 1711 1712 TargetLowering::ArgListTy Args; 1713 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1714 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 1715 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 1716 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 1717 } 1718 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 1719 1720 // We don't care about token chains for libcalls. We just use the entry 1721 // node as our input and ignore the output chain. This allows us to place 1722 // calls wherever we need them to satisfy data dependences. 1723 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 1724 SDOperand Result = TLI.LowerCallTo(InChain, RetTy, false, Callee, 1725 Args, DAG).first; 1726 switch (getTypeAction(Result.getValueType())) { 1727 default: assert(0 && "Unknown thing"); 1728 case Legal: 1729 return Result; 1730 case Promote: 1731 assert(0 && "Cannot promote this yet!"); 1732 case Expand: 1733 SDOperand Lo; 1734 ExpandOp(Result, Lo, Hi); 1735 return Lo; 1736 } 1737} 1738 1739 1740/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 1741/// destination type is legal. 1742SDOperand SelectionDAGLegalize:: 1743ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 1744 assert(getTypeAction(DestTy) == Legal && "Destination type is not legal!"); 1745 assert(getTypeAction(Source.getValueType()) == Expand && 1746 "This is not an expansion!"); 1747 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 1748 1749 SDNode *OutChain; 1750 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 1751 DAG.getEntryNode()); 1752 1753 const char *FnName = 0; 1754 if (isSigned) { 1755 if (DestTy == MVT::f32) 1756 FnName = "__floatdisf"; 1757 else { 1758 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 1759 FnName = "__floatdidf"; 1760 } 1761 } else { 1762 // If this is unsigned, and not supported, first perform the conversion to 1763 // signed, then adjust the result if the sign bit is set. 1764 SDOperand SignedConv = ExpandIntToFP(false, DestTy, Source); 1765 1766 assert(0 && "Unsigned casts not supported yet!"); 1767 } 1768 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 1769 1770 TargetLowering::ArgListTy Args; 1771 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 1772 Args.push_back(std::make_pair(Source, ArgTy)); 1773 1774 // We don't care about token chains for libcalls. We just use the entry 1775 // node as our input and ignore the output chain. This allows us to place 1776 // calls wherever we need them to satisfy data dependences. 1777 const Type *RetTy = MVT::getTypeForValueType(DestTy); 1778 return TLI.LowerCallTo(InChain, RetTy, false, Callee, Args, DAG).first; 1779 1780} 1781 1782 1783 1784/// ExpandOp - Expand the specified SDOperand into its two component pieces 1785/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 1786/// LegalizeNodes map is filled in for any results that are not expanded, the 1787/// ExpandedNodes map is filled in for any results that are expanded, and the 1788/// Lo/Hi values are returned. 1789void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 1790 MVT::ValueType VT = Op.getValueType(); 1791 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1792 SDNode *Node = Op.Val; 1793 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 1794 assert(MVT::isInteger(VT) && "Cannot expand FP values!"); 1795 assert(MVT::isInteger(NVT) && NVT < VT && 1796 "Cannot expand to FP value or to larger int value!"); 1797 1798 // If there is more than one use of this, see if we already expanded it. 1799 // There is no use remembering values that only have a single use, as the map 1800 // entries will never be reused. 1801 if (!Node->hasOneUse()) { 1802 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 1803 = ExpandedNodes.find(Op); 1804 if (I != ExpandedNodes.end()) { 1805 Lo = I->second.first; 1806 Hi = I->second.second; 1807 return; 1808 } 1809 } 1810 1811 // Expanding to multiple registers needs to perform an optimization step, and 1812 // is not careful to avoid operations the target does not support. Make sure 1813 // that all generated operations are legalized in the next iteration. 1814 NeedsAnotherIteration = true; 1815 1816 switch (Node->getOpcode()) { 1817 default: 1818 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 1819 assert(0 && "Do not know how to expand this operator!"); 1820 abort(); 1821 case ISD::UNDEF: 1822 Lo = DAG.getNode(ISD::UNDEF, NVT); 1823 Hi = DAG.getNode(ISD::UNDEF, NVT); 1824 break; 1825 case ISD::Constant: { 1826 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 1827 Lo = DAG.getConstant(Cst, NVT); 1828 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 1829 break; 1830 } 1831 1832 case ISD::CopyFromReg: { 1833 unsigned Reg = cast<RegSDNode>(Node)->getReg(); 1834 // Aggregate register values are always in consequtive pairs. 1835 Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0)); 1836 Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1)); 1837 1838 // Remember that we legalized the chain. 1839 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 1840 1841 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 1842 break; 1843 } 1844 1845 case ISD::BUILD_PAIR: 1846 // Legalize both operands. FIXME: in the future we should handle the case 1847 // where the two elements are not legal. 1848 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 1849 Lo = LegalizeOp(Node->getOperand(0)); 1850 Hi = LegalizeOp(Node->getOperand(1)); 1851 break; 1852 1853 case ISD::LOAD: { 1854 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1855 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1856 Lo = DAG.getLoad(NVT, Ch, Ptr); 1857 1858 // Increment the pointer to the other half. 1859 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 1860 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1861 getIntPtrConstant(IncrementSize)); 1862 Hi = DAG.getLoad(NVT, Ch, Ptr); 1863 1864 // Build a factor node to remember that this load is independent of the 1865 // other one. 1866 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1867 Hi.getValue(1)); 1868 1869 // Remember that we legalized the chain. 1870 AddLegalizedOperand(Op.getValue(1), TF); 1871 if (!TLI.isLittleEndian()) 1872 std::swap(Lo, Hi); 1873 break; 1874 } 1875 case ISD::CALL: { 1876 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1877 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 1878 1879 bool Changed = false; 1880 std::vector<SDOperand> Ops; 1881 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 1882 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1883 Changed |= Ops.back() != Node->getOperand(i); 1884 } 1885 1886 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 1887 "Can only expand a call once so far, not i64 -> i16!"); 1888 1889 std::vector<MVT::ValueType> RetTyVTs; 1890 RetTyVTs.reserve(3); 1891 RetTyVTs.push_back(NVT); 1892 RetTyVTs.push_back(NVT); 1893 RetTyVTs.push_back(MVT::Other); 1894 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops); 1895 Lo = SDOperand(NC, 0); 1896 Hi = SDOperand(NC, 1); 1897 1898 // Insert the new chain mapping. 1899 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 1900 break; 1901 } 1902 case ISD::AND: 1903 case ISD::OR: 1904 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 1905 SDOperand LL, LH, RL, RH; 1906 ExpandOp(Node->getOperand(0), LL, LH); 1907 ExpandOp(Node->getOperand(1), RL, RH); 1908 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 1909 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 1910 break; 1911 } 1912 case ISD::SELECT: { 1913 SDOperand C, LL, LH, RL, RH; 1914 1915 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1916 case Expand: assert(0 && "It's impossible to expand bools"); 1917 case Legal: 1918 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1919 break; 1920 case Promote: 1921 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 1922 break; 1923 } 1924 ExpandOp(Node->getOperand(1), LL, LH); 1925 ExpandOp(Node->getOperand(2), RL, RH); 1926 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 1927 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 1928 break; 1929 } 1930 case ISD::SIGN_EXTEND: { 1931 SDOperand In; 1932 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1933 case Expand: assert(0 && "expand-expand not implemented yet!"); 1934 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 1935 case Promote: 1936 In = PromoteOp(Node->getOperand(0)); 1937 // Emit the appropriate sign_extend_inreg to get the value we want. 1938 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 1939 Node->getOperand(0).getValueType()); 1940 break; 1941 } 1942 1943 // The low part is just a sign extension of the input (which degenerates to 1944 // a copy). 1945 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 1946 1947 // The high part is obtained by SRA'ing all but one of the bits of the lo 1948 // part. 1949 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 1950 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 1951 TLI.getShiftAmountTy())); 1952 break; 1953 } 1954 case ISD::ZERO_EXTEND: { 1955 SDOperand In; 1956 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1957 case Expand: assert(0 && "expand-expand not implemented yet!"); 1958 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 1959 case Promote: 1960 In = PromoteOp(Node->getOperand(0)); 1961 // Emit the appropriate zero_extend_inreg to get the value we want. 1962 In = DAG.getNode(ISD::ZERO_EXTEND_INREG, In.getValueType(), In, 1963 Node->getOperand(0).getValueType()); 1964 break; 1965 } 1966 1967 // The low part is just a zero extension of the input (which degenerates to 1968 // a copy). 1969 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 1970 1971 // The high part is just a zero. 1972 Hi = DAG.getConstant(0, NVT); 1973 break; 1974 } 1975 // These operators cannot be expanded directly, emit them as calls to 1976 // library functions. 1977 case ISD::FP_TO_SINT: 1978 if (Node->getOperand(0).getValueType() == MVT::f32) 1979 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 1980 else 1981 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 1982 break; 1983 case ISD::FP_TO_UINT: 1984 if (Node->getOperand(0).getValueType() == MVT::f32) 1985 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 1986 else 1987 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 1988 break; 1989 1990 case ISD::SHL: 1991 // If we can emit an efficient shift operation, do so now. 1992 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 1993 break; 1994 1995 // If this target supports SHL_PARTS, use it. 1996 if (TLI.getOperationAction(ISD::SHL_PARTS, NVT) == TargetLowering::Legal) { 1997 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 1998 Lo, Hi); 1999 break; 2000 } 2001 2002 // Otherwise, emit a libcall. 2003 Lo = ExpandLibCall("__ashldi3", Node, Hi); 2004 break; 2005 2006 case ISD::SRA: 2007 // If we can emit an efficient shift operation, do so now. 2008 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 2009 break; 2010 2011 // If this target supports SRA_PARTS, use it. 2012 if (TLI.getOperationAction(ISD::SRA_PARTS, NVT) == TargetLowering::Legal) { 2013 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 2014 Lo, Hi); 2015 break; 2016 } 2017 2018 // Otherwise, emit a libcall. 2019 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 2020 break; 2021 case ISD::SRL: 2022 // If we can emit an efficient shift operation, do so now. 2023 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 2024 break; 2025 2026 // If this target supports SRL_PARTS, use it. 2027 if (TLI.getOperationAction(ISD::SRL_PARTS, NVT) == TargetLowering::Legal) { 2028 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 2029 Lo, Hi); 2030 break; 2031 } 2032 2033 // Otherwise, emit a libcall. 2034 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 2035 break; 2036 2037 case ISD::ADD: 2038 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 2039 Lo, Hi); 2040 break; 2041 case ISD::SUB: 2042 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 2043 Lo, Hi); 2044 break; 2045 case ISD::MUL: Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 2046 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 2047 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 2048 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 2049 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 2050 } 2051 2052 // Remember in a map if the values will be reused later. 2053 if (!Node->hasOneUse()) { 2054 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 2055 std::make_pair(Lo, Hi))).second; 2056 assert(isNew && "Value already expanded?!?"); 2057 } 2058} 2059 2060 2061// SelectionDAG::Legalize - This is the entry point for the file. 2062// 2063void SelectionDAG::Legalize() { 2064 /// run - This is the main entry point to this class. 2065 /// 2066 SelectionDAGLegalize(*this).Run(); 2067} 2068 2069