LegalizeDAG.cpp revision 09386bd850e89f0cabae20944ad76bd806d4741d
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/Target/TargetFrameInfo.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetMachine.h" 22#include "llvm/Target/TargetOptions.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/DerivedTypes.h" 26#include "llvm/Support/MathExtras.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Compiler.h" 29#include "llvm/ADT/DenseMap.h" 30#include "llvm/ADT/SmallVector.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include <map> 33using namespace llvm; 34 35#ifndef NDEBUG 36static cl::opt<bool> 37ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 38 cl::desc("Pop up a window to show dags before legalize")); 39#else 40static const bool ViewLegalizeDAGs = 0; 41#endif 42 43//===----------------------------------------------------------------------===// 44/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 45/// hacks on it until the target machine can handle it. This involves 46/// eliminating value sizes the machine cannot handle (promoting small sizes to 47/// large sizes or splitting up large values into small values) as well as 48/// eliminating operations the machine cannot handle. 49/// 50/// This code also does a small amount of optimization and recognition of idioms 51/// as part of its processing. For example, if a target does not support a 52/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 53/// will attempt merge setcc and brc instructions into brcc's. 54/// 55namespace { 56class VISIBILITY_HIDDEN SelectionDAGLegalize { 57 TargetLowering &TLI; 58 SelectionDAG &DAG; 59 60 // Libcall insertion helpers. 61 62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 63 /// legalized. We use this to ensure that calls are properly serialized 64 /// against each other, including inserted libcalls. 65 SDOperand LastCALLSEQ_END; 66 67 /// IsLegalizingCall - This member is used *only* for purposes of providing 68 /// helpful assertions that a libcall isn't created while another call is 69 /// being legalized (which could lead to non-serialized call sequences). 70 bool IsLegalizingCall; 71 72 enum LegalizeAction { 73 Legal, // The target natively supports this operation. 74 Promote, // This operation should be executed in a larger type. 75 Expand // Try to expand this to other ops, otherwise use a libcall. 76 }; 77 78 /// ValueTypeActions - This is a bitvector that contains two bits for each 79 /// value type, where the two bits correspond to the LegalizeAction enum. 80 /// This can be queried with "getTypeAction(VT)". 81 TargetLowering::ValueTypeActionImpl ValueTypeActions; 82 83 /// LegalizedNodes - For nodes that are of legal width, and that have more 84 /// than one use, this map indicates what regularized operand to use. This 85 /// allows us to avoid legalizing the same thing more than once. 86 DenseMap<SDOperand, SDOperand> LegalizedNodes; 87 88 /// PromotedNodes - For nodes that are below legal width, and that have more 89 /// than one use, this map indicates what promoted value to use. This allows 90 /// us to avoid promoting the same thing more than once. 91 DenseMap<SDOperand, SDOperand> PromotedNodes; 92 93 /// ExpandedNodes - For nodes that need to be expanded this map indicates 94 /// which which operands are the expanded version of the input. This allows 95 /// us to avoid expanding the same node more than once. 96 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 97 98 /// SplitNodes - For vector nodes that need to be split, this map indicates 99 /// which which operands are the split version of the input. This allows us 100 /// to avoid splitting the same node more than once. 101 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 102 103 /// ScalarizedNodes - For nodes that need to be converted from vector types to 104 /// scalar types, this contains the mapping of ones we have already 105 /// processed to the result. 106 std::map<SDOperand, SDOperand> ScalarizedNodes; 107 108 void AddLegalizedOperand(SDOperand From, SDOperand To) { 109 LegalizedNodes.insert(std::make_pair(From, To)); 110 // If someone requests legalization of the new node, return itself. 111 if (From != To) 112 LegalizedNodes.insert(std::make_pair(To, To)); 113 } 114 void AddPromotedOperand(SDOperand From, SDOperand To) { 115 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 116 assert(isNew && "Got into the map somehow?"); 117 // If someone requests legalization of the new node, return itself. 118 LegalizedNodes.insert(std::make_pair(To, To)); 119 } 120 121public: 122 123 SelectionDAGLegalize(SelectionDAG &DAG); 124 125 /// getTypeAction - Return how we should legalize values of this type, either 126 /// it is already legal or we need to expand it into multiple registers of 127 /// smaller integer type, or we need to promote it to a larger type. 128 LegalizeAction getTypeAction(MVT::ValueType VT) const { 129 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 130 } 131 132 /// isTypeLegal - Return true if this type is legal on this target. 133 /// 134 bool isTypeLegal(MVT::ValueType VT) const { 135 return getTypeAction(VT) == Legal; 136 } 137 138 void LegalizeDAG(); 139 140private: 141 /// HandleOp - Legalize, Promote, or Expand the specified operand as 142 /// appropriate for its type. 143 void HandleOp(SDOperand Op); 144 145 /// LegalizeOp - We know that the specified value has a legal type. 146 /// Recursively ensure that the operands have legal types, then return the 147 /// result. 148 SDOperand LegalizeOp(SDOperand O); 149 150 /// PromoteOp - Given an operation that produces a value in an invalid type, 151 /// promote it to compute the value into a larger type. The produced value 152 /// will have the correct bits for the low portion of the register, but no 153 /// guarantee is made about the top bits: it may be zero, sign-extended, or 154 /// garbage. 155 SDOperand PromoteOp(SDOperand O); 156 157 /// ExpandOp - Expand the specified SDOperand into its two component pieces 158 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 159 /// the LegalizeNodes map is filled in for any results that are not expanded, 160 /// the ExpandedNodes map is filled in for any results that are expanded, and 161 /// the Lo/Hi values are returned. This applies to integer types and Vector 162 /// types. 163 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 164 165 /// SplitVectorOp - Given an operand of vector type, break it down into 166 /// two smaller values. 167 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 168 169 /// ScalarizeVectorOp - Given an operand of single-element vector type 170 /// (e.g. v1f32), convert it into the equivalent operation that returns a 171 /// scalar (e.g. f32) value. 172 SDOperand ScalarizeVectorOp(SDOperand O); 173 174 /// isShuffleLegal - Return true if a vector shuffle is legal with the 175 /// specified mask and type. Targets can specify exactly which masks they 176 /// support and the code generator is tasked with not creating illegal masks. 177 /// 178 /// Note that this will also return true for shuffles that are promoted to a 179 /// different type. 180 /// 181 /// If this is a legal shuffle, this method returns the (possibly promoted) 182 /// build_vector Mask. If it's not a legal shuffle, it returns null. 183 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 184 185 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 186 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 187 188 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 189 190 SDOperand CreateStackTemporary(MVT::ValueType VT); 191 192 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 193 SDOperand &Hi); 194 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 195 SDOperand Source); 196 197 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 198 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 199 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 200 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 201 SDOperand LegalOp, 202 MVT::ValueType DestVT); 203 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 204 bool isSigned); 205 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 206 bool isSigned); 207 208 SDOperand ExpandBSWAP(SDOperand Op); 209 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 210 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 211 SDOperand &Lo, SDOperand &Hi); 212 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 213 SDOperand &Lo, SDOperand &Hi); 214 215 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 216 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 217 218 SDOperand getIntPtrConstant(uint64_t Val) { 219 return DAG.getConstant(Val, TLI.getPointerTy()); 220 } 221}; 222} 223 224/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 225/// specified mask and type. Targets can specify exactly which masks they 226/// support and the code generator is tasked with not creating illegal masks. 227/// 228/// Note that this will also return true for shuffles that are promoted to a 229/// different type. 230SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 231 SDOperand Mask) const { 232 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 233 default: return 0; 234 case TargetLowering::Legal: 235 case TargetLowering::Custom: 236 break; 237 case TargetLowering::Promote: { 238 // If this is promoted to a different type, convert the shuffle mask and 239 // ask if it is legal in the promoted type! 240 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 241 242 // If we changed # elements, change the shuffle mask. 243 unsigned NumEltsGrowth = 244 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 245 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 246 if (NumEltsGrowth > 1) { 247 // Renumber the elements. 248 SmallVector<SDOperand, 8> Ops; 249 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 250 SDOperand InOp = Mask.getOperand(i); 251 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 252 if (InOp.getOpcode() == ISD::UNDEF) 253 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 254 else { 255 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 256 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 257 } 258 } 259 } 260 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 261 } 262 VT = NVT; 263 break; 264 } 265 } 266 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 267} 268 269SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 270 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 271 ValueTypeActions(TLI.getValueTypeActions()) { 272 assert(MVT::LAST_VALUETYPE <= 32 && 273 "Too many value types for ValueTypeActions to hold!"); 274} 275 276/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 277/// contains all of a nodes operands before it contains the node. 278static void ComputeTopDownOrdering(SelectionDAG &DAG, 279 SmallVector<SDNode*, 64> &Order) { 280 281 DenseMap<SDNode*, unsigned> Visited; 282 std::vector<SDNode*> Worklist; 283 Worklist.reserve(128); 284 285 // Compute ordering from all of the leaves in the graphs, those (like the 286 // entry node) that have no operands. 287 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 288 E = DAG.allnodes_end(); I != E; ++I) { 289 if (I->getNumOperands() == 0) { 290 Visited[I] = 0 - 1U; 291 Worklist.push_back(I); 292 } 293 } 294 295 while (!Worklist.empty()) { 296 SDNode *N = Worklist.back(); 297 Worklist.pop_back(); 298 299 if (++Visited[N] != N->getNumOperands()) 300 continue; // Haven't visited all operands yet 301 302 Order.push_back(N); 303 304 // Now that we have N in, add anything that uses it if all of their operands 305 // are now done. 306 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 307 UI != E; ++UI) 308 Worklist.push_back(*UI); 309 } 310 311 assert(Order.size() == Visited.size() && 312 Order.size() == 313 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 314 "Error: DAG is cyclic!"); 315} 316 317 318void SelectionDAGLegalize::LegalizeDAG() { 319 LastCALLSEQ_END = DAG.getEntryNode(); 320 IsLegalizingCall = false; 321 322 // The legalize process is inherently a bottom-up recursive process (users 323 // legalize their uses before themselves). Given infinite stack space, we 324 // could just start legalizing on the root and traverse the whole graph. In 325 // practice however, this causes us to run out of stack space on large basic 326 // blocks. To avoid this problem, compute an ordering of the nodes where each 327 // node is only legalized after all of its operands are legalized. 328 SmallVector<SDNode*, 64> Order; 329 ComputeTopDownOrdering(DAG, Order); 330 331 for (unsigned i = 0, e = Order.size(); i != e; ++i) 332 HandleOp(SDOperand(Order[i], 0)); 333 334 // Finally, it's possible the root changed. Get the new root. 335 SDOperand OldRoot = DAG.getRoot(); 336 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 337 DAG.setRoot(LegalizedNodes[OldRoot]); 338 339 ExpandedNodes.clear(); 340 LegalizedNodes.clear(); 341 PromotedNodes.clear(); 342 SplitNodes.clear(); 343 ScalarizedNodes.clear(); 344 345 // Remove dead nodes now. 346 DAG.RemoveDeadNodes(); 347} 348 349 350/// FindCallEndFromCallStart - Given a chained node that is part of a call 351/// sequence, find the CALLSEQ_END node that terminates the call sequence. 352static SDNode *FindCallEndFromCallStart(SDNode *Node) { 353 if (Node->getOpcode() == ISD::CALLSEQ_END) 354 return Node; 355 if (Node->use_empty()) 356 return 0; // No CallSeqEnd 357 358 // The chain is usually at the end. 359 SDOperand TheChain(Node, Node->getNumValues()-1); 360 if (TheChain.getValueType() != MVT::Other) { 361 // Sometimes it's at the beginning. 362 TheChain = SDOperand(Node, 0); 363 if (TheChain.getValueType() != MVT::Other) { 364 // Otherwise, hunt for it. 365 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 366 if (Node->getValueType(i) == MVT::Other) { 367 TheChain = SDOperand(Node, i); 368 break; 369 } 370 371 // Otherwise, we walked into a node without a chain. 372 if (TheChain.getValueType() != MVT::Other) 373 return 0; 374 } 375 } 376 377 for (SDNode::use_iterator UI = Node->use_begin(), 378 E = Node->use_end(); UI != E; ++UI) { 379 380 // Make sure to only follow users of our token chain. 381 SDNode *User = *UI; 382 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 383 if (User->getOperand(i) == TheChain) 384 if (SDNode *Result = FindCallEndFromCallStart(User)) 385 return Result; 386 } 387 return 0; 388} 389 390/// FindCallStartFromCallEnd - Given a chained node that is part of a call 391/// sequence, find the CALLSEQ_START node that initiates the call sequence. 392static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 393 assert(Node && "Didn't find callseq_start for a call??"); 394 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 395 396 assert(Node->getOperand(0).getValueType() == MVT::Other && 397 "Node doesn't have a token chain argument!"); 398 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 399} 400 401/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 402/// see if any uses can reach Dest. If no dest operands can get to dest, 403/// legalize them, legalize ourself, and return false, otherwise, return true. 404/// 405/// Keep track of the nodes we fine that actually do lead to Dest in 406/// NodesLeadingTo. This avoids retraversing them exponential number of times. 407/// 408bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 409 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 410 if (N == Dest) return true; // N certainly leads to Dest :) 411 412 // If we've already processed this node and it does lead to Dest, there is no 413 // need to reprocess it. 414 if (NodesLeadingTo.count(N)) return true; 415 416 // If the first result of this node has been already legalized, then it cannot 417 // reach N. 418 switch (getTypeAction(N->getValueType(0))) { 419 case Legal: 420 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 421 break; 422 case Promote: 423 if (PromotedNodes.count(SDOperand(N, 0))) return false; 424 break; 425 case Expand: 426 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 427 break; 428 } 429 430 // Okay, this node has not already been legalized. Check and legalize all 431 // operands. If none lead to Dest, then we can legalize this node. 432 bool OperandsLeadToDest = false; 433 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 434 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 435 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 436 437 if (OperandsLeadToDest) { 438 NodesLeadingTo.insert(N); 439 return true; 440 } 441 442 // Okay, this node looks safe, legalize it and return false. 443 HandleOp(SDOperand(N, 0)); 444 return false; 445} 446 447/// HandleOp - Legalize, Promote, or Expand the specified operand as 448/// appropriate for its type. 449void SelectionDAGLegalize::HandleOp(SDOperand Op) { 450 MVT::ValueType VT = Op.getValueType(); 451 switch (getTypeAction(VT)) { 452 default: assert(0 && "Bad type action!"); 453 case Legal: (void)LegalizeOp(Op); break; 454 case Promote: (void)PromoteOp(Op); break; 455 case Expand: 456 if (!MVT::isVector(VT)) { 457 // If this is an illegal scalar, expand it into its two component 458 // pieces. 459 SDOperand X, Y; 460 if (Op.getOpcode() == ISD::TargetConstant) 461 break; // Allow illegal target nodes. 462 ExpandOp(Op, X, Y); 463 } else if (MVT::getVectorNumElements(VT) == 1) { 464 // If this is an illegal single element vector, convert it to a 465 // scalar operation. 466 (void)ScalarizeVectorOp(Op); 467 } else { 468 // Otherwise, this is an illegal multiple element vector. 469 // Split it in half and legalize both parts. 470 SDOperand X, Y; 471 SplitVectorOp(Op, X, Y); 472 } 473 break; 474 } 475} 476 477/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 478/// a load from the constant pool. 479static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 480 SelectionDAG &DAG, TargetLowering &TLI) { 481 bool Extend = false; 482 483 // If a FP immediate is precise when represented as a float and if the 484 // target can do an extending load from float to double, we put it into 485 // the constant pool as a float, even if it's is statically typed as a 486 // double. 487 MVT::ValueType VT = CFP->getValueType(0); 488 bool isDouble = VT == MVT::f64; 489 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 490 Type::FloatTy, CFP->getValue()); 491 if (!UseCP) { 492 double Val = LLVMC->getValue(); 493 return isDouble 494 ? DAG.getConstant(DoubleToBits(Val), MVT::i64) 495 : DAG.getConstant(FloatToBits(Val), MVT::i32); 496 } 497 498 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 499 // Only do this if the target has a native EXTLOAD instruction from f32. 500 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 501 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); 502 VT = MVT::f32; 503 Extend = true; 504 } 505 506 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 507 if (Extend) { 508 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 509 CPIdx, NULL, 0, MVT::f32); 510 } else { 511 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 512 } 513} 514 515 516/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 517/// operations. 518static 519SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 520 SelectionDAG &DAG, TargetLowering &TLI) { 521 MVT::ValueType VT = Node->getValueType(0); 522 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 523 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 524 "fcopysign expansion only supported for f32 and f64"); 525 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 526 527 // First get the sign bit of second operand. 528 SDOperand Mask1 = (SrcVT == MVT::f64) 529 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 530 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 531 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 532 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 533 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 534 // Shift right or sign-extend it if the two operands have different types. 535 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 536 if (SizeDiff > 0) { 537 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 538 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 539 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 540 } else if (SizeDiff < 0) 541 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 542 543 // Clear the sign bit of first operand. 544 SDOperand Mask2 = (VT == MVT::f64) 545 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 546 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 547 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 548 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 549 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 550 551 // Or the value with the sign bit. 552 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 553 return Result; 554} 555 556/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 557static 558SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 559 TargetLowering &TLI) { 560 assert(MVT::isInteger(ST->getStoredVT()) && 561 "Non integer unaligned stores not implemented."); 562 int SVOffset = ST->getSrcValueOffset(); 563 SDOperand Chain = ST->getChain(); 564 SDOperand Ptr = ST->getBasePtr(); 565 SDOperand Val = ST->getValue(); 566 MVT::ValueType VT = Val.getValueType(); 567 // Get the half-size VT 568 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1; 569 int NumBits = MVT::getSizeInBits(NewStoredVT); 570 int Alignment = ST->getAlignment(); 571 int IncrementSize = NumBits / 8; 572 573 // Divide the stored value in two parts. 574 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 575 SDOperand Lo = Val; 576 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 577 578 // Store the two parts 579 SDOperand Store1, Store2; 580 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 581 ST->getSrcValue(), SVOffset, NewStoredVT, 582 ST->isVolatile(), Alignment); 583 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 584 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 585 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 586 ST->getSrcValue(), SVOffset + IncrementSize, 587 NewStoredVT, ST->isVolatile(), Alignment); 588 589 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 590} 591 592/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 593static 594SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 595 TargetLowering &TLI) { 596 assert(MVT::isInteger(LD->getLoadedVT()) && 597 "Non integer unaligned loads not implemented."); 598 int SVOffset = LD->getSrcValueOffset(); 599 SDOperand Chain = LD->getChain(); 600 SDOperand Ptr = LD->getBasePtr(); 601 MVT::ValueType VT = LD->getValueType(0); 602 MVT::ValueType NewLoadedVT = LD->getLoadedVT() - 1; 603 int NumBits = MVT::getSizeInBits(NewLoadedVT); 604 int Alignment = LD->getAlignment(); 605 int IncrementSize = NumBits / 8; 606 ISD::LoadExtType HiExtType = LD->getExtensionType(); 607 608 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 609 if (HiExtType == ISD::NON_EXTLOAD) 610 HiExtType = ISD::ZEXTLOAD; 611 612 // Load the value in two parts 613 SDOperand Lo, Hi; 614 if (TLI.isLittleEndian()) { 615 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 616 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 617 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 618 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 619 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 620 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 621 Alignment); 622 } else { 623 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 624 NewLoadedVT,LD->isVolatile(), Alignment); 625 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 626 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 627 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 628 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 629 Alignment); 630 } 631 632 // aggregate the two parts 633 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 634 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 635 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 636 637 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 638 Hi.getValue(1)); 639 640 SDOperand Ops[] = { Result, TF }; 641 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 642} 643 644/// LegalizeOp - We know that the specified value has a legal type, and 645/// that its operands are legal. Now ensure that the operation itself 646/// is legal, recursively ensuring that the operands' operations remain 647/// legal. 648SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 649 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 650 return Op; 651 652 assert(isTypeLegal(Op.getValueType()) && 653 "Caller should expand or promote operands that are not legal!"); 654 SDNode *Node = Op.Val; 655 656 // If this operation defines any values that cannot be represented in a 657 // register on this target, make sure to expand or promote them. 658 if (Node->getNumValues() > 1) { 659 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 660 if (getTypeAction(Node->getValueType(i)) != Legal) { 661 HandleOp(Op.getValue(i)); 662 assert(LegalizedNodes.count(Op) && 663 "Handling didn't add legal operands!"); 664 return LegalizedNodes[Op]; 665 } 666 } 667 668 // Note that LegalizeOp may be reentered even from single-use nodes, which 669 // means that we always must cache transformed nodes. 670 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 671 if (I != LegalizedNodes.end()) return I->second; 672 673 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 674 SDOperand Result = Op; 675 bool isCustom = false; 676 677 switch (Node->getOpcode()) { 678 case ISD::FrameIndex: 679 case ISD::EntryToken: 680 case ISD::Register: 681 case ISD::BasicBlock: 682 case ISD::TargetFrameIndex: 683 case ISD::TargetJumpTable: 684 case ISD::TargetConstant: 685 case ISD::TargetConstantFP: 686 case ISD::TargetConstantPool: 687 case ISD::TargetGlobalAddress: 688 case ISD::TargetGlobalTLSAddress: 689 case ISD::TargetExternalSymbol: 690 case ISD::VALUETYPE: 691 case ISD::SRCVALUE: 692 case ISD::STRING: 693 case ISD::CONDCODE: 694 // Primitives must all be legal. 695 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 696 "This must be legal!"); 697 break; 698 default: 699 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 700 // If this is a target node, legalize it by legalizing the operands then 701 // passing it through. 702 SmallVector<SDOperand, 8> Ops; 703 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 704 Ops.push_back(LegalizeOp(Node->getOperand(i))); 705 706 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 707 708 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 709 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 710 return Result.getValue(Op.ResNo); 711 } 712 // Otherwise this is an unhandled builtin node. splat. 713#ifndef NDEBUG 714 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 715#endif 716 assert(0 && "Do not know how to legalize this operator!"); 717 abort(); 718 case ISD::GLOBAL_OFFSET_TABLE: 719 case ISD::GlobalAddress: 720 case ISD::GlobalTLSAddress: 721 case ISD::ExternalSymbol: 722 case ISD::ConstantPool: 723 case ISD::JumpTable: // Nothing to do. 724 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 725 default: assert(0 && "This action is not supported yet!"); 726 case TargetLowering::Custom: 727 Tmp1 = TLI.LowerOperation(Op, DAG); 728 if (Tmp1.Val) Result = Tmp1; 729 // FALLTHROUGH if the target doesn't want to lower this op after all. 730 case TargetLowering::Legal: 731 break; 732 } 733 break; 734 case ISD::FRAMEADDR: 735 case ISD::RETURNADDR: 736 // The only option for these nodes is to custom lower them. If the target 737 // does not custom lower them, then return zero. 738 Tmp1 = TLI.LowerOperation(Op, DAG); 739 if (Tmp1.Val) 740 Result = Tmp1; 741 else 742 Result = DAG.getConstant(0, TLI.getPointerTy()); 743 break; 744 case ISD::FRAME_TO_ARGS_OFFSET: 745 MVT::ValueType VT = Node->getValueType(0); 746 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 747 default: assert(0 && "This action is not supported yet!"); 748 case TargetLowering::Custom: 749 Result = TLI.LowerOperation(Op, DAG); 750 if (Result.Val) break; 751 // Fall Thru 752 case TargetLowering::Legal: 753 Result = DAG.getConstant(0, VT); 754 break; 755 } 756 break; 757 case ISD::EXCEPTIONADDR: { 758 Tmp1 = LegalizeOp(Node->getOperand(0)); 759 MVT::ValueType VT = Node->getValueType(0); 760 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 761 default: assert(0 && "This action is not supported yet!"); 762 case TargetLowering::Expand: { 763 unsigned Reg = TLI.getExceptionAddressRegister(); 764 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo); 765 } 766 break; 767 case TargetLowering::Custom: 768 Result = TLI.LowerOperation(Op, DAG); 769 if (Result.Val) break; 770 // Fall Thru 771 case TargetLowering::Legal: { 772 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 773 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 774 Ops, 2).getValue(Op.ResNo); 775 break; 776 } 777 } 778 } 779 break; 780 case ISD::EHSELECTION: { 781 Tmp1 = LegalizeOp(Node->getOperand(0)); 782 Tmp2 = LegalizeOp(Node->getOperand(1)); 783 MVT::ValueType VT = Node->getValueType(0); 784 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 785 default: assert(0 && "This action is not supported yet!"); 786 case TargetLowering::Expand: { 787 unsigned Reg = TLI.getExceptionSelectorRegister(); 788 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo); 789 } 790 break; 791 case TargetLowering::Custom: 792 Result = TLI.LowerOperation(Op, DAG); 793 if (Result.Val) break; 794 // Fall Thru 795 case TargetLowering::Legal: { 796 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 797 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 798 Ops, 2).getValue(Op.ResNo); 799 break; 800 } 801 } 802 } 803 break; 804 case ISD::EH_RETURN: { 805 MVT::ValueType VT = Node->getValueType(0); 806 // The only "good" option for this node is to custom lower it. 807 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 808 default: assert(0 && "This action is not supported at all!"); 809 case TargetLowering::Custom: 810 Result = TLI.LowerOperation(Op, DAG); 811 if (Result.Val) break; 812 // Fall Thru 813 case TargetLowering::Legal: 814 // Target does not know, how to lower this, lower to noop 815 Result = LegalizeOp(Node->getOperand(0)); 816 break; 817 } 818 } 819 break; 820 case ISD::AssertSext: 821 case ISD::AssertZext: 822 Tmp1 = LegalizeOp(Node->getOperand(0)); 823 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 824 break; 825 case ISD::MERGE_VALUES: 826 // Legalize eliminates MERGE_VALUES nodes. 827 Result = Node->getOperand(Op.ResNo); 828 break; 829 case ISD::CopyFromReg: 830 Tmp1 = LegalizeOp(Node->getOperand(0)); 831 Result = Op.getValue(0); 832 if (Node->getNumValues() == 2) { 833 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 834 } else { 835 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 836 if (Node->getNumOperands() == 3) { 837 Tmp2 = LegalizeOp(Node->getOperand(2)); 838 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 839 } else { 840 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 841 } 842 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 843 } 844 // Since CopyFromReg produces two values, make sure to remember that we 845 // legalized both of them. 846 AddLegalizedOperand(Op.getValue(0), Result); 847 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 848 return Result.getValue(Op.ResNo); 849 case ISD::UNDEF: { 850 MVT::ValueType VT = Op.getValueType(); 851 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 852 default: assert(0 && "This action is not supported yet!"); 853 case TargetLowering::Expand: 854 if (MVT::isInteger(VT)) 855 Result = DAG.getConstant(0, VT); 856 else if (MVT::isFloatingPoint(VT)) 857 Result = DAG.getConstantFP(0, VT); 858 else 859 assert(0 && "Unknown value type!"); 860 break; 861 case TargetLowering::Legal: 862 break; 863 } 864 break; 865 } 866 867 case ISD::INTRINSIC_W_CHAIN: 868 case ISD::INTRINSIC_WO_CHAIN: 869 case ISD::INTRINSIC_VOID: { 870 SmallVector<SDOperand, 8> Ops; 871 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 872 Ops.push_back(LegalizeOp(Node->getOperand(i))); 873 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 874 875 // Allow the target to custom lower its intrinsics if it wants to. 876 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 877 TargetLowering::Custom) { 878 Tmp3 = TLI.LowerOperation(Result, DAG); 879 if (Tmp3.Val) Result = Tmp3; 880 } 881 882 if (Result.Val->getNumValues() == 1) break; 883 884 // Must have return value and chain result. 885 assert(Result.Val->getNumValues() == 2 && 886 "Cannot return more than two values!"); 887 888 // Since loads produce two values, make sure to remember that we 889 // legalized both of them. 890 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 891 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 892 return Result.getValue(Op.ResNo); 893 } 894 895 case ISD::LOCATION: 896 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 897 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 898 899 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 900 case TargetLowering::Promote: 901 default: assert(0 && "This action is not supported yet!"); 902 case TargetLowering::Expand: { 903 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 904 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 905 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 906 907 if (MMI && (useDEBUG_LOC || useLABEL)) { 908 const std::string &FName = 909 cast<StringSDNode>(Node->getOperand(3))->getValue(); 910 const std::string &DirName = 911 cast<StringSDNode>(Node->getOperand(4))->getValue(); 912 unsigned SrcFile = MMI->RecordSource(DirName, FName); 913 914 SmallVector<SDOperand, 8> Ops; 915 Ops.push_back(Tmp1); // chain 916 SDOperand LineOp = Node->getOperand(1); 917 SDOperand ColOp = Node->getOperand(2); 918 919 if (useDEBUG_LOC) { 920 Ops.push_back(LineOp); // line # 921 Ops.push_back(ColOp); // col # 922 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 923 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 924 } else { 925 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 926 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 927 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile); 928 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 929 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size()); 930 } 931 } else { 932 Result = Tmp1; // chain 933 } 934 break; 935 } 936 case TargetLowering::Legal: 937 if (Tmp1 != Node->getOperand(0) || 938 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 939 SmallVector<SDOperand, 8> Ops; 940 Ops.push_back(Tmp1); 941 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 942 Ops.push_back(Node->getOperand(1)); // line # must be legal. 943 Ops.push_back(Node->getOperand(2)); // col # must be legal. 944 } else { 945 // Otherwise promote them. 946 Ops.push_back(PromoteOp(Node->getOperand(1))); 947 Ops.push_back(PromoteOp(Node->getOperand(2))); 948 } 949 Ops.push_back(Node->getOperand(3)); // filename must be legal. 950 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 951 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 952 } 953 break; 954 } 955 break; 956 957 case ISD::DEBUG_LOC: 958 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 959 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 960 default: assert(0 && "This action is not supported yet!"); 961 case TargetLowering::Legal: 962 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 963 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 964 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 965 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 966 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 967 break; 968 } 969 break; 970 971 case ISD::LABEL: 972 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!"); 973 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 974 default: assert(0 && "This action is not supported yet!"); 975 case TargetLowering::Legal: 976 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 977 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 978 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 979 break; 980 case TargetLowering::Expand: 981 Result = LegalizeOp(Node->getOperand(0)); 982 break; 983 } 984 break; 985 986 case ISD::Constant: { 987 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 988 unsigned opAction = 989 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 990 991 // We know we don't need to expand constants here, constants only have one 992 // value and we check that it is fine above. 993 994 if (opAction == TargetLowering::Custom) { 995 Tmp1 = TLI.LowerOperation(Result, DAG); 996 if (Tmp1.Val) 997 Result = Tmp1; 998 } 999 break; 1000 } 1001 case ISD::ConstantFP: { 1002 // Spill FP immediates to the constant pool if the target cannot directly 1003 // codegen them. Targets often have some immediate values that can be 1004 // efficiently generated into an FP register without a load. We explicitly 1005 // leave these constants as ConstantFP nodes for the target to deal with. 1006 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1007 1008 // Check to see if this FP immediate is already legal. 1009 bool isLegal = false; 1010 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1011 E = TLI.legal_fpimm_end(); I != E; ++I) 1012 if (CFP->isExactlyValue(*I)) { 1013 isLegal = true; 1014 break; 1015 } 1016 1017 // If this is a legal constant, turn it into a TargetConstantFP node. 1018 if (isLegal) { 1019 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0)); 1020 break; 1021 } 1022 1023 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1024 default: assert(0 && "This action is not supported yet!"); 1025 case TargetLowering::Custom: 1026 Tmp3 = TLI.LowerOperation(Result, DAG); 1027 if (Tmp3.Val) { 1028 Result = Tmp3; 1029 break; 1030 } 1031 // FALLTHROUGH 1032 case TargetLowering::Expand: 1033 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1034 } 1035 break; 1036 } 1037 case ISD::TokenFactor: 1038 if (Node->getNumOperands() == 2) { 1039 Tmp1 = LegalizeOp(Node->getOperand(0)); 1040 Tmp2 = LegalizeOp(Node->getOperand(1)); 1041 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1042 } else if (Node->getNumOperands() == 3) { 1043 Tmp1 = LegalizeOp(Node->getOperand(0)); 1044 Tmp2 = LegalizeOp(Node->getOperand(1)); 1045 Tmp3 = LegalizeOp(Node->getOperand(2)); 1046 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1047 } else { 1048 SmallVector<SDOperand, 8> Ops; 1049 // Legalize the operands. 1050 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1051 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1052 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1053 } 1054 break; 1055 1056 case ISD::FORMAL_ARGUMENTS: 1057 case ISD::CALL: 1058 // The only option for this is to custom lower it. 1059 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1060 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1061 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() && 1062 "Lowering call/formal_arguments produced unexpected # results!"); 1063 1064 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1065 // remember that we legalized all of them, so it doesn't get relegalized. 1066 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1067 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1068 if (Op.ResNo == i) 1069 Tmp2 = Tmp1; 1070 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1071 } 1072 return Tmp2; 1073 case ISD::EXTRACT_SUBREG: { 1074 Tmp1 = LegalizeOp(Node->getOperand(0)); 1075 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1076 assert(idx && "Operand must be a constant"); 1077 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1078 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1079 } 1080 break; 1081 case ISD::INSERT_SUBREG: { 1082 Tmp1 = LegalizeOp(Node->getOperand(0)); 1083 Tmp2 = LegalizeOp(Node->getOperand(1)); 1084 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1085 assert(idx && "Operand must be a constant"); 1086 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1087 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1088 } 1089 break; 1090 case ISD::BUILD_VECTOR: 1091 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1092 default: assert(0 && "This action is not supported yet!"); 1093 case TargetLowering::Custom: 1094 Tmp3 = TLI.LowerOperation(Result, DAG); 1095 if (Tmp3.Val) { 1096 Result = Tmp3; 1097 break; 1098 } 1099 // FALLTHROUGH 1100 case TargetLowering::Expand: 1101 Result = ExpandBUILD_VECTOR(Result.Val); 1102 break; 1103 } 1104 break; 1105 case ISD::INSERT_VECTOR_ELT: 1106 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1107 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 1108 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1109 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1110 1111 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1112 Node->getValueType(0))) { 1113 default: assert(0 && "This action is not supported yet!"); 1114 case TargetLowering::Legal: 1115 break; 1116 case TargetLowering::Custom: 1117 Tmp3 = TLI.LowerOperation(Result, DAG); 1118 if (Tmp3.Val) { 1119 Result = Tmp3; 1120 break; 1121 } 1122 // FALLTHROUGH 1123 case TargetLowering::Expand: { 1124 // If the insert index is a constant, codegen this as a scalar_to_vector, 1125 // then a shuffle that inserts it into the right position in the vector. 1126 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1127 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1128 Tmp1.getValueType(), Tmp2); 1129 1130 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1131 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1132 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); 1133 1134 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 1135 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 1136 // the RHS. 1137 SmallVector<SDOperand, 8> ShufOps; 1138 for (unsigned i = 0; i != NumElts; ++i) { 1139 if (i != InsertPos->getValue()) 1140 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1141 else 1142 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1143 } 1144 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1145 &ShufOps[0], ShufOps.size()); 1146 1147 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1148 Tmp1, ScVec, ShufMask); 1149 Result = LegalizeOp(Result); 1150 break; 1151 } 1152 1153 // If the target doesn't support this, we have to spill the input vector 1154 // to a temporary stack slot, update the element, then reload it. This is 1155 // badness. We could also load the value into a vector register (either 1156 // with a "move to register" or "extload into register" instruction, then 1157 // permute it into place, if the idx is a constant and if the idx is 1158 // supported by the target. 1159 MVT::ValueType VT = Tmp1.getValueType(); 1160 MVT::ValueType EltVT = Tmp2.getValueType(); 1161 MVT::ValueType IdxVT = Tmp3.getValueType(); 1162 MVT::ValueType PtrVT = TLI.getPointerTy(); 1163 SDOperand StackPtr = CreateStackTemporary(VT); 1164 // Store the vector. 1165 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); 1166 1167 // Truncate or zero extend offset to target pointer type. 1168 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1169 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 1170 // Add the offset to the index. 1171 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 1172 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 1173 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 1174 // Store the scalar value. 1175 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); 1176 // Load the updated vector. 1177 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); 1178 break; 1179 } 1180 } 1181 break; 1182 case ISD::SCALAR_TO_VECTOR: 1183 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1184 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1185 break; 1186 } 1187 1188 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1189 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1190 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1191 Node->getValueType(0))) { 1192 default: assert(0 && "This action is not supported yet!"); 1193 case TargetLowering::Legal: 1194 break; 1195 case TargetLowering::Custom: 1196 Tmp3 = TLI.LowerOperation(Result, DAG); 1197 if (Tmp3.Val) { 1198 Result = Tmp3; 1199 break; 1200 } 1201 // FALLTHROUGH 1202 case TargetLowering::Expand: 1203 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1204 break; 1205 } 1206 break; 1207 case ISD::VECTOR_SHUFFLE: 1208 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1209 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1210 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1211 1212 // Allow targets to custom lower the SHUFFLEs they support. 1213 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1214 default: assert(0 && "Unknown operation action!"); 1215 case TargetLowering::Legal: 1216 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1217 "vector shuffle should not be created if not legal!"); 1218 break; 1219 case TargetLowering::Custom: 1220 Tmp3 = TLI.LowerOperation(Result, DAG); 1221 if (Tmp3.Val) { 1222 Result = Tmp3; 1223 break; 1224 } 1225 // FALLTHROUGH 1226 case TargetLowering::Expand: { 1227 MVT::ValueType VT = Node->getValueType(0); 1228 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1229 MVT::ValueType PtrVT = TLI.getPointerTy(); 1230 SDOperand Mask = Node->getOperand(2); 1231 unsigned NumElems = Mask.getNumOperands(); 1232 SmallVector<SDOperand,8> Ops; 1233 for (unsigned i = 0; i != NumElems; ++i) { 1234 SDOperand Arg = Mask.getOperand(i); 1235 if (Arg.getOpcode() == ISD::UNDEF) { 1236 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1237 } else { 1238 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1239 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1240 if (Idx < NumElems) 1241 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1242 DAG.getConstant(Idx, PtrVT))); 1243 else 1244 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1245 DAG.getConstant(Idx - NumElems, PtrVT))); 1246 } 1247 } 1248 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1249 break; 1250 } 1251 case TargetLowering::Promote: { 1252 // Change base type to a different vector type. 1253 MVT::ValueType OVT = Node->getValueType(0); 1254 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1255 1256 // Cast the two input vectors. 1257 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1258 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1259 1260 // Convert the shuffle mask to the right # elements. 1261 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1262 assert(Tmp3.Val && "Shuffle not legal?"); 1263 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1264 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1265 break; 1266 } 1267 } 1268 break; 1269 1270 case ISD::EXTRACT_VECTOR_ELT: 1271 Tmp1 = Node->getOperand(0); 1272 Tmp2 = LegalizeOp(Node->getOperand(1)); 1273 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1274 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1275 break; 1276 1277 case ISD::EXTRACT_SUBVECTOR: 1278 Tmp1 = Node->getOperand(0); 1279 Tmp2 = LegalizeOp(Node->getOperand(1)); 1280 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1281 Result = ExpandEXTRACT_SUBVECTOR(Result); 1282 break; 1283 1284 case ISD::CALLSEQ_START: { 1285 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1286 1287 // Recursively Legalize all of the inputs of the call end that do not lead 1288 // to this call start. This ensures that any libcalls that need be inserted 1289 // are inserted *before* the CALLSEQ_START. 1290 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1291 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1292 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1293 NodesLeadingTo); 1294 } 1295 1296 // Now that we legalized all of the inputs (which may have inserted 1297 // libcalls) create the new CALLSEQ_START node. 1298 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1299 1300 // Merge in the last call, to ensure that this call start after the last 1301 // call ended. 1302 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1303 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1304 Tmp1 = LegalizeOp(Tmp1); 1305 } 1306 1307 // Do not try to legalize the target-specific arguments (#1+). 1308 if (Tmp1 != Node->getOperand(0)) { 1309 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1310 Ops[0] = Tmp1; 1311 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1312 } 1313 1314 // Remember that the CALLSEQ_START is legalized. 1315 AddLegalizedOperand(Op.getValue(0), Result); 1316 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1317 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1318 1319 // Now that the callseq_start and all of the non-call nodes above this call 1320 // sequence have been legalized, legalize the call itself. During this 1321 // process, no libcalls can/will be inserted, guaranteeing that no calls 1322 // can overlap. 1323 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1324 SDOperand InCallSEQ = LastCALLSEQ_END; 1325 // Note that we are selecting this call! 1326 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1327 IsLegalizingCall = true; 1328 1329 // Legalize the call, starting from the CALLSEQ_END. 1330 LegalizeOp(LastCALLSEQ_END); 1331 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1332 return Result; 1333 } 1334 case ISD::CALLSEQ_END: 1335 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1336 // will cause this node to be legalized as well as handling libcalls right. 1337 if (LastCALLSEQ_END.Val != Node) { 1338 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1339 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1340 assert(I != LegalizedNodes.end() && 1341 "Legalizing the call start should have legalized this node!"); 1342 return I->second; 1343 } 1344 1345 // Otherwise, the call start has been legalized and everything is going 1346 // according to plan. Just legalize ourselves normally here. 1347 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1348 // Do not try to legalize the target-specific arguments (#1+), except for 1349 // an optional flag input. 1350 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1351 if (Tmp1 != Node->getOperand(0)) { 1352 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1353 Ops[0] = Tmp1; 1354 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1355 } 1356 } else { 1357 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1358 if (Tmp1 != Node->getOperand(0) || 1359 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1360 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1361 Ops[0] = Tmp1; 1362 Ops.back() = Tmp2; 1363 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1364 } 1365 } 1366 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1367 // This finishes up call legalization. 1368 IsLegalizingCall = false; 1369 1370 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1371 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1372 if (Node->getNumValues() == 2) 1373 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1374 return Result.getValue(Op.ResNo); 1375 case ISD::DYNAMIC_STACKALLOC: { 1376 MVT::ValueType VT = Node->getValueType(0); 1377 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1378 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1379 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1380 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1381 1382 Tmp1 = Result.getValue(0); 1383 Tmp2 = Result.getValue(1); 1384 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1385 default: assert(0 && "This action is not supported yet!"); 1386 case TargetLowering::Expand: { 1387 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1388 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1389 " not tell us which reg is the stack pointer!"); 1390 SDOperand Chain = Tmp1.getOperand(0); 1391 SDOperand Size = Tmp2.getOperand(1); 1392 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1393 Chain = SP.getValue(1); 1394 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1395 unsigned StackAlign = 1396 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1397 if (Align > StackAlign) 1398 SP = DAG.getNode(ISD::AND, VT, SP, 1399 DAG.getConstant(-(uint64_t)Align, VT)); 1400 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1401 Tmp2 = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1402 Tmp1 = LegalizeOp(Tmp1); 1403 Tmp2 = LegalizeOp(Tmp2); 1404 break; 1405 } 1406 case TargetLowering::Custom: 1407 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1408 if (Tmp3.Val) { 1409 Tmp1 = LegalizeOp(Tmp3); 1410 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1411 } 1412 break; 1413 case TargetLowering::Legal: 1414 break; 1415 } 1416 // Since this op produce two values, make sure to remember that we 1417 // legalized both of them. 1418 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1419 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1420 return Op.ResNo ? Tmp2 : Tmp1; 1421 } 1422 case ISD::INLINEASM: { 1423 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1424 bool Changed = false; 1425 // Legalize all of the operands of the inline asm, in case they are nodes 1426 // that need to be expanded or something. Note we skip the asm string and 1427 // all of the TargetConstant flags. 1428 SDOperand Op = LegalizeOp(Ops[0]); 1429 Changed = Op != Ops[0]; 1430 Ops[0] = Op; 1431 1432 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1433 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1434 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1435 for (++i; NumVals; ++i, --NumVals) { 1436 SDOperand Op = LegalizeOp(Ops[i]); 1437 if (Op != Ops[i]) { 1438 Changed = true; 1439 Ops[i] = Op; 1440 } 1441 } 1442 } 1443 1444 if (HasInFlag) { 1445 Op = LegalizeOp(Ops.back()); 1446 Changed |= Op != Ops.back(); 1447 Ops.back() = Op; 1448 } 1449 1450 if (Changed) 1451 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1452 1453 // INLINE asm returns a chain and flag, make sure to add both to the map. 1454 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1455 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1456 return Result.getValue(Op.ResNo); 1457 } 1458 case ISD::BR: 1459 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1460 // Ensure that libcalls are emitted before a branch. 1461 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1462 Tmp1 = LegalizeOp(Tmp1); 1463 LastCALLSEQ_END = DAG.getEntryNode(); 1464 1465 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1466 break; 1467 case ISD::BRIND: 1468 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1469 // Ensure that libcalls are emitted before a branch. 1470 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1471 Tmp1 = LegalizeOp(Tmp1); 1472 LastCALLSEQ_END = DAG.getEntryNode(); 1473 1474 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1475 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1476 case Legal: 1477 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1478 break; 1479 } 1480 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1481 break; 1482 case ISD::BR_JT: 1483 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1484 // Ensure that libcalls are emitted before a branch. 1485 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1486 Tmp1 = LegalizeOp(Tmp1); 1487 LastCALLSEQ_END = DAG.getEntryNode(); 1488 1489 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1490 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1491 1492 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1493 default: assert(0 && "This action is not supported yet!"); 1494 case TargetLowering::Legal: break; 1495 case TargetLowering::Custom: 1496 Tmp1 = TLI.LowerOperation(Result, DAG); 1497 if (Tmp1.Val) Result = Tmp1; 1498 break; 1499 case TargetLowering::Expand: { 1500 SDOperand Chain = Result.getOperand(0); 1501 SDOperand Table = Result.getOperand(1); 1502 SDOperand Index = Result.getOperand(2); 1503 1504 MVT::ValueType PTy = TLI.getPointerTy(); 1505 MachineFunction &MF = DAG.getMachineFunction(); 1506 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1507 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1508 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1509 1510 SDOperand LD; 1511 switch (EntrySize) { 1512 default: assert(0 && "Size of jump table not supported yet."); break; 1513 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; 1514 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; 1515 } 1516 1517 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1518 // For PIC, the sequence is: 1519 // BRIND(load(Jumptable + index) + RelocBase) 1520 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha 1521 SDOperand Reloc; 1522 if (TLI.usesGlobalOffsetTable()) 1523 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy); 1524 else 1525 Reloc = Table; 1526 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD; 1527 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc); 1528 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1529 } else { 1530 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD); 1531 } 1532 } 1533 } 1534 break; 1535 case ISD::BRCOND: 1536 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1537 // Ensure that libcalls are emitted before a return. 1538 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1539 Tmp1 = LegalizeOp(Tmp1); 1540 LastCALLSEQ_END = DAG.getEntryNode(); 1541 1542 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1543 case Expand: assert(0 && "It's impossible to expand bools"); 1544 case Legal: 1545 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1546 break; 1547 case Promote: 1548 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1549 1550 // The top bits of the promoted condition are not necessarily zero, ensure 1551 // that the value is properly zero extended. 1552 if (!DAG.MaskedValueIsZero(Tmp2, 1553 MVT::getIntVTBitMask(Tmp2.getValueType())^1)) 1554 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1555 break; 1556 } 1557 1558 // Basic block destination (Op#2) is always legal. 1559 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1560 1561 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1562 default: assert(0 && "This action is not supported yet!"); 1563 case TargetLowering::Legal: break; 1564 case TargetLowering::Custom: 1565 Tmp1 = TLI.LowerOperation(Result, DAG); 1566 if (Tmp1.Val) Result = Tmp1; 1567 break; 1568 case TargetLowering::Expand: 1569 // Expand brcond's setcc into its constituent parts and create a BR_CC 1570 // Node. 1571 if (Tmp2.getOpcode() == ISD::SETCC) { 1572 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1573 Tmp2.getOperand(0), Tmp2.getOperand(1), 1574 Node->getOperand(2)); 1575 } else { 1576 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1577 DAG.getCondCode(ISD::SETNE), Tmp2, 1578 DAG.getConstant(0, Tmp2.getValueType()), 1579 Node->getOperand(2)); 1580 } 1581 break; 1582 } 1583 break; 1584 case ISD::BR_CC: 1585 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1586 // Ensure that libcalls are emitted before a branch. 1587 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1588 Tmp1 = LegalizeOp(Tmp1); 1589 Tmp2 = Node->getOperand(2); // LHS 1590 Tmp3 = Node->getOperand(3); // RHS 1591 Tmp4 = Node->getOperand(1); // CC 1592 1593 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1594 LastCALLSEQ_END = DAG.getEntryNode(); 1595 1596 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1597 // the LHS is a legal SETCC itself. In this case, we need to compare 1598 // the result against zero to select between true and false values. 1599 if (Tmp3.Val == 0) { 1600 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1601 Tmp4 = DAG.getCondCode(ISD::SETNE); 1602 } 1603 1604 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1605 Node->getOperand(4)); 1606 1607 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1608 default: assert(0 && "Unexpected action for BR_CC!"); 1609 case TargetLowering::Legal: break; 1610 case TargetLowering::Custom: 1611 Tmp4 = TLI.LowerOperation(Result, DAG); 1612 if (Tmp4.Val) Result = Tmp4; 1613 break; 1614 } 1615 break; 1616 case ISD::LOAD: { 1617 LoadSDNode *LD = cast<LoadSDNode>(Node); 1618 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1619 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1620 1621 ISD::LoadExtType ExtType = LD->getExtensionType(); 1622 if (ExtType == ISD::NON_EXTLOAD) { 1623 MVT::ValueType VT = Node->getValueType(0); 1624 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1625 Tmp3 = Result.getValue(0); 1626 Tmp4 = Result.getValue(1); 1627 1628 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1629 default: assert(0 && "This action is not supported yet!"); 1630 case TargetLowering::Legal: 1631 // If this is an unaligned load and the target doesn't support it, 1632 // expand it. 1633 if (!TLI.allowsUnalignedMemoryAccesses()) { 1634 unsigned ABIAlignment = TLI.getTargetData()-> 1635 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1636 if (LD->getAlignment() < ABIAlignment){ 1637 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1638 TLI); 1639 Tmp3 = Result.getOperand(0); 1640 Tmp4 = Result.getOperand(1); 1641 LegalizeOp(Tmp3); 1642 LegalizeOp(Tmp4); 1643 } 1644 } 1645 break; 1646 case TargetLowering::Custom: 1647 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1648 if (Tmp1.Val) { 1649 Tmp3 = LegalizeOp(Tmp1); 1650 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1651 } 1652 break; 1653 case TargetLowering::Promote: { 1654 // Only promote a load of vector type to another. 1655 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1656 // Change base type to a different vector type. 1657 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1658 1659 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1660 LD->getSrcValueOffset(), 1661 LD->isVolatile(), LD->getAlignment()); 1662 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1663 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1664 break; 1665 } 1666 } 1667 // Since loads produce two values, make sure to remember that we 1668 // legalized both of them. 1669 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1670 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1671 return Op.ResNo ? Tmp4 : Tmp3; 1672 } else { 1673 MVT::ValueType SrcVT = LD->getLoadedVT(); 1674 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1675 default: assert(0 && "This action is not supported yet!"); 1676 case TargetLowering::Promote: 1677 assert(SrcVT == MVT::i1 && 1678 "Can only promote extending LOAD from i1 -> i8!"); 1679 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1680 LD->getSrcValue(), LD->getSrcValueOffset(), 1681 MVT::i8, LD->isVolatile(), LD->getAlignment()); 1682 Tmp1 = Result.getValue(0); 1683 Tmp2 = Result.getValue(1); 1684 break; 1685 case TargetLowering::Custom: 1686 isCustom = true; 1687 // FALLTHROUGH 1688 case TargetLowering::Legal: 1689 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1690 Tmp1 = Result.getValue(0); 1691 Tmp2 = Result.getValue(1); 1692 1693 if (isCustom) { 1694 Tmp3 = TLI.LowerOperation(Result, DAG); 1695 if (Tmp3.Val) { 1696 Tmp1 = LegalizeOp(Tmp3); 1697 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1698 } 1699 } else { 1700 // If this is an unaligned load and the target doesn't support it, 1701 // expand it. 1702 if (!TLI.allowsUnalignedMemoryAccesses()) { 1703 unsigned ABIAlignment = TLI.getTargetData()-> 1704 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1705 if (LD->getAlignment() < ABIAlignment){ 1706 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1707 TLI); 1708 Tmp1 = Result.getOperand(0); 1709 Tmp2 = Result.getOperand(1); 1710 LegalizeOp(Tmp1); 1711 LegalizeOp(Tmp2); 1712 } 1713 } 1714 } 1715 break; 1716 case TargetLowering::Expand: 1717 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1718 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1719 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 1720 LD->getSrcValueOffset(), 1721 LD->isVolatile(), LD->getAlignment()); 1722 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1723 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1724 Tmp2 = LegalizeOp(Load.getValue(1)); 1725 break; 1726 } 1727 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1728 // Turn the unsupported load into an EXTLOAD followed by an explicit 1729 // zero/sign extend inreg. 1730 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1731 Tmp1, Tmp2, LD->getSrcValue(), 1732 LD->getSrcValueOffset(), SrcVT, 1733 LD->isVolatile(), LD->getAlignment()); 1734 SDOperand ValRes; 1735 if (ExtType == ISD::SEXTLOAD) 1736 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1737 Result, DAG.getValueType(SrcVT)); 1738 else 1739 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1740 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1741 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1742 break; 1743 } 1744 // Since loads produce two values, make sure to remember that we legalized 1745 // both of them. 1746 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1747 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1748 return Op.ResNo ? Tmp2 : Tmp1; 1749 } 1750 } 1751 case ISD::EXTRACT_ELEMENT: { 1752 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1753 switch (getTypeAction(OpTy)) { 1754 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1755 case Legal: 1756 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1757 // 1 -> Hi 1758 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1759 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1760 TLI.getShiftAmountTy())); 1761 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1762 } else { 1763 // 0 -> Lo 1764 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1765 Node->getOperand(0)); 1766 } 1767 break; 1768 case Expand: 1769 // Get both the low and high parts. 1770 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1771 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1772 Result = Tmp2; // 1 -> Hi 1773 else 1774 Result = Tmp1; // 0 -> Lo 1775 break; 1776 } 1777 break; 1778 } 1779 1780 case ISD::CopyToReg: 1781 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1782 1783 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1784 "Register type must be legal!"); 1785 // Legalize the incoming value (must be a legal type). 1786 Tmp2 = LegalizeOp(Node->getOperand(2)); 1787 if (Node->getNumValues() == 1) { 1788 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1789 } else { 1790 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1791 if (Node->getNumOperands() == 4) { 1792 Tmp3 = LegalizeOp(Node->getOperand(3)); 1793 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1794 Tmp3); 1795 } else { 1796 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1797 } 1798 1799 // Since this produces two values, make sure to remember that we legalized 1800 // both of them. 1801 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1802 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1803 return Result; 1804 } 1805 break; 1806 1807 case ISD::RET: 1808 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1809 1810 // Ensure that libcalls are emitted before a return. 1811 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1812 Tmp1 = LegalizeOp(Tmp1); 1813 LastCALLSEQ_END = DAG.getEntryNode(); 1814 1815 switch (Node->getNumOperands()) { 1816 case 3: // ret val 1817 Tmp2 = Node->getOperand(1); 1818 Tmp3 = Node->getOperand(2); // Signness 1819 switch (getTypeAction(Tmp2.getValueType())) { 1820 case Legal: 1821 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1822 break; 1823 case Expand: 1824 if (!MVT::isVector(Tmp2.getValueType())) { 1825 SDOperand Lo, Hi; 1826 ExpandOp(Tmp2, Lo, Hi); 1827 1828 // Big endian systems want the hi reg first. 1829 if (!TLI.isLittleEndian()) 1830 std::swap(Lo, Hi); 1831 1832 if (Hi.Val) 1833 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1834 else 1835 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 1836 Result = LegalizeOp(Result); 1837 } else { 1838 SDNode *InVal = Tmp2.Val; 1839 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0)); 1840 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0)); 1841 1842 // Figure out if there is a simple type corresponding to this Vector 1843 // type. If so, convert to the vector type. 1844 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1845 if (TLI.isTypeLegal(TVT)) { 1846 // Turn this into a return of the vector type. 1847 Tmp2 = LegalizeOp(Tmp2); 1848 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1849 } else if (NumElems == 1) { 1850 // Turn this into a return of the scalar type. 1851 Tmp2 = ScalarizeVectorOp(Tmp2); 1852 Tmp2 = LegalizeOp(Tmp2); 1853 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1854 1855 // FIXME: Returns of gcc generic vectors smaller than a legal type 1856 // should be returned in integer registers! 1857 1858 // The scalarized value type may not be legal, e.g. it might require 1859 // promotion or expansion. Relegalize the return. 1860 Result = LegalizeOp(Result); 1861 } else { 1862 // FIXME: Returns of gcc generic vectors larger than a legal vector 1863 // type should be returned by reference! 1864 SDOperand Lo, Hi; 1865 SplitVectorOp(Tmp2, Lo, Hi); 1866 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1867 Result = LegalizeOp(Result); 1868 } 1869 } 1870 break; 1871 case Promote: 1872 Tmp2 = PromoteOp(Node->getOperand(1)); 1873 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1874 Result = LegalizeOp(Result); 1875 break; 1876 } 1877 break; 1878 case 1: // ret void 1879 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1880 break; 1881 default: { // ret <values> 1882 SmallVector<SDOperand, 8> NewValues; 1883 NewValues.push_back(Tmp1); 1884 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 1885 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1886 case Legal: 1887 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1888 NewValues.push_back(Node->getOperand(i+1)); 1889 break; 1890 case Expand: { 1891 SDOperand Lo, Hi; 1892 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && 1893 "FIXME: TODO: implement returning non-legal vector types!"); 1894 ExpandOp(Node->getOperand(i), Lo, Hi); 1895 NewValues.push_back(Lo); 1896 NewValues.push_back(Node->getOperand(i+1)); 1897 if (Hi.Val) { 1898 NewValues.push_back(Hi); 1899 NewValues.push_back(Node->getOperand(i+1)); 1900 } 1901 break; 1902 } 1903 case Promote: 1904 assert(0 && "Can't promote multiple return value yet!"); 1905 } 1906 1907 if (NewValues.size() == Node->getNumOperands()) 1908 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 1909 else 1910 Result = DAG.getNode(ISD::RET, MVT::Other, 1911 &NewValues[0], NewValues.size()); 1912 break; 1913 } 1914 } 1915 1916 if (Result.getOpcode() == ISD::RET) { 1917 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 1918 default: assert(0 && "This action is not supported yet!"); 1919 case TargetLowering::Legal: break; 1920 case TargetLowering::Custom: 1921 Tmp1 = TLI.LowerOperation(Result, DAG); 1922 if (Tmp1.Val) Result = Tmp1; 1923 break; 1924 } 1925 } 1926 break; 1927 case ISD::STORE: { 1928 StoreSDNode *ST = cast<StoreSDNode>(Node); 1929 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1930 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1931 int SVOffset = ST->getSrcValueOffset(); 1932 unsigned Alignment = ST->getAlignment(); 1933 bool isVolatile = ST->isVolatile(); 1934 1935 if (!ST->isTruncatingStore()) { 1936 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1937 // FIXME: We shouldn't do this for TargetConstantFP's. 1938 // FIXME: move this to the DAG Combiner! Note that we can't regress due 1939 // to phase ordering between legalized code and the dag combiner. This 1940 // probably means that we need to integrate dag combiner and legalizer 1941 // together. 1942 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 1943 if (CFP->getValueType(0) == MVT::f32) { 1944 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 1945 } else { 1946 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1947 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 1948 } 1949 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1950 SVOffset, isVolatile, Alignment); 1951 break; 1952 } 1953 1954 switch (getTypeAction(ST->getStoredVT())) { 1955 case Legal: { 1956 Tmp3 = LegalizeOp(ST->getValue()); 1957 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1958 ST->getOffset()); 1959 1960 MVT::ValueType VT = Tmp3.getValueType(); 1961 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1962 default: assert(0 && "This action is not supported yet!"); 1963 case TargetLowering::Legal: 1964 // If this is an unaligned store and the target doesn't support it, 1965 // expand it. 1966 if (!TLI.allowsUnalignedMemoryAccesses()) { 1967 unsigned ABIAlignment = TLI.getTargetData()-> 1968 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 1969 if (ST->getAlignment() < ABIAlignment) 1970 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 1971 TLI); 1972 } 1973 break; 1974 case TargetLowering::Custom: 1975 Tmp1 = TLI.LowerOperation(Result, DAG); 1976 if (Tmp1.Val) Result = Tmp1; 1977 break; 1978 case TargetLowering::Promote: 1979 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 1980 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 1981 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1982 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 1983 ST->getSrcValue(), SVOffset, isVolatile, 1984 Alignment); 1985 break; 1986 } 1987 break; 1988 } 1989 case Promote: 1990 // Truncate the value and store the result. 1991 Tmp3 = PromoteOp(ST->getValue()); 1992 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1993 SVOffset, ST->getStoredVT(), 1994 isVolatile, Alignment); 1995 break; 1996 1997 case Expand: 1998 unsigned IncrementSize = 0; 1999 SDOperand Lo, Hi; 2000 2001 // If this is a vector type, then we have to calculate the increment as 2002 // the product of the element size in bytes, and the number of elements 2003 // in the high half of the vector. 2004 if (MVT::isVector(ST->getValue().getValueType())) { 2005 SDNode *InVal = ST->getValue().Val; 2006 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0)); 2007 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0)); 2008 2009 // Figure out if there is a simple type corresponding to this Vector 2010 // type. If so, convert to the vector type. 2011 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2012 if (TLI.isTypeLegal(TVT)) { 2013 // Turn this into a normal store of the vector type. 2014 Tmp3 = LegalizeOp(Node->getOperand(1)); 2015 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2016 SVOffset, isVolatile, Alignment); 2017 Result = LegalizeOp(Result); 2018 break; 2019 } else if (NumElems == 1) { 2020 // Turn this into a normal store of the scalar type. 2021 Tmp3 = ScalarizeVectorOp(Node->getOperand(1)); 2022 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2023 SVOffset, isVolatile, Alignment); 2024 // The scalarized value type may not be legal, e.g. it might require 2025 // promotion or expansion. Relegalize the scalar store. 2026 Result = LegalizeOp(Result); 2027 break; 2028 } else { 2029 SplitVectorOp(Node->getOperand(1), Lo, Hi); 2030 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; 2031 } 2032 } else { 2033 ExpandOp(Node->getOperand(1), Lo, Hi); 2034 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 2035 2036 if (!TLI.isLittleEndian()) 2037 std::swap(Lo, Hi); 2038 } 2039 2040 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2041 SVOffset, isVolatile, Alignment); 2042 2043 if (Hi.Val == NULL) { 2044 // Must be int <-> float one-to-one expansion. 2045 Result = Lo; 2046 break; 2047 } 2048 2049 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2050 getIntPtrConstant(IncrementSize)); 2051 assert(isTypeLegal(Tmp2.getValueType()) && 2052 "Pointers must be legal!"); 2053 SVOffset += IncrementSize; 2054 if (Alignment > IncrementSize) 2055 Alignment = IncrementSize; 2056 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2057 SVOffset, isVolatile, Alignment); 2058 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2059 break; 2060 } 2061 } else { 2062 // Truncating store 2063 assert(isTypeLegal(ST->getValue().getValueType()) && 2064 "Cannot handle illegal TRUNCSTORE yet!"); 2065 Tmp3 = LegalizeOp(ST->getValue()); 2066 2067 // The only promote case we handle is TRUNCSTORE:i1 X into 2068 // -> TRUNCSTORE:i8 (and X, 1) 2069 if (ST->getStoredVT() == MVT::i1 && 2070 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) { 2071 // Promote the bool to a mask then store. 2072 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3, 2073 DAG.getConstant(1, Tmp3.getValueType())); 2074 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2075 SVOffset, MVT::i8, 2076 isVolatile, Alignment); 2077 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2078 Tmp2 != ST->getBasePtr()) { 2079 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2080 ST->getOffset()); 2081 } 2082 2083 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT(); 2084 switch (TLI.getStoreXAction(StVT)) { 2085 default: assert(0 && "This action is not supported yet!"); 2086 case TargetLowering::Legal: 2087 // If this is an unaligned store and the target doesn't support it, 2088 // expand it. 2089 if (!TLI.allowsUnalignedMemoryAccesses()) { 2090 unsigned ABIAlignment = TLI.getTargetData()-> 2091 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2092 if (ST->getAlignment() < ABIAlignment) 2093 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2094 TLI); 2095 } 2096 break; 2097 case TargetLowering::Custom: 2098 Tmp1 = TLI.LowerOperation(Result, DAG); 2099 if (Tmp1.Val) Result = Tmp1; 2100 break; 2101 } 2102 } 2103 break; 2104 } 2105 case ISD::PCMARKER: 2106 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2107 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2108 break; 2109 case ISD::STACKSAVE: 2110 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2111 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2112 Tmp1 = Result.getValue(0); 2113 Tmp2 = Result.getValue(1); 2114 2115 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2116 default: assert(0 && "This action is not supported yet!"); 2117 case TargetLowering::Legal: break; 2118 case TargetLowering::Custom: 2119 Tmp3 = TLI.LowerOperation(Result, DAG); 2120 if (Tmp3.Val) { 2121 Tmp1 = LegalizeOp(Tmp3); 2122 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2123 } 2124 break; 2125 case TargetLowering::Expand: 2126 // Expand to CopyFromReg if the target set 2127 // StackPointerRegisterToSaveRestore. 2128 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2129 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2130 Node->getValueType(0)); 2131 Tmp2 = Tmp1.getValue(1); 2132 } else { 2133 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2134 Tmp2 = Node->getOperand(0); 2135 } 2136 break; 2137 } 2138 2139 // Since stacksave produce two values, make sure to remember that we 2140 // legalized both of them. 2141 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2142 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2143 return Op.ResNo ? Tmp2 : Tmp1; 2144 2145 case ISD::STACKRESTORE: 2146 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2147 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2148 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2149 2150 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2151 default: assert(0 && "This action is not supported yet!"); 2152 case TargetLowering::Legal: break; 2153 case TargetLowering::Custom: 2154 Tmp1 = TLI.LowerOperation(Result, DAG); 2155 if (Tmp1.Val) Result = Tmp1; 2156 break; 2157 case TargetLowering::Expand: 2158 // Expand to CopyToReg if the target set 2159 // StackPointerRegisterToSaveRestore. 2160 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2161 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2162 } else { 2163 Result = Tmp1; 2164 } 2165 break; 2166 } 2167 break; 2168 2169 case ISD::READCYCLECOUNTER: 2170 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2171 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2172 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2173 Node->getValueType(0))) { 2174 default: assert(0 && "This action is not supported yet!"); 2175 case TargetLowering::Legal: 2176 Tmp1 = Result.getValue(0); 2177 Tmp2 = Result.getValue(1); 2178 break; 2179 case TargetLowering::Custom: 2180 Result = TLI.LowerOperation(Result, DAG); 2181 Tmp1 = LegalizeOp(Result.getValue(0)); 2182 Tmp2 = LegalizeOp(Result.getValue(1)); 2183 break; 2184 } 2185 2186 // Since rdcc produce two values, make sure to remember that we legalized 2187 // both of them. 2188 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2189 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2190 return Result; 2191 2192 case ISD::SELECT: 2193 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2194 case Expand: assert(0 && "It's impossible to expand bools"); 2195 case Legal: 2196 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2197 break; 2198 case Promote: 2199 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2200 // Make sure the condition is either zero or one. 2201 if (!DAG.MaskedValueIsZero(Tmp1, 2202 MVT::getIntVTBitMask(Tmp1.getValueType())^1)) 2203 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2204 break; 2205 } 2206 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2207 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2208 2209 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2210 2211 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2212 default: assert(0 && "This action is not supported yet!"); 2213 case TargetLowering::Legal: break; 2214 case TargetLowering::Custom: { 2215 Tmp1 = TLI.LowerOperation(Result, DAG); 2216 if (Tmp1.Val) Result = Tmp1; 2217 break; 2218 } 2219 case TargetLowering::Expand: 2220 if (Tmp1.getOpcode() == ISD::SETCC) { 2221 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2222 Tmp2, Tmp3, 2223 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2224 } else { 2225 Result = DAG.getSelectCC(Tmp1, 2226 DAG.getConstant(0, Tmp1.getValueType()), 2227 Tmp2, Tmp3, ISD::SETNE); 2228 } 2229 break; 2230 case TargetLowering::Promote: { 2231 MVT::ValueType NVT = 2232 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2233 unsigned ExtOp, TruncOp; 2234 if (MVT::isVector(Tmp2.getValueType())) { 2235 ExtOp = ISD::BIT_CONVERT; 2236 TruncOp = ISD::BIT_CONVERT; 2237 } else if (MVT::isInteger(Tmp2.getValueType())) { 2238 ExtOp = ISD::ANY_EXTEND; 2239 TruncOp = ISD::TRUNCATE; 2240 } else { 2241 ExtOp = ISD::FP_EXTEND; 2242 TruncOp = ISD::FP_ROUND; 2243 } 2244 // Promote each of the values to the new type. 2245 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2246 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2247 // Perform the larger operation, then round down. 2248 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2249 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2250 break; 2251 } 2252 } 2253 break; 2254 case ISD::SELECT_CC: { 2255 Tmp1 = Node->getOperand(0); // LHS 2256 Tmp2 = Node->getOperand(1); // RHS 2257 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2258 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2259 SDOperand CC = Node->getOperand(4); 2260 2261 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2262 2263 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2264 // the LHS is a legal SETCC itself. In this case, we need to compare 2265 // the result against zero to select between true and false values. 2266 if (Tmp2.Val == 0) { 2267 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2268 CC = DAG.getCondCode(ISD::SETNE); 2269 } 2270 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2271 2272 // Everything is legal, see if we should expand this op or something. 2273 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2274 default: assert(0 && "This action is not supported yet!"); 2275 case TargetLowering::Legal: break; 2276 case TargetLowering::Custom: 2277 Tmp1 = TLI.LowerOperation(Result, DAG); 2278 if (Tmp1.Val) Result = Tmp1; 2279 break; 2280 } 2281 break; 2282 } 2283 case ISD::SETCC: 2284 Tmp1 = Node->getOperand(0); 2285 Tmp2 = Node->getOperand(1); 2286 Tmp3 = Node->getOperand(2); 2287 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2288 2289 // If we had to Expand the SetCC operands into a SELECT node, then it may 2290 // not always be possible to return a true LHS & RHS. In this case, just 2291 // return the value we legalized, returned in the LHS 2292 if (Tmp2.Val == 0) { 2293 Result = Tmp1; 2294 break; 2295 } 2296 2297 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2298 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2299 case TargetLowering::Custom: 2300 isCustom = true; 2301 // FALLTHROUGH. 2302 case TargetLowering::Legal: 2303 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2304 if (isCustom) { 2305 Tmp4 = TLI.LowerOperation(Result, DAG); 2306 if (Tmp4.Val) Result = Tmp4; 2307 } 2308 break; 2309 case TargetLowering::Promote: { 2310 // First step, figure out the appropriate operation to use. 2311 // Allow SETCC to not be supported for all legal data types 2312 // Mostly this targets FP 2313 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2314 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2315 2316 // Scan for the appropriate larger type to use. 2317 while (1) { 2318 NewInTy = (MVT::ValueType)(NewInTy+1); 2319 2320 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2321 "Fell off of the edge of the integer world"); 2322 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2323 "Fell off of the edge of the floating point world"); 2324 2325 // If the target supports SETCC of this type, use it. 2326 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2327 break; 2328 } 2329 if (MVT::isInteger(NewInTy)) 2330 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2331 else { 2332 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2333 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2334 } 2335 Tmp1 = LegalizeOp(Tmp1); 2336 Tmp2 = LegalizeOp(Tmp2); 2337 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2338 Result = LegalizeOp(Result); 2339 break; 2340 } 2341 case TargetLowering::Expand: 2342 // Expand a setcc node into a select_cc of the same condition, lhs, and 2343 // rhs that selects between const 1 (true) and const 0 (false). 2344 MVT::ValueType VT = Node->getValueType(0); 2345 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2346 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2347 Tmp3); 2348 break; 2349 } 2350 break; 2351 case ISD::MEMSET: 2352 case ISD::MEMCPY: 2353 case ISD::MEMMOVE: { 2354 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2355 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2356 2357 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2358 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2359 case Expand: assert(0 && "Cannot expand a byte!"); 2360 case Legal: 2361 Tmp3 = LegalizeOp(Node->getOperand(2)); 2362 break; 2363 case Promote: 2364 Tmp3 = PromoteOp(Node->getOperand(2)); 2365 break; 2366 } 2367 } else { 2368 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2369 } 2370 2371 SDOperand Tmp4; 2372 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2373 case Expand: { 2374 // Length is too big, just take the lo-part of the length. 2375 SDOperand HiPart; 2376 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2377 break; 2378 } 2379 case Legal: 2380 Tmp4 = LegalizeOp(Node->getOperand(3)); 2381 break; 2382 case Promote: 2383 Tmp4 = PromoteOp(Node->getOperand(3)); 2384 break; 2385 } 2386 2387 SDOperand Tmp5; 2388 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2389 case Expand: assert(0 && "Cannot expand this yet!"); 2390 case Legal: 2391 Tmp5 = LegalizeOp(Node->getOperand(4)); 2392 break; 2393 case Promote: 2394 Tmp5 = PromoteOp(Node->getOperand(4)); 2395 break; 2396 } 2397 2398 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2399 default: assert(0 && "This action not implemented for this operation!"); 2400 case TargetLowering::Custom: 2401 isCustom = true; 2402 // FALLTHROUGH 2403 case TargetLowering::Legal: 2404 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 2405 if (isCustom) { 2406 Tmp1 = TLI.LowerOperation(Result, DAG); 2407 if (Tmp1.Val) Result = Tmp1; 2408 } 2409 break; 2410 case TargetLowering::Expand: { 2411 // Otherwise, the target does not support this operation. Lower the 2412 // operation to an explicit libcall as appropriate. 2413 MVT::ValueType IntPtr = TLI.getPointerTy(); 2414 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2415 TargetLowering::ArgListTy Args; 2416 TargetLowering::ArgListEntry Entry; 2417 2418 const char *FnName = 0; 2419 if (Node->getOpcode() == ISD::MEMSET) { 2420 Entry.Node = Tmp2; Entry.Ty = IntPtrTy; 2421 Args.push_back(Entry); 2422 // Extend the (previously legalized) ubyte argument to be an int value 2423 // for the call. 2424 if (Tmp3.getValueType() > MVT::i32) 2425 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2426 else 2427 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2428 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 2429 Args.push_back(Entry); 2430 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false; 2431 Args.push_back(Entry); 2432 2433 FnName = "memset"; 2434 } else if (Node->getOpcode() == ISD::MEMCPY || 2435 Node->getOpcode() == ISD::MEMMOVE) { 2436 Entry.Ty = IntPtrTy; 2437 Entry.Node = Tmp2; Args.push_back(Entry); 2438 Entry.Node = Tmp3; Args.push_back(Entry); 2439 Entry.Node = Tmp4; Args.push_back(Entry); 2440 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2441 } else { 2442 assert(0 && "Unknown op!"); 2443 } 2444 2445 std::pair<SDOperand,SDOperand> CallResult = 2446 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 2447 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2448 Result = CallResult.second; 2449 break; 2450 } 2451 } 2452 break; 2453 } 2454 2455 case ISD::SHL_PARTS: 2456 case ISD::SRA_PARTS: 2457 case ISD::SRL_PARTS: { 2458 SmallVector<SDOperand, 8> Ops; 2459 bool Changed = false; 2460 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2461 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2462 Changed |= Ops.back() != Node->getOperand(i); 2463 } 2464 if (Changed) 2465 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2466 2467 switch (TLI.getOperationAction(Node->getOpcode(), 2468 Node->getValueType(0))) { 2469 default: assert(0 && "This action is not supported yet!"); 2470 case TargetLowering::Legal: break; 2471 case TargetLowering::Custom: 2472 Tmp1 = TLI.LowerOperation(Result, DAG); 2473 if (Tmp1.Val) { 2474 SDOperand Tmp2, RetVal(0, 0); 2475 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2476 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2477 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2478 if (i == Op.ResNo) 2479 RetVal = Tmp2; 2480 } 2481 assert(RetVal.Val && "Illegal result number"); 2482 return RetVal; 2483 } 2484 break; 2485 } 2486 2487 // Since these produce multiple values, make sure to remember that we 2488 // legalized all of them. 2489 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2490 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2491 return Result.getValue(Op.ResNo); 2492 } 2493 2494 // Binary operators 2495 case ISD::ADD: 2496 case ISD::SUB: 2497 case ISD::MUL: 2498 case ISD::MULHS: 2499 case ISD::MULHU: 2500 case ISD::UDIV: 2501 case ISD::SDIV: 2502 case ISD::AND: 2503 case ISD::OR: 2504 case ISD::XOR: 2505 case ISD::SHL: 2506 case ISD::SRL: 2507 case ISD::SRA: 2508 case ISD::FADD: 2509 case ISD::FSUB: 2510 case ISD::FMUL: 2511 case ISD::FDIV: 2512 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2513 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2514 case Expand: assert(0 && "Not possible"); 2515 case Legal: 2516 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2517 break; 2518 case Promote: 2519 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2520 break; 2521 } 2522 2523 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2524 2525 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2526 default: assert(0 && "BinOp legalize operation not supported"); 2527 case TargetLowering::Legal: break; 2528 case TargetLowering::Custom: 2529 Tmp1 = TLI.LowerOperation(Result, DAG); 2530 if (Tmp1.Val) Result = Tmp1; 2531 break; 2532 case TargetLowering::Expand: { 2533 if (Node->getValueType(0) == MVT::i32) { 2534 switch (Node->getOpcode()) { 2535 default: assert(0 && "Do not know how to expand this integer BinOp!"); 2536 case ISD::UDIV: 2537 case ISD::SDIV: 2538 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV 2539 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 2540 SDOperand Dummy; 2541 bool isSigned = Node->getOpcode() == ISD::SDIV; 2542 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2543 }; 2544 break; 2545 } 2546 2547 assert(MVT::isVector(Node->getValueType(0)) && 2548 "Cannot expand this binary operator!"); 2549 // Expand the operation into a bunch of nasty scalar code. 2550 SmallVector<SDOperand, 8> Ops; 2551 MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0)); 2552 MVT::ValueType PtrVT = TLI.getPointerTy(); 2553 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0)); 2554 i != e; ++i) { 2555 SDOperand Idx = DAG.getConstant(i, PtrVT); 2556 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx); 2557 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx); 2558 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS)); 2559 } 2560 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), 2561 &Ops[0], Ops.size()); 2562 break; 2563 } 2564 case TargetLowering::Promote: { 2565 switch (Node->getOpcode()) { 2566 default: assert(0 && "Do not know how to promote this BinOp!"); 2567 case ISD::AND: 2568 case ISD::OR: 2569 case ISD::XOR: { 2570 MVT::ValueType OVT = Node->getValueType(0); 2571 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2572 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2573 // Bit convert each of the values to the new type. 2574 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2575 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2576 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2577 // Bit convert the result back the original type. 2578 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2579 break; 2580 } 2581 } 2582 } 2583 } 2584 break; 2585 2586 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2587 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2588 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2589 case Expand: assert(0 && "Not possible"); 2590 case Legal: 2591 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2592 break; 2593 case Promote: 2594 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2595 break; 2596 } 2597 2598 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2599 2600 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2601 default: assert(0 && "Operation not supported"); 2602 case TargetLowering::Custom: 2603 Tmp1 = TLI.LowerOperation(Result, DAG); 2604 if (Tmp1.Val) Result = Tmp1; 2605 break; 2606 case TargetLowering::Legal: break; 2607 case TargetLowering::Expand: { 2608 // If this target supports fabs/fneg natively and select is cheap, 2609 // do this efficiently. 2610 if (!TLI.isSelectExpensive() && 2611 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 2612 TargetLowering::Legal && 2613 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 2614 TargetLowering::Legal) { 2615 // Get the sign bit of the RHS. 2616 MVT::ValueType IVT = 2617 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2618 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2619 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2620 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2621 // Get the absolute value of the result. 2622 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2623 // Select between the nabs and abs value based on the sign bit of 2624 // the input. 2625 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2626 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2627 AbsVal), 2628 AbsVal); 2629 Result = LegalizeOp(Result); 2630 break; 2631 } 2632 2633 // Otherwise, do bitwise ops! 2634 MVT::ValueType NVT = 2635 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 2636 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 2637 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 2638 Result = LegalizeOp(Result); 2639 break; 2640 } 2641 } 2642 break; 2643 2644 case ISD::ADDC: 2645 case ISD::SUBC: 2646 Tmp1 = LegalizeOp(Node->getOperand(0)); 2647 Tmp2 = LegalizeOp(Node->getOperand(1)); 2648 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2649 // Since this produces two values, make sure to remember that we legalized 2650 // both of them. 2651 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2652 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2653 return Result; 2654 2655 case ISD::ADDE: 2656 case ISD::SUBE: 2657 Tmp1 = LegalizeOp(Node->getOperand(0)); 2658 Tmp2 = LegalizeOp(Node->getOperand(1)); 2659 Tmp3 = LegalizeOp(Node->getOperand(2)); 2660 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2661 // Since this produces two values, make sure to remember that we legalized 2662 // both of them. 2663 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2664 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2665 return Result; 2666 2667 case ISD::BUILD_PAIR: { 2668 MVT::ValueType PairTy = Node->getValueType(0); 2669 // TODO: handle the case where the Lo and Hi operands are not of legal type 2670 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2671 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2672 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2673 case TargetLowering::Promote: 2674 case TargetLowering::Custom: 2675 assert(0 && "Cannot promote/custom this yet!"); 2676 case TargetLowering::Legal: 2677 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2678 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2679 break; 2680 case TargetLowering::Expand: 2681 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2682 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2683 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2684 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2685 TLI.getShiftAmountTy())); 2686 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2687 break; 2688 } 2689 break; 2690 } 2691 2692 case ISD::UREM: 2693 case ISD::SREM: 2694 case ISD::FREM: 2695 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2696 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2697 2698 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2699 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2700 case TargetLowering::Custom: 2701 isCustom = true; 2702 // FALLTHROUGH 2703 case TargetLowering::Legal: 2704 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2705 if (isCustom) { 2706 Tmp1 = TLI.LowerOperation(Result, DAG); 2707 if (Tmp1.Val) Result = Tmp1; 2708 } 2709 break; 2710 case TargetLowering::Expand: 2711 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2712 bool isSigned = DivOpc == ISD::SDIV; 2713 if (MVT::isInteger(Node->getValueType(0))) { 2714 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) == 2715 TargetLowering::Legal) { 2716 // X % Y -> X-X/Y*Y 2717 MVT::ValueType VT = Node->getValueType(0); 2718 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 2719 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2720 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2721 } else { 2722 assert(Node->getValueType(0) == MVT::i32 && 2723 "Cannot expand this binary operator!"); 2724 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 2725 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 2726 SDOperand Dummy; 2727 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2728 } 2729 } else { 2730 // Floating point mod -> fmod libcall. 2731 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32 2732 ? RTLIB::REM_F32 : RTLIB::REM_F64; 2733 SDOperand Dummy; 2734 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2735 false/*sign irrelevant*/, Dummy); 2736 } 2737 break; 2738 } 2739 break; 2740 case ISD::VAARG: { 2741 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2742 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2743 2744 MVT::ValueType VT = Node->getValueType(0); 2745 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2746 default: assert(0 && "This action is not supported yet!"); 2747 case TargetLowering::Custom: 2748 isCustom = true; 2749 // FALLTHROUGH 2750 case TargetLowering::Legal: 2751 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2752 Result = Result.getValue(0); 2753 Tmp1 = Result.getValue(1); 2754 2755 if (isCustom) { 2756 Tmp2 = TLI.LowerOperation(Result, DAG); 2757 if (Tmp2.Val) { 2758 Result = LegalizeOp(Tmp2); 2759 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 2760 } 2761 } 2762 break; 2763 case TargetLowering::Expand: { 2764 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 2765 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2766 SV->getValue(), SV->getOffset()); 2767 // Increment the pointer, VAList, to the next vaarg 2768 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2769 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2770 TLI.getPointerTy())); 2771 // Store the incremented VAList to the legalized pointer 2772 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 2773 SV->getOffset()); 2774 // Load the actual argument out of the pointer VAList 2775 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 2776 Tmp1 = LegalizeOp(Result.getValue(1)); 2777 Result = LegalizeOp(Result); 2778 break; 2779 } 2780 } 2781 // Since VAARG produces two values, make sure to remember that we 2782 // legalized both of them. 2783 AddLegalizedOperand(SDOperand(Node, 0), Result); 2784 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 2785 return Op.ResNo ? Tmp1 : Result; 2786 } 2787 2788 case ISD::VACOPY: 2789 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2790 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 2791 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 2792 2793 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 2794 default: assert(0 && "This action is not supported yet!"); 2795 case TargetLowering::Custom: 2796 isCustom = true; 2797 // FALLTHROUGH 2798 case TargetLowering::Legal: 2799 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 2800 Node->getOperand(3), Node->getOperand(4)); 2801 if (isCustom) { 2802 Tmp1 = TLI.LowerOperation(Result, DAG); 2803 if (Tmp1.Val) Result = Tmp1; 2804 } 2805 break; 2806 case TargetLowering::Expand: 2807 // This defaults to loading a pointer from the input and storing it to the 2808 // output, returning the chain. 2809 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); 2810 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); 2811 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), 2812 SVD->getOffset()); 2813 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), 2814 SVS->getOffset()); 2815 break; 2816 } 2817 break; 2818 2819 case ISD::VAEND: 2820 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2821 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2822 2823 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 2824 default: assert(0 && "This action is not supported yet!"); 2825 case TargetLowering::Custom: 2826 isCustom = true; 2827 // FALLTHROUGH 2828 case TargetLowering::Legal: 2829 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2830 if (isCustom) { 2831 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 2832 if (Tmp1.Val) Result = Tmp1; 2833 } 2834 break; 2835 case TargetLowering::Expand: 2836 Result = Tmp1; // Default to a no-op, return the chain 2837 break; 2838 } 2839 break; 2840 2841 case ISD::VASTART: 2842 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2843 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2844 2845 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2846 2847 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 2848 default: assert(0 && "This action is not supported yet!"); 2849 case TargetLowering::Legal: break; 2850 case TargetLowering::Custom: 2851 Tmp1 = TLI.LowerOperation(Result, DAG); 2852 if (Tmp1.Val) Result = Tmp1; 2853 break; 2854 } 2855 break; 2856 2857 case ISD::ROTL: 2858 case ISD::ROTR: 2859 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2860 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2861 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2862 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2863 default: 2864 assert(0 && "ROTL/ROTR legalize operation not supported"); 2865 break; 2866 case TargetLowering::Legal: 2867 break; 2868 case TargetLowering::Custom: 2869 Tmp1 = TLI.LowerOperation(Result, DAG); 2870 if (Tmp1.Val) Result = Tmp1; 2871 break; 2872 case TargetLowering::Promote: 2873 assert(0 && "Do not know how to promote ROTL/ROTR"); 2874 break; 2875 case TargetLowering::Expand: 2876 assert(0 && "Do not know how to expand ROTL/ROTR"); 2877 break; 2878 } 2879 break; 2880 2881 case ISD::BSWAP: 2882 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2883 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2884 case TargetLowering::Custom: 2885 assert(0 && "Cannot custom legalize this yet!"); 2886 case TargetLowering::Legal: 2887 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2888 break; 2889 case TargetLowering::Promote: { 2890 MVT::ValueType OVT = Tmp1.getValueType(); 2891 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2892 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); 2893 2894 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2895 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 2896 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 2897 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 2898 break; 2899 } 2900 case TargetLowering::Expand: 2901 Result = ExpandBSWAP(Tmp1); 2902 break; 2903 } 2904 break; 2905 2906 case ISD::CTPOP: 2907 case ISD::CTTZ: 2908 case ISD::CTLZ: 2909 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2910 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2911 case TargetLowering::Custom: 2912 case TargetLowering::Legal: 2913 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2914 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 2915 TargetLowering::Custom) { 2916 Tmp1 = TLI.LowerOperation(Result, DAG); 2917 if (Tmp1.Val) { 2918 Result = Tmp1; 2919 } 2920 } 2921 break; 2922 case TargetLowering::Promote: { 2923 MVT::ValueType OVT = Tmp1.getValueType(); 2924 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2925 2926 // Zero extend the argument. 2927 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2928 // Perform the larger operation, then subtract if needed. 2929 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2930 switch (Node->getOpcode()) { 2931 case ISD::CTPOP: 2932 Result = Tmp1; 2933 break; 2934 case ISD::CTTZ: 2935 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2936 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2937 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 2938 ISD::SETEQ); 2939 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2940 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); 2941 break; 2942 case ISD::CTLZ: 2943 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2944 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2945 DAG.getConstant(MVT::getSizeInBits(NVT) - 2946 MVT::getSizeInBits(OVT), NVT)); 2947 break; 2948 } 2949 break; 2950 } 2951 case TargetLowering::Expand: 2952 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 2953 break; 2954 } 2955 break; 2956 2957 // Unary operators 2958 case ISD::FABS: 2959 case ISD::FNEG: 2960 case ISD::FSQRT: 2961 case ISD::FSIN: 2962 case ISD::FCOS: 2963 Tmp1 = LegalizeOp(Node->getOperand(0)); 2964 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2965 case TargetLowering::Promote: 2966 case TargetLowering::Custom: 2967 isCustom = true; 2968 // FALLTHROUGH 2969 case TargetLowering::Legal: 2970 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2971 if (isCustom) { 2972 Tmp1 = TLI.LowerOperation(Result, DAG); 2973 if (Tmp1.Val) Result = Tmp1; 2974 } 2975 break; 2976 case TargetLowering::Expand: 2977 switch (Node->getOpcode()) { 2978 default: assert(0 && "Unreachable!"); 2979 case ISD::FNEG: 2980 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2981 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2982 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 2983 break; 2984 case ISD::FABS: { 2985 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2986 MVT::ValueType VT = Node->getValueType(0); 2987 Tmp2 = DAG.getConstantFP(0.0, VT); 2988 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2989 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2990 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2991 break; 2992 } 2993 case ISD::FSQRT: 2994 case ISD::FSIN: 2995 case ISD::FCOS: { 2996 MVT::ValueType VT = Node->getValueType(0); 2997 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2998 switch(Node->getOpcode()) { 2999 case ISD::FSQRT: 3000 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64; 3001 break; 3002 case ISD::FSIN: 3003 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 3004 break; 3005 case ISD::FCOS: 3006 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64; 3007 break; 3008 default: assert(0 && "Unreachable!"); 3009 } 3010 SDOperand Dummy; 3011 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3012 false/*sign irrelevant*/, Dummy); 3013 break; 3014 } 3015 } 3016 break; 3017 } 3018 break; 3019 case ISD::FPOWI: { 3020 // We always lower FPOWI into a libcall. No target support it yet. 3021 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32 3022 ? RTLIB::POWI_F32 : RTLIB::POWI_F64; 3023 SDOperand Dummy; 3024 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3025 false/*sign irrelevant*/, Dummy); 3026 break; 3027 } 3028 case ISD::BIT_CONVERT: 3029 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3030 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3031 } else if (MVT::isVector(Op.getOperand(0).getValueType())) { 3032 // The input has to be a vector type, we have to either scalarize it, pack 3033 // it, or convert it based on whether the input vector type is legal. 3034 SDNode *InVal = Node->getOperand(0).Val; 3035 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0)); 3036 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0)); 3037 3038 // Figure out if there is a simple type corresponding to this Vector 3039 // type. If so, convert to the vector type. 3040 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3041 if (TLI.isTypeLegal(TVT)) { 3042 // Turn this into a bit convert of the vector input. 3043 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3044 LegalizeOp(Node->getOperand(0))); 3045 break; 3046 } else if (NumElems == 1) { 3047 // Turn this into a bit convert of the scalar input. 3048 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3049 ScalarizeVectorOp(Node->getOperand(0))); 3050 break; 3051 } else { 3052 // FIXME: UNIMP! Store then reload 3053 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3054 } 3055 } else { 3056 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3057 Node->getOperand(0).getValueType())) { 3058 default: assert(0 && "Unknown operation action!"); 3059 case TargetLowering::Expand: 3060 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3061 break; 3062 case TargetLowering::Legal: 3063 Tmp1 = LegalizeOp(Node->getOperand(0)); 3064 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3065 break; 3066 } 3067 } 3068 break; 3069 3070 // Conversion operators. The source and destination have different types. 3071 case ISD::SINT_TO_FP: 3072 case ISD::UINT_TO_FP: { 3073 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3074 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3075 case Legal: 3076 switch (TLI.getOperationAction(Node->getOpcode(), 3077 Node->getOperand(0).getValueType())) { 3078 default: assert(0 && "Unknown operation action!"); 3079 case TargetLowering::Custom: 3080 isCustom = true; 3081 // FALLTHROUGH 3082 case TargetLowering::Legal: 3083 Tmp1 = LegalizeOp(Node->getOperand(0)); 3084 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3085 if (isCustom) { 3086 Tmp1 = TLI.LowerOperation(Result, DAG); 3087 if (Tmp1.Val) Result = Tmp1; 3088 } 3089 break; 3090 case TargetLowering::Expand: 3091 Result = ExpandLegalINT_TO_FP(isSigned, 3092 LegalizeOp(Node->getOperand(0)), 3093 Node->getValueType(0)); 3094 break; 3095 case TargetLowering::Promote: 3096 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3097 Node->getValueType(0), 3098 isSigned); 3099 break; 3100 } 3101 break; 3102 case Expand: 3103 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3104 Node->getValueType(0), Node->getOperand(0)); 3105 break; 3106 case Promote: 3107 Tmp1 = PromoteOp(Node->getOperand(0)); 3108 if (isSigned) { 3109 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3110 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3111 } else { 3112 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3113 Node->getOperand(0).getValueType()); 3114 } 3115 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3116 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3117 break; 3118 } 3119 break; 3120 } 3121 case ISD::TRUNCATE: 3122 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3123 case Legal: 3124 Tmp1 = LegalizeOp(Node->getOperand(0)); 3125 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3126 break; 3127 case Expand: 3128 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3129 3130 // Since the result is legal, we should just be able to truncate the low 3131 // part of the source. 3132 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3133 break; 3134 case Promote: 3135 Result = PromoteOp(Node->getOperand(0)); 3136 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3137 break; 3138 } 3139 break; 3140 3141 case ISD::FP_TO_SINT: 3142 case ISD::FP_TO_UINT: 3143 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3144 case Legal: 3145 Tmp1 = LegalizeOp(Node->getOperand(0)); 3146 3147 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3148 default: assert(0 && "Unknown operation action!"); 3149 case TargetLowering::Custom: 3150 isCustom = true; 3151 // FALLTHROUGH 3152 case TargetLowering::Legal: 3153 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3154 if (isCustom) { 3155 Tmp1 = TLI.LowerOperation(Result, DAG); 3156 if (Tmp1.Val) Result = Tmp1; 3157 } 3158 break; 3159 case TargetLowering::Promote: 3160 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3161 Node->getOpcode() == ISD::FP_TO_SINT); 3162 break; 3163 case TargetLowering::Expand: 3164 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3165 SDOperand True, False; 3166 MVT::ValueType VT = Node->getOperand(0).getValueType(); 3167 MVT::ValueType NVT = Node->getValueType(0); 3168 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 3169 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 3170 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 3171 Node->getOperand(0), Tmp2, ISD::SETLT); 3172 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3173 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3174 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3175 Tmp2)); 3176 False = DAG.getNode(ISD::XOR, NVT, False, 3177 DAG.getConstant(1ULL << ShiftAmt, NVT)); 3178 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3179 break; 3180 } else { 3181 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3182 } 3183 break; 3184 } 3185 break; 3186 case Expand: { 3187 // Convert f32 / f64 to i32 / i64. 3188 MVT::ValueType VT = Op.getValueType(); 3189 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3190 switch (Node->getOpcode()) { 3191 case ISD::FP_TO_SINT: 3192 if (Node->getOperand(0).getValueType() == MVT::f32) 3193 LC = (VT == MVT::i32) 3194 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3195 else 3196 LC = (VT == MVT::i32) 3197 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3198 break; 3199 case ISD::FP_TO_UINT: 3200 if (Node->getOperand(0).getValueType() == MVT::f32) 3201 LC = (VT == MVT::i32) 3202 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3203 else 3204 LC = (VT == MVT::i32) 3205 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3206 break; 3207 default: assert(0 && "Unreachable!"); 3208 } 3209 SDOperand Dummy; 3210 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3211 false/*sign irrelevant*/, Dummy); 3212 break; 3213 } 3214 case Promote: 3215 Tmp1 = PromoteOp(Node->getOperand(0)); 3216 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3217 Result = LegalizeOp(Result); 3218 break; 3219 } 3220 break; 3221 3222 case ISD::FP_EXTEND: 3223 case ISD::FP_ROUND: { 3224 MVT::ValueType newVT = Op.getValueType(); 3225 MVT::ValueType oldVT = Op.getOperand(0).getValueType(); 3226 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) { 3227 // The only way we can lower this is to turn it into a STORE, 3228 // LOAD pair, targetting a temporary location (a stack slot). 3229 3230 // NOTE: there is a choice here between constantly creating new stack 3231 // slots and always reusing the same one. We currently always create 3232 // new ones, as reuse may inhibit scheduling. 3233 MVT::ValueType slotVT = 3234 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT; 3235 const Type *Ty = MVT::getTypeForValueType(slotVT); 3236 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3237 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3238 MachineFunction &MF = DAG.getMachineFunction(); 3239 int SSFI = 3240 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3241 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3242 if (Node->getOpcode() == ISD::FP_EXTEND) { 3243 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), 3244 StackSlot, NULL, 0); 3245 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT, 3246 Result, StackSlot, NULL, 0, oldVT); 3247 } else { 3248 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3249 StackSlot, NULL, 0, newVT); 3250 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0, newVT); 3251 } 3252 break; 3253 } 3254 } 3255 // FALL THROUGH 3256 case ISD::ANY_EXTEND: 3257 case ISD::ZERO_EXTEND: 3258 case ISD::SIGN_EXTEND: 3259 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3260 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3261 case Legal: 3262 Tmp1 = LegalizeOp(Node->getOperand(0)); 3263 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3264 break; 3265 case Promote: 3266 switch (Node->getOpcode()) { 3267 case ISD::ANY_EXTEND: 3268 Tmp1 = PromoteOp(Node->getOperand(0)); 3269 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3270 break; 3271 case ISD::ZERO_EXTEND: 3272 Result = PromoteOp(Node->getOperand(0)); 3273 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3274 Result = DAG.getZeroExtendInReg(Result, 3275 Node->getOperand(0).getValueType()); 3276 break; 3277 case ISD::SIGN_EXTEND: 3278 Result = PromoteOp(Node->getOperand(0)); 3279 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3280 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3281 Result, 3282 DAG.getValueType(Node->getOperand(0).getValueType())); 3283 break; 3284 case ISD::FP_EXTEND: 3285 Result = PromoteOp(Node->getOperand(0)); 3286 if (Result.getValueType() != Op.getValueType()) 3287 // Dynamically dead while we have only 2 FP types. 3288 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 3289 break; 3290 case ISD::FP_ROUND: 3291 Result = PromoteOp(Node->getOperand(0)); 3292 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 3293 break; 3294 } 3295 } 3296 break; 3297 case ISD::FP_ROUND_INREG: 3298 case ISD::SIGN_EXTEND_INREG: { 3299 Tmp1 = LegalizeOp(Node->getOperand(0)); 3300 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3301 3302 // If this operation is not supported, convert it to a shl/shr or load/store 3303 // pair. 3304 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3305 default: assert(0 && "This action not supported for this op yet!"); 3306 case TargetLowering::Legal: 3307 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3308 break; 3309 case TargetLowering::Expand: 3310 // If this is an integer extend and shifts are supported, do that. 3311 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3312 // NOTE: we could fall back on load/store here too for targets without 3313 // SAR. However, it is doubtful that any exist. 3314 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3315 MVT::getSizeInBits(ExtraVT); 3316 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3317 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3318 Node->getOperand(0), ShiftCst); 3319 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3320 Result, ShiftCst); 3321 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3322 // The only way we can lower this is to turn it into a TRUNCSTORE, 3323 // EXTLOAD pair, targetting a temporary location (a stack slot). 3324 3325 // NOTE: there is a choice here between constantly creating new stack 3326 // slots and always reusing the same one. We currently always create 3327 // new ones, as reuse may inhibit scheduling. 3328 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 3329 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3330 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3331 MachineFunction &MF = DAG.getMachineFunction(); 3332 int SSFI = 3333 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3334 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3335 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3336 StackSlot, NULL, 0, ExtraVT); 3337 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 3338 Result, StackSlot, NULL, 0, ExtraVT); 3339 } else { 3340 assert(0 && "Unknown op"); 3341 } 3342 break; 3343 } 3344 break; 3345 } 3346 case ISD::ADJUST_TRAMP: { 3347 Tmp1 = LegalizeOp(Node->getOperand(0)); 3348 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3349 default: assert(0 && "This action is not supported yet!"); 3350 case TargetLowering::Custom: 3351 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3352 Result = TLI.LowerOperation(Result, DAG); 3353 if (Result.Val) break; 3354 // FALL THROUGH 3355 case TargetLowering::Expand: 3356 Result = Tmp1; 3357 break; 3358 } 3359 break; 3360 } 3361 case ISD::TRAMPOLINE: { 3362 SDOperand Ops[6]; 3363 for (unsigned i = 0; i != 6; ++i) 3364 Ops[i] = LegalizeOp(Node->getOperand(i)); 3365 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3366 // The only option for this node is to custom lower it. 3367 Result = TLI.LowerOperation(Result, DAG); 3368 assert(Result.Val && "Should always custom lower!"); 3369 break; 3370 } 3371 } 3372 3373 assert(Result.getValueType() == Op.getValueType() && 3374 "Bad legalization!"); 3375 3376 // Make sure that the generated code is itself legal. 3377 if (Result != Op) 3378 Result = LegalizeOp(Result); 3379 3380 // Note that LegalizeOp may be reentered even from single-use nodes, which 3381 // means that we always must cache transformed nodes. 3382 AddLegalizedOperand(Op, Result); 3383 return Result; 3384} 3385 3386/// PromoteOp - Given an operation that produces a value in an invalid type, 3387/// promote it to compute the value into a larger type. The produced value will 3388/// have the correct bits for the low portion of the register, but no guarantee 3389/// is made about the top bits: it may be zero, sign-extended, or garbage. 3390SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 3391 MVT::ValueType VT = Op.getValueType(); 3392 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3393 assert(getTypeAction(VT) == Promote && 3394 "Caller should expand or legalize operands that are not promotable!"); 3395 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 3396 "Cannot promote to smaller type!"); 3397 3398 SDOperand Tmp1, Tmp2, Tmp3; 3399 SDOperand Result; 3400 SDNode *Node = Op.Val; 3401 3402 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 3403 if (I != PromotedNodes.end()) return I->second; 3404 3405 switch (Node->getOpcode()) { 3406 case ISD::CopyFromReg: 3407 assert(0 && "CopyFromReg must be legal!"); 3408 default: 3409#ifndef NDEBUG 3410 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 3411#endif 3412 assert(0 && "Do not know how to promote this operator!"); 3413 abort(); 3414 case ISD::UNDEF: 3415 Result = DAG.getNode(ISD::UNDEF, NVT); 3416 break; 3417 case ISD::Constant: 3418 if (VT != MVT::i1) 3419 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 3420 else 3421 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 3422 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 3423 break; 3424 case ISD::ConstantFP: 3425 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 3426 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 3427 break; 3428 3429 case ISD::SETCC: 3430 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 3431 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 3432 Node->getOperand(1), Node->getOperand(2)); 3433 break; 3434 3435 case ISD::TRUNCATE: 3436 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3437 case Legal: 3438 Result = LegalizeOp(Node->getOperand(0)); 3439 assert(Result.getValueType() >= NVT && 3440 "This truncation doesn't make sense!"); 3441 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 3442 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 3443 break; 3444 case Promote: 3445 // The truncation is not required, because we don't guarantee anything 3446 // about high bits anyway. 3447 Result = PromoteOp(Node->getOperand(0)); 3448 break; 3449 case Expand: 3450 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3451 // Truncate the low part of the expanded value to the result type 3452 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 3453 } 3454 break; 3455 case ISD::SIGN_EXTEND: 3456 case ISD::ZERO_EXTEND: 3457 case ISD::ANY_EXTEND: 3458 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3459 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 3460 case Legal: 3461 // Input is legal? Just do extend all the way to the larger type. 3462 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3463 break; 3464 case Promote: 3465 // Promote the reg if it's smaller. 3466 Result = PromoteOp(Node->getOperand(0)); 3467 // The high bits are not guaranteed to be anything. Insert an extend. 3468 if (Node->getOpcode() == ISD::SIGN_EXTEND) 3469 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3470 DAG.getValueType(Node->getOperand(0).getValueType())); 3471 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 3472 Result = DAG.getZeroExtendInReg(Result, 3473 Node->getOperand(0).getValueType()); 3474 break; 3475 } 3476 break; 3477 case ISD::BIT_CONVERT: 3478 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3479 Result = PromoteOp(Result); 3480 break; 3481 3482 case ISD::FP_EXTEND: 3483 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 3484 case ISD::FP_ROUND: 3485 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3486 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 3487 case Promote: assert(0 && "Unreachable with 2 FP types!"); 3488 case Legal: 3489 // Input is legal? Do an FP_ROUND_INREG. 3490 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 3491 DAG.getValueType(VT)); 3492 break; 3493 } 3494 break; 3495 3496 case ISD::SINT_TO_FP: 3497 case ISD::UINT_TO_FP: 3498 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3499 case Legal: 3500 // No extra round required here. 3501 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3502 break; 3503 3504 case Promote: 3505 Result = PromoteOp(Node->getOperand(0)); 3506 if (Node->getOpcode() == ISD::SINT_TO_FP) 3507 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3508 Result, 3509 DAG.getValueType(Node->getOperand(0).getValueType())); 3510 else 3511 Result = DAG.getZeroExtendInReg(Result, 3512 Node->getOperand(0).getValueType()); 3513 // No extra round required here. 3514 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3515 break; 3516 case Expand: 3517 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3518 Node->getOperand(0)); 3519 // Round if we cannot tolerate excess precision. 3520 if (NoExcessFPPrecision) 3521 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3522 DAG.getValueType(VT)); 3523 break; 3524 } 3525 break; 3526 3527 case ISD::SIGN_EXTEND_INREG: 3528 Result = PromoteOp(Node->getOperand(0)); 3529 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3530 Node->getOperand(1)); 3531 break; 3532 case ISD::FP_TO_SINT: 3533 case ISD::FP_TO_UINT: 3534 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3535 case Legal: 3536 case Expand: 3537 Tmp1 = Node->getOperand(0); 3538 break; 3539 case Promote: 3540 // The input result is prerounded, so we don't have to do anything 3541 // special. 3542 Tmp1 = PromoteOp(Node->getOperand(0)); 3543 break; 3544 } 3545 // If we're promoting a UINT to a larger size, check to see if the new node 3546 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3547 // we can use that instead. This allows us to generate better code for 3548 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3549 // legal, such as PowerPC. 3550 if (Node->getOpcode() == ISD::FP_TO_UINT && 3551 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3552 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3553 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3554 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3555 } else { 3556 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3557 } 3558 break; 3559 3560 case ISD::FABS: 3561 case ISD::FNEG: 3562 Tmp1 = PromoteOp(Node->getOperand(0)); 3563 assert(Tmp1.getValueType() == NVT); 3564 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3565 // NOTE: we do not have to do any extra rounding here for 3566 // NoExcessFPPrecision, because we know the input will have the appropriate 3567 // precision, and these operations don't modify precision at all. 3568 break; 3569 3570 case ISD::FSQRT: 3571 case ISD::FSIN: 3572 case ISD::FCOS: 3573 Tmp1 = PromoteOp(Node->getOperand(0)); 3574 assert(Tmp1.getValueType() == NVT); 3575 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3576 if (NoExcessFPPrecision) 3577 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3578 DAG.getValueType(VT)); 3579 break; 3580 3581 case ISD::FPOWI: { 3582 // Promote f32 powi to f64 powi. Note that this could insert a libcall 3583 // directly as well, which may be better. 3584 Tmp1 = PromoteOp(Node->getOperand(0)); 3585 assert(Tmp1.getValueType() == NVT); 3586 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 3587 if (NoExcessFPPrecision) 3588 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3589 DAG.getValueType(VT)); 3590 break; 3591 } 3592 3593 case ISD::AND: 3594 case ISD::OR: 3595 case ISD::XOR: 3596 case ISD::ADD: 3597 case ISD::SUB: 3598 case ISD::MUL: 3599 // The input may have strange things in the top bits of the registers, but 3600 // these operations don't care. They may have weird bits going out, but 3601 // that too is okay if they are integer operations. 3602 Tmp1 = PromoteOp(Node->getOperand(0)); 3603 Tmp2 = PromoteOp(Node->getOperand(1)); 3604 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3605 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3606 break; 3607 case ISD::FADD: 3608 case ISD::FSUB: 3609 case ISD::FMUL: 3610 Tmp1 = PromoteOp(Node->getOperand(0)); 3611 Tmp2 = PromoteOp(Node->getOperand(1)); 3612 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3613 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3614 3615 // Floating point operations will give excess precision that we may not be 3616 // able to tolerate. If we DO allow excess precision, just leave it, 3617 // otherwise excise it. 3618 // FIXME: Why would we need to round FP ops more than integer ones? 3619 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3620 if (NoExcessFPPrecision) 3621 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3622 DAG.getValueType(VT)); 3623 break; 3624 3625 case ISD::SDIV: 3626 case ISD::SREM: 3627 // These operators require that their input be sign extended. 3628 Tmp1 = PromoteOp(Node->getOperand(0)); 3629 Tmp2 = PromoteOp(Node->getOperand(1)); 3630 if (MVT::isInteger(NVT)) { 3631 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3632 DAG.getValueType(VT)); 3633 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3634 DAG.getValueType(VT)); 3635 } 3636 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3637 3638 // Perform FP_ROUND: this is probably overly pessimistic. 3639 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 3640 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3641 DAG.getValueType(VT)); 3642 break; 3643 case ISD::FDIV: 3644 case ISD::FREM: 3645 case ISD::FCOPYSIGN: 3646 // These operators require that their input be fp extended. 3647 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3648 case Legal: 3649 Tmp1 = LegalizeOp(Node->getOperand(0)); 3650 break; 3651 case Promote: 3652 Tmp1 = PromoteOp(Node->getOperand(0)); 3653 break; 3654 case Expand: 3655 assert(0 && "not implemented"); 3656 } 3657 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3658 case Legal: 3659 Tmp2 = LegalizeOp(Node->getOperand(1)); 3660 break; 3661 case Promote: 3662 Tmp2 = PromoteOp(Node->getOperand(1)); 3663 break; 3664 case Expand: 3665 assert(0 && "not implemented"); 3666 } 3667 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3668 3669 // Perform FP_ROUND: this is probably overly pessimistic. 3670 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 3671 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3672 DAG.getValueType(VT)); 3673 break; 3674 3675 case ISD::UDIV: 3676 case ISD::UREM: 3677 // These operators require that their input be zero extended. 3678 Tmp1 = PromoteOp(Node->getOperand(0)); 3679 Tmp2 = PromoteOp(Node->getOperand(1)); 3680 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 3681 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3682 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3683 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3684 break; 3685 3686 case ISD::SHL: 3687 Tmp1 = PromoteOp(Node->getOperand(0)); 3688 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 3689 break; 3690 case ISD::SRA: 3691 // The input value must be properly sign extended. 3692 Tmp1 = PromoteOp(Node->getOperand(0)); 3693 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3694 DAG.getValueType(VT)); 3695 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 3696 break; 3697 case ISD::SRL: 3698 // The input value must be properly zero extended. 3699 Tmp1 = PromoteOp(Node->getOperand(0)); 3700 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3701 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 3702 break; 3703 3704 case ISD::VAARG: 3705 Tmp1 = Node->getOperand(0); // Get the chain. 3706 Tmp2 = Node->getOperand(1); // Get the pointer. 3707 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 3708 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 3709 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 3710 } else { 3711 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 3712 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3713 SV->getValue(), SV->getOffset()); 3714 // Increment the pointer, VAList, to the next vaarg 3715 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3716 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3717 TLI.getPointerTy())); 3718 // Store the incremented VAList to the legalized pointer 3719 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 3720 SV->getOffset()); 3721 // Load the actual argument out of the pointer VAList 3722 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 3723 } 3724 // Remember that we legalized the chain. 3725 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3726 break; 3727 3728 case ISD::LOAD: { 3729 LoadSDNode *LD = cast<LoadSDNode>(Node); 3730 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 3731 ? ISD::EXTLOAD : LD->getExtensionType(); 3732 Result = DAG.getExtLoad(ExtType, NVT, 3733 LD->getChain(), LD->getBasePtr(), 3734 LD->getSrcValue(), LD->getSrcValueOffset(), 3735 LD->getLoadedVT(), 3736 LD->isVolatile(), 3737 LD->getAlignment()); 3738 // Remember that we legalized the chain. 3739 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3740 break; 3741 } 3742 case ISD::SELECT: 3743 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 3744 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 3745 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 3746 break; 3747 case ISD::SELECT_CC: 3748 Tmp2 = PromoteOp(Node->getOperand(2)); // True 3749 Tmp3 = PromoteOp(Node->getOperand(3)); // False 3750 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3751 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 3752 break; 3753 case ISD::BSWAP: 3754 Tmp1 = Node->getOperand(0); 3755 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3756 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3757 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3758 DAG.getConstant(MVT::getSizeInBits(NVT) - 3759 MVT::getSizeInBits(VT), 3760 TLI.getShiftAmountTy())); 3761 break; 3762 case ISD::CTPOP: 3763 case ISD::CTTZ: 3764 case ISD::CTLZ: 3765 // Zero extend the argument 3766 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 3767 // Perform the larger operation, then subtract if needed. 3768 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3769 switch(Node->getOpcode()) { 3770 case ISD::CTPOP: 3771 Result = Tmp1; 3772 break; 3773 case ISD::CTTZ: 3774 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3775 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3776 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 3777 ISD::SETEQ); 3778 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3779 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); 3780 break; 3781 case ISD::CTLZ: 3782 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3783 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3784 DAG.getConstant(MVT::getSizeInBits(NVT) - 3785 MVT::getSizeInBits(VT), NVT)); 3786 break; 3787 } 3788 break; 3789 case ISD::EXTRACT_SUBVECTOR: 3790 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 3791 break; 3792 case ISD::EXTRACT_VECTOR_ELT: 3793 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 3794 break; 3795 } 3796 3797 assert(Result.Val && "Didn't set a result!"); 3798 3799 // Make sure the result is itself legal. 3800 Result = LegalizeOp(Result); 3801 3802 // Remember that we promoted this! 3803 AddPromotedOperand(Op, Result); 3804 return Result; 3805} 3806 3807/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 3808/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 3809/// based on the vector type. The return type of this matches the element type 3810/// of the vector, which may not be legal for the target. 3811SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 3812 // We know that operand #0 is the Vec vector. If the index is a constant 3813 // or if the invec is a supported hardware type, we can use it. Otherwise, 3814 // lower to a store then an indexed load. 3815 SDOperand Vec = Op.getOperand(0); 3816 SDOperand Idx = Op.getOperand(1); 3817 3818 SDNode *InVal = Vec.Val; 3819 MVT::ValueType TVT = InVal->getValueType(0); 3820 unsigned NumElems = MVT::getVectorNumElements(TVT); 3821 3822 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 3823 default: assert(0 && "This action is not supported yet!"); 3824 case TargetLowering::Custom: { 3825 Vec = LegalizeOp(Vec); 3826 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3827 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 3828 if (Tmp3.Val) 3829 return Tmp3; 3830 break; 3831 } 3832 case TargetLowering::Legal: 3833 if (isTypeLegal(TVT)) { 3834 Vec = LegalizeOp(Vec); 3835 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3836 return Op; 3837 } 3838 break; 3839 case TargetLowering::Expand: 3840 break; 3841 } 3842 3843 if (NumElems == 1) { 3844 // This must be an access of the only element. Return it. 3845 Op = ScalarizeVectorOp(Vec); 3846 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 3847 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 3848 SDOperand Lo, Hi; 3849 SplitVectorOp(Vec, Lo, Hi); 3850 if (CIdx->getValue() < NumElems/2) { 3851 Vec = Lo; 3852 } else { 3853 Vec = Hi; 3854 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, 3855 Idx.getValueType()); 3856 } 3857 3858 // It's now an extract from the appropriate high or low part. Recurse. 3859 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3860 Op = ExpandEXTRACT_VECTOR_ELT(Op); 3861 } else { 3862 // Store the value to a temporary stack slot, then LOAD the scalar 3863 // element back out. 3864 SDOperand StackPtr = CreateStackTemporary(Vec.getValueType()); 3865 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 3866 3867 // Add the offset to the index. 3868 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 3869 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 3870 DAG.getConstant(EltSize, Idx.getValueType())); 3871 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 3872 3873 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 3874 } 3875 return Op; 3876} 3877 3878/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 3879/// we assume the operation can be split if it is not already legal. 3880SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 3881 // We know that operand #0 is the Vec vector. For now we assume the index 3882 // is a constant and that the extracted result is a supported hardware type. 3883 SDOperand Vec = Op.getOperand(0); 3884 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 3885 3886 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); 3887 3888 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { 3889 // This must be an access of the desired vector length. Return it. 3890 return Vec; 3891 } 3892 3893 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 3894 SDOperand Lo, Hi; 3895 SplitVectorOp(Vec, Lo, Hi); 3896 if (CIdx->getValue() < NumElems/2) { 3897 Vec = Lo; 3898 } else { 3899 Vec = Hi; 3900 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 3901 } 3902 3903 // It's now an extract from the appropriate high or low part. Recurse. 3904 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3905 return ExpandEXTRACT_SUBVECTOR(Op); 3906} 3907 3908/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 3909/// with condition CC on the current target. This usually involves legalizing 3910/// or promoting the arguments. In the case where LHS and RHS must be expanded, 3911/// there may be no choice but to create a new SetCC node to represent the 3912/// legalized value of setcc lhs, rhs. In this case, the value is returned in 3913/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 3914void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 3915 SDOperand &RHS, 3916 SDOperand &CC) { 3917 SDOperand Tmp1, Tmp2, Result; 3918 3919 switch (getTypeAction(LHS.getValueType())) { 3920 case Legal: 3921 Tmp1 = LegalizeOp(LHS); // LHS 3922 Tmp2 = LegalizeOp(RHS); // RHS 3923 break; 3924 case Promote: 3925 Tmp1 = PromoteOp(LHS); // LHS 3926 Tmp2 = PromoteOp(RHS); // RHS 3927 3928 // If this is an FP compare, the operands have already been extended. 3929 if (MVT::isInteger(LHS.getValueType())) { 3930 MVT::ValueType VT = LHS.getValueType(); 3931 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3932 3933 // Otherwise, we have to insert explicit sign or zero extends. Note 3934 // that we could insert sign extends for ALL conditions, but zero extend 3935 // is cheaper on many machines (an AND instead of two shifts), so prefer 3936 // it. 3937 switch (cast<CondCodeSDNode>(CC)->get()) { 3938 default: assert(0 && "Unknown integer comparison!"); 3939 case ISD::SETEQ: 3940 case ISD::SETNE: 3941 case ISD::SETUGE: 3942 case ISD::SETUGT: 3943 case ISD::SETULE: 3944 case ISD::SETULT: 3945 // ALL of these operations will work if we either sign or zero extend 3946 // the operands (including the unsigned comparisons!). Zero extend is 3947 // usually a simpler/cheaper operation, so prefer it. 3948 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3949 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3950 break; 3951 case ISD::SETGE: 3952 case ISD::SETGT: 3953 case ISD::SETLT: 3954 case ISD::SETLE: 3955 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3956 DAG.getValueType(VT)); 3957 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3958 DAG.getValueType(VT)); 3959 break; 3960 } 3961 } 3962 break; 3963 case Expand: { 3964 MVT::ValueType VT = LHS.getValueType(); 3965 if (VT == MVT::f32 || VT == MVT::f64) { 3966 // Expand into one or more soft-fp libcall(s). 3967 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 3968 switch (cast<CondCodeSDNode>(CC)->get()) { 3969 case ISD::SETEQ: 3970 case ISD::SETOEQ: 3971 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 3972 break; 3973 case ISD::SETNE: 3974 case ISD::SETUNE: 3975 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 3976 break; 3977 case ISD::SETGE: 3978 case ISD::SETOGE: 3979 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 3980 break; 3981 case ISD::SETLT: 3982 case ISD::SETOLT: 3983 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3984 break; 3985 case ISD::SETLE: 3986 case ISD::SETOLE: 3987 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 3988 break; 3989 case ISD::SETGT: 3990 case ISD::SETOGT: 3991 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 3992 break; 3993 case ISD::SETUO: 3994 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 3995 break; 3996 case ISD::SETO: 3997 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 3998 break; 3999 default: 4000 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4001 switch (cast<CondCodeSDNode>(CC)->get()) { 4002 case ISD::SETONE: 4003 // SETONE = SETOLT | SETOGT 4004 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4005 // Fallthrough 4006 case ISD::SETUGT: 4007 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4008 break; 4009 case ISD::SETUGE: 4010 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4011 break; 4012 case ISD::SETULT: 4013 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4014 break; 4015 case ISD::SETULE: 4016 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4017 break; 4018 case ISD::SETUEQ: 4019 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4020 break; 4021 default: assert(0 && "Unsupported FP setcc!"); 4022 } 4023 } 4024 4025 SDOperand Dummy; 4026 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 4027 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4028 false /*sign irrelevant*/, Dummy); 4029 Tmp2 = DAG.getConstant(0, MVT::i32); 4030 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4031 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4032 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); 4033 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 4034 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4035 false /*sign irrelevant*/, Dummy); 4036 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, 4037 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4038 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4039 Tmp2 = SDOperand(); 4040 } 4041 LHS = Tmp1; 4042 RHS = Tmp2; 4043 return; 4044 } 4045 4046 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4047 ExpandOp(LHS, LHSLo, LHSHi); 4048 ExpandOp(RHS, RHSLo, RHSHi); 4049 switch (cast<CondCodeSDNode>(CC)->get()) { 4050 case ISD::SETEQ: 4051 case ISD::SETNE: 4052 if (RHSLo == RHSHi) 4053 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4054 if (RHSCST->isAllOnesValue()) { 4055 // Comparison to -1. 4056 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4057 Tmp2 = RHSLo; 4058 break; 4059 } 4060 4061 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4062 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4063 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4064 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4065 break; 4066 default: 4067 // If this is a comparison of the sign bit, just look at the top part. 4068 // X > -1, x < 0 4069 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4070 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4071 CST->getValue() == 0) || // X < 0 4072 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4073 CST->isAllOnesValue())) { // X > -1 4074 Tmp1 = LHSHi; 4075 Tmp2 = RHSHi; 4076 break; 4077 } 4078 4079 // FIXME: This generated code sucks. 4080 ISD::CondCode LowCC; 4081 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4082 switch (CCCode) { 4083 default: assert(0 && "Unknown integer setcc!"); 4084 case ISD::SETLT: 4085 case ISD::SETULT: LowCC = ISD::SETULT; break; 4086 case ISD::SETGT: 4087 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4088 case ISD::SETLE: 4089 case ISD::SETULE: LowCC = ISD::SETULE; break; 4090 case ISD::SETGE: 4091 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4092 } 4093 4094 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4095 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4096 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4097 4098 // NOTE: on targets without efficient SELECT of bools, we can always use 4099 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4100 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4101 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, 4102 false, DagCombineInfo); 4103 if (!Tmp1.Val) 4104 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 4105 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4106 CCCode, false, DagCombineInfo); 4107 if (!Tmp2.Val) 4108 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC); 4109 4110 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4111 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4112 if ((Tmp1C && Tmp1C->getValue() == 0) || 4113 (Tmp2C && Tmp2C->getValue() == 0 && 4114 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4115 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4116 (Tmp2C && Tmp2C->getValue() == 1 && 4117 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4118 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4119 // low part is known false, returns high part. 4120 // For LE / GE, if high part is known false, ignore the low part. 4121 // For LT / GT, if high part is known true, ignore the low part. 4122 Tmp1 = Tmp2; 4123 Tmp2 = SDOperand(); 4124 } else { 4125 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4126 ISD::SETEQ, false, DagCombineInfo); 4127 if (!Result.Val) 4128 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4129 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4130 Result, Tmp1, Tmp2)); 4131 Tmp1 = Result; 4132 Tmp2 = SDOperand(); 4133 } 4134 } 4135 } 4136 } 4137 LHS = Tmp1; 4138 RHS = Tmp2; 4139} 4140 4141/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 4142/// The resultant code need not be legal. Note that SrcOp is the input operand 4143/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 4144SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 4145 SDOperand SrcOp) { 4146 // Create the stack frame object. 4147 SDOperand FIPtr = CreateStackTemporary(DestVT); 4148 4149 // Emit a store to the stack slot. 4150 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); 4151 // Result is a load from the stack slot. 4152 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4153} 4154 4155SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4156 // Create a vector sized/aligned stack slot, store the value to element #0, 4157 // then load the whole vector back out. 4158 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); 4159 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4160 NULL, 0); 4161 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); 4162} 4163 4164 4165/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4166/// support the operation, but do support the resultant vector type. 4167SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4168 4169 // If the only non-undef value is the low element, turn this into a 4170 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4171 unsigned NumElems = Node->getNumOperands(); 4172 bool isOnlyLowElement = true; 4173 SDOperand SplatValue = Node->getOperand(0); 4174 std::map<SDOperand, std::vector<unsigned> > Values; 4175 Values[SplatValue].push_back(0); 4176 bool isConstant = true; 4177 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4178 SplatValue.getOpcode() != ISD::UNDEF) 4179 isConstant = false; 4180 4181 for (unsigned i = 1; i < NumElems; ++i) { 4182 SDOperand V = Node->getOperand(i); 4183 Values[V].push_back(i); 4184 if (V.getOpcode() != ISD::UNDEF) 4185 isOnlyLowElement = false; 4186 if (SplatValue != V) 4187 SplatValue = SDOperand(0,0); 4188 4189 // If this isn't a constant element or an undef, we can't use a constant 4190 // pool load. 4191 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4192 V.getOpcode() != ISD::UNDEF) 4193 isConstant = false; 4194 } 4195 4196 if (isOnlyLowElement) { 4197 // If the low element is an undef too, then this whole things is an undef. 4198 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4199 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4200 // Otherwise, turn this into a scalar_to_vector node. 4201 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4202 Node->getOperand(0)); 4203 } 4204 4205 // If all elements are constants, create a load from the constant pool. 4206 if (isConstant) { 4207 MVT::ValueType VT = Node->getValueType(0); 4208 const Type *OpNTy = 4209 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 4210 std::vector<Constant*> CV; 4211 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4212 if (ConstantFPSDNode *V = 4213 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4214 CV.push_back(ConstantFP::get(OpNTy, V->getValue())); 4215 } else if (ConstantSDNode *V = 4216 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4217 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 4218 } else { 4219 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4220 CV.push_back(UndefValue::get(OpNTy)); 4221 } 4222 } 4223 Constant *CP = ConstantVector::get(CV); 4224 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4225 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 4226 } 4227 4228 if (SplatValue.Val) { // Splat of one value? 4229 // Build the shuffle constant vector: <0, 0, 0, 0> 4230 MVT::ValueType MaskVT = 4231 MVT::getIntVectorWithNumElements(NumElems); 4232 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); 4233 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4234 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4235 &ZeroVec[0], ZeroVec.size()); 4236 4237 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4238 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 4239 // Get the splatted value into the low element of a vector register. 4240 SDOperand LowValVec = 4241 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 4242 4243 // Return shuffle(LowValVec, undef, <0,0,0,0>) 4244 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 4245 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 4246 SplatMask); 4247 } 4248 } 4249 4250 // If there are only two unique elements, we may be able to turn this into a 4251 // vector shuffle. 4252 if (Values.size() == 2) { 4253 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 4254 MVT::ValueType MaskVT = 4255 MVT::getIntVectorWithNumElements(NumElems); 4256 std::vector<SDOperand> MaskVec(NumElems); 4257 unsigned i = 0; 4258 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4259 E = Values.end(); I != E; ++I) { 4260 for (std::vector<unsigned>::iterator II = I->second.begin(), 4261 EE = I->second.end(); II != EE; ++II) 4262 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT)); 4263 i += NumElems; 4264 } 4265 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4266 &MaskVec[0], MaskVec.size()); 4267 4268 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4269 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 4270 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 4271 SmallVector<SDOperand, 8> Ops; 4272 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4273 E = Values.end(); I != E; ++I) { 4274 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4275 I->first); 4276 Ops.push_back(Op); 4277 } 4278 Ops.push_back(ShuffleMask); 4279 4280 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 4281 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 4282 &Ops[0], Ops.size()); 4283 } 4284 } 4285 4286 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 4287 // aligned object on the stack, store each element into it, then load 4288 // the result as a vector. 4289 MVT::ValueType VT = Node->getValueType(0); 4290 // Create the stack frame object. 4291 SDOperand FIPtr = CreateStackTemporary(VT); 4292 4293 // Emit a store of each element to the stack slot. 4294 SmallVector<SDOperand, 8> Stores; 4295 unsigned TypeByteSize = 4296 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 4297 // Store (in the right endianness) the elements to memory. 4298 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4299 // Ignore undef elements. 4300 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4301 4302 unsigned Offset = TypeByteSize*i; 4303 4304 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 4305 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 4306 4307 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 4308 NULL, 0)); 4309 } 4310 4311 SDOperand StoreChain; 4312 if (!Stores.empty()) // Not all undef elements? 4313 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4314 &Stores[0], Stores.size()); 4315 else 4316 StoreChain = DAG.getEntryNode(); 4317 4318 // Result is a load from the stack slot. 4319 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 4320} 4321 4322/// CreateStackTemporary - Create a stack temporary, suitable for holding the 4323/// specified value type. 4324SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) { 4325 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4326 unsigned ByteSize = MVT::getSizeInBits(VT)/8; 4327 const Type *Ty = MVT::getTypeForValueType(VT); 4328 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty); 4329 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 4330 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 4331} 4332 4333void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 4334 SDOperand Op, SDOperand Amt, 4335 SDOperand &Lo, SDOperand &Hi) { 4336 // Expand the subcomponents. 4337 SDOperand LHSL, LHSH; 4338 ExpandOp(Op, LHSL, LHSH); 4339 4340 SDOperand Ops[] = { LHSL, LHSH, Amt }; 4341 MVT::ValueType VT = LHSL.getValueType(); 4342 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 4343 Hi = Lo.getValue(1); 4344} 4345 4346 4347/// ExpandShift - Try to find a clever way to expand this shift operation out to 4348/// smaller elements. If we can't find a way that is more efficient than a 4349/// libcall on this target, return false. Otherwise, return true with the 4350/// low-parts expanded into Lo and Hi. 4351bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 4352 SDOperand &Lo, SDOperand &Hi) { 4353 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 4354 "This is not a shift!"); 4355 4356 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 4357 SDOperand ShAmt = LegalizeOp(Amt); 4358 MVT::ValueType ShTy = ShAmt.getValueType(); 4359 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 4360 unsigned NVTBits = MVT::getSizeInBits(NVT); 4361 4362 // Handle the case when Amt is an immediate. Other cases are currently broken 4363 // and are disabled. 4364 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 4365 unsigned Cst = CN->getValue(); 4366 // Expand the incoming operand to be shifted, so that we have its parts 4367 SDOperand InL, InH; 4368 ExpandOp(Op, InL, InH); 4369 switch(Opc) { 4370 case ISD::SHL: 4371 if (Cst > VTBits) { 4372 Lo = DAG.getConstant(0, NVT); 4373 Hi = DAG.getConstant(0, NVT); 4374 } else if (Cst > NVTBits) { 4375 Lo = DAG.getConstant(0, NVT); 4376 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 4377 } else if (Cst == NVTBits) { 4378 Lo = DAG.getConstant(0, NVT); 4379 Hi = InL; 4380 } else { 4381 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 4382 Hi = DAG.getNode(ISD::OR, NVT, 4383 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 4384 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 4385 } 4386 return true; 4387 case ISD::SRL: 4388 if (Cst > VTBits) { 4389 Lo = DAG.getConstant(0, NVT); 4390 Hi = DAG.getConstant(0, NVT); 4391 } else if (Cst > NVTBits) { 4392 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 4393 Hi = DAG.getConstant(0, NVT); 4394 } else if (Cst == NVTBits) { 4395 Lo = InH; 4396 Hi = DAG.getConstant(0, NVT); 4397 } else { 4398 Lo = DAG.getNode(ISD::OR, NVT, 4399 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4400 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4401 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 4402 } 4403 return true; 4404 case ISD::SRA: 4405 if (Cst > VTBits) { 4406 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 4407 DAG.getConstant(NVTBits-1, ShTy)); 4408 } else if (Cst > NVTBits) { 4409 Lo = DAG.getNode(ISD::SRA, NVT, InH, 4410 DAG.getConstant(Cst-NVTBits, ShTy)); 4411 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4412 DAG.getConstant(NVTBits-1, ShTy)); 4413 } else if (Cst == NVTBits) { 4414 Lo = InH; 4415 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4416 DAG.getConstant(NVTBits-1, ShTy)); 4417 } else { 4418 Lo = DAG.getNode(ISD::OR, NVT, 4419 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4420 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4421 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 4422 } 4423 return true; 4424 } 4425 } 4426 4427 // Okay, the shift amount isn't constant. However, if we can tell that it is 4428 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 4429 uint64_t Mask = NVTBits, KnownZero, KnownOne; 4430 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 4431 4432 // If we know that the high bit of the shift amount is one, then we can do 4433 // this as a couple of simple shifts. 4434 if (KnownOne & Mask) { 4435 // Mask out the high bit, which we know is set. 4436 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 4437 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4438 4439 // Expand the incoming operand to be shifted, so that we have its parts 4440 SDOperand InL, InH; 4441 ExpandOp(Op, InL, InH); 4442 switch(Opc) { 4443 case ISD::SHL: 4444 Lo = DAG.getConstant(0, NVT); // Low part is zero. 4445 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 4446 return true; 4447 case ISD::SRL: 4448 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 4449 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 4450 return true; 4451 case ISD::SRA: 4452 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 4453 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4454 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 4455 return true; 4456 } 4457 } 4458 4459 // If we know that the high bit of the shift amount is zero, then we can do 4460 // this as a couple of simple shifts. 4461 if (KnownZero & Mask) { 4462 // Compute 32-amt. 4463 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 4464 DAG.getConstant(NVTBits, Amt.getValueType()), 4465 Amt); 4466 4467 // Expand the incoming operand to be shifted, so that we have its parts 4468 SDOperand InL, InH; 4469 ExpandOp(Op, InL, InH); 4470 switch(Opc) { 4471 case ISD::SHL: 4472 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 4473 Hi = DAG.getNode(ISD::OR, NVT, 4474 DAG.getNode(ISD::SHL, NVT, InH, Amt), 4475 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 4476 return true; 4477 case ISD::SRL: 4478 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 4479 Lo = DAG.getNode(ISD::OR, NVT, 4480 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4481 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4482 return true; 4483 case ISD::SRA: 4484 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 4485 Lo = DAG.getNode(ISD::OR, NVT, 4486 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4487 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4488 return true; 4489 } 4490 } 4491 4492 return false; 4493} 4494 4495 4496// ExpandLibCall - Expand a node into a call to a libcall. If the result value 4497// does not fit into a register, return the lo part and set the hi part to the 4498// by-reg argument. If it does fit into a single register, return the result 4499// and leave the Hi part unset. 4500SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 4501 bool isSigned, SDOperand &Hi) { 4502 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 4503 // The input chain to this libcall is the entry node of the function. 4504 // Legalizing the call will automatically add the previous call to the 4505 // dependence. 4506 SDOperand InChain = DAG.getEntryNode(); 4507 4508 TargetLowering::ArgListTy Args; 4509 TargetLowering::ArgListEntry Entry; 4510 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4511 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 4512 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 4513 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 4514 Entry.isSExt = isSigned; 4515 Args.push_back(Entry); 4516 } 4517 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 4518 4519 // Splice the libcall in wherever FindInputOutputChains tells us to. 4520 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 4521 std::pair<SDOperand,SDOperand> CallInfo = 4522 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false, 4523 Callee, Args, DAG); 4524 4525 // Legalize the call sequence, starting with the chain. This will advance 4526 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 4527 // was added by LowerCallTo (guaranteeing proper serialization of calls). 4528 LegalizeOp(CallInfo.second); 4529 SDOperand Result; 4530 switch (getTypeAction(CallInfo.first.getValueType())) { 4531 default: assert(0 && "Unknown thing"); 4532 case Legal: 4533 Result = CallInfo.first; 4534 break; 4535 case Expand: 4536 ExpandOp(CallInfo.first, Result, Hi); 4537 break; 4538 } 4539 return Result; 4540} 4541 4542 4543/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 4544/// 4545SDOperand SelectionDAGLegalize:: 4546ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 4547 assert(getTypeAction(Source.getValueType()) == Expand && 4548 "This is not an expansion!"); 4549 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 4550 4551 if (!isSigned) { 4552 assert(Source.getValueType() == MVT::i64 && 4553 "This only works for 64-bit -> FP"); 4554 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 4555 // incoming integer is set. To handle this, we dynamically test to see if 4556 // it is set, and, if so, add a fudge factor. 4557 SDOperand Lo, Hi; 4558 ExpandOp(Source, Lo, Hi); 4559 4560 // If this is unsigned, and not supported, first perform the conversion to 4561 // signed, then adjust the result if the sign bit is set. 4562 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 4563 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 4564 4565 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 4566 DAG.getConstant(0, Hi.getValueType()), 4567 ISD::SETLT); 4568 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4569 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4570 SignSet, Four, Zero); 4571 uint64_t FF = 0x5f800000ULL; 4572 if (TLI.isLittleEndian()) FF <<= 32; 4573 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4574 4575 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4576 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4577 SDOperand FudgeInReg; 4578 if (DestTy == MVT::f32) 4579 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4580 else { 4581 assert(DestTy == MVT::f64 && "Unexpected conversion"); 4582 // FIXME: Avoid the extend by construction the right constantpool? 4583 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 4584 CPIdx, NULL, 0, MVT::f32); 4585 } 4586 MVT::ValueType SCVT = SignedConv.getValueType(); 4587 if (SCVT != DestTy) { 4588 // Destination type needs to be expanded as well. The FADD now we are 4589 // constructing will be expanded into a libcall. 4590 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { 4591 assert(SCVT == MVT::i32 && DestTy == MVT::f64); 4592 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, 4593 SignedConv, SignedConv.getValue(1)); 4594 } 4595 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 4596 } 4597 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 4598 } 4599 4600 // Check to see if the target has a custom way to lower this. If so, use it. 4601 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 4602 default: assert(0 && "This action not implemented for this operation!"); 4603 case TargetLowering::Legal: 4604 case TargetLowering::Expand: 4605 break; // This case is handled below. 4606 case TargetLowering::Custom: { 4607 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 4608 Source), DAG); 4609 if (NV.Val) 4610 return LegalizeOp(NV); 4611 break; // The target decided this was legal after all 4612 } 4613 } 4614 4615 // Expand the source, then glue it back together for the call. We must expand 4616 // the source in case it is shared (this pass of legalize must traverse it). 4617 SDOperand SrcLo, SrcHi; 4618 ExpandOp(Source, SrcLo, SrcHi); 4619 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 4620 4621 RTLIB::Libcall LC; 4622 if (DestTy == MVT::f32) 4623 LC = RTLIB::SINTTOFP_I64_F32; 4624 else { 4625 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 4626 LC = RTLIB::SINTTOFP_I64_F64; 4627 } 4628 4629 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 4630 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 4631 SDOperand UnusedHiPart; 4632 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 4633 UnusedHiPart); 4634} 4635 4636/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 4637/// INT_TO_FP operation of the specified operand when the target requests that 4638/// we expand it. At this point, we know that the result and operand types are 4639/// legal for the target. 4640SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 4641 SDOperand Op0, 4642 MVT::ValueType DestVT) { 4643 if (Op0.getValueType() == MVT::i32) { 4644 // simple 32-bit [signed|unsigned] integer to float/double expansion 4645 4646 // get the stack frame index of a 8 byte buffer, pessimistically aligned 4647 MachineFunction &MF = DAG.getMachineFunction(); 4648 const Type *F64Type = MVT::getTypeForValueType(MVT::f64); 4649 unsigned StackAlign = 4650 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type); 4651 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign); 4652 // get address of 8 byte buffer 4653 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4654 // word offset constant for Hi/Lo address computation 4655 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 4656 // set up Hi and Lo (into buffer) address based on endian 4657 SDOperand Hi = StackSlot; 4658 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 4659 if (TLI.isLittleEndian()) 4660 std::swap(Hi, Lo); 4661 4662 // if signed map to unsigned space 4663 SDOperand Op0Mapped; 4664 if (isSigned) { 4665 // constant used to invert sign bit (signed to unsigned mapping) 4666 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 4667 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 4668 } else { 4669 Op0Mapped = Op0; 4670 } 4671 // store the lo of the constructed double - based on integer input 4672 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 4673 Op0Mapped, Lo, NULL, 0); 4674 // initial hi portion of constructed double 4675 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 4676 // store the hi of the constructed double - biased exponent 4677 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 4678 // load the constructed double 4679 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 4680 // FP constant to bias correct the final result 4681 SDOperand Bias = DAG.getConstantFP(isSigned ? 4682 BitsToDouble(0x4330000080000000ULL) 4683 : BitsToDouble(0x4330000000000000ULL), 4684 MVT::f64); 4685 // subtract the bias 4686 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 4687 // final result 4688 SDOperand Result; 4689 // handle final rounding 4690 if (DestVT == MVT::f64) { 4691 // do nothing 4692 Result = Sub; 4693 } else { 4694 // if f32 then cast to f32 4695 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 4696 } 4697 return Result; 4698 } 4699 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 4700 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 4701 4702 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 4703 DAG.getConstant(0, Op0.getValueType()), 4704 ISD::SETLT); 4705 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4706 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4707 SignSet, Four, Zero); 4708 4709 // If the sign bit of the integer is set, the large number will be treated 4710 // as a negative number. To counteract this, the dynamic code adds an 4711 // offset depending on the data type. 4712 uint64_t FF; 4713 switch (Op0.getValueType()) { 4714 default: assert(0 && "Unsupported integer type!"); 4715 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 4716 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 4717 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 4718 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 4719 } 4720 if (TLI.isLittleEndian()) FF <<= 32; 4721 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4722 4723 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4724 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4725 SDOperand FudgeInReg; 4726 if (DestVT == MVT::f32) 4727 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4728 else { 4729 assert(DestVT == MVT::f64 && "Unexpected conversion"); 4730 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 4731 DAG.getEntryNode(), CPIdx, 4732 NULL, 0, MVT::f32)); 4733 } 4734 4735 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 4736} 4737 4738/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 4739/// *INT_TO_FP operation of the specified operand when the target requests that 4740/// we promote it. At this point, we know that the result and operand types are 4741/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 4742/// operation that takes a larger input. 4743SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 4744 MVT::ValueType DestVT, 4745 bool isSigned) { 4746 // First step, figure out the appropriate *INT_TO_FP operation to use. 4747 MVT::ValueType NewInTy = LegalOp.getValueType(); 4748 4749 unsigned OpToUse = 0; 4750 4751 // Scan for the appropriate larger type to use. 4752 while (1) { 4753 NewInTy = (MVT::ValueType)(NewInTy+1); 4754 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 4755 4756 // If the target supports SINT_TO_FP of this type, use it. 4757 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 4758 default: break; 4759 case TargetLowering::Legal: 4760 if (!TLI.isTypeLegal(NewInTy)) 4761 break; // Can't use this datatype. 4762 // FALL THROUGH. 4763 case TargetLowering::Custom: 4764 OpToUse = ISD::SINT_TO_FP; 4765 break; 4766 } 4767 if (OpToUse) break; 4768 if (isSigned) continue; 4769 4770 // If the target supports UINT_TO_FP of this type, use it. 4771 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 4772 default: break; 4773 case TargetLowering::Legal: 4774 if (!TLI.isTypeLegal(NewInTy)) 4775 break; // Can't use this datatype. 4776 // FALL THROUGH. 4777 case TargetLowering::Custom: 4778 OpToUse = ISD::UINT_TO_FP; 4779 break; 4780 } 4781 if (OpToUse) break; 4782 4783 // Otherwise, try a larger type. 4784 } 4785 4786 // Okay, we found the operation and type to use. Zero extend our input to the 4787 // desired type then run the operation on it. 4788 return DAG.getNode(OpToUse, DestVT, 4789 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 4790 NewInTy, LegalOp)); 4791} 4792 4793/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 4794/// FP_TO_*INT operation of the specified operand when the target requests that 4795/// we promote it. At this point, we know that the result and operand types are 4796/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 4797/// operation that returns a larger result. 4798SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 4799 MVT::ValueType DestVT, 4800 bool isSigned) { 4801 // First step, figure out the appropriate FP_TO*INT operation to use. 4802 MVT::ValueType NewOutTy = DestVT; 4803 4804 unsigned OpToUse = 0; 4805 4806 // Scan for the appropriate larger type to use. 4807 while (1) { 4808 NewOutTy = (MVT::ValueType)(NewOutTy+1); 4809 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 4810 4811 // If the target supports FP_TO_SINT returning this type, use it. 4812 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 4813 default: break; 4814 case TargetLowering::Legal: 4815 if (!TLI.isTypeLegal(NewOutTy)) 4816 break; // Can't use this datatype. 4817 // FALL THROUGH. 4818 case TargetLowering::Custom: 4819 OpToUse = ISD::FP_TO_SINT; 4820 break; 4821 } 4822 if (OpToUse) break; 4823 4824 // If the target supports FP_TO_UINT of this type, use it. 4825 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 4826 default: break; 4827 case TargetLowering::Legal: 4828 if (!TLI.isTypeLegal(NewOutTy)) 4829 break; // Can't use this datatype. 4830 // FALL THROUGH. 4831 case TargetLowering::Custom: 4832 OpToUse = ISD::FP_TO_UINT; 4833 break; 4834 } 4835 if (OpToUse) break; 4836 4837 // Otherwise, try a larger type. 4838 } 4839 4840 // Okay, we found the operation and type to use. Truncate the result of the 4841 // extended FP_TO_*INT operation to the desired size. 4842 return DAG.getNode(ISD::TRUNCATE, DestVT, 4843 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 4844} 4845 4846/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 4847/// 4848SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 4849 MVT::ValueType VT = Op.getValueType(); 4850 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 4851 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 4852 switch (VT) { 4853 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 4854 case MVT::i16: 4855 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4856 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4857 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 4858 case MVT::i32: 4859 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4860 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4861 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4862 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4863 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 4864 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 4865 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4866 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4867 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4868 case MVT::i64: 4869 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 4870 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 4871 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4872 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4873 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4874 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4875 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 4876 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 4877 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 4878 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 4879 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 4880 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 4881 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 4882 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 4883 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 4884 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 4885 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4886 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4887 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 4888 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4889 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 4890 } 4891} 4892 4893/// ExpandBitCount - Expand the specified bitcount instruction into operations. 4894/// 4895SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 4896 switch (Opc) { 4897 default: assert(0 && "Cannot expand this yet!"); 4898 case ISD::CTPOP: { 4899 static const uint64_t mask[6] = { 4900 0x5555555555555555ULL, 0x3333333333333333ULL, 4901 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 4902 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 4903 }; 4904 MVT::ValueType VT = Op.getValueType(); 4905 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4906 unsigned len = MVT::getSizeInBits(VT); 4907 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4908 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 4909 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 4910 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4911 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 4912 DAG.getNode(ISD::AND, VT, 4913 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 4914 } 4915 return Op; 4916 } 4917 case ISD::CTLZ: { 4918 // for now, we do this: 4919 // x = x | (x >> 1); 4920 // x = x | (x >> 2); 4921 // ... 4922 // x = x | (x >>16); 4923 // x = x | (x >>32); // for 64-bit input 4924 // return popcount(~x); 4925 // 4926 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 4927 MVT::ValueType VT = Op.getValueType(); 4928 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4929 unsigned len = MVT::getSizeInBits(VT); 4930 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4931 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4932 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 4933 } 4934 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 4935 return DAG.getNode(ISD::CTPOP, VT, Op); 4936 } 4937 case ISD::CTTZ: { 4938 // for now, we use: { return popcount(~x & (x - 1)); } 4939 // unless the target has ctlz but not ctpop, in which case we use: 4940 // { return 32 - nlz(~x & (x-1)); } 4941 // see also http://www.hackersdelight.org/HDcode/ntz.cc 4942 MVT::ValueType VT = Op.getValueType(); 4943 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 4944 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 4945 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 4946 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 4947 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 4948 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 4949 TLI.isOperationLegal(ISD::CTLZ, VT)) 4950 return DAG.getNode(ISD::SUB, VT, 4951 DAG.getConstant(MVT::getSizeInBits(VT), VT), 4952 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 4953 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 4954 } 4955 } 4956} 4957 4958/// ExpandOp - Expand the specified SDOperand into its two component pieces 4959/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 4960/// LegalizeNodes map is filled in for any results that are not expanded, the 4961/// ExpandedNodes map is filled in for any results that are expanded, and the 4962/// Lo/Hi values are returned. 4963void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 4964 MVT::ValueType VT = Op.getValueType(); 4965 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4966 SDNode *Node = Op.Val; 4967 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 4968 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 4969 MVT::isVector(VT)) && 4970 "Cannot expand to FP value or to larger int value!"); 4971 4972 // See if we already expanded it. 4973 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 4974 = ExpandedNodes.find(Op); 4975 if (I != ExpandedNodes.end()) { 4976 Lo = I->second.first; 4977 Hi = I->second.second; 4978 return; 4979 } 4980 4981 switch (Node->getOpcode()) { 4982 case ISD::CopyFromReg: 4983 assert(0 && "CopyFromReg must be legal!"); 4984 default: 4985#ifndef NDEBUG 4986 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4987#endif 4988 assert(0 && "Do not know how to expand this operator!"); 4989 abort(); 4990 case ISD::UNDEF: 4991 NVT = TLI.getTypeToExpandTo(VT); 4992 Lo = DAG.getNode(ISD::UNDEF, NVT); 4993 Hi = DAG.getNode(ISD::UNDEF, NVT); 4994 break; 4995 case ISD::Constant: { 4996 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 4997 Lo = DAG.getConstant(Cst, NVT); 4998 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 4999 break; 5000 } 5001 case ISD::ConstantFP: { 5002 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5003 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5004 if (getTypeAction(Lo.getValueType()) == Expand) 5005 ExpandOp(Lo, Lo, Hi); 5006 break; 5007 } 5008 case ISD::BUILD_PAIR: 5009 // Return the operands. 5010 Lo = Node->getOperand(0); 5011 Hi = Node->getOperand(1); 5012 break; 5013 5014 case ISD::SIGN_EXTEND_INREG: 5015 ExpandOp(Node->getOperand(0), Lo, Hi); 5016 // sext_inreg the low part if needed. 5017 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5018 5019 // The high part gets the sign extension from the lo-part. This handles 5020 // things like sextinreg V:i64 from i8. 5021 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5022 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 5023 TLI.getShiftAmountTy())); 5024 break; 5025 5026 case ISD::BSWAP: { 5027 ExpandOp(Node->getOperand(0), Lo, Hi); 5028 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5029 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5030 Lo = TempLo; 5031 break; 5032 } 5033 5034 case ISD::CTPOP: 5035 ExpandOp(Node->getOperand(0), Lo, Hi); 5036 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5037 DAG.getNode(ISD::CTPOP, NVT, Lo), 5038 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5039 Hi = DAG.getConstant(0, NVT); 5040 break; 5041 5042 case ISD::CTLZ: { 5043 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5044 ExpandOp(Node->getOperand(0), Lo, Hi); 5045 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5046 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5047 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 5048 ISD::SETNE); 5049 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5050 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5051 5052 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5053 Hi = DAG.getConstant(0, NVT); 5054 break; 5055 } 5056 5057 case ISD::CTTZ: { 5058 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5059 ExpandOp(Node->getOperand(0), Lo, Hi); 5060 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5061 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5062 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 5063 ISD::SETNE); 5064 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5065 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5066 5067 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5068 Hi = DAG.getConstant(0, NVT); 5069 break; 5070 } 5071 5072 case ISD::VAARG: { 5073 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5074 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5075 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5076 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5077 5078 // Remember that we legalized the chain. 5079 Hi = LegalizeOp(Hi); 5080 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5081 if (!TLI.isLittleEndian()) 5082 std::swap(Lo, Hi); 5083 break; 5084 } 5085 5086 case ISD::LOAD: { 5087 LoadSDNode *LD = cast<LoadSDNode>(Node); 5088 SDOperand Ch = LD->getChain(); // Legalize the chain. 5089 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5090 ISD::LoadExtType ExtType = LD->getExtensionType(); 5091 int SVOffset = LD->getSrcValueOffset(); 5092 unsigned Alignment = LD->getAlignment(); 5093 bool isVolatile = LD->isVolatile(); 5094 5095 if (ExtType == ISD::NON_EXTLOAD) { 5096 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5097 isVolatile, Alignment); 5098 if (VT == MVT::f32 || VT == MVT::f64) { 5099 // f32->i32 or f64->i64 one to one expansion. 5100 // Remember that we legalized the chain. 5101 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5102 // Recursively expand the new load. 5103 if (getTypeAction(NVT) == Expand) 5104 ExpandOp(Lo, Lo, Hi); 5105 break; 5106 } 5107 5108 // Increment the pointer to the other half. 5109 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 5110 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5111 getIntPtrConstant(IncrementSize)); 5112 SVOffset += IncrementSize; 5113 if (Alignment > IncrementSize) 5114 Alignment = IncrementSize; 5115 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5116 isVolatile, Alignment); 5117 5118 // Build a factor node to remember that this load is independent of the 5119 // other one. 5120 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5121 Hi.getValue(1)); 5122 5123 // Remember that we legalized the chain. 5124 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5125 if (!TLI.isLittleEndian()) 5126 std::swap(Lo, Hi); 5127 } else { 5128 MVT::ValueType EVT = LD->getLoadedVT(); 5129 5130 if (VT == MVT::f64 && EVT == MVT::f32) { 5131 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5132 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5133 SVOffset, isVolatile, Alignment); 5134 // Remember that we legalized the chain. 5135 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 5136 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 5137 break; 5138 } 5139 5140 if (EVT == NVT) 5141 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 5142 SVOffset, isVolatile, Alignment); 5143 else 5144 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 5145 SVOffset, EVT, isVolatile, 5146 Alignment); 5147 5148 // Remember that we legalized the chain. 5149 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5150 5151 if (ExtType == ISD::SEXTLOAD) { 5152 // The high part is obtained by SRA'ing all but one of the bits of the 5153 // lo part. 5154 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5155 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5156 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5157 } else if (ExtType == ISD::ZEXTLOAD) { 5158 // The high part is just a zero. 5159 Hi = DAG.getConstant(0, NVT); 5160 } else /* if (ExtType == ISD::EXTLOAD) */ { 5161 // The high part is undefined. 5162 Hi = DAG.getNode(ISD::UNDEF, NVT); 5163 } 5164 } 5165 break; 5166 } 5167 case ISD::AND: 5168 case ISD::OR: 5169 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 5170 SDOperand LL, LH, RL, RH; 5171 ExpandOp(Node->getOperand(0), LL, LH); 5172 ExpandOp(Node->getOperand(1), RL, RH); 5173 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 5174 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 5175 break; 5176 } 5177 case ISD::SELECT: { 5178 SDOperand LL, LH, RL, RH; 5179 ExpandOp(Node->getOperand(1), LL, LH); 5180 ExpandOp(Node->getOperand(2), RL, RH); 5181 if (getTypeAction(NVT) == Expand) 5182 NVT = TLI.getTypeToExpandTo(NVT); 5183 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 5184 if (VT != MVT::f32) 5185 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 5186 break; 5187 } 5188 case ISD::SELECT_CC: { 5189 SDOperand TL, TH, FL, FH; 5190 ExpandOp(Node->getOperand(2), TL, TH); 5191 ExpandOp(Node->getOperand(3), FL, FH); 5192 if (getTypeAction(NVT) == Expand) 5193 NVT = TLI.getTypeToExpandTo(NVT); 5194 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5195 Node->getOperand(1), TL, FL, Node->getOperand(4)); 5196 if (VT != MVT::f32) 5197 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5198 Node->getOperand(1), TH, FH, Node->getOperand(4)); 5199 break; 5200 } 5201 case ISD::ANY_EXTEND: 5202 // The low part is any extension of the input (which degenerates to a copy). 5203 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 5204 // The high part is undefined. 5205 Hi = DAG.getNode(ISD::UNDEF, NVT); 5206 break; 5207 case ISD::SIGN_EXTEND: { 5208 // The low part is just a sign extension of the input (which degenerates to 5209 // a copy). 5210 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 5211 5212 // The high part is obtained by SRA'ing all but one of the bits of the lo 5213 // part. 5214 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5215 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5216 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5217 break; 5218 } 5219 case ISD::ZERO_EXTEND: 5220 // The low part is just a zero extension of the input (which degenerates to 5221 // a copy). 5222 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 5223 5224 // The high part is just a zero. 5225 Hi = DAG.getConstant(0, NVT); 5226 break; 5227 5228 case ISD::TRUNCATE: { 5229 // The input value must be larger than this value. Expand *it*. 5230 SDOperand NewLo; 5231 ExpandOp(Node->getOperand(0), NewLo, Hi); 5232 5233 // The low part is now either the right size, or it is closer. If not the 5234 // right size, make an illegal truncate so we recursively expand it. 5235 if (NewLo.getValueType() != Node->getValueType(0)) 5236 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 5237 ExpandOp(NewLo, Lo, Hi); 5238 break; 5239 } 5240 5241 case ISD::BIT_CONVERT: { 5242 SDOperand Tmp; 5243 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 5244 // If the target wants to, allow it to lower this itself. 5245 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5246 case Expand: assert(0 && "cannot expand FP!"); 5247 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 5248 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 5249 } 5250 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 5251 } 5252 5253 // f32 / f64 must be expanded to i32 / i64. 5254 if (VT == MVT::f32 || VT == MVT::f64) { 5255 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5256 if (getTypeAction(NVT) == Expand) 5257 ExpandOp(Lo, Lo, Hi); 5258 break; 5259 } 5260 5261 // If source operand will be expanded to the same type as VT, i.e. 5262 // i64 <- f64, i32 <- f32, expand the source operand instead. 5263 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 5264 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 5265 ExpandOp(Node->getOperand(0), Lo, Hi); 5266 break; 5267 } 5268 5269 // Turn this into a load/store pair by default. 5270 if (Tmp.Val == 0) 5271 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0)); 5272 5273 ExpandOp(Tmp, Lo, Hi); 5274 break; 5275 } 5276 5277 case ISD::READCYCLECOUNTER: 5278 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 5279 TargetLowering::Custom && 5280 "Must custom expand ReadCycleCounter"); 5281 Lo = TLI.LowerOperation(Op, DAG); 5282 assert(Lo.Val && "Node must be custom expanded!"); 5283 Hi = Lo.getValue(1); 5284 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 5285 LegalizeOp(Lo.getValue(2))); 5286 break; 5287 5288 // These operators cannot be expanded directly, emit them as calls to 5289 // library functions. 5290 case ISD::FP_TO_SINT: { 5291 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 5292 SDOperand Op; 5293 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5294 case Expand: assert(0 && "cannot expand FP!"); 5295 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5296 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5297 } 5298 5299 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 5300 5301 // Now that the custom expander is done, expand the result, which is still 5302 // VT. 5303 if (Op.Val) { 5304 ExpandOp(Op, Lo, Hi); 5305 break; 5306 } 5307 } 5308 5309 RTLIB::Libcall LC; 5310 if (Node->getOperand(0).getValueType() == MVT::f32) 5311 LC = RTLIB::FPTOSINT_F32_I64; 5312 else 5313 LC = RTLIB::FPTOSINT_F64_I64; 5314 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5315 false/*sign irrelevant*/, Hi); 5316 break; 5317 } 5318 5319 case ISD::FP_TO_UINT: { 5320 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 5321 SDOperand Op; 5322 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5323 case Expand: assert(0 && "cannot expand FP!"); 5324 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5325 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5326 } 5327 5328 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 5329 5330 // Now that the custom expander is done, expand the result. 5331 if (Op.Val) { 5332 ExpandOp(Op, Lo, Hi); 5333 break; 5334 } 5335 } 5336 5337 RTLIB::Libcall LC; 5338 if (Node->getOperand(0).getValueType() == MVT::f32) 5339 LC = RTLIB::FPTOUINT_F32_I64; 5340 else 5341 LC = RTLIB::FPTOUINT_F64_I64; 5342 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5343 false/*sign irrelevant*/, Hi); 5344 break; 5345 } 5346 5347 case ISD::SHL: { 5348 // If the target wants custom lowering, do so. 5349 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5350 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 5351 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 5352 Op = TLI.LowerOperation(Op, DAG); 5353 if (Op.Val) { 5354 // Now that the custom expander is done, expand the result, which is 5355 // still VT. 5356 ExpandOp(Op, Lo, Hi); 5357 break; 5358 } 5359 } 5360 5361 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 5362 // this X << 1 as X+X. 5363 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 5364 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 5365 TLI.isOperationLegal(ISD::ADDE, NVT)) { 5366 SDOperand LoOps[2], HiOps[3]; 5367 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 5368 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 5369 LoOps[1] = LoOps[0]; 5370 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5371 5372 HiOps[1] = HiOps[0]; 5373 HiOps[2] = Lo.getValue(1); 5374 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5375 break; 5376 } 5377 } 5378 5379 // If we can emit an efficient shift operation, do so now. 5380 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5381 break; 5382 5383 // If this target supports SHL_PARTS, use it. 5384 TargetLowering::LegalizeAction Action = 5385 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 5386 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5387 Action == TargetLowering::Custom) { 5388 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5389 break; 5390 } 5391 5392 // Otherwise, emit a libcall. 5393 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 5394 false/*left shift=unsigned*/, Hi); 5395 break; 5396 } 5397 5398 case ISD::SRA: { 5399 // If the target wants custom lowering, do so. 5400 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5401 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 5402 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 5403 Op = TLI.LowerOperation(Op, DAG); 5404 if (Op.Val) { 5405 // Now that the custom expander is done, expand the result, which is 5406 // still VT. 5407 ExpandOp(Op, Lo, Hi); 5408 break; 5409 } 5410 } 5411 5412 // If we can emit an efficient shift operation, do so now. 5413 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5414 break; 5415 5416 // If this target supports SRA_PARTS, use it. 5417 TargetLowering::LegalizeAction Action = 5418 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 5419 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5420 Action == TargetLowering::Custom) { 5421 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5422 break; 5423 } 5424 5425 // Otherwise, emit a libcall. 5426 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 5427 true/*ashr is signed*/, Hi); 5428 break; 5429 } 5430 5431 case ISD::SRL: { 5432 // If the target wants custom lowering, do so. 5433 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5434 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 5435 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 5436 Op = TLI.LowerOperation(Op, DAG); 5437 if (Op.Val) { 5438 // Now that the custom expander is done, expand the result, which is 5439 // still VT. 5440 ExpandOp(Op, Lo, Hi); 5441 break; 5442 } 5443 } 5444 5445 // If we can emit an efficient shift operation, do so now. 5446 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5447 break; 5448 5449 // If this target supports SRL_PARTS, use it. 5450 TargetLowering::LegalizeAction Action = 5451 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 5452 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5453 Action == TargetLowering::Custom) { 5454 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5455 break; 5456 } 5457 5458 // Otherwise, emit a libcall. 5459 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 5460 false/*lshr is unsigned*/, Hi); 5461 break; 5462 } 5463 5464 case ISD::ADD: 5465 case ISD::SUB: { 5466 // If the target wants to custom expand this, let them. 5467 if (TLI.getOperationAction(Node->getOpcode(), VT) == 5468 TargetLowering::Custom) { 5469 Op = TLI.LowerOperation(Op, DAG); 5470 if (Op.Val) { 5471 ExpandOp(Op, Lo, Hi); 5472 break; 5473 } 5474 } 5475 5476 // Expand the subcomponents. 5477 SDOperand LHSL, LHSH, RHSL, RHSH; 5478 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5479 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5480 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5481 SDOperand LoOps[2], HiOps[3]; 5482 LoOps[0] = LHSL; 5483 LoOps[1] = RHSL; 5484 HiOps[0] = LHSH; 5485 HiOps[1] = RHSH; 5486 if (Node->getOpcode() == ISD::ADD) { 5487 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5488 HiOps[2] = Lo.getValue(1); 5489 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5490 } else { 5491 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5492 HiOps[2] = Lo.getValue(1); 5493 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5494 } 5495 break; 5496 } 5497 5498 case ISD::ADDC: 5499 case ISD::SUBC: { 5500 // Expand the subcomponents. 5501 SDOperand LHSL, LHSH, RHSL, RHSH; 5502 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5503 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5504 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5505 SDOperand LoOps[2] = { LHSL, RHSL }; 5506 SDOperand HiOps[3] = { LHSH, RHSH }; 5507 5508 if (Node->getOpcode() == ISD::ADDC) { 5509 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5510 HiOps[2] = Lo.getValue(1); 5511 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5512 } else { 5513 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5514 HiOps[2] = Lo.getValue(1); 5515 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5516 } 5517 // Remember that we legalized the flag. 5518 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5519 break; 5520 } 5521 case ISD::ADDE: 5522 case ISD::SUBE: { 5523 // Expand the subcomponents. 5524 SDOperand LHSL, LHSH, RHSL, RHSH; 5525 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5526 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5527 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5528 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 5529 SDOperand HiOps[3] = { LHSH, RHSH }; 5530 5531 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 5532 HiOps[2] = Lo.getValue(1); 5533 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 5534 5535 // Remember that we legalized the flag. 5536 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5537 break; 5538 } 5539 case ISD::MUL: { 5540 // If the target wants to custom expand this, let them. 5541 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 5542 SDOperand New = TLI.LowerOperation(Op, DAG); 5543 if (New.Val) { 5544 ExpandOp(New, Lo, Hi); 5545 break; 5546 } 5547 } 5548 5549 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 5550 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 5551 if (HasMULHS || HasMULHU) { 5552 SDOperand LL, LH, RL, RH; 5553 ExpandOp(Node->getOperand(0), LL, LH); 5554 ExpandOp(Node->getOperand(1), RL, RH); 5555 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 5556 // FIXME: Move this to the dag combiner. 5557 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 5558 // extended the sign bit of the low half through the upper half, and if so 5559 // emit a MULHS instead of the alternate sequence that is valid for any 5560 // i64 x i64 multiply. 5561 if (HasMULHS && 5562 // is RH an extension of the sign bit of RL? 5563 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 5564 RH.getOperand(1).getOpcode() == ISD::Constant && 5565 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 5566 // is LH an extension of the sign bit of LL? 5567 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 5568 LH.getOperand(1).getOpcode() == ISD::Constant && 5569 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 5570 // Low part: 5571 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5572 // High part: 5573 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 5574 break; 5575 } else if (HasMULHU) { 5576 // Low part: 5577 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5578 5579 // High part: 5580 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 5581 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 5582 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 5583 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 5584 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 5585 break; 5586 } 5587 } 5588 5589 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 5590 false/*sign irrelevant*/, Hi); 5591 break; 5592 } 5593 case ISD::SDIV: 5594 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 5595 break; 5596 case ISD::UDIV: 5597 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 5598 break; 5599 case ISD::SREM: 5600 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 5601 break; 5602 case ISD::UREM: 5603 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 5604 break; 5605 5606 case ISD::FADD: 5607 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5608 ? RTLIB::ADD_F32 : RTLIB::ADD_F64), 5609 Node, false, Hi); 5610 break; 5611 case ISD::FSUB: 5612 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5613 ? RTLIB::SUB_F32 : RTLIB::SUB_F64), 5614 Node, false, Hi); 5615 break; 5616 case ISD::FMUL: 5617 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5618 ? RTLIB::MUL_F32 : RTLIB::MUL_F64), 5619 Node, false, Hi); 5620 break; 5621 case ISD::FDIV: 5622 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5623 ? RTLIB::DIV_F32 : RTLIB::DIV_F64), 5624 Node, false, Hi); 5625 break; 5626 case ISD::FP_EXTEND: 5627 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 5628 break; 5629 case ISD::FP_ROUND: 5630 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 5631 break; 5632 case ISD::FPOWI: 5633 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5634 ? RTLIB::POWI_F32 : RTLIB::POWI_F64), 5635 Node, false, Hi); 5636 break; 5637 case ISD::FSQRT: 5638 case ISD::FSIN: 5639 case ISD::FCOS: { 5640 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5641 switch(Node->getOpcode()) { 5642 case ISD::FSQRT: 5643 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64; 5644 break; 5645 case ISD::FSIN: 5646 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 5647 break; 5648 case ISD::FCOS: 5649 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64; 5650 break; 5651 default: assert(0 && "Unreachable!"); 5652 } 5653 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 5654 break; 5655 } 5656 case ISD::FABS: { 5657 SDOperand Mask = (VT == MVT::f64) 5658 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 5659 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 5660 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 5661 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5662 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 5663 if (getTypeAction(NVT) == Expand) 5664 ExpandOp(Lo, Lo, Hi); 5665 break; 5666 } 5667 case ISD::FNEG: { 5668 SDOperand Mask = (VT == MVT::f64) 5669 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 5670 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 5671 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 5672 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5673 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 5674 if (getTypeAction(NVT) == Expand) 5675 ExpandOp(Lo, Lo, Hi); 5676 break; 5677 } 5678 case ISD::FCOPYSIGN: { 5679 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 5680 if (getTypeAction(NVT) == Expand) 5681 ExpandOp(Lo, Lo, Hi); 5682 break; 5683 } 5684 case ISD::SINT_TO_FP: 5685 case ISD::UINT_TO_FP: { 5686 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 5687 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 5688 RTLIB::Libcall LC; 5689 if (Node->getOperand(0).getValueType() == MVT::i64) { 5690 if (VT == MVT::f32) 5691 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; 5692 else 5693 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; 5694 } else { 5695 if (VT == MVT::f32) 5696 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 5697 else 5698 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 5699 } 5700 5701 // Promote the operand if needed. 5702 if (getTypeAction(SrcVT) == Promote) { 5703 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 5704 Tmp = isSigned 5705 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 5706 DAG.getValueType(SrcVT)) 5707 : DAG.getZeroExtendInReg(Tmp, SrcVT); 5708 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 5709 } 5710 5711 const char *LibCall = TLI.getLibcallName(LC); 5712 if (LibCall) 5713 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi); 5714 else { 5715 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 5716 Node->getOperand(0)); 5717 if (getTypeAction(Lo.getValueType()) == Expand) 5718 ExpandOp(Lo, Lo, Hi); 5719 } 5720 break; 5721 } 5722 } 5723 5724 // Make sure the resultant values have been legalized themselves, unless this 5725 // is a type that requires multi-step expansion. 5726 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 5727 Lo = LegalizeOp(Lo); 5728 if (Hi.Val) 5729 // Don't legalize the high part if it is expanded to a single node. 5730 Hi = LegalizeOp(Hi); 5731 } 5732 5733 // Remember in a map if the values will be reused later. 5734 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 5735 assert(isNew && "Value already expanded?!?"); 5736} 5737 5738/// SplitVectorOp - Given an operand of vector type, break it down into 5739/// two smaller values, still of vector type. 5740void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 5741 SDOperand &Hi) { 5742 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); 5743 SDNode *Node = Op.Val; 5744 unsigned NumElements = MVT::getVectorNumElements(Node->getValueType(0)); 5745 assert(NumElements > 1 && "Cannot split a single element vector!"); 5746 unsigned NewNumElts = NumElements/2; 5747 MVT::ValueType NewEltVT = MVT::getVectorElementType(Node->getValueType(0)); 5748 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts); 5749 5750 // See if we already split it. 5751 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5752 = SplitNodes.find(Op); 5753 if (I != SplitNodes.end()) { 5754 Lo = I->second.first; 5755 Hi = I->second.second; 5756 return; 5757 } 5758 5759 switch (Node->getOpcode()) { 5760 default: 5761#ifndef NDEBUG 5762 Node->dump(&DAG); 5763#endif 5764 assert(0 && "Unhandled operation in SplitVectorOp!"); 5765 case ISD::BUILD_PAIR: 5766 Lo = Node->getOperand(0); 5767 Hi = Node->getOperand(1); 5768 break; 5769 case ISD::BUILD_VECTOR: { 5770 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 5771 Node->op_begin()+NewNumElts); 5772 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size()); 5773 5774 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts, 5775 Node->op_end()); 5776 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size()); 5777 break; 5778 } 5779 case ISD::CONCAT_VECTORS: { 5780 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 5781 if (NewNumSubvectors == 1) { 5782 Lo = Node->getOperand(0); 5783 Hi = Node->getOperand(1); 5784 } else { 5785 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 5786 Node->op_begin()+NewNumSubvectors); 5787 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size()); 5788 5789 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 5790 Node->op_end()); 5791 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size()); 5792 } 5793 break; 5794 } 5795 case ISD::ADD: 5796 case ISD::SUB: 5797 case ISD::MUL: 5798 case ISD::FADD: 5799 case ISD::FSUB: 5800 case ISD::FMUL: 5801 case ISD::SDIV: 5802 case ISD::UDIV: 5803 case ISD::FDIV: 5804 case ISD::AND: 5805 case ISD::OR: 5806 case ISD::XOR: { 5807 SDOperand LL, LH, RL, RH; 5808 SplitVectorOp(Node->getOperand(0), LL, LH); 5809 SplitVectorOp(Node->getOperand(1), RL, RH); 5810 5811 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL); 5812 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH); 5813 break; 5814 } 5815 case ISD::LOAD: { 5816 LoadSDNode *LD = cast<LoadSDNode>(Node); 5817 SDOperand Ch = LD->getChain(); 5818 SDOperand Ptr = LD->getBasePtr(); 5819 const Value *SV = LD->getSrcValue(); 5820 int SVOffset = LD->getSrcValueOffset(); 5821 unsigned Alignment = LD->getAlignment(); 5822 bool isVolatile = LD->isVolatile(); 5823 5824 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 5825 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8; 5826 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5827 getIntPtrConstant(IncrementSize)); 5828 SVOffset += IncrementSize; 5829 if (Alignment > IncrementSize) 5830 Alignment = IncrementSize; 5831 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 5832 5833 // Build a factor node to remember that this load is independent of the 5834 // other one. 5835 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5836 Hi.getValue(1)); 5837 5838 // Remember that we legalized the chain. 5839 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5840 break; 5841 } 5842 case ISD::BIT_CONVERT: { 5843 // We know the result is a vector. The input may be either a vector or a 5844 // scalar value. 5845 SDOperand InOp = Node->getOperand(0); 5846 if (!MVT::isVector(InOp.getValueType()) || 5847 MVT::getVectorNumElements(InOp.getValueType()) == 1) { 5848 // The input is a scalar or single-element vector. 5849 // Lower to a store/load so that it can be split. 5850 // FIXME: this could be improved probably. 5851 SDOperand Ptr = CreateStackTemporary(InOp.getValueType()); 5852 5853 SDOperand St = DAG.getStore(DAG.getEntryNode(), 5854 InOp, Ptr, NULL, 0); 5855 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0); 5856 } 5857 // Split the vector and convert each of the pieces now. 5858 SplitVectorOp(InOp, Lo, Hi); 5859 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo); 5860 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi); 5861 break; 5862 } 5863 } 5864 5865 // Remember in a map if the values will be reused later. 5866 bool isNew = 5867 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 5868 assert(isNew && "Value already split?!?"); 5869} 5870 5871 5872/// ScalarizeVectorOp - Given an operand of single-element vector type 5873/// (e.g. v1f32), convert it into the equivalent operation that returns a 5874/// scalar (e.g. f32) value. 5875SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 5876 assert(MVT::isVector(Op.getValueType()) && 5877 "Bad ScalarizeVectorOp invocation!"); 5878 SDNode *Node = Op.Val; 5879 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); 5880 assert(MVT::getVectorNumElements(Op.getValueType()) == 1); 5881 5882 // See if we already scalarized it. 5883 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 5884 if (I != ScalarizedNodes.end()) return I->second; 5885 5886 SDOperand Result; 5887 switch (Node->getOpcode()) { 5888 default: 5889#ifndef NDEBUG 5890 Node->dump(&DAG); cerr << "\n"; 5891#endif 5892 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 5893 case ISD::ADD: 5894 case ISD::FADD: 5895 case ISD::SUB: 5896 case ISD::FSUB: 5897 case ISD::MUL: 5898 case ISD::FMUL: 5899 case ISD::SDIV: 5900 case ISD::UDIV: 5901 case ISD::FDIV: 5902 case ISD::SREM: 5903 case ISD::UREM: 5904 case ISD::FREM: 5905 case ISD::AND: 5906 case ISD::OR: 5907 case ISD::XOR: 5908 Result = DAG.getNode(Node->getOpcode(), 5909 NewVT, 5910 ScalarizeVectorOp(Node->getOperand(0)), 5911 ScalarizeVectorOp(Node->getOperand(1))); 5912 break; 5913 case ISD::FNEG: 5914 case ISD::FABS: 5915 case ISD::FSQRT: 5916 case ISD::FSIN: 5917 case ISD::FCOS: 5918 Result = DAG.getNode(Node->getOpcode(), 5919 NewVT, 5920 ScalarizeVectorOp(Node->getOperand(0))); 5921 break; 5922 case ISD::LOAD: { 5923 LoadSDNode *LD = cast<LoadSDNode>(Node); 5924 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 5925 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 5926 5927 const Value *SV = LD->getSrcValue(); 5928 int SVOffset = LD->getSrcValueOffset(); 5929 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 5930 LD->isVolatile(), LD->getAlignment()); 5931 5932 // Remember that we legalized the chain. 5933 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 5934 break; 5935 } 5936 case ISD::BUILD_VECTOR: 5937 Result = Node->getOperand(0); 5938 break; 5939 case ISD::INSERT_VECTOR_ELT: 5940 // Returning the inserted scalar element. 5941 Result = Node->getOperand(1); 5942 break; 5943 case ISD::CONCAT_VECTORS: 5944 assert(Node->getOperand(0).getValueType() == NewVT && 5945 "Concat of non-legal vectors not yet supported!"); 5946 Result = Node->getOperand(0); 5947 break; 5948 case ISD::VECTOR_SHUFFLE: { 5949 // Figure out if the scalar is the LHS or RHS and return it. 5950 SDOperand EltNum = Node->getOperand(2).getOperand(0); 5951 if (cast<ConstantSDNode>(EltNum)->getValue()) 5952 Result = ScalarizeVectorOp(Node->getOperand(1)); 5953 else 5954 Result = ScalarizeVectorOp(Node->getOperand(0)); 5955 break; 5956 } 5957 case ISD::EXTRACT_SUBVECTOR: 5958 Result = Node->getOperand(0); 5959 assert(Result.getValueType() == NewVT); 5960 break; 5961 case ISD::BIT_CONVERT: 5962 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 5963 break; 5964 case ISD::SELECT: 5965 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 5966 ScalarizeVectorOp(Op.getOperand(1)), 5967 ScalarizeVectorOp(Op.getOperand(2))); 5968 break; 5969 } 5970 5971 if (TLI.isTypeLegal(NewVT)) 5972 Result = LegalizeOp(Result); 5973 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 5974 assert(isNew && "Value already scalarized?"); 5975 return Result; 5976} 5977 5978 5979// SelectionDAG::Legalize - This is the entry point for the file. 5980// 5981void SelectionDAG::Legalize() { 5982 if (ViewLegalizeDAGs) viewGraph(); 5983 5984 /// run - This is the main entry point to this class. 5985 /// 5986 SelectionDAGLegalize(*this).LegalizeDAG(); 5987} 5988 5989