LegalizeDAG.cpp revision 0f8d9c04d9feef86cee35cf5fecfb348a6b3de50
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/Target/TargetFrameInfo.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetMachine.h" 22#include "llvm/Target/TargetOptions.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/DerivedTypes.h" 26#include "llvm/Support/CommandLine.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/MathExtras.h" 29#include "llvm/ADT/DenseMap.h" 30#include "llvm/ADT/SmallVector.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include <map> 33using namespace llvm; 34 35#ifndef NDEBUG 36static cl::opt<bool> 37ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 38 cl::desc("Pop up a window to show dags before legalize")); 39#else 40static const bool ViewLegalizeDAGs = 0; 41#endif 42 43//===----------------------------------------------------------------------===// 44/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 45/// hacks on it until the target machine can handle it. This involves 46/// eliminating value sizes the machine cannot handle (promoting small sizes to 47/// large sizes or splitting up large values into small values) as well as 48/// eliminating operations the machine cannot handle. 49/// 50/// This code also does a small amount of optimization and recognition of idioms 51/// as part of its processing. For example, if a target does not support a 52/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 53/// will attempt merge setcc and brc instructions into brcc's. 54/// 55namespace { 56class VISIBILITY_HIDDEN SelectionDAGLegalize { 57 TargetLowering &TLI; 58 SelectionDAG &DAG; 59 60 // Libcall insertion helpers. 61 62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 63 /// legalized. We use this to ensure that calls are properly serialized 64 /// against each other, including inserted libcalls. 65 SDOperand LastCALLSEQ_END; 66 67 /// IsLegalizingCall - This member is used *only* for purposes of providing 68 /// helpful assertions that a libcall isn't created while another call is 69 /// being legalized (which could lead to non-serialized call sequences). 70 bool IsLegalizingCall; 71 72 enum LegalizeAction { 73 Legal, // The target natively supports this operation. 74 Promote, // This operation should be executed in a larger type. 75 Expand // Try to expand this to other ops, otherwise use a libcall. 76 }; 77 78 /// ValueTypeActions - This is a bitvector that contains two bits for each 79 /// value type, where the two bits correspond to the LegalizeAction enum. 80 /// This can be queried with "getTypeAction(VT)". 81 TargetLowering::ValueTypeActionImpl ValueTypeActions; 82 83 /// LegalizedNodes - For nodes that are of legal width, and that have more 84 /// than one use, this map indicates what regularized operand to use. This 85 /// allows us to avoid legalizing the same thing more than once. 86 DenseMap<SDOperand, SDOperand> LegalizedNodes; 87 88 /// PromotedNodes - For nodes that are below legal width, and that have more 89 /// than one use, this map indicates what promoted value to use. This allows 90 /// us to avoid promoting the same thing more than once. 91 DenseMap<SDOperand, SDOperand> PromotedNodes; 92 93 /// ExpandedNodes - For nodes that need to be expanded this map indicates 94 /// which which operands are the expanded version of the input. This allows 95 /// us to avoid expanding the same node more than once. 96 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 97 98 /// SplitNodes - For vector nodes that need to be split, this map indicates 99 /// which which operands are the split version of the input. This allows us 100 /// to avoid splitting the same node more than once. 101 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 102 103 /// ScalarizedNodes - For nodes that need to be converted from vector types to 104 /// scalar types, this contains the mapping of ones we have already 105 /// processed to the result. 106 std::map<SDOperand, SDOperand> ScalarizedNodes; 107 108 void AddLegalizedOperand(SDOperand From, SDOperand To) { 109 LegalizedNodes.insert(std::make_pair(From, To)); 110 // If someone requests legalization of the new node, return itself. 111 if (From != To) 112 LegalizedNodes.insert(std::make_pair(To, To)); 113 } 114 void AddPromotedOperand(SDOperand From, SDOperand To) { 115 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 116 assert(isNew && "Got into the map somehow?"); 117 // If someone requests legalization of the new node, return itself. 118 LegalizedNodes.insert(std::make_pair(To, To)); 119 } 120 121public: 122 123 SelectionDAGLegalize(SelectionDAG &DAG); 124 125 /// getTypeAction - Return how we should legalize values of this type, either 126 /// it is already legal or we need to expand it into multiple registers of 127 /// smaller integer type, or we need to promote it to a larger type. 128 LegalizeAction getTypeAction(MVT::ValueType VT) const { 129 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 130 } 131 132 /// isTypeLegal - Return true if this type is legal on this target. 133 /// 134 bool isTypeLegal(MVT::ValueType VT) const { 135 return getTypeAction(VT) == Legal; 136 } 137 138 void LegalizeDAG(); 139 140private: 141 /// HandleOp - Legalize, Promote, or Expand the specified operand as 142 /// appropriate for its type. 143 void HandleOp(SDOperand Op); 144 145 /// LegalizeOp - We know that the specified value has a legal type. 146 /// Recursively ensure that the operands have legal types, then return the 147 /// result. 148 SDOperand LegalizeOp(SDOperand O); 149 150 /// UnrollVectorOp - We know that the given vector has a legal type, however 151 /// the operation it performs is not legal and is an operation that we have 152 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 153 /// operating on each element individually. 154 SDOperand UnrollVectorOp(SDOperand O); 155 156 /// PromoteOp - Given an operation that produces a value in an invalid type, 157 /// promote it to compute the value into a larger type. The produced value 158 /// will have the correct bits for the low portion of the register, but no 159 /// guarantee is made about the top bits: it may be zero, sign-extended, or 160 /// garbage. 161 SDOperand PromoteOp(SDOperand O); 162 163 /// ExpandOp - Expand the specified SDOperand into its two component pieces 164 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 165 /// the LegalizeNodes map is filled in for any results that are not expanded, 166 /// the ExpandedNodes map is filled in for any results that are expanded, and 167 /// the Lo/Hi values are returned. This applies to integer types and Vector 168 /// types. 169 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 170 171 /// SplitVectorOp - Given an operand of vector type, break it down into 172 /// two smaller values. 173 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 174 175 /// ScalarizeVectorOp - Given an operand of single-element vector type 176 /// (e.g. v1f32), convert it into the equivalent operation that returns a 177 /// scalar (e.g. f32) value. 178 SDOperand ScalarizeVectorOp(SDOperand O); 179 180 /// isShuffleLegal - Return true if a vector shuffle is legal with the 181 /// specified mask and type. Targets can specify exactly which masks they 182 /// support and the code generator is tasked with not creating illegal masks. 183 /// 184 /// Note that this will also return true for shuffles that are promoted to a 185 /// different type. 186 /// 187 /// If this is a legal shuffle, this method returns the (possibly promoted) 188 /// build_vector Mask. If it's not a legal shuffle, it returns null. 189 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 190 191 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 192 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 193 194 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 195 196 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 197 SDOperand &Hi); 198 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 199 SDOperand Source); 200 201 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 202 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 203 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 204 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 205 SDOperand LegalOp, 206 MVT::ValueType DestVT); 207 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 208 bool isSigned); 209 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 210 bool isSigned); 211 212 SDOperand ExpandBSWAP(SDOperand Op); 213 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 214 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 215 SDOperand &Lo, SDOperand &Hi); 216 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 217 SDOperand &Lo, SDOperand &Hi); 218 219 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 220 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 221 222 SDOperand getIntPtrConstant(uint64_t Val) { 223 return DAG.getConstant(Val, TLI.getPointerTy()); 224 } 225}; 226} 227 228/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 229/// specified mask and type. Targets can specify exactly which masks they 230/// support and the code generator is tasked with not creating illegal masks. 231/// 232/// Note that this will also return true for shuffles that are promoted to a 233/// different type. 234SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 235 SDOperand Mask) const { 236 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 237 default: return 0; 238 case TargetLowering::Legal: 239 case TargetLowering::Custom: 240 break; 241 case TargetLowering::Promote: { 242 // If this is promoted to a different type, convert the shuffle mask and 243 // ask if it is legal in the promoted type! 244 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 245 246 // If we changed # elements, change the shuffle mask. 247 unsigned NumEltsGrowth = 248 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 249 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 250 if (NumEltsGrowth > 1) { 251 // Renumber the elements. 252 SmallVector<SDOperand, 8> Ops; 253 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 254 SDOperand InOp = Mask.getOperand(i); 255 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 256 if (InOp.getOpcode() == ISD::UNDEF) 257 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 258 else { 259 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 260 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 261 } 262 } 263 } 264 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 265 } 266 VT = NVT; 267 break; 268 } 269 } 270 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 271} 272 273SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 274 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 275 ValueTypeActions(TLI.getValueTypeActions()) { 276 assert(MVT::LAST_VALUETYPE <= 32 && 277 "Too many value types for ValueTypeActions to hold!"); 278} 279 280/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 281/// contains all of a nodes operands before it contains the node. 282static void ComputeTopDownOrdering(SelectionDAG &DAG, 283 SmallVector<SDNode*, 64> &Order) { 284 285 DenseMap<SDNode*, unsigned> Visited; 286 std::vector<SDNode*> Worklist; 287 Worklist.reserve(128); 288 289 // Compute ordering from all of the leaves in the graphs, those (like the 290 // entry node) that have no operands. 291 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 292 E = DAG.allnodes_end(); I != E; ++I) { 293 if (I->getNumOperands() == 0) { 294 Visited[I] = 0 - 1U; 295 Worklist.push_back(I); 296 } 297 } 298 299 while (!Worklist.empty()) { 300 SDNode *N = Worklist.back(); 301 Worklist.pop_back(); 302 303 if (++Visited[N] != N->getNumOperands()) 304 continue; // Haven't visited all operands yet 305 306 Order.push_back(N); 307 308 // Now that we have N in, add anything that uses it if all of their operands 309 // are now done. 310 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 311 UI != E; ++UI) 312 Worklist.push_back(*UI); 313 } 314 315 assert(Order.size() == Visited.size() && 316 Order.size() == 317 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 318 "Error: DAG is cyclic!"); 319} 320 321 322void SelectionDAGLegalize::LegalizeDAG() { 323 LastCALLSEQ_END = DAG.getEntryNode(); 324 IsLegalizingCall = false; 325 326 // The legalize process is inherently a bottom-up recursive process (users 327 // legalize their uses before themselves). Given infinite stack space, we 328 // could just start legalizing on the root and traverse the whole graph. In 329 // practice however, this causes us to run out of stack space on large basic 330 // blocks. To avoid this problem, compute an ordering of the nodes where each 331 // node is only legalized after all of its operands are legalized. 332 SmallVector<SDNode*, 64> Order; 333 ComputeTopDownOrdering(DAG, Order); 334 335 for (unsigned i = 0, e = Order.size(); i != e; ++i) 336 HandleOp(SDOperand(Order[i], 0)); 337 338 // Finally, it's possible the root changed. Get the new root. 339 SDOperand OldRoot = DAG.getRoot(); 340 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 341 DAG.setRoot(LegalizedNodes[OldRoot]); 342 343 ExpandedNodes.clear(); 344 LegalizedNodes.clear(); 345 PromotedNodes.clear(); 346 SplitNodes.clear(); 347 ScalarizedNodes.clear(); 348 349 // Remove dead nodes now. 350 DAG.RemoveDeadNodes(); 351} 352 353 354/// FindCallEndFromCallStart - Given a chained node that is part of a call 355/// sequence, find the CALLSEQ_END node that terminates the call sequence. 356static SDNode *FindCallEndFromCallStart(SDNode *Node) { 357 if (Node->getOpcode() == ISD::CALLSEQ_END) 358 return Node; 359 if (Node->use_empty()) 360 return 0; // No CallSeqEnd 361 362 // The chain is usually at the end. 363 SDOperand TheChain(Node, Node->getNumValues()-1); 364 if (TheChain.getValueType() != MVT::Other) { 365 // Sometimes it's at the beginning. 366 TheChain = SDOperand(Node, 0); 367 if (TheChain.getValueType() != MVT::Other) { 368 // Otherwise, hunt for it. 369 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 370 if (Node->getValueType(i) == MVT::Other) { 371 TheChain = SDOperand(Node, i); 372 break; 373 } 374 375 // Otherwise, we walked into a node without a chain. 376 if (TheChain.getValueType() != MVT::Other) 377 return 0; 378 } 379 } 380 381 for (SDNode::use_iterator UI = Node->use_begin(), 382 E = Node->use_end(); UI != E; ++UI) { 383 384 // Make sure to only follow users of our token chain. 385 SDNode *User = *UI; 386 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 387 if (User->getOperand(i) == TheChain) 388 if (SDNode *Result = FindCallEndFromCallStart(User)) 389 return Result; 390 } 391 return 0; 392} 393 394/// FindCallStartFromCallEnd - Given a chained node that is part of a call 395/// sequence, find the CALLSEQ_START node that initiates the call sequence. 396static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 397 assert(Node && "Didn't find callseq_start for a call??"); 398 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 399 400 assert(Node->getOperand(0).getValueType() == MVT::Other && 401 "Node doesn't have a token chain argument!"); 402 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 403} 404 405/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 406/// see if any uses can reach Dest. If no dest operands can get to dest, 407/// legalize them, legalize ourself, and return false, otherwise, return true. 408/// 409/// Keep track of the nodes we fine that actually do lead to Dest in 410/// NodesLeadingTo. This avoids retraversing them exponential number of times. 411/// 412bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 413 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 414 if (N == Dest) return true; // N certainly leads to Dest :) 415 416 // If we've already processed this node and it does lead to Dest, there is no 417 // need to reprocess it. 418 if (NodesLeadingTo.count(N)) return true; 419 420 // If the first result of this node has been already legalized, then it cannot 421 // reach N. 422 switch (getTypeAction(N->getValueType(0))) { 423 case Legal: 424 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 425 break; 426 case Promote: 427 if (PromotedNodes.count(SDOperand(N, 0))) return false; 428 break; 429 case Expand: 430 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 431 break; 432 } 433 434 // Okay, this node has not already been legalized. Check and legalize all 435 // operands. If none lead to Dest, then we can legalize this node. 436 bool OperandsLeadToDest = false; 437 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 438 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 439 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 440 441 if (OperandsLeadToDest) { 442 NodesLeadingTo.insert(N); 443 return true; 444 } 445 446 // Okay, this node looks safe, legalize it and return false. 447 HandleOp(SDOperand(N, 0)); 448 return false; 449} 450 451/// HandleOp - Legalize, Promote, or Expand the specified operand as 452/// appropriate for its type. 453void SelectionDAGLegalize::HandleOp(SDOperand Op) { 454 MVT::ValueType VT = Op.getValueType(); 455 switch (getTypeAction(VT)) { 456 default: assert(0 && "Bad type action!"); 457 case Legal: (void)LegalizeOp(Op); break; 458 case Promote: (void)PromoteOp(Op); break; 459 case Expand: 460 if (!MVT::isVector(VT)) { 461 // If this is an illegal scalar, expand it into its two component 462 // pieces. 463 SDOperand X, Y; 464 if (Op.getOpcode() == ISD::TargetConstant) 465 break; // Allow illegal target nodes. 466 ExpandOp(Op, X, Y); 467 } else if (MVT::getVectorNumElements(VT) == 1) { 468 // If this is an illegal single element vector, convert it to a 469 // scalar operation. 470 (void)ScalarizeVectorOp(Op); 471 } else { 472 // Otherwise, this is an illegal multiple element vector. 473 // Split it in half and legalize both parts. 474 SDOperand X, Y; 475 SplitVectorOp(Op, X, Y); 476 } 477 break; 478 } 479} 480 481/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 482/// a load from the constant pool. 483static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 484 SelectionDAG &DAG, TargetLowering &TLI) { 485 bool Extend = false; 486 487 // If a FP immediate is precise when represented as a float and if the 488 // target can do an extending load from float to double, we put it into 489 // the constant pool as a float, even if it's is statically typed as a 490 // double. 491 MVT::ValueType VT = CFP->getValueType(0); 492 bool isDouble = VT == MVT::f64; 493 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT), 494 CFP->getValueAPF()); 495 if (!UseCP) { 496 if (VT!=MVT::f64 && VT!=MVT::f32) 497 assert(0 && "Invalid type expansion"); 498 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(), 499 isDouble ? MVT::i64 : MVT::i32); 500 } 501 502 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) && 503 // Only do this if the target has a native EXTLOAD instruction from f32. 504 // Do not try to be clever about long doubles (so far) 505 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 506 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); 507 VT = MVT::f32; 508 Extend = true; 509 } 510 511 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 512 if (Extend) { 513 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 514 CPIdx, NULL, 0, MVT::f32); 515 } else { 516 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 517 } 518} 519 520 521/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 522/// operations. 523static 524SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 525 SelectionDAG &DAG, TargetLowering &TLI) { 526 MVT::ValueType VT = Node->getValueType(0); 527 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 528 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 529 "fcopysign expansion only supported for f32 and f64"); 530 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 531 532 // First get the sign bit of second operand. 533 SDOperand Mask1 = (SrcVT == MVT::f64) 534 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 535 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 536 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 537 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 538 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 539 // Shift right or sign-extend it if the two operands have different types. 540 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 541 if (SizeDiff > 0) { 542 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 543 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 544 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 545 } else if (SizeDiff < 0) 546 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 547 548 // Clear the sign bit of first operand. 549 SDOperand Mask2 = (VT == MVT::f64) 550 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 551 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 552 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 553 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 554 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 555 556 // Or the value with the sign bit. 557 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 558 return Result; 559} 560 561/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 562static 563SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 564 TargetLowering &TLI) { 565 SDOperand Chain = ST->getChain(); 566 SDOperand Ptr = ST->getBasePtr(); 567 SDOperand Val = ST->getValue(); 568 MVT::ValueType VT = Val.getValueType(); 569 int Alignment = ST->getAlignment(); 570 int SVOffset = ST->getSrcValueOffset(); 571 if (MVT::isFloatingPoint(ST->getStoredVT())) { 572 // Expand to a bitconvert of the value to the integer type of the 573 // same size, then a (misaligned) int store. 574 MVT::ValueType intVT; 575 if (VT==MVT::f64) 576 intVT = MVT::i64; 577 else if (VT==MVT::f32) 578 intVT = MVT::i32; 579 else 580 assert(0 && "Unaligned load of unsupported floating point type"); 581 582 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 583 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 584 SVOffset, ST->isVolatile(), Alignment); 585 } 586 assert(MVT::isInteger(ST->getStoredVT()) && 587 "Unaligned store of unknown type."); 588 // Get the half-size VT 589 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1; 590 int NumBits = MVT::getSizeInBits(NewStoredVT); 591 int IncrementSize = NumBits / 8; 592 593 // Divide the stored value in two parts. 594 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 595 SDOperand Lo = Val; 596 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 597 598 // Store the two parts 599 SDOperand Store1, Store2; 600 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 601 ST->getSrcValue(), SVOffset, NewStoredVT, 602 ST->isVolatile(), Alignment); 603 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 604 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 605 Alignment = MinAlign(Alignment, IncrementSize); 606 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 607 ST->getSrcValue(), SVOffset + IncrementSize, 608 NewStoredVT, ST->isVolatile(), Alignment); 609 610 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 611} 612 613/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 614static 615SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 616 TargetLowering &TLI) { 617 int SVOffset = LD->getSrcValueOffset(); 618 SDOperand Chain = LD->getChain(); 619 SDOperand Ptr = LD->getBasePtr(); 620 MVT::ValueType VT = LD->getValueType(0); 621 MVT::ValueType LoadedVT = LD->getLoadedVT(); 622 if (MVT::isFloatingPoint(VT)) { 623 // Expand to a (misaligned) integer load of the same size, 624 // then bitconvert to floating point. 625 MVT::ValueType intVT; 626 if (LoadedVT==MVT::f64) 627 intVT = MVT::i64; 628 else if (LoadedVT==MVT::f32) 629 intVT = MVT::i32; 630 else 631 assert(0 && "Unaligned load of unsupported floating point type"); 632 633 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 634 SVOffset, LD->isVolatile(), 635 LD->getAlignment()); 636 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 637 if (LoadedVT != VT) 638 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 639 640 SDOperand Ops[] = { Result, Chain }; 641 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 642 Ops, 2); 643 } 644 assert(MVT::isInteger(LoadedVT) && "Unaligned load of unsupported type."); 645 MVT::ValueType NewLoadedVT = LoadedVT - 1; 646 int NumBits = MVT::getSizeInBits(NewLoadedVT); 647 int Alignment = LD->getAlignment(); 648 int IncrementSize = NumBits / 8; 649 ISD::LoadExtType HiExtType = LD->getExtensionType(); 650 651 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 652 if (HiExtType == ISD::NON_EXTLOAD) 653 HiExtType = ISD::ZEXTLOAD; 654 655 // Load the value in two parts 656 SDOperand Lo, Hi; 657 if (TLI.isLittleEndian()) { 658 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 659 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 660 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 661 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 662 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 663 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 664 MinAlign(Alignment, IncrementSize)); 665 } else { 666 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 667 NewLoadedVT,LD->isVolatile(), Alignment); 668 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 669 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 670 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 671 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 672 MinAlign(Alignment, IncrementSize)); 673 } 674 675 // aggregate the two parts 676 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 677 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 678 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 679 680 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 681 Hi.getValue(1)); 682 683 SDOperand Ops[] = { Result, TF }; 684 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 685} 686 687/// UnrollVectorOp - We know that the given vector has a legal type, however 688/// the operation it performs is not legal and is an operation that we have 689/// no way of lowering. "Unroll" the vector, splitting out the scalars and 690/// operating on each element individually. 691SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { 692 MVT::ValueType VT = Op.getValueType(); 693 assert(isTypeLegal(VT) && 694 "Caller should expand or promote operands that are not legal!"); 695 assert(Op.Val->getNumValues() == 1 && 696 "Can't unroll a vector with multiple results!"); 697 unsigned NE = MVT::getVectorNumElements(VT); 698 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 699 700 SmallVector<SDOperand, 8> Scalars; 701 SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); 702 for (unsigned i = 0; i != NE; ++i) { 703 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 704 SDOperand Operand = Op.getOperand(j); 705 MVT::ValueType OperandVT = Operand.getValueType(); 706 if (MVT::isVector(OperandVT)) { 707 // A vector operand; extract a single element. 708 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT); 709 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 710 OperandEltVT, 711 Operand, 712 DAG.getConstant(i, MVT::i32)); 713 } else { 714 // A scalar operand; just use it as is. 715 Operands[j] = Operand; 716 } 717 } 718 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 719 &Operands[0], Operands.size())); 720 } 721 722 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 723} 724 725/// LegalizeOp - We know that the specified value has a legal type, and 726/// that its operands are legal. Now ensure that the operation itself 727/// is legal, recursively ensuring that the operands' operations remain 728/// legal. 729SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 730 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 731 return Op; 732 733 assert(isTypeLegal(Op.getValueType()) && 734 "Caller should expand or promote operands that are not legal!"); 735 SDNode *Node = Op.Val; 736 737 // If this operation defines any values that cannot be represented in a 738 // register on this target, make sure to expand or promote them. 739 if (Node->getNumValues() > 1) { 740 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 741 if (getTypeAction(Node->getValueType(i)) != Legal) { 742 HandleOp(Op.getValue(i)); 743 assert(LegalizedNodes.count(Op) && 744 "Handling didn't add legal operands!"); 745 return LegalizedNodes[Op]; 746 } 747 } 748 749 // Note that LegalizeOp may be reentered even from single-use nodes, which 750 // means that we always must cache transformed nodes. 751 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 752 if (I != LegalizedNodes.end()) return I->second; 753 754 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 755 SDOperand Result = Op; 756 bool isCustom = false; 757 758 switch (Node->getOpcode()) { 759 case ISD::FrameIndex: 760 case ISD::EntryToken: 761 case ISD::Register: 762 case ISD::BasicBlock: 763 case ISD::TargetFrameIndex: 764 case ISD::TargetJumpTable: 765 case ISD::TargetConstant: 766 case ISD::TargetConstantFP: 767 case ISD::TargetConstantPool: 768 case ISD::TargetGlobalAddress: 769 case ISD::TargetGlobalTLSAddress: 770 case ISD::TargetExternalSymbol: 771 case ISD::VALUETYPE: 772 case ISD::SRCVALUE: 773 case ISD::STRING: 774 case ISD::CONDCODE: 775 // Primitives must all be legal. 776 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 777 "This must be legal!"); 778 break; 779 default: 780 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 781 // If this is a target node, legalize it by legalizing the operands then 782 // passing it through. 783 SmallVector<SDOperand, 8> Ops; 784 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 785 Ops.push_back(LegalizeOp(Node->getOperand(i))); 786 787 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 788 789 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 790 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 791 return Result.getValue(Op.ResNo); 792 } 793 // Otherwise this is an unhandled builtin node. splat. 794#ifndef NDEBUG 795 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 796#endif 797 assert(0 && "Do not know how to legalize this operator!"); 798 abort(); 799 case ISD::GLOBAL_OFFSET_TABLE: 800 case ISD::GlobalAddress: 801 case ISD::GlobalTLSAddress: 802 case ISD::ExternalSymbol: 803 case ISD::ConstantPool: 804 case ISD::JumpTable: // Nothing to do. 805 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 806 default: assert(0 && "This action is not supported yet!"); 807 case TargetLowering::Custom: 808 Tmp1 = TLI.LowerOperation(Op, DAG); 809 if (Tmp1.Val) Result = Tmp1; 810 // FALLTHROUGH if the target doesn't want to lower this op after all. 811 case TargetLowering::Legal: 812 break; 813 } 814 break; 815 case ISD::FRAMEADDR: 816 case ISD::RETURNADDR: 817 // The only option for these nodes is to custom lower them. If the target 818 // does not custom lower them, then return zero. 819 Tmp1 = TLI.LowerOperation(Op, DAG); 820 if (Tmp1.Val) 821 Result = Tmp1; 822 else 823 Result = DAG.getConstant(0, TLI.getPointerTy()); 824 break; 825 case ISD::FRAME_TO_ARGS_OFFSET: { 826 MVT::ValueType VT = Node->getValueType(0); 827 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 828 default: assert(0 && "This action is not supported yet!"); 829 case TargetLowering::Custom: 830 Result = TLI.LowerOperation(Op, DAG); 831 if (Result.Val) break; 832 // Fall Thru 833 case TargetLowering::Legal: 834 Result = DAG.getConstant(0, VT); 835 break; 836 } 837 } 838 break; 839 case ISD::EXCEPTIONADDR: { 840 Tmp1 = LegalizeOp(Node->getOperand(0)); 841 MVT::ValueType VT = Node->getValueType(0); 842 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 843 default: assert(0 && "This action is not supported yet!"); 844 case TargetLowering::Expand: { 845 unsigned Reg = TLI.getExceptionAddressRegister(); 846 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo); 847 } 848 break; 849 case TargetLowering::Custom: 850 Result = TLI.LowerOperation(Op, DAG); 851 if (Result.Val) break; 852 // Fall Thru 853 case TargetLowering::Legal: { 854 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 855 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 856 Ops, 2).getValue(Op.ResNo); 857 break; 858 } 859 } 860 } 861 break; 862 case ISD::EHSELECTION: { 863 Tmp1 = LegalizeOp(Node->getOperand(0)); 864 Tmp2 = LegalizeOp(Node->getOperand(1)); 865 MVT::ValueType VT = Node->getValueType(0); 866 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 867 default: assert(0 && "This action is not supported yet!"); 868 case TargetLowering::Expand: { 869 unsigned Reg = TLI.getExceptionSelectorRegister(); 870 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo); 871 } 872 break; 873 case TargetLowering::Custom: 874 Result = TLI.LowerOperation(Op, DAG); 875 if (Result.Val) break; 876 // Fall Thru 877 case TargetLowering::Legal: { 878 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 879 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 880 Ops, 2).getValue(Op.ResNo); 881 break; 882 } 883 } 884 } 885 break; 886 case ISD::EH_RETURN: { 887 MVT::ValueType VT = Node->getValueType(0); 888 // The only "good" option for this node is to custom lower it. 889 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 890 default: assert(0 && "This action is not supported at all!"); 891 case TargetLowering::Custom: 892 Result = TLI.LowerOperation(Op, DAG); 893 if (Result.Val) break; 894 // Fall Thru 895 case TargetLowering::Legal: 896 // Target does not know, how to lower this, lower to noop 897 Result = LegalizeOp(Node->getOperand(0)); 898 break; 899 } 900 } 901 break; 902 case ISD::AssertSext: 903 case ISD::AssertZext: 904 Tmp1 = LegalizeOp(Node->getOperand(0)); 905 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 906 break; 907 case ISD::MERGE_VALUES: 908 // Legalize eliminates MERGE_VALUES nodes. 909 Result = Node->getOperand(Op.ResNo); 910 break; 911 case ISD::CopyFromReg: 912 Tmp1 = LegalizeOp(Node->getOperand(0)); 913 Result = Op.getValue(0); 914 if (Node->getNumValues() == 2) { 915 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 916 } else { 917 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 918 if (Node->getNumOperands() == 3) { 919 Tmp2 = LegalizeOp(Node->getOperand(2)); 920 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 921 } else { 922 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 923 } 924 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 925 } 926 // Since CopyFromReg produces two values, make sure to remember that we 927 // legalized both of them. 928 AddLegalizedOperand(Op.getValue(0), Result); 929 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 930 return Result.getValue(Op.ResNo); 931 case ISD::UNDEF: { 932 MVT::ValueType VT = Op.getValueType(); 933 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 934 default: assert(0 && "This action is not supported yet!"); 935 case TargetLowering::Expand: 936 if (MVT::isInteger(VT)) 937 Result = DAG.getConstant(0, VT); 938 else if (MVT::isFloatingPoint(VT)) 939 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)), 940 VT); 941 else 942 assert(0 && "Unknown value type!"); 943 break; 944 case TargetLowering::Legal: 945 break; 946 } 947 break; 948 } 949 950 case ISD::INTRINSIC_W_CHAIN: 951 case ISD::INTRINSIC_WO_CHAIN: 952 case ISD::INTRINSIC_VOID: { 953 SmallVector<SDOperand, 8> Ops; 954 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 955 Ops.push_back(LegalizeOp(Node->getOperand(i))); 956 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 957 958 // Allow the target to custom lower its intrinsics if it wants to. 959 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 960 TargetLowering::Custom) { 961 Tmp3 = TLI.LowerOperation(Result, DAG); 962 if (Tmp3.Val) Result = Tmp3; 963 } 964 965 if (Result.Val->getNumValues() == 1) break; 966 967 // Must have return value and chain result. 968 assert(Result.Val->getNumValues() == 2 && 969 "Cannot return more than two values!"); 970 971 // Since loads produce two values, make sure to remember that we 972 // legalized both of them. 973 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 974 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 975 return Result.getValue(Op.ResNo); 976 } 977 978 case ISD::LOCATION: 979 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 980 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 981 982 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 983 case TargetLowering::Promote: 984 default: assert(0 && "This action is not supported yet!"); 985 case TargetLowering::Expand: { 986 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 987 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 988 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 989 990 if (MMI && (useDEBUG_LOC || useLABEL)) { 991 const std::string &FName = 992 cast<StringSDNode>(Node->getOperand(3))->getValue(); 993 const std::string &DirName = 994 cast<StringSDNode>(Node->getOperand(4))->getValue(); 995 unsigned SrcFile = MMI->RecordSource(DirName, FName); 996 997 SmallVector<SDOperand, 8> Ops; 998 Ops.push_back(Tmp1); // chain 999 SDOperand LineOp = Node->getOperand(1); 1000 SDOperand ColOp = Node->getOperand(2); 1001 1002 if (useDEBUG_LOC) { 1003 Ops.push_back(LineOp); // line # 1004 Ops.push_back(ColOp); // col # 1005 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 1006 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 1007 } else { 1008 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 1009 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 1010 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile); 1011 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 1012 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size()); 1013 } 1014 } else { 1015 Result = Tmp1; // chain 1016 } 1017 break; 1018 } 1019 case TargetLowering::Legal: 1020 if (Tmp1 != Node->getOperand(0) || 1021 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 1022 SmallVector<SDOperand, 8> Ops; 1023 Ops.push_back(Tmp1); 1024 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 1025 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1026 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1027 } else { 1028 // Otherwise promote them. 1029 Ops.push_back(PromoteOp(Node->getOperand(1))); 1030 Ops.push_back(PromoteOp(Node->getOperand(2))); 1031 } 1032 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1033 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1034 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1035 } 1036 break; 1037 } 1038 break; 1039 1040 case ISD::DEBUG_LOC: 1041 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1042 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1043 default: assert(0 && "This action is not supported yet!"); 1044 case TargetLowering::Legal: 1045 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1046 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1047 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1048 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1049 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1050 break; 1051 } 1052 break; 1053 1054 case ISD::LABEL: 1055 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!"); 1056 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 1057 default: assert(0 && "This action is not supported yet!"); 1058 case TargetLowering::Legal: 1059 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1060 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 1061 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1062 break; 1063 case TargetLowering::Expand: 1064 Result = LegalizeOp(Node->getOperand(0)); 1065 break; 1066 } 1067 break; 1068 1069 case ISD::Constant: { 1070 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1071 unsigned opAction = 1072 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1073 1074 // We know we don't need to expand constants here, constants only have one 1075 // value and we check that it is fine above. 1076 1077 if (opAction == TargetLowering::Custom) { 1078 Tmp1 = TLI.LowerOperation(Result, DAG); 1079 if (Tmp1.Val) 1080 Result = Tmp1; 1081 } 1082 break; 1083 } 1084 case ISD::ConstantFP: { 1085 // Spill FP immediates to the constant pool if the target cannot directly 1086 // codegen them. Targets often have some immediate values that can be 1087 // efficiently generated into an FP register without a load. We explicitly 1088 // leave these constants as ConstantFP nodes for the target to deal with. 1089 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1090 1091 // Check to see if this FP immediate is already legal. 1092 bool isLegal = false; 1093 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1094 E = TLI.legal_fpimm_end(); I != E; ++I) 1095 if (CFP->isExactlyValue(*I)) { 1096 isLegal = true; 1097 break; 1098 } 1099 1100 // If this is a legal constant, turn it into a TargetConstantFP node. 1101 if (isLegal) { 1102 Result = DAG.getTargetConstantFP(CFP->getValueAPF(), 1103 CFP->getValueType(0)); 1104 break; 1105 } 1106 1107 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1108 default: assert(0 && "This action is not supported yet!"); 1109 case TargetLowering::Custom: 1110 Tmp3 = TLI.LowerOperation(Result, DAG); 1111 if (Tmp3.Val) { 1112 Result = Tmp3; 1113 break; 1114 } 1115 // FALLTHROUGH 1116 case TargetLowering::Expand: 1117 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1118 } 1119 break; 1120 } 1121 case ISD::TokenFactor: 1122 if (Node->getNumOperands() == 2) { 1123 Tmp1 = LegalizeOp(Node->getOperand(0)); 1124 Tmp2 = LegalizeOp(Node->getOperand(1)); 1125 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1126 } else if (Node->getNumOperands() == 3) { 1127 Tmp1 = LegalizeOp(Node->getOperand(0)); 1128 Tmp2 = LegalizeOp(Node->getOperand(1)); 1129 Tmp3 = LegalizeOp(Node->getOperand(2)); 1130 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1131 } else { 1132 SmallVector<SDOperand, 8> Ops; 1133 // Legalize the operands. 1134 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1135 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1136 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1137 } 1138 break; 1139 1140 case ISD::FORMAL_ARGUMENTS: 1141 case ISD::CALL: 1142 // The only option for this is to custom lower it. 1143 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1144 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1145 1146 // The number of incoming and outgoing values should match; unless the final 1147 // outgoing value is a flag. 1148 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || 1149 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && 1150 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == 1151 MVT::Flag)) && 1152 "Lowering call/formal_arguments produced unexpected # results!"); 1153 1154 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1155 // remember that we legalized all of them, so it doesn't get relegalized. 1156 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1157 if (Tmp3.Val->getValueType(i) == MVT::Flag) 1158 continue; 1159 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1160 if (Op.ResNo == i) 1161 Tmp2 = Tmp1; 1162 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1163 } 1164 return Tmp2; 1165 case ISD::EXTRACT_SUBREG: { 1166 Tmp1 = LegalizeOp(Node->getOperand(0)); 1167 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1168 assert(idx && "Operand must be a constant"); 1169 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1170 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1171 } 1172 break; 1173 case ISD::INSERT_SUBREG: { 1174 Tmp1 = LegalizeOp(Node->getOperand(0)); 1175 Tmp2 = LegalizeOp(Node->getOperand(1)); 1176 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1177 assert(idx && "Operand must be a constant"); 1178 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1179 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1180 } 1181 break; 1182 case ISD::BUILD_VECTOR: 1183 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1184 default: assert(0 && "This action is not supported yet!"); 1185 case TargetLowering::Custom: 1186 Tmp3 = TLI.LowerOperation(Result, DAG); 1187 if (Tmp3.Val) { 1188 Result = Tmp3; 1189 break; 1190 } 1191 // FALLTHROUGH 1192 case TargetLowering::Expand: 1193 Result = ExpandBUILD_VECTOR(Result.Val); 1194 break; 1195 } 1196 break; 1197 case ISD::INSERT_VECTOR_ELT: 1198 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1199 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 1200 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1201 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1202 1203 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1204 Node->getValueType(0))) { 1205 default: assert(0 && "This action is not supported yet!"); 1206 case TargetLowering::Legal: 1207 break; 1208 case TargetLowering::Custom: 1209 Tmp3 = TLI.LowerOperation(Result, DAG); 1210 if (Tmp3.Val) { 1211 Result = Tmp3; 1212 break; 1213 } 1214 // FALLTHROUGH 1215 case TargetLowering::Expand: { 1216 // If the insert index is a constant, codegen this as a scalar_to_vector, 1217 // then a shuffle that inserts it into the right position in the vector. 1218 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1219 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1220 Tmp1.getValueType(), Tmp2); 1221 1222 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1223 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1224 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); 1225 1226 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 1227 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 1228 // the RHS. 1229 SmallVector<SDOperand, 8> ShufOps; 1230 for (unsigned i = 0; i != NumElts; ++i) { 1231 if (i != InsertPos->getValue()) 1232 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1233 else 1234 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1235 } 1236 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1237 &ShufOps[0], ShufOps.size()); 1238 1239 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1240 Tmp1, ScVec, ShufMask); 1241 Result = LegalizeOp(Result); 1242 break; 1243 } 1244 1245 // If the target doesn't support this, we have to spill the input vector 1246 // to a temporary stack slot, update the element, then reload it. This is 1247 // badness. We could also load the value into a vector register (either 1248 // with a "move to register" or "extload into register" instruction, then 1249 // permute it into place, if the idx is a constant and if the idx is 1250 // supported by the target. 1251 MVT::ValueType VT = Tmp1.getValueType(); 1252 MVT::ValueType EltVT = Tmp2.getValueType(); 1253 MVT::ValueType IdxVT = Tmp3.getValueType(); 1254 MVT::ValueType PtrVT = TLI.getPointerTy(); 1255 SDOperand StackPtr = DAG.CreateStackTemporary(VT); 1256 // Store the vector. 1257 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); 1258 1259 // Truncate or zero extend offset to target pointer type. 1260 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1261 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 1262 // Add the offset to the index. 1263 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 1264 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 1265 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 1266 // Store the scalar value. 1267 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); 1268 // Load the updated vector. 1269 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); 1270 break; 1271 } 1272 } 1273 break; 1274 case ISD::SCALAR_TO_VECTOR: 1275 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1276 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1277 break; 1278 } 1279 1280 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1281 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1282 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1283 Node->getValueType(0))) { 1284 default: assert(0 && "This action is not supported yet!"); 1285 case TargetLowering::Legal: 1286 break; 1287 case TargetLowering::Custom: 1288 Tmp3 = TLI.LowerOperation(Result, DAG); 1289 if (Tmp3.Val) { 1290 Result = Tmp3; 1291 break; 1292 } 1293 // FALLTHROUGH 1294 case TargetLowering::Expand: 1295 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1296 break; 1297 } 1298 break; 1299 case ISD::VECTOR_SHUFFLE: 1300 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1301 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1302 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1303 1304 // Allow targets to custom lower the SHUFFLEs they support. 1305 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1306 default: assert(0 && "Unknown operation action!"); 1307 case TargetLowering::Legal: 1308 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1309 "vector shuffle should not be created if not legal!"); 1310 break; 1311 case TargetLowering::Custom: 1312 Tmp3 = TLI.LowerOperation(Result, DAG); 1313 if (Tmp3.Val) { 1314 Result = Tmp3; 1315 break; 1316 } 1317 // FALLTHROUGH 1318 case TargetLowering::Expand: { 1319 MVT::ValueType VT = Node->getValueType(0); 1320 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1321 MVT::ValueType PtrVT = TLI.getPointerTy(); 1322 SDOperand Mask = Node->getOperand(2); 1323 unsigned NumElems = Mask.getNumOperands(); 1324 SmallVector<SDOperand,8> Ops; 1325 for (unsigned i = 0; i != NumElems; ++i) { 1326 SDOperand Arg = Mask.getOperand(i); 1327 if (Arg.getOpcode() == ISD::UNDEF) { 1328 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1329 } else { 1330 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1331 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1332 if (Idx < NumElems) 1333 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1334 DAG.getConstant(Idx, PtrVT))); 1335 else 1336 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1337 DAG.getConstant(Idx - NumElems, PtrVT))); 1338 } 1339 } 1340 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1341 break; 1342 } 1343 case TargetLowering::Promote: { 1344 // Change base type to a different vector type. 1345 MVT::ValueType OVT = Node->getValueType(0); 1346 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1347 1348 // Cast the two input vectors. 1349 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1350 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1351 1352 // Convert the shuffle mask to the right # elements. 1353 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1354 assert(Tmp3.Val && "Shuffle not legal?"); 1355 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1356 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1357 break; 1358 } 1359 } 1360 break; 1361 1362 case ISD::EXTRACT_VECTOR_ELT: 1363 Tmp1 = Node->getOperand(0); 1364 Tmp2 = LegalizeOp(Node->getOperand(1)); 1365 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1366 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1367 break; 1368 1369 case ISD::EXTRACT_SUBVECTOR: 1370 Tmp1 = Node->getOperand(0); 1371 Tmp2 = LegalizeOp(Node->getOperand(1)); 1372 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1373 Result = ExpandEXTRACT_SUBVECTOR(Result); 1374 break; 1375 1376 case ISD::CALLSEQ_START: { 1377 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1378 1379 // Recursively Legalize all of the inputs of the call end that do not lead 1380 // to this call start. This ensures that any libcalls that need be inserted 1381 // are inserted *before* the CALLSEQ_START. 1382 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1383 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1384 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1385 NodesLeadingTo); 1386 } 1387 1388 // Now that we legalized all of the inputs (which may have inserted 1389 // libcalls) create the new CALLSEQ_START node. 1390 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1391 1392 // Merge in the last call, to ensure that this call start after the last 1393 // call ended. 1394 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1395 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1396 Tmp1 = LegalizeOp(Tmp1); 1397 } 1398 1399 // Do not try to legalize the target-specific arguments (#1+). 1400 if (Tmp1 != Node->getOperand(0)) { 1401 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1402 Ops[0] = Tmp1; 1403 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1404 } 1405 1406 // Remember that the CALLSEQ_START is legalized. 1407 AddLegalizedOperand(Op.getValue(0), Result); 1408 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1409 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1410 1411 // Now that the callseq_start and all of the non-call nodes above this call 1412 // sequence have been legalized, legalize the call itself. During this 1413 // process, no libcalls can/will be inserted, guaranteeing that no calls 1414 // can overlap. 1415 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1416 SDOperand InCallSEQ = LastCALLSEQ_END; 1417 // Note that we are selecting this call! 1418 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1419 IsLegalizingCall = true; 1420 1421 // Legalize the call, starting from the CALLSEQ_END. 1422 LegalizeOp(LastCALLSEQ_END); 1423 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1424 return Result; 1425 } 1426 case ISD::CALLSEQ_END: 1427 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1428 // will cause this node to be legalized as well as handling libcalls right. 1429 if (LastCALLSEQ_END.Val != Node) { 1430 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1431 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1432 assert(I != LegalizedNodes.end() && 1433 "Legalizing the call start should have legalized this node!"); 1434 return I->second; 1435 } 1436 1437 // Otherwise, the call start has been legalized and everything is going 1438 // according to plan. Just legalize ourselves normally here. 1439 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1440 // Do not try to legalize the target-specific arguments (#1+), except for 1441 // an optional flag input. 1442 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1443 if (Tmp1 != Node->getOperand(0)) { 1444 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1445 Ops[0] = Tmp1; 1446 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1447 } 1448 } else { 1449 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1450 if (Tmp1 != Node->getOperand(0) || 1451 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1452 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1453 Ops[0] = Tmp1; 1454 Ops.back() = Tmp2; 1455 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1456 } 1457 } 1458 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1459 // This finishes up call legalization. 1460 IsLegalizingCall = false; 1461 1462 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1463 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1464 if (Node->getNumValues() == 2) 1465 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1466 return Result.getValue(Op.ResNo); 1467 case ISD::DYNAMIC_STACKALLOC: { 1468 MVT::ValueType VT = Node->getValueType(0); 1469 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1470 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1471 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1472 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1473 1474 Tmp1 = Result.getValue(0); 1475 Tmp2 = Result.getValue(1); 1476 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1477 default: assert(0 && "This action is not supported yet!"); 1478 case TargetLowering::Expand: { 1479 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1480 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1481 " not tell us which reg is the stack pointer!"); 1482 SDOperand Chain = Tmp1.getOperand(0); 1483 1484 // Chain the dynamic stack allocation so that it doesn't modify the stack 1485 // pointer when other instructions are using the stack. 1486 Chain = DAG.getCALLSEQ_START(Chain, 1487 DAG.getConstant(0, TLI.getPointerTy())); 1488 1489 SDOperand Size = Tmp2.getOperand(1); 1490 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1491 Chain = SP.getValue(1); 1492 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1493 unsigned StackAlign = 1494 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1495 if (Align > StackAlign) 1496 SP = DAG.getNode(ISD::AND, VT, SP, 1497 DAG.getConstant(-(uint64_t)Align, VT)); 1498 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1499 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1500 1501 Tmp2 = 1502 DAG.getCALLSEQ_END(Chain, 1503 DAG.getConstant(0, TLI.getPointerTy()), 1504 DAG.getConstant(0, TLI.getPointerTy()), 1505 SDOperand()); 1506 1507 Tmp1 = LegalizeOp(Tmp1); 1508 Tmp2 = LegalizeOp(Tmp2); 1509 break; 1510 } 1511 case TargetLowering::Custom: 1512 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1513 if (Tmp3.Val) { 1514 Tmp1 = LegalizeOp(Tmp3); 1515 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1516 } 1517 break; 1518 case TargetLowering::Legal: 1519 break; 1520 } 1521 // Since this op produce two values, make sure to remember that we 1522 // legalized both of them. 1523 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1524 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1525 return Op.ResNo ? Tmp2 : Tmp1; 1526 } 1527 case ISD::INLINEASM: { 1528 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1529 bool Changed = false; 1530 // Legalize all of the operands of the inline asm, in case they are nodes 1531 // that need to be expanded or something. Note we skip the asm string and 1532 // all of the TargetConstant flags. 1533 SDOperand Op = LegalizeOp(Ops[0]); 1534 Changed = Op != Ops[0]; 1535 Ops[0] = Op; 1536 1537 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1538 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1539 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1540 for (++i; NumVals; ++i, --NumVals) { 1541 SDOperand Op = LegalizeOp(Ops[i]); 1542 if (Op != Ops[i]) { 1543 Changed = true; 1544 Ops[i] = Op; 1545 } 1546 } 1547 } 1548 1549 if (HasInFlag) { 1550 Op = LegalizeOp(Ops.back()); 1551 Changed |= Op != Ops.back(); 1552 Ops.back() = Op; 1553 } 1554 1555 if (Changed) 1556 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1557 1558 // INLINE asm returns a chain and flag, make sure to add both to the map. 1559 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1560 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1561 return Result.getValue(Op.ResNo); 1562 } 1563 case ISD::BR: 1564 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1565 // Ensure that libcalls are emitted before a branch. 1566 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1567 Tmp1 = LegalizeOp(Tmp1); 1568 LastCALLSEQ_END = DAG.getEntryNode(); 1569 1570 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1571 break; 1572 case ISD::BRIND: 1573 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1574 // Ensure that libcalls are emitted before a branch. 1575 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1576 Tmp1 = LegalizeOp(Tmp1); 1577 LastCALLSEQ_END = DAG.getEntryNode(); 1578 1579 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1580 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1581 case Legal: 1582 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1583 break; 1584 } 1585 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1586 break; 1587 case ISD::BR_JT: 1588 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1589 // Ensure that libcalls are emitted before a branch. 1590 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1591 Tmp1 = LegalizeOp(Tmp1); 1592 LastCALLSEQ_END = DAG.getEntryNode(); 1593 1594 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1595 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1596 1597 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1598 default: assert(0 && "This action is not supported yet!"); 1599 case TargetLowering::Legal: break; 1600 case TargetLowering::Custom: 1601 Tmp1 = TLI.LowerOperation(Result, DAG); 1602 if (Tmp1.Val) Result = Tmp1; 1603 break; 1604 case TargetLowering::Expand: { 1605 SDOperand Chain = Result.getOperand(0); 1606 SDOperand Table = Result.getOperand(1); 1607 SDOperand Index = Result.getOperand(2); 1608 1609 MVT::ValueType PTy = TLI.getPointerTy(); 1610 MachineFunction &MF = DAG.getMachineFunction(); 1611 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1612 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1613 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1614 1615 SDOperand LD; 1616 switch (EntrySize) { 1617 default: assert(0 && "Size of jump table not supported yet."); break; 1618 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; 1619 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; 1620 } 1621 1622 Addr = LD; 1623 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1624 // For PIC, the sequence is: 1625 // BRIND(load(Jumptable + index) + RelocBase) 1626 // RelocBase can be JumpTable, GOT or some sort of global base. 1627 if (PTy != MVT::i32) 1628 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1629 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1630 TLI.getPICJumpTableRelocBase(Table, DAG)); 1631 } 1632 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1633 } 1634 } 1635 break; 1636 case ISD::BRCOND: 1637 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1638 // Ensure that libcalls are emitted before a return. 1639 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1640 Tmp1 = LegalizeOp(Tmp1); 1641 LastCALLSEQ_END = DAG.getEntryNode(); 1642 1643 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1644 case Expand: assert(0 && "It's impossible to expand bools"); 1645 case Legal: 1646 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1647 break; 1648 case Promote: 1649 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1650 1651 // The top bits of the promoted condition are not necessarily zero, ensure 1652 // that the value is properly zero extended. 1653 if (!DAG.MaskedValueIsZero(Tmp2, 1654 MVT::getIntVTBitMask(Tmp2.getValueType())^1)) 1655 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1656 break; 1657 } 1658 1659 // Basic block destination (Op#2) is always legal. 1660 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1661 1662 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1663 default: assert(0 && "This action is not supported yet!"); 1664 case TargetLowering::Legal: break; 1665 case TargetLowering::Custom: 1666 Tmp1 = TLI.LowerOperation(Result, DAG); 1667 if (Tmp1.Val) Result = Tmp1; 1668 break; 1669 case TargetLowering::Expand: 1670 // Expand brcond's setcc into its constituent parts and create a BR_CC 1671 // Node. 1672 if (Tmp2.getOpcode() == ISD::SETCC) { 1673 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1674 Tmp2.getOperand(0), Tmp2.getOperand(1), 1675 Node->getOperand(2)); 1676 } else { 1677 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1678 DAG.getCondCode(ISD::SETNE), Tmp2, 1679 DAG.getConstant(0, Tmp2.getValueType()), 1680 Node->getOperand(2)); 1681 } 1682 break; 1683 } 1684 break; 1685 case ISD::BR_CC: 1686 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1687 // Ensure that libcalls are emitted before a branch. 1688 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1689 Tmp1 = LegalizeOp(Tmp1); 1690 Tmp2 = Node->getOperand(2); // LHS 1691 Tmp3 = Node->getOperand(3); // RHS 1692 Tmp4 = Node->getOperand(1); // CC 1693 1694 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1695 LastCALLSEQ_END = DAG.getEntryNode(); 1696 1697 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1698 // the LHS is a legal SETCC itself. In this case, we need to compare 1699 // the result against zero to select between true and false values. 1700 if (Tmp3.Val == 0) { 1701 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1702 Tmp4 = DAG.getCondCode(ISD::SETNE); 1703 } 1704 1705 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1706 Node->getOperand(4)); 1707 1708 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1709 default: assert(0 && "Unexpected action for BR_CC!"); 1710 case TargetLowering::Legal: break; 1711 case TargetLowering::Custom: 1712 Tmp4 = TLI.LowerOperation(Result, DAG); 1713 if (Tmp4.Val) Result = Tmp4; 1714 break; 1715 } 1716 break; 1717 case ISD::LOAD: { 1718 LoadSDNode *LD = cast<LoadSDNode>(Node); 1719 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1720 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1721 1722 ISD::LoadExtType ExtType = LD->getExtensionType(); 1723 if (ExtType == ISD::NON_EXTLOAD) { 1724 MVT::ValueType VT = Node->getValueType(0); 1725 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1726 Tmp3 = Result.getValue(0); 1727 Tmp4 = Result.getValue(1); 1728 1729 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1730 default: assert(0 && "This action is not supported yet!"); 1731 case TargetLowering::Legal: 1732 // If this is an unaligned load and the target doesn't support it, 1733 // expand it. 1734 if (!TLI.allowsUnalignedMemoryAccesses()) { 1735 unsigned ABIAlignment = TLI.getTargetData()-> 1736 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1737 if (LD->getAlignment() < ABIAlignment){ 1738 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1739 TLI); 1740 Tmp3 = Result.getOperand(0); 1741 Tmp4 = Result.getOperand(1); 1742 Tmp3 = LegalizeOp(Tmp3); 1743 Tmp4 = LegalizeOp(Tmp4); 1744 } 1745 } 1746 break; 1747 case TargetLowering::Custom: 1748 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1749 if (Tmp1.Val) { 1750 Tmp3 = LegalizeOp(Tmp1); 1751 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1752 } 1753 break; 1754 case TargetLowering::Promote: { 1755 // Only promote a load of vector type to another. 1756 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1757 // Change base type to a different vector type. 1758 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1759 1760 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1761 LD->getSrcValueOffset(), 1762 LD->isVolatile(), LD->getAlignment()); 1763 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1764 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1765 break; 1766 } 1767 } 1768 // Since loads produce two values, make sure to remember that we 1769 // legalized both of them. 1770 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1771 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1772 return Op.ResNo ? Tmp4 : Tmp3; 1773 } else { 1774 MVT::ValueType SrcVT = LD->getLoadedVT(); 1775 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1776 default: assert(0 && "This action is not supported yet!"); 1777 case TargetLowering::Promote: 1778 assert(SrcVT == MVT::i1 && 1779 "Can only promote extending LOAD from i1 -> i8!"); 1780 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1781 LD->getSrcValue(), LD->getSrcValueOffset(), 1782 MVT::i8, LD->isVolatile(), LD->getAlignment()); 1783 Tmp1 = Result.getValue(0); 1784 Tmp2 = Result.getValue(1); 1785 break; 1786 case TargetLowering::Custom: 1787 isCustom = true; 1788 // FALLTHROUGH 1789 case TargetLowering::Legal: 1790 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1791 Tmp1 = Result.getValue(0); 1792 Tmp2 = Result.getValue(1); 1793 1794 if (isCustom) { 1795 Tmp3 = TLI.LowerOperation(Result, DAG); 1796 if (Tmp3.Val) { 1797 Tmp1 = LegalizeOp(Tmp3); 1798 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1799 } 1800 } else { 1801 // If this is an unaligned load and the target doesn't support it, 1802 // expand it. 1803 if (!TLI.allowsUnalignedMemoryAccesses()) { 1804 unsigned ABIAlignment = TLI.getTargetData()-> 1805 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1806 if (LD->getAlignment() < ABIAlignment){ 1807 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1808 TLI); 1809 Tmp1 = Result.getOperand(0); 1810 Tmp2 = Result.getOperand(1); 1811 Tmp1 = LegalizeOp(Tmp1); 1812 Tmp2 = LegalizeOp(Tmp2); 1813 } 1814 } 1815 } 1816 break; 1817 case TargetLowering::Expand: 1818 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1819 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1820 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 1821 LD->getSrcValueOffset(), 1822 LD->isVolatile(), LD->getAlignment()); 1823 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1824 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1825 Tmp2 = LegalizeOp(Load.getValue(1)); 1826 break; 1827 } 1828 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1829 // Turn the unsupported load into an EXTLOAD followed by an explicit 1830 // zero/sign extend inreg. 1831 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1832 Tmp1, Tmp2, LD->getSrcValue(), 1833 LD->getSrcValueOffset(), SrcVT, 1834 LD->isVolatile(), LD->getAlignment()); 1835 SDOperand ValRes; 1836 if (ExtType == ISD::SEXTLOAD) 1837 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1838 Result, DAG.getValueType(SrcVT)); 1839 else 1840 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1841 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1842 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1843 break; 1844 } 1845 // Since loads produce two values, make sure to remember that we legalized 1846 // both of them. 1847 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1848 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1849 return Op.ResNo ? Tmp2 : Tmp1; 1850 } 1851 } 1852 case ISD::EXTRACT_ELEMENT: { 1853 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1854 switch (getTypeAction(OpTy)) { 1855 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1856 case Legal: 1857 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1858 // 1 -> Hi 1859 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1860 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1861 TLI.getShiftAmountTy())); 1862 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1863 } else { 1864 // 0 -> Lo 1865 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1866 Node->getOperand(0)); 1867 } 1868 break; 1869 case Expand: 1870 // Get both the low and high parts. 1871 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1872 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1873 Result = Tmp2; // 1 -> Hi 1874 else 1875 Result = Tmp1; // 0 -> Lo 1876 break; 1877 } 1878 break; 1879 } 1880 1881 case ISD::CopyToReg: 1882 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1883 1884 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1885 "Register type must be legal!"); 1886 // Legalize the incoming value (must be a legal type). 1887 Tmp2 = LegalizeOp(Node->getOperand(2)); 1888 if (Node->getNumValues() == 1) { 1889 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1890 } else { 1891 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1892 if (Node->getNumOperands() == 4) { 1893 Tmp3 = LegalizeOp(Node->getOperand(3)); 1894 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1895 Tmp3); 1896 } else { 1897 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1898 } 1899 1900 // Since this produces two values, make sure to remember that we legalized 1901 // both of them. 1902 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1903 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1904 return Result; 1905 } 1906 break; 1907 1908 case ISD::RET: 1909 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1910 1911 // Ensure that libcalls are emitted before a return. 1912 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1913 Tmp1 = LegalizeOp(Tmp1); 1914 LastCALLSEQ_END = DAG.getEntryNode(); 1915 1916 switch (Node->getNumOperands()) { 1917 case 3: // ret val 1918 Tmp2 = Node->getOperand(1); 1919 Tmp3 = Node->getOperand(2); // Signness 1920 switch (getTypeAction(Tmp2.getValueType())) { 1921 case Legal: 1922 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1923 break; 1924 case Expand: 1925 if (!MVT::isVector(Tmp2.getValueType())) { 1926 SDOperand Lo, Hi; 1927 ExpandOp(Tmp2, Lo, Hi); 1928 1929 // Big endian systems want the hi reg first. 1930 if (!TLI.isLittleEndian()) 1931 std::swap(Lo, Hi); 1932 1933 if (Hi.Val) 1934 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1935 else 1936 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 1937 Result = LegalizeOp(Result); 1938 } else { 1939 SDNode *InVal = Tmp2.Val; 1940 int InIx = Tmp2.ResNo; 1941 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 1942 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 1943 1944 // Figure out if there is a simple type corresponding to this Vector 1945 // type. If so, convert to the vector type. 1946 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1947 if (TLI.isTypeLegal(TVT)) { 1948 // Turn this into a return of the vector type. 1949 Tmp2 = LegalizeOp(Tmp2); 1950 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1951 } else if (NumElems == 1) { 1952 // Turn this into a return of the scalar type. 1953 Tmp2 = ScalarizeVectorOp(Tmp2); 1954 Tmp2 = LegalizeOp(Tmp2); 1955 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1956 1957 // FIXME: Returns of gcc generic vectors smaller than a legal type 1958 // should be returned in integer registers! 1959 1960 // The scalarized value type may not be legal, e.g. it might require 1961 // promotion or expansion. Relegalize the return. 1962 Result = LegalizeOp(Result); 1963 } else { 1964 // FIXME: Returns of gcc generic vectors larger than a legal vector 1965 // type should be returned by reference! 1966 SDOperand Lo, Hi; 1967 SplitVectorOp(Tmp2, Lo, Hi); 1968 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1969 Result = LegalizeOp(Result); 1970 } 1971 } 1972 break; 1973 case Promote: 1974 Tmp2 = PromoteOp(Node->getOperand(1)); 1975 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1976 Result = LegalizeOp(Result); 1977 break; 1978 } 1979 break; 1980 case 1: // ret void 1981 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1982 break; 1983 default: { // ret <values> 1984 SmallVector<SDOperand, 8> NewValues; 1985 NewValues.push_back(Tmp1); 1986 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 1987 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1988 case Legal: 1989 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1990 NewValues.push_back(Node->getOperand(i+1)); 1991 break; 1992 case Expand: { 1993 SDOperand Lo, Hi; 1994 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && 1995 "FIXME: TODO: implement returning non-legal vector types!"); 1996 ExpandOp(Node->getOperand(i), Lo, Hi); 1997 NewValues.push_back(Lo); 1998 NewValues.push_back(Node->getOperand(i+1)); 1999 if (Hi.Val) { 2000 NewValues.push_back(Hi); 2001 NewValues.push_back(Node->getOperand(i+1)); 2002 } 2003 break; 2004 } 2005 case Promote: 2006 assert(0 && "Can't promote multiple return value yet!"); 2007 } 2008 2009 if (NewValues.size() == Node->getNumOperands()) 2010 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2011 else 2012 Result = DAG.getNode(ISD::RET, MVT::Other, 2013 &NewValues[0], NewValues.size()); 2014 break; 2015 } 2016 } 2017 2018 if (Result.getOpcode() == ISD::RET) { 2019 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2020 default: assert(0 && "This action is not supported yet!"); 2021 case TargetLowering::Legal: break; 2022 case TargetLowering::Custom: 2023 Tmp1 = TLI.LowerOperation(Result, DAG); 2024 if (Tmp1.Val) Result = Tmp1; 2025 break; 2026 } 2027 } 2028 break; 2029 case ISD::STORE: { 2030 StoreSDNode *ST = cast<StoreSDNode>(Node); 2031 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2032 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2033 int SVOffset = ST->getSrcValueOffset(); 2034 unsigned Alignment = ST->getAlignment(); 2035 bool isVolatile = ST->isVolatile(); 2036 2037 if (!ST->isTruncatingStore()) { 2038 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2039 // FIXME: We shouldn't do this for TargetConstantFP's. 2040 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2041 // to phase ordering between legalized code and the dag combiner. This 2042 // probably means that we need to integrate dag combiner and legalizer 2043 // together. 2044 // We generally can't do this one for long doubles. 2045 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2046 if (CFP->getValueType(0) == MVT::f32 && 2047 getTypeAction(MVT::i32) == Legal) { 2048 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF(). 2049 convertToAPInt().getZExtValue(), 2050 MVT::i32); 2051 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2052 SVOffset, isVolatile, Alignment); 2053 break; 2054 } else if (CFP->getValueType(0) == MVT::f64) { 2055 // If this target supports 64-bit registers, do a single 64-bit store. 2056 if (getTypeAction(MVT::i64) == Legal) { 2057 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2058 getZExtValue(), MVT::i64); 2059 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2060 SVOffset, isVolatile, Alignment); 2061 break; 2062 } else if (getTypeAction(MVT::i32) == Legal) { 2063 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2064 // stores. If the target supports neither 32- nor 64-bits, this 2065 // xform is certainly not worth it. 2066 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue(); 2067 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32); 2068 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32); 2069 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 2070 2071 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2072 SVOffset, isVolatile, Alignment); 2073 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2074 getIntPtrConstant(4)); 2075 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2076 isVolatile, MinAlign(Alignment, 4U)); 2077 2078 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2079 break; 2080 } 2081 } 2082 } 2083 2084 switch (getTypeAction(ST->getStoredVT())) { 2085 case Legal: { 2086 Tmp3 = LegalizeOp(ST->getValue()); 2087 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2088 ST->getOffset()); 2089 2090 MVT::ValueType VT = Tmp3.getValueType(); 2091 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2092 default: assert(0 && "This action is not supported yet!"); 2093 case TargetLowering::Legal: 2094 // If this is an unaligned store and the target doesn't support it, 2095 // expand it. 2096 if (!TLI.allowsUnalignedMemoryAccesses()) { 2097 unsigned ABIAlignment = TLI.getTargetData()-> 2098 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2099 if (ST->getAlignment() < ABIAlignment) 2100 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2101 TLI); 2102 } 2103 break; 2104 case TargetLowering::Custom: 2105 Tmp1 = TLI.LowerOperation(Result, DAG); 2106 if (Tmp1.Val) Result = Tmp1; 2107 break; 2108 case TargetLowering::Promote: 2109 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 2110 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2111 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2112 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2113 ST->getSrcValue(), SVOffset, isVolatile, 2114 Alignment); 2115 break; 2116 } 2117 break; 2118 } 2119 case Promote: 2120 // Truncate the value and store the result. 2121 Tmp3 = PromoteOp(ST->getValue()); 2122 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2123 SVOffset, ST->getStoredVT(), 2124 isVolatile, Alignment); 2125 break; 2126 2127 case Expand: 2128 unsigned IncrementSize = 0; 2129 SDOperand Lo, Hi; 2130 2131 // If this is a vector type, then we have to calculate the increment as 2132 // the product of the element size in bytes, and the number of elements 2133 // in the high half of the vector. 2134 if (MVT::isVector(ST->getValue().getValueType())) { 2135 SDNode *InVal = ST->getValue().Val; 2136 int InIx = ST->getValue().ResNo; 2137 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 2138 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 2139 2140 // Figure out if there is a simple type corresponding to this Vector 2141 // type. If so, convert to the vector type. 2142 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2143 if (TLI.isTypeLegal(TVT)) { 2144 // Turn this into a normal store of the vector type. 2145 Tmp3 = LegalizeOp(Node->getOperand(1)); 2146 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2147 SVOffset, isVolatile, Alignment); 2148 Result = LegalizeOp(Result); 2149 break; 2150 } else if (NumElems == 1) { 2151 // Turn this into a normal store of the scalar type. 2152 Tmp3 = ScalarizeVectorOp(Node->getOperand(1)); 2153 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2154 SVOffset, isVolatile, Alignment); 2155 // The scalarized value type may not be legal, e.g. it might require 2156 // promotion or expansion. Relegalize the scalar store. 2157 Result = LegalizeOp(Result); 2158 break; 2159 } else { 2160 SplitVectorOp(Node->getOperand(1), Lo, Hi); 2161 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; 2162 } 2163 } else { 2164 ExpandOp(Node->getOperand(1), Lo, Hi); 2165 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 2166 2167 if (!TLI.isLittleEndian()) 2168 std::swap(Lo, Hi); 2169 } 2170 2171 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2172 SVOffset, isVolatile, Alignment); 2173 2174 if (Hi.Val == NULL) { 2175 // Must be int <-> float one-to-one expansion. 2176 Result = Lo; 2177 break; 2178 } 2179 2180 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2181 getIntPtrConstant(IncrementSize)); 2182 assert(isTypeLegal(Tmp2.getValueType()) && 2183 "Pointers must be legal!"); 2184 SVOffset += IncrementSize; 2185 Alignment = MinAlign(Alignment, IncrementSize); 2186 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2187 SVOffset, isVolatile, Alignment); 2188 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2189 break; 2190 } 2191 } else { 2192 // Truncating store 2193 assert(isTypeLegal(ST->getValue().getValueType()) && 2194 "Cannot handle illegal TRUNCSTORE yet!"); 2195 Tmp3 = LegalizeOp(ST->getValue()); 2196 2197 // The only promote case we handle is TRUNCSTORE:i1 X into 2198 // -> TRUNCSTORE:i8 (and X, 1) 2199 if (ST->getStoredVT() == MVT::i1 && 2200 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) { 2201 // Promote the bool to a mask then store. 2202 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3, 2203 DAG.getConstant(1, Tmp3.getValueType())); 2204 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2205 SVOffset, MVT::i8, 2206 isVolatile, Alignment); 2207 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2208 Tmp2 != ST->getBasePtr()) { 2209 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2210 ST->getOffset()); 2211 } 2212 2213 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT(); 2214 switch (TLI.getStoreXAction(StVT)) { 2215 default: assert(0 && "This action is not supported yet!"); 2216 case TargetLowering::Legal: 2217 // If this is an unaligned store and the target doesn't support it, 2218 // expand it. 2219 if (!TLI.allowsUnalignedMemoryAccesses()) { 2220 unsigned ABIAlignment = TLI.getTargetData()-> 2221 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2222 if (ST->getAlignment() < ABIAlignment) 2223 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2224 TLI); 2225 } 2226 break; 2227 case TargetLowering::Custom: 2228 Tmp1 = TLI.LowerOperation(Result, DAG); 2229 if (Tmp1.Val) Result = Tmp1; 2230 break; 2231 } 2232 } 2233 break; 2234 } 2235 case ISD::PCMARKER: 2236 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2237 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2238 break; 2239 case ISD::STACKSAVE: 2240 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2241 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2242 Tmp1 = Result.getValue(0); 2243 Tmp2 = Result.getValue(1); 2244 2245 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2246 default: assert(0 && "This action is not supported yet!"); 2247 case TargetLowering::Legal: break; 2248 case TargetLowering::Custom: 2249 Tmp3 = TLI.LowerOperation(Result, DAG); 2250 if (Tmp3.Val) { 2251 Tmp1 = LegalizeOp(Tmp3); 2252 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2253 } 2254 break; 2255 case TargetLowering::Expand: 2256 // Expand to CopyFromReg if the target set 2257 // StackPointerRegisterToSaveRestore. 2258 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2259 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2260 Node->getValueType(0)); 2261 Tmp2 = Tmp1.getValue(1); 2262 } else { 2263 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2264 Tmp2 = Node->getOperand(0); 2265 } 2266 break; 2267 } 2268 2269 // Since stacksave produce two values, make sure to remember that we 2270 // legalized both of them. 2271 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2272 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2273 return Op.ResNo ? Tmp2 : Tmp1; 2274 2275 case ISD::STACKRESTORE: 2276 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2277 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2278 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2279 2280 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2281 default: assert(0 && "This action is not supported yet!"); 2282 case TargetLowering::Legal: break; 2283 case TargetLowering::Custom: 2284 Tmp1 = TLI.LowerOperation(Result, DAG); 2285 if (Tmp1.Val) Result = Tmp1; 2286 break; 2287 case TargetLowering::Expand: 2288 // Expand to CopyToReg if the target set 2289 // StackPointerRegisterToSaveRestore. 2290 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2291 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2292 } else { 2293 Result = Tmp1; 2294 } 2295 break; 2296 } 2297 break; 2298 2299 case ISD::READCYCLECOUNTER: 2300 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2301 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2302 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2303 Node->getValueType(0))) { 2304 default: assert(0 && "This action is not supported yet!"); 2305 case TargetLowering::Legal: 2306 Tmp1 = Result.getValue(0); 2307 Tmp2 = Result.getValue(1); 2308 break; 2309 case TargetLowering::Custom: 2310 Result = TLI.LowerOperation(Result, DAG); 2311 Tmp1 = LegalizeOp(Result.getValue(0)); 2312 Tmp2 = LegalizeOp(Result.getValue(1)); 2313 break; 2314 } 2315 2316 // Since rdcc produce two values, make sure to remember that we legalized 2317 // both of them. 2318 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2319 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2320 return Result; 2321 2322 case ISD::SELECT: 2323 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2324 case Expand: assert(0 && "It's impossible to expand bools"); 2325 case Legal: 2326 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2327 break; 2328 case Promote: 2329 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2330 // Make sure the condition is either zero or one. 2331 if (!DAG.MaskedValueIsZero(Tmp1, 2332 MVT::getIntVTBitMask(Tmp1.getValueType())^1)) 2333 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2334 break; 2335 } 2336 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2337 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2338 2339 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2340 2341 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2342 default: assert(0 && "This action is not supported yet!"); 2343 case TargetLowering::Legal: break; 2344 case TargetLowering::Custom: { 2345 Tmp1 = TLI.LowerOperation(Result, DAG); 2346 if (Tmp1.Val) Result = Tmp1; 2347 break; 2348 } 2349 case TargetLowering::Expand: 2350 if (Tmp1.getOpcode() == ISD::SETCC) { 2351 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2352 Tmp2, Tmp3, 2353 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2354 } else { 2355 Result = DAG.getSelectCC(Tmp1, 2356 DAG.getConstant(0, Tmp1.getValueType()), 2357 Tmp2, Tmp3, ISD::SETNE); 2358 } 2359 break; 2360 case TargetLowering::Promote: { 2361 MVT::ValueType NVT = 2362 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2363 unsigned ExtOp, TruncOp; 2364 if (MVT::isVector(Tmp2.getValueType())) { 2365 ExtOp = ISD::BIT_CONVERT; 2366 TruncOp = ISD::BIT_CONVERT; 2367 } else if (MVT::isInteger(Tmp2.getValueType())) { 2368 ExtOp = ISD::ANY_EXTEND; 2369 TruncOp = ISD::TRUNCATE; 2370 } else { 2371 ExtOp = ISD::FP_EXTEND; 2372 TruncOp = ISD::FP_ROUND; 2373 } 2374 // Promote each of the values to the new type. 2375 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2376 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2377 // Perform the larger operation, then round down. 2378 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2379 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2380 break; 2381 } 2382 } 2383 break; 2384 case ISD::SELECT_CC: { 2385 Tmp1 = Node->getOperand(0); // LHS 2386 Tmp2 = Node->getOperand(1); // RHS 2387 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2388 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2389 SDOperand CC = Node->getOperand(4); 2390 2391 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2392 2393 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2394 // the LHS is a legal SETCC itself. In this case, we need to compare 2395 // the result against zero to select between true and false values. 2396 if (Tmp2.Val == 0) { 2397 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2398 CC = DAG.getCondCode(ISD::SETNE); 2399 } 2400 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2401 2402 // Everything is legal, see if we should expand this op or something. 2403 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2404 default: assert(0 && "This action is not supported yet!"); 2405 case TargetLowering::Legal: break; 2406 case TargetLowering::Custom: 2407 Tmp1 = TLI.LowerOperation(Result, DAG); 2408 if (Tmp1.Val) Result = Tmp1; 2409 break; 2410 } 2411 break; 2412 } 2413 case ISD::SETCC: 2414 Tmp1 = Node->getOperand(0); 2415 Tmp2 = Node->getOperand(1); 2416 Tmp3 = Node->getOperand(2); 2417 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2418 2419 // If we had to Expand the SetCC operands into a SELECT node, then it may 2420 // not always be possible to return a true LHS & RHS. In this case, just 2421 // return the value we legalized, returned in the LHS 2422 if (Tmp2.Val == 0) { 2423 Result = Tmp1; 2424 break; 2425 } 2426 2427 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2428 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2429 case TargetLowering::Custom: 2430 isCustom = true; 2431 // FALLTHROUGH. 2432 case TargetLowering::Legal: 2433 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2434 if (isCustom) { 2435 Tmp4 = TLI.LowerOperation(Result, DAG); 2436 if (Tmp4.Val) Result = Tmp4; 2437 } 2438 break; 2439 case TargetLowering::Promote: { 2440 // First step, figure out the appropriate operation to use. 2441 // Allow SETCC to not be supported for all legal data types 2442 // Mostly this targets FP 2443 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2444 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2445 2446 // Scan for the appropriate larger type to use. 2447 while (1) { 2448 NewInTy = (MVT::ValueType)(NewInTy+1); 2449 2450 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2451 "Fell off of the edge of the integer world"); 2452 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2453 "Fell off of the edge of the floating point world"); 2454 2455 // If the target supports SETCC of this type, use it. 2456 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2457 break; 2458 } 2459 if (MVT::isInteger(NewInTy)) 2460 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2461 else { 2462 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2463 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2464 } 2465 Tmp1 = LegalizeOp(Tmp1); 2466 Tmp2 = LegalizeOp(Tmp2); 2467 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2468 Result = LegalizeOp(Result); 2469 break; 2470 } 2471 case TargetLowering::Expand: 2472 // Expand a setcc node into a select_cc of the same condition, lhs, and 2473 // rhs that selects between const 1 (true) and const 0 (false). 2474 MVT::ValueType VT = Node->getValueType(0); 2475 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2476 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2477 Tmp3); 2478 break; 2479 } 2480 break; 2481 case ISD::MEMSET: 2482 case ISD::MEMCPY: 2483 case ISD::MEMMOVE: { 2484 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2485 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2486 2487 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2488 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2489 case Expand: assert(0 && "Cannot expand a byte!"); 2490 case Legal: 2491 Tmp3 = LegalizeOp(Node->getOperand(2)); 2492 break; 2493 case Promote: 2494 Tmp3 = PromoteOp(Node->getOperand(2)); 2495 break; 2496 } 2497 } else { 2498 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2499 } 2500 2501 SDOperand Tmp4; 2502 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2503 case Expand: { 2504 // Length is too big, just take the lo-part of the length. 2505 SDOperand HiPart; 2506 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2507 break; 2508 } 2509 case Legal: 2510 Tmp4 = LegalizeOp(Node->getOperand(3)); 2511 break; 2512 case Promote: 2513 Tmp4 = PromoteOp(Node->getOperand(3)); 2514 break; 2515 } 2516 2517 SDOperand Tmp5; 2518 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2519 case Expand: assert(0 && "Cannot expand this yet!"); 2520 case Legal: 2521 Tmp5 = LegalizeOp(Node->getOperand(4)); 2522 break; 2523 case Promote: 2524 Tmp5 = PromoteOp(Node->getOperand(4)); 2525 break; 2526 } 2527 2528 SDOperand Tmp6; 2529 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool 2530 case Expand: assert(0 && "Cannot expand this yet!"); 2531 case Legal: 2532 Tmp6 = LegalizeOp(Node->getOperand(5)); 2533 break; 2534 case Promote: 2535 Tmp6 = PromoteOp(Node->getOperand(5)); 2536 break; 2537 } 2538 2539 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2540 default: assert(0 && "This action not implemented for this operation!"); 2541 case TargetLowering::Custom: 2542 isCustom = true; 2543 // FALLTHROUGH 2544 case TargetLowering::Legal: { 2545 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 }; 2546 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 2547 if (isCustom) { 2548 Tmp1 = TLI.LowerOperation(Result, DAG); 2549 if (Tmp1.Val) Result = Tmp1; 2550 } 2551 break; 2552 } 2553 case TargetLowering::Expand: { 2554 // Otherwise, the target does not support this operation. Lower the 2555 // operation to an explicit libcall as appropriate. 2556 MVT::ValueType IntPtr = TLI.getPointerTy(); 2557 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2558 TargetLowering::ArgListTy Args; 2559 TargetLowering::ArgListEntry Entry; 2560 2561 const char *FnName = 0; 2562 if (Node->getOpcode() == ISD::MEMSET) { 2563 Entry.Node = Tmp2; Entry.Ty = IntPtrTy; 2564 Args.push_back(Entry); 2565 // Extend the (previously legalized) ubyte argument to be an int value 2566 // for the call. 2567 if (Tmp3.getValueType() > MVT::i32) 2568 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2569 else 2570 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2571 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 2572 Args.push_back(Entry); 2573 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false; 2574 Args.push_back(Entry); 2575 2576 FnName = "memset"; 2577 } else if (Node->getOpcode() == ISD::MEMCPY || 2578 Node->getOpcode() == ISD::MEMMOVE) { 2579 Entry.Ty = IntPtrTy; 2580 Entry.Node = Tmp2; Args.push_back(Entry); 2581 Entry.Node = Tmp3; Args.push_back(Entry); 2582 Entry.Node = Tmp4; Args.push_back(Entry); 2583 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2584 } else { 2585 assert(0 && "Unknown op!"); 2586 } 2587 2588 std::pair<SDOperand,SDOperand> CallResult = 2589 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 2590 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2591 Result = CallResult.second; 2592 break; 2593 } 2594 } 2595 break; 2596 } 2597 2598 case ISD::SHL_PARTS: 2599 case ISD::SRA_PARTS: 2600 case ISD::SRL_PARTS: { 2601 SmallVector<SDOperand, 8> Ops; 2602 bool Changed = false; 2603 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2604 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2605 Changed |= Ops.back() != Node->getOperand(i); 2606 } 2607 if (Changed) 2608 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2609 2610 switch (TLI.getOperationAction(Node->getOpcode(), 2611 Node->getValueType(0))) { 2612 default: assert(0 && "This action is not supported yet!"); 2613 case TargetLowering::Legal: break; 2614 case TargetLowering::Custom: 2615 Tmp1 = TLI.LowerOperation(Result, DAG); 2616 if (Tmp1.Val) { 2617 SDOperand Tmp2, RetVal(0, 0); 2618 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2619 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2620 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2621 if (i == Op.ResNo) 2622 RetVal = Tmp2; 2623 } 2624 assert(RetVal.Val && "Illegal result number"); 2625 return RetVal; 2626 } 2627 break; 2628 } 2629 2630 // Since these produce multiple values, make sure to remember that we 2631 // legalized all of them. 2632 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2633 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2634 return Result.getValue(Op.ResNo); 2635 } 2636 2637 // Binary operators 2638 case ISD::ADD: 2639 case ISD::SUB: 2640 case ISD::MUL: 2641 case ISD::MULHS: 2642 case ISD::MULHU: 2643 case ISD::UDIV: 2644 case ISD::SDIV: 2645 case ISD::AND: 2646 case ISD::OR: 2647 case ISD::XOR: 2648 case ISD::SHL: 2649 case ISD::SRL: 2650 case ISD::SRA: 2651 case ISD::FADD: 2652 case ISD::FSUB: 2653 case ISD::FMUL: 2654 case ISD::FDIV: 2655 case ISD::FPOW: 2656 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2657 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2658 case Expand: assert(0 && "Not possible"); 2659 case Legal: 2660 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2661 break; 2662 case Promote: 2663 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2664 break; 2665 } 2666 2667 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2668 2669 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2670 default: assert(0 && "BinOp legalize operation not supported"); 2671 case TargetLowering::Legal: break; 2672 case TargetLowering::Custom: 2673 Tmp1 = TLI.LowerOperation(Result, DAG); 2674 if (Tmp1.Val) Result = Tmp1; 2675 break; 2676 case TargetLowering::Expand: { 2677 MVT::ValueType VT = Op.getValueType(); 2678 2679 // See if multiply or divide can be lowered using two-result operations. 2680 SDVTList VTs = DAG.getVTList(VT, VT); 2681 if (Node->getOpcode() == ISD::MUL) { 2682 // We just need the low half of the multiply; try both the signed 2683 // and unsigned forms. If the target supports both SMUL_LOHI and 2684 // UMUL_LOHI, form a preference by checking which forms of plain 2685 // MULH it supports. 2686 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2687 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2688 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2689 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2690 unsigned OpToUse = 0; 2691 if (HasSMUL_LOHI && !HasMULHS) { 2692 OpToUse = ISD::SMUL_LOHI; 2693 } else if (HasUMUL_LOHI && !HasMULHU) { 2694 OpToUse = ISD::UMUL_LOHI; 2695 } else if (HasSMUL_LOHI) { 2696 OpToUse = ISD::SMUL_LOHI; 2697 } else if (HasUMUL_LOHI) { 2698 OpToUse = ISD::UMUL_LOHI; 2699 } 2700 if (OpToUse) { 2701 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 2702 break; 2703 } 2704 } 2705 if (Node->getOpcode() == ISD::MULHS && 2706 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 2707 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 2708 break; 2709 } 2710 if (Node->getOpcode() == ISD::MULHU && 2711 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 2712 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 2713 break; 2714 } 2715 if (Node->getOpcode() == ISD::SDIV && 2716 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 2717 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 2718 break; 2719 } 2720 if (Node->getOpcode() == ISD::UDIV && 2721 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 2722 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 2723 break; 2724 } 2725 2726 // Check to see if we have a libcall for this operator. 2727 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2728 bool isSigned = false; 2729 switch (Node->getOpcode()) { 2730 case ISD::UDIV: 2731 case ISD::SDIV: 2732 if (VT == MVT::i32) { 2733 LC = Node->getOpcode() == ISD::UDIV 2734 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 2735 isSigned = Node->getOpcode() == ISD::SDIV; 2736 } 2737 break; 2738 case ISD::FPOW: 2739 LC = VT == MVT::f32 ? RTLIB::POW_F32 : 2740 VT == MVT::f64 ? RTLIB::POW_F64 : 2741 VT == MVT::f80 ? RTLIB::POW_F80 : 2742 VT == MVT::ppcf128 ? RTLIB::POW_PPCF128 : 2743 RTLIB::UNKNOWN_LIBCALL; 2744 break; 2745 default: break; 2746 } 2747 if (LC != RTLIB::UNKNOWN_LIBCALL) { 2748 SDOperand Dummy; 2749 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2750 break; 2751 } 2752 2753 assert(MVT::isVector(Node->getValueType(0)) && 2754 "Cannot expand this binary operator!"); 2755 // Expand the operation into a bunch of nasty scalar code. 2756 Result = LegalizeOp(UnrollVectorOp(Op)); 2757 break; 2758 } 2759 case TargetLowering::Promote: { 2760 switch (Node->getOpcode()) { 2761 default: assert(0 && "Do not know how to promote this BinOp!"); 2762 case ISD::AND: 2763 case ISD::OR: 2764 case ISD::XOR: { 2765 MVT::ValueType OVT = Node->getValueType(0); 2766 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2767 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2768 // Bit convert each of the values to the new type. 2769 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2770 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2771 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2772 // Bit convert the result back the original type. 2773 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2774 break; 2775 } 2776 } 2777 } 2778 } 2779 break; 2780 2781 case ISD::SMUL_LOHI: 2782 case ISD::UMUL_LOHI: 2783 case ISD::SDIVREM: 2784 case ISD::UDIVREM: 2785 // These nodes will only be produced by target-specific lowering, so 2786 // they shouldn't be here if they aren't legal. 2787 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 2788 "This must be legal!"); 2789 2790 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2791 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2792 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2793 break; 2794 2795 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2796 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2797 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2798 case Expand: assert(0 && "Not possible"); 2799 case Legal: 2800 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2801 break; 2802 case Promote: 2803 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2804 break; 2805 } 2806 2807 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2808 2809 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2810 default: assert(0 && "Operation not supported"); 2811 case TargetLowering::Custom: 2812 Tmp1 = TLI.LowerOperation(Result, DAG); 2813 if (Tmp1.Val) Result = Tmp1; 2814 break; 2815 case TargetLowering::Legal: break; 2816 case TargetLowering::Expand: { 2817 // If this target supports fabs/fneg natively and select is cheap, 2818 // do this efficiently. 2819 if (!TLI.isSelectExpensive() && 2820 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 2821 TargetLowering::Legal && 2822 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 2823 TargetLowering::Legal) { 2824 // Get the sign bit of the RHS. 2825 MVT::ValueType IVT = 2826 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2827 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2828 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2829 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2830 // Get the absolute value of the result. 2831 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2832 // Select between the nabs and abs value based on the sign bit of 2833 // the input. 2834 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2835 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2836 AbsVal), 2837 AbsVal); 2838 Result = LegalizeOp(Result); 2839 break; 2840 } 2841 2842 // Otherwise, do bitwise ops! 2843 MVT::ValueType NVT = 2844 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 2845 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 2846 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 2847 Result = LegalizeOp(Result); 2848 break; 2849 } 2850 } 2851 break; 2852 2853 case ISD::ADDC: 2854 case ISD::SUBC: 2855 Tmp1 = LegalizeOp(Node->getOperand(0)); 2856 Tmp2 = LegalizeOp(Node->getOperand(1)); 2857 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2858 // Since this produces two values, make sure to remember that we legalized 2859 // both of them. 2860 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2861 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2862 return Result; 2863 2864 case ISD::ADDE: 2865 case ISD::SUBE: 2866 Tmp1 = LegalizeOp(Node->getOperand(0)); 2867 Tmp2 = LegalizeOp(Node->getOperand(1)); 2868 Tmp3 = LegalizeOp(Node->getOperand(2)); 2869 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2870 // Since this produces two values, make sure to remember that we legalized 2871 // both of them. 2872 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2873 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2874 return Result; 2875 2876 case ISD::BUILD_PAIR: { 2877 MVT::ValueType PairTy = Node->getValueType(0); 2878 // TODO: handle the case where the Lo and Hi operands are not of legal type 2879 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2880 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2881 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2882 case TargetLowering::Promote: 2883 case TargetLowering::Custom: 2884 assert(0 && "Cannot promote/custom this yet!"); 2885 case TargetLowering::Legal: 2886 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2887 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2888 break; 2889 case TargetLowering::Expand: 2890 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2891 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2892 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2893 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2894 TLI.getShiftAmountTy())); 2895 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2896 break; 2897 } 2898 break; 2899 } 2900 2901 case ISD::UREM: 2902 case ISD::SREM: 2903 case ISD::FREM: 2904 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2905 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2906 2907 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2908 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2909 case TargetLowering::Custom: 2910 isCustom = true; 2911 // FALLTHROUGH 2912 case TargetLowering::Legal: 2913 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2914 if (isCustom) { 2915 Tmp1 = TLI.LowerOperation(Result, DAG); 2916 if (Tmp1.Val) Result = Tmp1; 2917 } 2918 break; 2919 case TargetLowering::Expand: { 2920 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2921 bool isSigned = DivOpc == ISD::SDIV; 2922 MVT::ValueType VT = Node->getValueType(0); 2923 2924 // See if remainder can be lowered using two-result operations. 2925 SDVTList VTs = DAG.getVTList(VT, VT); 2926 if (Node->getOpcode() == ISD::SREM && 2927 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 2928 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 2929 break; 2930 } 2931 if (Node->getOpcode() == ISD::UREM && 2932 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 2933 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 2934 break; 2935 } 2936 2937 if (MVT::isInteger(VT)) { 2938 if (TLI.getOperationAction(DivOpc, VT) == 2939 TargetLowering::Legal) { 2940 // X % Y -> X-X/Y*Y 2941 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 2942 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2943 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2944 } else if (MVT::isVector(VT)) { 2945 Result = LegalizeOp(UnrollVectorOp(Op)); 2946 } else { 2947 assert(VT == MVT::i32 && 2948 "Cannot expand this binary operator!"); 2949 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 2950 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 2951 SDOperand Dummy; 2952 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2953 } 2954 } else { 2955 assert(MVT::isFloatingPoint(VT) && 2956 "remainder op must have integer or floating-point type"); 2957 if (MVT::isVector(VT)) { 2958 Result = LegalizeOp(UnrollVectorOp(Op)); 2959 } else { 2960 // Floating point mod -> fmod libcall. 2961 RTLIB::Libcall LC = VT == MVT::f32 2962 ? RTLIB::REM_F32 : RTLIB::REM_F64; 2963 SDOperand Dummy; 2964 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2965 false/*sign irrelevant*/, Dummy); 2966 } 2967 } 2968 break; 2969 } 2970 } 2971 break; 2972 case ISD::VAARG: { 2973 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2974 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2975 2976 MVT::ValueType VT = Node->getValueType(0); 2977 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2978 default: assert(0 && "This action is not supported yet!"); 2979 case TargetLowering::Custom: 2980 isCustom = true; 2981 // FALLTHROUGH 2982 case TargetLowering::Legal: 2983 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2984 Result = Result.getValue(0); 2985 Tmp1 = Result.getValue(1); 2986 2987 if (isCustom) { 2988 Tmp2 = TLI.LowerOperation(Result, DAG); 2989 if (Tmp2.Val) { 2990 Result = LegalizeOp(Tmp2); 2991 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 2992 } 2993 } 2994 break; 2995 case TargetLowering::Expand: { 2996 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 2997 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2998 SV->getValue(), SV->getOffset()); 2999 // Increment the pointer, VAList, to the next vaarg 3000 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3001 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3002 TLI.getPointerTy())); 3003 // Store the incremented VAList to the legalized pointer 3004 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 3005 SV->getOffset()); 3006 // Load the actual argument out of the pointer VAList 3007 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3008 Tmp1 = LegalizeOp(Result.getValue(1)); 3009 Result = LegalizeOp(Result); 3010 break; 3011 } 3012 } 3013 // Since VAARG produces two values, make sure to remember that we 3014 // legalized both of them. 3015 AddLegalizedOperand(SDOperand(Node, 0), Result); 3016 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3017 return Op.ResNo ? Tmp1 : Result; 3018 } 3019 3020 case ISD::VACOPY: 3021 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3022 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3023 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3024 3025 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3026 default: assert(0 && "This action is not supported yet!"); 3027 case TargetLowering::Custom: 3028 isCustom = true; 3029 // FALLTHROUGH 3030 case TargetLowering::Legal: 3031 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3032 Node->getOperand(3), Node->getOperand(4)); 3033 if (isCustom) { 3034 Tmp1 = TLI.LowerOperation(Result, DAG); 3035 if (Tmp1.Val) Result = Tmp1; 3036 } 3037 break; 3038 case TargetLowering::Expand: 3039 // This defaults to loading a pointer from the input and storing it to the 3040 // output, returning the chain. 3041 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); 3042 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); 3043 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), 3044 SVD->getOffset()); 3045 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), 3046 SVS->getOffset()); 3047 break; 3048 } 3049 break; 3050 3051 case ISD::VAEND: 3052 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3053 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3054 3055 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3056 default: assert(0 && "This action is not supported yet!"); 3057 case TargetLowering::Custom: 3058 isCustom = true; 3059 // FALLTHROUGH 3060 case TargetLowering::Legal: 3061 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3062 if (isCustom) { 3063 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3064 if (Tmp1.Val) Result = Tmp1; 3065 } 3066 break; 3067 case TargetLowering::Expand: 3068 Result = Tmp1; // Default to a no-op, return the chain 3069 break; 3070 } 3071 break; 3072 3073 case ISD::VASTART: 3074 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3075 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3076 3077 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3078 3079 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3080 default: assert(0 && "This action is not supported yet!"); 3081 case TargetLowering::Legal: break; 3082 case TargetLowering::Custom: 3083 Tmp1 = TLI.LowerOperation(Result, DAG); 3084 if (Tmp1.Val) Result = Tmp1; 3085 break; 3086 } 3087 break; 3088 3089 case ISD::ROTL: 3090 case ISD::ROTR: 3091 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3092 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3093 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3094 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3095 default: 3096 assert(0 && "ROTL/ROTR legalize operation not supported"); 3097 break; 3098 case TargetLowering::Legal: 3099 break; 3100 case TargetLowering::Custom: 3101 Tmp1 = TLI.LowerOperation(Result, DAG); 3102 if (Tmp1.Val) Result = Tmp1; 3103 break; 3104 case TargetLowering::Promote: 3105 assert(0 && "Do not know how to promote ROTL/ROTR"); 3106 break; 3107 case TargetLowering::Expand: 3108 assert(0 && "Do not know how to expand ROTL/ROTR"); 3109 break; 3110 } 3111 break; 3112 3113 case ISD::BSWAP: 3114 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3115 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3116 case TargetLowering::Custom: 3117 assert(0 && "Cannot custom legalize this yet!"); 3118 case TargetLowering::Legal: 3119 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3120 break; 3121 case TargetLowering::Promote: { 3122 MVT::ValueType OVT = Tmp1.getValueType(); 3123 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3124 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); 3125 3126 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3127 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3128 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3129 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3130 break; 3131 } 3132 case TargetLowering::Expand: 3133 Result = ExpandBSWAP(Tmp1); 3134 break; 3135 } 3136 break; 3137 3138 case ISD::CTPOP: 3139 case ISD::CTTZ: 3140 case ISD::CTLZ: 3141 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3142 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3143 case TargetLowering::Custom: 3144 case TargetLowering::Legal: 3145 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3146 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3147 TargetLowering::Custom) { 3148 Tmp1 = TLI.LowerOperation(Result, DAG); 3149 if (Tmp1.Val) { 3150 Result = Tmp1; 3151 } 3152 } 3153 break; 3154 case TargetLowering::Promote: { 3155 MVT::ValueType OVT = Tmp1.getValueType(); 3156 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3157 3158 // Zero extend the argument. 3159 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3160 // Perform the larger operation, then subtract if needed. 3161 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3162 switch (Node->getOpcode()) { 3163 case ISD::CTPOP: 3164 Result = Tmp1; 3165 break; 3166 case ISD::CTTZ: 3167 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3168 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3169 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 3170 ISD::SETEQ); 3171 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3172 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); 3173 break; 3174 case ISD::CTLZ: 3175 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3176 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3177 DAG.getConstant(MVT::getSizeInBits(NVT) - 3178 MVT::getSizeInBits(OVT), NVT)); 3179 break; 3180 } 3181 break; 3182 } 3183 case TargetLowering::Expand: 3184 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3185 break; 3186 } 3187 break; 3188 3189 // Unary operators 3190 case ISD::FABS: 3191 case ISD::FNEG: 3192 case ISD::FSQRT: 3193 case ISD::FSIN: 3194 case ISD::FCOS: 3195 Tmp1 = LegalizeOp(Node->getOperand(0)); 3196 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3197 case TargetLowering::Promote: 3198 case TargetLowering::Custom: 3199 isCustom = true; 3200 // FALLTHROUGH 3201 case TargetLowering::Legal: 3202 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3203 if (isCustom) { 3204 Tmp1 = TLI.LowerOperation(Result, DAG); 3205 if (Tmp1.Val) Result = Tmp1; 3206 } 3207 break; 3208 case TargetLowering::Expand: 3209 switch (Node->getOpcode()) { 3210 default: assert(0 && "Unreachable!"); 3211 case ISD::FNEG: 3212 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3213 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3214 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3215 break; 3216 case ISD::FABS: { 3217 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3218 MVT::ValueType VT = Node->getValueType(0); 3219 Tmp2 = DAG.getConstantFP(0.0, VT); 3220 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 3221 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3222 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3223 break; 3224 } 3225 case ISD::FSQRT: 3226 case ISD::FSIN: 3227 case ISD::FCOS: { 3228 MVT::ValueType VT = Node->getValueType(0); 3229 3230 // Expand unsupported unary vector operators by unrolling them. 3231 if (MVT::isVector(VT)) { 3232 Result = LegalizeOp(UnrollVectorOp(Op)); 3233 break; 3234 } 3235 3236 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3237 switch(Node->getOpcode()) { 3238 case ISD::FSQRT: 3239 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : 3240 VT == MVT::f64 ? RTLIB::SQRT_F64 : 3241 VT == MVT::f80 ? RTLIB::SQRT_F80 : 3242 VT == MVT::ppcf128 ? RTLIB::SQRT_PPCF128 : 3243 RTLIB::UNKNOWN_LIBCALL; 3244 break; 3245 case ISD::FSIN: 3246 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 3247 break; 3248 case ISD::FCOS: 3249 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64; 3250 break; 3251 default: assert(0 && "Unreachable!"); 3252 } 3253 SDOperand Dummy; 3254 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3255 false/*sign irrelevant*/, Dummy); 3256 break; 3257 } 3258 } 3259 break; 3260 } 3261 break; 3262 case ISD::FPOWI: { 3263 MVT::ValueType VT = Node->getValueType(0); 3264 3265 // Expand unsupported unary vector operators by unrolling them. 3266 if (MVT::isVector(VT)) { 3267 Result = LegalizeOp(UnrollVectorOp(Op)); 3268 break; 3269 } 3270 3271 // We always lower FPOWI into a libcall. No target support for it yet. 3272 RTLIB::Libcall LC = 3273 VT == MVT::f32 ? RTLIB::POWI_F32 : 3274 VT == MVT::f64 ? RTLIB::POWI_F64 : 3275 VT == MVT::f80 ? RTLIB::POWI_F80 : 3276 VT == MVT::ppcf128 ? RTLIB::POWI_PPCF128 : 3277 RTLIB::UNKNOWN_LIBCALL; 3278 SDOperand Dummy; 3279 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3280 false/*sign irrelevant*/, Dummy); 3281 break; 3282 } 3283 case ISD::BIT_CONVERT: 3284 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3285 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3286 } else if (MVT::isVector(Op.getOperand(0).getValueType())) { 3287 // The input has to be a vector type, we have to either scalarize it, pack 3288 // it, or convert it based on whether the input vector type is legal. 3289 SDNode *InVal = Node->getOperand(0).Val; 3290 int InIx = Node->getOperand(0).ResNo; 3291 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 3292 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 3293 3294 // Figure out if there is a simple type corresponding to this Vector 3295 // type. If so, convert to the vector type. 3296 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3297 if (TLI.isTypeLegal(TVT)) { 3298 // Turn this into a bit convert of the vector input. 3299 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3300 LegalizeOp(Node->getOperand(0))); 3301 break; 3302 } else if (NumElems == 1) { 3303 // Turn this into a bit convert of the scalar input. 3304 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3305 ScalarizeVectorOp(Node->getOperand(0))); 3306 break; 3307 } else { 3308 // FIXME: UNIMP! Store then reload 3309 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3310 } 3311 } else { 3312 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3313 Node->getOperand(0).getValueType())) { 3314 default: assert(0 && "Unknown operation action!"); 3315 case TargetLowering::Expand: 3316 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3317 break; 3318 case TargetLowering::Legal: 3319 Tmp1 = LegalizeOp(Node->getOperand(0)); 3320 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3321 break; 3322 } 3323 } 3324 break; 3325 3326 // Conversion operators. The source and destination have different types. 3327 case ISD::SINT_TO_FP: 3328 case ISD::UINT_TO_FP: { 3329 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3330 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3331 case Legal: 3332 switch (TLI.getOperationAction(Node->getOpcode(), 3333 Node->getOperand(0).getValueType())) { 3334 default: assert(0 && "Unknown operation action!"); 3335 case TargetLowering::Custom: 3336 isCustom = true; 3337 // FALLTHROUGH 3338 case TargetLowering::Legal: 3339 Tmp1 = LegalizeOp(Node->getOperand(0)); 3340 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3341 if (isCustom) { 3342 Tmp1 = TLI.LowerOperation(Result, DAG); 3343 if (Tmp1.Val) Result = Tmp1; 3344 } 3345 break; 3346 case TargetLowering::Expand: 3347 Result = ExpandLegalINT_TO_FP(isSigned, 3348 LegalizeOp(Node->getOperand(0)), 3349 Node->getValueType(0)); 3350 break; 3351 case TargetLowering::Promote: 3352 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3353 Node->getValueType(0), 3354 isSigned); 3355 break; 3356 } 3357 break; 3358 case Expand: 3359 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3360 Node->getValueType(0), Node->getOperand(0)); 3361 break; 3362 case Promote: 3363 Tmp1 = PromoteOp(Node->getOperand(0)); 3364 if (isSigned) { 3365 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3366 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3367 } else { 3368 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3369 Node->getOperand(0).getValueType()); 3370 } 3371 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3372 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3373 break; 3374 } 3375 break; 3376 } 3377 case ISD::TRUNCATE: 3378 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3379 case Legal: 3380 Tmp1 = LegalizeOp(Node->getOperand(0)); 3381 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3382 break; 3383 case Expand: 3384 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3385 3386 // Since the result is legal, we should just be able to truncate the low 3387 // part of the source. 3388 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3389 break; 3390 case Promote: 3391 Result = PromoteOp(Node->getOperand(0)); 3392 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3393 break; 3394 } 3395 break; 3396 3397 case ISD::FP_TO_SINT: 3398 case ISD::FP_TO_UINT: 3399 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3400 case Legal: 3401 Tmp1 = LegalizeOp(Node->getOperand(0)); 3402 3403 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3404 default: assert(0 && "Unknown operation action!"); 3405 case TargetLowering::Custom: 3406 isCustom = true; 3407 // FALLTHROUGH 3408 case TargetLowering::Legal: 3409 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3410 if (isCustom) { 3411 Tmp1 = TLI.LowerOperation(Result, DAG); 3412 if (Tmp1.Val) Result = Tmp1; 3413 } 3414 break; 3415 case TargetLowering::Promote: 3416 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3417 Node->getOpcode() == ISD::FP_TO_SINT); 3418 break; 3419 case TargetLowering::Expand: 3420 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3421 SDOperand True, False; 3422 MVT::ValueType VT = Node->getOperand(0).getValueType(); 3423 MVT::ValueType NVT = Node->getValueType(0); 3424 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1; 3425 const uint64_t zero[] = {0, 0}; 3426 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero)); 3427 uint64_t x = 1ULL << ShiftAmt; 3428 (void)apf.convertFromZeroExtendedInteger 3429 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven); 3430 Tmp2 = DAG.getConstantFP(apf, VT); 3431 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 3432 Node->getOperand(0), Tmp2, ISD::SETLT); 3433 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3434 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3435 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3436 Tmp2)); 3437 False = DAG.getNode(ISD::XOR, NVT, False, 3438 DAG.getConstant(1ULL << ShiftAmt, NVT)); 3439 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3440 break; 3441 } else { 3442 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3443 } 3444 break; 3445 } 3446 break; 3447 case Expand: { 3448 MVT::ValueType VT = Op.getValueType(); 3449 MVT::ValueType OVT = Node->getOperand(0).getValueType(); 3450 // Convert ppcf128 to i32 3451 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3452 if (Node->getOpcode()==ISD::FP_TO_SINT) 3453 Result = DAG.getNode(ISD::FP_TO_SINT, VT, 3454 DAG.getNode(ISD::FP_ROUND, MVT::f64, 3455 (DAG.getNode(ISD::FP_ROUND_INREG, 3456 MVT::ppcf128, Node->getOperand(0), 3457 DAG.getValueType(MVT::f64))))); 3458 else { 3459 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3460 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3461 Tmp2 = DAG.getConstantFP(apf, OVT); 3462 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3463 // FIXME: generated code sucks. 3464 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3465 DAG.getNode(ISD::ADD, MVT::i32, 3466 DAG.getNode(ISD::FP_TO_SINT, VT, 3467 DAG.getNode(ISD::FSUB, OVT, 3468 Node->getOperand(0), Tmp2)), 3469 DAG.getConstant(0x80000000, MVT::i32)), 3470 DAG.getNode(ISD::FP_TO_SINT, VT, 3471 Node->getOperand(0)), 3472 DAG.getCondCode(ISD::SETGE)); 3473 } 3474 break; 3475 } 3476 // Convert f32 / f64 to i32 / i64. 3477 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3478 switch (Node->getOpcode()) { 3479 case ISD::FP_TO_SINT: { 3480 if (OVT == MVT::f32) 3481 LC = (VT == MVT::i32) 3482 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3483 else if (OVT == MVT::f64) 3484 LC = (VT == MVT::i32) 3485 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3486 else if (OVT == MVT::f80) { 3487 assert(VT == MVT::i64); 3488 LC = RTLIB::FPTOSINT_F80_I64; 3489 } 3490 else if (OVT == MVT::ppcf128) { 3491 assert(VT == MVT::i64); 3492 LC = RTLIB::FPTOSINT_PPCF128_I64; 3493 } 3494 break; 3495 } 3496 case ISD::FP_TO_UINT: { 3497 if (OVT == MVT::f32) 3498 LC = (VT == MVT::i32) 3499 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3500 else if (OVT == MVT::f64) 3501 LC = (VT == MVT::i32) 3502 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3503 else if (OVT == MVT::f80) { 3504 LC = (VT == MVT::i32) 3505 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64; 3506 } 3507 else if (OVT == MVT::ppcf128) { 3508 assert(VT == MVT::i64); 3509 LC = RTLIB::FPTOUINT_PPCF128_I64; 3510 } 3511 break; 3512 } 3513 default: assert(0 && "Unreachable!"); 3514 } 3515 SDOperand Dummy; 3516 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3517 false/*sign irrelevant*/, Dummy); 3518 break; 3519 } 3520 case Promote: 3521 Tmp1 = PromoteOp(Node->getOperand(0)); 3522 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3523 Result = LegalizeOp(Result); 3524 break; 3525 } 3526 break; 3527 3528 case ISD::FP_EXTEND: 3529 case ISD::FP_ROUND: { 3530 MVT::ValueType newVT = Op.getValueType(); 3531 MVT::ValueType oldVT = Op.getOperand(0).getValueType(); 3532 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) { 3533 if (Node->getOpcode() == ISD::FP_ROUND && oldVT == MVT::ppcf128) { 3534 SDOperand Lo, Hi; 3535 ExpandOp(Node->getOperand(0), Lo, Hi); 3536 if (newVT == MVT::f64) 3537 Result = Hi; 3538 else 3539 Result = DAG.getNode(ISD::FP_ROUND, newVT, Hi); 3540 break; 3541 } else { 3542 // The only other way we can lower this is to turn it into a STORE, 3543 // LOAD pair, targetting a temporary location (a stack slot). 3544 3545 // NOTE: there is a choice here between constantly creating new stack 3546 // slots and always reusing the same one. We currently always create 3547 // new ones, as reuse may inhibit scheduling. 3548 MVT::ValueType slotVT = 3549 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT; 3550 const Type *Ty = MVT::getTypeForValueType(slotVT); 3551 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 3552 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3553 MachineFunction &MF = DAG.getMachineFunction(); 3554 int SSFI = 3555 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3556 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3557 if (Node->getOpcode() == ISD::FP_EXTEND) { 3558 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), 3559 StackSlot, NULL, 0); 3560 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT, 3561 Result, StackSlot, NULL, 0, oldVT); 3562 } else { 3563 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3564 StackSlot, NULL, 0, newVT); 3565 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0); 3566 } 3567 break; 3568 } 3569 } 3570 } 3571 // FALL THROUGH 3572 case ISD::ANY_EXTEND: 3573 case ISD::ZERO_EXTEND: 3574 case ISD::SIGN_EXTEND: 3575 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3576 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3577 case Legal: 3578 Tmp1 = LegalizeOp(Node->getOperand(0)); 3579 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3580 break; 3581 case Promote: 3582 switch (Node->getOpcode()) { 3583 case ISD::ANY_EXTEND: 3584 Tmp1 = PromoteOp(Node->getOperand(0)); 3585 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3586 break; 3587 case ISD::ZERO_EXTEND: 3588 Result = PromoteOp(Node->getOperand(0)); 3589 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3590 Result = DAG.getZeroExtendInReg(Result, 3591 Node->getOperand(0).getValueType()); 3592 break; 3593 case ISD::SIGN_EXTEND: 3594 Result = PromoteOp(Node->getOperand(0)); 3595 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3596 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3597 Result, 3598 DAG.getValueType(Node->getOperand(0).getValueType())); 3599 break; 3600 case ISD::FP_EXTEND: 3601 Result = PromoteOp(Node->getOperand(0)); 3602 if (Result.getValueType() != Op.getValueType()) 3603 // Dynamically dead while we have only 2 FP types. 3604 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 3605 break; 3606 case ISD::FP_ROUND: 3607 Result = PromoteOp(Node->getOperand(0)); 3608 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 3609 break; 3610 } 3611 } 3612 break; 3613 case ISD::FP_ROUND_INREG: 3614 case ISD::SIGN_EXTEND_INREG: { 3615 Tmp1 = LegalizeOp(Node->getOperand(0)); 3616 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3617 3618 // If this operation is not supported, convert it to a shl/shr or load/store 3619 // pair. 3620 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3621 default: assert(0 && "This action not supported for this op yet!"); 3622 case TargetLowering::Legal: 3623 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3624 break; 3625 case TargetLowering::Expand: 3626 // If this is an integer extend and shifts are supported, do that. 3627 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3628 // NOTE: we could fall back on load/store here too for targets without 3629 // SAR. However, it is doubtful that any exist. 3630 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3631 MVT::getSizeInBits(ExtraVT); 3632 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3633 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3634 Node->getOperand(0), ShiftCst); 3635 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3636 Result, ShiftCst); 3637 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3638 // The only way we can lower this is to turn it into a TRUNCSTORE, 3639 // EXTLOAD pair, targetting a temporary location (a stack slot). 3640 3641 // NOTE: there is a choice here between constantly creating new stack 3642 // slots and always reusing the same one. We currently always create 3643 // new ones, as reuse may inhibit scheduling. 3644 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 3645 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 3646 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3647 MachineFunction &MF = DAG.getMachineFunction(); 3648 int SSFI = 3649 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3650 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3651 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3652 StackSlot, NULL, 0, ExtraVT); 3653 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 3654 Result, StackSlot, NULL, 0, ExtraVT); 3655 } else { 3656 assert(0 && "Unknown op"); 3657 } 3658 break; 3659 } 3660 break; 3661 } 3662 case ISD::TRAMPOLINE: { 3663 SDOperand Ops[6]; 3664 for (unsigned i = 0; i != 6; ++i) 3665 Ops[i] = LegalizeOp(Node->getOperand(i)); 3666 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3667 // The only option for this node is to custom lower it. 3668 Result = TLI.LowerOperation(Result, DAG); 3669 assert(Result.Val && "Should always custom lower!"); 3670 3671 // Since trampoline produces two values, make sure to remember that we 3672 // legalized both of them. 3673 Tmp1 = LegalizeOp(Result.getValue(1)); 3674 Result = LegalizeOp(Result); 3675 AddLegalizedOperand(SDOperand(Node, 0), Result); 3676 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3677 return Op.ResNo ? Tmp1 : Result; 3678 } 3679 } 3680 3681 assert(Result.getValueType() == Op.getValueType() && 3682 "Bad legalization!"); 3683 3684 // Make sure that the generated code is itself legal. 3685 if (Result != Op) 3686 Result = LegalizeOp(Result); 3687 3688 // Note that LegalizeOp may be reentered even from single-use nodes, which 3689 // means that we always must cache transformed nodes. 3690 AddLegalizedOperand(Op, Result); 3691 return Result; 3692} 3693 3694/// PromoteOp - Given an operation that produces a value in an invalid type, 3695/// promote it to compute the value into a larger type. The produced value will 3696/// have the correct bits for the low portion of the register, but no guarantee 3697/// is made about the top bits: it may be zero, sign-extended, or garbage. 3698SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 3699 MVT::ValueType VT = Op.getValueType(); 3700 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3701 assert(getTypeAction(VT) == Promote && 3702 "Caller should expand or legalize operands that are not promotable!"); 3703 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 3704 "Cannot promote to smaller type!"); 3705 3706 SDOperand Tmp1, Tmp2, Tmp3; 3707 SDOperand Result; 3708 SDNode *Node = Op.Val; 3709 3710 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 3711 if (I != PromotedNodes.end()) return I->second; 3712 3713 switch (Node->getOpcode()) { 3714 case ISD::CopyFromReg: 3715 assert(0 && "CopyFromReg must be legal!"); 3716 default: 3717#ifndef NDEBUG 3718 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 3719#endif 3720 assert(0 && "Do not know how to promote this operator!"); 3721 abort(); 3722 case ISD::UNDEF: 3723 Result = DAG.getNode(ISD::UNDEF, NVT); 3724 break; 3725 case ISD::Constant: 3726 if (VT != MVT::i1) 3727 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 3728 else 3729 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 3730 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 3731 break; 3732 case ISD::ConstantFP: 3733 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 3734 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 3735 break; 3736 3737 case ISD::SETCC: 3738 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 3739 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 3740 Node->getOperand(1), Node->getOperand(2)); 3741 break; 3742 3743 case ISD::TRUNCATE: 3744 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3745 case Legal: 3746 Result = LegalizeOp(Node->getOperand(0)); 3747 assert(Result.getValueType() >= NVT && 3748 "This truncation doesn't make sense!"); 3749 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 3750 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 3751 break; 3752 case Promote: 3753 // The truncation is not required, because we don't guarantee anything 3754 // about high bits anyway. 3755 Result = PromoteOp(Node->getOperand(0)); 3756 break; 3757 case Expand: 3758 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3759 // Truncate the low part of the expanded value to the result type 3760 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 3761 } 3762 break; 3763 case ISD::SIGN_EXTEND: 3764 case ISD::ZERO_EXTEND: 3765 case ISD::ANY_EXTEND: 3766 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3767 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 3768 case Legal: 3769 // Input is legal? Just do extend all the way to the larger type. 3770 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3771 break; 3772 case Promote: 3773 // Promote the reg if it's smaller. 3774 Result = PromoteOp(Node->getOperand(0)); 3775 // The high bits are not guaranteed to be anything. Insert an extend. 3776 if (Node->getOpcode() == ISD::SIGN_EXTEND) 3777 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3778 DAG.getValueType(Node->getOperand(0).getValueType())); 3779 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 3780 Result = DAG.getZeroExtendInReg(Result, 3781 Node->getOperand(0).getValueType()); 3782 break; 3783 } 3784 break; 3785 case ISD::BIT_CONVERT: 3786 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3787 Result = PromoteOp(Result); 3788 break; 3789 3790 case ISD::FP_EXTEND: 3791 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 3792 case ISD::FP_ROUND: 3793 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3794 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 3795 case Promote: assert(0 && "Unreachable with 2 FP types!"); 3796 case Legal: 3797 // Input is legal? Do an FP_ROUND_INREG. 3798 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 3799 DAG.getValueType(VT)); 3800 break; 3801 } 3802 break; 3803 3804 case ISD::SINT_TO_FP: 3805 case ISD::UINT_TO_FP: 3806 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3807 case Legal: 3808 // No extra round required here. 3809 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3810 break; 3811 3812 case Promote: 3813 Result = PromoteOp(Node->getOperand(0)); 3814 if (Node->getOpcode() == ISD::SINT_TO_FP) 3815 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3816 Result, 3817 DAG.getValueType(Node->getOperand(0).getValueType())); 3818 else 3819 Result = DAG.getZeroExtendInReg(Result, 3820 Node->getOperand(0).getValueType()); 3821 // No extra round required here. 3822 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3823 break; 3824 case Expand: 3825 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3826 Node->getOperand(0)); 3827 // Round if we cannot tolerate excess precision. 3828 if (NoExcessFPPrecision) 3829 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3830 DAG.getValueType(VT)); 3831 break; 3832 } 3833 break; 3834 3835 case ISD::SIGN_EXTEND_INREG: 3836 Result = PromoteOp(Node->getOperand(0)); 3837 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3838 Node->getOperand(1)); 3839 break; 3840 case ISD::FP_TO_SINT: 3841 case ISD::FP_TO_UINT: 3842 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3843 case Legal: 3844 case Expand: 3845 Tmp1 = Node->getOperand(0); 3846 break; 3847 case Promote: 3848 // The input result is prerounded, so we don't have to do anything 3849 // special. 3850 Tmp1 = PromoteOp(Node->getOperand(0)); 3851 break; 3852 } 3853 // If we're promoting a UINT to a larger size, check to see if the new node 3854 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3855 // we can use that instead. This allows us to generate better code for 3856 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3857 // legal, such as PowerPC. 3858 if (Node->getOpcode() == ISD::FP_TO_UINT && 3859 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3860 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3861 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3862 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3863 } else { 3864 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3865 } 3866 break; 3867 3868 case ISD::FABS: 3869 case ISD::FNEG: 3870 Tmp1 = PromoteOp(Node->getOperand(0)); 3871 assert(Tmp1.getValueType() == NVT); 3872 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3873 // NOTE: we do not have to do any extra rounding here for 3874 // NoExcessFPPrecision, because we know the input will have the appropriate 3875 // precision, and these operations don't modify precision at all. 3876 break; 3877 3878 case ISD::FSQRT: 3879 case ISD::FSIN: 3880 case ISD::FCOS: 3881 Tmp1 = PromoteOp(Node->getOperand(0)); 3882 assert(Tmp1.getValueType() == NVT); 3883 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3884 if (NoExcessFPPrecision) 3885 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3886 DAG.getValueType(VT)); 3887 break; 3888 3889 case ISD::FPOWI: { 3890 // Promote f32 powi to f64 powi. Note that this could insert a libcall 3891 // directly as well, which may be better. 3892 Tmp1 = PromoteOp(Node->getOperand(0)); 3893 assert(Tmp1.getValueType() == NVT); 3894 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 3895 if (NoExcessFPPrecision) 3896 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3897 DAG.getValueType(VT)); 3898 break; 3899 } 3900 3901 case ISD::AND: 3902 case ISD::OR: 3903 case ISD::XOR: 3904 case ISD::ADD: 3905 case ISD::SUB: 3906 case ISD::MUL: 3907 // The input may have strange things in the top bits of the registers, but 3908 // these operations don't care. They may have weird bits going out, but 3909 // that too is okay if they are integer operations. 3910 Tmp1 = PromoteOp(Node->getOperand(0)); 3911 Tmp2 = PromoteOp(Node->getOperand(1)); 3912 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3913 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3914 break; 3915 case ISD::FADD: 3916 case ISD::FSUB: 3917 case ISD::FMUL: 3918 Tmp1 = PromoteOp(Node->getOperand(0)); 3919 Tmp2 = PromoteOp(Node->getOperand(1)); 3920 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3921 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3922 3923 // Floating point operations will give excess precision that we may not be 3924 // able to tolerate. If we DO allow excess precision, just leave it, 3925 // otherwise excise it. 3926 // FIXME: Why would we need to round FP ops more than integer ones? 3927 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3928 if (NoExcessFPPrecision) 3929 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3930 DAG.getValueType(VT)); 3931 break; 3932 3933 case ISD::SDIV: 3934 case ISD::SREM: 3935 // These operators require that their input be sign extended. 3936 Tmp1 = PromoteOp(Node->getOperand(0)); 3937 Tmp2 = PromoteOp(Node->getOperand(1)); 3938 if (MVT::isInteger(NVT)) { 3939 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3940 DAG.getValueType(VT)); 3941 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3942 DAG.getValueType(VT)); 3943 } 3944 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3945 3946 // Perform FP_ROUND: this is probably overly pessimistic. 3947 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 3948 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3949 DAG.getValueType(VT)); 3950 break; 3951 case ISD::FDIV: 3952 case ISD::FREM: 3953 case ISD::FCOPYSIGN: 3954 // These operators require that their input be fp extended. 3955 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3956 case Legal: 3957 Tmp1 = LegalizeOp(Node->getOperand(0)); 3958 break; 3959 case Promote: 3960 Tmp1 = PromoteOp(Node->getOperand(0)); 3961 break; 3962 case Expand: 3963 assert(0 && "not implemented"); 3964 } 3965 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3966 case Legal: 3967 Tmp2 = LegalizeOp(Node->getOperand(1)); 3968 break; 3969 case Promote: 3970 Tmp2 = PromoteOp(Node->getOperand(1)); 3971 break; 3972 case Expand: 3973 assert(0 && "not implemented"); 3974 } 3975 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3976 3977 // Perform FP_ROUND: this is probably overly pessimistic. 3978 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 3979 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3980 DAG.getValueType(VT)); 3981 break; 3982 3983 case ISD::UDIV: 3984 case ISD::UREM: 3985 // These operators require that their input be zero extended. 3986 Tmp1 = PromoteOp(Node->getOperand(0)); 3987 Tmp2 = PromoteOp(Node->getOperand(1)); 3988 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 3989 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3990 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3991 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3992 break; 3993 3994 case ISD::SHL: 3995 Tmp1 = PromoteOp(Node->getOperand(0)); 3996 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 3997 break; 3998 case ISD::SRA: 3999 // The input value must be properly sign extended. 4000 Tmp1 = PromoteOp(Node->getOperand(0)); 4001 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4002 DAG.getValueType(VT)); 4003 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4004 break; 4005 case ISD::SRL: 4006 // The input value must be properly zero extended. 4007 Tmp1 = PromoteOp(Node->getOperand(0)); 4008 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4009 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4010 break; 4011 4012 case ISD::VAARG: 4013 Tmp1 = Node->getOperand(0); // Get the chain. 4014 Tmp2 = Node->getOperand(1); // Get the pointer. 4015 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4016 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4017 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 4018 } else { 4019 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 4020 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 4021 SV->getValue(), SV->getOffset()); 4022 // Increment the pointer, VAList, to the next vaarg 4023 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4024 DAG.getConstant(MVT::getSizeInBits(VT)/8, 4025 TLI.getPointerTy())); 4026 // Store the incremented VAList to the legalized pointer 4027 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 4028 SV->getOffset()); 4029 // Load the actual argument out of the pointer VAList 4030 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4031 } 4032 // Remember that we legalized the chain. 4033 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4034 break; 4035 4036 case ISD::LOAD: { 4037 LoadSDNode *LD = cast<LoadSDNode>(Node); 4038 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4039 ? ISD::EXTLOAD : LD->getExtensionType(); 4040 Result = DAG.getExtLoad(ExtType, NVT, 4041 LD->getChain(), LD->getBasePtr(), 4042 LD->getSrcValue(), LD->getSrcValueOffset(), 4043 LD->getLoadedVT(), 4044 LD->isVolatile(), 4045 LD->getAlignment()); 4046 // Remember that we legalized the chain. 4047 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4048 break; 4049 } 4050 case ISD::SELECT: 4051 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4052 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4053 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 4054 break; 4055 case ISD::SELECT_CC: 4056 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4057 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4058 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4059 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4060 break; 4061 case ISD::BSWAP: 4062 Tmp1 = Node->getOperand(0); 4063 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4064 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4065 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4066 DAG.getConstant(MVT::getSizeInBits(NVT) - 4067 MVT::getSizeInBits(VT), 4068 TLI.getShiftAmountTy())); 4069 break; 4070 case ISD::CTPOP: 4071 case ISD::CTTZ: 4072 case ISD::CTLZ: 4073 // Zero extend the argument 4074 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4075 // Perform the larger operation, then subtract if needed. 4076 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4077 switch(Node->getOpcode()) { 4078 case ISD::CTPOP: 4079 Result = Tmp1; 4080 break; 4081 case ISD::CTTZ: 4082 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4083 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 4084 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 4085 ISD::SETEQ); 4086 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4087 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); 4088 break; 4089 case ISD::CTLZ: 4090 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4091 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4092 DAG.getConstant(MVT::getSizeInBits(NVT) - 4093 MVT::getSizeInBits(VT), NVT)); 4094 break; 4095 } 4096 break; 4097 case ISD::EXTRACT_SUBVECTOR: 4098 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4099 break; 4100 case ISD::EXTRACT_VECTOR_ELT: 4101 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4102 break; 4103 } 4104 4105 assert(Result.Val && "Didn't set a result!"); 4106 4107 // Make sure the result is itself legal. 4108 Result = LegalizeOp(Result); 4109 4110 // Remember that we promoted this! 4111 AddPromotedOperand(Op, Result); 4112 return Result; 4113} 4114 4115/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4116/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4117/// based on the vector type. The return type of this matches the element type 4118/// of the vector, which may not be legal for the target. 4119SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 4120 // We know that operand #0 is the Vec vector. If the index is a constant 4121 // or if the invec is a supported hardware type, we can use it. Otherwise, 4122 // lower to a store then an indexed load. 4123 SDOperand Vec = Op.getOperand(0); 4124 SDOperand Idx = Op.getOperand(1); 4125 4126 MVT::ValueType TVT = Vec.getValueType(); 4127 unsigned NumElems = MVT::getVectorNumElements(TVT); 4128 4129 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4130 default: assert(0 && "This action is not supported yet!"); 4131 case TargetLowering::Custom: { 4132 Vec = LegalizeOp(Vec); 4133 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4134 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 4135 if (Tmp3.Val) 4136 return Tmp3; 4137 break; 4138 } 4139 case TargetLowering::Legal: 4140 if (isTypeLegal(TVT)) { 4141 Vec = LegalizeOp(Vec); 4142 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4143 return Op; 4144 } 4145 break; 4146 case TargetLowering::Expand: 4147 break; 4148 } 4149 4150 if (NumElems == 1) { 4151 // This must be an access of the only element. Return it. 4152 Op = ScalarizeVectorOp(Vec); 4153 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4154 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4155 SDOperand Lo, Hi; 4156 SplitVectorOp(Vec, Lo, Hi); 4157 if (CIdx->getValue() < NumElems/2) { 4158 Vec = Lo; 4159 } else { 4160 Vec = Hi; 4161 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, 4162 Idx.getValueType()); 4163 } 4164 4165 // It's now an extract from the appropriate high or low part. Recurse. 4166 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4167 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4168 } else { 4169 // Store the value to a temporary stack slot, then LOAD the scalar 4170 // element back out. 4171 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4172 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4173 4174 // Add the offset to the index. 4175 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 4176 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4177 DAG.getConstant(EltSize, Idx.getValueType())); 4178 4179 if (MVT::getSizeInBits(Idx.getValueType()) > 4180 MVT::getSizeInBits(TLI.getPointerTy())) 4181 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4182 else 4183 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4184 4185 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4186 4187 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4188 } 4189 return Op; 4190} 4191 4192/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4193/// we assume the operation can be split if it is not already legal. 4194SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 4195 // We know that operand #0 is the Vec vector. For now we assume the index 4196 // is a constant and that the extracted result is a supported hardware type. 4197 SDOperand Vec = Op.getOperand(0); 4198 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 4199 4200 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); 4201 4202 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { 4203 // This must be an access of the desired vector length. Return it. 4204 return Vec; 4205 } 4206 4207 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4208 SDOperand Lo, Hi; 4209 SplitVectorOp(Vec, Lo, Hi); 4210 if (CIdx->getValue() < NumElems/2) { 4211 Vec = Lo; 4212 } else { 4213 Vec = Hi; 4214 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4215 } 4216 4217 // It's now an extract from the appropriate high or low part. Recurse. 4218 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4219 return ExpandEXTRACT_SUBVECTOR(Op); 4220} 4221 4222/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4223/// with condition CC on the current target. This usually involves legalizing 4224/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4225/// there may be no choice but to create a new SetCC node to represent the 4226/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4227/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 4228void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 4229 SDOperand &RHS, 4230 SDOperand &CC) { 4231 SDOperand Tmp1, Tmp2, Tmp3, Result; 4232 4233 switch (getTypeAction(LHS.getValueType())) { 4234 case Legal: 4235 Tmp1 = LegalizeOp(LHS); // LHS 4236 Tmp2 = LegalizeOp(RHS); // RHS 4237 break; 4238 case Promote: 4239 Tmp1 = PromoteOp(LHS); // LHS 4240 Tmp2 = PromoteOp(RHS); // RHS 4241 4242 // If this is an FP compare, the operands have already been extended. 4243 if (MVT::isInteger(LHS.getValueType())) { 4244 MVT::ValueType VT = LHS.getValueType(); 4245 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4246 4247 // Otherwise, we have to insert explicit sign or zero extends. Note 4248 // that we could insert sign extends for ALL conditions, but zero extend 4249 // is cheaper on many machines (an AND instead of two shifts), so prefer 4250 // it. 4251 switch (cast<CondCodeSDNode>(CC)->get()) { 4252 default: assert(0 && "Unknown integer comparison!"); 4253 case ISD::SETEQ: 4254 case ISD::SETNE: 4255 case ISD::SETUGE: 4256 case ISD::SETUGT: 4257 case ISD::SETULE: 4258 case ISD::SETULT: 4259 // ALL of these operations will work if we either sign or zero extend 4260 // the operands (including the unsigned comparisons!). Zero extend is 4261 // usually a simpler/cheaper operation, so prefer it. 4262 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4263 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4264 break; 4265 case ISD::SETGE: 4266 case ISD::SETGT: 4267 case ISD::SETLT: 4268 case ISD::SETLE: 4269 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4270 DAG.getValueType(VT)); 4271 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4272 DAG.getValueType(VT)); 4273 break; 4274 } 4275 } 4276 break; 4277 case Expand: { 4278 MVT::ValueType VT = LHS.getValueType(); 4279 if (VT == MVT::f32 || VT == MVT::f64) { 4280 // Expand into one or more soft-fp libcall(s). 4281 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 4282 switch (cast<CondCodeSDNode>(CC)->get()) { 4283 case ISD::SETEQ: 4284 case ISD::SETOEQ: 4285 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4286 break; 4287 case ISD::SETNE: 4288 case ISD::SETUNE: 4289 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4290 break; 4291 case ISD::SETGE: 4292 case ISD::SETOGE: 4293 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4294 break; 4295 case ISD::SETLT: 4296 case ISD::SETOLT: 4297 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4298 break; 4299 case ISD::SETLE: 4300 case ISD::SETOLE: 4301 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4302 break; 4303 case ISD::SETGT: 4304 case ISD::SETOGT: 4305 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4306 break; 4307 case ISD::SETUO: 4308 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4309 break; 4310 case ISD::SETO: 4311 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4312 break; 4313 default: 4314 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4315 switch (cast<CondCodeSDNode>(CC)->get()) { 4316 case ISD::SETONE: 4317 // SETONE = SETOLT | SETOGT 4318 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4319 // Fallthrough 4320 case ISD::SETUGT: 4321 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4322 break; 4323 case ISD::SETUGE: 4324 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4325 break; 4326 case ISD::SETULT: 4327 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4328 break; 4329 case ISD::SETULE: 4330 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4331 break; 4332 case ISD::SETUEQ: 4333 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4334 break; 4335 default: assert(0 && "Unsupported FP setcc!"); 4336 } 4337 } 4338 4339 SDOperand Dummy; 4340 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 4341 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4342 false /*sign irrelevant*/, Dummy); 4343 Tmp2 = DAG.getConstant(0, MVT::i32); 4344 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4345 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4346 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); 4347 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 4348 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4349 false /*sign irrelevant*/, Dummy); 4350 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, 4351 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4352 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4353 Tmp2 = SDOperand(); 4354 } 4355 LHS = Tmp1; 4356 RHS = Tmp2; 4357 return; 4358 } 4359 4360 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4361 ExpandOp(LHS, LHSLo, LHSHi); 4362 ExpandOp(RHS, RHSLo, RHSHi); 4363 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4364 4365 if (VT==MVT::ppcf128) { 4366 // FIXME: This generated code sucks. We want to generate 4367 // FCMP crN, hi1, hi2 4368 // BNE crN, L: 4369 // FCMP crN, lo1, lo2 4370 // The following can be improved, but not that much. 4371 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4372 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode); 4373 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4374 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE); 4375 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode); 4376 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4377 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4378 Tmp2 = SDOperand(); 4379 break; 4380 } 4381 4382 switch (CCCode) { 4383 case ISD::SETEQ: 4384 case ISD::SETNE: 4385 if (RHSLo == RHSHi) 4386 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4387 if (RHSCST->isAllOnesValue()) { 4388 // Comparison to -1. 4389 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4390 Tmp2 = RHSLo; 4391 break; 4392 } 4393 4394 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4395 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4396 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4397 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4398 break; 4399 default: 4400 // If this is a comparison of the sign bit, just look at the top part. 4401 // X > -1, x < 0 4402 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4403 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4404 CST->getValue() == 0) || // X < 0 4405 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4406 CST->isAllOnesValue())) { // X > -1 4407 Tmp1 = LHSHi; 4408 Tmp2 = RHSHi; 4409 break; 4410 } 4411 4412 // FIXME: This generated code sucks. 4413 ISD::CondCode LowCC; 4414 switch (CCCode) { 4415 default: assert(0 && "Unknown integer setcc!"); 4416 case ISD::SETLT: 4417 case ISD::SETULT: LowCC = ISD::SETULT; break; 4418 case ISD::SETGT: 4419 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4420 case ISD::SETLE: 4421 case ISD::SETULE: LowCC = ISD::SETULE; break; 4422 case ISD::SETGE: 4423 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4424 } 4425 4426 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4427 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4428 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4429 4430 // NOTE: on targets without efficient SELECT of bools, we can always use 4431 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4432 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4433 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, 4434 false, DagCombineInfo); 4435 if (!Tmp1.Val) 4436 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 4437 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4438 CCCode, false, DagCombineInfo); 4439 if (!Tmp2.Val) 4440 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC); 4441 4442 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4443 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4444 if ((Tmp1C && Tmp1C->getValue() == 0) || 4445 (Tmp2C && Tmp2C->getValue() == 0 && 4446 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4447 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4448 (Tmp2C && Tmp2C->getValue() == 1 && 4449 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4450 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4451 // low part is known false, returns high part. 4452 // For LE / GE, if high part is known false, ignore the low part. 4453 // For LT / GT, if high part is known true, ignore the low part. 4454 Tmp1 = Tmp2; 4455 Tmp2 = SDOperand(); 4456 } else { 4457 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4458 ISD::SETEQ, false, DagCombineInfo); 4459 if (!Result.Val) 4460 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4461 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4462 Result, Tmp1, Tmp2)); 4463 Tmp1 = Result; 4464 Tmp2 = SDOperand(); 4465 } 4466 } 4467 } 4468 } 4469 LHS = Tmp1; 4470 RHS = Tmp2; 4471} 4472 4473/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 4474/// The resultant code need not be legal. Note that SrcOp is the input operand 4475/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 4476SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 4477 SDOperand SrcOp) { 4478 // Create the stack frame object. 4479 SDOperand FIPtr = DAG.CreateStackTemporary(DestVT); 4480 4481 // Emit a store to the stack slot. 4482 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); 4483 // Result is a load from the stack slot. 4484 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4485} 4486 4487SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4488 // Create a vector sized/aligned stack slot, store the value to element #0, 4489 // then load the whole vector back out. 4490 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4491 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4492 NULL, 0); 4493 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); 4494} 4495 4496 4497/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4498/// support the operation, but do support the resultant vector type. 4499SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4500 4501 // If the only non-undef value is the low element, turn this into a 4502 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4503 unsigned NumElems = Node->getNumOperands(); 4504 bool isOnlyLowElement = true; 4505 SDOperand SplatValue = Node->getOperand(0); 4506 std::map<SDOperand, std::vector<unsigned> > Values; 4507 Values[SplatValue].push_back(0); 4508 bool isConstant = true; 4509 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4510 SplatValue.getOpcode() != ISD::UNDEF) 4511 isConstant = false; 4512 4513 for (unsigned i = 1; i < NumElems; ++i) { 4514 SDOperand V = Node->getOperand(i); 4515 Values[V].push_back(i); 4516 if (V.getOpcode() != ISD::UNDEF) 4517 isOnlyLowElement = false; 4518 if (SplatValue != V) 4519 SplatValue = SDOperand(0,0); 4520 4521 // If this isn't a constant element or an undef, we can't use a constant 4522 // pool load. 4523 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4524 V.getOpcode() != ISD::UNDEF) 4525 isConstant = false; 4526 } 4527 4528 if (isOnlyLowElement) { 4529 // If the low element is an undef too, then this whole things is an undef. 4530 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4531 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4532 // Otherwise, turn this into a scalar_to_vector node. 4533 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4534 Node->getOperand(0)); 4535 } 4536 4537 // If all elements are constants, create a load from the constant pool. 4538 if (isConstant) { 4539 MVT::ValueType VT = Node->getValueType(0); 4540 const Type *OpNTy = 4541 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 4542 std::vector<Constant*> CV; 4543 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4544 if (ConstantFPSDNode *V = 4545 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4546 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF())); 4547 } else if (ConstantSDNode *V = 4548 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4549 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 4550 } else { 4551 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4552 CV.push_back(UndefValue::get(OpNTy)); 4553 } 4554 } 4555 Constant *CP = ConstantVector::get(CV); 4556 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4557 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 4558 } 4559 4560 if (SplatValue.Val) { // Splat of one value? 4561 // Build the shuffle constant vector: <0, 0, 0, 0> 4562 MVT::ValueType MaskVT = 4563 MVT::getIntVectorWithNumElements(NumElems); 4564 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); 4565 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4566 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4567 &ZeroVec[0], ZeroVec.size()); 4568 4569 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4570 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 4571 // Get the splatted value into the low element of a vector register. 4572 SDOperand LowValVec = 4573 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 4574 4575 // Return shuffle(LowValVec, undef, <0,0,0,0>) 4576 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 4577 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 4578 SplatMask); 4579 } 4580 } 4581 4582 // If there are only two unique elements, we may be able to turn this into a 4583 // vector shuffle. 4584 if (Values.size() == 2) { 4585 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 4586 MVT::ValueType MaskVT = 4587 MVT::getIntVectorWithNumElements(NumElems); 4588 std::vector<SDOperand> MaskVec(NumElems); 4589 unsigned i = 0; 4590 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4591 E = Values.end(); I != E; ++I) { 4592 for (std::vector<unsigned>::iterator II = I->second.begin(), 4593 EE = I->second.end(); II != EE; ++II) 4594 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT)); 4595 i += NumElems; 4596 } 4597 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4598 &MaskVec[0], MaskVec.size()); 4599 4600 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4601 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 4602 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 4603 SmallVector<SDOperand, 8> Ops; 4604 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4605 E = Values.end(); I != E; ++I) { 4606 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4607 I->first); 4608 Ops.push_back(Op); 4609 } 4610 Ops.push_back(ShuffleMask); 4611 4612 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 4613 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 4614 &Ops[0], Ops.size()); 4615 } 4616 } 4617 4618 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 4619 // aligned object on the stack, store each element into it, then load 4620 // the result as a vector. 4621 MVT::ValueType VT = Node->getValueType(0); 4622 // Create the stack frame object. 4623 SDOperand FIPtr = DAG.CreateStackTemporary(VT); 4624 4625 // Emit a store of each element to the stack slot. 4626 SmallVector<SDOperand, 8> Stores; 4627 unsigned TypeByteSize = 4628 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 4629 // Store (in the right endianness) the elements to memory. 4630 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4631 // Ignore undef elements. 4632 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4633 4634 unsigned Offset = TypeByteSize*i; 4635 4636 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 4637 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 4638 4639 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 4640 NULL, 0)); 4641 } 4642 4643 SDOperand StoreChain; 4644 if (!Stores.empty()) // Not all undef elements? 4645 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4646 &Stores[0], Stores.size()); 4647 else 4648 StoreChain = DAG.getEntryNode(); 4649 4650 // Result is a load from the stack slot. 4651 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 4652} 4653 4654void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 4655 SDOperand Op, SDOperand Amt, 4656 SDOperand &Lo, SDOperand &Hi) { 4657 // Expand the subcomponents. 4658 SDOperand LHSL, LHSH; 4659 ExpandOp(Op, LHSL, LHSH); 4660 4661 SDOperand Ops[] = { LHSL, LHSH, Amt }; 4662 MVT::ValueType VT = LHSL.getValueType(); 4663 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 4664 Hi = Lo.getValue(1); 4665} 4666 4667 4668/// ExpandShift - Try to find a clever way to expand this shift operation out to 4669/// smaller elements. If we can't find a way that is more efficient than a 4670/// libcall on this target, return false. Otherwise, return true with the 4671/// low-parts expanded into Lo and Hi. 4672bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 4673 SDOperand &Lo, SDOperand &Hi) { 4674 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 4675 "This is not a shift!"); 4676 4677 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 4678 SDOperand ShAmt = LegalizeOp(Amt); 4679 MVT::ValueType ShTy = ShAmt.getValueType(); 4680 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 4681 unsigned NVTBits = MVT::getSizeInBits(NVT); 4682 4683 // Handle the case when Amt is an immediate. 4684 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 4685 unsigned Cst = CN->getValue(); 4686 // Expand the incoming operand to be shifted, so that we have its parts 4687 SDOperand InL, InH; 4688 ExpandOp(Op, InL, InH); 4689 switch(Opc) { 4690 case ISD::SHL: 4691 if (Cst > VTBits) { 4692 Lo = DAG.getConstant(0, NVT); 4693 Hi = DAG.getConstant(0, NVT); 4694 } else if (Cst > NVTBits) { 4695 Lo = DAG.getConstant(0, NVT); 4696 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 4697 } else if (Cst == NVTBits) { 4698 Lo = DAG.getConstant(0, NVT); 4699 Hi = InL; 4700 } else { 4701 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 4702 Hi = DAG.getNode(ISD::OR, NVT, 4703 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 4704 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 4705 } 4706 return true; 4707 case ISD::SRL: 4708 if (Cst > VTBits) { 4709 Lo = DAG.getConstant(0, NVT); 4710 Hi = DAG.getConstant(0, NVT); 4711 } else if (Cst > NVTBits) { 4712 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 4713 Hi = DAG.getConstant(0, NVT); 4714 } else if (Cst == NVTBits) { 4715 Lo = InH; 4716 Hi = DAG.getConstant(0, NVT); 4717 } else { 4718 Lo = DAG.getNode(ISD::OR, NVT, 4719 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4720 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4721 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 4722 } 4723 return true; 4724 case ISD::SRA: 4725 if (Cst > VTBits) { 4726 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 4727 DAG.getConstant(NVTBits-1, ShTy)); 4728 } else if (Cst > NVTBits) { 4729 Lo = DAG.getNode(ISD::SRA, NVT, InH, 4730 DAG.getConstant(Cst-NVTBits, ShTy)); 4731 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4732 DAG.getConstant(NVTBits-1, ShTy)); 4733 } else if (Cst == NVTBits) { 4734 Lo = InH; 4735 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4736 DAG.getConstant(NVTBits-1, ShTy)); 4737 } else { 4738 Lo = DAG.getNode(ISD::OR, NVT, 4739 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4740 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4741 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 4742 } 4743 return true; 4744 } 4745 } 4746 4747 // Okay, the shift amount isn't constant. However, if we can tell that it is 4748 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 4749 uint64_t Mask = NVTBits, KnownZero, KnownOne; 4750 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 4751 4752 // If we know that the high bit of the shift amount is one, then we can do 4753 // this as a couple of simple shifts. 4754 if (KnownOne & Mask) { 4755 // Mask out the high bit, which we know is set. 4756 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 4757 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4758 4759 // Expand the incoming operand to be shifted, so that we have its parts 4760 SDOperand InL, InH; 4761 ExpandOp(Op, InL, InH); 4762 switch(Opc) { 4763 case ISD::SHL: 4764 Lo = DAG.getConstant(0, NVT); // Low part is zero. 4765 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 4766 return true; 4767 case ISD::SRL: 4768 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 4769 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 4770 return true; 4771 case ISD::SRA: 4772 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 4773 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4774 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 4775 return true; 4776 } 4777 } 4778 4779 // If we know that the high bit of the shift amount is zero, then we can do 4780 // this as a couple of simple shifts. 4781 if (KnownZero & Mask) { 4782 // Compute 32-amt. 4783 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 4784 DAG.getConstant(NVTBits, Amt.getValueType()), 4785 Amt); 4786 4787 // Expand the incoming operand to be shifted, so that we have its parts 4788 SDOperand InL, InH; 4789 ExpandOp(Op, InL, InH); 4790 switch(Opc) { 4791 case ISD::SHL: 4792 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 4793 Hi = DAG.getNode(ISD::OR, NVT, 4794 DAG.getNode(ISD::SHL, NVT, InH, Amt), 4795 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 4796 return true; 4797 case ISD::SRL: 4798 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 4799 Lo = DAG.getNode(ISD::OR, NVT, 4800 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4801 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4802 return true; 4803 case ISD::SRA: 4804 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 4805 Lo = DAG.getNode(ISD::OR, NVT, 4806 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4807 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4808 return true; 4809 } 4810 } 4811 4812 return false; 4813} 4814 4815 4816// ExpandLibCall - Expand a node into a call to a libcall. If the result value 4817// does not fit into a register, return the lo part and set the hi part to the 4818// by-reg argument. If it does fit into a single register, return the result 4819// and leave the Hi part unset. 4820SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 4821 bool isSigned, SDOperand &Hi) { 4822 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 4823 // The input chain to this libcall is the entry node of the function. 4824 // Legalizing the call will automatically add the previous call to the 4825 // dependence. 4826 SDOperand InChain = DAG.getEntryNode(); 4827 4828 TargetLowering::ArgListTy Args; 4829 TargetLowering::ArgListEntry Entry; 4830 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4831 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 4832 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 4833 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 4834 Entry.isSExt = isSigned; 4835 Args.push_back(Entry); 4836 } 4837 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 4838 4839 // Splice the libcall in wherever FindInputOutputChains tells us to. 4840 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 4841 std::pair<SDOperand,SDOperand> CallInfo = 4842 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false, 4843 Callee, Args, DAG); 4844 4845 // Legalize the call sequence, starting with the chain. This will advance 4846 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 4847 // was added by LowerCallTo (guaranteeing proper serialization of calls). 4848 LegalizeOp(CallInfo.second); 4849 SDOperand Result; 4850 switch (getTypeAction(CallInfo.first.getValueType())) { 4851 default: assert(0 && "Unknown thing"); 4852 case Legal: 4853 Result = CallInfo.first; 4854 break; 4855 case Expand: 4856 ExpandOp(CallInfo.first, Result, Hi); 4857 break; 4858 } 4859 return Result; 4860} 4861 4862 4863/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 4864/// 4865SDOperand SelectionDAGLegalize:: 4866ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 4867 assert(getTypeAction(Source.getValueType()) == Expand && 4868 "This is not an expansion!"); 4869 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 4870 4871 if (!isSigned) { 4872 assert(Source.getValueType() == MVT::i64 && 4873 "This only works for 64-bit -> FP"); 4874 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 4875 // incoming integer is set. To handle this, we dynamically test to see if 4876 // it is set, and, if so, add a fudge factor. 4877 SDOperand Lo, Hi; 4878 ExpandOp(Source, Lo, Hi); 4879 4880 // If this is unsigned, and not supported, first perform the conversion to 4881 // signed, then adjust the result if the sign bit is set. 4882 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 4883 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 4884 4885 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 4886 DAG.getConstant(0, Hi.getValueType()), 4887 ISD::SETLT); 4888 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4889 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4890 SignSet, Four, Zero); 4891 uint64_t FF = 0x5f800000ULL; 4892 if (TLI.isLittleEndian()) FF <<= 32; 4893 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4894 4895 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4896 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4897 SDOperand FudgeInReg; 4898 if (DestTy == MVT::f32) 4899 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4900 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) 4901 // FIXME: Avoid the extend by construction the right constantpool? 4902 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 4903 CPIdx, NULL, 0, MVT::f32); 4904 else 4905 assert(0 && "Unexpected conversion"); 4906 4907 MVT::ValueType SCVT = SignedConv.getValueType(); 4908 if (SCVT != DestTy) { 4909 // Destination type needs to be expanded as well. The FADD now we are 4910 // constructing will be expanded into a libcall. 4911 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { 4912 assert(SCVT == MVT::i32 && DestTy == MVT::f64); 4913 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, 4914 SignedConv, SignedConv.getValue(1)); 4915 } 4916 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 4917 } 4918 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 4919 } 4920 4921 // Check to see if the target has a custom way to lower this. If so, use it. 4922 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 4923 default: assert(0 && "This action not implemented for this operation!"); 4924 case TargetLowering::Legal: 4925 case TargetLowering::Expand: 4926 break; // This case is handled below. 4927 case TargetLowering::Custom: { 4928 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 4929 Source), DAG); 4930 if (NV.Val) 4931 return LegalizeOp(NV); 4932 break; // The target decided this was legal after all 4933 } 4934 } 4935 4936 // Expand the source, then glue it back together for the call. We must expand 4937 // the source in case it is shared (this pass of legalize must traverse it). 4938 SDOperand SrcLo, SrcHi; 4939 ExpandOp(Source, SrcLo, SrcHi); 4940 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 4941 4942 RTLIB::Libcall LC; 4943 if (DestTy == MVT::f32) 4944 LC = RTLIB::SINTTOFP_I64_F32; 4945 else { 4946 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 4947 LC = RTLIB::SINTTOFP_I64_F64; 4948 } 4949 4950 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 4951 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 4952 SDOperand UnusedHiPart; 4953 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 4954 UnusedHiPart); 4955} 4956 4957/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 4958/// INT_TO_FP operation of the specified operand when the target requests that 4959/// we expand it. At this point, we know that the result and operand types are 4960/// legal for the target. 4961SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 4962 SDOperand Op0, 4963 MVT::ValueType DestVT) { 4964 if (Op0.getValueType() == MVT::i32) { 4965 // simple 32-bit [signed|unsigned] integer to float/double expansion 4966 4967 // get the stack frame index of a 8 byte buffer, pessimistically aligned 4968 MachineFunction &MF = DAG.getMachineFunction(); 4969 const Type *F64Type = MVT::getTypeForValueType(MVT::f64); 4970 unsigned StackAlign = 4971 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type); 4972 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign); 4973 // get address of 8 byte buffer 4974 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4975 // word offset constant for Hi/Lo address computation 4976 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 4977 // set up Hi and Lo (into buffer) address based on endian 4978 SDOperand Hi = StackSlot; 4979 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 4980 if (TLI.isLittleEndian()) 4981 std::swap(Hi, Lo); 4982 4983 // if signed map to unsigned space 4984 SDOperand Op0Mapped; 4985 if (isSigned) { 4986 // constant used to invert sign bit (signed to unsigned mapping) 4987 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 4988 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 4989 } else { 4990 Op0Mapped = Op0; 4991 } 4992 // store the lo of the constructed double - based on integer input 4993 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 4994 Op0Mapped, Lo, NULL, 0); 4995 // initial hi portion of constructed double 4996 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 4997 // store the hi of the constructed double - biased exponent 4998 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 4999 // load the constructed double 5000 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5001 // FP constant to bias correct the final result 5002 SDOperand Bias = DAG.getConstantFP(isSigned ? 5003 BitsToDouble(0x4330000080000000ULL) 5004 : BitsToDouble(0x4330000000000000ULL), 5005 MVT::f64); 5006 // subtract the bias 5007 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5008 // final result 5009 SDOperand Result; 5010 // handle final rounding 5011 if (DestVT == MVT::f64) { 5012 // do nothing 5013 Result = Sub; 5014 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) { 5015 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub); 5016 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) { 5017 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5018 } 5019 return Result; 5020 } 5021 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5022 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5023 5024 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 5025 DAG.getConstant(0, Op0.getValueType()), 5026 ISD::SETLT); 5027 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 5028 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5029 SignSet, Four, Zero); 5030 5031 // If the sign bit of the integer is set, the large number will be treated 5032 // as a negative number. To counteract this, the dynamic code adds an 5033 // offset depending on the data type. 5034 uint64_t FF; 5035 switch (Op0.getValueType()) { 5036 default: assert(0 && "Unsupported integer type!"); 5037 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5038 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5039 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5040 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5041 } 5042 if (TLI.isLittleEndian()) FF <<= 32; 5043 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5044 5045 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5046 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5047 SDOperand FudgeInReg; 5048 if (DestVT == MVT::f32) 5049 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 5050 else { 5051 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5052 DAG.getEntryNode(), CPIdx, 5053 NULL, 0, MVT::f32)); 5054 } 5055 5056 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5057} 5058 5059/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5060/// *INT_TO_FP operation of the specified operand when the target requests that 5061/// we promote it. At this point, we know that the result and operand types are 5062/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5063/// operation that takes a larger input. 5064SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 5065 MVT::ValueType DestVT, 5066 bool isSigned) { 5067 // First step, figure out the appropriate *INT_TO_FP operation to use. 5068 MVT::ValueType NewInTy = LegalOp.getValueType(); 5069 5070 unsigned OpToUse = 0; 5071 5072 // Scan for the appropriate larger type to use. 5073 while (1) { 5074 NewInTy = (MVT::ValueType)(NewInTy+1); 5075 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 5076 5077 // If the target supports SINT_TO_FP of this type, use it. 5078 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5079 default: break; 5080 case TargetLowering::Legal: 5081 if (!TLI.isTypeLegal(NewInTy)) 5082 break; // Can't use this datatype. 5083 // FALL THROUGH. 5084 case TargetLowering::Custom: 5085 OpToUse = ISD::SINT_TO_FP; 5086 break; 5087 } 5088 if (OpToUse) break; 5089 if (isSigned) continue; 5090 5091 // If the target supports UINT_TO_FP of this type, use it. 5092 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5093 default: break; 5094 case TargetLowering::Legal: 5095 if (!TLI.isTypeLegal(NewInTy)) 5096 break; // Can't use this datatype. 5097 // FALL THROUGH. 5098 case TargetLowering::Custom: 5099 OpToUse = ISD::UINT_TO_FP; 5100 break; 5101 } 5102 if (OpToUse) break; 5103 5104 // Otherwise, try a larger type. 5105 } 5106 5107 // Okay, we found the operation and type to use. Zero extend our input to the 5108 // desired type then run the operation on it. 5109 return DAG.getNode(OpToUse, DestVT, 5110 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5111 NewInTy, LegalOp)); 5112} 5113 5114/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5115/// FP_TO_*INT operation of the specified operand when the target requests that 5116/// we promote it. At this point, we know that the result and operand types are 5117/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5118/// operation that returns a larger result. 5119SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 5120 MVT::ValueType DestVT, 5121 bool isSigned) { 5122 // First step, figure out the appropriate FP_TO*INT operation to use. 5123 MVT::ValueType NewOutTy = DestVT; 5124 5125 unsigned OpToUse = 0; 5126 5127 // Scan for the appropriate larger type to use. 5128 while (1) { 5129 NewOutTy = (MVT::ValueType)(NewOutTy+1); 5130 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 5131 5132 // If the target supports FP_TO_SINT returning this type, use it. 5133 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5134 default: break; 5135 case TargetLowering::Legal: 5136 if (!TLI.isTypeLegal(NewOutTy)) 5137 break; // Can't use this datatype. 5138 // FALL THROUGH. 5139 case TargetLowering::Custom: 5140 OpToUse = ISD::FP_TO_SINT; 5141 break; 5142 } 5143 if (OpToUse) break; 5144 5145 // If the target supports FP_TO_UINT of this type, use it. 5146 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5147 default: break; 5148 case TargetLowering::Legal: 5149 if (!TLI.isTypeLegal(NewOutTy)) 5150 break; // Can't use this datatype. 5151 // FALL THROUGH. 5152 case TargetLowering::Custom: 5153 OpToUse = ISD::FP_TO_UINT; 5154 break; 5155 } 5156 if (OpToUse) break; 5157 5158 // Otherwise, try a larger type. 5159 } 5160 5161 // Okay, we found the operation and type to use. Truncate the result of the 5162 // extended FP_TO_*INT operation to the desired size. 5163 return DAG.getNode(ISD::TRUNCATE, DestVT, 5164 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 5165} 5166 5167/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5168/// 5169SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 5170 MVT::ValueType VT = Op.getValueType(); 5171 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 5172 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5173 switch (VT) { 5174 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5175 case MVT::i16: 5176 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5177 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5178 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5179 case MVT::i32: 5180 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5181 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5182 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5183 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5184 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5185 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5186 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5187 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5188 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5189 case MVT::i64: 5190 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5191 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5192 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5193 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5194 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5195 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5196 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5197 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5198 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5199 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5200 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5201 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5202 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5203 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5204 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5205 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5206 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5207 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5208 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5209 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5210 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5211 } 5212} 5213 5214/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5215/// 5216SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 5217 switch (Opc) { 5218 default: assert(0 && "Cannot expand this yet!"); 5219 case ISD::CTPOP: { 5220 static const uint64_t mask[6] = { 5221 0x5555555555555555ULL, 0x3333333333333333ULL, 5222 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5223 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5224 }; 5225 MVT::ValueType VT = Op.getValueType(); 5226 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5227 unsigned len = MVT::getSizeInBits(VT); 5228 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5229 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5230 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 5231 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5232 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5233 DAG.getNode(ISD::AND, VT, 5234 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5235 } 5236 return Op; 5237 } 5238 case ISD::CTLZ: { 5239 // for now, we do this: 5240 // x = x | (x >> 1); 5241 // x = x | (x >> 2); 5242 // ... 5243 // x = x | (x >>16); 5244 // x = x | (x >>32); // for 64-bit input 5245 // return popcount(~x); 5246 // 5247 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5248 MVT::ValueType VT = Op.getValueType(); 5249 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5250 unsigned len = MVT::getSizeInBits(VT); 5251 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5252 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5253 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5254 } 5255 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5256 return DAG.getNode(ISD::CTPOP, VT, Op); 5257 } 5258 case ISD::CTTZ: { 5259 // for now, we use: { return popcount(~x & (x - 1)); } 5260 // unless the target has ctlz but not ctpop, in which case we use: 5261 // { return 32 - nlz(~x & (x-1)); } 5262 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5263 MVT::ValueType VT = Op.getValueType(); 5264 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 5265 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 5266 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5267 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5268 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5269 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5270 TLI.isOperationLegal(ISD::CTLZ, VT)) 5271 return DAG.getNode(ISD::SUB, VT, 5272 DAG.getConstant(MVT::getSizeInBits(VT), VT), 5273 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5274 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5275 } 5276 } 5277} 5278 5279/// ExpandOp - Expand the specified SDOperand into its two component pieces 5280/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5281/// LegalizeNodes map is filled in for any results that are not expanded, the 5282/// ExpandedNodes map is filled in for any results that are expanded, and the 5283/// Lo/Hi values are returned. 5284void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 5285 MVT::ValueType VT = Op.getValueType(); 5286 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 5287 SDNode *Node = Op.Val; 5288 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5289 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 5290 MVT::isVector(VT)) && 5291 "Cannot expand to FP value or to larger int value!"); 5292 5293 // See if we already expanded it. 5294 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5295 = ExpandedNodes.find(Op); 5296 if (I != ExpandedNodes.end()) { 5297 Lo = I->second.first; 5298 Hi = I->second.second; 5299 return; 5300 } 5301 5302 switch (Node->getOpcode()) { 5303 case ISD::CopyFromReg: 5304 assert(0 && "CopyFromReg must be legal!"); 5305 case ISD::FP_ROUND_INREG: 5306 if (VT == MVT::ppcf128 && 5307 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5308 TargetLowering::Custom) { 5309 SDOperand SrcLo, SrcHi, Src; 5310 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5311 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5312 SDOperand Result = TLI.LowerOperation( 5313 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5314 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5315 Lo = Result.Val->getOperand(0); 5316 Hi = Result.Val->getOperand(1); 5317 break; 5318 } 5319 // fall through 5320 default: 5321#ifndef NDEBUG 5322 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5323#endif 5324 assert(0 && "Do not know how to expand this operator!"); 5325 abort(); 5326 case ISD::EXTRACT_VECTOR_ELT: 5327 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5328 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5329 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5330 return ExpandOp(Lo, Lo, Hi); 5331 case ISD::UNDEF: 5332 NVT = TLI.getTypeToExpandTo(VT); 5333 Lo = DAG.getNode(ISD::UNDEF, NVT); 5334 Hi = DAG.getNode(ISD::UNDEF, NVT); 5335 break; 5336 case ISD::Constant: { 5337 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 5338 Lo = DAG.getConstant(Cst, NVT); 5339 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 5340 break; 5341 } 5342 case ISD::ConstantFP: { 5343 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5344 if (CFP->getValueType(0) == MVT::ppcf128) { 5345 APInt api = CFP->getValueAPF().convertToAPInt(); 5346 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5347 MVT::f64); 5348 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5349 MVT::f64); 5350 break; 5351 } 5352 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5353 if (getTypeAction(Lo.getValueType()) == Expand) 5354 ExpandOp(Lo, Lo, Hi); 5355 break; 5356 } 5357 case ISD::BUILD_PAIR: 5358 // Return the operands. 5359 Lo = Node->getOperand(0); 5360 Hi = Node->getOperand(1); 5361 break; 5362 5363 case ISD::SIGN_EXTEND_INREG: 5364 ExpandOp(Node->getOperand(0), Lo, Hi); 5365 // sext_inreg the low part if needed. 5366 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5367 5368 // The high part gets the sign extension from the lo-part. This handles 5369 // things like sextinreg V:i64 from i8. 5370 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5371 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 5372 TLI.getShiftAmountTy())); 5373 break; 5374 5375 case ISD::BSWAP: { 5376 ExpandOp(Node->getOperand(0), Lo, Hi); 5377 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5378 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5379 Lo = TempLo; 5380 break; 5381 } 5382 5383 case ISD::CTPOP: 5384 ExpandOp(Node->getOperand(0), Lo, Hi); 5385 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5386 DAG.getNode(ISD::CTPOP, NVT, Lo), 5387 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5388 Hi = DAG.getConstant(0, NVT); 5389 break; 5390 5391 case ISD::CTLZ: { 5392 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5393 ExpandOp(Node->getOperand(0), Lo, Hi); 5394 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5395 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5396 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 5397 ISD::SETNE); 5398 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5399 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5400 5401 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5402 Hi = DAG.getConstant(0, NVT); 5403 break; 5404 } 5405 5406 case ISD::CTTZ: { 5407 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5408 ExpandOp(Node->getOperand(0), Lo, Hi); 5409 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5410 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5411 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 5412 ISD::SETNE); 5413 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5414 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5415 5416 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5417 Hi = DAG.getConstant(0, NVT); 5418 break; 5419 } 5420 5421 case ISD::VAARG: { 5422 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5423 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5424 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5425 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5426 5427 // Remember that we legalized the chain. 5428 Hi = LegalizeOp(Hi); 5429 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5430 if (!TLI.isLittleEndian()) 5431 std::swap(Lo, Hi); 5432 break; 5433 } 5434 5435 case ISD::LOAD: { 5436 LoadSDNode *LD = cast<LoadSDNode>(Node); 5437 SDOperand Ch = LD->getChain(); // Legalize the chain. 5438 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5439 ISD::LoadExtType ExtType = LD->getExtensionType(); 5440 int SVOffset = LD->getSrcValueOffset(); 5441 unsigned Alignment = LD->getAlignment(); 5442 bool isVolatile = LD->isVolatile(); 5443 5444 if (ExtType == ISD::NON_EXTLOAD) { 5445 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5446 isVolatile, Alignment); 5447 if (VT == MVT::f32 || VT == MVT::f64) { 5448 // f32->i32 or f64->i64 one to one expansion. 5449 // Remember that we legalized the chain. 5450 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5451 // Recursively expand the new load. 5452 if (getTypeAction(NVT) == Expand) 5453 ExpandOp(Lo, Lo, Hi); 5454 break; 5455 } 5456 5457 // Increment the pointer to the other half. 5458 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 5459 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5460 getIntPtrConstant(IncrementSize)); 5461 SVOffset += IncrementSize; 5462 Alignment = MinAlign(Alignment, IncrementSize); 5463 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5464 isVolatile, Alignment); 5465 5466 // Build a factor node to remember that this load is independent of the 5467 // other one. 5468 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5469 Hi.getValue(1)); 5470 5471 // Remember that we legalized the chain. 5472 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5473 if (!TLI.isLittleEndian()) 5474 std::swap(Lo, Hi); 5475 } else { 5476 MVT::ValueType EVT = LD->getLoadedVT(); 5477 5478 if ((VT == MVT::f64 && EVT == MVT::f32) || 5479 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 5480 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5481 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5482 SVOffset, isVolatile, Alignment); 5483 // Remember that we legalized the chain. 5484 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 5485 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 5486 break; 5487 } 5488 5489 if (EVT == NVT) 5490 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 5491 SVOffset, isVolatile, Alignment); 5492 else 5493 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 5494 SVOffset, EVT, isVolatile, 5495 Alignment); 5496 5497 // Remember that we legalized the chain. 5498 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5499 5500 if (ExtType == ISD::SEXTLOAD) { 5501 // The high part is obtained by SRA'ing all but one of the bits of the 5502 // lo part. 5503 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5504 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5505 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5506 } else if (ExtType == ISD::ZEXTLOAD) { 5507 // The high part is just a zero. 5508 Hi = DAG.getConstant(0, NVT); 5509 } else /* if (ExtType == ISD::EXTLOAD) */ { 5510 // The high part is undefined. 5511 Hi = DAG.getNode(ISD::UNDEF, NVT); 5512 } 5513 } 5514 break; 5515 } 5516 case ISD::AND: 5517 case ISD::OR: 5518 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 5519 SDOperand LL, LH, RL, RH; 5520 ExpandOp(Node->getOperand(0), LL, LH); 5521 ExpandOp(Node->getOperand(1), RL, RH); 5522 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 5523 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 5524 break; 5525 } 5526 case ISD::SELECT: { 5527 SDOperand LL, LH, RL, RH; 5528 ExpandOp(Node->getOperand(1), LL, LH); 5529 ExpandOp(Node->getOperand(2), RL, RH); 5530 if (getTypeAction(NVT) == Expand) 5531 NVT = TLI.getTypeToExpandTo(NVT); 5532 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 5533 if (VT != MVT::f32) 5534 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 5535 break; 5536 } 5537 case ISD::SELECT_CC: { 5538 SDOperand TL, TH, FL, FH; 5539 ExpandOp(Node->getOperand(2), TL, TH); 5540 ExpandOp(Node->getOperand(3), FL, FH); 5541 if (getTypeAction(NVT) == Expand) 5542 NVT = TLI.getTypeToExpandTo(NVT); 5543 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5544 Node->getOperand(1), TL, FL, Node->getOperand(4)); 5545 if (VT != MVT::f32) 5546 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5547 Node->getOperand(1), TH, FH, Node->getOperand(4)); 5548 break; 5549 } 5550 case ISD::ANY_EXTEND: 5551 // The low part is any extension of the input (which degenerates to a copy). 5552 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 5553 // The high part is undefined. 5554 Hi = DAG.getNode(ISD::UNDEF, NVT); 5555 break; 5556 case ISD::SIGN_EXTEND: { 5557 // The low part is just a sign extension of the input (which degenerates to 5558 // a copy). 5559 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 5560 5561 // The high part is obtained by SRA'ing all but one of the bits of the lo 5562 // part. 5563 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5564 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5565 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5566 break; 5567 } 5568 case ISD::ZERO_EXTEND: 5569 // The low part is just a zero extension of the input (which degenerates to 5570 // a copy). 5571 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 5572 5573 // The high part is just a zero. 5574 Hi = DAG.getConstant(0, NVT); 5575 break; 5576 5577 case ISD::TRUNCATE: { 5578 // The input value must be larger than this value. Expand *it*. 5579 SDOperand NewLo; 5580 ExpandOp(Node->getOperand(0), NewLo, Hi); 5581 5582 // The low part is now either the right size, or it is closer. If not the 5583 // right size, make an illegal truncate so we recursively expand it. 5584 if (NewLo.getValueType() != Node->getValueType(0)) 5585 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 5586 ExpandOp(NewLo, Lo, Hi); 5587 break; 5588 } 5589 5590 case ISD::BIT_CONVERT: { 5591 SDOperand Tmp; 5592 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 5593 // If the target wants to, allow it to lower this itself. 5594 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5595 case Expand: assert(0 && "cannot expand FP!"); 5596 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 5597 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 5598 } 5599 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 5600 } 5601 5602 // f32 / f64 must be expanded to i32 / i64. 5603 if (VT == MVT::f32 || VT == MVT::f64) { 5604 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5605 if (getTypeAction(NVT) == Expand) 5606 ExpandOp(Lo, Lo, Hi); 5607 break; 5608 } 5609 5610 // If source operand will be expanded to the same type as VT, i.e. 5611 // i64 <- f64, i32 <- f32, expand the source operand instead. 5612 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 5613 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 5614 ExpandOp(Node->getOperand(0), Lo, Hi); 5615 break; 5616 } 5617 5618 // Turn this into a load/store pair by default. 5619 if (Tmp.Val == 0) 5620 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0)); 5621 5622 ExpandOp(Tmp, Lo, Hi); 5623 break; 5624 } 5625 5626 case ISD::READCYCLECOUNTER: 5627 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 5628 TargetLowering::Custom && 5629 "Must custom expand ReadCycleCounter"); 5630 Lo = TLI.LowerOperation(Op, DAG); 5631 assert(Lo.Val && "Node must be custom expanded!"); 5632 Hi = Lo.getValue(1); 5633 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 5634 LegalizeOp(Lo.getValue(2))); 5635 break; 5636 5637 // These operators cannot be expanded directly, emit them as calls to 5638 // library functions. 5639 case ISD::FP_TO_SINT: { 5640 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 5641 SDOperand Op; 5642 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5643 case Expand: assert(0 && "cannot expand FP!"); 5644 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5645 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5646 } 5647 5648 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 5649 5650 // Now that the custom expander is done, expand the result, which is still 5651 // VT. 5652 if (Op.Val) { 5653 ExpandOp(Op, Lo, Hi); 5654 break; 5655 } 5656 } 5657 5658 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5659 if (Node->getOperand(0).getValueType() == MVT::f32) 5660 LC = RTLIB::FPTOSINT_F32_I64; 5661 else if (Node->getOperand(0).getValueType() == MVT::f64) 5662 LC = RTLIB::FPTOSINT_F64_I64; 5663 else if (Node->getOperand(0).getValueType() == MVT::f80) 5664 LC = RTLIB::FPTOSINT_F80_I64; 5665 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 5666 LC = RTLIB::FPTOSINT_PPCF128_I64; 5667 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5668 false/*sign irrelevant*/, Hi); 5669 break; 5670 } 5671 5672 case ISD::FP_TO_UINT: { 5673 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 5674 SDOperand Op; 5675 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5676 case Expand: assert(0 && "cannot expand FP!"); 5677 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5678 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5679 } 5680 5681 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 5682 5683 // Now that the custom expander is done, expand the result. 5684 if (Op.Val) { 5685 ExpandOp(Op, Lo, Hi); 5686 break; 5687 } 5688 } 5689 5690 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5691 if (Node->getOperand(0).getValueType() == MVT::f32) 5692 LC = RTLIB::FPTOUINT_F32_I64; 5693 else if (Node->getOperand(0).getValueType() == MVT::f64) 5694 LC = RTLIB::FPTOUINT_F64_I64; 5695 else if (Node->getOperand(0).getValueType() == MVT::f80) 5696 LC = RTLIB::FPTOUINT_F80_I64; 5697 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 5698 LC = RTLIB::FPTOUINT_PPCF128_I64; 5699 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5700 false/*sign irrelevant*/, Hi); 5701 break; 5702 } 5703 5704 case ISD::SHL: { 5705 // If the target wants custom lowering, do so. 5706 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5707 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 5708 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 5709 Op = TLI.LowerOperation(Op, DAG); 5710 if (Op.Val) { 5711 // Now that the custom expander is done, expand the result, which is 5712 // still VT. 5713 ExpandOp(Op, Lo, Hi); 5714 break; 5715 } 5716 } 5717 5718 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 5719 // this X << 1 as X+X. 5720 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 5721 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 5722 TLI.isOperationLegal(ISD::ADDE, NVT)) { 5723 SDOperand LoOps[2], HiOps[3]; 5724 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 5725 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 5726 LoOps[1] = LoOps[0]; 5727 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5728 5729 HiOps[1] = HiOps[0]; 5730 HiOps[2] = Lo.getValue(1); 5731 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5732 break; 5733 } 5734 } 5735 5736 // If we can emit an efficient shift operation, do so now. 5737 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5738 break; 5739 5740 // If this target supports SHL_PARTS, use it. 5741 TargetLowering::LegalizeAction Action = 5742 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 5743 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5744 Action == TargetLowering::Custom) { 5745 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5746 break; 5747 } 5748 5749 // Otherwise, emit a libcall. 5750 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 5751 false/*left shift=unsigned*/, Hi); 5752 break; 5753 } 5754 5755 case ISD::SRA: { 5756 // If the target wants custom lowering, do so. 5757 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5758 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 5759 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 5760 Op = TLI.LowerOperation(Op, DAG); 5761 if (Op.Val) { 5762 // Now that the custom expander is done, expand the result, which is 5763 // still VT. 5764 ExpandOp(Op, Lo, Hi); 5765 break; 5766 } 5767 } 5768 5769 // If we can emit an efficient shift operation, do so now. 5770 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5771 break; 5772 5773 // If this target supports SRA_PARTS, use it. 5774 TargetLowering::LegalizeAction Action = 5775 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 5776 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5777 Action == TargetLowering::Custom) { 5778 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5779 break; 5780 } 5781 5782 // Otherwise, emit a libcall. 5783 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 5784 true/*ashr is signed*/, Hi); 5785 break; 5786 } 5787 5788 case ISD::SRL: { 5789 // If the target wants custom lowering, do so. 5790 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5791 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 5792 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 5793 Op = TLI.LowerOperation(Op, DAG); 5794 if (Op.Val) { 5795 // Now that the custom expander is done, expand the result, which is 5796 // still VT. 5797 ExpandOp(Op, Lo, Hi); 5798 break; 5799 } 5800 } 5801 5802 // If we can emit an efficient shift operation, do so now. 5803 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5804 break; 5805 5806 // If this target supports SRL_PARTS, use it. 5807 TargetLowering::LegalizeAction Action = 5808 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 5809 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5810 Action == TargetLowering::Custom) { 5811 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5812 break; 5813 } 5814 5815 // Otherwise, emit a libcall. 5816 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 5817 false/*lshr is unsigned*/, Hi); 5818 break; 5819 } 5820 5821 case ISD::ADD: 5822 case ISD::SUB: { 5823 // If the target wants to custom expand this, let them. 5824 if (TLI.getOperationAction(Node->getOpcode(), VT) == 5825 TargetLowering::Custom) { 5826 Op = TLI.LowerOperation(Op, DAG); 5827 if (Op.Val) { 5828 ExpandOp(Op, Lo, Hi); 5829 break; 5830 } 5831 } 5832 5833 // Expand the subcomponents. 5834 SDOperand LHSL, LHSH, RHSL, RHSH; 5835 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5836 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5837 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5838 SDOperand LoOps[2], HiOps[3]; 5839 LoOps[0] = LHSL; 5840 LoOps[1] = RHSL; 5841 HiOps[0] = LHSH; 5842 HiOps[1] = RHSH; 5843 if (Node->getOpcode() == ISD::ADD) { 5844 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5845 HiOps[2] = Lo.getValue(1); 5846 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5847 } else { 5848 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5849 HiOps[2] = Lo.getValue(1); 5850 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5851 } 5852 break; 5853 } 5854 5855 case ISD::ADDC: 5856 case ISD::SUBC: { 5857 // Expand the subcomponents. 5858 SDOperand LHSL, LHSH, RHSL, RHSH; 5859 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5860 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5861 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5862 SDOperand LoOps[2] = { LHSL, RHSL }; 5863 SDOperand HiOps[3] = { LHSH, RHSH }; 5864 5865 if (Node->getOpcode() == ISD::ADDC) { 5866 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5867 HiOps[2] = Lo.getValue(1); 5868 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5869 } else { 5870 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5871 HiOps[2] = Lo.getValue(1); 5872 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5873 } 5874 // Remember that we legalized the flag. 5875 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5876 break; 5877 } 5878 case ISD::ADDE: 5879 case ISD::SUBE: { 5880 // Expand the subcomponents. 5881 SDOperand LHSL, LHSH, RHSL, RHSH; 5882 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5883 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5884 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5885 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 5886 SDOperand HiOps[3] = { LHSH, RHSH }; 5887 5888 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 5889 HiOps[2] = Lo.getValue(1); 5890 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 5891 5892 // Remember that we legalized the flag. 5893 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5894 break; 5895 } 5896 case ISD::MUL: { 5897 // If the target wants to custom expand this, let them. 5898 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 5899 SDOperand New = TLI.LowerOperation(Op, DAG); 5900 if (New.Val) { 5901 ExpandOp(New, Lo, Hi); 5902 break; 5903 } 5904 } 5905 5906 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 5907 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 5908 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 5909 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 5910 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 5911 SDOperand LL, LH, RL, RH; 5912 ExpandOp(Node->getOperand(0), LL, LH); 5913 ExpandOp(Node->getOperand(1), RL, RH); 5914 unsigned BitSize = MVT::getSizeInBits(RH.getValueType()); 5915 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 5916 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 5917 // FIXME: generalize this to handle other bit sizes 5918 if (LHSSB == 32 && RHSSB == 32 && 5919 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) && 5920 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) { 5921 // The inputs are both zero-extended. 5922 if (HasUMUL_LOHI) { 5923 // We can emit a umul_lohi. 5924 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 5925 Hi = SDOperand(Lo.Val, 1); 5926 break; 5927 } 5928 if (HasMULHU) { 5929 // We can emit a mulhu+mul. 5930 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5931 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 5932 break; 5933 } 5934 } 5935 if (LHSSB > BitSize && RHSSB > BitSize) { 5936 // The input values are both sign-extended. 5937 if (HasSMUL_LOHI) { 5938 // We can emit a smul_lohi. 5939 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 5940 Hi = SDOperand(Lo.Val, 1); 5941 break; 5942 } 5943 if (HasMULHS) { 5944 // We can emit a mulhs+mul. 5945 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5946 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 5947 break; 5948 } 5949 } 5950 if (HasUMUL_LOHI) { 5951 // Lo,Hi = umul LHS, RHS. 5952 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 5953 DAG.getVTList(NVT, NVT), LL, RL); 5954 Lo = UMulLOHI; 5955 Hi = UMulLOHI.getValue(1); 5956 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 5957 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 5958 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 5959 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 5960 break; 5961 } 5962 if (HasMULHU) { 5963 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5964 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 5965 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 5966 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 5967 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 5968 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 5969 break; 5970 } 5971 } 5972 5973 // If nothing else, we can make a libcall. 5974 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 5975 false/*sign irrelevant*/, Hi); 5976 break; 5977 } 5978 case ISD::SDIV: 5979 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 5980 break; 5981 case ISD::UDIV: 5982 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 5983 break; 5984 case ISD::SREM: 5985 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 5986 break; 5987 case ISD::UREM: 5988 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 5989 break; 5990 5991 case ISD::FADD: 5992 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::ADD_F32 : 5993 VT == MVT::f64 ? RTLIB::ADD_F64 : 5994 VT == MVT::ppcf128 ? 5995 RTLIB::ADD_PPCF128 : 5996 RTLIB::UNKNOWN_LIBCALL), 5997 Node, false, Hi); 5998 break; 5999 case ISD::FSUB: 6000 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::SUB_F32 : 6001 VT == MVT::f64 ? RTLIB::SUB_F64 : 6002 VT == MVT::ppcf128 ? 6003 RTLIB::SUB_PPCF128 : 6004 RTLIB::UNKNOWN_LIBCALL), 6005 Node, false, Hi); 6006 break; 6007 case ISD::FMUL: 6008 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::MUL_F32 : 6009 VT == MVT::f64 ? RTLIB::MUL_F64 : 6010 VT == MVT::ppcf128 ? 6011 RTLIB::MUL_PPCF128 : 6012 RTLIB::UNKNOWN_LIBCALL), 6013 Node, false, Hi); 6014 break; 6015 case ISD::FDIV: 6016 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::DIV_F32 : 6017 VT == MVT::f64 ? RTLIB::DIV_F64 : 6018 VT == MVT::ppcf128 ? 6019 RTLIB::DIV_PPCF128 : 6020 RTLIB::UNKNOWN_LIBCALL), 6021 Node, false, Hi); 6022 break; 6023 case ISD::FP_EXTEND: 6024 if (VT == MVT::ppcf128) { 6025 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6026 Node->getOperand(0).getValueType()==MVT::f64); 6027 const uint64_t zero = 0; 6028 if (Node->getOperand(0).getValueType()==MVT::f32) 6029 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6030 else 6031 Hi = Node->getOperand(0); 6032 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6033 break; 6034 } 6035 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 6036 break; 6037 case ISD::FP_ROUND: 6038 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 6039 break; 6040 case ISD::FPOWI: 6041 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) ? RTLIB::POWI_F32 : 6042 (VT == MVT::f64) ? RTLIB::POWI_F64 : 6043 (VT == MVT::f80) ? RTLIB::POWI_F80 : 6044 (VT == MVT::ppcf128) ? 6045 RTLIB::POWI_PPCF128 : 6046 RTLIB::UNKNOWN_LIBCALL), 6047 Node, false, Hi); 6048 break; 6049 case ISD::FSQRT: 6050 case ISD::FSIN: 6051 case ISD::FCOS: { 6052 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6053 switch(Node->getOpcode()) { 6054 case ISD::FSQRT: 6055 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : 6056 (VT == MVT::f64) ? RTLIB::SQRT_F64 : 6057 (VT == MVT::f80) ? RTLIB::SQRT_F80 : 6058 (VT == MVT::ppcf128) ? RTLIB::SQRT_PPCF128 : 6059 RTLIB::UNKNOWN_LIBCALL; 6060 break; 6061 case ISD::FSIN: 6062 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 6063 break; 6064 case ISD::FCOS: 6065 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64; 6066 break; 6067 default: assert(0 && "Unreachable!"); 6068 } 6069 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 6070 break; 6071 } 6072 case ISD::FABS: { 6073 if (VT == MVT::ppcf128) { 6074 SDOperand Tmp; 6075 ExpandOp(Node->getOperand(0), Lo, Tmp); 6076 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6077 // lo = hi==fabs(hi) ? lo : -lo; 6078 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6079 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6080 DAG.getCondCode(ISD::SETEQ)); 6081 break; 6082 } 6083 SDOperand Mask = (VT == MVT::f64) 6084 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6085 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6086 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6087 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6088 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6089 if (getTypeAction(NVT) == Expand) 6090 ExpandOp(Lo, Lo, Hi); 6091 break; 6092 } 6093 case ISD::FNEG: { 6094 if (VT == MVT::ppcf128) { 6095 ExpandOp(Node->getOperand(0), Lo, Hi); 6096 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6097 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6098 break; 6099 } 6100 SDOperand Mask = (VT == MVT::f64) 6101 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6102 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6103 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6104 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6105 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6106 if (getTypeAction(NVT) == Expand) 6107 ExpandOp(Lo, Lo, Hi); 6108 break; 6109 } 6110 case ISD::FCOPYSIGN: { 6111 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6112 if (getTypeAction(NVT) == Expand) 6113 ExpandOp(Lo, Lo, Hi); 6114 break; 6115 } 6116 case ISD::SINT_TO_FP: 6117 case ISD::UINT_TO_FP: { 6118 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6119 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 6120 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) { 6121 static uint64_t zero = 0; 6122 if (isSigned) { 6123 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6124 Node->getOperand(0))); 6125 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6126 } else { 6127 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6128 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6129 Node->getOperand(0))); 6130 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6131 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6132 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6133 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6134 DAG.getConstant(0, MVT::i32), 6135 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6136 DAG.getConstantFP( 6137 APFloat(APInt(128, 2, TwoE32)), 6138 MVT::ppcf128)), 6139 Hi, 6140 DAG.getCondCode(ISD::SETLT)), 6141 Lo, Hi); 6142 } 6143 break; 6144 } 6145 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6146 // si64->ppcf128 done by libcall, below 6147 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6148 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6149 Lo, Hi); 6150 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6151 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6152 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6153 DAG.getConstant(0, MVT::i64), 6154 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6155 DAG.getConstantFP( 6156 APFloat(APInt(128, 2, TwoE64)), 6157 MVT::ppcf128)), 6158 Hi, 6159 DAG.getCondCode(ISD::SETLT)), 6160 Lo, Hi); 6161 break; 6162 } 6163 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6164 if (Node->getOperand(0).getValueType() == MVT::i64) { 6165 if (VT == MVT::f32) 6166 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; 6167 else if (VT == MVT::f64) 6168 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; 6169 else if (VT == MVT::f80) { 6170 assert(isSigned); 6171 LC = RTLIB::SINTTOFP_I64_F80; 6172 } 6173 else if (VT == MVT::ppcf128) { 6174 assert(isSigned); 6175 LC = RTLIB::SINTTOFP_I64_PPCF128; 6176 } 6177 } else { 6178 if (VT == MVT::f32) 6179 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 6180 else 6181 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 6182 } 6183 6184 // Promote the operand if needed. 6185 if (getTypeAction(SrcVT) == Promote) { 6186 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 6187 Tmp = isSigned 6188 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6189 DAG.getValueType(SrcVT)) 6190 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6191 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6192 } 6193 6194 const char *LibCall = TLI.getLibcallName(LC); 6195 if (LibCall) 6196 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi); 6197 else { 6198 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6199 Node->getOperand(0)); 6200 if (getTypeAction(Lo.getValueType()) == Expand) 6201 ExpandOp(Lo, Lo, Hi); 6202 } 6203 break; 6204 } 6205 } 6206 6207 // Make sure the resultant values have been legalized themselves, unless this 6208 // is a type that requires multi-step expansion. 6209 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6210 Lo = LegalizeOp(Lo); 6211 if (Hi.Val) 6212 // Don't legalize the high part if it is expanded to a single node. 6213 Hi = LegalizeOp(Hi); 6214 } 6215 6216 // Remember in a map if the values will be reused later. 6217 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 6218 assert(isNew && "Value already expanded?!?"); 6219} 6220 6221/// SplitVectorOp - Given an operand of vector type, break it down into 6222/// two smaller values, still of vector type. 6223void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 6224 SDOperand &Hi) { 6225 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); 6226 SDNode *Node = Op.Val; 6227 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType()); 6228 assert(NumElements > 1 && "Cannot split a single element vector!"); 6229 unsigned NewNumElts = NumElements/2; 6230 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType()); 6231 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts); 6232 6233 // See if we already split it. 6234 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 6235 = SplitNodes.find(Op); 6236 if (I != SplitNodes.end()) { 6237 Lo = I->second.first; 6238 Hi = I->second.second; 6239 return; 6240 } 6241 6242 switch (Node->getOpcode()) { 6243 default: 6244#ifndef NDEBUG 6245 Node->dump(&DAG); 6246#endif 6247 assert(0 && "Unhandled operation in SplitVectorOp!"); 6248 case ISD::BUILD_PAIR: 6249 Lo = Node->getOperand(0); 6250 Hi = Node->getOperand(1); 6251 break; 6252 case ISD::INSERT_VECTOR_ELT: { 6253 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6254 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 6255 SDOperand ScalarOp = Node->getOperand(1); 6256 if (Index < NewNumElts) 6257 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, Lo, ScalarOp, 6258 DAG.getConstant(Index, TLI.getPointerTy())); 6259 else 6260 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, Hi, ScalarOp, 6261 DAG.getConstant(Index - NewNumElts, TLI.getPointerTy())); 6262 break; 6263 } 6264 case ISD::BUILD_VECTOR: { 6265 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6266 Node->op_begin()+NewNumElts); 6267 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size()); 6268 6269 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts, 6270 Node->op_end()); 6271 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size()); 6272 break; 6273 } 6274 case ISD::CONCAT_VECTORS: { 6275 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6276 if (NewNumSubvectors == 1) { 6277 Lo = Node->getOperand(0); 6278 Hi = Node->getOperand(1); 6279 } else { 6280 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6281 Node->op_begin()+NewNumSubvectors); 6282 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size()); 6283 6284 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6285 Node->op_end()); 6286 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size()); 6287 } 6288 break; 6289 } 6290 case ISD::SELECT: { 6291 SDOperand Cond = Node->getOperand(0); 6292 6293 SDOperand LL, LH, RL, RH; 6294 SplitVectorOp(Node->getOperand(1), LL, LH); 6295 SplitVectorOp(Node->getOperand(2), RL, RH); 6296 6297 if (MVT::isVector(Cond.getValueType())) { 6298 // Handle a vector merge. 6299 SDOperand CL, CH; 6300 SplitVectorOp(Cond, CL, CH); 6301 Lo = DAG.getNode(Node->getOpcode(), NewVT, CL, LL, RL); 6302 Hi = DAG.getNode(Node->getOpcode(), NewVT, CH, LH, RH); 6303 } else { 6304 // Handle a simple select with vector operands. 6305 Lo = DAG.getNode(Node->getOpcode(), NewVT, Cond, LL, RL); 6306 Hi = DAG.getNode(Node->getOpcode(), NewVT, Cond, LH, RH); 6307 } 6308 break; 6309 } 6310 case ISD::ADD: 6311 case ISD::SUB: 6312 case ISD::MUL: 6313 case ISD::FADD: 6314 case ISD::FSUB: 6315 case ISD::FMUL: 6316 case ISD::SDIV: 6317 case ISD::UDIV: 6318 case ISD::FDIV: 6319 case ISD::FPOW: 6320 case ISD::AND: 6321 case ISD::OR: 6322 case ISD::XOR: { 6323 SDOperand LL, LH, RL, RH; 6324 SplitVectorOp(Node->getOperand(0), LL, LH); 6325 SplitVectorOp(Node->getOperand(1), RL, RH); 6326 6327 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL); 6328 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH); 6329 break; 6330 } 6331 case ISD::FPOWI: { 6332 SDOperand L, H; 6333 SplitVectorOp(Node->getOperand(0), L, H); 6334 6335 Lo = DAG.getNode(Node->getOpcode(), NewVT, L, Node->getOperand(1)); 6336 Hi = DAG.getNode(Node->getOpcode(), NewVT, H, Node->getOperand(1)); 6337 break; 6338 } 6339 case ISD::CTTZ: 6340 case ISD::CTLZ: 6341 case ISD::CTPOP: 6342 case ISD::FNEG: 6343 case ISD::FABS: 6344 case ISD::FSQRT: 6345 case ISD::FSIN: 6346 case ISD::FCOS: { 6347 SDOperand L, H; 6348 SplitVectorOp(Node->getOperand(0), L, H); 6349 6350 Lo = DAG.getNode(Node->getOpcode(), NewVT, L); 6351 Hi = DAG.getNode(Node->getOpcode(), NewVT, H); 6352 break; 6353 } 6354 case ISD::LOAD: { 6355 LoadSDNode *LD = cast<LoadSDNode>(Node); 6356 SDOperand Ch = LD->getChain(); 6357 SDOperand Ptr = LD->getBasePtr(); 6358 const Value *SV = LD->getSrcValue(); 6359 int SVOffset = LD->getSrcValueOffset(); 6360 unsigned Alignment = LD->getAlignment(); 6361 bool isVolatile = LD->isVolatile(); 6362 6363 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6364 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8; 6365 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6366 getIntPtrConstant(IncrementSize)); 6367 SVOffset += IncrementSize; 6368 Alignment = MinAlign(Alignment, IncrementSize); 6369 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6370 6371 // Build a factor node to remember that this load is independent of the 6372 // other one. 6373 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6374 Hi.getValue(1)); 6375 6376 // Remember that we legalized the chain. 6377 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6378 break; 6379 } 6380 case ISD::BIT_CONVERT: { 6381 // We know the result is a vector. The input may be either a vector or a 6382 // scalar value. 6383 SDOperand InOp = Node->getOperand(0); 6384 if (!MVT::isVector(InOp.getValueType()) || 6385 MVT::getVectorNumElements(InOp.getValueType()) == 1) { 6386 // The input is a scalar or single-element vector. 6387 // Lower to a store/load so that it can be split. 6388 // FIXME: this could be improved probably. 6389 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); 6390 6391 SDOperand St = DAG.getStore(DAG.getEntryNode(), 6392 InOp, Ptr, NULL, 0); 6393 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0); 6394 } 6395 // Split the vector and convert each of the pieces now. 6396 SplitVectorOp(InOp, Lo, Hi); 6397 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo); 6398 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi); 6399 break; 6400 } 6401 } 6402 6403 // Remember in a map if the values will be reused later. 6404 bool isNew = 6405 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 6406 assert(isNew && "Value already split?!?"); 6407} 6408 6409 6410/// ScalarizeVectorOp - Given an operand of single-element vector type 6411/// (e.g. v1f32), convert it into the equivalent operation that returns a 6412/// scalar (e.g. f32) value. 6413SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 6414 assert(MVT::isVector(Op.getValueType()) && 6415 "Bad ScalarizeVectorOp invocation!"); 6416 SDNode *Node = Op.Val; 6417 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); 6418 assert(MVT::getVectorNumElements(Op.getValueType()) == 1); 6419 6420 // See if we already scalarized it. 6421 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 6422 if (I != ScalarizedNodes.end()) return I->second; 6423 6424 SDOperand Result; 6425 switch (Node->getOpcode()) { 6426 default: 6427#ifndef NDEBUG 6428 Node->dump(&DAG); cerr << "\n"; 6429#endif 6430 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 6431 case ISD::ADD: 6432 case ISD::FADD: 6433 case ISD::SUB: 6434 case ISD::FSUB: 6435 case ISD::MUL: 6436 case ISD::FMUL: 6437 case ISD::SDIV: 6438 case ISD::UDIV: 6439 case ISD::FDIV: 6440 case ISD::SREM: 6441 case ISD::UREM: 6442 case ISD::FREM: 6443 case ISD::FPOW: 6444 case ISD::AND: 6445 case ISD::OR: 6446 case ISD::XOR: 6447 Result = DAG.getNode(Node->getOpcode(), 6448 NewVT, 6449 ScalarizeVectorOp(Node->getOperand(0)), 6450 ScalarizeVectorOp(Node->getOperand(1))); 6451 break; 6452 case ISD::FNEG: 6453 case ISD::FABS: 6454 case ISD::FSQRT: 6455 case ISD::FSIN: 6456 case ISD::FCOS: 6457 Result = DAG.getNode(Node->getOpcode(), 6458 NewVT, 6459 ScalarizeVectorOp(Node->getOperand(0))); 6460 break; 6461 case ISD::FPOWI: 6462 Result = DAG.getNode(Node->getOpcode(), 6463 NewVT, 6464 ScalarizeVectorOp(Node->getOperand(0)), 6465 Node->getOperand(1)); 6466 break; 6467 case ISD::LOAD: { 6468 LoadSDNode *LD = cast<LoadSDNode>(Node); 6469 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 6470 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 6471 6472 const Value *SV = LD->getSrcValue(); 6473 int SVOffset = LD->getSrcValueOffset(); 6474 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 6475 LD->isVolatile(), LD->getAlignment()); 6476 6477 // Remember that we legalized the chain. 6478 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 6479 break; 6480 } 6481 case ISD::BUILD_VECTOR: 6482 Result = Node->getOperand(0); 6483 break; 6484 case ISD::INSERT_VECTOR_ELT: 6485 // Returning the inserted scalar element. 6486 Result = Node->getOperand(1); 6487 break; 6488 case ISD::CONCAT_VECTORS: 6489 assert(Node->getOperand(0).getValueType() == NewVT && 6490 "Concat of non-legal vectors not yet supported!"); 6491 Result = Node->getOperand(0); 6492 break; 6493 case ISD::VECTOR_SHUFFLE: { 6494 // Figure out if the scalar is the LHS or RHS and return it. 6495 SDOperand EltNum = Node->getOperand(2).getOperand(0); 6496 if (cast<ConstantSDNode>(EltNum)->getValue()) 6497 Result = ScalarizeVectorOp(Node->getOperand(1)); 6498 else 6499 Result = ScalarizeVectorOp(Node->getOperand(0)); 6500 break; 6501 } 6502 case ISD::EXTRACT_SUBVECTOR: 6503 Result = Node->getOperand(0); 6504 assert(Result.getValueType() == NewVT); 6505 break; 6506 case ISD::BIT_CONVERT: 6507 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 6508 break; 6509 case ISD::SELECT: 6510 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 6511 ScalarizeVectorOp(Op.getOperand(1)), 6512 ScalarizeVectorOp(Op.getOperand(2))); 6513 break; 6514 } 6515 6516 if (TLI.isTypeLegal(NewVT)) 6517 Result = LegalizeOp(Result); 6518 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 6519 assert(isNew && "Value already scalarized?"); 6520 return Result; 6521} 6522 6523 6524// SelectionDAG::Legalize - This is the entry point for the file. 6525// 6526void SelectionDAG::Legalize() { 6527 if (ViewLegalizeDAGs) viewGraph(); 6528 6529 /// run - This is the main entry point to this class. 6530 /// 6531 SelectionDAGLegalize(*this).LegalizeDAG(); 6532} 6533 6534