LegalizeDAG.cpp revision 18dd6d0a2aeb3b827391f46996a7b40c9b1f907a
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Target/TargetLowering.h" 18#include "llvm/Target/TargetData.h" 19#include "llvm/Target/TargetOptions.h" 20#include "llvm/CallingConv.h" 21#include "llvm/Constants.h" 22#include "llvm/Support/MathExtras.h" 23#include "llvm/Support/CommandLine.h" 24#include <iostream> 25#include <map> 26using namespace llvm; 27 28#ifndef NDEBUG 29static cl::opt<bool> 30ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 31 cl::desc("Pop up a window to show dags before legalize")); 32#else 33static const bool ViewLegalizeDAGs = 0; 34#endif 35 36//===----------------------------------------------------------------------===// 37/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 38/// hacks on it until the target machine can handle it. This involves 39/// eliminating value sizes the machine cannot handle (promoting small sizes to 40/// large sizes or splitting up large values into small values) as well as 41/// eliminating operations the machine cannot handle. 42/// 43/// This code also does a small amount of optimization and recognition of idioms 44/// as part of its processing. For example, if a target does not support a 45/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 46/// will attempt merge setcc and brc instructions into brcc's. 47/// 48namespace { 49class SelectionDAGLegalize { 50 TargetLowering &TLI; 51 SelectionDAG &DAG; 52 53 // Libcall insertion helpers. 54 55 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 56 /// legalized. We use this to ensure that calls are properly serialized 57 /// against each other, including inserted libcalls. 58 SDOperand LastCALLSEQ_END; 59 60 /// IsLegalizingCall - This member is used *only* for purposes of providing 61 /// helpful assertions that a libcall isn't created while another call is 62 /// being legalized (which could lead to non-serialized call sequences). 63 bool IsLegalizingCall; 64 65 enum LegalizeAction { 66 Legal, // The target natively supports this operation. 67 Promote, // This operation should be executed in a larger type. 68 Expand, // Try to expand this to other ops, otherwise use a libcall. 69 }; 70 71 /// ValueTypeActions - This is a bitvector that contains two bits for each 72 /// value type, where the two bits correspond to the LegalizeAction enum. 73 /// This can be queried with "getTypeAction(VT)". 74 TargetLowering::ValueTypeActionImpl ValueTypeActions; 75 76 /// LegalizedNodes - For nodes that are of legal width, and that have more 77 /// than one use, this map indicates what regularized operand to use. This 78 /// allows us to avoid legalizing the same thing more than once. 79 std::map<SDOperand, SDOperand> LegalizedNodes; 80 81 /// PromotedNodes - For nodes that are below legal width, and that have more 82 /// than one use, this map indicates what promoted value to use. This allows 83 /// us to avoid promoting the same thing more than once. 84 std::map<SDOperand, SDOperand> PromotedNodes; 85 86 /// ExpandedNodes - For nodes that need to be expanded this map indicates 87 /// which which operands are the expanded version of the input. This allows 88 /// us to avoid expanding the same node more than once. 89 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 90 91 /// SplitNodes - For vector nodes that need to be split, this map indicates 92 /// which which operands are the split version of the input. This allows us 93 /// to avoid splitting the same node more than once. 94 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 95 96 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to 97 /// concrete packed types, this contains the mapping of ones we have already 98 /// processed to the result. 99 std::map<SDOperand, SDOperand> PackedNodes; 100 101 void AddLegalizedOperand(SDOperand From, SDOperand To) { 102 LegalizedNodes.insert(std::make_pair(From, To)); 103 // If someone requests legalization of the new node, return itself. 104 if (From != To) 105 LegalizedNodes.insert(std::make_pair(To, To)); 106 } 107 void AddPromotedOperand(SDOperand From, SDOperand To) { 108 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 109 assert(isNew && "Got into the map somehow?"); 110 // If someone requests legalization of the new node, return itself. 111 LegalizedNodes.insert(std::make_pair(To, To)); 112 } 113 114public: 115 116 SelectionDAGLegalize(SelectionDAG &DAG); 117 118 /// getTypeAction - Return how we should legalize values of this type, either 119 /// it is already legal or we need to expand it into multiple registers of 120 /// smaller integer type, or we need to promote it to a larger type. 121 LegalizeAction getTypeAction(MVT::ValueType VT) const { 122 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 123 } 124 125 /// isTypeLegal - Return true if this type is legal on this target. 126 /// 127 bool isTypeLegal(MVT::ValueType VT) const { 128 return getTypeAction(VT) == Legal; 129 } 130 131 void LegalizeDAG(); 132 133private: 134 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 135 /// appropriate for its type. 136 void HandleOp(SDOperand Op); 137 138 /// LegalizeOp - We know that the specified value has a legal type. 139 /// Recursively ensure that the operands have legal types, then return the 140 /// result. 141 SDOperand LegalizeOp(SDOperand O); 142 143 /// PromoteOp - Given an operation that produces a value in an invalid type, 144 /// promote it to compute the value into a larger type. The produced value 145 /// will have the correct bits for the low portion of the register, but no 146 /// guarantee is made about the top bits: it may be zero, sign-extended, or 147 /// garbage. 148 SDOperand PromoteOp(SDOperand O); 149 150 /// ExpandOp - Expand the specified SDOperand into its two component pieces 151 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 152 /// the LegalizeNodes map is filled in for any results that are not expanded, 153 /// the ExpandedNodes map is filled in for any results that are expanded, and 154 /// the Lo/Hi values are returned. This applies to integer types and Vector 155 /// types. 156 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 157 158 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 159 /// two smaller values of MVT::Vector type. 160 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 161 162 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 163 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When 164 /// this is called, we know that PackedVT is the right type for the result and 165 /// we know that this type is legal for the target. 166 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT); 167 168 /// isShuffleLegal - Return true if a vector shuffle is legal with the 169 /// specified mask and type. Targets can specify exactly which masks they 170 /// support and the code generator is tasked with not creating illegal masks. 171 /// 172 /// Note that this will also return true for shuffles that are promoted to a 173 /// different type. 174 /// 175 /// If this is a legal shuffle, this method returns the (possibly promoted) 176 /// build_vector Mask. If it's not a legal shuffle, it returns null. 177 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 178 179 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest); 180 181 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 182 183 SDOperand CreateStackTemporary(MVT::ValueType VT); 184 185 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 186 SDOperand &Hi); 187 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 188 SDOperand Source); 189 190 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 191 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 192 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 193 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 194 SDOperand LegalOp, 195 MVT::ValueType DestVT); 196 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 197 bool isSigned); 198 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 199 bool isSigned); 200 201 SDOperand ExpandBSWAP(SDOperand Op); 202 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 203 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 204 SDOperand &Lo, SDOperand &Hi); 205 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 206 SDOperand &Lo, SDOperand &Hi); 207 208 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op); 209 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 210 211 SDOperand getIntPtrConstant(uint64_t Val) { 212 return DAG.getConstant(Val, TLI.getPointerTy()); 213 } 214}; 215} 216 217/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 218/// specified mask and type. Targets can specify exactly which masks they 219/// support and the code generator is tasked with not creating illegal masks. 220/// 221/// Note that this will also return true for shuffles that are promoted to a 222/// different type. 223SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 224 SDOperand Mask) const { 225 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 226 default: return 0; 227 case TargetLowering::Legal: 228 case TargetLowering::Custom: 229 break; 230 case TargetLowering::Promote: { 231 // If this is promoted to a different type, convert the shuffle mask and 232 // ask if it is legal in the promoted type! 233 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 234 235 // If we changed # elements, change the shuffle mask. 236 unsigned NumEltsGrowth = 237 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 238 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 239 if (NumEltsGrowth > 1) { 240 // Renumber the elements. 241 std::vector<SDOperand> Ops; 242 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 243 SDOperand InOp = Mask.getOperand(i); 244 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 245 if (InOp.getOpcode() == ISD::UNDEF) 246 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 247 else { 248 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 249 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 250 } 251 } 252 } 253 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, Ops); 254 } 255 VT = NVT; 256 break; 257 } 258 } 259 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 260} 261 262/// getScalarizedOpcode - Return the scalar opcode that corresponds to the 263/// specified vector opcode. 264static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 265 switch (VecOp) { 266 default: assert(0 && "Don't know how to scalarize this opcode!"); 267 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 268 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 269 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 270 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV; 271 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV; 272 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0; 273 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0; 274 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0; 275 } 276} 277 278SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 279 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 280 ValueTypeActions(TLI.getValueTypeActions()) { 281 assert(MVT::LAST_VALUETYPE <= 32 && 282 "Too many value types for ValueTypeActions to hold!"); 283} 284 285/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 286/// not been visited yet and if all of its operands have already been visited. 287static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 288 std::map<SDNode*, unsigned> &Visited) { 289 if (++Visited[N] != N->getNumOperands()) 290 return; // Haven't visited all operands yet 291 292 Order.push_back(N); 293 294 if (N->hasOneUse()) { // Tail recurse in common case. 295 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 296 return; 297 } 298 299 // Now that we have N in, add anything that uses it if all of their operands 300 // are now done. 301 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 302 ComputeTopDownOrdering(*UI, Order, Visited); 303} 304 305 306void SelectionDAGLegalize::LegalizeDAG() { 307 LastCALLSEQ_END = DAG.getEntryNode(); 308 IsLegalizingCall = false; 309 310 // The legalize process is inherently a bottom-up recursive process (users 311 // legalize their uses before themselves). Given infinite stack space, we 312 // could just start legalizing on the root and traverse the whole graph. In 313 // practice however, this causes us to run out of stack space on large basic 314 // blocks. To avoid this problem, compute an ordering of the nodes where each 315 // node is only legalized after all of its operands are legalized. 316 std::map<SDNode*, unsigned> Visited; 317 std::vector<SDNode*> Order; 318 319 // Compute ordering from all of the leaves in the graphs, those (like the 320 // entry node) that have no operands. 321 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 322 E = DAG.allnodes_end(); I != E; ++I) { 323 if (I->getNumOperands() == 0) { 324 Visited[I] = 0 - 1U; 325 ComputeTopDownOrdering(I, Order, Visited); 326 } 327 } 328 329 assert(Order.size() == Visited.size() && 330 Order.size() == 331 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 332 "Error: DAG is cyclic!"); 333 Visited.clear(); 334 335 for (unsigned i = 0, e = Order.size(); i != e; ++i) 336 HandleOp(SDOperand(Order[i], 0)); 337 338 // Finally, it's possible the root changed. Get the new root. 339 SDOperand OldRoot = DAG.getRoot(); 340 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 341 DAG.setRoot(LegalizedNodes[OldRoot]); 342 343 ExpandedNodes.clear(); 344 LegalizedNodes.clear(); 345 PromotedNodes.clear(); 346 SplitNodes.clear(); 347 PackedNodes.clear(); 348 349 // Remove dead nodes now. 350 DAG.RemoveDeadNodes(OldRoot.Val); 351} 352 353 354/// FindCallEndFromCallStart - Given a chained node that is part of a call 355/// sequence, find the CALLSEQ_END node that terminates the call sequence. 356static SDNode *FindCallEndFromCallStart(SDNode *Node) { 357 if (Node->getOpcode() == ISD::CALLSEQ_END) 358 return Node; 359 if (Node->use_empty()) 360 return 0; // No CallSeqEnd 361 362 // The chain is usually at the end. 363 SDOperand TheChain(Node, Node->getNumValues()-1); 364 if (TheChain.getValueType() != MVT::Other) { 365 // Sometimes it's at the beginning. 366 TheChain = SDOperand(Node, 0); 367 if (TheChain.getValueType() != MVT::Other) { 368 // Otherwise, hunt for it. 369 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 370 if (Node->getValueType(i) == MVT::Other) { 371 TheChain = SDOperand(Node, i); 372 break; 373 } 374 375 // Otherwise, we walked into a node without a chain. 376 if (TheChain.getValueType() != MVT::Other) 377 return 0; 378 } 379 } 380 381 for (SDNode::use_iterator UI = Node->use_begin(), 382 E = Node->use_end(); UI != E; ++UI) { 383 384 // Make sure to only follow users of our token chain. 385 SDNode *User = *UI; 386 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 387 if (User->getOperand(i) == TheChain) 388 if (SDNode *Result = FindCallEndFromCallStart(User)) 389 return Result; 390 } 391 return 0; 392} 393 394/// FindCallStartFromCallEnd - Given a chained node that is part of a call 395/// sequence, find the CALLSEQ_START node that initiates the call sequence. 396static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 397 assert(Node && "Didn't find callseq_start for a call??"); 398 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 399 400 assert(Node->getOperand(0).getValueType() == MVT::Other && 401 "Node doesn't have a token chain argument!"); 402 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 403} 404 405/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 406/// see if any uses can reach Dest. If no dest operands can get to dest, 407/// legalize them, legalize ourself, and return false, otherwise, return true. 408bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, 409 SDNode *Dest) { 410 if (N == Dest) return true; // N certainly leads to Dest :) 411 412 // If the first result of this node has been already legalized, then it cannot 413 // reach N. 414 switch (getTypeAction(N->getValueType(0))) { 415 case Legal: 416 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 417 break; 418 case Promote: 419 if (PromotedNodes.count(SDOperand(N, 0))) return false; 420 break; 421 case Expand: 422 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 423 break; 424 } 425 426 // Okay, this node has not already been legalized. Check and legalize all 427 // operands. If none lead to Dest, then we can legalize this node. 428 bool OperandsLeadToDest = false; 429 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 430 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 431 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest); 432 433 if (OperandsLeadToDest) return true; 434 435 // Okay, this node looks safe, legalize it and return false. 436 switch (getTypeAction(N->getValueType(0))) { 437 case Legal: 438 LegalizeOp(SDOperand(N, 0)); 439 break; 440 case Promote: 441 PromoteOp(SDOperand(N, 0)); 442 break; 443 case Expand: { 444 SDOperand X, Y; 445 ExpandOp(SDOperand(N, 0), X, Y); 446 break; 447 } 448 } 449 return false; 450} 451 452/// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 453/// appropriate for its type. 454void SelectionDAGLegalize::HandleOp(SDOperand Op) { 455 switch (getTypeAction(Op.getValueType())) { 456 default: assert(0 && "Bad type action!"); 457 case Legal: LegalizeOp(Op); break; 458 case Promote: PromoteOp(Op); break; 459 case Expand: 460 if (Op.getValueType() != MVT::Vector) { 461 SDOperand X, Y; 462 ExpandOp(Op, X, Y); 463 } else { 464 SDNode *N = Op.Val; 465 unsigned NumOps = N->getNumOperands(); 466 unsigned NumElements = 467 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue(); 468 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT(); 469 MVT::ValueType PackedVT = getVectorType(EVT, NumElements); 470 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) { 471 // In the common case, this is a legal vector type, convert it to the 472 // packed operation and type now. 473 PackVectorOp(Op, PackedVT); 474 } else if (NumElements == 1) { 475 // Otherwise, if this is a single element vector, convert it to a 476 // scalar operation. 477 PackVectorOp(Op, EVT); 478 } else { 479 // Otherwise, this is a multiple element vector that isn't supported. 480 // Split it in half and legalize both parts. 481 SDOperand X, Y; 482 SplitVectorOp(Op, X, Y); 483 } 484 } 485 break; 486 } 487} 488 489 490/// LegalizeOp - We know that the specified value has a legal type. 491/// Recursively ensure that the operands have legal types, then return the 492/// result. 493SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 494 assert(isTypeLegal(Op.getValueType()) && 495 "Caller should expand or promote operands that are not legal!"); 496 SDNode *Node = Op.Val; 497 498 // If this operation defines any values that cannot be represented in a 499 // register on this target, make sure to expand or promote them. 500 if (Node->getNumValues() > 1) { 501 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 502 if (getTypeAction(Node->getValueType(i)) != Legal) { 503 HandleOp(Op.getValue(i)); 504 assert(LegalizedNodes.count(Op) && 505 "Handling didn't add legal operands!"); 506 return LegalizedNodes[Op]; 507 } 508 } 509 510 // Note that LegalizeOp may be reentered even from single-use nodes, which 511 // means that we always must cache transformed nodes. 512 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 513 if (I != LegalizedNodes.end()) return I->second; 514 515 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 516 SDOperand Result = Op; 517 bool isCustom = false; 518 519 switch (Node->getOpcode()) { 520 case ISD::FrameIndex: 521 case ISD::EntryToken: 522 case ISD::Register: 523 case ISD::BasicBlock: 524 case ISD::TargetFrameIndex: 525 case ISD::TargetConstant: 526 case ISD::TargetConstantFP: 527 case ISD::TargetConstantPool: 528 case ISD::TargetGlobalAddress: 529 case ISD::TargetExternalSymbol: 530 case ISD::VALUETYPE: 531 case ISD::SRCVALUE: 532 case ISD::STRING: 533 case ISD::CONDCODE: 534 // Primitives must all be legal. 535 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 536 "This must be legal!"); 537 break; 538 default: 539 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 540 // If this is a target node, legalize it by legalizing the operands then 541 // passing it through. 542 std::vector<SDOperand> Ops; 543 bool Changed = false; 544 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 545 Ops.push_back(LegalizeOp(Node->getOperand(i))); 546 Changed = Changed || Node->getOperand(i) != Ops.back(); 547 } 548 if (Changed) 549 if (Node->getNumValues() == 1) 550 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 551 else { 552 std::vector<MVT::ValueType> VTs(Node->value_begin(), 553 Node->value_end()); 554 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 555 } 556 557 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 558 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 559 return Result.getValue(Op.ResNo); 560 } 561 // Otherwise this is an unhandled builtin node. splat. 562 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 563 assert(0 && "Do not know how to legalize this operator!"); 564 abort(); 565 case ISD::GlobalAddress: 566 case ISD::ExternalSymbol: 567 case ISD::ConstantPool: // Nothing to do. 568 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 569 default: assert(0 && "This action is not supported yet!"); 570 case TargetLowering::Custom: 571 Tmp1 = TLI.LowerOperation(Op, DAG); 572 if (Tmp1.Val) Result = Tmp1; 573 // FALLTHROUGH if the target doesn't want to lower this op after all. 574 case TargetLowering::Legal: 575 break; 576 } 577 break; 578 case ISD::AssertSext: 579 case ISD::AssertZext: 580 Tmp1 = LegalizeOp(Node->getOperand(0)); 581 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 582 break; 583 case ISD::MERGE_VALUES: 584 // Legalize eliminates MERGE_VALUES nodes. 585 Result = Node->getOperand(Op.ResNo); 586 break; 587 case ISD::CopyFromReg: 588 Tmp1 = LegalizeOp(Node->getOperand(0)); 589 Result = Op.getValue(0); 590 if (Node->getNumValues() == 2) { 591 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 592 } else { 593 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 594 if (Node->getNumOperands() == 3) { 595 Tmp2 = LegalizeOp(Node->getOperand(2)); 596 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 597 } else { 598 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 599 } 600 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 601 } 602 // Since CopyFromReg produces two values, make sure to remember that we 603 // legalized both of them. 604 AddLegalizedOperand(Op.getValue(0), Result); 605 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 606 return Result.getValue(Op.ResNo); 607 case ISD::UNDEF: { 608 MVT::ValueType VT = Op.getValueType(); 609 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 610 default: assert(0 && "This action is not supported yet!"); 611 case TargetLowering::Expand: 612 if (MVT::isInteger(VT)) 613 Result = DAG.getConstant(0, VT); 614 else if (MVT::isFloatingPoint(VT)) 615 Result = DAG.getConstantFP(0, VT); 616 else 617 assert(0 && "Unknown value type!"); 618 break; 619 case TargetLowering::Legal: 620 break; 621 } 622 break; 623 } 624 625 case ISD::INTRINSIC_W_CHAIN: 626 case ISD::INTRINSIC_WO_CHAIN: 627 case ISD::INTRINSIC_VOID: { 628 std::vector<SDOperand> Ops; 629 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 630 Ops.push_back(LegalizeOp(Node->getOperand(i))); 631 Result = DAG.UpdateNodeOperands(Result, Ops); 632 633 // Allow the target to custom lower its intrinsics if it wants to. 634 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 635 TargetLowering::Custom) { 636 Tmp3 = TLI.LowerOperation(Result, DAG); 637 if (Tmp3.Val) Result = Tmp3; 638 } 639 640 if (Result.Val->getNumValues() == 1) break; 641 642 // Must have return value and chain result. 643 assert(Result.Val->getNumValues() == 2 && 644 "Cannot return more than two values!"); 645 646 // Since loads produce two values, make sure to remember that we 647 // legalized both of them. 648 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 649 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 650 return Result.getValue(Op.ResNo); 651 } 652 653 case ISD::LOCATION: 654 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 655 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 656 657 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 658 case TargetLowering::Promote: 659 default: assert(0 && "This action is not supported yet!"); 660 case TargetLowering::Expand: { 661 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 662 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 663 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other); 664 665 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) { 666 const std::string &FName = 667 cast<StringSDNode>(Node->getOperand(3))->getValue(); 668 const std::string &DirName = 669 cast<StringSDNode>(Node->getOperand(4))->getValue(); 670 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName); 671 672 std::vector<SDOperand> Ops; 673 Ops.push_back(Tmp1); // chain 674 SDOperand LineOp = Node->getOperand(1); 675 SDOperand ColOp = Node->getOperand(2); 676 677 if (useDEBUG_LOC) { 678 Ops.push_back(LineOp); // line # 679 Ops.push_back(ColOp); // col # 680 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 681 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops); 682 } else { 683 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 684 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 685 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile); 686 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 687 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops); 688 } 689 } else { 690 Result = Tmp1; // chain 691 } 692 break; 693 } 694 case TargetLowering::Legal: 695 if (Tmp1 != Node->getOperand(0) || 696 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 697 std::vector<SDOperand> Ops; 698 Ops.push_back(Tmp1); 699 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 700 Ops.push_back(Node->getOperand(1)); // line # must be legal. 701 Ops.push_back(Node->getOperand(2)); // col # must be legal. 702 } else { 703 // Otherwise promote them. 704 Ops.push_back(PromoteOp(Node->getOperand(1))); 705 Ops.push_back(PromoteOp(Node->getOperand(2))); 706 } 707 Ops.push_back(Node->getOperand(3)); // filename must be legal. 708 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 709 Result = DAG.UpdateNodeOperands(Result, Ops); 710 } 711 break; 712 } 713 break; 714 715 case ISD::DEBUG_LOC: 716 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 717 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 718 default: assert(0 && "This action is not supported yet!"); 719 case TargetLowering::Legal: 720 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 721 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 722 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 723 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 724 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 725 break; 726 } 727 break; 728 729 case ISD::DEBUG_LABEL: 730 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!"); 731 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) { 732 default: assert(0 && "This action is not supported yet!"); 733 case TargetLowering::Legal: 734 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 735 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 736 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 737 break; 738 } 739 break; 740 741 case ISD::Constant: 742 // We know we don't need to expand constants here, constants only have one 743 // value and we check that it is fine above. 744 745 // FIXME: Maybe we should handle things like targets that don't support full 746 // 32-bit immediates? 747 break; 748 case ISD::ConstantFP: { 749 // Spill FP immediates to the constant pool if the target cannot directly 750 // codegen them. Targets often have some immediate values that can be 751 // efficiently generated into an FP register without a load. We explicitly 752 // leave these constants as ConstantFP nodes for the target to deal with. 753 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 754 755 // Check to see if this FP immediate is already legal. 756 bool isLegal = false; 757 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 758 E = TLI.legal_fpimm_end(); I != E; ++I) 759 if (CFP->isExactlyValue(*I)) { 760 isLegal = true; 761 break; 762 } 763 764 // If this is a legal constant, turn it into a TargetConstantFP node. 765 if (isLegal) { 766 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0)); 767 break; 768 } 769 770 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 771 default: assert(0 && "This action is not supported yet!"); 772 case TargetLowering::Custom: 773 Tmp3 = TLI.LowerOperation(Result, DAG); 774 if (Tmp3.Val) { 775 Result = Tmp3; 776 break; 777 } 778 // FALLTHROUGH 779 case TargetLowering::Expand: 780 // Otherwise we need to spill the constant to memory. 781 bool Extend = false; 782 783 // If a FP immediate is precise when represented as a float and if the 784 // target can do an extending load from float to double, we put it into 785 // the constant pool as a float, even if it's is statically typed as a 786 // double. 787 MVT::ValueType VT = CFP->getValueType(0); 788 bool isDouble = VT == MVT::f64; 789 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 790 Type::FloatTy, CFP->getValue()); 791 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 792 // Only do this if the target has a native EXTLOAD instruction from 793 // f32. 794 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 795 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 796 VT = MVT::f32; 797 Extend = true; 798 } 799 800 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 801 if (Extend) { 802 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 803 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 804 } else { 805 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 806 DAG.getSrcValue(NULL)); 807 } 808 } 809 break; 810 } 811 case ISD::TokenFactor: 812 if (Node->getNumOperands() == 2) { 813 Tmp1 = LegalizeOp(Node->getOperand(0)); 814 Tmp2 = LegalizeOp(Node->getOperand(1)); 815 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 816 } else if (Node->getNumOperands() == 3) { 817 Tmp1 = LegalizeOp(Node->getOperand(0)); 818 Tmp2 = LegalizeOp(Node->getOperand(1)); 819 Tmp3 = LegalizeOp(Node->getOperand(2)); 820 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 821 } else { 822 std::vector<SDOperand> Ops; 823 // Legalize the operands. 824 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 825 Ops.push_back(LegalizeOp(Node->getOperand(i))); 826 Result = DAG.UpdateNodeOperands(Result, Ops); 827 } 828 break; 829 830 case ISD::BUILD_VECTOR: 831 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 832 default: assert(0 && "This action is not supported yet!"); 833 case TargetLowering::Custom: 834 Tmp3 = TLI.LowerOperation(Result, DAG); 835 if (Tmp3.Val) { 836 Result = Tmp3; 837 break; 838 } 839 // FALLTHROUGH 840 case TargetLowering::Expand: 841 Result = ExpandBUILD_VECTOR(Result.Val); 842 break; 843 } 844 break; 845 case ISD::INSERT_VECTOR_ELT: 846 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 847 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 848 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 849 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 850 851 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 852 Node->getValueType(0))) { 853 default: assert(0 && "This action is not supported yet!"); 854 case TargetLowering::Legal: 855 break; 856 case TargetLowering::Custom: 857 Tmp3 = TLI.LowerOperation(Result, DAG); 858 if (Tmp3.Val) { 859 Result = Tmp3; 860 break; 861 } 862 // FALLTHROUGH 863 case TargetLowering::Expand: { 864 // If the target doesn't support this, we have to spill the input vector 865 // to a temporary stack slot, update the element, then reload it. This is 866 // badness. We could also load the value into a vector register (either 867 // with a "move to register" or "extload into register" instruction, then 868 // permute it into place, if the idx is a constant and if the idx is 869 // supported by the target. 870 SDOperand StackPtr = CreateStackTemporary(Tmp1.getValueType()); 871 // Store the vector. 872 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 873 Tmp1, StackPtr, DAG.getSrcValue(NULL)); 874 875 // Truncate or zero extend offset to target pointer type. 876 MVT::ValueType IntPtr = TLI.getPointerTy(); 877 if (Tmp3.getValueType() > IntPtr) 878 Tmp3 = DAG.getNode(ISD::TRUNCATE, IntPtr, Tmp3); 879 else 880 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Tmp3); 881 882 // Add the offset to the index. 883 unsigned EltSize = MVT::getSizeInBits(Result.getValueType())/8; 884 Tmp3 = DAG.getNode(ISD::MUL, Tmp3.getValueType(), Tmp3, 885 DAG.getConstant(EltSize, Tmp3.getValueType())); 886 SDOperand StackPtr2 = 887 DAG.getNode(ISD::ADD, Tmp3.getValueType(), Tmp3, StackPtr); 888 // Store the scalar value. 889 Ch = DAG.getNode(ISD::STORE, MVT::Other, Ch, 890 Tmp2, StackPtr2, DAG.getSrcValue(NULL)); 891 // Load the updated vector. 892 Result = DAG.getLoad(Result.getValueType(), Ch, StackPtr, 893 DAG.getSrcValue(NULL)); 894 break; 895 } 896 } 897 break; 898 case ISD::SCALAR_TO_VECTOR: 899 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 900 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 901 break; 902 } 903 904 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 905 Result = DAG.UpdateNodeOperands(Result, Tmp1); 906 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 907 Node->getValueType(0))) { 908 default: assert(0 && "This action is not supported yet!"); 909 case TargetLowering::Legal: 910 break; 911 case TargetLowering::Custom: 912 Tmp3 = TLI.LowerOperation(Result, DAG); 913 if (Tmp3.Val) { 914 Result = Tmp3; 915 break; 916 } 917 // FALLTHROUGH 918 case TargetLowering::Expand: 919 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 920 break; 921 } 922 break; 923 case ISD::VECTOR_SHUFFLE: 924 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 925 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 926 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 927 928 // Allow targets to custom lower the SHUFFLEs they support. 929 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 930 default: assert(0 && "Unknown operation action!"); 931 case TargetLowering::Legal: 932 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 933 "vector shuffle should not be created if not legal!"); 934 break; 935 case TargetLowering::Custom: 936 Tmp3 = TLI.LowerOperation(Result, DAG); 937 if (Tmp3.Val) { 938 Result = Tmp3; 939 break; 940 } 941 // FALLTHROUGH 942 case TargetLowering::Expand: { 943 MVT::ValueType VT = Node->getValueType(0); 944 MVT::ValueType EltVT = MVT::getVectorBaseType(VT); 945 MVT::ValueType PtrVT = TLI.getPointerTy(); 946 SDOperand Mask = Node->getOperand(2); 947 unsigned NumElems = Mask.getNumOperands(); 948 std::vector<SDOperand> Ops; 949 for (unsigned i = 0; i != NumElems; ++i) { 950 SDOperand Arg = Mask.getOperand(i); 951 if (Arg.getOpcode() == ISD::UNDEF) { 952 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 953 } else { 954 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 955 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 956 if (Idx < NumElems) 957 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 958 DAG.getConstant(Idx, PtrVT))); 959 else 960 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 961 DAG.getConstant(Idx - NumElems, PtrVT))); 962 } 963 } 964 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, Ops); 965 break; 966 } 967 case TargetLowering::Promote: { 968 // Change base type to a different vector type. 969 MVT::ValueType OVT = Node->getValueType(0); 970 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 971 972 // Cast the two input vectors. 973 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 974 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 975 976 // Convert the shuffle mask to the right # elements. 977 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 978 assert(Tmp3.Val && "Shuffle not legal?"); 979 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 980 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 981 break; 982 } 983 } 984 break; 985 986 case ISD::EXTRACT_VECTOR_ELT: 987 Tmp1 = LegalizeOp(Node->getOperand(0)); 988 Tmp2 = LegalizeOp(Node->getOperand(1)); 989 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 990 991 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, 992 Tmp1.getValueType())) { 993 default: assert(0 && "This action is not supported yet!"); 994 case TargetLowering::Legal: 995 break; 996 case TargetLowering::Custom: 997 Tmp3 = TLI.LowerOperation(Result, DAG); 998 if (Tmp3.Val) { 999 Result = Tmp3; 1000 break; 1001 } 1002 // FALLTHROUGH 1003 case TargetLowering::Expand: 1004 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1005 break; 1006 } 1007 break; 1008 1009 case ISD::VEXTRACT_VECTOR_ELT: 1010 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op)); 1011 break; 1012 1013 case ISD::CALLSEQ_START: { 1014 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1015 1016 // Recursively Legalize all of the inputs of the call end that do not lead 1017 // to this call start. This ensures that any libcalls that need be inserted 1018 // are inserted *before* the CALLSEQ_START. 1019 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1020 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node); 1021 1022 // Now that we legalized all of the inputs (which may have inserted 1023 // libcalls) create the new CALLSEQ_START node. 1024 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1025 1026 // Merge in the last call, to ensure that this call start after the last 1027 // call ended. 1028 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1029 Tmp1 = LegalizeOp(Tmp1); 1030 1031 // Do not try to legalize the target-specific arguments (#1+). 1032 if (Tmp1 != Node->getOperand(0)) { 1033 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 1034 Ops[0] = Tmp1; 1035 Result = DAG.UpdateNodeOperands(Result, Ops); 1036 } 1037 1038 // Remember that the CALLSEQ_START is legalized. 1039 AddLegalizedOperand(Op.getValue(0), Result); 1040 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1041 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1042 1043 // Now that the callseq_start and all of the non-call nodes above this call 1044 // sequence have been legalized, legalize the call itself. During this 1045 // process, no libcalls can/will be inserted, guaranteeing that no calls 1046 // can overlap. 1047 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1048 SDOperand InCallSEQ = LastCALLSEQ_END; 1049 // Note that we are selecting this call! 1050 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1051 IsLegalizingCall = true; 1052 1053 // Legalize the call, starting from the CALLSEQ_END. 1054 LegalizeOp(LastCALLSEQ_END); 1055 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1056 return Result; 1057 } 1058 case ISD::CALLSEQ_END: 1059 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1060 // will cause this node to be legalized as well as handling libcalls right. 1061 if (LastCALLSEQ_END.Val != Node) { 1062 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1063 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1064 assert(I != LegalizedNodes.end() && 1065 "Legalizing the call start should have legalized this node!"); 1066 return I->second; 1067 } 1068 1069 // Otherwise, the call start has been legalized and everything is going 1070 // according to plan. Just legalize ourselves normally here. 1071 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1072 // Do not try to legalize the target-specific arguments (#1+), except for 1073 // an optional flag input. 1074 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1075 if (Tmp1 != Node->getOperand(0)) { 1076 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 1077 Ops[0] = Tmp1; 1078 Result = DAG.UpdateNodeOperands(Result, Ops); 1079 } 1080 } else { 1081 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1082 if (Tmp1 != Node->getOperand(0) || 1083 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1084 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 1085 Ops[0] = Tmp1; 1086 Ops.back() = Tmp2; 1087 Result = DAG.UpdateNodeOperands(Result, Ops); 1088 } 1089 } 1090 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1091 // This finishes up call legalization. 1092 IsLegalizingCall = false; 1093 1094 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1095 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1096 if (Node->getNumValues() == 2) 1097 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1098 return Result.getValue(Op.ResNo); 1099 case ISD::DYNAMIC_STACKALLOC: { 1100 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1101 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1102 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1103 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1104 1105 Tmp1 = Result.getValue(0); 1106 Tmp2 = Result.getValue(1); 1107 switch (TLI.getOperationAction(Node->getOpcode(), 1108 Node->getValueType(0))) { 1109 default: assert(0 && "This action is not supported yet!"); 1110 case TargetLowering::Expand: { 1111 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1112 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1113 " not tell us which reg is the stack pointer!"); 1114 SDOperand Chain = Tmp1.getOperand(0); 1115 SDOperand Size = Tmp2.getOperand(1); 1116 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0)); 1117 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value 1118 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain 1119 Tmp1 = LegalizeOp(Tmp1); 1120 Tmp2 = LegalizeOp(Tmp2); 1121 break; 1122 } 1123 case TargetLowering::Custom: 1124 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1125 if (Tmp3.Val) { 1126 Tmp1 = LegalizeOp(Tmp3); 1127 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1128 } 1129 break; 1130 case TargetLowering::Legal: 1131 break; 1132 } 1133 // Since this op produce two values, make sure to remember that we 1134 // legalized both of them. 1135 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1136 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1137 return Op.ResNo ? Tmp2 : Tmp1; 1138 } 1139 case ISD::INLINEASM: 1140 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize Chain. 1141 Tmp2 = Node->getOperand(Node->getNumOperands()-1); 1142 if (Tmp2.getValueType() == MVT::Flag) // Legalize Flag if it exists. 1143 Tmp2 = Tmp3 = SDOperand(0, 0); 1144 else 1145 Tmp3 = LegalizeOp(Tmp2); 1146 1147 if (Tmp1 != Node->getOperand(0) || Tmp2 != Tmp3) { 1148 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 1149 Ops[0] = Tmp1; 1150 if (Tmp3.Val) Ops.back() = Tmp3; 1151 Result = DAG.UpdateNodeOperands(Result, Ops); 1152 } 1153 1154 // INLINE asm returns a chain and flag, make sure to add both to the map. 1155 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1156 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1157 return Result.getValue(Op.ResNo); 1158 case ISD::BR: 1159 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1160 // Ensure that libcalls are emitted before a branch. 1161 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1162 Tmp1 = LegalizeOp(Tmp1); 1163 LastCALLSEQ_END = DAG.getEntryNode(); 1164 1165 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1166 break; 1167 1168 case ISD::BRCOND: 1169 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1170 // Ensure that libcalls are emitted before a return. 1171 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1172 Tmp1 = LegalizeOp(Tmp1); 1173 LastCALLSEQ_END = DAG.getEntryNode(); 1174 1175 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1176 case Expand: assert(0 && "It's impossible to expand bools"); 1177 case Legal: 1178 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1179 break; 1180 case Promote: 1181 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1182 break; 1183 } 1184 1185 // Basic block destination (Op#2) is always legal. 1186 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1187 1188 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1189 default: assert(0 && "This action is not supported yet!"); 1190 case TargetLowering::Legal: break; 1191 case TargetLowering::Custom: 1192 Tmp1 = TLI.LowerOperation(Result, DAG); 1193 if (Tmp1.Val) Result = Tmp1; 1194 break; 1195 case TargetLowering::Expand: 1196 // Expand brcond's setcc into its constituent parts and create a BR_CC 1197 // Node. 1198 if (Tmp2.getOpcode() == ISD::SETCC) { 1199 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1200 Tmp2.getOperand(0), Tmp2.getOperand(1), 1201 Node->getOperand(2)); 1202 } else { 1203 // Make sure the condition is either zero or one. It may have been 1204 // promoted from something else. 1205 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType()); 1206 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1)) 1207 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1208 1209 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1210 DAG.getCondCode(ISD::SETNE), Tmp2, 1211 DAG.getConstant(0, Tmp2.getValueType()), 1212 Node->getOperand(2)); 1213 } 1214 break; 1215 } 1216 break; 1217 case ISD::BR_CC: 1218 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1219 // Ensure that libcalls are emitted before a branch. 1220 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1221 Tmp1 = LegalizeOp(Tmp1); 1222 LastCALLSEQ_END = DAG.getEntryNode(); 1223 1224 Tmp2 = Node->getOperand(2); // LHS 1225 Tmp3 = Node->getOperand(3); // RHS 1226 Tmp4 = Node->getOperand(1); // CC 1227 1228 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1229 1230 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1231 // the LHS is a legal SETCC itself. In this case, we need to compare 1232 // the result against zero to select between true and false values. 1233 if (Tmp3.Val == 0) { 1234 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1235 Tmp4 = DAG.getCondCode(ISD::SETNE); 1236 } 1237 1238 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1239 Node->getOperand(4)); 1240 1241 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1242 default: assert(0 && "Unexpected action for BR_CC!"); 1243 case TargetLowering::Legal: break; 1244 case TargetLowering::Custom: 1245 Tmp4 = TLI.LowerOperation(Result, DAG); 1246 if (Tmp4.Val) Result = Tmp4; 1247 break; 1248 } 1249 break; 1250 case ISD::LOAD: { 1251 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1252 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1253 1254 MVT::ValueType VT = Node->getValueType(0); 1255 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1256 Tmp2 = Result.getValue(0); 1257 Tmp3 = Result.getValue(1); 1258 1259 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1260 default: assert(0 && "This action is not supported yet!"); 1261 case TargetLowering::Legal: break; 1262 case TargetLowering::Custom: 1263 Tmp1 = TLI.LowerOperation(Tmp2, DAG); 1264 if (Tmp1.Val) { 1265 Tmp2 = LegalizeOp(Tmp1); 1266 Tmp3 = LegalizeOp(Tmp1.getValue(1)); 1267 } 1268 break; 1269 } 1270 // Since loads produce two values, make sure to remember that we 1271 // legalized both of them. 1272 AddLegalizedOperand(SDOperand(Node, 0), Tmp2); 1273 AddLegalizedOperand(SDOperand(Node, 1), Tmp3); 1274 return Op.ResNo ? Tmp3 : Tmp2; 1275 } 1276 case ISD::EXTLOAD: 1277 case ISD::SEXTLOAD: 1278 case ISD::ZEXTLOAD: { 1279 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1280 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1281 1282 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 1283 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 1284 default: assert(0 && "This action is not supported yet!"); 1285 case TargetLowering::Promote: 1286 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 1287 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), 1288 DAG.getValueType(MVT::i8)); 1289 Tmp1 = Result.getValue(0); 1290 Tmp2 = Result.getValue(1); 1291 break; 1292 case TargetLowering::Custom: 1293 isCustom = true; 1294 // FALLTHROUGH 1295 case TargetLowering::Legal: 1296 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), 1297 Node->getOperand(3)); 1298 Tmp1 = Result.getValue(0); 1299 Tmp2 = Result.getValue(1); 1300 1301 if (isCustom) { 1302 Tmp3 = TLI.LowerOperation(Tmp3, DAG); 1303 if (Tmp3.Val) { 1304 Tmp1 = LegalizeOp(Tmp3); 1305 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1306 } 1307 } 1308 break; 1309 case TargetLowering::Expand: 1310 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1311 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1312 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 1313 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1314 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1315 Tmp2 = LegalizeOp(Load.getValue(1)); 1316 break; 1317 } 1318 assert(Node->getOpcode() != ISD::EXTLOAD && 1319 "EXTLOAD should always be supported!"); 1320 // Turn the unsupported load into an EXTLOAD followed by an explicit 1321 // zero/sign extend inreg. 1322 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1323 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1324 SDOperand ValRes; 1325 if (Node->getOpcode() == ISD::SEXTLOAD) 1326 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1327 Result, DAG.getValueType(SrcVT)); 1328 else 1329 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1330 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1331 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1332 break; 1333 } 1334 // Since loads produce two values, make sure to remember that we legalized 1335 // both of them. 1336 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1337 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1338 return Op.ResNo ? Tmp2 : Tmp1; 1339 } 1340 case ISD::EXTRACT_ELEMENT: { 1341 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1342 switch (getTypeAction(OpTy)) { 1343 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1344 case Legal: 1345 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1346 // 1 -> Hi 1347 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1348 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1349 TLI.getShiftAmountTy())); 1350 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1351 } else { 1352 // 0 -> Lo 1353 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1354 Node->getOperand(0)); 1355 } 1356 break; 1357 case Expand: 1358 // Get both the low and high parts. 1359 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1360 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1361 Result = Tmp2; // 1 -> Hi 1362 else 1363 Result = Tmp1; // 0 -> Lo 1364 break; 1365 } 1366 break; 1367 } 1368 1369 case ISD::CopyToReg: 1370 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1371 1372 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1373 "Register type must be legal!"); 1374 // Legalize the incoming value (must be a legal type). 1375 Tmp2 = LegalizeOp(Node->getOperand(2)); 1376 if (Node->getNumValues() == 1) { 1377 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1378 } else { 1379 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1380 if (Node->getNumOperands() == 4) { 1381 Tmp3 = LegalizeOp(Node->getOperand(3)); 1382 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1383 Tmp3); 1384 } else { 1385 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1386 } 1387 1388 // Since this produces two values, make sure to remember that we legalized 1389 // both of them. 1390 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1391 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1392 return Result; 1393 } 1394 break; 1395 1396 case ISD::RET: 1397 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1398 1399 // Ensure that libcalls are emitted before a return. 1400 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1401 Tmp1 = LegalizeOp(Tmp1); 1402 LastCALLSEQ_END = DAG.getEntryNode(); 1403 1404 switch (Node->getNumOperands()) { 1405 case 2: // ret val 1406 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1407 case Legal: 1408 Tmp2 = LegalizeOp(Node->getOperand(1)); 1409 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1410 break; 1411 case Expand: { 1412 SDOperand Lo, Hi; 1413 ExpandOp(Node->getOperand(1), Lo, Hi); 1414 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1415 break; 1416 } 1417 case Promote: 1418 Tmp2 = PromoteOp(Node->getOperand(1)); 1419 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1420 Result = LegalizeOp(Result); 1421 break; 1422 } 1423 break; 1424 case 1: // ret void 1425 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1426 break; 1427 default: { // ret <values> 1428 std::vector<SDOperand> NewValues; 1429 NewValues.push_back(Tmp1); 1430 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1431 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1432 case Legal: 1433 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1434 break; 1435 case Expand: { 1436 SDOperand Lo, Hi; 1437 ExpandOp(Node->getOperand(i), Lo, Hi); 1438 NewValues.push_back(Lo); 1439 NewValues.push_back(Hi); 1440 break; 1441 } 1442 case Promote: 1443 assert(0 && "Can't promote multiple return value yet!"); 1444 } 1445 1446 if (NewValues.size() == Node->getNumOperands()) 1447 Result = DAG.UpdateNodeOperands(Result, NewValues); 1448 else 1449 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1450 break; 1451 } 1452 } 1453 1454 if (Result.getOpcode() == ISD::RET) { 1455 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 1456 default: assert(0 && "This action is not supported yet!"); 1457 case TargetLowering::Legal: break; 1458 case TargetLowering::Custom: 1459 Tmp1 = TLI.LowerOperation(Result, DAG); 1460 if (Tmp1.Val) Result = Tmp1; 1461 break; 1462 } 1463 } 1464 break; 1465 case ISD::STORE: { 1466 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1467 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1468 1469 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1470 // FIXME: We shouldn't do this for TargetConstantFP's. 1471 // FIXME: move this to the DAG Combiner! 1472 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1473 if (CFP->getValueType(0) == MVT::f32) { 1474 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 1475 } else { 1476 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1477 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 1478 } 1479 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1480 Node->getOperand(3)); 1481 break; 1482 } 1483 1484 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1485 case Legal: { 1486 Tmp3 = LegalizeOp(Node->getOperand(1)); 1487 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1488 Node->getOperand(3)); 1489 1490 MVT::ValueType VT = Tmp3.getValueType(); 1491 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1492 default: assert(0 && "This action is not supported yet!"); 1493 case TargetLowering::Legal: break; 1494 case TargetLowering::Custom: 1495 Tmp1 = TLI.LowerOperation(Result, DAG); 1496 if (Tmp1.Val) Result = Tmp1; 1497 break; 1498 } 1499 break; 1500 } 1501 case Promote: 1502 // Truncate the value and store the result. 1503 Tmp3 = PromoteOp(Node->getOperand(1)); 1504 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1505 Node->getOperand(3), 1506 DAG.getValueType(Node->getOperand(1).getValueType())); 1507 break; 1508 1509 case Expand: 1510 unsigned IncrementSize = 0; 1511 SDOperand Lo, Hi; 1512 1513 // If this is a vector type, then we have to calculate the increment as 1514 // the product of the element size in bytes, and the number of elements 1515 // in the high half of the vector. 1516 if (Node->getOperand(1).getValueType() == MVT::Vector) { 1517 SDNode *InVal = Node->getOperand(1).Val; 1518 unsigned NumElems = 1519 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 1520 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 1521 1522 // Figure out if there is a Packed type corresponding to this Vector 1523 // type. If so, convert to the packed type. 1524 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1525 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 1526 // Turn this into a normal store of the packed type. 1527 Tmp3 = PackVectorOp(Node->getOperand(1), TVT); 1528 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1529 Node->getOperand(3)); 1530 break; 1531 } else if (NumElems == 1) { 1532 // Turn this into a normal store of the scalar type. 1533 Tmp3 = PackVectorOp(Node->getOperand(1), EVT); 1534 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1535 Node->getOperand(3)); 1536 // The scalarized value type may not be legal, e.g. it might require 1537 // promotion or expansion. Relegalize the scalar store. 1538 Result = LegalizeOp(Result); 1539 break; 1540 } else { 1541 SplitVectorOp(Node->getOperand(1), Lo, Hi); 1542 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; 1543 } 1544 } else { 1545 ExpandOp(Node->getOperand(1), Lo, Hi); 1546 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1547 1548 if (!TLI.isLittleEndian()) 1549 std::swap(Lo, Hi); 1550 } 1551 1552 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1553 Node->getOperand(3)); 1554 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1555 getIntPtrConstant(IncrementSize)); 1556 assert(isTypeLegal(Tmp2.getValueType()) && 1557 "Pointers must be legal!"); 1558 // FIXME: This sets the srcvalue of both halves to be the same, which is 1559 // wrong. 1560 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1561 Node->getOperand(3)); 1562 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1563 break; 1564 } 1565 break; 1566 } 1567 case ISD::PCMARKER: 1568 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1569 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1570 break; 1571 case ISD::STACKSAVE: 1572 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1573 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1574 Tmp1 = Result.getValue(0); 1575 Tmp2 = Result.getValue(1); 1576 1577 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 1578 default: assert(0 && "This action is not supported yet!"); 1579 case TargetLowering::Legal: break; 1580 case TargetLowering::Custom: 1581 Tmp3 = TLI.LowerOperation(Result, DAG); 1582 if (Tmp3.Val) { 1583 Tmp1 = LegalizeOp(Tmp3); 1584 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1585 } 1586 break; 1587 case TargetLowering::Expand: 1588 // Expand to CopyFromReg if the target set 1589 // StackPointerRegisterToSaveRestore. 1590 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1591 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 1592 Node->getValueType(0)); 1593 Tmp2 = Tmp1.getValue(1); 1594 } else { 1595 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 1596 Tmp2 = Node->getOperand(0); 1597 } 1598 break; 1599 } 1600 1601 // Since stacksave produce two values, make sure to remember that we 1602 // legalized both of them. 1603 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1604 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1605 return Op.ResNo ? Tmp2 : Tmp1; 1606 1607 case ISD::STACKRESTORE: 1608 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1609 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1610 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1611 1612 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 1613 default: assert(0 && "This action is not supported yet!"); 1614 case TargetLowering::Legal: break; 1615 case TargetLowering::Custom: 1616 Tmp1 = TLI.LowerOperation(Result, DAG); 1617 if (Tmp1.Val) Result = Tmp1; 1618 break; 1619 case TargetLowering::Expand: 1620 // Expand to CopyToReg if the target set 1621 // StackPointerRegisterToSaveRestore. 1622 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1623 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 1624 } else { 1625 Result = Tmp1; 1626 } 1627 break; 1628 } 1629 break; 1630 1631 case ISD::READCYCLECOUNTER: 1632 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1633 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1634 1635 // Since rdcc produce two values, make sure to remember that we legalized 1636 // both of them. 1637 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1638 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1639 return Result; 1640 1641 case ISD::TRUNCSTORE: { 1642 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1643 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1644 1645 assert(isTypeLegal(Node->getOperand(1).getValueType()) && 1646 "Cannot handle illegal TRUNCSTORE yet!"); 1647 Tmp2 = LegalizeOp(Node->getOperand(1)); 1648 1649 // The only promote case we handle is TRUNCSTORE:i1 X into 1650 // -> TRUNCSTORE:i8 (and X, 1) 1651 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1652 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1653 TargetLowering::Promote) { 1654 // Promote the bool to a mask then store. 1655 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1656 DAG.getConstant(1, Tmp2.getValueType())); 1657 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1658 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1659 1660 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1661 Tmp3 != Node->getOperand(2)) { 1662 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 1663 Node->getOperand(3), Node->getOperand(4)); 1664 } 1665 1666 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT(); 1667 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) { 1668 default: assert(0 && "This action is not supported yet!"); 1669 case TargetLowering::Legal: break; 1670 case TargetLowering::Custom: 1671 Tmp1 = TLI.LowerOperation(Result, DAG); 1672 if (Tmp1.Val) Result = Tmp1; 1673 break; 1674 } 1675 break; 1676 } 1677 case ISD::SELECT: 1678 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1679 case Expand: assert(0 && "It's impossible to expand bools"); 1680 case Legal: 1681 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1682 break; 1683 case Promote: 1684 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1685 break; 1686 } 1687 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1688 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1689 1690 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1691 1692 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1693 default: assert(0 && "This action is not supported yet!"); 1694 case TargetLowering::Legal: break; 1695 case TargetLowering::Custom: { 1696 Tmp1 = TLI.LowerOperation(Result, DAG); 1697 if (Tmp1.Val) Result = Tmp1; 1698 break; 1699 } 1700 case TargetLowering::Expand: 1701 if (Tmp1.getOpcode() == ISD::SETCC) { 1702 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1703 Tmp2, Tmp3, 1704 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1705 } else { 1706 // Make sure the condition is either zero or one. It may have been 1707 // promoted from something else. 1708 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType()); 1709 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1)) 1710 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1711 Result = DAG.getSelectCC(Tmp1, 1712 DAG.getConstant(0, Tmp1.getValueType()), 1713 Tmp2, Tmp3, ISD::SETNE); 1714 } 1715 break; 1716 case TargetLowering::Promote: { 1717 MVT::ValueType NVT = 1718 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1719 unsigned ExtOp, TruncOp; 1720 if (MVT::isInteger(Tmp2.getValueType())) { 1721 ExtOp = ISD::ANY_EXTEND; 1722 TruncOp = ISD::TRUNCATE; 1723 } else { 1724 ExtOp = ISD::FP_EXTEND; 1725 TruncOp = ISD::FP_ROUND; 1726 } 1727 // Promote each of the values to the new type. 1728 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1729 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1730 // Perform the larger operation, then round down. 1731 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1732 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1733 break; 1734 } 1735 } 1736 break; 1737 case ISD::SELECT_CC: { 1738 Tmp1 = Node->getOperand(0); // LHS 1739 Tmp2 = Node->getOperand(1); // RHS 1740 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1741 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1742 SDOperand CC = Node->getOperand(4); 1743 1744 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 1745 1746 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1747 // the LHS is a legal SETCC itself. In this case, we need to compare 1748 // the result against zero to select between true and false values. 1749 if (Tmp2.Val == 0) { 1750 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1751 CC = DAG.getCondCode(ISD::SETNE); 1752 } 1753 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 1754 1755 // Everything is legal, see if we should expand this op or something. 1756 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 1757 default: assert(0 && "This action is not supported yet!"); 1758 case TargetLowering::Legal: break; 1759 case TargetLowering::Custom: 1760 Tmp1 = TLI.LowerOperation(Result, DAG); 1761 if (Tmp1.Val) Result = Tmp1; 1762 break; 1763 } 1764 break; 1765 } 1766 case ISD::SETCC: 1767 Tmp1 = Node->getOperand(0); 1768 Tmp2 = Node->getOperand(1); 1769 Tmp3 = Node->getOperand(2); 1770 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 1771 1772 // If we had to Expand the SetCC operands into a SELECT node, then it may 1773 // not always be possible to return a true LHS & RHS. In this case, just 1774 // return the value we legalized, returned in the LHS 1775 if (Tmp2.Val == 0) { 1776 Result = Tmp1; 1777 break; 1778 } 1779 1780 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 1781 default: assert(0 && "Cannot handle this action for SETCC yet!"); 1782 case TargetLowering::Custom: 1783 isCustom = true; 1784 // FALLTHROUGH. 1785 case TargetLowering::Legal: 1786 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1787 if (isCustom) { 1788 Tmp3 = TLI.LowerOperation(Result, DAG); 1789 if (Tmp3.Val) Result = Tmp3; 1790 } 1791 break; 1792 case TargetLowering::Promote: { 1793 // First step, figure out the appropriate operation to use. 1794 // Allow SETCC to not be supported for all legal data types 1795 // Mostly this targets FP 1796 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 1797 MVT::ValueType OldVT = NewInTy; 1798 1799 // Scan for the appropriate larger type to use. 1800 while (1) { 1801 NewInTy = (MVT::ValueType)(NewInTy+1); 1802 1803 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 1804 "Fell off of the edge of the integer world"); 1805 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 1806 "Fell off of the edge of the floating point world"); 1807 1808 // If the target supports SETCC of this type, use it. 1809 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 1810 break; 1811 } 1812 if (MVT::isInteger(NewInTy)) 1813 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1814 else { 1815 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 1816 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 1817 } 1818 Tmp1 = LegalizeOp(Tmp1); 1819 Tmp2 = LegalizeOp(Tmp2); 1820 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1821 Result = LegalizeOp(Result); 1822 break; 1823 } 1824 case TargetLowering::Expand: 1825 // Expand a setcc node into a select_cc of the same condition, lhs, and 1826 // rhs that selects between const 1 (true) and const 0 (false). 1827 MVT::ValueType VT = Node->getValueType(0); 1828 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1829 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1830 Node->getOperand(2)); 1831 break; 1832 } 1833 break; 1834 case ISD::MEMSET: 1835 case ISD::MEMCPY: 1836 case ISD::MEMMOVE: { 1837 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1838 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1839 1840 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1841 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1842 case Expand: assert(0 && "Cannot expand a byte!"); 1843 case Legal: 1844 Tmp3 = LegalizeOp(Node->getOperand(2)); 1845 break; 1846 case Promote: 1847 Tmp3 = PromoteOp(Node->getOperand(2)); 1848 break; 1849 } 1850 } else { 1851 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1852 } 1853 1854 SDOperand Tmp4; 1855 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1856 case Expand: { 1857 // Length is too big, just take the lo-part of the length. 1858 SDOperand HiPart; 1859 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1860 break; 1861 } 1862 case Legal: 1863 Tmp4 = LegalizeOp(Node->getOperand(3)); 1864 break; 1865 case Promote: 1866 Tmp4 = PromoteOp(Node->getOperand(3)); 1867 break; 1868 } 1869 1870 SDOperand Tmp5; 1871 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1872 case Expand: assert(0 && "Cannot expand this yet!"); 1873 case Legal: 1874 Tmp5 = LegalizeOp(Node->getOperand(4)); 1875 break; 1876 case Promote: 1877 Tmp5 = PromoteOp(Node->getOperand(4)); 1878 break; 1879 } 1880 1881 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1882 default: assert(0 && "This action not implemented for this operation!"); 1883 case TargetLowering::Custom: 1884 isCustom = true; 1885 // FALLTHROUGH 1886 case TargetLowering::Legal: 1887 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 1888 if (isCustom) { 1889 Tmp1 = TLI.LowerOperation(Result, DAG); 1890 if (Tmp1.Val) Result = Tmp1; 1891 } 1892 break; 1893 case TargetLowering::Expand: { 1894 // Otherwise, the target does not support this operation. Lower the 1895 // operation to an explicit libcall as appropriate. 1896 MVT::ValueType IntPtr = TLI.getPointerTy(); 1897 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1898 std::vector<std::pair<SDOperand, const Type*> > Args; 1899 1900 const char *FnName = 0; 1901 if (Node->getOpcode() == ISD::MEMSET) { 1902 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1903 // Extend the (previously legalized) ubyte argument to be an int value 1904 // for the call. 1905 if (Tmp3.getValueType() > MVT::i32) 1906 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 1907 else 1908 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1909 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1910 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1911 1912 FnName = "memset"; 1913 } else if (Node->getOpcode() == ISD::MEMCPY || 1914 Node->getOpcode() == ISD::MEMMOVE) { 1915 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1916 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1917 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1918 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1919 } else { 1920 assert(0 && "Unknown op!"); 1921 } 1922 1923 std::pair<SDOperand,SDOperand> CallResult = 1924 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1925 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1926 Result = CallResult.second; 1927 break; 1928 } 1929 } 1930 break; 1931 } 1932 1933 case ISD::SHL_PARTS: 1934 case ISD::SRA_PARTS: 1935 case ISD::SRL_PARTS: { 1936 std::vector<SDOperand> Ops; 1937 bool Changed = false; 1938 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1939 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1940 Changed |= Ops.back() != Node->getOperand(i); 1941 } 1942 if (Changed) 1943 Result = DAG.UpdateNodeOperands(Result, Ops); 1944 1945 switch (TLI.getOperationAction(Node->getOpcode(), 1946 Node->getValueType(0))) { 1947 default: assert(0 && "This action is not supported yet!"); 1948 case TargetLowering::Legal: break; 1949 case TargetLowering::Custom: 1950 Tmp1 = TLI.LowerOperation(Result, DAG); 1951 if (Tmp1.Val) { 1952 SDOperand Tmp2, RetVal(0, 0); 1953 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 1954 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 1955 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 1956 if (i == Op.ResNo) 1957 RetVal = Tmp2; 1958 } 1959 assert(RetVal.Val && "Illegal result number"); 1960 return RetVal; 1961 } 1962 break; 1963 } 1964 1965 // Since these produce multiple values, make sure to remember that we 1966 // legalized all of them. 1967 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1968 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1969 return Result.getValue(Op.ResNo); 1970 } 1971 1972 // Binary operators 1973 case ISD::ADD: 1974 case ISD::SUB: 1975 case ISD::MUL: 1976 case ISD::MULHS: 1977 case ISD::MULHU: 1978 case ISD::UDIV: 1979 case ISD::SDIV: 1980 case ISD::AND: 1981 case ISD::OR: 1982 case ISD::XOR: 1983 case ISD::SHL: 1984 case ISD::SRL: 1985 case ISD::SRA: 1986 case ISD::FADD: 1987 case ISD::FSUB: 1988 case ISD::FMUL: 1989 case ISD::FDIV: 1990 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1991 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1992 case Expand: assert(0 && "Not possible"); 1993 case Legal: 1994 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 1995 break; 1996 case Promote: 1997 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 1998 break; 1999 } 2000 2001 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2002 2003 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2004 default: assert(0 && "BinOp legalize operation not supported"); 2005 case TargetLowering::Legal: break; 2006 case TargetLowering::Custom: 2007 Tmp1 = TLI.LowerOperation(Result, DAG); 2008 if (Tmp1.Val) Result = Tmp1; 2009 break; 2010 case TargetLowering::Expand: { 2011 assert(MVT::isVector(Node->getValueType(0)) && 2012 "Cannot expand this binary operator!"); 2013 // Expand the operation into a bunch of nasty scalar code. 2014 std::vector<SDOperand> Ops; 2015 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0)); 2016 MVT::ValueType PtrVT = TLI.getPointerTy(); 2017 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0)); 2018 i != e; ++i) { 2019 SDOperand Idx = DAG.getConstant(i, PtrVT); 2020 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx); 2021 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx); 2022 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS)); 2023 } 2024 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops); 2025 break; 2026 } 2027 } 2028 break; 2029 2030 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2031 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2032 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2033 case Expand: assert(0 && "Not possible"); 2034 case Legal: 2035 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2036 break; 2037 case Promote: 2038 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2039 break; 2040 } 2041 2042 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2043 2044 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2045 default: assert(0 && "Operation not supported"); 2046 case TargetLowering::Custom: 2047 Tmp1 = TLI.LowerOperation(Result, DAG); 2048 if (Tmp1.Val) Result = Tmp1; 2049 break; 2050 case TargetLowering::Legal: break; 2051 case TargetLowering::Expand: 2052 // If this target supports fabs/fneg natively, do this efficiently. 2053 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) && 2054 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) { 2055 // Get the sign bit of the RHS. 2056 MVT::ValueType IVT = 2057 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2058 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2059 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2060 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2061 // Get the absolute value of the result. 2062 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2063 // Select between the nabs and abs value based on the sign bit of 2064 // the input. 2065 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2066 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2067 AbsVal), 2068 AbsVal); 2069 Result = LegalizeOp(Result); 2070 break; 2071 } 2072 2073 // Otherwise, do bitwise ops! 2074 2075 // copysign -> copysignf/copysign libcall. 2076 const char *FnName; 2077 if (Node->getValueType(0) == MVT::f32) { 2078 FnName = "copysignf"; 2079 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type. 2080 Result = DAG.UpdateNodeOperands(Result, Tmp1, 2081 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2)); 2082 } else { 2083 FnName = "copysign"; 2084 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type. 2085 Result = DAG.UpdateNodeOperands(Result, Tmp1, 2086 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2)); 2087 } 2088 SDOperand Dummy; 2089 Result = ExpandLibCall(FnName, Node, Dummy); 2090 break; 2091 } 2092 break; 2093 2094 case ISD::ADDC: 2095 case ISD::SUBC: 2096 Tmp1 = LegalizeOp(Node->getOperand(0)); 2097 Tmp2 = LegalizeOp(Node->getOperand(1)); 2098 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2099 // Since this produces two values, make sure to remember that we legalized 2100 // both of them. 2101 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2102 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2103 return Result; 2104 2105 case ISD::ADDE: 2106 case ISD::SUBE: 2107 Tmp1 = LegalizeOp(Node->getOperand(0)); 2108 Tmp2 = LegalizeOp(Node->getOperand(1)); 2109 Tmp3 = LegalizeOp(Node->getOperand(2)); 2110 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2111 // Since this produces two values, make sure to remember that we legalized 2112 // both of them. 2113 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2114 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2115 return Result; 2116 2117 case ISD::BUILD_PAIR: { 2118 MVT::ValueType PairTy = Node->getValueType(0); 2119 // TODO: handle the case where the Lo and Hi operands are not of legal type 2120 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2121 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2122 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2123 case TargetLowering::Promote: 2124 case TargetLowering::Custom: 2125 assert(0 && "Cannot promote/custom this yet!"); 2126 case TargetLowering::Legal: 2127 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2128 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2129 break; 2130 case TargetLowering::Expand: 2131 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2132 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2133 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2134 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2135 TLI.getShiftAmountTy())); 2136 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2137 break; 2138 } 2139 break; 2140 } 2141 2142 case ISD::UREM: 2143 case ISD::SREM: 2144 case ISD::FREM: 2145 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2146 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2147 2148 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2149 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2150 case TargetLowering::Custom: 2151 isCustom = true; 2152 // FALLTHROUGH 2153 case TargetLowering::Legal: 2154 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2155 if (isCustom) { 2156 Tmp1 = TLI.LowerOperation(Result, DAG); 2157 if (Tmp1.Val) Result = Tmp1; 2158 } 2159 break; 2160 case TargetLowering::Expand: 2161 if (MVT::isInteger(Node->getValueType(0))) { 2162 // X % Y -> X-X/Y*Y 2163 MVT::ValueType VT = Node->getValueType(0); 2164 unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV; 2165 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 2166 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2167 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2168 } else { 2169 // Floating point mod -> fmod libcall. 2170 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 2171 SDOperand Dummy; 2172 Result = ExpandLibCall(FnName, Node, Dummy); 2173 } 2174 break; 2175 } 2176 break; 2177 case ISD::VAARG: { 2178 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2179 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2180 2181 MVT::ValueType VT = Node->getValueType(0); 2182 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2183 default: assert(0 && "This action is not supported yet!"); 2184 case TargetLowering::Custom: 2185 isCustom = true; 2186 // FALLTHROUGH 2187 case TargetLowering::Legal: 2188 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2189 Result = Result.getValue(0); 2190 Tmp1 = Result.getValue(1); 2191 2192 if (isCustom) { 2193 Tmp2 = TLI.LowerOperation(Result, DAG); 2194 if (Tmp2.Val) { 2195 Result = LegalizeOp(Tmp2); 2196 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 2197 } 2198 } 2199 break; 2200 case TargetLowering::Expand: { 2201 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2202 Node->getOperand(2)); 2203 // Increment the pointer, VAList, to the next vaarg 2204 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2205 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2206 TLI.getPointerTy())); 2207 // Store the incremented VAList to the legalized pointer 2208 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2, 2209 Node->getOperand(2)); 2210 // Load the actual argument out of the pointer VAList 2211 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0)); 2212 Tmp1 = LegalizeOp(Result.getValue(1)); 2213 Result = LegalizeOp(Result); 2214 break; 2215 } 2216 } 2217 // Since VAARG produces two values, make sure to remember that we 2218 // legalized both of them. 2219 AddLegalizedOperand(SDOperand(Node, 0), Result); 2220 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 2221 return Op.ResNo ? Tmp1 : Result; 2222 } 2223 2224 case ISD::VACOPY: 2225 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2226 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 2227 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 2228 2229 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 2230 default: assert(0 && "This action is not supported yet!"); 2231 case TargetLowering::Custom: 2232 isCustom = true; 2233 // FALLTHROUGH 2234 case TargetLowering::Legal: 2235 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 2236 Node->getOperand(3), Node->getOperand(4)); 2237 if (isCustom) { 2238 Tmp1 = TLI.LowerOperation(Result, DAG); 2239 if (Tmp1.Val) Result = Tmp1; 2240 } 2241 break; 2242 case TargetLowering::Expand: 2243 // This defaults to loading a pointer from the input and storing it to the 2244 // output, returning the chain. 2245 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3)); 2246 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2, 2247 Node->getOperand(4)); 2248 break; 2249 } 2250 break; 2251 2252 case ISD::VAEND: 2253 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2254 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2255 2256 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 2257 default: assert(0 && "This action is not supported yet!"); 2258 case TargetLowering::Custom: 2259 isCustom = true; 2260 // FALLTHROUGH 2261 case TargetLowering::Legal: 2262 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2263 if (isCustom) { 2264 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 2265 if (Tmp1.Val) Result = Tmp1; 2266 } 2267 break; 2268 case TargetLowering::Expand: 2269 Result = Tmp1; // Default to a no-op, return the chain 2270 break; 2271 } 2272 break; 2273 2274 case ISD::VASTART: 2275 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2276 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2277 2278 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2279 2280 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 2281 default: assert(0 && "This action is not supported yet!"); 2282 case TargetLowering::Legal: break; 2283 case TargetLowering::Custom: 2284 Tmp1 = TLI.LowerOperation(Result, DAG); 2285 if (Tmp1.Val) Result = Tmp1; 2286 break; 2287 } 2288 break; 2289 2290 case ISD::ROTL: 2291 case ISD::ROTR: 2292 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2293 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2294 2295 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 2296 "Cannot handle this yet!"); 2297 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2298 break; 2299 2300 case ISD::BSWAP: 2301 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2302 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2303 case TargetLowering::Custom: 2304 assert(0 && "Cannot custom legalize this yet!"); 2305 case TargetLowering::Legal: 2306 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2307 break; 2308 case TargetLowering::Promote: { 2309 MVT::ValueType OVT = Tmp1.getValueType(); 2310 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2311 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT); 2312 2313 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2314 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 2315 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 2316 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 2317 break; 2318 } 2319 case TargetLowering::Expand: 2320 Result = ExpandBSWAP(Tmp1); 2321 break; 2322 } 2323 break; 2324 2325 case ISD::CTPOP: 2326 case ISD::CTTZ: 2327 case ISD::CTLZ: 2328 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2329 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2330 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!"); 2331 case TargetLowering::Legal: 2332 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2333 break; 2334 case TargetLowering::Promote: { 2335 MVT::ValueType OVT = Tmp1.getValueType(); 2336 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2337 2338 // Zero extend the argument. 2339 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2340 // Perform the larger operation, then subtract if needed. 2341 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2342 switch (Node->getOpcode()) { 2343 case ISD::CTPOP: 2344 Result = Tmp1; 2345 break; 2346 case ISD::CTTZ: 2347 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2348 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2349 DAG.getConstant(getSizeInBits(NVT), NVT), 2350 ISD::SETEQ); 2351 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2352 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 2353 break; 2354 case ISD::CTLZ: 2355 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2356 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2357 DAG.getConstant(getSizeInBits(NVT) - 2358 getSizeInBits(OVT), NVT)); 2359 break; 2360 } 2361 break; 2362 } 2363 case TargetLowering::Expand: 2364 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 2365 break; 2366 } 2367 break; 2368 2369 // Unary operators 2370 case ISD::FABS: 2371 case ISD::FNEG: 2372 case ISD::FSQRT: 2373 case ISD::FSIN: 2374 case ISD::FCOS: 2375 Tmp1 = LegalizeOp(Node->getOperand(0)); 2376 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2377 case TargetLowering::Promote: 2378 case TargetLowering::Custom: 2379 isCustom = true; 2380 // FALLTHROUGH 2381 case TargetLowering::Legal: 2382 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2383 if (isCustom) { 2384 Tmp1 = TLI.LowerOperation(Result, DAG); 2385 if (Tmp1.Val) Result = Tmp1; 2386 } 2387 break; 2388 case TargetLowering::Expand: 2389 switch (Node->getOpcode()) { 2390 default: assert(0 && "Unreachable!"); 2391 case ISD::FNEG: 2392 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2393 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2394 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 2395 break; 2396 case ISD::FABS: { 2397 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2398 MVT::ValueType VT = Node->getValueType(0); 2399 Tmp2 = DAG.getConstantFP(0.0, VT); 2400 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2401 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2402 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2403 break; 2404 } 2405 case ISD::FSQRT: 2406 case ISD::FSIN: 2407 case ISD::FCOS: { 2408 MVT::ValueType VT = Node->getValueType(0); 2409 const char *FnName = 0; 2410 switch(Node->getOpcode()) { 2411 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 2412 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 2413 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 2414 default: assert(0 && "Unreachable!"); 2415 } 2416 SDOperand Dummy; 2417 Result = ExpandLibCall(FnName, Node, Dummy); 2418 break; 2419 } 2420 } 2421 break; 2422 } 2423 break; 2424 2425 case ISD::BIT_CONVERT: 2426 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 2427 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2428 } else { 2429 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 2430 Node->getOperand(0).getValueType())) { 2431 default: assert(0 && "Unknown operation action!"); 2432 case TargetLowering::Expand: 2433 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2434 break; 2435 case TargetLowering::Legal: 2436 Tmp1 = LegalizeOp(Node->getOperand(0)); 2437 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2438 break; 2439 } 2440 } 2441 break; 2442 case ISD::VBIT_CONVERT: { 2443 assert(Op.getOperand(0).getValueType() == MVT::Vector && 2444 "Can only have VBIT_CONVERT where input or output is MVT::Vector!"); 2445 2446 // The input has to be a vector type, we have to either scalarize it, pack 2447 // it, or convert it based on whether the input vector type is legal. 2448 SDNode *InVal = Node->getOperand(0).Val; 2449 unsigned NumElems = 2450 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 2451 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 2452 2453 // Figure out if there is a Packed type corresponding to this Vector 2454 // type. If so, convert to the packed type. 2455 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2456 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 2457 // Turn this into a bit convert of the packed input. 2458 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2459 PackVectorOp(Node->getOperand(0), TVT)); 2460 break; 2461 } else if (NumElems == 1) { 2462 // Turn this into a bit convert of the scalar input. 2463 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2464 PackVectorOp(Node->getOperand(0), EVT)); 2465 break; 2466 } else { 2467 // FIXME: UNIMP! Store then reload 2468 assert(0 && "Cast from unsupported vector type not implemented yet!"); 2469 } 2470 } 2471 2472 // Conversion operators. The source and destination have different types. 2473 case ISD::SINT_TO_FP: 2474 case ISD::UINT_TO_FP: { 2475 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2476 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2477 case Legal: 2478 switch (TLI.getOperationAction(Node->getOpcode(), 2479 Node->getOperand(0).getValueType())) { 2480 default: assert(0 && "Unknown operation action!"); 2481 case TargetLowering::Custom: 2482 isCustom = true; 2483 // FALLTHROUGH 2484 case TargetLowering::Legal: 2485 Tmp1 = LegalizeOp(Node->getOperand(0)); 2486 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2487 if (isCustom) { 2488 Tmp1 = TLI.LowerOperation(Result, DAG); 2489 if (Tmp1.Val) Result = Tmp1; 2490 } 2491 break; 2492 case TargetLowering::Expand: 2493 Result = ExpandLegalINT_TO_FP(isSigned, 2494 LegalizeOp(Node->getOperand(0)), 2495 Node->getValueType(0)); 2496 break; 2497 case TargetLowering::Promote: 2498 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2499 Node->getValueType(0), 2500 isSigned); 2501 break; 2502 } 2503 break; 2504 case Expand: 2505 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2506 Node->getValueType(0), Node->getOperand(0)); 2507 break; 2508 case Promote: 2509 Tmp1 = PromoteOp(Node->getOperand(0)); 2510 if (isSigned) { 2511 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 2512 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 2513 } else { 2514 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 2515 Node->getOperand(0).getValueType()); 2516 } 2517 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2518 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 2519 break; 2520 } 2521 break; 2522 } 2523 case ISD::TRUNCATE: 2524 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2525 case Legal: 2526 Tmp1 = LegalizeOp(Node->getOperand(0)); 2527 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2528 break; 2529 case Expand: 2530 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2531 2532 // Since the result is legal, we should just be able to truncate the low 2533 // part of the source. 2534 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2535 break; 2536 case Promote: 2537 Result = PromoteOp(Node->getOperand(0)); 2538 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2539 break; 2540 } 2541 break; 2542 2543 case ISD::FP_TO_SINT: 2544 case ISD::FP_TO_UINT: 2545 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2546 case Legal: 2547 Tmp1 = LegalizeOp(Node->getOperand(0)); 2548 2549 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2550 default: assert(0 && "Unknown operation action!"); 2551 case TargetLowering::Custom: 2552 isCustom = true; 2553 // FALLTHROUGH 2554 case TargetLowering::Legal: 2555 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2556 if (isCustom) { 2557 Tmp1 = TLI.LowerOperation(Result, DAG); 2558 if (Tmp1.Val) Result = Tmp1; 2559 } 2560 break; 2561 case TargetLowering::Promote: 2562 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2563 Node->getOpcode() == ISD::FP_TO_SINT); 2564 break; 2565 case TargetLowering::Expand: 2566 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2567 SDOperand True, False; 2568 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2569 MVT::ValueType NVT = Node->getValueType(0); 2570 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2571 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2572 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2573 Node->getOperand(0), Tmp2, ISD::SETLT); 2574 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2575 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2576 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2577 Tmp2)); 2578 False = DAG.getNode(ISD::XOR, NVT, False, 2579 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2580 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 2581 break; 2582 } else { 2583 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2584 } 2585 break; 2586 } 2587 break; 2588 case Expand: 2589 assert(0 && "Shouldn't need to expand other operators here!"); 2590 case Promote: 2591 Tmp1 = PromoteOp(Node->getOperand(0)); 2592 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 2593 Result = LegalizeOp(Result); 2594 break; 2595 } 2596 break; 2597 2598 case ISD::ANY_EXTEND: 2599 case ISD::ZERO_EXTEND: 2600 case ISD::SIGN_EXTEND: 2601 case ISD::FP_EXTEND: 2602 case ISD::FP_ROUND: 2603 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2604 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 2605 case Legal: 2606 Tmp1 = LegalizeOp(Node->getOperand(0)); 2607 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2608 break; 2609 case Promote: 2610 switch (Node->getOpcode()) { 2611 case ISD::ANY_EXTEND: 2612 Tmp1 = PromoteOp(Node->getOperand(0)); 2613 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 2614 break; 2615 case ISD::ZERO_EXTEND: 2616 Result = PromoteOp(Node->getOperand(0)); 2617 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2618 Result = DAG.getZeroExtendInReg(Result, 2619 Node->getOperand(0).getValueType()); 2620 break; 2621 case ISD::SIGN_EXTEND: 2622 Result = PromoteOp(Node->getOperand(0)); 2623 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2624 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2625 Result, 2626 DAG.getValueType(Node->getOperand(0).getValueType())); 2627 break; 2628 case ISD::FP_EXTEND: 2629 Result = PromoteOp(Node->getOperand(0)); 2630 if (Result.getValueType() != Op.getValueType()) 2631 // Dynamically dead while we have only 2 FP types. 2632 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2633 break; 2634 case ISD::FP_ROUND: 2635 Result = PromoteOp(Node->getOperand(0)); 2636 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2637 break; 2638 } 2639 } 2640 break; 2641 case ISD::FP_ROUND_INREG: 2642 case ISD::SIGN_EXTEND_INREG: { 2643 Tmp1 = LegalizeOp(Node->getOperand(0)); 2644 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2645 2646 // If this operation is not supported, convert it to a shl/shr or load/store 2647 // pair. 2648 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2649 default: assert(0 && "This action not supported for this op yet!"); 2650 case TargetLowering::Legal: 2651 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2652 break; 2653 case TargetLowering::Expand: 2654 // If this is an integer extend and shifts are supported, do that. 2655 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2656 // NOTE: we could fall back on load/store here too for targets without 2657 // SAR. However, it is doubtful that any exist. 2658 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2659 MVT::getSizeInBits(ExtraVT); 2660 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2661 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2662 Node->getOperand(0), ShiftCst); 2663 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2664 Result, ShiftCst); 2665 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2666 // The only way we can lower this is to turn it into a STORETRUNC, 2667 // EXTLOAD pair, targetting a temporary location (a stack slot). 2668 2669 // NOTE: there is a choice here between constantly creating new stack 2670 // slots and always reusing the same one. We currently always create 2671 // new ones, as reuse may inhibit scheduling. 2672 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2673 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2674 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2675 MachineFunction &MF = DAG.getMachineFunction(); 2676 int SSFI = 2677 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2678 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2679 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2680 Node->getOperand(0), StackSlot, 2681 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2682 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2683 Result, StackSlot, DAG.getSrcValue(NULL), 2684 ExtraVT); 2685 } else { 2686 assert(0 && "Unknown op"); 2687 } 2688 break; 2689 } 2690 break; 2691 } 2692 } 2693 2694 // Make sure that the generated code is itself legal. 2695 if (Result != Op) 2696 Result = LegalizeOp(Result); 2697 2698 // Note that LegalizeOp may be reentered even from single-use nodes, which 2699 // means that we always must cache transformed nodes. 2700 AddLegalizedOperand(Op, Result); 2701 return Result; 2702} 2703 2704/// PromoteOp - Given an operation that produces a value in an invalid type, 2705/// promote it to compute the value into a larger type. The produced value will 2706/// have the correct bits for the low portion of the register, but no guarantee 2707/// is made about the top bits: it may be zero, sign-extended, or garbage. 2708SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2709 MVT::ValueType VT = Op.getValueType(); 2710 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2711 assert(getTypeAction(VT) == Promote && 2712 "Caller should expand or legalize operands that are not promotable!"); 2713 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2714 "Cannot promote to smaller type!"); 2715 2716 SDOperand Tmp1, Tmp2, Tmp3; 2717 SDOperand Result; 2718 SDNode *Node = Op.Val; 2719 2720 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2721 if (I != PromotedNodes.end()) return I->second; 2722 2723 switch (Node->getOpcode()) { 2724 case ISD::CopyFromReg: 2725 assert(0 && "CopyFromReg must be legal!"); 2726 default: 2727 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2728 assert(0 && "Do not know how to promote this operator!"); 2729 abort(); 2730 case ISD::UNDEF: 2731 Result = DAG.getNode(ISD::UNDEF, NVT); 2732 break; 2733 case ISD::Constant: 2734 if (VT != MVT::i1) 2735 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2736 else 2737 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2738 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2739 break; 2740 case ISD::ConstantFP: 2741 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2742 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2743 break; 2744 2745 case ISD::SETCC: 2746 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2747 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2748 Node->getOperand(1), Node->getOperand(2)); 2749 break; 2750 2751 case ISD::TRUNCATE: 2752 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2753 case Legal: 2754 Result = LegalizeOp(Node->getOperand(0)); 2755 assert(Result.getValueType() >= NVT && 2756 "This truncation doesn't make sense!"); 2757 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2758 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2759 break; 2760 case Promote: 2761 // The truncation is not required, because we don't guarantee anything 2762 // about high bits anyway. 2763 Result = PromoteOp(Node->getOperand(0)); 2764 break; 2765 case Expand: 2766 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2767 // Truncate the low part of the expanded value to the result type 2768 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2769 } 2770 break; 2771 case ISD::SIGN_EXTEND: 2772 case ISD::ZERO_EXTEND: 2773 case ISD::ANY_EXTEND: 2774 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2775 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2776 case Legal: 2777 // Input is legal? Just do extend all the way to the larger type. 2778 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 2779 break; 2780 case Promote: 2781 // Promote the reg if it's smaller. 2782 Result = PromoteOp(Node->getOperand(0)); 2783 // The high bits are not guaranteed to be anything. Insert an extend. 2784 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2785 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2786 DAG.getValueType(Node->getOperand(0).getValueType())); 2787 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2788 Result = DAG.getZeroExtendInReg(Result, 2789 Node->getOperand(0).getValueType()); 2790 break; 2791 } 2792 break; 2793 case ISD::BIT_CONVERT: 2794 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2795 Result = PromoteOp(Result); 2796 break; 2797 2798 case ISD::FP_EXTEND: 2799 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2800 case ISD::FP_ROUND: 2801 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2802 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2803 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2804 case Legal: 2805 // Input is legal? Do an FP_ROUND_INREG. 2806 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 2807 DAG.getValueType(VT)); 2808 break; 2809 } 2810 break; 2811 2812 case ISD::SINT_TO_FP: 2813 case ISD::UINT_TO_FP: 2814 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2815 case Legal: 2816 // No extra round required here. 2817 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 2818 break; 2819 2820 case Promote: 2821 Result = PromoteOp(Node->getOperand(0)); 2822 if (Node->getOpcode() == ISD::SINT_TO_FP) 2823 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2824 Result, 2825 DAG.getValueType(Node->getOperand(0).getValueType())); 2826 else 2827 Result = DAG.getZeroExtendInReg(Result, 2828 Node->getOperand(0).getValueType()); 2829 // No extra round required here. 2830 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2831 break; 2832 case Expand: 2833 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2834 Node->getOperand(0)); 2835 // Round if we cannot tolerate excess precision. 2836 if (NoExcessFPPrecision) 2837 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2838 DAG.getValueType(VT)); 2839 break; 2840 } 2841 break; 2842 2843 case ISD::SIGN_EXTEND_INREG: 2844 Result = PromoteOp(Node->getOperand(0)); 2845 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2846 Node->getOperand(1)); 2847 break; 2848 case ISD::FP_TO_SINT: 2849 case ISD::FP_TO_UINT: 2850 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2851 case Legal: 2852 Tmp1 = Node->getOperand(0); 2853 break; 2854 case Promote: 2855 // The input result is prerounded, so we don't have to do anything 2856 // special. 2857 Tmp1 = PromoteOp(Node->getOperand(0)); 2858 break; 2859 case Expand: 2860 assert(0 && "not implemented"); 2861 } 2862 // If we're promoting a UINT to a larger size, check to see if the new node 2863 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2864 // we can use that instead. This allows us to generate better code for 2865 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2866 // legal, such as PowerPC. 2867 if (Node->getOpcode() == ISD::FP_TO_UINT && 2868 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2869 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2870 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2871 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2872 } else { 2873 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2874 } 2875 break; 2876 2877 case ISD::FABS: 2878 case ISD::FNEG: 2879 Tmp1 = PromoteOp(Node->getOperand(0)); 2880 assert(Tmp1.getValueType() == NVT); 2881 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2882 // NOTE: we do not have to do any extra rounding here for 2883 // NoExcessFPPrecision, because we know the input will have the appropriate 2884 // precision, and these operations don't modify precision at all. 2885 break; 2886 2887 case ISD::FSQRT: 2888 case ISD::FSIN: 2889 case ISD::FCOS: 2890 Tmp1 = PromoteOp(Node->getOperand(0)); 2891 assert(Tmp1.getValueType() == NVT); 2892 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2893 if (NoExcessFPPrecision) 2894 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2895 DAG.getValueType(VT)); 2896 break; 2897 2898 case ISD::AND: 2899 case ISD::OR: 2900 case ISD::XOR: 2901 case ISD::ADD: 2902 case ISD::SUB: 2903 case ISD::MUL: 2904 // The input may have strange things in the top bits of the registers, but 2905 // these operations don't care. They may have weird bits going out, but 2906 // that too is okay if they are integer operations. 2907 Tmp1 = PromoteOp(Node->getOperand(0)); 2908 Tmp2 = PromoteOp(Node->getOperand(1)); 2909 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2910 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2911 break; 2912 case ISD::FADD: 2913 case ISD::FSUB: 2914 case ISD::FMUL: 2915 Tmp1 = PromoteOp(Node->getOperand(0)); 2916 Tmp2 = PromoteOp(Node->getOperand(1)); 2917 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2918 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2919 2920 // Floating point operations will give excess precision that we may not be 2921 // able to tolerate. If we DO allow excess precision, just leave it, 2922 // otherwise excise it. 2923 // FIXME: Why would we need to round FP ops more than integer ones? 2924 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 2925 if (NoExcessFPPrecision) 2926 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2927 DAG.getValueType(VT)); 2928 break; 2929 2930 case ISD::SDIV: 2931 case ISD::SREM: 2932 // These operators require that their input be sign extended. 2933 Tmp1 = PromoteOp(Node->getOperand(0)); 2934 Tmp2 = PromoteOp(Node->getOperand(1)); 2935 if (MVT::isInteger(NVT)) { 2936 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2937 DAG.getValueType(VT)); 2938 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 2939 DAG.getValueType(VT)); 2940 } 2941 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2942 2943 // Perform FP_ROUND: this is probably overly pessimistic. 2944 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2945 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2946 DAG.getValueType(VT)); 2947 break; 2948 case ISD::FDIV: 2949 case ISD::FREM: 2950 case ISD::FCOPYSIGN: 2951 // These operators require that their input be fp extended. 2952 Tmp1 = PromoteOp(Node->getOperand(0)); 2953 Tmp2 = PromoteOp(Node->getOperand(1)); 2954 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2955 2956 // Perform FP_ROUND: this is probably overly pessimistic. 2957 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 2958 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2959 DAG.getValueType(VT)); 2960 break; 2961 2962 case ISD::UDIV: 2963 case ISD::UREM: 2964 // These operators require that their input be zero extended. 2965 Tmp1 = PromoteOp(Node->getOperand(0)); 2966 Tmp2 = PromoteOp(Node->getOperand(1)); 2967 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 2968 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2969 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 2970 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2971 break; 2972 2973 case ISD::SHL: 2974 Tmp1 = PromoteOp(Node->getOperand(0)); 2975 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 2976 break; 2977 case ISD::SRA: 2978 // The input value must be properly sign extended. 2979 Tmp1 = PromoteOp(Node->getOperand(0)); 2980 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2981 DAG.getValueType(VT)); 2982 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 2983 break; 2984 case ISD::SRL: 2985 // The input value must be properly zero extended. 2986 Tmp1 = PromoteOp(Node->getOperand(0)); 2987 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2988 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 2989 break; 2990 2991 case ISD::VAARG: 2992 Tmp1 = Node->getOperand(0); // Get the chain. 2993 Tmp2 = Node->getOperand(1); // Get the pointer. 2994 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 2995 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 2996 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 2997 } else { 2998 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2999 Node->getOperand(2)); 3000 // Increment the pointer, VAList, to the next vaarg 3001 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3002 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3003 TLI.getPointerTy())); 3004 // Store the incremented VAList to the legalized pointer 3005 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2, 3006 Node->getOperand(2)); 3007 // Load the actual argument out of the pointer VAList 3008 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, 3009 DAG.getSrcValue(0), VT); 3010 } 3011 // Remember that we legalized the chain. 3012 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3013 break; 3014 3015 case ISD::LOAD: 3016 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0), 3017 Node->getOperand(1), Node->getOperand(2), VT); 3018 // Remember that we legalized the chain. 3019 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3020 break; 3021 case ISD::SEXTLOAD: 3022 case ISD::ZEXTLOAD: 3023 case ISD::EXTLOAD: 3024 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0), 3025 Node->getOperand(1), Node->getOperand(2), 3026 cast<VTSDNode>(Node->getOperand(3))->getVT()); 3027 // Remember that we legalized the chain. 3028 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3029 break; 3030 case ISD::SELECT: 3031 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 3032 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 3033 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 3034 break; 3035 case ISD::SELECT_CC: 3036 Tmp2 = PromoteOp(Node->getOperand(2)); // True 3037 Tmp3 = PromoteOp(Node->getOperand(3)); // False 3038 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3039 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 3040 break; 3041 case ISD::BSWAP: 3042 Tmp1 = Node->getOperand(0); 3043 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3044 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3045 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3046 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT), 3047 TLI.getShiftAmountTy())); 3048 break; 3049 case ISD::CTPOP: 3050 case ISD::CTTZ: 3051 case ISD::CTLZ: 3052 // Zero extend the argument 3053 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 3054 // Perform the larger operation, then subtract if needed. 3055 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3056 switch(Node->getOpcode()) { 3057 case ISD::CTPOP: 3058 Result = Tmp1; 3059 break; 3060 case ISD::CTTZ: 3061 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3062 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3063 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 3064 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3065 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1); 3066 break; 3067 case ISD::CTLZ: 3068 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3069 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3070 DAG.getConstant(getSizeInBits(NVT) - 3071 getSizeInBits(VT), NVT)); 3072 break; 3073 } 3074 break; 3075 case ISD::VEXTRACT_VECTOR_ELT: 3076 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op)); 3077 break; 3078 case ISD::EXTRACT_VECTOR_ELT: 3079 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 3080 break; 3081 } 3082 3083 assert(Result.Val && "Didn't set a result!"); 3084 3085 // Make sure the result is itself legal. 3086 Result = LegalizeOp(Result); 3087 3088 // Remember that we promoted this! 3089 AddPromotedOperand(Op, Result); 3090 return Result; 3091} 3092 3093/// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a 3094/// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based 3095/// on the vector type. The return type of this matches the element type of the 3096/// vector, which may not be legal for the target. 3097SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) { 3098 // We know that operand #0 is the Vec vector. If the index is a constant 3099 // or if the invec is a supported hardware type, we can use it. Otherwise, 3100 // lower to a store then an indexed load. 3101 SDOperand Vec = Op.getOperand(0); 3102 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 3103 3104 SDNode *InVal = Vec.Val; 3105 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 3106 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 3107 3108 // Figure out if there is a Packed type corresponding to this Vector 3109 // type. If so, convert to the packed type. 3110 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3111 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 3112 // Turn this into a packed extract_vector_elt operation. 3113 Vec = PackVectorOp(Vec, TVT); 3114 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx); 3115 } else if (NumElems == 1) { 3116 // This must be an access of the only element. Return it. 3117 return PackVectorOp(Vec, EVT); 3118 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 3119 SDOperand Lo, Hi; 3120 SplitVectorOp(Vec, Lo, Hi); 3121 if (CIdx->getValue() < NumElems/2) { 3122 Vec = Lo; 3123 } else { 3124 Vec = Hi; 3125 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 3126 } 3127 3128 // It's now an extract from the appropriate high or low part. Recurse. 3129 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3130 return LowerVEXTRACT_VECTOR_ELT(Op); 3131 } else { 3132 // Variable index case for extract element. 3133 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!! 3134 assert(0 && "unimp!"); 3135 return SDOperand(); 3136 } 3137} 3138 3139/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 3140/// memory traffic. 3141SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 3142 SDOperand Vector = Op.getOperand(0); 3143 SDOperand Idx = Op.getOperand(1); 3144 3145 // If the target doesn't support this, store the value to a temporary 3146 // stack slot, then LOAD the scalar element back out. 3147 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType()); 3148 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3149 Vector, StackPtr, DAG.getSrcValue(NULL)); 3150 3151 // Add the offset to the index. 3152 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 3153 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 3154 DAG.getConstant(EltSize, Idx.getValueType())); 3155 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 3156 3157 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL)); 3158} 3159 3160 3161/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 3162/// with condition CC on the current target. This usually involves legalizing 3163/// or promoting the arguments. In the case where LHS and RHS must be expanded, 3164/// there may be no choice but to create a new SetCC node to represent the 3165/// legalized value of setcc lhs, rhs. In this case, the value is returned in 3166/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 3167void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 3168 SDOperand &RHS, 3169 SDOperand &CC) { 3170 SDOperand Tmp1, Tmp2, Result; 3171 3172 switch (getTypeAction(LHS.getValueType())) { 3173 case Legal: 3174 Tmp1 = LegalizeOp(LHS); // LHS 3175 Tmp2 = LegalizeOp(RHS); // RHS 3176 break; 3177 case Promote: 3178 Tmp1 = PromoteOp(LHS); // LHS 3179 Tmp2 = PromoteOp(RHS); // RHS 3180 3181 // If this is an FP compare, the operands have already been extended. 3182 if (MVT::isInteger(LHS.getValueType())) { 3183 MVT::ValueType VT = LHS.getValueType(); 3184 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3185 3186 // Otherwise, we have to insert explicit sign or zero extends. Note 3187 // that we could insert sign extends for ALL conditions, but zero extend 3188 // is cheaper on many machines (an AND instead of two shifts), so prefer 3189 // it. 3190 switch (cast<CondCodeSDNode>(CC)->get()) { 3191 default: assert(0 && "Unknown integer comparison!"); 3192 case ISD::SETEQ: 3193 case ISD::SETNE: 3194 case ISD::SETUGE: 3195 case ISD::SETUGT: 3196 case ISD::SETULE: 3197 case ISD::SETULT: 3198 // ALL of these operations will work if we either sign or zero extend 3199 // the operands (including the unsigned comparisons!). Zero extend is 3200 // usually a simpler/cheaper operation, so prefer it. 3201 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3202 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3203 break; 3204 case ISD::SETGE: 3205 case ISD::SETGT: 3206 case ISD::SETLT: 3207 case ISD::SETLE: 3208 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3209 DAG.getValueType(VT)); 3210 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3211 DAG.getValueType(VT)); 3212 break; 3213 } 3214 } 3215 break; 3216 case Expand: 3217 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 3218 ExpandOp(LHS, LHSLo, LHSHi); 3219 ExpandOp(RHS, RHSLo, RHSHi); 3220 switch (cast<CondCodeSDNode>(CC)->get()) { 3221 case ISD::SETEQ: 3222 case ISD::SETNE: 3223 if (RHSLo == RHSHi) 3224 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 3225 if (RHSCST->isAllOnesValue()) { 3226 // Comparison to -1. 3227 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 3228 Tmp2 = RHSLo; 3229 break; 3230 } 3231 3232 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 3233 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 3234 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 3235 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3236 break; 3237 default: 3238 // If this is a comparison of the sign bit, just look at the top part. 3239 // X > -1, x < 0 3240 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 3241 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 3242 CST->getValue() == 0) || // X < 0 3243 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 3244 CST->isAllOnesValue())) { // X > -1 3245 Tmp1 = LHSHi; 3246 Tmp2 = RHSHi; 3247 break; 3248 } 3249 3250 // FIXME: This generated code sucks. 3251 ISD::CondCode LowCC; 3252 switch (cast<CondCodeSDNode>(CC)->get()) { 3253 default: assert(0 && "Unknown integer setcc!"); 3254 case ISD::SETLT: 3255 case ISD::SETULT: LowCC = ISD::SETULT; break; 3256 case ISD::SETGT: 3257 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 3258 case ISD::SETLE: 3259 case ISD::SETULE: LowCC = ISD::SETULE; break; 3260 case ISD::SETGE: 3261 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 3262 } 3263 3264 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 3265 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 3266 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 3267 3268 // NOTE: on targets without efficient SELECT of bools, we can always use 3269 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 3270 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 3271 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC); 3272 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 3273 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 3274 Result, Tmp1, Tmp2)); 3275 Tmp1 = Result; 3276 Tmp2 = SDOperand(); 3277 } 3278 } 3279 LHS = Tmp1; 3280 RHS = Tmp2; 3281} 3282 3283/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 3284/// The resultant code need not be legal. Note that SrcOp is the input operand 3285/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 3286SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 3287 SDOperand SrcOp) { 3288 // Create the stack frame object. 3289 SDOperand FIPtr = CreateStackTemporary(DestVT); 3290 3291 // Emit a store to the stack slot. 3292 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3293 SrcOp, FIPtr, DAG.getSrcValue(NULL)); 3294 // Result is a load from the stack slot. 3295 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0)); 3296} 3297 3298SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 3299 // Create a vector sized/aligned stack slot, store the value to element #0, 3300 // then load the whole vector back out. 3301 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); 3302 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3303 Node->getOperand(0), StackPtr, 3304 DAG.getSrcValue(NULL)); 3305 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,DAG.getSrcValue(NULL)); 3306} 3307 3308 3309/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 3310/// support the operation, but do support the resultant packed vector type. 3311SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 3312 3313 // If the only non-undef value is the low element, turn this into a 3314 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 3315 unsigned NumElems = Node->getNumOperands(); 3316 bool isOnlyLowElement = true; 3317 SDOperand SplatValue = Node->getOperand(0); 3318 std::map<SDOperand, std::vector<unsigned> > Values; 3319 Values[SplatValue].push_back(0); 3320 bool isConstant = true; 3321 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 3322 SplatValue.getOpcode() != ISD::UNDEF) 3323 isConstant = false; 3324 3325 for (unsigned i = 1; i < NumElems; ++i) { 3326 SDOperand V = Node->getOperand(i); 3327 std::map<SDOperand, std::vector<unsigned> >::iterator I = Values.find(V); 3328 if (I != Values.end()) 3329 I->second.push_back(i); 3330 else 3331 Values[V].push_back(i); 3332 if (V.getOpcode() != ISD::UNDEF) 3333 isOnlyLowElement = false; 3334 if (SplatValue != V) 3335 SplatValue = SDOperand(0,0); 3336 3337 // If this isn't a constant element or an undef, we can't use a constant 3338 // pool load. 3339 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 3340 V.getOpcode() != ISD::UNDEF) 3341 isConstant = false; 3342 } 3343 3344 if (isOnlyLowElement) { 3345 // If the low element is an undef too, then this whole things is an undef. 3346 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 3347 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 3348 // Otherwise, turn this into a scalar_to_vector node. 3349 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 3350 Node->getOperand(0)); 3351 } 3352 3353 // If all elements are constants, create a load from the constant pool. 3354 if (isConstant) { 3355 MVT::ValueType VT = Node->getValueType(0); 3356 const Type *OpNTy = 3357 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 3358 std::vector<Constant*> CV; 3359 for (unsigned i = 0, e = NumElems; i != e; ++i) { 3360 if (ConstantFPSDNode *V = 3361 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 3362 CV.push_back(ConstantFP::get(OpNTy, V->getValue())); 3363 } else if (ConstantSDNode *V = 3364 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 3365 CV.push_back(ConstantUInt::get(OpNTy, V->getValue())); 3366 } else { 3367 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 3368 CV.push_back(UndefValue::get(OpNTy)); 3369 } 3370 } 3371 Constant *CP = ConstantPacked::get(CV); 3372 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 3373 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 3374 DAG.getSrcValue(NULL)); 3375 } 3376 3377 if (SplatValue.Val) { // Splat of one value? 3378 // Build the shuffle constant vector: <0, 0, 0, 0> 3379 MVT::ValueType MaskVT = 3380 MVT::getIntVectorWithNumElements(NumElems); 3381 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT)); 3382 std::vector<SDOperand> ZeroVec(NumElems, Zero); 3383 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec); 3384 3385 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 3386 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 3387 // Get the splatted value into the low element of a vector register. 3388 SDOperand LowValVec = 3389 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 3390 3391 // Return shuffle(LowValVec, undef, <0,0,0,0>) 3392 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 3393 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 3394 SplatMask); 3395 } 3396 } 3397 3398 // If there are only two unique elements, we may be able to turn this into a 3399 // vector shuffle. 3400 if (Values.size() == 2) { 3401 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 3402 MVT::ValueType MaskVT = 3403 MVT::getIntVectorWithNumElements(NumElems); 3404 std::vector<SDOperand> MaskVec(NumElems); 3405 unsigned i = 0; 3406 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 3407 E = Values.end(); I != E; ++I) { 3408 for (std::vector<unsigned>::iterator II = I->second.begin(), 3409 EE = I->second.end(); II != EE; ++II) 3410 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT)); 3411 i += NumElems; 3412 } 3413 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec); 3414 3415 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 3416 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 3417 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 3418 std::vector<SDOperand> Ops; 3419 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 3420 E = Values.end(); I != E; ++I) { 3421 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 3422 I->first); 3423 Ops.push_back(Op); 3424 } 3425 Ops.push_back(ShuffleMask); 3426 3427 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 3428 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops); 3429 } 3430 } 3431 3432 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 3433 // aligned object on the stack, store each element into it, then load 3434 // the result as a vector. 3435 MVT::ValueType VT = Node->getValueType(0); 3436 // Create the stack frame object. 3437 SDOperand FIPtr = CreateStackTemporary(VT); 3438 3439 // Emit a store of each element to the stack slot. 3440 std::vector<SDOperand> Stores; 3441 unsigned TypeByteSize = 3442 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 3443 unsigned VectorSize = MVT::getSizeInBits(VT)/8; 3444 // Store (in the right endianness) the elements to memory. 3445 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3446 // Ignore undef elements. 3447 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3448 3449 unsigned Offset = TypeByteSize*i; 3450 3451 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 3452 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 3453 3454 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3455 Node->getOperand(i), Idx, 3456 DAG.getSrcValue(NULL))); 3457 } 3458 3459 SDOperand StoreChain; 3460 if (!Stores.empty()) // Not all undef elements? 3461 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 3462 else 3463 StoreChain = DAG.getEntryNode(); 3464 3465 // Result is a load from the stack slot. 3466 return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0)); 3467} 3468 3469/// CreateStackTemporary - Create a stack temporary, suitable for holding the 3470/// specified value type. 3471SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) { 3472 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 3473 unsigned ByteSize = MVT::getSizeInBits(VT)/8; 3474 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize); 3475 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 3476} 3477 3478void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 3479 SDOperand Op, SDOperand Amt, 3480 SDOperand &Lo, SDOperand &Hi) { 3481 // Expand the subcomponents. 3482 SDOperand LHSL, LHSH; 3483 ExpandOp(Op, LHSL, LHSH); 3484 3485 std::vector<SDOperand> Ops; 3486 Ops.push_back(LHSL); 3487 Ops.push_back(LHSH); 3488 Ops.push_back(Amt); 3489 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 3490 Lo = DAG.getNode(NodeOp, VTs, Ops); 3491 Hi = Lo.getValue(1); 3492} 3493 3494 3495/// ExpandShift - Try to find a clever way to expand this shift operation out to 3496/// smaller elements. If we can't find a way that is more efficient than a 3497/// libcall on this target, return false. Otherwise, return true with the 3498/// low-parts expanded into Lo and Hi. 3499bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 3500 SDOperand &Lo, SDOperand &Hi) { 3501 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 3502 "This is not a shift!"); 3503 3504 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 3505 SDOperand ShAmt = LegalizeOp(Amt); 3506 MVT::ValueType ShTy = ShAmt.getValueType(); 3507 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 3508 unsigned NVTBits = MVT::getSizeInBits(NVT); 3509 3510 // Handle the case when Amt is an immediate. Other cases are currently broken 3511 // and are disabled. 3512 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 3513 unsigned Cst = CN->getValue(); 3514 // Expand the incoming operand to be shifted, so that we have its parts 3515 SDOperand InL, InH; 3516 ExpandOp(Op, InL, InH); 3517 switch(Opc) { 3518 case ISD::SHL: 3519 if (Cst > VTBits) { 3520 Lo = DAG.getConstant(0, NVT); 3521 Hi = DAG.getConstant(0, NVT); 3522 } else if (Cst > NVTBits) { 3523 Lo = DAG.getConstant(0, NVT); 3524 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 3525 } else if (Cst == NVTBits) { 3526 Lo = DAG.getConstant(0, NVT); 3527 Hi = InL; 3528 } else { 3529 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 3530 Hi = DAG.getNode(ISD::OR, NVT, 3531 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 3532 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 3533 } 3534 return true; 3535 case ISD::SRL: 3536 if (Cst > VTBits) { 3537 Lo = DAG.getConstant(0, NVT); 3538 Hi = DAG.getConstant(0, NVT); 3539 } else if (Cst > NVTBits) { 3540 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 3541 Hi = DAG.getConstant(0, NVT); 3542 } else if (Cst == NVTBits) { 3543 Lo = InH; 3544 Hi = DAG.getConstant(0, NVT); 3545 } else { 3546 Lo = DAG.getNode(ISD::OR, NVT, 3547 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3548 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3549 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 3550 } 3551 return true; 3552 case ISD::SRA: 3553 if (Cst > VTBits) { 3554 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 3555 DAG.getConstant(NVTBits-1, ShTy)); 3556 } else if (Cst > NVTBits) { 3557 Lo = DAG.getNode(ISD::SRA, NVT, InH, 3558 DAG.getConstant(Cst-NVTBits, ShTy)); 3559 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3560 DAG.getConstant(NVTBits-1, ShTy)); 3561 } else if (Cst == NVTBits) { 3562 Lo = InH; 3563 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3564 DAG.getConstant(NVTBits-1, ShTy)); 3565 } else { 3566 Lo = DAG.getNode(ISD::OR, NVT, 3567 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3568 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3569 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 3570 } 3571 return true; 3572 } 3573 } 3574 return false; 3575} 3576 3577 3578// ExpandLibCall - Expand a node into a call to a libcall. If the result value 3579// does not fit into a register, return the lo part and set the hi part to the 3580// by-reg argument. If it does fit into a single register, return the result 3581// and leave the Hi part unset. 3582SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 3583 SDOperand &Hi) { 3584 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 3585 // The input chain to this libcall is the entry node of the function. 3586 // Legalizing the call will automatically add the previous call to the 3587 // dependence. 3588 SDOperand InChain = DAG.getEntryNode(); 3589 3590 TargetLowering::ArgListTy Args; 3591 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3592 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 3593 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 3594 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 3595 } 3596 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 3597 3598 // Splice the libcall in wherever FindInputOutputChains tells us to. 3599 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 3600 std::pair<SDOperand,SDOperand> CallInfo = 3601 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 3602 Callee, Args, DAG); 3603 3604 // Legalize the call sequence, starting with the chain. This will advance 3605 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 3606 // was added by LowerCallTo (guaranteeing proper serialization of calls). 3607 LegalizeOp(CallInfo.second); 3608 SDOperand Result; 3609 switch (getTypeAction(CallInfo.first.getValueType())) { 3610 default: assert(0 && "Unknown thing"); 3611 case Legal: 3612 Result = CallInfo.first; 3613 break; 3614 case Expand: 3615 ExpandOp(CallInfo.first, Result, Hi); 3616 break; 3617 } 3618 return Result; 3619} 3620 3621 3622/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 3623/// destination type is legal. 3624SDOperand SelectionDAGLegalize:: 3625ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 3626 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 3627 assert(getTypeAction(Source.getValueType()) == Expand && 3628 "This is not an expansion!"); 3629 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 3630 3631 if (!isSigned) { 3632 assert(Source.getValueType() == MVT::i64 && 3633 "This only works for 64-bit -> FP"); 3634 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 3635 // incoming integer is set. To handle this, we dynamically test to see if 3636 // it is set, and, if so, add a fudge factor. 3637 SDOperand Lo, Hi; 3638 ExpandOp(Source, Lo, Hi); 3639 3640 // If this is unsigned, and not supported, first perform the conversion to 3641 // signed, then adjust the result if the sign bit is set. 3642 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 3643 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 3644 3645 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 3646 DAG.getConstant(0, Hi.getValueType()), 3647 ISD::SETLT); 3648 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3649 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3650 SignSet, Four, Zero); 3651 uint64_t FF = 0x5f800000ULL; 3652 if (TLI.isLittleEndian()) FF <<= 32; 3653 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3654 3655 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3656 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3657 SDOperand FudgeInReg; 3658 if (DestTy == MVT::f32) 3659 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3660 DAG.getSrcValue(NULL)); 3661 else { 3662 assert(DestTy == MVT::f64 && "Unexpected conversion"); 3663 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 3664 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 3665 } 3666 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 3667 } 3668 3669 // Check to see if the target has a custom way to lower this. If so, use it. 3670 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 3671 default: assert(0 && "This action not implemented for this operation!"); 3672 case TargetLowering::Legal: 3673 case TargetLowering::Expand: 3674 break; // This case is handled below. 3675 case TargetLowering::Custom: { 3676 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 3677 Source), DAG); 3678 if (NV.Val) 3679 return LegalizeOp(NV); 3680 break; // The target decided this was legal after all 3681 } 3682 } 3683 3684 // Expand the source, then glue it back together for the call. We must expand 3685 // the source in case it is shared (this pass of legalize must traverse it). 3686 SDOperand SrcLo, SrcHi; 3687 ExpandOp(Source, SrcLo, SrcHi); 3688 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3689 3690 const char *FnName = 0; 3691 if (DestTy == MVT::f32) 3692 FnName = "__floatdisf"; 3693 else { 3694 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3695 FnName = "__floatdidf"; 3696 } 3697 3698 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 3699 SDOperand UnusedHiPart; 3700 return ExpandLibCall(FnName, Source.Val, UnusedHiPart); 3701} 3702 3703/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 3704/// INT_TO_FP operation of the specified operand when the target requests that 3705/// we expand it. At this point, we know that the result and operand types are 3706/// legal for the target. 3707SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 3708 SDOperand Op0, 3709 MVT::ValueType DestVT) { 3710 if (Op0.getValueType() == MVT::i32) { 3711 // simple 32-bit [signed|unsigned] integer to float/double expansion 3712 3713 // get the stack frame index of a 8 byte buffer 3714 MachineFunction &MF = DAG.getMachineFunction(); 3715 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 3716 // get address of 8 byte buffer 3717 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3718 // word offset constant for Hi/Lo address computation 3719 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 3720 // set up Hi and Lo (into buffer) address based on endian 3721 SDOperand Hi = StackSlot; 3722 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 3723 if (TLI.isLittleEndian()) 3724 std::swap(Hi, Lo); 3725 3726 // if signed map to unsigned space 3727 SDOperand Op0Mapped; 3728 if (isSigned) { 3729 // constant used to invert sign bit (signed to unsigned mapping) 3730 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 3731 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 3732 } else { 3733 Op0Mapped = Op0; 3734 } 3735 // store the lo of the constructed double - based on integer input 3736 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3737 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 3738 // initial hi portion of constructed double 3739 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 3740 // store the hi of the constructed double - biased exponent 3741 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 3742 InitialHi, Hi, DAG.getSrcValue(NULL)); 3743 // load the constructed double 3744 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 3745 DAG.getSrcValue(NULL)); 3746 // FP constant to bias correct the final result 3747 SDOperand Bias = DAG.getConstantFP(isSigned ? 3748 BitsToDouble(0x4330000080000000ULL) 3749 : BitsToDouble(0x4330000000000000ULL), 3750 MVT::f64); 3751 // subtract the bias 3752 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 3753 // final result 3754 SDOperand Result; 3755 // handle final rounding 3756 if (DestVT == MVT::f64) { 3757 // do nothing 3758 Result = Sub; 3759 } else { 3760 // if f32 then cast to f32 3761 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 3762 } 3763 return Result; 3764 } 3765 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 3766 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 3767 3768 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 3769 DAG.getConstant(0, Op0.getValueType()), 3770 ISD::SETLT); 3771 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3772 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3773 SignSet, Four, Zero); 3774 3775 // If the sign bit of the integer is set, the large number will be treated 3776 // as a negative number. To counteract this, the dynamic code adds an 3777 // offset depending on the data type. 3778 uint64_t FF; 3779 switch (Op0.getValueType()) { 3780 default: assert(0 && "Unsupported integer type!"); 3781 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 3782 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 3783 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 3784 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 3785 } 3786 if (TLI.isLittleEndian()) FF <<= 32; 3787 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3788 3789 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3790 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3791 SDOperand FudgeInReg; 3792 if (DestVT == MVT::f32) 3793 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3794 DAG.getSrcValue(NULL)); 3795 else { 3796 assert(DestVT == MVT::f64 && "Unexpected conversion"); 3797 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 3798 DAG.getEntryNode(), CPIdx, 3799 DAG.getSrcValue(NULL), MVT::f32)); 3800 } 3801 3802 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 3803} 3804 3805/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 3806/// *INT_TO_FP operation of the specified operand when the target requests that 3807/// we promote it. At this point, we know that the result and operand types are 3808/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 3809/// operation that takes a larger input. 3810SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 3811 MVT::ValueType DestVT, 3812 bool isSigned) { 3813 // First step, figure out the appropriate *INT_TO_FP operation to use. 3814 MVT::ValueType NewInTy = LegalOp.getValueType(); 3815 3816 unsigned OpToUse = 0; 3817 3818 // Scan for the appropriate larger type to use. 3819 while (1) { 3820 NewInTy = (MVT::ValueType)(NewInTy+1); 3821 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 3822 3823 // If the target supports SINT_TO_FP of this type, use it. 3824 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 3825 default: break; 3826 case TargetLowering::Legal: 3827 if (!TLI.isTypeLegal(NewInTy)) 3828 break; // Can't use this datatype. 3829 // FALL THROUGH. 3830 case TargetLowering::Custom: 3831 OpToUse = ISD::SINT_TO_FP; 3832 break; 3833 } 3834 if (OpToUse) break; 3835 if (isSigned) continue; 3836 3837 // If the target supports UINT_TO_FP of this type, use it. 3838 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 3839 default: break; 3840 case TargetLowering::Legal: 3841 if (!TLI.isTypeLegal(NewInTy)) 3842 break; // Can't use this datatype. 3843 // FALL THROUGH. 3844 case TargetLowering::Custom: 3845 OpToUse = ISD::UINT_TO_FP; 3846 break; 3847 } 3848 if (OpToUse) break; 3849 3850 // Otherwise, try a larger type. 3851 } 3852 3853 // Okay, we found the operation and type to use. Zero extend our input to the 3854 // desired type then run the operation on it. 3855 return DAG.getNode(OpToUse, DestVT, 3856 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 3857 NewInTy, LegalOp)); 3858} 3859 3860/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 3861/// FP_TO_*INT operation of the specified operand when the target requests that 3862/// we promote it. At this point, we know that the result and operand types are 3863/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 3864/// operation that returns a larger result. 3865SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 3866 MVT::ValueType DestVT, 3867 bool isSigned) { 3868 // First step, figure out the appropriate FP_TO*INT operation to use. 3869 MVT::ValueType NewOutTy = DestVT; 3870 3871 unsigned OpToUse = 0; 3872 3873 // Scan for the appropriate larger type to use. 3874 while (1) { 3875 NewOutTy = (MVT::ValueType)(NewOutTy+1); 3876 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 3877 3878 // If the target supports FP_TO_SINT returning this type, use it. 3879 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 3880 default: break; 3881 case TargetLowering::Legal: 3882 if (!TLI.isTypeLegal(NewOutTy)) 3883 break; // Can't use this datatype. 3884 // FALL THROUGH. 3885 case TargetLowering::Custom: 3886 OpToUse = ISD::FP_TO_SINT; 3887 break; 3888 } 3889 if (OpToUse) break; 3890 3891 // If the target supports FP_TO_UINT of this type, use it. 3892 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 3893 default: break; 3894 case TargetLowering::Legal: 3895 if (!TLI.isTypeLegal(NewOutTy)) 3896 break; // Can't use this datatype. 3897 // FALL THROUGH. 3898 case TargetLowering::Custom: 3899 OpToUse = ISD::FP_TO_UINT; 3900 break; 3901 } 3902 if (OpToUse) break; 3903 3904 // Otherwise, try a larger type. 3905 } 3906 3907 // Okay, we found the operation and type to use. Truncate the result of the 3908 // extended FP_TO_*INT operation to the desired size. 3909 return DAG.getNode(ISD::TRUNCATE, DestVT, 3910 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 3911} 3912 3913/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 3914/// 3915SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 3916 MVT::ValueType VT = Op.getValueType(); 3917 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 3918 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 3919 switch (VT) { 3920 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 3921 case MVT::i16: 3922 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 3923 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 3924 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 3925 case MVT::i32: 3926 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 3927 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 3928 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 3929 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 3930 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 3931 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 3932 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 3933 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 3934 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 3935 case MVT::i64: 3936 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 3937 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 3938 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 3939 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 3940 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 3941 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 3942 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 3943 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 3944 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 3945 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 3946 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 3947 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 3948 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 3949 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 3950 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 3951 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 3952 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 3953 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 3954 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 3955 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 3956 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 3957 } 3958} 3959 3960/// ExpandBitCount - Expand the specified bitcount instruction into operations. 3961/// 3962SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 3963 switch (Opc) { 3964 default: assert(0 && "Cannot expand this yet!"); 3965 case ISD::CTPOP: { 3966 static const uint64_t mask[6] = { 3967 0x5555555555555555ULL, 0x3333333333333333ULL, 3968 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 3969 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 3970 }; 3971 MVT::ValueType VT = Op.getValueType(); 3972 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 3973 unsigned len = getSizeInBits(VT); 3974 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 3975 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 3976 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 3977 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 3978 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 3979 DAG.getNode(ISD::AND, VT, 3980 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 3981 } 3982 return Op; 3983 } 3984 case ISD::CTLZ: { 3985 // for now, we do this: 3986 // x = x | (x >> 1); 3987 // x = x | (x >> 2); 3988 // ... 3989 // x = x | (x >>16); 3990 // x = x | (x >>32); // for 64-bit input 3991 // return popcount(~x); 3992 // 3993 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 3994 MVT::ValueType VT = Op.getValueType(); 3995 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 3996 unsigned len = getSizeInBits(VT); 3997 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 3998 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 3999 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 4000 } 4001 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 4002 return DAG.getNode(ISD::CTPOP, VT, Op); 4003 } 4004 case ISD::CTTZ: { 4005 // for now, we use: { return popcount(~x & (x - 1)); } 4006 // unless the target has ctlz but not ctpop, in which case we use: 4007 // { return 32 - nlz(~x & (x-1)); } 4008 // see also http://www.hackersdelight.org/HDcode/ntz.cc 4009 MVT::ValueType VT = Op.getValueType(); 4010 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 4011 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 4012 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 4013 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 4014 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 4015 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 4016 TLI.isOperationLegal(ISD::CTLZ, VT)) 4017 return DAG.getNode(ISD::SUB, VT, 4018 DAG.getConstant(getSizeInBits(VT), VT), 4019 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 4020 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 4021 } 4022 } 4023} 4024 4025 4026/// ExpandOp - Expand the specified SDOperand into its two component pieces 4027/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 4028/// LegalizeNodes map is filled in for any results that are not expanded, the 4029/// ExpandedNodes map is filled in for any results that are expanded, and the 4030/// Lo/Hi values are returned. 4031void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 4032 MVT::ValueType VT = Op.getValueType(); 4033 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4034 SDNode *Node = Op.Val; 4035 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 4036 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 4037 "Cannot expand FP values!"); 4038 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 4039 "Cannot expand to FP value or to larger int value!"); 4040 4041 // See if we already expanded it. 4042 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 4043 = ExpandedNodes.find(Op); 4044 if (I != ExpandedNodes.end()) { 4045 Lo = I->second.first; 4046 Hi = I->second.second; 4047 return; 4048 } 4049 4050 switch (Node->getOpcode()) { 4051 case ISD::CopyFromReg: 4052 assert(0 && "CopyFromReg must be legal!"); 4053 default: 4054 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 4055 assert(0 && "Do not know how to expand this operator!"); 4056 abort(); 4057 case ISD::UNDEF: 4058 Lo = DAG.getNode(ISD::UNDEF, NVT); 4059 Hi = DAG.getNode(ISD::UNDEF, NVT); 4060 break; 4061 case ISD::Constant: { 4062 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 4063 Lo = DAG.getConstant(Cst, NVT); 4064 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 4065 break; 4066 } 4067 case ISD::BUILD_PAIR: 4068 // Return the operands. 4069 Lo = Node->getOperand(0); 4070 Hi = Node->getOperand(1); 4071 break; 4072 4073 case ISD::SIGN_EXTEND_INREG: 4074 ExpandOp(Node->getOperand(0), Lo, Hi); 4075 // Sign extend the lo-part. 4076 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4077 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 4078 TLI.getShiftAmountTy())); 4079 // sext_inreg the low part if needed. 4080 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 4081 break; 4082 4083 case ISD::BSWAP: { 4084 ExpandOp(Node->getOperand(0), Lo, Hi); 4085 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 4086 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 4087 Lo = TempLo; 4088 break; 4089 } 4090 4091 case ISD::CTPOP: 4092 ExpandOp(Node->getOperand(0), Lo, Hi); 4093 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 4094 DAG.getNode(ISD::CTPOP, NVT, Lo), 4095 DAG.getNode(ISD::CTPOP, NVT, Hi)); 4096 Hi = DAG.getConstant(0, NVT); 4097 break; 4098 4099 case ISD::CTLZ: { 4100 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 4101 ExpandOp(Node->getOperand(0), Lo, Hi); 4102 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4103 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 4104 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 4105 ISD::SETNE); 4106 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 4107 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 4108 4109 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 4110 Hi = DAG.getConstant(0, NVT); 4111 break; 4112 } 4113 4114 case ISD::CTTZ: { 4115 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 4116 ExpandOp(Node->getOperand(0), Lo, Hi); 4117 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4118 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 4119 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 4120 ISD::SETNE); 4121 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 4122 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 4123 4124 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 4125 Hi = DAG.getConstant(0, NVT); 4126 break; 4127 } 4128 4129 case ISD::VAARG: { 4130 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 4131 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 4132 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 4133 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 4134 4135 // Remember that we legalized the chain. 4136 Hi = LegalizeOp(Hi); 4137 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 4138 if (!TLI.isLittleEndian()) 4139 std::swap(Lo, Hi); 4140 break; 4141 } 4142 4143 case ISD::LOAD: { 4144 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 4145 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 4146 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 4147 4148 // Increment the pointer to the other half. 4149 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 4150 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4151 getIntPtrConstant(IncrementSize)); 4152 // FIXME: This creates a bogus srcvalue! 4153 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 4154 4155 // Build a factor node to remember that this load is independent of the 4156 // other one. 4157 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 4158 Hi.getValue(1)); 4159 4160 // Remember that we legalized the chain. 4161 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 4162 if (!TLI.isLittleEndian()) 4163 std::swap(Lo, Hi); 4164 break; 4165 } 4166 case ISD::AND: 4167 case ISD::OR: 4168 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 4169 SDOperand LL, LH, RL, RH; 4170 ExpandOp(Node->getOperand(0), LL, LH); 4171 ExpandOp(Node->getOperand(1), RL, RH); 4172 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 4173 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 4174 break; 4175 } 4176 case ISD::SELECT: { 4177 SDOperand LL, LH, RL, RH; 4178 ExpandOp(Node->getOperand(1), LL, LH); 4179 ExpandOp(Node->getOperand(2), RL, RH); 4180 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 4181 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 4182 break; 4183 } 4184 case ISD::SELECT_CC: { 4185 SDOperand TL, TH, FL, FH; 4186 ExpandOp(Node->getOperand(2), TL, TH); 4187 ExpandOp(Node->getOperand(3), FL, FH); 4188 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4189 Node->getOperand(1), TL, FL, Node->getOperand(4)); 4190 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4191 Node->getOperand(1), TH, FH, Node->getOperand(4)); 4192 break; 4193 } 4194 case ISD::SEXTLOAD: { 4195 SDOperand Chain = Node->getOperand(0); 4196 SDOperand Ptr = Node->getOperand(1); 4197 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4198 4199 if (EVT == NVT) 4200 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 4201 else 4202 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 4203 EVT); 4204 4205 // Remember that we legalized the chain. 4206 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4207 4208 // The high part is obtained by SRA'ing all but one of the bits of the lo 4209 // part. 4210 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4211 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 4212 TLI.getShiftAmountTy())); 4213 break; 4214 } 4215 case ISD::ZEXTLOAD: { 4216 SDOperand Chain = Node->getOperand(0); 4217 SDOperand Ptr = Node->getOperand(1); 4218 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4219 4220 if (EVT == NVT) 4221 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 4222 else 4223 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 4224 EVT); 4225 4226 // Remember that we legalized the chain. 4227 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4228 4229 // The high part is just a zero. 4230 Hi = DAG.getConstant(0, NVT); 4231 break; 4232 } 4233 case ISD::EXTLOAD: { 4234 SDOperand Chain = Node->getOperand(0); 4235 SDOperand Ptr = Node->getOperand(1); 4236 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4237 4238 if (EVT == NVT) 4239 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 4240 else 4241 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 4242 EVT); 4243 4244 // Remember that we legalized the chain. 4245 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4246 4247 // The high part is undefined. 4248 Hi = DAG.getNode(ISD::UNDEF, NVT); 4249 break; 4250 } 4251 case ISD::ANY_EXTEND: 4252 // The low part is any extension of the input (which degenerates to a copy). 4253 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 4254 // The high part is undefined. 4255 Hi = DAG.getNode(ISD::UNDEF, NVT); 4256 break; 4257 case ISD::SIGN_EXTEND: { 4258 // The low part is just a sign extension of the input (which degenerates to 4259 // a copy). 4260 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 4261 4262 // The high part is obtained by SRA'ing all but one of the bits of the lo 4263 // part. 4264 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4265 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4266 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 4267 break; 4268 } 4269 case ISD::ZERO_EXTEND: 4270 // The low part is just a zero extension of the input (which degenerates to 4271 // a copy). 4272 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4273 4274 // The high part is just a zero. 4275 Hi = DAG.getConstant(0, NVT); 4276 break; 4277 4278 case ISD::BIT_CONVERT: { 4279 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0), 4280 Node->getOperand(0)); 4281 ExpandOp(Tmp, Lo, Hi); 4282 break; 4283 } 4284 4285 case ISD::READCYCLECOUNTER: 4286 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 4287 TargetLowering::Custom && 4288 "Must custom expand ReadCycleCounter"); 4289 Lo = TLI.LowerOperation(Op, DAG); 4290 assert(Lo.Val && "Node must be custom expanded!"); 4291 Hi = Lo.getValue(1); 4292 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 4293 LegalizeOp(Lo.getValue(2))); 4294 break; 4295 4296 // These operators cannot be expanded directly, emit them as calls to 4297 // library functions. 4298 case ISD::FP_TO_SINT: 4299 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 4300 SDOperand Op; 4301 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4302 case Expand: assert(0 && "cannot expand FP!"); 4303 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 4304 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 4305 } 4306 4307 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 4308 4309 // Now that the custom expander is done, expand the result, which is still 4310 // VT. 4311 if (Op.Val) { 4312 ExpandOp(Op, Lo, Hi); 4313 break; 4314 } 4315 } 4316 4317 if (Node->getOperand(0).getValueType() == MVT::f32) 4318 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 4319 else 4320 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 4321 break; 4322 4323 case ISD::FP_TO_UINT: 4324 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 4325 SDOperand Op; 4326 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4327 case Expand: assert(0 && "cannot expand FP!"); 4328 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 4329 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 4330 } 4331 4332 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 4333 4334 // Now that the custom expander is done, expand the result. 4335 if (Op.Val) { 4336 ExpandOp(Op, Lo, Hi); 4337 break; 4338 } 4339 } 4340 4341 if (Node->getOperand(0).getValueType() == MVT::f32) 4342 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 4343 else 4344 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 4345 break; 4346 4347 case ISD::SHL: { 4348 // If the target wants custom lowering, do so. 4349 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4350 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 4351 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 4352 Op = TLI.LowerOperation(Op, DAG); 4353 if (Op.Val) { 4354 // Now that the custom expander is done, expand the result, which is 4355 // still VT. 4356 ExpandOp(Op, Lo, Hi); 4357 break; 4358 } 4359 } 4360 4361 // If we can emit an efficient shift operation, do so now. 4362 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4363 break; 4364 4365 // If this target supports SHL_PARTS, use it. 4366 TargetLowering::LegalizeAction Action = 4367 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 4368 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4369 Action == TargetLowering::Custom) { 4370 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4371 break; 4372 } 4373 4374 // Otherwise, emit a libcall. 4375 Lo = ExpandLibCall("__ashldi3", Node, Hi); 4376 break; 4377 } 4378 4379 case ISD::SRA: { 4380 // If the target wants custom lowering, do so. 4381 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4382 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 4383 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 4384 Op = TLI.LowerOperation(Op, DAG); 4385 if (Op.Val) { 4386 // Now that the custom expander is done, expand the result, which is 4387 // still VT. 4388 ExpandOp(Op, Lo, Hi); 4389 break; 4390 } 4391 } 4392 4393 // If we can emit an efficient shift operation, do so now. 4394 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4395 break; 4396 4397 // If this target supports SRA_PARTS, use it. 4398 TargetLowering::LegalizeAction Action = 4399 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 4400 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4401 Action == TargetLowering::Custom) { 4402 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4403 break; 4404 } 4405 4406 // Otherwise, emit a libcall. 4407 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 4408 break; 4409 } 4410 4411 case ISD::SRL: { 4412 // If the target wants custom lowering, do so. 4413 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4414 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 4415 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 4416 Op = TLI.LowerOperation(Op, DAG); 4417 if (Op.Val) { 4418 // Now that the custom expander is done, expand the result, which is 4419 // still VT. 4420 ExpandOp(Op, Lo, Hi); 4421 break; 4422 } 4423 } 4424 4425 // If we can emit an efficient shift operation, do so now. 4426 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4427 break; 4428 4429 // If this target supports SRL_PARTS, use it. 4430 TargetLowering::LegalizeAction Action = 4431 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 4432 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4433 Action == TargetLowering::Custom) { 4434 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4435 break; 4436 } 4437 4438 // Otherwise, emit a libcall. 4439 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 4440 break; 4441 } 4442 4443 case ISD::ADD: 4444 case ISD::SUB: { 4445 // If the target wants to custom expand this, let them. 4446 if (TLI.getOperationAction(Node->getOpcode(), VT) == 4447 TargetLowering::Custom) { 4448 Op = TLI.LowerOperation(Op, DAG); 4449 if (Op.Val) { 4450 ExpandOp(Op, Lo, Hi); 4451 break; 4452 } 4453 } 4454 4455 // Expand the subcomponents. 4456 SDOperand LHSL, LHSH, RHSL, RHSH; 4457 ExpandOp(Node->getOperand(0), LHSL, LHSH); 4458 ExpandOp(Node->getOperand(1), RHSL, RHSH); 4459 std::vector<MVT::ValueType> VTs; 4460 std::vector<SDOperand> LoOps, HiOps; 4461 VTs.push_back(LHSL.getValueType()); 4462 VTs.push_back(MVT::Flag); 4463 LoOps.push_back(LHSL); 4464 LoOps.push_back(RHSL); 4465 HiOps.push_back(LHSH); 4466 HiOps.push_back(RHSH); 4467 if (Node->getOpcode() == ISD::ADD) { 4468 Lo = DAG.getNode(ISD::ADDC, VTs, LoOps); 4469 HiOps.push_back(Lo.getValue(1)); 4470 Hi = DAG.getNode(ISD::ADDE, VTs, HiOps); 4471 } else { 4472 Lo = DAG.getNode(ISD::SUBC, VTs, LoOps); 4473 HiOps.push_back(Lo.getValue(1)); 4474 Hi = DAG.getNode(ISD::SUBE, VTs, HiOps); 4475 } 4476 break; 4477 } 4478 case ISD::MUL: { 4479 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 4480 SDOperand LL, LH, RL, RH; 4481 ExpandOp(Node->getOperand(0), LL, LH); 4482 ExpandOp(Node->getOperand(1), RL, RH); 4483 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 4484 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 4485 // extended the sign bit of the low half through the upper half, and if so 4486 // emit a MULHS instead of the alternate sequence that is valid for any 4487 // i64 x i64 multiply. 4488 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 4489 // is RH an extension of the sign bit of RL? 4490 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 4491 RH.getOperand(1).getOpcode() == ISD::Constant && 4492 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 4493 // is LH an extension of the sign bit of LL? 4494 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 4495 LH.getOperand(1).getOpcode() == ISD::Constant && 4496 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 4497 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 4498 } else { 4499 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 4500 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 4501 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 4502 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 4503 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 4504 } 4505 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 4506 } else { 4507 Lo = ExpandLibCall("__muldi3" , Node, Hi); 4508 } 4509 break; 4510 } 4511 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 4512 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 4513 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 4514 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 4515 } 4516 4517 // Make sure the resultant values have been legalized themselves, unless this 4518 // is a type that requires multi-step expansion. 4519 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 4520 Lo = LegalizeOp(Lo); 4521 Hi = LegalizeOp(Hi); 4522 } 4523 4524 // Remember in a map if the values will be reused later. 4525 bool isNew = 4526 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 4527 assert(isNew && "Value already expanded?!?"); 4528} 4529 4530/// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 4531/// two smaller values of MVT::Vector type. 4532void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 4533 SDOperand &Hi) { 4534 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!"); 4535 SDNode *Node = Op.Val; 4536 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue(); 4537 assert(NumElements > 1 && "Cannot split a single element vector!"); 4538 unsigned NewNumElts = NumElements/2; 4539 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32); 4540 SDOperand TypeNode = *(Node->op_end()-1); 4541 4542 // See if we already split it. 4543 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 4544 = SplitNodes.find(Op); 4545 if (I != SplitNodes.end()) { 4546 Lo = I->second.first; 4547 Hi = I->second.second; 4548 return; 4549 } 4550 4551 switch (Node->getOpcode()) { 4552 default: Node->dump(); assert(0 && "Unknown vector operation!"); 4553 case ISD::VBUILD_VECTOR: { 4554 std::vector<SDOperand> LoOps(Node->op_begin(), Node->op_begin()+NewNumElts); 4555 LoOps.push_back(NewNumEltsNode); 4556 LoOps.push_back(TypeNode); 4557 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps); 4558 4559 std::vector<SDOperand> HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2); 4560 HiOps.push_back(NewNumEltsNode); 4561 HiOps.push_back(TypeNode); 4562 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps); 4563 break; 4564 } 4565 case ISD::VADD: 4566 case ISD::VSUB: 4567 case ISD::VMUL: 4568 case ISD::VSDIV: 4569 case ISD::VUDIV: 4570 case ISD::VAND: 4571 case ISD::VOR: 4572 case ISD::VXOR: { 4573 SDOperand LL, LH, RL, RH; 4574 SplitVectorOp(Node->getOperand(0), LL, LH); 4575 SplitVectorOp(Node->getOperand(1), RL, RH); 4576 4577 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, 4578 NewNumEltsNode, TypeNode); 4579 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, 4580 NewNumEltsNode, TypeNode); 4581 break; 4582 } 4583 case ISD::VLOAD: { 4584 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 4585 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 4586 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 4587 4588 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 4589 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8; 4590 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4591 getIntPtrConstant(IncrementSize)); 4592 // FIXME: This creates a bogus srcvalue! 4593 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 4594 4595 // Build a factor node to remember that this load is independent of the 4596 // other one. 4597 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 4598 Hi.getValue(1)); 4599 4600 // Remember that we legalized the chain. 4601 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 4602 break; 4603 } 4604 case ISD::VBIT_CONVERT: { 4605 // We know the result is a vector. The input may be either a vector or a 4606 // scalar value. 4607 if (Op.getOperand(0).getValueType() != MVT::Vector) { 4608 // Lower to a store/load. FIXME: this could be improved probably. 4609 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType()); 4610 4611 SDOperand St = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 4612 Op.getOperand(0), Ptr, DAG.getSrcValue(0)); 4613 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 4614 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0)); 4615 SplitVectorOp(St, Lo, Hi); 4616 } else { 4617 // If the input is a vector type, we have to either scalarize it, pack it 4618 // or convert it based on whether the input vector type is legal. 4619 SDNode *InVal = Node->getOperand(0).Val; 4620 unsigned NumElems = 4621 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 4622 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 4623 4624 // If the input is from a single element vector, scalarize the vector, 4625 // then treat like a scalar. 4626 if (NumElems == 1) { 4627 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT); 4628 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar, 4629 Op.getOperand(1), Op.getOperand(2)); 4630 SplitVectorOp(Scalar, Lo, Hi); 4631 } else { 4632 // Split the input vector. 4633 SplitVectorOp(Op.getOperand(0), Lo, Hi); 4634 4635 // Convert each of the pieces now. 4636 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo, 4637 NewNumEltsNode, TypeNode); 4638 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi, 4639 NewNumEltsNode, TypeNode); 4640 } 4641 break; 4642 } 4643 } 4644 } 4645 4646 // Remember in a map if the values will be reused later. 4647 bool isNew = 4648 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 4649 assert(isNew && "Value already expanded?!?"); 4650} 4651 4652 4653/// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 4654/// equivalent operation that returns a scalar (e.g. F32) or packed value 4655/// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right 4656/// type for the result. 4657SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, 4658 MVT::ValueType NewVT) { 4659 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!"); 4660 SDNode *Node = Op.Val; 4661 4662 // See if we already packed it. 4663 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op); 4664 if (I != PackedNodes.end()) return I->second; 4665 4666 SDOperand Result; 4667 switch (Node->getOpcode()) { 4668 default: 4669 Node->dump(); std::cerr << "\n"; 4670 assert(0 && "Unknown vector operation in PackVectorOp!"); 4671 case ISD::VADD: 4672 case ISD::VSUB: 4673 case ISD::VMUL: 4674 case ISD::VSDIV: 4675 case ISD::VUDIV: 4676 case ISD::VAND: 4677 case ISD::VOR: 4678 case ISD::VXOR: 4679 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT), 4680 NewVT, 4681 PackVectorOp(Node->getOperand(0), NewVT), 4682 PackVectorOp(Node->getOperand(1), NewVT)); 4683 break; 4684 case ISD::VLOAD: { 4685 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 4686 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 4687 4688 Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2)); 4689 4690 // Remember that we legalized the chain. 4691 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4692 break; 4693 } 4694 case ISD::VBUILD_VECTOR: 4695 if (Node->getOperand(0).getValueType() == NewVT) { 4696 // Returning a scalar? 4697 Result = Node->getOperand(0); 4698 } else { 4699 // Returning a BUILD_VECTOR? 4700 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2); 4701 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops); 4702 } 4703 break; 4704 case ISD::VINSERT_VECTOR_ELT: 4705 if (!MVT::isVector(NewVT)) { 4706 // Returning a scalar? Must be the inserted element. 4707 Result = Node->getOperand(1); 4708 } else { 4709 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, 4710 PackVectorOp(Node->getOperand(0), NewVT), 4711 Node->getOperand(1), Node->getOperand(2)); 4712 } 4713 break; 4714 case ISD::VVECTOR_SHUFFLE: 4715 if (!MVT::isVector(NewVT)) { 4716 // Returning a scalar? Figure out if it is the LHS or RHS and return it. 4717 SDOperand EltNum = Node->getOperand(2).getOperand(0); 4718 if (cast<ConstantSDNode>(EltNum)->getValue()) 4719 Result = PackVectorOp(Node->getOperand(1), NewVT); 4720 else 4721 Result = PackVectorOp(Node->getOperand(0), NewVT); 4722 } else { 4723 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index 4724 // vector from a VBUILD_VECTOR to a BUILD_VECTOR. 4725 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(), 4726 Node->getOperand(2).Val->op_end()-2); 4727 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size()); 4728 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, BuildVecIdx); 4729 4730 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, 4731 PackVectorOp(Node->getOperand(0), NewVT), 4732 PackVectorOp(Node->getOperand(1), NewVT), BV); 4733 } 4734 break; 4735 case ISD::VBIT_CONVERT: 4736 if (Op.getOperand(0).getValueType() != MVT::Vector) 4737 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 4738 else { 4739 // If the input is a vector type, we have to either scalarize it, pack it 4740 // or convert it based on whether the input vector type is legal. 4741 SDNode *InVal = Node->getOperand(0).Val; 4742 unsigned NumElems = 4743 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 4744 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 4745 4746 // Figure out if there is a Packed type corresponding to this Vector 4747 // type. If so, convert to the packed type. 4748 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 4749 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 4750 // Turn this into a bit convert of the packed input. 4751 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 4752 PackVectorOp(Node->getOperand(0), TVT)); 4753 break; 4754 } else if (NumElems == 1) { 4755 // Turn this into a bit convert of the scalar input. 4756 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 4757 PackVectorOp(Node->getOperand(0), EVT)); 4758 break; 4759 } else { 4760 // FIXME: UNIMP! 4761 assert(0 && "Cast from unsupported vector type not implemented yet!"); 4762 } 4763 } 4764 } 4765 4766 if (TLI.isTypeLegal(NewVT)) 4767 Result = LegalizeOp(Result); 4768 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second; 4769 assert(isNew && "Value already packed?"); 4770 return Result; 4771} 4772 4773 4774// SelectionDAG::Legalize - This is the entry point for the file. 4775// 4776void SelectionDAG::Legalize() { 4777 if (ViewLegalizeDAGs) viewGraph(); 4778 4779 /// run - This is the main entry point to this class. 4780 /// 4781 SelectionDAGLegalize(*this).LegalizeDAG(); 4782} 4783 4784