LegalizeDAG.cpp revision 190a418bf6b49a4ef1c1980229a2f0d516e8a2cd
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Target/TargetLowering.h" 18#include "llvm/Target/TargetData.h" 19#include "llvm/Target/TargetOptions.h" 20#include "llvm/CallingConv.h" 21#include "llvm/Constants.h" 22#include "llvm/Support/MathExtras.h" 23#include "llvm/Support/CommandLine.h" 24#include "llvm/Support/Visibility.h" 25#include <iostream> 26#include <map> 27using namespace llvm; 28 29#ifndef NDEBUG 30static cl::opt<bool> 31ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 32 cl::desc("Pop up a window to show dags before legalize")); 33#else 34static const bool ViewLegalizeDAGs = 0; 35#endif 36 37//===----------------------------------------------------------------------===// 38/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 39/// hacks on it until the target machine can handle it. This involves 40/// eliminating value sizes the machine cannot handle (promoting small sizes to 41/// large sizes or splitting up large values into small values) as well as 42/// eliminating operations the machine cannot handle. 43/// 44/// This code also does a small amount of optimization and recognition of idioms 45/// as part of its processing. For example, if a target does not support a 46/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 47/// will attempt merge setcc and brc instructions into brcc's. 48/// 49namespace { 50class VISIBILITY_HIDDEN SelectionDAGLegalize { 51 TargetLowering &TLI; 52 SelectionDAG &DAG; 53 54 // Libcall insertion helpers. 55 56 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 57 /// legalized. We use this to ensure that calls are properly serialized 58 /// against each other, including inserted libcalls. 59 SDOperand LastCALLSEQ_END; 60 61 /// IsLegalizingCall - This member is used *only* for purposes of providing 62 /// helpful assertions that a libcall isn't created while another call is 63 /// being legalized (which could lead to non-serialized call sequences). 64 bool IsLegalizingCall; 65 66 enum LegalizeAction { 67 Legal, // The target natively supports this operation. 68 Promote, // This operation should be executed in a larger type. 69 Expand // Try to expand this to other ops, otherwise use a libcall. 70 }; 71 72 /// ValueTypeActions - This is a bitvector that contains two bits for each 73 /// value type, where the two bits correspond to the LegalizeAction enum. 74 /// This can be queried with "getTypeAction(VT)". 75 TargetLowering::ValueTypeActionImpl ValueTypeActions; 76 77 /// LegalizedNodes - For nodes that are of legal width, and that have more 78 /// than one use, this map indicates what regularized operand to use. This 79 /// allows us to avoid legalizing the same thing more than once. 80 std::map<SDOperand, SDOperand> LegalizedNodes; 81 82 /// PromotedNodes - For nodes that are below legal width, and that have more 83 /// than one use, this map indicates what promoted value to use. This allows 84 /// us to avoid promoting the same thing more than once. 85 std::map<SDOperand, SDOperand> PromotedNodes; 86 87 /// ExpandedNodes - For nodes that need to be expanded this map indicates 88 /// which which operands are the expanded version of the input. This allows 89 /// us to avoid expanding the same node more than once. 90 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 91 92 /// SplitNodes - For vector nodes that need to be split, this map indicates 93 /// which which operands are the split version of the input. This allows us 94 /// to avoid splitting the same node more than once. 95 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 96 97 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to 98 /// concrete packed types, this contains the mapping of ones we have already 99 /// processed to the result. 100 std::map<SDOperand, SDOperand> PackedNodes; 101 102 void AddLegalizedOperand(SDOperand From, SDOperand To) { 103 LegalizedNodes.insert(std::make_pair(From, To)); 104 // If someone requests legalization of the new node, return itself. 105 if (From != To) 106 LegalizedNodes.insert(std::make_pair(To, To)); 107 } 108 void AddPromotedOperand(SDOperand From, SDOperand To) { 109 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 110 assert(isNew && "Got into the map somehow?"); 111 // If someone requests legalization of the new node, return itself. 112 LegalizedNodes.insert(std::make_pair(To, To)); 113 } 114 115public: 116 117 SelectionDAGLegalize(SelectionDAG &DAG); 118 119 /// getTypeAction - Return how we should legalize values of this type, either 120 /// it is already legal or we need to expand it into multiple registers of 121 /// smaller integer type, or we need to promote it to a larger type. 122 LegalizeAction getTypeAction(MVT::ValueType VT) const { 123 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 124 } 125 126 /// isTypeLegal - Return true if this type is legal on this target. 127 /// 128 bool isTypeLegal(MVT::ValueType VT) const { 129 return getTypeAction(VT) == Legal; 130 } 131 132 void LegalizeDAG(); 133 134private: 135 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 136 /// appropriate for its type. 137 void HandleOp(SDOperand Op); 138 139 /// LegalizeOp - We know that the specified value has a legal type. 140 /// Recursively ensure that the operands have legal types, then return the 141 /// result. 142 SDOperand LegalizeOp(SDOperand O); 143 144 /// PromoteOp - Given an operation that produces a value in an invalid type, 145 /// promote it to compute the value into a larger type. The produced value 146 /// will have the correct bits for the low portion of the register, but no 147 /// guarantee is made about the top bits: it may be zero, sign-extended, or 148 /// garbage. 149 SDOperand PromoteOp(SDOperand O); 150 151 /// ExpandOp - Expand the specified SDOperand into its two component pieces 152 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 153 /// the LegalizeNodes map is filled in for any results that are not expanded, 154 /// the ExpandedNodes map is filled in for any results that are expanded, and 155 /// the Lo/Hi values are returned. This applies to integer types and Vector 156 /// types. 157 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 158 159 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 160 /// two smaller values of MVT::Vector type. 161 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 162 163 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 164 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When 165 /// this is called, we know that PackedVT is the right type for the result and 166 /// we know that this type is legal for the target. 167 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT); 168 169 /// isShuffleLegal - Return true if a vector shuffle is legal with the 170 /// specified mask and type. Targets can specify exactly which masks they 171 /// support and the code generator is tasked with not creating illegal masks. 172 /// 173 /// Note that this will also return true for shuffles that are promoted to a 174 /// different type. 175 /// 176 /// If this is a legal shuffle, this method returns the (possibly promoted) 177 /// build_vector Mask. If it's not a legal shuffle, it returns null. 178 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 179 180 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 181 std::set<SDNode*> &NodesLeadingTo); 182 183 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 184 185 SDOperand CreateStackTemporary(MVT::ValueType VT); 186 187 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 188 SDOperand &Hi); 189 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 190 SDOperand Source); 191 192 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 193 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 194 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 195 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 196 SDOperand LegalOp, 197 MVT::ValueType DestVT); 198 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 199 bool isSigned); 200 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 201 bool isSigned); 202 203 SDOperand ExpandBSWAP(SDOperand Op); 204 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 205 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 206 SDOperand &Lo, SDOperand &Hi); 207 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 208 SDOperand &Lo, SDOperand &Hi); 209 210 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op); 211 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 212 213 SDOperand getIntPtrConstant(uint64_t Val) { 214 return DAG.getConstant(Val, TLI.getPointerTy()); 215 } 216}; 217} 218 219/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 220/// specified mask and type. Targets can specify exactly which masks they 221/// support and the code generator is tasked with not creating illegal masks. 222/// 223/// Note that this will also return true for shuffles that are promoted to a 224/// different type. 225SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 226 SDOperand Mask) const { 227 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 228 default: return 0; 229 case TargetLowering::Legal: 230 case TargetLowering::Custom: 231 break; 232 case TargetLowering::Promote: { 233 // If this is promoted to a different type, convert the shuffle mask and 234 // ask if it is legal in the promoted type! 235 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 236 237 // If we changed # elements, change the shuffle mask. 238 unsigned NumEltsGrowth = 239 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 240 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 241 if (NumEltsGrowth > 1) { 242 // Renumber the elements. 243 std::vector<SDOperand> Ops; 244 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 245 SDOperand InOp = Mask.getOperand(i); 246 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 247 if (InOp.getOpcode() == ISD::UNDEF) 248 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 249 else { 250 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 251 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 252 } 253 } 254 } 255 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, Ops); 256 } 257 VT = NVT; 258 break; 259 } 260 } 261 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 262} 263 264/// getScalarizedOpcode - Return the scalar opcode that corresponds to the 265/// specified vector opcode. 266static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 267 switch (VecOp) { 268 default: assert(0 && "Don't know how to scalarize this opcode!"); 269 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 270 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 271 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 272 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV; 273 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV; 274 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0; 275 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0; 276 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0; 277 } 278} 279 280SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 281 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 282 ValueTypeActions(TLI.getValueTypeActions()) { 283 assert(MVT::LAST_VALUETYPE <= 32 && 284 "Too many value types for ValueTypeActions to hold!"); 285} 286 287/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 288/// not been visited yet and if all of its operands have already been visited. 289static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 290 std::map<SDNode*, unsigned> &Visited) { 291 if (++Visited[N] != N->getNumOperands()) 292 return; // Haven't visited all operands yet 293 294 Order.push_back(N); 295 296 if (N->hasOneUse()) { // Tail recurse in common case. 297 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 298 return; 299 } 300 301 // Now that we have N in, add anything that uses it if all of their operands 302 // are now done. 303 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 304 ComputeTopDownOrdering(*UI, Order, Visited); 305} 306 307 308void SelectionDAGLegalize::LegalizeDAG() { 309 LastCALLSEQ_END = DAG.getEntryNode(); 310 IsLegalizingCall = false; 311 312 // The legalize process is inherently a bottom-up recursive process (users 313 // legalize their uses before themselves). Given infinite stack space, we 314 // could just start legalizing on the root and traverse the whole graph. In 315 // practice however, this causes us to run out of stack space on large basic 316 // blocks. To avoid this problem, compute an ordering of the nodes where each 317 // node is only legalized after all of its operands are legalized. 318 std::map<SDNode*, unsigned> Visited; 319 std::vector<SDNode*> Order; 320 321 // Compute ordering from all of the leaves in the graphs, those (like the 322 // entry node) that have no operands. 323 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 324 E = DAG.allnodes_end(); I != E; ++I) { 325 if (I->getNumOperands() == 0) { 326 Visited[I] = 0 - 1U; 327 ComputeTopDownOrdering(I, Order, Visited); 328 } 329 } 330 331 assert(Order.size() == Visited.size() && 332 Order.size() == 333 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 334 "Error: DAG is cyclic!"); 335 Visited.clear(); 336 337 for (unsigned i = 0, e = Order.size(); i != e; ++i) 338 HandleOp(SDOperand(Order[i], 0)); 339 340 // Finally, it's possible the root changed. Get the new root. 341 SDOperand OldRoot = DAG.getRoot(); 342 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 343 DAG.setRoot(LegalizedNodes[OldRoot]); 344 345 ExpandedNodes.clear(); 346 LegalizedNodes.clear(); 347 PromotedNodes.clear(); 348 SplitNodes.clear(); 349 PackedNodes.clear(); 350 351 // Remove dead nodes now. 352 DAG.RemoveDeadNodes(); 353} 354 355 356/// FindCallEndFromCallStart - Given a chained node that is part of a call 357/// sequence, find the CALLSEQ_END node that terminates the call sequence. 358static SDNode *FindCallEndFromCallStart(SDNode *Node) { 359 if (Node->getOpcode() == ISD::CALLSEQ_END) 360 return Node; 361 if (Node->use_empty()) 362 return 0; // No CallSeqEnd 363 364 // The chain is usually at the end. 365 SDOperand TheChain(Node, Node->getNumValues()-1); 366 if (TheChain.getValueType() != MVT::Other) { 367 // Sometimes it's at the beginning. 368 TheChain = SDOperand(Node, 0); 369 if (TheChain.getValueType() != MVT::Other) { 370 // Otherwise, hunt for it. 371 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 372 if (Node->getValueType(i) == MVT::Other) { 373 TheChain = SDOperand(Node, i); 374 break; 375 } 376 377 // Otherwise, we walked into a node without a chain. 378 if (TheChain.getValueType() != MVT::Other) 379 return 0; 380 } 381 } 382 383 for (SDNode::use_iterator UI = Node->use_begin(), 384 E = Node->use_end(); UI != E; ++UI) { 385 386 // Make sure to only follow users of our token chain. 387 SDNode *User = *UI; 388 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 389 if (User->getOperand(i) == TheChain) 390 if (SDNode *Result = FindCallEndFromCallStart(User)) 391 return Result; 392 } 393 return 0; 394} 395 396/// FindCallStartFromCallEnd - Given a chained node that is part of a call 397/// sequence, find the CALLSEQ_START node that initiates the call sequence. 398static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 399 assert(Node && "Didn't find callseq_start for a call??"); 400 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 401 402 assert(Node->getOperand(0).getValueType() == MVT::Other && 403 "Node doesn't have a token chain argument!"); 404 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 405} 406 407/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 408/// see if any uses can reach Dest. If no dest operands can get to dest, 409/// legalize them, legalize ourself, and return false, otherwise, return true. 410/// 411/// Keep track of the nodes we fine that actually do lead to Dest in 412/// NodesLeadingTo. This avoids retraversing them exponential number of times. 413/// 414bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 415 std::set<SDNode*> &NodesLeadingTo) { 416 if (N == Dest) return true; // N certainly leads to Dest :) 417 418 // If we've already processed this node and it does lead to Dest, there is no 419 // need to reprocess it. 420 if (NodesLeadingTo.count(N)) return true; 421 422 // If the first result of this node has been already legalized, then it cannot 423 // reach N. 424 switch (getTypeAction(N->getValueType(0))) { 425 case Legal: 426 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 427 break; 428 case Promote: 429 if (PromotedNodes.count(SDOperand(N, 0))) return false; 430 break; 431 case Expand: 432 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 433 break; 434 } 435 436 // Okay, this node has not already been legalized. Check and legalize all 437 // operands. If none lead to Dest, then we can legalize this node. 438 bool OperandsLeadToDest = false; 439 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 440 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 441 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 442 443 if (OperandsLeadToDest) { 444 NodesLeadingTo.insert(N); 445 return true; 446 } 447 448 // Okay, this node looks safe, legalize it and return false. 449 HandleOp(SDOperand(N, 0)); 450 return false; 451} 452 453/// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 454/// appropriate for its type. 455void SelectionDAGLegalize::HandleOp(SDOperand Op) { 456 switch (getTypeAction(Op.getValueType())) { 457 default: assert(0 && "Bad type action!"); 458 case Legal: LegalizeOp(Op); break; 459 case Promote: PromoteOp(Op); break; 460 case Expand: 461 if (Op.getValueType() != MVT::Vector) { 462 SDOperand X, Y; 463 ExpandOp(Op, X, Y); 464 } else { 465 SDNode *N = Op.Val; 466 unsigned NumOps = N->getNumOperands(); 467 unsigned NumElements = 468 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue(); 469 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT(); 470 MVT::ValueType PackedVT = getVectorType(EVT, NumElements); 471 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) { 472 // In the common case, this is a legal vector type, convert it to the 473 // packed operation and type now. 474 PackVectorOp(Op, PackedVT); 475 } else if (NumElements == 1) { 476 // Otherwise, if this is a single element vector, convert it to a 477 // scalar operation. 478 PackVectorOp(Op, EVT); 479 } else { 480 // Otherwise, this is a multiple element vector that isn't supported. 481 // Split it in half and legalize both parts. 482 SDOperand X, Y; 483 SplitVectorOp(Op, X, Y); 484 } 485 } 486 break; 487 } 488} 489 490 491/// LegalizeOp - We know that the specified value has a legal type. 492/// Recursively ensure that the operands have legal types, then return the 493/// result. 494SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 495 assert(isTypeLegal(Op.getValueType()) && 496 "Caller should expand or promote operands that are not legal!"); 497 SDNode *Node = Op.Val; 498 499 // If this operation defines any values that cannot be represented in a 500 // register on this target, make sure to expand or promote them. 501 if (Node->getNumValues() > 1) { 502 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 503 if (getTypeAction(Node->getValueType(i)) != Legal) { 504 HandleOp(Op.getValue(i)); 505 assert(LegalizedNodes.count(Op) && 506 "Handling didn't add legal operands!"); 507 return LegalizedNodes[Op]; 508 } 509 } 510 511 // Note that LegalizeOp may be reentered even from single-use nodes, which 512 // means that we always must cache transformed nodes. 513 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 514 if (I != LegalizedNodes.end()) return I->second; 515 516 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 517 SDOperand Result = Op; 518 bool isCustom = false; 519 520 switch (Node->getOpcode()) { 521 case ISD::FrameIndex: 522 case ISD::EntryToken: 523 case ISD::Register: 524 case ISD::BasicBlock: 525 case ISD::TargetFrameIndex: 526 case ISD::TargetJumpTable: 527 case ISD::TargetConstant: 528 case ISD::TargetConstantFP: 529 case ISD::TargetConstantPool: 530 case ISD::TargetGlobalAddress: 531 case ISD::TargetExternalSymbol: 532 case ISD::VALUETYPE: 533 case ISD::SRCVALUE: 534 case ISD::STRING: 535 case ISD::CONDCODE: 536 // Primitives must all be legal. 537 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 538 "This must be legal!"); 539 break; 540 default: 541 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 542 // If this is a target node, legalize it by legalizing the operands then 543 // passing it through. 544 std::vector<SDOperand> Ops; 545 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 546 Ops.push_back(LegalizeOp(Node->getOperand(i))); 547 548 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops); 549 550 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 551 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 552 return Result.getValue(Op.ResNo); 553 } 554 // Otherwise this is an unhandled builtin node. splat. 555#ifndef NDEBUG 556 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 557#endif 558 assert(0 && "Do not know how to legalize this operator!"); 559 abort(); 560 case ISD::GlobalAddress: 561 case ISD::ExternalSymbol: 562 case ISD::ConstantPool: 563 case ISD::JumpTable: // Nothing to do. 564 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 565 default: assert(0 && "This action is not supported yet!"); 566 case TargetLowering::Custom: 567 Tmp1 = TLI.LowerOperation(Op, DAG); 568 if (Tmp1.Val) Result = Tmp1; 569 // FALLTHROUGH if the target doesn't want to lower this op after all. 570 case TargetLowering::Legal: 571 break; 572 } 573 break; 574 case ISD::AssertSext: 575 case ISD::AssertZext: 576 Tmp1 = LegalizeOp(Node->getOperand(0)); 577 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 578 break; 579 case ISD::MERGE_VALUES: 580 // Legalize eliminates MERGE_VALUES nodes. 581 Result = Node->getOperand(Op.ResNo); 582 break; 583 case ISD::CopyFromReg: 584 Tmp1 = LegalizeOp(Node->getOperand(0)); 585 Result = Op.getValue(0); 586 if (Node->getNumValues() == 2) { 587 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 588 } else { 589 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 590 if (Node->getNumOperands() == 3) { 591 Tmp2 = LegalizeOp(Node->getOperand(2)); 592 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 593 } else { 594 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 595 } 596 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 597 } 598 // Since CopyFromReg produces two values, make sure to remember that we 599 // legalized both of them. 600 AddLegalizedOperand(Op.getValue(0), Result); 601 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 602 return Result.getValue(Op.ResNo); 603 case ISD::UNDEF: { 604 MVT::ValueType VT = Op.getValueType(); 605 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 606 default: assert(0 && "This action is not supported yet!"); 607 case TargetLowering::Expand: 608 if (MVT::isInteger(VT)) 609 Result = DAG.getConstant(0, VT); 610 else if (MVT::isFloatingPoint(VT)) 611 Result = DAG.getConstantFP(0, VT); 612 else 613 assert(0 && "Unknown value type!"); 614 break; 615 case TargetLowering::Legal: 616 break; 617 } 618 break; 619 } 620 621 case ISD::INTRINSIC_W_CHAIN: 622 case ISD::INTRINSIC_WO_CHAIN: 623 case ISD::INTRINSIC_VOID: { 624 std::vector<SDOperand> Ops; 625 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 626 Ops.push_back(LegalizeOp(Node->getOperand(i))); 627 Result = DAG.UpdateNodeOperands(Result, Ops); 628 629 // Allow the target to custom lower its intrinsics if it wants to. 630 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 631 TargetLowering::Custom) { 632 Tmp3 = TLI.LowerOperation(Result, DAG); 633 if (Tmp3.Val) Result = Tmp3; 634 } 635 636 if (Result.Val->getNumValues() == 1) break; 637 638 // Must have return value and chain result. 639 assert(Result.Val->getNumValues() == 2 && 640 "Cannot return more than two values!"); 641 642 // Since loads produce two values, make sure to remember that we 643 // legalized both of them. 644 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 645 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 646 return Result.getValue(Op.ResNo); 647 } 648 649 case ISD::LOCATION: 650 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 651 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 652 653 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 654 case TargetLowering::Promote: 655 default: assert(0 && "This action is not supported yet!"); 656 case TargetLowering::Expand: { 657 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 658 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 659 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other); 660 661 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) { 662 const std::string &FName = 663 cast<StringSDNode>(Node->getOperand(3))->getValue(); 664 const std::string &DirName = 665 cast<StringSDNode>(Node->getOperand(4))->getValue(); 666 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName); 667 668 std::vector<SDOperand> Ops; 669 Ops.push_back(Tmp1); // chain 670 SDOperand LineOp = Node->getOperand(1); 671 SDOperand ColOp = Node->getOperand(2); 672 673 if (useDEBUG_LOC) { 674 Ops.push_back(LineOp); // line # 675 Ops.push_back(ColOp); // col # 676 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 677 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops); 678 } else { 679 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 680 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 681 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile); 682 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 683 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops); 684 } 685 } else { 686 Result = Tmp1; // chain 687 } 688 break; 689 } 690 case TargetLowering::Legal: 691 if (Tmp1 != Node->getOperand(0) || 692 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 693 std::vector<SDOperand> Ops; 694 Ops.push_back(Tmp1); 695 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 696 Ops.push_back(Node->getOperand(1)); // line # must be legal. 697 Ops.push_back(Node->getOperand(2)); // col # must be legal. 698 } else { 699 // Otherwise promote them. 700 Ops.push_back(PromoteOp(Node->getOperand(1))); 701 Ops.push_back(PromoteOp(Node->getOperand(2))); 702 } 703 Ops.push_back(Node->getOperand(3)); // filename must be legal. 704 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 705 Result = DAG.UpdateNodeOperands(Result, Ops); 706 } 707 break; 708 } 709 break; 710 711 case ISD::DEBUG_LOC: 712 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 713 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 714 default: assert(0 && "This action is not supported yet!"); 715 case TargetLowering::Legal: 716 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 717 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 718 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 719 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 720 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 721 break; 722 } 723 break; 724 725 case ISD::DEBUG_LABEL: 726 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!"); 727 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) { 728 default: assert(0 && "This action is not supported yet!"); 729 case TargetLowering::Legal: 730 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 731 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 732 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 733 break; 734 } 735 break; 736 737 case ISD::Constant: 738 // We know we don't need to expand constants here, constants only have one 739 // value and we check that it is fine above. 740 741 // FIXME: Maybe we should handle things like targets that don't support full 742 // 32-bit immediates? 743 break; 744 case ISD::ConstantFP: { 745 // Spill FP immediates to the constant pool if the target cannot directly 746 // codegen them. Targets often have some immediate values that can be 747 // efficiently generated into an FP register without a load. We explicitly 748 // leave these constants as ConstantFP nodes for the target to deal with. 749 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 750 751 // Check to see if this FP immediate is already legal. 752 bool isLegal = false; 753 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 754 E = TLI.legal_fpimm_end(); I != E; ++I) 755 if (CFP->isExactlyValue(*I)) { 756 isLegal = true; 757 break; 758 } 759 760 // If this is a legal constant, turn it into a TargetConstantFP node. 761 if (isLegal) { 762 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0)); 763 break; 764 } 765 766 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 767 default: assert(0 && "This action is not supported yet!"); 768 case TargetLowering::Custom: 769 Tmp3 = TLI.LowerOperation(Result, DAG); 770 if (Tmp3.Val) { 771 Result = Tmp3; 772 break; 773 } 774 // FALLTHROUGH 775 case TargetLowering::Expand: 776 // Otherwise we need to spill the constant to memory. 777 bool Extend = false; 778 779 // If a FP immediate is precise when represented as a float and if the 780 // target can do an extending load from float to double, we put it into 781 // the constant pool as a float, even if it's is statically typed as a 782 // double. 783 MVT::ValueType VT = CFP->getValueType(0); 784 bool isDouble = VT == MVT::f64; 785 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 786 Type::FloatTy, CFP->getValue()); 787 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 788 // Only do this if the target has a native EXTLOAD instruction from 789 // f32. 790 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 791 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 792 VT = MVT::f32; 793 Extend = true; 794 } 795 796 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 797 if (Extend) { 798 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 799 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 800 } else { 801 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 802 DAG.getSrcValue(NULL)); 803 } 804 } 805 break; 806 } 807 case ISD::TokenFactor: 808 if (Node->getNumOperands() == 2) { 809 Tmp1 = LegalizeOp(Node->getOperand(0)); 810 Tmp2 = LegalizeOp(Node->getOperand(1)); 811 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 812 } else if (Node->getNumOperands() == 3) { 813 Tmp1 = LegalizeOp(Node->getOperand(0)); 814 Tmp2 = LegalizeOp(Node->getOperand(1)); 815 Tmp3 = LegalizeOp(Node->getOperand(2)); 816 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 817 } else { 818 std::vector<SDOperand> Ops; 819 // Legalize the operands. 820 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 821 Ops.push_back(LegalizeOp(Node->getOperand(i))); 822 Result = DAG.UpdateNodeOperands(Result, Ops); 823 } 824 break; 825 826 case ISD::FORMAL_ARGUMENTS: 827 case ISD::CALL: 828 // The only option for this is to custom lower it. 829 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 830 assert(Tmp3.Val && "Target didn't custom lower this node!"); 831 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() && 832 "Lowering call/formal_arguments produced unexpected # results!"); 833 834 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 835 // remember that we legalized all of them, so it doesn't get relegalized. 836 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 837 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 838 if (Op.ResNo == i) 839 Tmp2 = Tmp1; 840 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 841 } 842 return Tmp2; 843 844 case ISD::BUILD_VECTOR: 845 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 846 default: assert(0 && "This action is not supported yet!"); 847 case TargetLowering::Custom: 848 Tmp3 = TLI.LowerOperation(Result, DAG); 849 if (Tmp3.Val) { 850 Result = Tmp3; 851 break; 852 } 853 // FALLTHROUGH 854 case TargetLowering::Expand: 855 Result = ExpandBUILD_VECTOR(Result.Val); 856 break; 857 } 858 break; 859 case ISD::INSERT_VECTOR_ELT: 860 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 861 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 862 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 863 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 864 865 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 866 Node->getValueType(0))) { 867 default: assert(0 && "This action is not supported yet!"); 868 case TargetLowering::Legal: 869 break; 870 case TargetLowering::Custom: 871 Tmp3 = TLI.LowerOperation(Result, DAG); 872 if (Tmp3.Val) { 873 Result = Tmp3; 874 break; 875 } 876 // FALLTHROUGH 877 case TargetLowering::Expand: { 878 // If the insert index is a constant, codegen this as a scalar_to_vector, 879 // then a shuffle that inserts it into the right position in the vector. 880 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 881 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 882 Tmp1.getValueType(), Tmp2); 883 884 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 885 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 886 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT); 887 888 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 889 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 890 // the RHS. 891 std::vector<SDOperand> ShufOps; 892 for (unsigned i = 0; i != NumElts; ++i) { 893 if (i != InsertPos->getValue()) 894 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 895 else 896 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 897 } 898 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,ShufOps); 899 900 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 901 Tmp1, ScVec, ShufMask); 902 Result = LegalizeOp(Result); 903 break; 904 } 905 906 // If the target doesn't support this, we have to spill the input vector 907 // to a temporary stack slot, update the element, then reload it. This is 908 // badness. We could also load the value into a vector register (either 909 // with a "move to register" or "extload into register" instruction, then 910 // permute it into place, if the idx is a constant and if the idx is 911 // supported by the target. 912 MVT::ValueType VT = Tmp1.getValueType(); 913 MVT::ValueType EltVT = Tmp2.getValueType(); 914 MVT::ValueType IdxVT = Tmp3.getValueType(); 915 MVT::ValueType PtrVT = TLI.getPointerTy(); 916 SDOperand StackPtr = CreateStackTemporary(VT); 917 // Store the vector. 918 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 919 Tmp1, StackPtr, DAG.getSrcValue(NULL)); 920 921 // Truncate or zero extend offset to target pointer type. 922 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 923 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 924 // Add the offset to the index. 925 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 926 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 927 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 928 // Store the scalar value. 929 Ch = DAG.getNode(ISD::STORE, MVT::Other, Ch, 930 Tmp2, StackPtr2, DAG.getSrcValue(NULL)); 931 // Load the updated vector. 932 Result = DAG.getLoad(VT, Ch, StackPtr, DAG.getSrcValue(NULL)); 933 break; 934 } 935 } 936 break; 937 case ISD::SCALAR_TO_VECTOR: 938 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 939 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 940 break; 941 } 942 943 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 944 Result = DAG.UpdateNodeOperands(Result, Tmp1); 945 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 946 Node->getValueType(0))) { 947 default: assert(0 && "This action is not supported yet!"); 948 case TargetLowering::Legal: 949 break; 950 case TargetLowering::Custom: 951 Tmp3 = TLI.LowerOperation(Result, DAG); 952 if (Tmp3.Val) { 953 Result = Tmp3; 954 break; 955 } 956 // FALLTHROUGH 957 case TargetLowering::Expand: 958 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 959 break; 960 } 961 break; 962 case ISD::VECTOR_SHUFFLE: 963 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 964 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 965 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 966 967 // Allow targets to custom lower the SHUFFLEs they support. 968 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 969 default: assert(0 && "Unknown operation action!"); 970 case TargetLowering::Legal: 971 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 972 "vector shuffle should not be created if not legal!"); 973 break; 974 case TargetLowering::Custom: 975 Tmp3 = TLI.LowerOperation(Result, DAG); 976 if (Tmp3.Val) { 977 Result = Tmp3; 978 break; 979 } 980 // FALLTHROUGH 981 case TargetLowering::Expand: { 982 MVT::ValueType VT = Node->getValueType(0); 983 MVT::ValueType EltVT = MVT::getVectorBaseType(VT); 984 MVT::ValueType PtrVT = TLI.getPointerTy(); 985 SDOperand Mask = Node->getOperand(2); 986 unsigned NumElems = Mask.getNumOperands(); 987 std::vector<SDOperand> Ops; 988 for (unsigned i = 0; i != NumElems; ++i) { 989 SDOperand Arg = Mask.getOperand(i); 990 if (Arg.getOpcode() == ISD::UNDEF) { 991 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 992 } else { 993 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 994 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 995 if (Idx < NumElems) 996 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 997 DAG.getConstant(Idx, PtrVT))); 998 else 999 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1000 DAG.getConstant(Idx - NumElems, PtrVT))); 1001 } 1002 } 1003 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, Ops); 1004 break; 1005 } 1006 case TargetLowering::Promote: { 1007 // Change base type to a different vector type. 1008 MVT::ValueType OVT = Node->getValueType(0); 1009 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1010 1011 // Cast the two input vectors. 1012 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1013 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1014 1015 // Convert the shuffle mask to the right # elements. 1016 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1017 assert(Tmp3.Val && "Shuffle not legal?"); 1018 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1019 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1020 break; 1021 } 1022 } 1023 break; 1024 1025 case ISD::EXTRACT_VECTOR_ELT: 1026 Tmp1 = LegalizeOp(Node->getOperand(0)); 1027 Tmp2 = LegalizeOp(Node->getOperand(1)); 1028 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1029 1030 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, 1031 Tmp1.getValueType())) { 1032 default: assert(0 && "This action is not supported yet!"); 1033 case TargetLowering::Legal: 1034 break; 1035 case TargetLowering::Custom: 1036 Tmp3 = TLI.LowerOperation(Result, DAG); 1037 if (Tmp3.Val) { 1038 Result = Tmp3; 1039 break; 1040 } 1041 // FALLTHROUGH 1042 case TargetLowering::Expand: 1043 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1044 break; 1045 } 1046 break; 1047 1048 case ISD::VEXTRACT_VECTOR_ELT: 1049 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op)); 1050 break; 1051 1052 case ISD::CALLSEQ_START: { 1053 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1054 1055 // Recursively Legalize all of the inputs of the call end that do not lead 1056 // to this call start. This ensures that any libcalls that need be inserted 1057 // are inserted *before* the CALLSEQ_START. 1058 {std::set<SDNode*> NodesLeadingTo; 1059 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1060 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1061 NodesLeadingTo); 1062 } 1063 1064 // Now that we legalized all of the inputs (which may have inserted 1065 // libcalls) create the new CALLSEQ_START node. 1066 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1067 1068 // Merge in the last call, to ensure that this call start after the last 1069 // call ended. 1070 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1071 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1072 Tmp1 = LegalizeOp(Tmp1); 1073 } 1074 1075 // Do not try to legalize the target-specific arguments (#1+). 1076 if (Tmp1 != Node->getOperand(0)) { 1077 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 1078 Ops[0] = Tmp1; 1079 Result = DAG.UpdateNodeOperands(Result, Ops); 1080 } 1081 1082 // Remember that the CALLSEQ_START is legalized. 1083 AddLegalizedOperand(Op.getValue(0), Result); 1084 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1085 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1086 1087 // Now that the callseq_start and all of the non-call nodes above this call 1088 // sequence have been legalized, legalize the call itself. During this 1089 // process, no libcalls can/will be inserted, guaranteeing that no calls 1090 // can overlap. 1091 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1092 SDOperand InCallSEQ = LastCALLSEQ_END; 1093 // Note that we are selecting this call! 1094 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1095 IsLegalizingCall = true; 1096 1097 // Legalize the call, starting from the CALLSEQ_END. 1098 LegalizeOp(LastCALLSEQ_END); 1099 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1100 return Result; 1101 } 1102 case ISD::CALLSEQ_END: 1103 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1104 // will cause this node to be legalized as well as handling libcalls right. 1105 if (LastCALLSEQ_END.Val != Node) { 1106 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1107 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1108 assert(I != LegalizedNodes.end() && 1109 "Legalizing the call start should have legalized this node!"); 1110 return I->second; 1111 } 1112 1113 // Otherwise, the call start has been legalized and everything is going 1114 // according to plan. Just legalize ourselves normally here. 1115 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1116 // Do not try to legalize the target-specific arguments (#1+), except for 1117 // an optional flag input. 1118 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1119 if (Tmp1 != Node->getOperand(0)) { 1120 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 1121 Ops[0] = Tmp1; 1122 Result = DAG.UpdateNodeOperands(Result, Ops); 1123 } 1124 } else { 1125 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1126 if (Tmp1 != Node->getOperand(0) || 1127 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1128 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 1129 Ops[0] = Tmp1; 1130 Ops.back() = Tmp2; 1131 Result = DAG.UpdateNodeOperands(Result, Ops); 1132 } 1133 } 1134 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1135 // This finishes up call legalization. 1136 IsLegalizingCall = false; 1137 1138 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1139 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1140 if (Node->getNumValues() == 2) 1141 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1142 return Result.getValue(Op.ResNo); 1143 case ISD::DYNAMIC_STACKALLOC: { 1144 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1145 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1146 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1147 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1148 1149 Tmp1 = Result.getValue(0); 1150 Tmp2 = Result.getValue(1); 1151 switch (TLI.getOperationAction(Node->getOpcode(), 1152 Node->getValueType(0))) { 1153 default: assert(0 && "This action is not supported yet!"); 1154 case TargetLowering::Expand: { 1155 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1156 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1157 " not tell us which reg is the stack pointer!"); 1158 SDOperand Chain = Tmp1.getOperand(0); 1159 SDOperand Size = Tmp2.getOperand(1); 1160 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0)); 1161 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value 1162 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain 1163 Tmp1 = LegalizeOp(Tmp1); 1164 Tmp2 = LegalizeOp(Tmp2); 1165 break; 1166 } 1167 case TargetLowering::Custom: 1168 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1169 if (Tmp3.Val) { 1170 Tmp1 = LegalizeOp(Tmp3); 1171 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1172 } 1173 break; 1174 case TargetLowering::Legal: 1175 break; 1176 } 1177 // Since this op produce two values, make sure to remember that we 1178 // legalized both of them. 1179 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1180 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1181 return Op.ResNo ? Tmp2 : Tmp1; 1182 } 1183 case ISD::INLINEASM: { 1184 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 1185 bool Changed = false; 1186 // Legalize all of the operands of the inline asm, in case they are nodes 1187 // that need to be expanded or something. Note we skip the asm string and 1188 // all of the TargetConstant flags. 1189 SDOperand Op = LegalizeOp(Ops[0]); 1190 Changed = Op != Ops[0]; 1191 Ops[0] = Op; 1192 1193 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1194 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1195 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1196 for (++i; NumVals; ++i, --NumVals) { 1197 SDOperand Op = LegalizeOp(Ops[i]); 1198 if (Op != Ops[i]) { 1199 Changed = true; 1200 Ops[i] = Op; 1201 } 1202 } 1203 } 1204 1205 if (HasInFlag) { 1206 Op = LegalizeOp(Ops.back()); 1207 Changed |= Op != Ops.back(); 1208 Ops.back() = Op; 1209 } 1210 1211 if (Changed) 1212 Result = DAG.UpdateNodeOperands(Result, Ops); 1213 1214 // INLINE asm returns a chain and flag, make sure to add both to the map. 1215 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1216 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1217 return Result.getValue(Op.ResNo); 1218 } 1219 case ISD::BR: 1220 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1221 // Ensure that libcalls are emitted before a branch. 1222 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1223 Tmp1 = LegalizeOp(Tmp1); 1224 LastCALLSEQ_END = DAG.getEntryNode(); 1225 1226 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1227 break; 1228 case ISD::BRIND: 1229 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1230 // Ensure that libcalls are emitted before a branch. 1231 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1232 Tmp1 = LegalizeOp(Tmp1); 1233 LastCALLSEQ_END = DAG.getEntryNode(); 1234 1235 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1236 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1237 case Legal: 1238 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1239 break; 1240 } 1241 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1242 break; 1243 case ISD::BRCOND: 1244 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1245 // Ensure that libcalls are emitted before a return. 1246 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1247 Tmp1 = LegalizeOp(Tmp1); 1248 LastCALLSEQ_END = DAG.getEntryNode(); 1249 1250 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1251 case Expand: assert(0 && "It's impossible to expand bools"); 1252 case Legal: 1253 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1254 break; 1255 case Promote: 1256 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1257 break; 1258 } 1259 1260 // Basic block destination (Op#2) is always legal. 1261 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1262 1263 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1264 default: assert(0 && "This action is not supported yet!"); 1265 case TargetLowering::Legal: break; 1266 case TargetLowering::Custom: 1267 Tmp1 = TLI.LowerOperation(Result, DAG); 1268 if (Tmp1.Val) Result = Tmp1; 1269 break; 1270 case TargetLowering::Expand: 1271 // Expand brcond's setcc into its constituent parts and create a BR_CC 1272 // Node. 1273 if (Tmp2.getOpcode() == ISD::SETCC) { 1274 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1275 Tmp2.getOperand(0), Tmp2.getOperand(1), 1276 Node->getOperand(2)); 1277 } else { 1278 // Make sure the condition is either zero or one. It may have been 1279 // promoted from something else. 1280 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType()); 1281 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1)) 1282 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1283 1284 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1285 DAG.getCondCode(ISD::SETNE), Tmp2, 1286 DAG.getConstant(0, Tmp2.getValueType()), 1287 Node->getOperand(2)); 1288 } 1289 break; 1290 } 1291 break; 1292 case ISD::BR_CC: 1293 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1294 // Ensure that libcalls are emitted before a branch. 1295 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1296 Tmp1 = LegalizeOp(Tmp1); 1297 LastCALLSEQ_END = DAG.getEntryNode(); 1298 1299 Tmp2 = Node->getOperand(2); // LHS 1300 Tmp3 = Node->getOperand(3); // RHS 1301 Tmp4 = Node->getOperand(1); // CC 1302 1303 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1304 1305 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1306 // the LHS is a legal SETCC itself. In this case, we need to compare 1307 // the result against zero to select between true and false values. 1308 if (Tmp3.Val == 0) { 1309 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1310 Tmp4 = DAG.getCondCode(ISD::SETNE); 1311 } 1312 1313 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1314 Node->getOperand(4)); 1315 1316 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1317 default: assert(0 && "Unexpected action for BR_CC!"); 1318 case TargetLowering::Legal: break; 1319 case TargetLowering::Custom: 1320 Tmp4 = TLI.LowerOperation(Result, DAG); 1321 if (Tmp4.Val) Result = Tmp4; 1322 break; 1323 } 1324 break; 1325 case ISD::LOAD: { 1326 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1327 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1328 1329 MVT::ValueType VT = Node->getValueType(0); 1330 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1331 Tmp3 = Result.getValue(0); 1332 Tmp4 = Result.getValue(1); 1333 1334 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1335 default: assert(0 && "This action is not supported yet!"); 1336 case TargetLowering::Legal: break; 1337 case TargetLowering::Custom: 1338 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1339 if (Tmp1.Val) { 1340 Tmp3 = LegalizeOp(Tmp1); 1341 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1342 } 1343 break; 1344 case TargetLowering::Promote: { 1345 // Only promote a load of vector type to another. 1346 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1347 // Change base type to a different vector type. 1348 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1349 1350 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, Node->getOperand(2)); 1351 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1352 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1353 break; 1354 } 1355 } 1356 // Since loads produce two values, make sure to remember that we 1357 // legalized both of them. 1358 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1359 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1360 return Op.ResNo ? Tmp4 : Tmp3; 1361 } 1362 case ISD::EXTLOAD: 1363 case ISD::SEXTLOAD: 1364 case ISD::ZEXTLOAD: { 1365 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1366 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1367 1368 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 1369 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 1370 default: assert(0 && "This action is not supported yet!"); 1371 case TargetLowering::Promote: 1372 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 1373 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), 1374 DAG.getValueType(MVT::i8)); 1375 Tmp1 = Result.getValue(0); 1376 Tmp2 = Result.getValue(1); 1377 break; 1378 case TargetLowering::Custom: 1379 isCustom = true; 1380 // FALLTHROUGH 1381 case TargetLowering::Legal: 1382 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), 1383 Node->getOperand(3)); 1384 Tmp1 = Result.getValue(0); 1385 Tmp2 = Result.getValue(1); 1386 1387 if (isCustom) { 1388 Tmp3 = TLI.LowerOperation(Tmp3, DAG); 1389 if (Tmp3.Val) { 1390 Tmp1 = LegalizeOp(Tmp3); 1391 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1392 } 1393 } 1394 break; 1395 case TargetLowering::Expand: 1396 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1397 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1398 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 1399 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1400 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1401 Tmp2 = LegalizeOp(Load.getValue(1)); 1402 break; 1403 } 1404 assert(Node->getOpcode() != ISD::EXTLOAD && 1405 "EXTLOAD should always be supported!"); 1406 // Turn the unsupported load into an EXTLOAD followed by an explicit 1407 // zero/sign extend inreg. 1408 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1409 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1410 SDOperand ValRes; 1411 if (Node->getOpcode() == ISD::SEXTLOAD) 1412 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1413 Result, DAG.getValueType(SrcVT)); 1414 else 1415 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1416 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1417 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1418 break; 1419 } 1420 // Since loads produce two values, make sure to remember that we legalized 1421 // both of them. 1422 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1423 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1424 return Op.ResNo ? Tmp2 : Tmp1; 1425 } 1426 case ISD::EXTRACT_ELEMENT: { 1427 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1428 switch (getTypeAction(OpTy)) { 1429 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1430 case Legal: 1431 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1432 // 1 -> Hi 1433 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1434 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1435 TLI.getShiftAmountTy())); 1436 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1437 } else { 1438 // 0 -> Lo 1439 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1440 Node->getOperand(0)); 1441 } 1442 break; 1443 case Expand: 1444 // Get both the low and high parts. 1445 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1446 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1447 Result = Tmp2; // 1 -> Hi 1448 else 1449 Result = Tmp1; // 0 -> Lo 1450 break; 1451 } 1452 break; 1453 } 1454 1455 case ISD::CopyToReg: 1456 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1457 1458 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1459 "Register type must be legal!"); 1460 // Legalize the incoming value (must be a legal type). 1461 Tmp2 = LegalizeOp(Node->getOperand(2)); 1462 if (Node->getNumValues() == 1) { 1463 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1464 } else { 1465 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1466 if (Node->getNumOperands() == 4) { 1467 Tmp3 = LegalizeOp(Node->getOperand(3)); 1468 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1469 Tmp3); 1470 } else { 1471 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1472 } 1473 1474 // Since this produces two values, make sure to remember that we legalized 1475 // both of them. 1476 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1477 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1478 return Result; 1479 } 1480 break; 1481 1482 case ISD::RET: 1483 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1484 1485 // Ensure that libcalls are emitted before a return. 1486 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1487 Tmp1 = LegalizeOp(Tmp1); 1488 LastCALLSEQ_END = DAG.getEntryNode(); 1489 1490 switch (Node->getNumOperands()) { 1491 case 3: // ret val 1492 Tmp2 = Node->getOperand(1); 1493 Tmp3 = Node->getOperand(2); // Signness 1494 switch (getTypeAction(Tmp2.getValueType())) { 1495 case Legal: 1496 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1497 break; 1498 case Expand: 1499 if (Tmp2.getValueType() != MVT::Vector) { 1500 SDOperand Lo, Hi; 1501 ExpandOp(Tmp2, Lo, Hi); 1502 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3); 1503 } else { 1504 SDNode *InVal = Tmp2.Val; 1505 unsigned NumElems = 1506 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 1507 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 1508 1509 // Figure out if there is a Packed type corresponding to this Vector 1510 // type. If so, convert to the packed type. 1511 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1512 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 1513 // Turn this into a return of the packed type. 1514 Tmp2 = PackVectorOp(Tmp2, TVT); 1515 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1516 } else if (NumElems == 1) { 1517 // Turn this into a return of the scalar type. 1518 Tmp2 = PackVectorOp(Tmp2, EVT); 1519 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1520 1521 // FIXME: Returns of gcc generic vectors smaller than a legal type 1522 // should be returned in integer registers! 1523 1524 // The scalarized value type may not be legal, e.g. it might require 1525 // promotion or expansion. Relegalize the return. 1526 Result = LegalizeOp(Result); 1527 } else { 1528 // FIXME: Returns of gcc generic vectors larger than a legal vector 1529 // type should be returned by reference! 1530 SDOperand Lo, Hi; 1531 SplitVectorOp(Tmp2, Lo, Hi); 1532 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3); 1533 Result = LegalizeOp(Result); 1534 } 1535 } 1536 break; 1537 case Promote: 1538 Tmp2 = PromoteOp(Node->getOperand(1)); 1539 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1540 Result = LegalizeOp(Result); 1541 break; 1542 } 1543 break; 1544 case 1: // ret void 1545 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1546 break; 1547 default: { // ret <values> 1548 std::vector<SDOperand> NewValues; 1549 NewValues.push_back(Tmp1); 1550 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 1551 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1552 case Legal: 1553 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1554 NewValues.push_back(Node->getOperand(i+1)); 1555 break; 1556 case Expand: { 1557 SDOperand Lo, Hi; 1558 assert(Node->getOperand(i).getValueType() != MVT::Vector && 1559 "FIXME: TODO: implement returning non-legal vector types!"); 1560 ExpandOp(Node->getOperand(i), Lo, Hi); 1561 NewValues.push_back(Lo); 1562 NewValues.push_back(Node->getOperand(i+1)); 1563 NewValues.push_back(Hi); 1564 NewValues.push_back(Node->getOperand(i+1)); 1565 break; 1566 } 1567 case Promote: 1568 assert(0 && "Can't promote multiple return value yet!"); 1569 } 1570 1571 if (NewValues.size() == Node->getNumOperands()) 1572 Result = DAG.UpdateNodeOperands(Result, NewValues); 1573 else 1574 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1575 break; 1576 } 1577 } 1578 1579 if (Result.getOpcode() == ISD::RET) { 1580 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 1581 default: assert(0 && "This action is not supported yet!"); 1582 case TargetLowering::Legal: break; 1583 case TargetLowering::Custom: 1584 Tmp1 = TLI.LowerOperation(Result, DAG); 1585 if (Tmp1.Val) Result = Tmp1; 1586 break; 1587 } 1588 } 1589 break; 1590 case ISD::STORE: { 1591 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1592 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1593 1594 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1595 // FIXME: We shouldn't do this for TargetConstantFP's. 1596 // FIXME: move this to the DAG Combiner! 1597 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1598 if (CFP->getValueType(0) == MVT::f32) { 1599 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 1600 } else { 1601 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1602 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 1603 } 1604 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1605 Node->getOperand(3)); 1606 break; 1607 } 1608 1609 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1610 case Legal: { 1611 Tmp3 = LegalizeOp(Node->getOperand(1)); 1612 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1613 Node->getOperand(3)); 1614 1615 MVT::ValueType VT = Tmp3.getValueType(); 1616 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1617 default: assert(0 && "This action is not supported yet!"); 1618 case TargetLowering::Legal: break; 1619 case TargetLowering::Custom: 1620 Tmp1 = TLI.LowerOperation(Result, DAG); 1621 if (Tmp1.Val) Result = Tmp1; 1622 break; 1623 case TargetLowering::Promote: 1624 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 1625 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 1626 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1627 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1628 Node->getOperand(3)); 1629 break; 1630 } 1631 break; 1632 } 1633 case Promote: 1634 // Truncate the value and store the result. 1635 Tmp3 = PromoteOp(Node->getOperand(1)); 1636 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1637 Node->getOperand(3), 1638 DAG.getValueType(Node->getOperand(1).getValueType())); 1639 break; 1640 1641 case Expand: 1642 unsigned IncrementSize = 0; 1643 SDOperand Lo, Hi; 1644 1645 // If this is a vector type, then we have to calculate the increment as 1646 // the product of the element size in bytes, and the number of elements 1647 // in the high half of the vector. 1648 if (Node->getOperand(1).getValueType() == MVT::Vector) { 1649 SDNode *InVal = Node->getOperand(1).Val; 1650 unsigned NumElems = 1651 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 1652 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 1653 1654 // Figure out if there is a Packed type corresponding to this Vector 1655 // type. If so, convert to the packed type. 1656 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1657 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 1658 // Turn this into a normal store of the packed type. 1659 Tmp3 = PackVectorOp(Node->getOperand(1), TVT); 1660 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1661 Node->getOperand(3)); 1662 Result = LegalizeOp(Result); 1663 break; 1664 } else if (NumElems == 1) { 1665 // Turn this into a normal store of the scalar type. 1666 Tmp3 = PackVectorOp(Node->getOperand(1), EVT); 1667 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1668 Node->getOperand(3)); 1669 // The scalarized value type may not be legal, e.g. it might require 1670 // promotion or expansion. Relegalize the scalar store. 1671 Result = LegalizeOp(Result); 1672 break; 1673 } else { 1674 SplitVectorOp(Node->getOperand(1), Lo, Hi); 1675 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; 1676 } 1677 } else { 1678 ExpandOp(Node->getOperand(1), Lo, Hi); 1679 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1680 1681 if (!TLI.isLittleEndian()) 1682 std::swap(Lo, Hi); 1683 } 1684 1685 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1686 Node->getOperand(3)); 1687 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1688 getIntPtrConstant(IncrementSize)); 1689 assert(isTypeLegal(Tmp2.getValueType()) && 1690 "Pointers must be legal!"); 1691 // FIXME: This sets the srcvalue of both halves to be the same, which is 1692 // wrong. 1693 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1694 Node->getOperand(3)); 1695 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1696 break; 1697 } 1698 break; 1699 } 1700 case ISD::PCMARKER: 1701 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1702 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1703 break; 1704 case ISD::STACKSAVE: 1705 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1706 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1707 Tmp1 = Result.getValue(0); 1708 Tmp2 = Result.getValue(1); 1709 1710 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 1711 default: assert(0 && "This action is not supported yet!"); 1712 case TargetLowering::Legal: break; 1713 case TargetLowering::Custom: 1714 Tmp3 = TLI.LowerOperation(Result, DAG); 1715 if (Tmp3.Val) { 1716 Tmp1 = LegalizeOp(Tmp3); 1717 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1718 } 1719 break; 1720 case TargetLowering::Expand: 1721 // Expand to CopyFromReg if the target set 1722 // StackPointerRegisterToSaveRestore. 1723 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1724 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 1725 Node->getValueType(0)); 1726 Tmp2 = Tmp1.getValue(1); 1727 } else { 1728 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 1729 Tmp2 = Node->getOperand(0); 1730 } 1731 break; 1732 } 1733 1734 // Since stacksave produce two values, make sure to remember that we 1735 // legalized both of them. 1736 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1737 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1738 return Op.ResNo ? Tmp2 : Tmp1; 1739 1740 case ISD::STACKRESTORE: 1741 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1742 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1743 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1744 1745 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 1746 default: assert(0 && "This action is not supported yet!"); 1747 case TargetLowering::Legal: break; 1748 case TargetLowering::Custom: 1749 Tmp1 = TLI.LowerOperation(Result, DAG); 1750 if (Tmp1.Val) Result = Tmp1; 1751 break; 1752 case TargetLowering::Expand: 1753 // Expand to CopyToReg if the target set 1754 // StackPointerRegisterToSaveRestore. 1755 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1756 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 1757 } else { 1758 Result = Tmp1; 1759 } 1760 break; 1761 } 1762 break; 1763 1764 case ISD::READCYCLECOUNTER: 1765 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1766 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1767 1768 // Since rdcc produce two values, make sure to remember that we legalized 1769 // both of them. 1770 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1771 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1772 return Result; 1773 1774 case ISD::TRUNCSTORE: { 1775 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1776 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1777 1778 assert(isTypeLegal(Node->getOperand(1).getValueType()) && 1779 "Cannot handle illegal TRUNCSTORE yet!"); 1780 Tmp2 = LegalizeOp(Node->getOperand(1)); 1781 1782 // The only promote case we handle is TRUNCSTORE:i1 X into 1783 // -> TRUNCSTORE:i8 (and X, 1) 1784 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1785 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1786 TargetLowering::Promote) { 1787 // Promote the bool to a mask then store. 1788 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1789 DAG.getConstant(1, Tmp2.getValueType())); 1790 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1791 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1792 1793 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1794 Tmp3 != Node->getOperand(2)) { 1795 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 1796 Node->getOperand(3), Node->getOperand(4)); 1797 } 1798 1799 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT(); 1800 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) { 1801 default: assert(0 && "This action is not supported yet!"); 1802 case TargetLowering::Legal: break; 1803 case TargetLowering::Custom: 1804 Tmp1 = TLI.LowerOperation(Result, DAG); 1805 if (Tmp1.Val) Result = Tmp1; 1806 break; 1807 } 1808 break; 1809 } 1810 case ISD::SELECT: 1811 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1812 case Expand: assert(0 && "It's impossible to expand bools"); 1813 case Legal: 1814 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1815 break; 1816 case Promote: 1817 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1818 break; 1819 } 1820 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1821 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1822 1823 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1824 1825 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1826 default: assert(0 && "This action is not supported yet!"); 1827 case TargetLowering::Legal: break; 1828 case TargetLowering::Custom: { 1829 Tmp1 = TLI.LowerOperation(Result, DAG); 1830 if (Tmp1.Val) Result = Tmp1; 1831 break; 1832 } 1833 case TargetLowering::Expand: 1834 if (Tmp1.getOpcode() == ISD::SETCC) { 1835 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1836 Tmp2, Tmp3, 1837 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1838 } else { 1839 // Make sure the condition is either zero or one. It may have been 1840 // promoted from something else. 1841 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType()); 1842 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1)) 1843 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1844 Result = DAG.getSelectCC(Tmp1, 1845 DAG.getConstant(0, Tmp1.getValueType()), 1846 Tmp2, Tmp3, ISD::SETNE); 1847 } 1848 break; 1849 case TargetLowering::Promote: { 1850 MVT::ValueType NVT = 1851 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1852 unsigned ExtOp, TruncOp; 1853 if (MVT::isVector(Tmp2.getValueType())) { 1854 ExtOp = ISD::BIT_CONVERT; 1855 TruncOp = ISD::BIT_CONVERT; 1856 } else if (MVT::isInteger(Tmp2.getValueType())) { 1857 ExtOp = ISD::ANY_EXTEND; 1858 TruncOp = ISD::TRUNCATE; 1859 } else { 1860 ExtOp = ISD::FP_EXTEND; 1861 TruncOp = ISD::FP_ROUND; 1862 } 1863 // Promote each of the values to the new type. 1864 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1865 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1866 // Perform the larger operation, then round down. 1867 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1868 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1869 break; 1870 } 1871 } 1872 break; 1873 case ISD::SELECT_CC: { 1874 Tmp1 = Node->getOperand(0); // LHS 1875 Tmp2 = Node->getOperand(1); // RHS 1876 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1877 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1878 SDOperand CC = Node->getOperand(4); 1879 1880 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 1881 1882 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1883 // the LHS is a legal SETCC itself. In this case, we need to compare 1884 // the result against zero to select between true and false values. 1885 if (Tmp2.Val == 0) { 1886 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1887 CC = DAG.getCondCode(ISD::SETNE); 1888 } 1889 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 1890 1891 // Everything is legal, see if we should expand this op or something. 1892 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 1893 default: assert(0 && "This action is not supported yet!"); 1894 case TargetLowering::Legal: break; 1895 case TargetLowering::Custom: 1896 Tmp1 = TLI.LowerOperation(Result, DAG); 1897 if (Tmp1.Val) Result = Tmp1; 1898 break; 1899 } 1900 break; 1901 } 1902 case ISD::SETCC: 1903 Tmp1 = Node->getOperand(0); 1904 Tmp2 = Node->getOperand(1); 1905 Tmp3 = Node->getOperand(2); 1906 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 1907 1908 // If we had to Expand the SetCC operands into a SELECT node, then it may 1909 // not always be possible to return a true LHS & RHS. In this case, just 1910 // return the value we legalized, returned in the LHS 1911 if (Tmp2.Val == 0) { 1912 Result = Tmp1; 1913 break; 1914 } 1915 1916 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 1917 default: assert(0 && "Cannot handle this action for SETCC yet!"); 1918 case TargetLowering::Custom: 1919 isCustom = true; 1920 // FALLTHROUGH. 1921 case TargetLowering::Legal: 1922 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1923 if (isCustom) { 1924 Tmp3 = TLI.LowerOperation(Result, DAG); 1925 if (Tmp3.Val) Result = Tmp3; 1926 } 1927 break; 1928 case TargetLowering::Promote: { 1929 // First step, figure out the appropriate operation to use. 1930 // Allow SETCC to not be supported for all legal data types 1931 // Mostly this targets FP 1932 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 1933 MVT::ValueType OldVT = NewInTy; 1934 1935 // Scan for the appropriate larger type to use. 1936 while (1) { 1937 NewInTy = (MVT::ValueType)(NewInTy+1); 1938 1939 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 1940 "Fell off of the edge of the integer world"); 1941 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 1942 "Fell off of the edge of the floating point world"); 1943 1944 // If the target supports SETCC of this type, use it. 1945 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 1946 break; 1947 } 1948 if (MVT::isInteger(NewInTy)) 1949 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1950 else { 1951 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 1952 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 1953 } 1954 Tmp1 = LegalizeOp(Tmp1); 1955 Tmp2 = LegalizeOp(Tmp2); 1956 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1957 Result = LegalizeOp(Result); 1958 break; 1959 } 1960 case TargetLowering::Expand: 1961 // Expand a setcc node into a select_cc of the same condition, lhs, and 1962 // rhs that selects between const 1 (true) and const 0 (false). 1963 MVT::ValueType VT = Node->getValueType(0); 1964 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1965 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1966 Node->getOperand(2)); 1967 break; 1968 } 1969 break; 1970 case ISD::MEMSET: 1971 case ISD::MEMCPY: 1972 case ISD::MEMMOVE: { 1973 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1974 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1975 1976 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1977 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1978 case Expand: assert(0 && "Cannot expand a byte!"); 1979 case Legal: 1980 Tmp3 = LegalizeOp(Node->getOperand(2)); 1981 break; 1982 case Promote: 1983 Tmp3 = PromoteOp(Node->getOperand(2)); 1984 break; 1985 } 1986 } else { 1987 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1988 } 1989 1990 SDOperand Tmp4; 1991 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1992 case Expand: { 1993 // Length is too big, just take the lo-part of the length. 1994 SDOperand HiPart; 1995 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1996 break; 1997 } 1998 case Legal: 1999 Tmp4 = LegalizeOp(Node->getOperand(3)); 2000 break; 2001 case Promote: 2002 Tmp4 = PromoteOp(Node->getOperand(3)); 2003 break; 2004 } 2005 2006 SDOperand Tmp5; 2007 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2008 case Expand: assert(0 && "Cannot expand this yet!"); 2009 case Legal: 2010 Tmp5 = LegalizeOp(Node->getOperand(4)); 2011 break; 2012 case Promote: 2013 Tmp5 = PromoteOp(Node->getOperand(4)); 2014 break; 2015 } 2016 2017 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2018 default: assert(0 && "This action not implemented for this operation!"); 2019 case TargetLowering::Custom: 2020 isCustom = true; 2021 // FALLTHROUGH 2022 case TargetLowering::Legal: 2023 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 2024 if (isCustom) { 2025 Tmp1 = TLI.LowerOperation(Result, DAG); 2026 if (Tmp1.Val) Result = Tmp1; 2027 } 2028 break; 2029 case TargetLowering::Expand: { 2030 // Otherwise, the target does not support this operation. Lower the 2031 // operation to an explicit libcall as appropriate. 2032 MVT::ValueType IntPtr = TLI.getPointerTy(); 2033 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2034 std::vector<std::pair<SDOperand, const Type*> > Args; 2035 2036 const char *FnName = 0; 2037 if (Node->getOpcode() == ISD::MEMSET) { 2038 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 2039 // Extend the (previously legalized) ubyte argument to be an int value 2040 // for the call. 2041 if (Tmp3.getValueType() > MVT::i32) 2042 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2043 else 2044 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2045 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 2046 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 2047 2048 FnName = "memset"; 2049 } else if (Node->getOpcode() == ISD::MEMCPY || 2050 Node->getOpcode() == ISD::MEMMOVE) { 2051 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 2052 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 2053 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 2054 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2055 } else { 2056 assert(0 && "Unknown op!"); 2057 } 2058 2059 std::pair<SDOperand,SDOperand> CallResult = 2060 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 2061 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2062 Result = CallResult.second; 2063 break; 2064 } 2065 } 2066 break; 2067 } 2068 2069 case ISD::SHL_PARTS: 2070 case ISD::SRA_PARTS: 2071 case ISD::SRL_PARTS: { 2072 std::vector<SDOperand> Ops; 2073 bool Changed = false; 2074 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2075 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2076 Changed |= Ops.back() != Node->getOperand(i); 2077 } 2078 if (Changed) 2079 Result = DAG.UpdateNodeOperands(Result, Ops); 2080 2081 switch (TLI.getOperationAction(Node->getOpcode(), 2082 Node->getValueType(0))) { 2083 default: assert(0 && "This action is not supported yet!"); 2084 case TargetLowering::Legal: break; 2085 case TargetLowering::Custom: 2086 Tmp1 = TLI.LowerOperation(Result, DAG); 2087 if (Tmp1.Val) { 2088 SDOperand Tmp2, RetVal(0, 0); 2089 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2090 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2091 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2092 if (i == Op.ResNo) 2093 RetVal = Tmp2; 2094 } 2095 assert(RetVal.Val && "Illegal result number"); 2096 return RetVal; 2097 } 2098 break; 2099 } 2100 2101 // Since these produce multiple values, make sure to remember that we 2102 // legalized all of them. 2103 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2104 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2105 return Result.getValue(Op.ResNo); 2106 } 2107 2108 // Binary operators 2109 case ISD::ADD: 2110 case ISD::SUB: 2111 case ISD::MUL: 2112 case ISD::MULHS: 2113 case ISD::MULHU: 2114 case ISD::UDIV: 2115 case ISD::SDIV: 2116 case ISD::AND: 2117 case ISD::OR: 2118 case ISD::XOR: 2119 case ISD::SHL: 2120 case ISD::SRL: 2121 case ISD::SRA: 2122 case ISD::FADD: 2123 case ISD::FSUB: 2124 case ISD::FMUL: 2125 case ISD::FDIV: 2126 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2127 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2128 case Expand: assert(0 && "Not possible"); 2129 case Legal: 2130 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2131 break; 2132 case Promote: 2133 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2134 break; 2135 } 2136 2137 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2138 2139 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2140 default: assert(0 && "BinOp legalize operation not supported"); 2141 case TargetLowering::Legal: break; 2142 case TargetLowering::Custom: 2143 Tmp1 = TLI.LowerOperation(Result, DAG); 2144 if (Tmp1.Val) Result = Tmp1; 2145 break; 2146 case TargetLowering::Expand: { 2147 assert(MVT::isVector(Node->getValueType(0)) && 2148 "Cannot expand this binary operator!"); 2149 // Expand the operation into a bunch of nasty scalar code. 2150 std::vector<SDOperand> Ops; 2151 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0)); 2152 MVT::ValueType PtrVT = TLI.getPointerTy(); 2153 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0)); 2154 i != e; ++i) { 2155 SDOperand Idx = DAG.getConstant(i, PtrVT); 2156 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx); 2157 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx); 2158 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS)); 2159 } 2160 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops); 2161 break; 2162 } 2163 case TargetLowering::Promote: { 2164 switch (Node->getOpcode()) { 2165 default: assert(0 && "Do not know how to promote this BinOp!"); 2166 case ISD::AND: 2167 case ISD::OR: 2168 case ISD::XOR: { 2169 MVT::ValueType OVT = Node->getValueType(0); 2170 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2171 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2172 // Bit convert each of the values to the new type. 2173 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2174 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2175 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2176 // Bit convert the result back the original type. 2177 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2178 break; 2179 } 2180 } 2181 } 2182 } 2183 break; 2184 2185 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2186 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2187 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2188 case Expand: assert(0 && "Not possible"); 2189 case Legal: 2190 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2191 break; 2192 case Promote: 2193 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2194 break; 2195 } 2196 2197 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2198 2199 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2200 default: assert(0 && "Operation not supported"); 2201 case TargetLowering::Custom: 2202 Tmp1 = TLI.LowerOperation(Result, DAG); 2203 if (Tmp1.Val) Result = Tmp1; 2204 break; 2205 case TargetLowering::Legal: break; 2206 case TargetLowering::Expand: 2207 // If this target supports fabs/fneg natively, do this efficiently. 2208 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) && 2209 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) { 2210 // Get the sign bit of the RHS. 2211 MVT::ValueType IVT = 2212 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2213 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2214 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2215 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2216 // Get the absolute value of the result. 2217 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2218 // Select between the nabs and abs value based on the sign bit of 2219 // the input. 2220 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2221 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2222 AbsVal), 2223 AbsVal); 2224 Result = LegalizeOp(Result); 2225 break; 2226 } 2227 2228 // Otherwise, do bitwise ops! 2229 2230 // copysign -> copysignf/copysign libcall. 2231 const char *FnName; 2232 if (Node->getValueType(0) == MVT::f32) { 2233 FnName = "copysignf"; 2234 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type. 2235 Result = DAG.UpdateNodeOperands(Result, Tmp1, 2236 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2)); 2237 } else { 2238 FnName = "copysign"; 2239 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type. 2240 Result = DAG.UpdateNodeOperands(Result, Tmp1, 2241 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2)); 2242 } 2243 SDOperand Dummy; 2244 Result = ExpandLibCall(FnName, Node, Dummy); 2245 break; 2246 } 2247 break; 2248 2249 case ISD::ADDC: 2250 case ISD::SUBC: 2251 Tmp1 = LegalizeOp(Node->getOperand(0)); 2252 Tmp2 = LegalizeOp(Node->getOperand(1)); 2253 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2254 // Since this produces two values, make sure to remember that we legalized 2255 // both of them. 2256 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2257 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2258 return Result; 2259 2260 case ISD::ADDE: 2261 case ISD::SUBE: 2262 Tmp1 = LegalizeOp(Node->getOperand(0)); 2263 Tmp2 = LegalizeOp(Node->getOperand(1)); 2264 Tmp3 = LegalizeOp(Node->getOperand(2)); 2265 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2266 // Since this produces two values, make sure to remember that we legalized 2267 // both of them. 2268 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2269 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2270 return Result; 2271 2272 case ISD::BUILD_PAIR: { 2273 MVT::ValueType PairTy = Node->getValueType(0); 2274 // TODO: handle the case where the Lo and Hi operands are not of legal type 2275 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2276 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2277 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2278 case TargetLowering::Promote: 2279 case TargetLowering::Custom: 2280 assert(0 && "Cannot promote/custom this yet!"); 2281 case TargetLowering::Legal: 2282 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2283 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2284 break; 2285 case TargetLowering::Expand: 2286 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2287 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2288 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2289 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2290 TLI.getShiftAmountTy())); 2291 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2292 break; 2293 } 2294 break; 2295 } 2296 2297 case ISD::UREM: 2298 case ISD::SREM: 2299 case ISD::FREM: 2300 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2301 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2302 2303 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2304 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2305 case TargetLowering::Custom: 2306 isCustom = true; 2307 // FALLTHROUGH 2308 case TargetLowering::Legal: 2309 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2310 if (isCustom) { 2311 Tmp1 = TLI.LowerOperation(Result, DAG); 2312 if (Tmp1.Val) Result = Tmp1; 2313 } 2314 break; 2315 case TargetLowering::Expand: 2316 if (MVT::isInteger(Node->getValueType(0))) { 2317 // X % Y -> X-X/Y*Y 2318 MVT::ValueType VT = Node->getValueType(0); 2319 unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV; 2320 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 2321 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2322 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2323 } else { 2324 // Floating point mod -> fmod libcall. 2325 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 2326 SDOperand Dummy; 2327 Result = ExpandLibCall(FnName, Node, Dummy); 2328 } 2329 break; 2330 } 2331 break; 2332 case ISD::VAARG: { 2333 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2334 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2335 2336 MVT::ValueType VT = Node->getValueType(0); 2337 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2338 default: assert(0 && "This action is not supported yet!"); 2339 case TargetLowering::Custom: 2340 isCustom = true; 2341 // FALLTHROUGH 2342 case TargetLowering::Legal: 2343 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2344 Result = Result.getValue(0); 2345 Tmp1 = Result.getValue(1); 2346 2347 if (isCustom) { 2348 Tmp2 = TLI.LowerOperation(Result, DAG); 2349 if (Tmp2.Val) { 2350 Result = LegalizeOp(Tmp2); 2351 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 2352 } 2353 } 2354 break; 2355 case TargetLowering::Expand: { 2356 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2357 Node->getOperand(2)); 2358 // Increment the pointer, VAList, to the next vaarg 2359 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2360 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2361 TLI.getPointerTy())); 2362 // Store the incremented VAList to the legalized pointer 2363 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2, 2364 Node->getOperand(2)); 2365 // Load the actual argument out of the pointer VAList 2366 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0)); 2367 Tmp1 = LegalizeOp(Result.getValue(1)); 2368 Result = LegalizeOp(Result); 2369 break; 2370 } 2371 } 2372 // Since VAARG produces two values, make sure to remember that we 2373 // legalized both of them. 2374 AddLegalizedOperand(SDOperand(Node, 0), Result); 2375 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 2376 return Op.ResNo ? Tmp1 : Result; 2377 } 2378 2379 case ISD::VACOPY: 2380 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2381 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 2382 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 2383 2384 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 2385 default: assert(0 && "This action is not supported yet!"); 2386 case TargetLowering::Custom: 2387 isCustom = true; 2388 // FALLTHROUGH 2389 case TargetLowering::Legal: 2390 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 2391 Node->getOperand(3), Node->getOperand(4)); 2392 if (isCustom) { 2393 Tmp1 = TLI.LowerOperation(Result, DAG); 2394 if (Tmp1.Val) Result = Tmp1; 2395 } 2396 break; 2397 case TargetLowering::Expand: 2398 // This defaults to loading a pointer from the input and storing it to the 2399 // output, returning the chain. 2400 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3)); 2401 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2, 2402 Node->getOperand(4)); 2403 break; 2404 } 2405 break; 2406 2407 case ISD::VAEND: 2408 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2409 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2410 2411 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 2412 default: assert(0 && "This action is not supported yet!"); 2413 case TargetLowering::Custom: 2414 isCustom = true; 2415 // FALLTHROUGH 2416 case TargetLowering::Legal: 2417 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2418 if (isCustom) { 2419 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 2420 if (Tmp1.Val) Result = Tmp1; 2421 } 2422 break; 2423 case TargetLowering::Expand: 2424 Result = Tmp1; // Default to a no-op, return the chain 2425 break; 2426 } 2427 break; 2428 2429 case ISD::VASTART: 2430 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2431 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2432 2433 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2434 2435 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 2436 default: assert(0 && "This action is not supported yet!"); 2437 case TargetLowering::Legal: break; 2438 case TargetLowering::Custom: 2439 Tmp1 = TLI.LowerOperation(Result, DAG); 2440 if (Tmp1.Val) Result = Tmp1; 2441 break; 2442 } 2443 break; 2444 2445 case ISD::ROTL: 2446 case ISD::ROTR: 2447 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2448 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2449 2450 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 2451 "Cannot handle this yet!"); 2452 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2453 break; 2454 2455 case ISD::BSWAP: 2456 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2457 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2458 case TargetLowering::Custom: 2459 assert(0 && "Cannot custom legalize this yet!"); 2460 case TargetLowering::Legal: 2461 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2462 break; 2463 case TargetLowering::Promote: { 2464 MVT::ValueType OVT = Tmp1.getValueType(); 2465 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2466 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT); 2467 2468 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2469 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 2470 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 2471 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 2472 break; 2473 } 2474 case TargetLowering::Expand: 2475 Result = ExpandBSWAP(Tmp1); 2476 break; 2477 } 2478 break; 2479 2480 case ISD::CTPOP: 2481 case ISD::CTTZ: 2482 case ISD::CTLZ: 2483 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2484 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2485 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!"); 2486 case TargetLowering::Legal: 2487 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2488 break; 2489 case TargetLowering::Promote: { 2490 MVT::ValueType OVT = Tmp1.getValueType(); 2491 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2492 2493 // Zero extend the argument. 2494 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2495 // Perform the larger operation, then subtract if needed. 2496 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2497 switch (Node->getOpcode()) { 2498 case ISD::CTPOP: 2499 Result = Tmp1; 2500 break; 2501 case ISD::CTTZ: 2502 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2503 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2504 DAG.getConstant(getSizeInBits(NVT), NVT), 2505 ISD::SETEQ); 2506 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2507 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 2508 break; 2509 case ISD::CTLZ: 2510 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2511 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2512 DAG.getConstant(getSizeInBits(NVT) - 2513 getSizeInBits(OVT), NVT)); 2514 break; 2515 } 2516 break; 2517 } 2518 case TargetLowering::Expand: 2519 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 2520 break; 2521 } 2522 break; 2523 2524 // Unary operators 2525 case ISD::FABS: 2526 case ISD::FNEG: 2527 case ISD::FSQRT: 2528 case ISD::FSIN: 2529 case ISD::FCOS: 2530 Tmp1 = LegalizeOp(Node->getOperand(0)); 2531 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2532 case TargetLowering::Promote: 2533 case TargetLowering::Custom: 2534 isCustom = true; 2535 // FALLTHROUGH 2536 case TargetLowering::Legal: 2537 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2538 if (isCustom) { 2539 Tmp1 = TLI.LowerOperation(Result, DAG); 2540 if (Tmp1.Val) Result = Tmp1; 2541 } 2542 break; 2543 case TargetLowering::Expand: 2544 switch (Node->getOpcode()) { 2545 default: assert(0 && "Unreachable!"); 2546 case ISD::FNEG: 2547 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2548 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2549 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 2550 break; 2551 case ISD::FABS: { 2552 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2553 MVT::ValueType VT = Node->getValueType(0); 2554 Tmp2 = DAG.getConstantFP(0.0, VT); 2555 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2556 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2557 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2558 break; 2559 } 2560 case ISD::FSQRT: 2561 case ISD::FSIN: 2562 case ISD::FCOS: { 2563 MVT::ValueType VT = Node->getValueType(0); 2564 const char *FnName = 0; 2565 switch(Node->getOpcode()) { 2566 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 2567 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 2568 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 2569 default: assert(0 && "Unreachable!"); 2570 } 2571 SDOperand Dummy; 2572 Result = ExpandLibCall(FnName, Node, Dummy); 2573 break; 2574 } 2575 } 2576 break; 2577 } 2578 break; 2579 2580 case ISD::BIT_CONVERT: 2581 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 2582 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2583 } else { 2584 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 2585 Node->getOperand(0).getValueType())) { 2586 default: assert(0 && "Unknown operation action!"); 2587 case TargetLowering::Expand: 2588 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2589 break; 2590 case TargetLowering::Legal: 2591 Tmp1 = LegalizeOp(Node->getOperand(0)); 2592 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2593 break; 2594 } 2595 } 2596 break; 2597 case ISD::VBIT_CONVERT: { 2598 assert(Op.getOperand(0).getValueType() == MVT::Vector && 2599 "Can only have VBIT_CONVERT where input or output is MVT::Vector!"); 2600 2601 // The input has to be a vector type, we have to either scalarize it, pack 2602 // it, or convert it based on whether the input vector type is legal. 2603 SDNode *InVal = Node->getOperand(0).Val; 2604 unsigned NumElems = 2605 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 2606 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 2607 2608 // Figure out if there is a Packed type corresponding to this Vector 2609 // type. If so, convert to the packed type. 2610 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2611 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 2612 // Turn this into a bit convert of the packed input. 2613 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2614 PackVectorOp(Node->getOperand(0), TVT)); 2615 break; 2616 } else if (NumElems == 1) { 2617 // Turn this into a bit convert of the scalar input. 2618 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2619 PackVectorOp(Node->getOperand(0), EVT)); 2620 break; 2621 } else { 2622 // FIXME: UNIMP! Store then reload 2623 assert(0 && "Cast from unsupported vector type not implemented yet!"); 2624 } 2625 } 2626 2627 // Conversion operators. The source and destination have different types. 2628 case ISD::SINT_TO_FP: 2629 case ISD::UINT_TO_FP: { 2630 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2631 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2632 case Legal: 2633 switch (TLI.getOperationAction(Node->getOpcode(), 2634 Node->getOperand(0).getValueType())) { 2635 default: assert(0 && "Unknown operation action!"); 2636 case TargetLowering::Custom: 2637 isCustom = true; 2638 // FALLTHROUGH 2639 case TargetLowering::Legal: 2640 Tmp1 = LegalizeOp(Node->getOperand(0)); 2641 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2642 if (isCustom) { 2643 Tmp1 = TLI.LowerOperation(Result, DAG); 2644 if (Tmp1.Val) Result = Tmp1; 2645 } 2646 break; 2647 case TargetLowering::Expand: 2648 Result = ExpandLegalINT_TO_FP(isSigned, 2649 LegalizeOp(Node->getOperand(0)), 2650 Node->getValueType(0)); 2651 break; 2652 case TargetLowering::Promote: 2653 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2654 Node->getValueType(0), 2655 isSigned); 2656 break; 2657 } 2658 break; 2659 case Expand: 2660 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2661 Node->getValueType(0), Node->getOperand(0)); 2662 break; 2663 case Promote: 2664 Tmp1 = PromoteOp(Node->getOperand(0)); 2665 if (isSigned) { 2666 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 2667 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 2668 } else { 2669 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 2670 Node->getOperand(0).getValueType()); 2671 } 2672 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2673 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 2674 break; 2675 } 2676 break; 2677 } 2678 case ISD::TRUNCATE: 2679 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2680 case Legal: 2681 Tmp1 = LegalizeOp(Node->getOperand(0)); 2682 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2683 break; 2684 case Expand: 2685 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2686 2687 // Since the result is legal, we should just be able to truncate the low 2688 // part of the source. 2689 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2690 break; 2691 case Promote: 2692 Result = PromoteOp(Node->getOperand(0)); 2693 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2694 break; 2695 } 2696 break; 2697 2698 case ISD::FP_TO_SINT: 2699 case ISD::FP_TO_UINT: 2700 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2701 case Legal: 2702 Tmp1 = LegalizeOp(Node->getOperand(0)); 2703 2704 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2705 default: assert(0 && "Unknown operation action!"); 2706 case TargetLowering::Custom: 2707 isCustom = true; 2708 // FALLTHROUGH 2709 case TargetLowering::Legal: 2710 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2711 if (isCustom) { 2712 Tmp1 = TLI.LowerOperation(Result, DAG); 2713 if (Tmp1.Val) Result = Tmp1; 2714 } 2715 break; 2716 case TargetLowering::Promote: 2717 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2718 Node->getOpcode() == ISD::FP_TO_SINT); 2719 break; 2720 case TargetLowering::Expand: 2721 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2722 SDOperand True, False; 2723 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2724 MVT::ValueType NVT = Node->getValueType(0); 2725 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2726 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2727 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2728 Node->getOperand(0), Tmp2, ISD::SETLT); 2729 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2730 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2731 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2732 Tmp2)); 2733 False = DAG.getNode(ISD::XOR, NVT, False, 2734 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2735 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 2736 break; 2737 } else { 2738 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2739 } 2740 break; 2741 } 2742 break; 2743 case Expand: 2744 assert(0 && "Shouldn't need to expand other operators here!"); 2745 case Promote: 2746 Tmp1 = PromoteOp(Node->getOperand(0)); 2747 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 2748 Result = LegalizeOp(Result); 2749 break; 2750 } 2751 break; 2752 2753 case ISD::ANY_EXTEND: 2754 case ISD::ZERO_EXTEND: 2755 case ISD::SIGN_EXTEND: 2756 case ISD::FP_EXTEND: 2757 case ISD::FP_ROUND: 2758 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2759 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 2760 case Legal: 2761 Tmp1 = LegalizeOp(Node->getOperand(0)); 2762 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2763 break; 2764 case Promote: 2765 switch (Node->getOpcode()) { 2766 case ISD::ANY_EXTEND: 2767 Tmp1 = PromoteOp(Node->getOperand(0)); 2768 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 2769 break; 2770 case ISD::ZERO_EXTEND: 2771 Result = PromoteOp(Node->getOperand(0)); 2772 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2773 Result = DAG.getZeroExtendInReg(Result, 2774 Node->getOperand(0).getValueType()); 2775 break; 2776 case ISD::SIGN_EXTEND: 2777 Result = PromoteOp(Node->getOperand(0)); 2778 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2779 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2780 Result, 2781 DAG.getValueType(Node->getOperand(0).getValueType())); 2782 break; 2783 case ISD::FP_EXTEND: 2784 Result = PromoteOp(Node->getOperand(0)); 2785 if (Result.getValueType() != Op.getValueType()) 2786 // Dynamically dead while we have only 2 FP types. 2787 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2788 break; 2789 case ISD::FP_ROUND: 2790 Result = PromoteOp(Node->getOperand(0)); 2791 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2792 break; 2793 } 2794 } 2795 break; 2796 case ISD::FP_ROUND_INREG: 2797 case ISD::SIGN_EXTEND_INREG: { 2798 Tmp1 = LegalizeOp(Node->getOperand(0)); 2799 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2800 2801 // If this operation is not supported, convert it to a shl/shr or load/store 2802 // pair. 2803 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2804 default: assert(0 && "This action not supported for this op yet!"); 2805 case TargetLowering::Legal: 2806 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2807 break; 2808 case TargetLowering::Expand: 2809 // If this is an integer extend and shifts are supported, do that. 2810 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2811 // NOTE: we could fall back on load/store here too for targets without 2812 // SAR. However, it is doubtful that any exist. 2813 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2814 MVT::getSizeInBits(ExtraVT); 2815 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2816 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2817 Node->getOperand(0), ShiftCst); 2818 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2819 Result, ShiftCst); 2820 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2821 // The only way we can lower this is to turn it into a STORETRUNC, 2822 // EXTLOAD pair, targetting a temporary location (a stack slot). 2823 2824 // NOTE: there is a choice here between constantly creating new stack 2825 // slots and always reusing the same one. We currently always create 2826 // new ones, as reuse may inhibit scheduling. 2827 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2828 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty); 2829 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty); 2830 MachineFunction &MF = DAG.getMachineFunction(); 2831 int SSFI = 2832 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2833 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2834 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2835 Node->getOperand(0), StackSlot, 2836 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2837 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2838 Result, StackSlot, DAG.getSrcValue(NULL), 2839 ExtraVT); 2840 } else { 2841 assert(0 && "Unknown op"); 2842 } 2843 break; 2844 } 2845 break; 2846 } 2847 } 2848 2849 assert(Result.getValueType() == Op.getValueType() && 2850 "Bad legalization!"); 2851 2852 // Make sure that the generated code is itself legal. 2853 if (Result != Op) 2854 Result = LegalizeOp(Result); 2855 2856 // Note that LegalizeOp may be reentered even from single-use nodes, which 2857 // means that we always must cache transformed nodes. 2858 AddLegalizedOperand(Op, Result); 2859 return Result; 2860} 2861 2862/// PromoteOp - Given an operation that produces a value in an invalid type, 2863/// promote it to compute the value into a larger type. The produced value will 2864/// have the correct bits for the low portion of the register, but no guarantee 2865/// is made about the top bits: it may be zero, sign-extended, or garbage. 2866SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2867 MVT::ValueType VT = Op.getValueType(); 2868 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2869 assert(getTypeAction(VT) == Promote && 2870 "Caller should expand or legalize operands that are not promotable!"); 2871 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2872 "Cannot promote to smaller type!"); 2873 2874 SDOperand Tmp1, Tmp2, Tmp3; 2875 SDOperand Result; 2876 SDNode *Node = Op.Val; 2877 2878 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2879 if (I != PromotedNodes.end()) return I->second; 2880 2881 switch (Node->getOpcode()) { 2882 case ISD::CopyFromReg: 2883 assert(0 && "CopyFromReg must be legal!"); 2884 default: 2885#ifndef NDEBUG 2886 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2887#endif 2888 assert(0 && "Do not know how to promote this operator!"); 2889 abort(); 2890 case ISD::UNDEF: 2891 Result = DAG.getNode(ISD::UNDEF, NVT); 2892 break; 2893 case ISD::Constant: 2894 if (VT != MVT::i1) 2895 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2896 else 2897 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2898 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2899 break; 2900 case ISD::ConstantFP: 2901 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2902 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2903 break; 2904 2905 case ISD::SETCC: 2906 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2907 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2908 Node->getOperand(1), Node->getOperand(2)); 2909 break; 2910 2911 case ISD::TRUNCATE: 2912 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2913 case Legal: 2914 Result = LegalizeOp(Node->getOperand(0)); 2915 assert(Result.getValueType() >= NVT && 2916 "This truncation doesn't make sense!"); 2917 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2918 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2919 break; 2920 case Promote: 2921 // The truncation is not required, because we don't guarantee anything 2922 // about high bits anyway. 2923 Result = PromoteOp(Node->getOperand(0)); 2924 break; 2925 case Expand: 2926 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2927 // Truncate the low part of the expanded value to the result type 2928 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2929 } 2930 break; 2931 case ISD::SIGN_EXTEND: 2932 case ISD::ZERO_EXTEND: 2933 case ISD::ANY_EXTEND: 2934 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2935 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2936 case Legal: 2937 // Input is legal? Just do extend all the way to the larger type. 2938 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 2939 break; 2940 case Promote: 2941 // Promote the reg if it's smaller. 2942 Result = PromoteOp(Node->getOperand(0)); 2943 // The high bits are not guaranteed to be anything. Insert an extend. 2944 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2945 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2946 DAG.getValueType(Node->getOperand(0).getValueType())); 2947 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2948 Result = DAG.getZeroExtendInReg(Result, 2949 Node->getOperand(0).getValueType()); 2950 break; 2951 } 2952 break; 2953 case ISD::BIT_CONVERT: 2954 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2955 Result = PromoteOp(Result); 2956 break; 2957 2958 case ISD::FP_EXTEND: 2959 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2960 case ISD::FP_ROUND: 2961 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2962 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2963 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2964 case Legal: 2965 // Input is legal? Do an FP_ROUND_INREG. 2966 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 2967 DAG.getValueType(VT)); 2968 break; 2969 } 2970 break; 2971 2972 case ISD::SINT_TO_FP: 2973 case ISD::UINT_TO_FP: 2974 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2975 case Legal: 2976 // No extra round required here. 2977 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 2978 break; 2979 2980 case Promote: 2981 Result = PromoteOp(Node->getOperand(0)); 2982 if (Node->getOpcode() == ISD::SINT_TO_FP) 2983 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2984 Result, 2985 DAG.getValueType(Node->getOperand(0).getValueType())); 2986 else 2987 Result = DAG.getZeroExtendInReg(Result, 2988 Node->getOperand(0).getValueType()); 2989 // No extra round required here. 2990 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2991 break; 2992 case Expand: 2993 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2994 Node->getOperand(0)); 2995 // Round if we cannot tolerate excess precision. 2996 if (NoExcessFPPrecision) 2997 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2998 DAG.getValueType(VT)); 2999 break; 3000 } 3001 break; 3002 3003 case ISD::SIGN_EXTEND_INREG: 3004 Result = PromoteOp(Node->getOperand(0)); 3005 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3006 Node->getOperand(1)); 3007 break; 3008 case ISD::FP_TO_SINT: 3009 case ISD::FP_TO_UINT: 3010 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3011 case Legal: 3012 Tmp1 = Node->getOperand(0); 3013 break; 3014 case Promote: 3015 // The input result is prerounded, so we don't have to do anything 3016 // special. 3017 Tmp1 = PromoteOp(Node->getOperand(0)); 3018 break; 3019 case Expand: 3020 assert(0 && "not implemented"); 3021 } 3022 // If we're promoting a UINT to a larger size, check to see if the new node 3023 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3024 // we can use that instead. This allows us to generate better code for 3025 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3026 // legal, such as PowerPC. 3027 if (Node->getOpcode() == ISD::FP_TO_UINT && 3028 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3029 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3030 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3031 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3032 } else { 3033 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3034 } 3035 break; 3036 3037 case ISD::FABS: 3038 case ISD::FNEG: 3039 Tmp1 = PromoteOp(Node->getOperand(0)); 3040 assert(Tmp1.getValueType() == NVT); 3041 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3042 // NOTE: we do not have to do any extra rounding here for 3043 // NoExcessFPPrecision, because we know the input will have the appropriate 3044 // precision, and these operations don't modify precision at all. 3045 break; 3046 3047 case ISD::FSQRT: 3048 case ISD::FSIN: 3049 case ISD::FCOS: 3050 Tmp1 = PromoteOp(Node->getOperand(0)); 3051 assert(Tmp1.getValueType() == NVT); 3052 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3053 if (NoExcessFPPrecision) 3054 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3055 DAG.getValueType(VT)); 3056 break; 3057 3058 case ISD::AND: 3059 case ISD::OR: 3060 case ISD::XOR: 3061 case ISD::ADD: 3062 case ISD::SUB: 3063 case ISD::MUL: 3064 // The input may have strange things in the top bits of the registers, but 3065 // these operations don't care. They may have weird bits going out, but 3066 // that too is okay if they are integer operations. 3067 Tmp1 = PromoteOp(Node->getOperand(0)); 3068 Tmp2 = PromoteOp(Node->getOperand(1)); 3069 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3070 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3071 break; 3072 case ISD::FADD: 3073 case ISD::FSUB: 3074 case ISD::FMUL: 3075 Tmp1 = PromoteOp(Node->getOperand(0)); 3076 Tmp2 = PromoteOp(Node->getOperand(1)); 3077 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3078 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3079 3080 // Floating point operations will give excess precision that we may not be 3081 // able to tolerate. If we DO allow excess precision, just leave it, 3082 // otherwise excise it. 3083 // FIXME: Why would we need to round FP ops more than integer ones? 3084 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3085 if (NoExcessFPPrecision) 3086 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3087 DAG.getValueType(VT)); 3088 break; 3089 3090 case ISD::SDIV: 3091 case ISD::SREM: 3092 // These operators require that their input be sign extended. 3093 Tmp1 = PromoteOp(Node->getOperand(0)); 3094 Tmp2 = PromoteOp(Node->getOperand(1)); 3095 if (MVT::isInteger(NVT)) { 3096 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3097 DAG.getValueType(VT)); 3098 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3099 DAG.getValueType(VT)); 3100 } 3101 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3102 3103 // Perform FP_ROUND: this is probably overly pessimistic. 3104 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 3105 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3106 DAG.getValueType(VT)); 3107 break; 3108 case ISD::FDIV: 3109 case ISD::FREM: 3110 case ISD::FCOPYSIGN: 3111 // These operators require that their input be fp extended. 3112 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3113 case Legal: 3114 Tmp1 = LegalizeOp(Node->getOperand(0)); 3115 break; 3116 case Promote: 3117 Tmp1 = PromoteOp(Node->getOperand(0)); 3118 break; 3119 case Expand: 3120 assert(0 && "not implemented"); 3121 } 3122 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3123 case Legal: 3124 Tmp2 = LegalizeOp(Node->getOperand(1)); 3125 break; 3126 case Promote: 3127 Tmp2 = PromoteOp(Node->getOperand(1)); 3128 break; 3129 case Expand: 3130 assert(0 && "not implemented"); 3131 } 3132 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3133 3134 // Perform FP_ROUND: this is probably overly pessimistic. 3135 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 3136 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3137 DAG.getValueType(VT)); 3138 break; 3139 3140 case ISD::UDIV: 3141 case ISD::UREM: 3142 // These operators require that their input be zero extended. 3143 Tmp1 = PromoteOp(Node->getOperand(0)); 3144 Tmp2 = PromoteOp(Node->getOperand(1)); 3145 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 3146 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3147 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3148 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3149 break; 3150 3151 case ISD::SHL: 3152 Tmp1 = PromoteOp(Node->getOperand(0)); 3153 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 3154 break; 3155 case ISD::SRA: 3156 // The input value must be properly sign extended. 3157 Tmp1 = PromoteOp(Node->getOperand(0)); 3158 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3159 DAG.getValueType(VT)); 3160 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 3161 break; 3162 case ISD::SRL: 3163 // The input value must be properly zero extended. 3164 Tmp1 = PromoteOp(Node->getOperand(0)); 3165 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3166 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 3167 break; 3168 3169 case ISD::VAARG: 3170 Tmp1 = Node->getOperand(0); // Get the chain. 3171 Tmp2 = Node->getOperand(1); // Get the pointer. 3172 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 3173 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 3174 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 3175 } else { 3176 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3177 Node->getOperand(2)); 3178 // Increment the pointer, VAList, to the next vaarg 3179 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3180 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3181 TLI.getPointerTy())); 3182 // Store the incremented VAList to the legalized pointer 3183 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2, 3184 Node->getOperand(2)); 3185 // Load the actual argument out of the pointer VAList 3186 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, 3187 DAG.getSrcValue(0), VT); 3188 } 3189 // Remember that we legalized the chain. 3190 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3191 break; 3192 3193 case ISD::LOAD: 3194 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0), 3195 Node->getOperand(1), Node->getOperand(2), VT); 3196 // Remember that we legalized the chain. 3197 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3198 break; 3199 case ISD::SEXTLOAD: 3200 case ISD::ZEXTLOAD: 3201 case ISD::EXTLOAD: 3202 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0), 3203 Node->getOperand(1), Node->getOperand(2), 3204 cast<VTSDNode>(Node->getOperand(3))->getVT()); 3205 // Remember that we legalized the chain. 3206 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3207 break; 3208 case ISD::SELECT: 3209 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 3210 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 3211 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 3212 break; 3213 case ISD::SELECT_CC: 3214 Tmp2 = PromoteOp(Node->getOperand(2)); // True 3215 Tmp3 = PromoteOp(Node->getOperand(3)); // False 3216 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3217 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 3218 break; 3219 case ISD::BSWAP: 3220 Tmp1 = Node->getOperand(0); 3221 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3222 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3223 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3224 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT), 3225 TLI.getShiftAmountTy())); 3226 break; 3227 case ISD::CTPOP: 3228 case ISD::CTTZ: 3229 case ISD::CTLZ: 3230 // Zero extend the argument 3231 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 3232 // Perform the larger operation, then subtract if needed. 3233 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3234 switch(Node->getOpcode()) { 3235 case ISD::CTPOP: 3236 Result = Tmp1; 3237 break; 3238 case ISD::CTTZ: 3239 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3240 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3241 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 3242 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3243 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1); 3244 break; 3245 case ISD::CTLZ: 3246 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3247 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3248 DAG.getConstant(getSizeInBits(NVT) - 3249 getSizeInBits(VT), NVT)); 3250 break; 3251 } 3252 break; 3253 case ISD::VEXTRACT_VECTOR_ELT: 3254 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op)); 3255 break; 3256 case ISD::EXTRACT_VECTOR_ELT: 3257 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 3258 break; 3259 } 3260 3261 assert(Result.Val && "Didn't set a result!"); 3262 3263 // Make sure the result is itself legal. 3264 Result = LegalizeOp(Result); 3265 3266 // Remember that we promoted this! 3267 AddPromotedOperand(Op, Result); 3268 return Result; 3269} 3270 3271/// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a 3272/// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based 3273/// on the vector type. The return type of this matches the element type of the 3274/// vector, which may not be legal for the target. 3275SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) { 3276 // We know that operand #0 is the Vec vector. If the index is a constant 3277 // or if the invec is a supported hardware type, we can use it. Otherwise, 3278 // lower to a store then an indexed load. 3279 SDOperand Vec = Op.getOperand(0); 3280 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 3281 3282 SDNode *InVal = Vec.Val; 3283 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 3284 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 3285 3286 // Figure out if there is a Packed type corresponding to this Vector 3287 // type. If so, convert to the packed type. 3288 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3289 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 3290 // Turn this into a packed extract_vector_elt operation. 3291 Vec = PackVectorOp(Vec, TVT); 3292 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx); 3293 } else if (NumElems == 1) { 3294 // This must be an access of the only element. Return it. 3295 return PackVectorOp(Vec, EVT); 3296 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 3297 SDOperand Lo, Hi; 3298 SplitVectorOp(Vec, Lo, Hi); 3299 if (CIdx->getValue() < NumElems/2) { 3300 Vec = Lo; 3301 } else { 3302 Vec = Hi; 3303 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 3304 } 3305 3306 // It's now an extract from the appropriate high or low part. Recurse. 3307 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3308 return LowerVEXTRACT_VECTOR_ELT(Op); 3309 } else { 3310 // Variable index case for extract element. 3311 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!! 3312 assert(0 && "unimp!"); 3313 return SDOperand(); 3314 } 3315} 3316 3317/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 3318/// memory traffic. 3319SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 3320 SDOperand Vector = Op.getOperand(0); 3321 SDOperand Idx = Op.getOperand(1); 3322 3323 // If the target doesn't support this, store the value to a temporary 3324 // stack slot, then LOAD the scalar element back out. 3325 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType()); 3326 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3327 Vector, StackPtr, DAG.getSrcValue(NULL)); 3328 3329 // Add the offset to the index. 3330 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 3331 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 3332 DAG.getConstant(EltSize, Idx.getValueType())); 3333 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 3334 3335 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL)); 3336} 3337 3338 3339/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 3340/// with condition CC on the current target. This usually involves legalizing 3341/// or promoting the arguments. In the case where LHS and RHS must be expanded, 3342/// there may be no choice but to create a new SetCC node to represent the 3343/// legalized value of setcc lhs, rhs. In this case, the value is returned in 3344/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 3345void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 3346 SDOperand &RHS, 3347 SDOperand &CC) { 3348 SDOperand Tmp1, Tmp2, Result; 3349 3350 switch (getTypeAction(LHS.getValueType())) { 3351 case Legal: 3352 Tmp1 = LegalizeOp(LHS); // LHS 3353 Tmp2 = LegalizeOp(RHS); // RHS 3354 break; 3355 case Promote: 3356 Tmp1 = PromoteOp(LHS); // LHS 3357 Tmp2 = PromoteOp(RHS); // RHS 3358 3359 // If this is an FP compare, the operands have already been extended. 3360 if (MVT::isInteger(LHS.getValueType())) { 3361 MVT::ValueType VT = LHS.getValueType(); 3362 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3363 3364 // Otherwise, we have to insert explicit sign or zero extends. Note 3365 // that we could insert sign extends for ALL conditions, but zero extend 3366 // is cheaper on many machines (an AND instead of two shifts), so prefer 3367 // it. 3368 switch (cast<CondCodeSDNode>(CC)->get()) { 3369 default: assert(0 && "Unknown integer comparison!"); 3370 case ISD::SETEQ: 3371 case ISD::SETNE: 3372 case ISD::SETUGE: 3373 case ISD::SETUGT: 3374 case ISD::SETULE: 3375 case ISD::SETULT: 3376 // ALL of these operations will work if we either sign or zero extend 3377 // the operands (including the unsigned comparisons!). Zero extend is 3378 // usually a simpler/cheaper operation, so prefer it. 3379 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3380 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3381 break; 3382 case ISD::SETGE: 3383 case ISD::SETGT: 3384 case ISD::SETLT: 3385 case ISD::SETLE: 3386 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3387 DAG.getValueType(VT)); 3388 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3389 DAG.getValueType(VT)); 3390 break; 3391 } 3392 } 3393 break; 3394 case Expand: 3395 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 3396 ExpandOp(LHS, LHSLo, LHSHi); 3397 ExpandOp(RHS, RHSLo, RHSHi); 3398 switch (cast<CondCodeSDNode>(CC)->get()) { 3399 case ISD::SETEQ: 3400 case ISD::SETNE: 3401 if (RHSLo == RHSHi) 3402 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 3403 if (RHSCST->isAllOnesValue()) { 3404 // Comparison to -1. 3405 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 3406 Tmp2 = RHSLo; 3407 break; 3408 } 3409 3410 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 3411 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 3412 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 3413 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3414 break; 3415 default: 3416 // If this is a comparison of the sign bit, just look at the top part. 3417 // X > -1, x < 0 3418 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 3419 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 3420 CST->getValue() == 0) || // X < 0 3421 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 3422 CST->isAllOnesValue())) { // X > -1 3423 Tmp1 = LHSHi; 3424 Tmp2 = RHSHi; 3425 break; 3426 } 3427 3428 // FIXME: This generated code sucks. 3429 ISD::CondCode LowCC; 3430 switch (cast<CondCodeSDNode>(CC)->get()) { 3431 default: assert(0 && "Unknown integer setcc!"); 3432 case ISD::SETLT: 3433 case ISD::SETULT: LowCC = ISD::SETULT; break; 3434 case ISD::SETGT: 3435 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 3436 case ISD::SETLE: 3437 case ISD::SETULE: LowCC = ISD::SETULE; break; 3438 case ISD::SETGE: 3439 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 3440 } 3441 3442 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 3443 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 3444 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 3445 3446 // NOTE: on targets without efficient SELECT of bools, we can always use 3447 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 3448 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 3449 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC); 3450 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 3451 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 3452 Result, Tmp1, Tmp2)); 3453 Tmp1 = Result; 3454 Tmp2 = SDOperand(); 3455 } 3456 } 3457 LHS = Tmp1; 3458 RHS = Tmp2; 3459} 3460 3461/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 3462/// The resultant code need not be legal. Note that SrcOp is the input operand 3463/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 3464SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 3465 SDOperand SrcOp) { 3466 // Create the stack frame object. 3467 SDOperand FIPtr = CreateStackTemporary(DestVT); 3468 3469 // Emit a store to the stack slot. 3470 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3471 SrcOp, FIPtr, DAG.getSrcValue(NULL)); 3472 // Result is a load from the stack slot. 3473 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0)); 3474} 3475 3476SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 3477 // Create a vector sized/aligned stack slot, store the value to element #0, 3478 // then load the whole vector back out. 3479 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); 3480 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3481 Node->getOperand(0), StackPtr, 3482 DAG.getSrcValue(NULL)); 3483 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,DAG.getSrcValue(NULL)); 3484} 3485 3486 3487/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 3488/// support the operation, but do support the resultant packed vector type. 3489SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 3490 3491 // If the only non-undef value is the low element, turn this into a 3492 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 3493 unsigned NumElems = Node->getNumOperands(); 3494 bool isOnlyLowElement = true; 3495 SDOperand SplatValue = Node->getOperand(0); 3496 std::map<SDOperand, std::vector<unsigned> > Values; 3497 Values[SplatValue].push_back(0); 3498 bool isConstant = true; 3499 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 3500 SplatValue.getOpcode() != ISD::UNDEF) 3501 isConstant = false; 3502 3503 for (unsigned i = 1; i < NumElems; ++i) { 3504 SDOperand V = Node->getOperand(i); 3505 Values[V].push_back(i); 3506 if (V.getOpcode() != ISD::UNDEF) 3507 isOnlyLowElement = false; 3508 if (SplatValue != V) 3509 SplatValue = SDOperand(0,0); 3510 3511 // If this isn't a constant element or an undef, we can't use a constant 3512 // pool load. 3513 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 3514 V.getOpcode() != ISD::UNDEF) 3515 isConstant = false; 3516 } 3517 3518 if (isOnlyLowElement) { 3519 // If the low element is an undef too, then this whole things is an undef. 3520 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 3521 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 3522 // Otherwise, turn this into a scalar_to_vector node. 3523 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 3524 Node->getOperand(0)); 3525 } 3526 3527 // If all elements are constants, create a load from the constant pool. 3528 if (isConstant) { 3529 MVT::ValueType VT = Node->getValueType(0); 3530 const Type *OpNTy = 3531 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 3532 std::vector<Constant*> CV; 3533 for (unsigned i = 0, e = NumElems; i != e; ++i) { 3534 if (ConstantFPSDNode *V = 3535 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 3536 CV.push_back(ConstantFP::get(OpNTy, V->getValue())); 3537 } else if (ConstantSDNode *V = 3538 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 3539 CV.push_back(ConstantUInt::get(OpNTy, V->getValue())); 3540 } else { 3541 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 3542 CV.push_back(UndefValue::get(OpNTy)); 3543 } 3544 } 3545 Constant *CP = ConstantPacked::get(CV); 3546 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 3547 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 3548 DAG.getSrcValue(NULL)); 3549 } 3550 3551 if (SplatValue.Val) { // Splat of one value? 3552 // Build the shuffle constant vector: <0, 0, 0, 0> 3553 MVT::ValueType MaskVT = 3554 MVT::getIntVectorWithNumElements(NumElems); 3555 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT)); 3556 std::vector<SDOperand> ZeroVec(NumElems, Zero); 3557 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec); 3558 3559 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 3560 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 3561 // Get the splatted value into the low element of a vector register. 3562 SDOperand LowValVec = 3563 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 3564 3565 // Return shuffle(LowValVec, undef, <0,0,0,0>) 3566 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 3567 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 3568 SplatMask); 3569 } 3570 } 3571 3572 // If there are only two unique elements, we may be able to turn this into a 3573 // vector shuffle. 3574 if (Values.size() == 2) { 3575 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 3576 MVT::ValueType MaskVT = 3577 MVT::getIntVectorWithNumElements(NumElems); 3578 std::vector<SDOperand> MaskVec(NumElems); 3579 unsigned i = 0; 3580 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 3581 E = Values.end(); I != E; ++I) { 3582 for (std::vector<unsigned>::iterator II = I->second.begin(), 3583 EE = I->second.end(); II != EE; ++II) 3584 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT)); 3585 i += NumElems; 3586 } 3587 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec); 3588 3589 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 3590 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 3591 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 3592 std::vector<SDOperand> Ops; 3593 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 3594 E = Values.end(); I != E; ++I) { 3595 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 3596 I->first); 3597 Ops.push_back(Op); 3598 } 3599 Ops.push_back(ShuffleMask); 3600 3601 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 3602 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops); 3603 } 3604 } 3605 3606 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 3607 // aligned object on the stack, store each element into it, then load 3608 // the result as a vector. 3609 MVT::ValueType VT = Node->getValueType(0); 3610 // Create the stack frame object. 3611 SDOperand FIPtr = CreateStackTemporary(VT); 3612 3613 // Emit a store of each element to the stack slot. 3614 std::vector<SDOperand> Stores; 3615 unsigned TypeByteSize = 3616 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 3617 unsigned VectorSize = MVT::getSizeInBits(VT)/8; 3618 // Store (in the right endianness) the elements to memory. 3619 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3620 // Ignore undef elements. 3621 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3622 3623 unsigned Offset = TypeByteSize*i; 3624 3625 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 3626 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 3627 3628 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3629 Node->getOperand(i), Idx, 3630 DAG.getSrcValue(NULL))); 3631 } 3632 3633 SDOperand StoreChain; 3634 if (!Stores.empty()) // Not all undef elements? 3635 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 3636 else 3637 StoreChain = DAG.getEntryNode(); 3638 3639 // Result is a load from the stack slot. 3640 return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0)); 3641} 3642 3643/// CreateStackTemporary - Create a stack temporary, suitable for holding the 3644/// specified value type. 3645SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) { 3646 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 3647 unsigned ByteSize = MVT::getSizeInBits(VT)/8; 3648 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize); 3649 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 3650} 3651 3652void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 3653 SDOperand Op, SDOperand Amt, 3654 SDOperand &Lo, SDOperand &Hi) { 3655 // Expand the subcomponents. 3656 SDOperand LHSL, LHSH; 3657 ExpandOp(Op, LHSL, LHSH); 3658 3659 std::vector<SDOperand> Ops; 3660 Ops.push_back(LHSL); 3661 Ops.push_back(LHSH); 3662 Ops.push_back(Amt); 3663 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 3664 Lo = DAG.getNode(NodeOp, VTs, Ops); 3665 Hi = Lo.getValue(1); 3666} 3667 3668 3669/// ExpandShift - Try to find a clever way to expand this shift operation out to 3670/// smaller elements. If we can't find a way that is more efficient than a 3671/// libcall on this target, return false. Otherwise, return true with the 3672/// low-parts expanded into Lo and Hi. 3673bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 3674 SDOperand &Lo, SDOperand &Hi) { 3675 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 3676 "This is not a shift!"); 3677 3678 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 3679 SDOperand ShAmt = LegalizeOp(Amt); 3680 MVT::ValueType ShTy = ShAmt.getValueType(); 3681 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 3682 unsigned NVTBits = MVT::getSizeInBits(NVT); 3683 3684 // Handle the case when Amt is an immediate. Other cases are currently broken 3685 // and are disabled. 3686 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 3687 unsigned Cst = CN->getValue(); 3688 // Expand the incoming operand to be shifted, so that we have its parts 3689 SDOperand InL, InH; 3690 ExpandOp(Op, InL, InH); 3691 switch(Opc) { 3692 case ISD::SHL: 3693 if (Cst > VTBits) { 3694 Lo = DAG.getConstant(0, NVT); 3695 Hi = DAG.getConstant(0, NVT); 3696 } else if (Cst > NVTBits) { 3697 Lo = DAG.getConstant(0, NVT); 3698 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 3699 } else if (Cst == NVTBits) { 3700 Lo = DAG.getConstant(0, NVT); 3701 Hi = InL; 3702 } else { 3703 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 3704 Hi = DAG.getNode(ISD::OR, NVT, 3705 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 3706 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 3707 } 3708 return true; 3709 case ISD::SRL: 3710 if (Cst > VTBits) { 3711 Lo = DAG.getConstant(0, NVT); 3712 Hi = DAG.getConstant(0, NVT); 3713 } else if (Cst > NVTBits) { 3714 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 3715 Hi = DAG.getConstant(0, NVT); 3716 } else if (Cst == NVTBits) { 3717 Lo = InH; 3718 Hi = DAG.getConstant(0, NVT); 3719 } else { 3720 Lo = DAG.getNode(ISD::OR, NVT, 3721 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3722 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3723 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 3724 } 3725 return true; 3726 case ISD::SRA: 3727 if (Cst > VTBits) { 3728 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 3729 DAG.getConstant(NVTBits-1, ShTy)); 3730 } else if (Cst > NVTBits) { 3731 Lo = DAG.getNode(ISD::SRA, NVT, InH, 3732 DAG.getConstant(Cst-NVTBits, ShTy)); 3733 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3734 DAG.getConstant(NVTBits-1, ShTy)); 3735 } else if (Cst == NVTBits) { 3736 Lo = InH; 3737 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3738 DAG.getConstant(NVTBits-1, ShTy)); 3739 } else { 3740 Lo = DAG.getNode(ISD::OR, NVT, 3741 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3742 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3743 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 3744 } 3745 return true; 3746 } 3747 } 3748 return false; 3749} 3750 3751 3752// ExpandLibCall - Expand a node into a call to a libcall. If the result value 3753// does not fit into a register, return the lo part and set the hi part to the 3754// by-reg argument. If it does fit into a single register, return the result 3755// and leave the Hi part unset. 3756SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 3757 SDOperand &Hi) { 3758 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 3759 // The input chain to this libcall is the entry node of the function. 3760 // Legalizing the call will automatically add the previous call to the 3761 // dependence. 3762 SDOperand InChain = DAG.getEntryNode(); 3763 3764 TargetLowering::ArgListTy Args; 3765 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3766 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 3767 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 3768 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 3769 } 3770 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 3771 3772 // Splice the libcall in wherever FindInputOutputChains tells us to. 3773 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 3774 std::pair<SDOperand,SDOperand> CallInfo = 3775 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 3776 Callee, Args, DAG); 3777 3778 // Legalize the call sequence, starting with the chain. This will advance 3779 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 3780 // was added by LowerCallTo (guaranteeing proper serialization of calls). 3781 LegalizeOp(CallInfo.second); 3782 SDOperand Result; 3783 switch (getTypeAction(CallInfo.first.getValueType())) { 3784 default: assert(0 && "Unknown thing"); 3785 case Legal: 3786 Result = CallInfo.first; 3787 break; 3788 case Expand: 3789 ExpandOp(CallInfo.first, Result, Hi); 3790 break; 3791 } 3792 return Result; 3793} 3794 3795 3796/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 3797/// destination type is legal. 3798SDOperand SelectionDAGLegalize:: 3799ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 3800 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 3801 assert(getTypeAction(Source.getValueType()) == Expand && 3802 "This is not an expansion!"); 3803 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 3804 3805 if (!isSigned) { 3806 assert(Source.getValueType() == MVT::i64 && 3807 "This only works for 64-bit -> FP"); 3808 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 3809 // incoming integer is set. To handle this, we dynamically test to see if 3810 // it is set, and, if so, add a fudge factor. 3811 SDOperand Lo, Hi; 3812 ExpandOp(Source, Lo, Hi); 3813 3814 // If this is unsigned, and not supported, first perform the conversion to 3815 // signed, then adjust the result if the sign bit is set. 3816 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 3817 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 3818 3819 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 3820 DAG.getConstant(0, Hi.getValueType()), 3821 ISD::SETLT); 3822 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3823 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3824 SignSet, Four, Zero); 3825 uint64_t FF = 0x5f800000ULL; 3826 if (TLI.isLittleEndian()) FF <<= 32; 3827 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3828 3829 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3830 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3831 SDOperand FudgeInReg; 3832 if (DestTy == MVT::f32) 3833 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3834 DAG.getSrcValue(NULL)); 3835 else { 3836 assert(DestTy == MVT::f64 && "Unexpected conversion"); 3837 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 3838 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 3839 } 3840 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 3841 } 3842 3843 // Check to see if the target has a custom way to lower this. If so, use it. 3844 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 3845 default: assert(0 && "This action not implemented for this operation!"); 3846 case TargetLowering::Legal: 3847 case TargetLowering::Expand: 3848 break; // This case is handled below. 3849 case TargetLowering::Custom: { 3850 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 3851 Source), DAG); 3852 if (NV.Val) 3853 return LegalizeOp(NV); 3854 break; // The target decided this was legal after all 3855 } 3856 } 3857 3858 // Expand the source, then glue it back together for the call. We must expand 3859 // the source in case it is shared (this pass of legalize must traverse it). 3860 SDOperand SrcLo, SrcHi; 3861 ExpandOp(Source, SrcLo, SrcHi); 3862 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3863 3864 const char *FnName = 0; 3865 if (DestTy == MVT::f32) 3866 FnName = "__floatdisf"; 3867 else { 3868 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3869 FnName = "__floatdidf"; 3870 } 3871 3872 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 3873 SDOperand UnusedHiPart; 3874 return ExpandLibCall(FnName, Source.Val, UnusedHiPart); 3875} 3876 3877/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 3878/// INT_TO_FP operation of the specified operand when the target requests that 3879/// we expand it. At this point, we know that the result and operand types are 3880/// legal for the target. 3881SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 3882 SDOperand Op0, 3883 MVT::ValueType DestVT) { 3884 if (Op0.getValueType() == MVT::i32) { 3885 // simple 32-bit [signed|unsigned] integer to float/double expansion 3886 3887 // get the stack frame index of a 8 byte buffer 3888 MachineFunction &MF = DAG.getMachineFunction(); 3889 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 3890 // get address of 8 byte buffer 3891 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3892 // word offset constant for Hi/Lo address computation 3893 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 3894 // set up Hi and Lo (into buffer) address based on endian 3895 SDOperand Hi = StackSlot; 3896 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 3897 if (TLI.isLittleEndian()) 3898 std::swap(Hi, Lo); 3899 3900 // if signed map to unsigned space 3901 SDOperand Op0Mapped; 3902 if (isSigned) { 3903 // constant used to invert sign bit (signed to unsigned mapping) 3904 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 3905 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 3906 } else { 3907 Op0Mapped = Op0; 3908 } 3909 // store the lo of the constructed double - based on integer input 3910 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3911 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 3912 // initial hi portion of constructed double 3913 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 3914 // store the hi of the constructed double - biased exponent 3915 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 3916 InitialHi, Hi, DAG.getSrcValue(NULL)); 3917 // load the constructed double 3918 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 3919 DAG.getSrcValue(NULL)); 3920 // FP constant to bias correct the final result 3921 SDOperand Bias = DAG.getConstantFP(isSigned ? 3922 BitsToDouble(0x4330000080000000ULL) 3923 : BitsToDouble(0x4330000000000000ULL), 3924 MVT::f64); 3925 // subtract the bias 3926 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 3927 // final result 3928 SDOperand Result; 3929 // handle final rounding 3930 if (DestVT == MVT::f64) { 3931 // do nothing 3932 Result = Sub; 3933 } else { 3934 // if f32 then cast to f32 3935 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 3936 } 3937 return Result; 3938 } 3939 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 3940 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 3941 3942 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 3943 DAG.getConstant(0, Op0.getValueType()), 3944 ISD::SETLT); 3945 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3946 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3947 SignSet, Four, Zero); 3948 3949 // If the sign bit of the integer is set, the large number will be treated 3950 // as a negative number. To counteract this, the dynamic code adds an 3951 // offset depending on the data type. 3952 uint64_t FF; 3953 switch (Op0.getValueType()) { 3954 default: assert(0 && "Unsupported integer type!"); 3955 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 3956 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 3957 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 3958 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 3959 } 3960 if (TLI.isLittleEndian()) FF <<= 32; 3961 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3962 3963 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3964 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3965 SDOperand FudgeInReg; 3966 if (DestVT == MVT::f32) 3967 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3968 DAG.getSrcValue(NULL)); 3969 else { 3970 assert(DestVT == MVT::f64 && "Unexpected conversion"); 3971 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 3972 DAG.getEntryNode(), CPIdx, 3973 DAG.getSrcValue(NULL), MVT::f32)); 3974 } 3975 3976 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 3977} 3978 3979/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 3980/// *INT_TO_FP operation of the specified operand when the target requests that 3981/// we promote it. At this point, we know that the result and operand types are 3982/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 3983/// operation that takes a larger input. 3984SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 3985 MVT::ValueType DestVT, 3986 bool isSigned) { 3987 // First step, figure out the appropriate *INT_TO_FP operation to use. 3988 MVT::ValueType NewInTy = LegalOp.getValueType(); 3989 3990 unsigned OpToUse = 0; 3991 3992 // Scan for the appropriate larger type to use. 3993 while (1) { 3994 NewInTy = (MVT::ValueType)(NewInTy+1); 3995 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 3996 3997 // If the target supports SINT_TO_FP of this type, use it. 3998 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 3999 default: break; 4000 case TargetLowering::Legal: 4001 if (!TLI.isTypeLegal(NewInTy)) 4002 break; // Can't use this datatype. 4003 // FALL THROUGH. 4004 case TargetLowering::Custom: 4005 OpToUse = ISD::SINT_TO_FP; 4006 break; 4007 } 4008 if (OpToUse) break; 4009 if (isSigned) continue; 4010 4011 // If the target supports UINT_TO_FP of this type, use it. 4012 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 4013 default: break; 4014 case TargetLowering::Legal: 4015 if (!TLI.isTypeLegal(NewInTy)) 4016 break; // Can't use this datatype. 4017 // FALL THROUGH. 4018 case TargetLowering::Custom: 4019 OpToUse = ISD::UINT_TO_FP; 4020 break; 4021 } 4022 if (OpToUse) break; 4023 4024 // Otherwise, try a larger type. 4025 } 4026 4027 // Okay, we found the operation and type to use. Zero extend our input to the 4028 // desired type then run the operation on it. 4029 return DAG.getNode(OpToUse, DestVT, 4030 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 4031 NewInTy, LegalOp)); 4032} 4033 4034/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 4035/// FP_TO_*INT operation of the specified operand when the target requests that 4036/// we promote it. At this point, we know that the result and operand types are 4037/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 4038/// operation that returns a larger result. 4039SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 4040 MVT::ValueType DestVT, 4041 bool isSigned) { 4042 // First step, figure out the appropriate FP_TO*INT operation to use. 4043 MVT::ValueType NewOutTy = DestVT; 4044 4045 unsigned OpToUse = 0; 4046 4047 // Scan for the appropriate larger type to use. 4048 while (1) { 4049 NewOutTy = (MVT::ValueType)(NewOutTy+1); 4050 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 4051 4052 // If the target supports FP_TO_SINT returning this type, use it. 4053 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 4054 default: break; 4055 case TargetLowering::Legal: 4056 if (!TLI.isTypeLegal(NewOutTy)) 4057 break; // Can't use this datatype. 4058 // FALL THROUGH. 4059 case TargetLowering::Custom: 4060 OpToUse = ISD::FP_TO_SINT; 4061 break; 4062 } 4063 if (OpToUse) break; 4064 4065 // If the target supports FP_TO_UINT of this type, use it. 4066 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 4067 default: break; 4068 case TargetLowering::Legal: 4069 if (!TLI.isTypeLegal(NewOutTy)) 4070 break; // Can't use this datatype. 4071 // FALL THROUGH. 4072 case TargetLowering::Custom: 4073 OpToUse = ISD::FP_TO_UINT; 4074 break; 4075 } 4076 if (OpToUse) break; 4077 4078 // Otherwise, try a larger type. 4079 } 4080 4081 // Okay, we found the operation and type to use. Truncate the result of the 4082 // extended FP_TO_*INT operation to the desired size. 4083 return DAG.getNode(ISD::TRUNCATE, DestVT, 4084 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 4085} 4086 4087/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 4088/// 4089SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 4090 MVT::ValueType VT = Op.getValueType(); 4091 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 4092 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 4093 switch (VT) { 4094 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 4095 case MVT::i16: 4096 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4097 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4098 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 4099 case MVT::i32: 4100 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4101 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4102 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4103 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4104 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 4105 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 4106 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4107 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4108 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4109 case MVT::i64: 4110 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 4111 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 4112 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4113 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4114 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4115 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4116 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 4117 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 4118 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 4119 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 4120 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 4121 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 4122 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 4123 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 4124 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 4125 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 4126 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4127 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4128 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 4129 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4130 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 4131 } 4132} 4133 4134/// ExpandBitCount - Expand the specified bitcount instruction into operations. 4135/// 4136SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 4137 switch (Opc) { 4138 default: assert(0 && "Cannot expand this yet!"); 4139 case ISD::CTPOP: { 4140 static const uint64_t mask[6] = { 4141 0x5555555555555555ULL, 0x3333333333333333ULL, 4142 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 4143 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 4144 }; 4145 MVT::ValueType VT = Op.getValueType(); 4146 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4147 unsigned len = getSizeInBits(VT); 4148 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4149 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 4150 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 4151 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4152 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 4153 DAG.getNode(ISD::AND, VT, 4154 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 4155 } 4156 return Op; 4157 } 4158 case ISD::CTLZ: { 4159 // for now, we do this: 4160 // x = x | (x >> 1); 4161 // x = x | (x >> 2); 4162 // ... 4163 // x = x | (x >>16); 4164 // x = x | (x >>32); // for 64-bit input 4165 // return popcount(~x); 4166 // 4167 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 4168 MVT::ValueType VT = Op.getValueType(); 4169 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4170 unsigned len = getSizeInBits(VT); 4171 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4172 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4173 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 4174 } 4175 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 4176 return DAG.getNode(ISD::CTPOP, VT, Op); 4177 } 4178 case ISD::CTTZ: { 4179 // for now, we use: { return popcount(~x & (x - 1)); } 4180 // unless the target has ctlz but not ctpop, in which case we use: 4181 // { return 32 - nlz(~x & (x-1)); } 4182 // see also http://www.hackersdelight.org/HDcode/ntz.cc 4183 MVT::ValueType VT = Op.getValueType(); 4184 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 4185 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 4186 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 4187 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 4188 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 4189 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 4190 TLI.isOperationLegal(ISD::CTLZ, VT)) 4191 return DAG.getNode(ISD::SUB, VT, 4192 DAG.getConstant(getSizeInBits(VT), VT), 4193 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 4194 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 4195 } 4196 } 4197} 4198 4199/// ExpandOp - Expand the specified SDOperand into its two component pieces 4200/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 4201/// LegalizeNodes map is filled in for any results that are not expanded, the 4202/// ExpandedNodes map is filled in for any results that are expanded, and the 4203/// Lo/Hi values are returned. 4204void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 4205 MVT::ValueType VT = Op.getValueType(); 4206 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4207 SDNode *Node = Op.Val; 4208 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 4209 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 4210 "Cannot expand FP values!"); 4211 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 4212 "Cannot expand to FP value or to larger int value!"); 4213 4214 // See if we already expanded it. 4215 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 4216 = ExpandedNodes.find(Op); 4217 if (I != ExpandedNodes.end()) { 4218 Lo = I->second.first; 4219 Hi = I->second.second; 4220 return; 4221 } 4222 4223 switch (Node->getOpcode()) { 4224 case ISD::CopyFromReg: 4225 assert(0 && "CopyFromReg must be legal!"); 4226 default: 4227#ifndef NDEBUG 4228 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 4229#endif 4230 assert(0 && "Do not know how to expand this operator!"); 4231 abort(); 4232 case ISD::UNDEF: 4233 Lo = DAG.getNode(ISD::UNDEF, NVT); 4234 Hi = DAG.getNode(ISD::UNDEF, NVT); 4235 break; 4236 case ISD::Constant: { 4237 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 4238 Lo = DAG.getConstant(Cst, NVT); 4239 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 4240 break; 4241 } 4242 case ISD::BUILD_PAIR: 4243 // Return the operands. 4244 Lo = Node->getOperand(0); 4245 Hi = Node->getOperand(1); 4246 break; 4247 4248 case ISD::SIGN_EXTEND_INREG: 4249 ExpandOp(Node->getOperand(0), Lo, Hi); 4250 // Sign extend the lo-part. 4251 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4252 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 4253 TLI.getShiftAmountTy())); 4254 // sext_inreg the low part if needed. 4255 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 4256 break; 4257 4258 case ISD::BSWAP: { 4259 ExpandOp(Node->getOperand(0), Lo, Hi); 4260 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 4261 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 4262 Lo = TempLo; 4263 break; 4264 } 4265 4266 case ISD::CTPOP: 4267 ExpandOp(Node->getOperand(0), Lo, Hi); 4268 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 4269 DAG.getNode(ISD::CTPOP, NVT, Lo), 4270 DAG.getNode(ISD::CTPOP, NVT, Hi)); 4271 Hi = DAG.getConstant(0, NVT); 4272 break; 4273 4274 case ISD::CTLZ: { 4275 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 4276 ExpandOp(Node->getOperand(0), Lo, Hi); 4277 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4278 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 4279 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 4280 ISD::SETNE); 4281 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 4282 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 4283 4284 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 4285 Hi = DAG.getConstant(0, NVT); 4286 break; 4287 } 4288 4289 case ISD::CTTZ: { 4290 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 4291 ExpandOp(Node->getOperand(0), Lo, Hi); 4292 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4293 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 4294 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 4295 ISD::SETNE); 4296 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 4297 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 4298 4299 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 4300 Hi = DAG.getConstant(0, NVT); 4301 break; 4302 } 4303 4304 case ISD::VAARG: { 4305 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 4306 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 4307 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 4308 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 4309 4310 // Remember that we legalized the chain. 4311 Hi = LegalizeOp(Hi); 4312 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 4313 if (!TLI.isLittleEndian()) 4314 std::swap(Lo, Hi); 4315 break; 4316 } 4317 4318 case ISD::LOAD: { 4319 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 4320 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 4321 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 4322 4323 // Increment the pointer to the other half. 4324 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 4325 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4326 getIntPtrConstant(IncrementSize)); 4327 // FIXME: This creates a bogus srcvalue! 4328 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 4329 4330 // Build a factor node to remember that this load is independent of the 4331 // other one. 4332 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 4333 Hi.getValue(1)); 4334 4335 // Remember that we legalized the chain. 4336 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 4337 if (!TLI.isLittleEndian()) 4338 std::swap(Lo, Hi); 4339 break; 4340 } 4341 case ISD::AND: 4342 case ISD::OR: 4343 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 4344 SDOperand LL, LH, RL, RH; 4345 ExpandOp(Node->getOperand(0), LL, LH); 4346 ExpandOp(Node->getOperand(1), RL, RH); 4347 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 4348 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 4349 break; 4350 } 4351 case ISD::SELECT: { 4352 SDOperand LL, LH, RL, RH; 4353 ExpandOp(Node->getOperand(1), LL, LH); 4354 ExpandOp(Node->getOperand(2), RL, RH); 4355 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 4356 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 4357 break; 4358 } 4359 case ISD::SELECT_CC: { 4360 SDOperand TL, TH, FL, FH; 4361 ExpandOp(Node->getOperand(2), TL, TH); 4362 ExpandOp(Node->getOperand(3), FL, FH); 4363 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4364 Node->getOperand(1), TL, FL, Node->getOperand(4)); 4365 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4366 Node->getOperand(1), TH, FH, Node->getOperand(4)); 4367 break; 4368 } 4369 case ISD::SEXTLOAD: { 4370 SDOperand Chain = Node->getOperand(0); 4371 SDOperand Ptr = Node->getOperand(1); 4372 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4373 4374 if (EVT == NVT) 4375 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 4376 else 4377 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 4378 EVT); 4379 4380 // Remember that we legalized the chain. 4381 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4382 4383 // The high part is obtained by SRA'ing all but one of the bits of the lo 4384 // part. 4385 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4386 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 4387 TLI.getShiftAmountTy())); 4388 break; 4389 } 4390 case ISD::ZEXTLOAD: { 4391 SDOperand Chain = Node->getOperand(0); 4392 SDOperand Ptr = Node->getOperand(1); 4393 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4394 4395 if (EVT == NVT) 4396 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 4397 else 4398 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 4399 EVT); 4400 4401 // Remember that we legalized the chain. 4402 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4403 4404 // The high part is just a zero. 4405 Hi = DAG.getConstant(0, NVT); 4406 break; 4407 } 4408 case ISD::EXTLOAD: { 4409 SDOperand Chain = Node->getOperand(0); 4410 SDOperand Ptr = Node->getOperand(1); 4411 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4412 4413 if (EVT == NVT) 4414 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 4415 else 4416 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 4417 EVT); 4418 4419 // Remember that we legalized the chain. 4420 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4421 4422 // The high part is undefined. 4423 Hi = DAG.getNode(ISD::UNDEF, NVT); 4424 break; 4425 } 4426 case ISD::ANY_EXTEND: 4427 // The low part is any extension of the input (which degenerates to a copy). 4428 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 4429 // The high part is undefined. 4430 Hi = DAG.getNode(ISD::UNDEF, NVT); 4431 break; 4432 case ISD::SIGN_EXTEND: { 4433 // The low part is just a sign extension of the input (which degenerates to 4434 // a copy). 4435 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 4436 4437 // The high part is obtained by SRA'ing all but one of the bits of the lo 4438 // part. 4439 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4440 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4441 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 4442 break; 4443 } 4444 case ISD::ZERO_EXTEND: 4445 // The low part is just a zero extension of the input (which degenerates to 4446 // a copy). 4447 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4448 4449 // The high part is just a zero. 4450 Hi = DAG.getConstant(0, NVT); 4451 break; 4452 4453 case ISD::BIT_CONVERT: { 4454 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0), 4455 Node->getOperand(0)); 4456 ExpandOp(Tmp, Lo, Hi); 4457 break; 4458 } 4459 4460 case ISD::READCYCLECOUNTER: 4461 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 4462 TargetLowering::Custom && 4463 "Must custom expand ReadCycleCounter"); 4464 Lo = TLI.LowerOperation(Op, DAG); 4465 assert(Lo.Val && "Node must be custom expanded!"); 4466 Hi = Lo.getValue(1); 4467 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 4468 LegalizeOp(Lo.getValue(2))); 4469 break; 4470 4471 // These operators cannot be expanded directly, emit them as calls to 4472 // library functions. 4473 case ISD::FP_TO_SINT: 4474 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 4475 SDOperand Op; 4476 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4477 case Expand: assert(0 && "cannot expand FP!"); 4478 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 4479 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 4480 } 4481 4482 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 4483 4484 // Now that the custom expander is done, expand the result, which is still 4485 // VT. 4486 if (Op.Val) { 4487 ExpandOp(Op, Lo, Hi); 4488 break; 4489 } 4490 } 4491 4492 if (Node->getOperand(0).getValueType() == MVT::f32) 4493 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 4494 else 4495 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 4496 break; 4497 4498 case ISD::FP_TO_UINT: 4499 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 4500 SDOperand Op; 4501 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4502 case Expand: assert(0 && "cannot expand FP!"); 4503 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 4504 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 4505 } 4506 4507 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 4508 4509 // Now that the custom expander is done, expand the result. 4510 if (Op.Val) { 4511 ExpandOp(Op, Lo, Hi); 4512 break; 4513 } 4514 } 4515 4516 if (Node->getOperand(0).getValueType() == MVT::f32) 4517 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 4518 else 4519 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 4520 break; 4521 4522 case ISD::SHL: { 4523 // If the target wants custom lowering, do so. 4524 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4525 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 4526 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 4527 Op = TLI.LowerOperation(Op, DAG); 4528 if (Op.Val) { 4529 // Now that the custom expander is done, expand the result, which is 4530 // still VT. 4531 ExpandOp(Op, Lo, Hi); 4532 break; 4533 } 4534 } 4535 4536 // If we can emit an efficient shift operation, do so now. 4537 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4538 break; 4539 4540 // If this target supports SHL_PARTS, use it. 4541 TargetLowering::LegalizeAction Action = 4542 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 4543 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4544 Action == TargetLowering::Custom) { 4545 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4546 break; 4547 } 4548 4549 // Otherwise, emit a libcall. 4550 Lo = ExpandLibCall("__ashldi3", Node, Hi); 4551 break; 4552 } 4553 4554 case ISD::SRA: { 4555 // If the target wants custom lowering, do so. 4556 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4557 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 4558 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 4559 Op = TLI.LowerOperation(Op, DAG); 4560 if (Op.Val) { 4561 // Now that the custom expander is done, expand the result, which is 4562 // still VT. 4563 ExpandOp(Op, Lo, Hi); 4564 break; 4565 } 4566 } 4567 4568 // If we can emit an efficient shift operation, do so now. 4569 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4570 break; 4571 4572 // If this target supports SRA_PARTS, use it. 4573 TargetLowering::LegalizeAction Action = 4574 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 4575 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4576 Action == TargetLowering::Custom) { 4577 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4578 break; 4579 } 4580 4581 // Otherwise, emit a libcall. 4582 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 4583 break; 4584 } 4585 4586 case ISD::SRL: { 4587 // If the target wants custom lowering, do so. 4588 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4589 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 4590 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 4591 Op = TLI.LowerOperation(Op, DAG); 4592 if (Op.Val) { 4593 // Now that the custom expander is done, expand the result, which is 4594 // still VT. 4595 ExpandOp(Op, Lo, Hi); 4596 break; 4597 } 4598 } 4599 4600 // If we can emit an efficient shift operation, do so now. 4601 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4602 break; 4603 4604 // If this target supports SRL_PARTS, use it. 4605 TargetLowering::LegalizeAction Action = 4606 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 4607 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4608 Action == TargetLowering::Custom) { 4609 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4610 break; 4611 } 4612 4613 // Otherwise, emit a libcall. 4614 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 4615 break; 4616 } 4617 4618 case ISD::ADD: 4619 case ISD::SUB: { 4620 // If the target wants to custom expand this, let them. 4621 if (TLI.getOperationAction(Node->getOpcode(), VT) == 4622 TargetLowering::Custom) { 4623 Op = TLI.LowerOperation(Op, DAG); 4624 if (Op.Val) { 4625 ExpandOp(Op, Lo, Hi); 4626 break; 4627 } 4628 } 4629 4630 // Expand the subcomponents. 4631 SDOperand LHSL, LHSH, RHSL, RHSH; 4632 ExpandOp(Node->getOperand(0), LHSL, LHSH); 4633 ExpandOp(Node->getOperand(1), RHSL, RHSH); 4634 std::vector<MVT::ValueType> VTs; 4635 std::vector<SDOperand> LoOps, HiOps; 4636 VTs.push_back(LHSL.getValueType()); 4637 VTs.push_back(MVT::Flag); 4638 LoOps.push_back(LHSL); 4639 LoOps.push_back(RHSL); 4640 HiOps.push_back(LHSH); 4641 HiOps.push_back(RHSH); 4642 if (Node->getOpcode() == ISD::ADD) { 4643 Lo = DAG.getNode(ISD::ADDC, VTs, LoOps); 4644 HiOps.push_back(Lo.getValue(1)); 4645 Hi = DAG.getNode(ISD::ADDE, VTs, HiOps); 4646 } else { 4647 Lo = DAG.getNode(ISD::SUBC, VTs, LoOps); 4648 HiOps.push_back(Lo.getValue(1)); 4649 Hi = DAG.getNode(ISD::SUBE, VTs, HiOps); 4650 } 4651 break; 4652 } 4653 case ISD::MUL: { 4654 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 4655 SDOperand LL, LH, RL, RH; 4656 ExpandOp(Node->getOperand(0), LL, LH); 4657 ExpandOp(Node->getOperand(1), RL, RH); 4658 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 4659 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 4660 // extended the sign bit of the low half through the upper half, and if so 4661 // emit a MULHS instead of the alternate sequence that is valid for any 4662 // i64 x i64 multiply. 4663 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 4664 // is RH an extension of the sign bit of RL? 4665 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 4666 RH.getOperand(1).getOpcode() == ISD::Constant && 4667 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 4668 // is LH an extension of the sign bit of LL? 4669 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 4670 LH.getOperand(1).getOpcode() == ISD::Constant && 4671 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 4672 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 4673 } else { 4674 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 4675 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 4676 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 4677 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 4678 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 4679 } 4680 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 4681 } else { 4682 Lo = ExpandLibCall("__muldi3" , Node, Hi); 4683 } 4684 break; 4685 } 4686 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 4687 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 4688 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 4689 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 4690 } 4691 4692 // Make sure the resultant values have been legalized themselves, unless this 4693 // is a type that requires multi-step expansion. 4694 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 4695 Lo = LegalizeOp(Lo); 4696 Hi = LegalizeOp(Hi); 4697 } 4698 4699 // Remember in a map if the values will be reused later. 4700 bool isNew = 4701 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 4702 assert(isNew && "Value already expanded?!?"); 4703} 4704 4705/// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 4706/// two smaller values of MVT::Vector type. 4707void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 4708 SDOperand &Hi) { 4709 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!"); 4710 SDNode *Node = Op.Val; 4711 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue(); 4712 assert(NumElements > 1 && "Cannot split a single element vector!"); 4713 unsigned NewNumElts = NumElements/2; 4714 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32); 4715 SDOperand TypeNode = *(Node->op_end()-1); 4716 4717 // See if we already split it. 4718 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 4719 = SplitNodes.find(Op); 4720 if (I != SplitNodes.end()) { 4721 Lo = I->second.first; 4722 Hi = I->second.second; 4723 return; 4724 } 4725 4726 switch (Node->getOpcode()) { 4727 default: 4728#ifndef NDEBUG 4729 Node->dump(); 4730#endif 4731 assert(0 && "Unhandled operation in SplitVectorOp!"); 4732 case ISD::VBUILD_VECTOR: { 4733 std::vector<SDOperand> LoOps(Node->op_begin(), Node->op_begin()+NewNumElts); 4734 LoOps.push_back(NewNumEltsNode); 4735 LoOps.push_back(TypeNode); 4736 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps); 4737 4738 std::vector<SDOperand> HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2); 4739 HiOps.push_back(NewNumEltsNode); 4740 HiOps.push_back(TypeNode); 4741 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps); 4742 break; 4743 } 4744 case ISD::VADD: 4745 case ISD::VSUB: 4746 case ISD::VMUL: 4747 case ISD::VSDIV: 4748 case ISD::VUDIV: 4749 case ISD::VAND: 4750 case ISD::VOR: 4751 case ISD::VXOR: { 4752 SDOperand LL, LH, RL, RH; 4753 SplitVectorOp(Node->getOperand(0), LL, LH); 4754 SplitVectorOp(Node->getOperand(1), RL, RH); 4755 4756 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, 4757 NewNumEltsNode, TypeNode); 4758 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, 4759 NewNumEltsNode, TypeNode); 4760 break; 4761 } 4762 case ISD::VLOAD: { 4763 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 4764 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 4765 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 4766 4767 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 4768 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8; 4769 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4770 getIntPtrConstant(IncrementSize)); 4771 // FIXME: This creates a bogus srcvalue! 4772 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 4773 4774 // Build a factor node to remember that this load is independent of the 4775 // other one. 4776 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 4777 Hi.getValue(1)); 4778 4779 // Remember that we legalized the chain. 4780 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 4781 break; 4782 } 4783 case ISD::VBIT_CONVERT: { 4784 // We know the result is a vector. The input may be either a vector or a 4785 // scalar value. 4786 if (Op.getOperand(0).getValueType() != MVT::Vector) { 4787 // Lower to a store/load. FIXME: this could be improved probably. 4788 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType()); 4789 4790 SDOperand St = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 4791 Op.getOperand(0), Ptr, DAG.getSrcValue(0)); 4792 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 4793 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0)); 4794 SplitVectorOp(St, Lo, Hi); 4795 } else { 4796 // If the input is a vector type, we have to either scalarize it, pack it 4797 // or convert it based on whether the input vector type is legal. 4798 SDNode *InVal = Node->getOperand(0).Val; 4799 unsigned NumElems = 4800 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 4801 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 4802 4803 // If the input is from a single element vector, scalarize the vector, 4804 // then treat like a scalar. 4805 if (NumElems == 1) { 4806 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT); 4807 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar, 4808 Op.getOperand(1), Op.getOperand(2)); 4809 SplitVectorOp(Scalar, Lo, Hi); 4810 } else { 4811 // Split the input vector. 4812 SplitVectorOp(Op.getOperand(0), Lo, Hi); 4813 4814 // Convert each of the pieces now. 4815 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo, 4816 NewNumEltsNode, TypeNode); 4817 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi, 4818 NewNumEltsNode, TypeNode); 4819 } 4820 break; 4821 } 4822 } 4823 } 4824 4825 // Remember in a map if the values will be reused later. 4826 bool isNew = 4827 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 4828 assert(isNew && "Value already expanded?!?"); 4829} 4830 4831 4832/// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 4833/// equivalent operation that returns a scalar (e.g. F32) or packed value 4834/// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right 4835/// type for the result. 4836SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, 4837 MVT::ValueType NewVT) { 4838 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!"); 4839 SDNode *Node = Op.Val; 4840 4841 // See if we already packed it. 4842 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op); 4843 if (I != PackedNodes.end()) return I->second; 4844 4845 SDOperand Result; 4846 switch (Node->getOpcode()) { 4847 default: 4848#ifndef NDEBUG 4849 Node->dump(); std::cerr << "\n"; 4850#endif 4851 assert(0 && "Unknown vector operation in PackVectorOp!"); 4852 case ISD::VADD: 4853 case ISD::VSUB: 4854 case ISD::VMUL: 4855 case ISD::VSDIV: 4856 case ISD::VUDIV: 4857 case ISD::VAND: 4858 case ISD::VOR: 4859 case ISD::VXOR: 4860 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT), 4861 NewVT, 4862 PackVectorOp(Node->getOperand(0), NewVT), 4863 PackVectorOp(Node->getOperand(1), NewVT)); 4864 break; 4865 case ISD::VLOAD: { 4866 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 4867 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 4868 4869 Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2)); 4870 4871 // Remember that we legalized the chain. 4872 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4873 break; 4874 } 4875 case ISD::VBUILD_VECTOR: 4876 if (Node->getOperand(0).getValueType() == NewVT) { 4877 // Returning a scalar? 4878 Result = Node->getOperand(0); 4879 } else { 4880 // Returning a BUILD_VECTOR? 4881 4882 // If all elements of the build_vector are undefs, return an undef. 4883 bool AllUndef = true; 4884 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i) 4885 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) { 4886 AllUndef = false; 4887 break; 4888 } 4889 if (AllUndef) { 4890 Result = DAG.getNode(ISD::UNDEF, NewVT); 4891 } else { 4892 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2); 4893 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops); 4894 } 4895 } 4896 break; 4897 case ISD::VINSERT_VECTOR_ELT: 4898 if (!MVT::isVector(NewVT)) { 4899 // Returning a scalar? Must be the inserted element. 4900 Result = Node->getOperand(1); 4901 } else { 4902 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, 4903 PackVectorOp(Node->getOperand(0), NewVT), 4904 Node->getOperand(1), Node->getOperand(2)); 4905 } 4906 break; 4907 case ISD::VVECTOR_SHUFFLE: 4908 if (!MVT::isVector(NewVT)) { 4909 // Returning a scalar? Figure out if it is the LHS or RHS and return it. 4910 SDOperand EltNum = Node->getOperand(2).getOperand(0); 4911 if (cast<ConstantSDNode>(EltNum)->getValue()) 4912 Result = PackVectorOp(Node->getOperand(1), NewVT); 4913 else 4914 Result = PackVectorOp(Node->getOperand(0), NewVT); 4915 } else { 4916 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index 4917 // vector from a VBUILD_VECTOR to a BUILD_VECTOR. 4918 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(), 4919 Node->getOperand(2).Val->op_end()-2); 4920 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size()); 4921 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, BuildVecIdx); 4922 4923 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, 4924 PackVectorOp(Node->getOperand(0), NewVT), 4925 PackVectorOp(Node->getOperand(1), NewVT), BV); 4926 } 4927 break; 4928 case ISD::VBIT_CONVERT: 4929 if (Op.getOperand(0).getValueType() != MVT::Vector) 4930 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 4931 else { 4932 // If the input is a vector type, we have to either scalarize it, pack it 4933 // or convert it based on whether the input vector type is legal. 4934 SDNode *InVal = Node->getOperand(0).Val; 4935 unsigned NumElems = 4936 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 4937 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 4938 4939 // Figure out if there is a Packed type corresponding to this Vector 4940 // type. If so, convert to the packed type. 4941 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 4942 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 4943 // Turn this into a bit convert of the packed input. 4944 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 4945 PackVectorOp(Node->getOperand(0), TVT)); 4946 break; 4947 } else if (NumElems == 1) { 4948 // Turn this into a bit convert of the scalar input. 4949 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 4950 PackVectorOp(Node->getOperand(0), EVT)); 4951 break; 4952 } else { 4953 // FIXME: UNIMP! 4954 assert(0 && "Cast from unsupported vector type not implemented yet!"); 4955 } 4956 } 4957 break; 4958 case ISD::VSELECT: 4959 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 4960 PackVectorOp(Op.getOperand(1), NewVT), 4961 PackVectorOp(Op.getOperand(2), NewVT)); 4962 break; 4963 } 4964 4965 if (TLI.isTypeLegal(NewVT)) 4966 Result = LegalizeOp(Result); 4967 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second; 4968 assert(isNew && "Value already packed?"); 4969 return Result; 4970} 4971 4972 4973// SelectionDAG::Legalize - This is the entry point for the file. 4974// 4975void SelectionDAG::Legalize() { 4976 if (ViewLegalizeDAGs) viewGraph(); 4977 4978 /// run - This is the main entry point to this class. 4979 /// 4980 SelectionDAGLegalize(*this).LegalizeDAG(); 4981} 4982 4983