LegalizeDAG.cpp revision 19dc8c9bcd5007ca61d8b42d363602a24216f0a6
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/Analysis/DebugInfo.h" 20#include "llvm/CodeGen/PseudoSourceValue.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetOptions.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Function.h" 30#include "llvm/GlobalVariable.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/ADT/DenseMap.h" 37#include "llvm/ADT/SmallVector.h" 38#include "llvm/ADT/SmallPtrSet.h" 39using namespace llvm; 40 41//===----------------------------------------------------------------------===// 42/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 43/// hacks on it until the target machine can handle it. This involves 44/// eliminating value sizes the machine cannot handle (promoting small sizes to 45/// large sizes or splitting up large values into small values) as well as 46/// eliminating operations the machine cannot handle. 47/// 48/// This code also does a small amount of optimization and recognition of idioms 49/// as part of its processing. For example, if a target does not support a 50/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 51/// will attempt merge setcc and brc instructions into brcc's. 52/// 53namespace { 54class SelectionDAGLegalize { 55 const TargetMachine &TM; 56 const TargetLowering &TLI; 57 SelectionDAG &DAG; 58 CodeGenOpt::Level OptLevel; 59 60 // Libcall insertion helpers. 61 62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 63 /// legalized. We use this to ensure that calls are properly serialized 64 /// against each other, including inserted libcalls. 65 SDValue LastCALLSEQ_END; 66 67 /// IsLegalizingCall - This member is used *only* for purposes of providing 68 /// helpful assertions that a libcall isn't created while another call is 69 /// being legalized (which could lead to non-serialized call sequences). 70 bool IsLegalizingCall; 71 72 enum LegalizeAction { 73 Legal, // The target natively supports this operation. 74 Promote, // This operation should be executed in a larger type. 75 Expand // Try to expand this to other ops, otherwise use a libcall. 76 }; 77 78 /// ValueTypeActions - This is a bitvector that contains two bits for each 79 /// value type, where the two bits correspond to the LegalizeAction enum. 80 /// This can be queried with "getTypeAction(VT)". 81 TargetLowering::ValueTypeActionImpl ValueTypeActions; 82 83 /// LegalizedNodes - For nodes that are of legal width, and that have more 84 /// than one use, this map indicates what regularized operand to use. This 85 /// allows us to avoid legalizing the same thing more than once. 86 DenseMap<SDValue, SDValue> LegalizedNodes; 87 88 void AddLegalizedOperand(SDValue From, SDValue To) { 89 LegalizedNodes.insert(std::make_pair(From, To)); 90 // If someone requests legalization of the new node, return itself. 91 if (From != To) 92 LegalizedNodes.insert(std::make_pair(To, To)); 93 } 94 95public: 96 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 97 98 /// getTypeAction - Return how we should legalize values of this type, either 99 /// it is already legal or we need to expand it into multiple registers of 100 /// smaller integer type, or we need to promote it to a larger type. 101 LegalizeAction getTypeAction(EVT VT) const { 102 return 103 (LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT); 104 } 105 106 /// isTypeLegal - Return true if this type is legal on this target. 107 /// 108 bool isTypeLegal(EVT VT) const { 109 return getTypeAction(VT) == Legal; 110 } 111 112 void LegalizeDAG(); 113 114private: 115 /// LegalizeOp - We know that the specified value has a legal type. 116 /// Recursively ensure that the operands have legal types, then return the 117 /// result. 118 SDValue LegalizeOp(SDValue O); 119 120 SDValue OptimizeFloatStore(StoreSDNode *ST); 121 122 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 123 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 124 /// is necessary to spill the vector being inserted into to memory, perform 125 /// the insert there, and then read the result back. 126 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 127 SDValue Idx, DebugLoc dl); 128 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 129 SDValue Idx, DebugLoc dl); 130 131 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 132 /// performs the same shuffe in terms of order or result bytes, but on a type 133 /// whose vector element type is narrower than the original shuffle type. 134 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 135 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 136 SDValue N1, SDValue N2, 137 SmallVectorImpl<int> &Mask) const; 138 139 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 140 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 141 142 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 143 DebugLoc dl); 144 145 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 146 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 147 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 148 RTLIB::Libcall Call_PPCF128); 149 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 150 RTLIB::Libcall Call_I8, 151 RTLIB::Libcall Call_I16, 152 RTLIB::Libcall Call_I32, 153 RTLIB::Libcall Call_I64, 154 RTLIB::Libcall Call_I128); 155 156 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 157 SDValue ExpandBUILD_VECTOR(SDNode *Node); 158 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 159 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 160 SmallVectorImpl<SDValue> &Results); 161 SDValue ExpandFCOPYSIGN(SDNode *Node); 162 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 163 DebugLoc dl); 164 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 165 DebugLoc dl); 166 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 167 DebugLoc dl); 168 169 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 170 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 171 172 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 173 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 174 175 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 176 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 177}; 178} 179 180/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 181/// performs the same shuffe in terms of order or result bytes, but on a type 182/// whose vector element type is narrower than the original shuffle type. 183/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 184SDValue 185SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 186 SDValue N1, SDValue N2, 187 SmallVectorImpl<int> &Mask) const { 188 unsigned NumMaskElts = VT.getVectorNumElements(); 189 unsigned NumDestElts = NVT.getVectorNumElements(); 190 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 191 192 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 193 194 if (NumEltsGrowth == 1) 195 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 196 197 SmallVector<int, 8> NewMask; 198 for (unsigned i = 0; i != NumMaskElts; ++i) { 199 int Idx = Mask[i]; 200 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 201 if (Idx < 0) 202 NewMask.push_back(-1); 203 else 204 NewMask.push_back(Idx * NumEltsGrowth + j); 205 } 206 } 207 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 208 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 209 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 210} 211 212SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 213 CodeGenOpt::Level ol) 214 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 215 DAG(dag), OptLevel(ol), 216 ValueTypeActions(TLI.getValueTypeActions()) { 217 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 218 "Too many value types for ValueTypeActions to hold!"); 219} 220 221void SelectionDAGLegalize::LegalizeDAG() { 222 LastCALLSEQ_END = DAG.getEntryNode(); 223 IsLegalizingCall = false; 224 225 // The legalize process is inherently a bottom-up recursive process (users 226 // legalize their uses before themselves). Given infinite stack space, we 227 // could just start legalizing on the root and traverse the whole graph. In 228 // practice however, this causes us to run out of stack space on large basic 229 // blocks. To avoid this problem, compute an ordering of the nodes where each 230 // node is only legalized after all of its operands are legalized. 231 DAG.AssignTopologicalOrder(); 232 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 233 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 234 LegalizeOp(SDValue(I, 0)); 235 236 // Finally, it's possible the root changed. Get the new root. 237 SDValue OldRoot = DAG.getRoot(); 238 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 239 DAG.setRoot(LegalizedNodes[OldRoot]); 240 241 LegalizedNodes.clear(); 242 243 // Remove dead nodes now. 244 DAG.RemoveDeadNodes(); 245} 246 247 248/// FindCallEndFromCallStart - Given a chained node that is part of a call 249/// sequence, find the CALLSEQ_END node that terminates the call sequence. 250static SDNode *FindCallEndFromCallStart(SDNode *Node) { 251 if (Node->getOpcode() == ISD::CALLSEQ_END) 252 return Node; 253 if (Node->use_empty()) 254 return 0; // No CallSeqEnd 255 256 // The chain is usually at the end. 257 SDValue TheChain(Node, Node->getNumValues()-1); 258 if (TheChain.getValueType() != MVT::Other) { 259 // Sometimes it's at the beginning. 260 TheChain = SDValue(Node, 0); 261 if (TheChain.getValueType() != MVT::Other) { 262 // Otherwise, hunt for it. 263 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 264 if (Node->getValueType(i) == MVT::Other) { 265 TheChain = SDValue(Node, i); 266 break; 267 } 268 269 // Otherwise, we walked into a node without a chain. 270 if (TheChain.getValueType() != MVT::Other) 271 return 0; 272 } 273 } 274 275 for (SDNode::use_iterator UI = Node->use_begin(), 276 E = Node->use_end(); UI != E; ++UI) { 277 278 // Make sure to only follow users of our token chain. 279 SDNode *User = *UI; 280 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 281 if (User->getOperand(i) == TheChain) 282 if (SDNode *Result = FindCallEndFromCallStart(User)) 283 return Result; 284 } 285 return 0; 286} 287 288/// FindCallStartFromCallEnd - Given a chained node that is part of a call 289/// sequence, find the CALLSEQ_START node that initiates the call sequence. 290static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 291 assert(Node && "Didn't find callseq_start for a call??"); 292 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 293 294 assert(Node->getOperand(0).getValueType() == MVT::Other && 295 "Node doesn't have a token chain argument!"); 296 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 297} 298 299/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 300/// see if any uses can reach Dest. If no dest operands can get to dest, 301/// legalize them, legalize ourself, and return false, otherwise, return true. 302/// 303/// Keep track of the nodes we fine that actually do lead to Dest in 304/// NodesLeadingTo. This avoids retraversing them exponential number of times. 305/// 306bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 307 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 308 if (N == Dest) return true; // N certainly leads to Dest :) 309 310 // If we've already processed this node and it does lead to Dest, there is no 311 // need to reprocess it. 312 if (NodesLeadingTo.count(N)) return true; 313 314 // If the first result of this node has been already legalized, then it cannot 315 // reach N. 316 if (LegalizedNodes.count(SDValue(N, 0))) return false; 317 318 // Okay, this node has not already been legalized. Check and legalize all 319 // operands. If none lead to Dest, then we can legalize this node. 320 bool OperandsLeadToDest = false; 321 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 322 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 323 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 324 325 if (OperandsLeadToDest) { 326 NodesLeadingTo.insert(N); 327 return true; 328 } 329 330 // Okay, this node looks safe, legalize it and return false. 331 LegalizeOp(SDValue(N, 0)); 332 return false; 333} 334 335/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 336/// a load from the constant pool. 337static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 338 SelectionDAG &DAG, const TargetLowering &TLI) { 339 bool Extend = false; 340 DebugLoc dl = CFP->getDebugLoc(); 341 342 // If a FP immediate is precise when represented as a float and if the 343 // target can do an extending load from float to double, we put it into 344 // the constant pool as a float, even if it's is statically typed as a 345 // double. This shrinks FP constants and canonicalizes them for targets where 346 // an FP extending load is the same cost as a normal load (such as on the x87 347 // fp stack or PPC FP unit). 348 EVT VT = CFP->getValueType(0); 349 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 350 if (!UseCP) { 351 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 352 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 353 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 354 } 355 356 EVT OrigVT = VT; 357 EVT SVT = VT; 358 while (SVT != MVT::f32) { 359 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 360 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 361 // Only do this if the target has a native EXTLOAD instruction from 362 // smaller type. 363 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 364 TLI.ShouldShrinkFPConstant(OrigVT)) { 365 const Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 366 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 367 VT = SVT; 368 Extend = true; 369 } 370 } 371 372 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 373 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 374 if (Extend) 375 return DAG.getExtLoad(ISD::EXTLOAD, dl, 376 OrigVT, DAG.getEntryNode(), 377 CPIdx, PseudoSourceValue::getConstantPool(), 378 0, VT, false, false, Alignment); 379 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 380 PseudoSourceValue::getConstantPool(), 0, false, false, 381 Alignment); 382} 383 384/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 385static 386SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 387 const TargetLowering &TLI) { 388 SDValue Chain = ST->getChain(); 389 SDValue Ptr = ST->getBasePtr(); 390 SDValue Val = ST->getValue(); 391 EVT VT = Val.getValueType(); 392 int Alignment = ST->getAlignment(); 393 int SVOffset = ST->getSrcValueOffset(); 394 DebugLoc dl = ST->getDebugLoc(); 395 if (ST->getMemoryVT().isFloatingPoint() || 396 ST->getMemoryVT().isVector()) { 397 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 398 if (TLI.isTypeLegal(intVT)) { 399 // Expand to a bitconvert of the value to the integer type of the 400 // same size, then a (misaligned) int store. 401 // FIXME: Does not handle truncating floating point stores! 402 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 403 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 404 SVOffset, ST->isVolatile(), ST->isNonTemporal(), 405 Alignment); 406 } else { 407 // Do a (aligned) store to a stack slot, then copy from the stack slot 408 // to the final destination using (unaligned) integer loads and stores. 409 EVT StoredVT = ST->getMemoryVT(); 410 EVT RegVT = 411 TLI.getRegisterType(*DAG.getContext(), 412 EVT::getIntegerVT(*DAG.getContext(), 413 StoredVT.getSizeInBits())); 414 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 415 unsigned RegBytes = RegVT.getSizeInBits() / 8; 416 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 417 418 // Make sure the stack slot is also aligned for the register type. 419 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 420 421 // Perform the original store, only redirected to the stack slot. 422 SDValue Store = DAG.getTruncStore(Chain, dl, 423 Val, StackPtr, NULL, 0, StoredVT, 424 false, false, 0); 425 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 426 SmallVector<SDValue, 8> Stores; 427 unsigned Offset = 0; 428 429 // Do all but one copies using the full register width. 430 for (unsigned i = 1; i < NumRegs; i++) { 431 // Load one integer register's worth from the stack slot. 432 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0, 433 false, false, 0); 434 // Store it to the final location. Remember the store. 435 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 436 ST->getSrcValue(), SVOffset + Offset, 437 ST->isVolatile(), ST->isNonTemporal(), 438 MinAlign(ST->getAlignment(), Offset))); 439 // Increment the pointers. 440 Offset += RegBytes; 441 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 442 Increment); 443 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 444 } 445 446 // The last store may be partial. Do a truncating store. On big-endian 447 // machines this requires an extending load from the stack slot to ensure 448 // that the bits are in the right place. 449 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 450 8 * (StoredBytes - Offset)); 451 452 // Load from the stack slot. 453 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 454 NULL, 0, MemVT, false, false, 0); 455 456 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 457 ST->getSrcValue(), SVOffset + Offset, 458 MemVT, ST->isVolatile(), 459 ST->isNonTemporal(), 460 MinAlign(ST->getAlignment(), Offset))); 461 // The order of the stores doesn't matter - say it with a TokenFactor. 462 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 463 Stores.size()); 464 } 465 } 466 assert(ST->getMemoryVT().isInteger() && 467 !ST->getMemoryVT().isVector() && 468 "Unaligned store of unknown type."); 469 // Get the half-size VT 470 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 471 int NumBits = NewStoredVT.getSizeInBits(); 472 int IncrementSize = NumBits / 8; 473 474 // Divide the stored value in two parts. 475 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 476 SDValue Lo = Val; 477 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 478 479 // Store the two parts 480 SDValue Store1, Store2; 481 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 482 ST->getSrcValue(), SVOffset, NewStoredVT, 483 ST->isVolatile(), ST->isNonTemporal(), Alignment); 484 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 485 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 486 Alignment = MinAlign(Alignment, IncrementSize); 487 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 488 ST->getSrcValue(), SVOffset + IncrementSize, 489 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 490 Alignment); 491 492 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 493} 494 495/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 496static 497SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 498 const TargetLowering &TLI) { 499 int SVOffset = LD->getSrcValueOffset(); 500 SDValue Chain = LD->getChain(); 501 SDValue Ptr = LD->getBasePtr(); 502 EVT VT = LD->getValueType(0); 503 EVT LoadedVT = LD->getMemoryVT(); 504 DebugLoc dl = LD->getDebugLoc(); 505 if (VT.isFloatingPoint() || VT.isVector()) { 506 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 507 if (TLI.isTypeLegal(intVT)) { 508 // Expand to a (misaligned) integer load of the same size, 509 // then bitconvert to floating point or vector. 510 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 511 SVOffset, LD->isVolatile(), 512 LD->isNonTemporal(), LD->getAlignment()); 513 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 514 if (VT.isFloatingPoint() && LoadedVT != VT) 515 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 516 517 SDValue Ops[] = { Result, Chain }; 518 return DAG.getMergeValues(Ops, 2, dl); 519 } else { 520 // Copy the value to a (aligned) stack slot using (unaligned) integer 521 // loads and stores, then do a (aligned) load from the stack slot. 522 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 523 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 524 unsigned RegBytes = RegVT.getSizeInBits() / 8; 525 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 526 527 // Make sure the stack slot is also aligned for the register type. 528 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 529 530 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 531 SmallVector<SDValue, 8> Stores; 532 SDValue StackPtr = StackBase; 533 unsigned Offset = 0; 534 535 // Do all but one copies using the full register width. 536 for (unsigned i = 1; i < NumRegs; i++) { 537 // Load one integer register's worth from the original location. 538 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 539 SVOffset + Offset, LD->isVolatile(), 540 LD->isNonTemporal(), 541 MinAlign(LD->getAlignment(), Offset)); 542 // Follow the load with a store to the stack slot. Remember the store. 543 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 544 NULL, 0, false, false, 0)); 545 // Increment the pointers. 546 Offset += RegBytes; 547 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 548 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 549 Increment); 550 } 551 552 // The last copy may be partial. Do an extending load. 553 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 554 8 * (LoadedBytes - Offset)); 555 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 556 LD->getSrcValue(), SVOffset + Offset, 557 MemVT, LD->isVolatile(), 558 LD->isNonTemporal(), 559 MinAlign(LD->getAlignment(), Offset)); 560 // Follow the load with a store to the stack slot. Remember the store. 561 // On big-endian machines this requires a truncating store to ensure 562 // that the bits end up in the right place. 563 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 564 NULL, 0, MemVT, false, false, 0)); 565 566 // The order of the stores doesn't matter - say it with a TokenFactor. 567 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 568 Stores.size()); 569 570 // Finally, perform the original load only redirected to the stack slot. 571 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 572 NULL, 0, LoadedVT, false, false, 0); 573 574 // Callers expect a MERGE_VALUES node. 575 SDValue Ops[] = { Load, TF }; 576 return DAG.getMergeValues(Ops, 2, dl); 577 } 578 } 579 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 580 "Unaligned load of unsupported type."); 581 582 // Compute the new VT that is half the size of the old one. This is an 583 // integer MVT. 584 unsigned NumBits = LoadedVT.getSizeInBits(); 585 EVT NewLoadedVT; 586 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 587 NumBits >>= 1; 588 589 unsigned Alignment = LD->getAlignment(); 590 unsigned IncrementSize = NumBits / 8; 591 ISD::LoadExtType HiExtType = LD->getExtensionType(); 592 593 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 594 if (HiExtType == ISD::NON_EXTLOAD) 595 HiExtType = ISD::ZEXTLOAD; 596 597 // Load the value in two parts 598 SDValue Lo, Hi; 599 if (TLI.isLittleEndian()) { 600 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 601 SVOffset, NewLoadedVT, LD->isVolatile(), 602 LD->isNonTemporal(), Alignment); 603 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 604 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 605 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 606 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 607 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize)); 608 } else { 609 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 610 SVOffset, NewLoadedVT, LD->isVolatile(), 611 LD->isNonTemporal(), Alignment); 612 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 613 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 614 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 615 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 616 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize)); 617 } 618 619 // aggregate the two parts 620 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 621 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 622 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 623 624 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 625 Hi.getValue(1)); 626 627 SDValue Ops[] = { Result, TF }; 628 return DAG.getMergeValues(Ops, 2, dl); 629} 630 631/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 632/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 633/// is necessary to spill the vector being inserted into to memory, perform 634/// the insert there, and then read the result back. 635SDValue SelectionDAGLegalize:: 636PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 637 DebugLoc dl) { 638 SDValue Tmp1 = Vec; 639 SDValue Tmp2 = Val; 640 SDValue Tmp3 = Idx; 641 642 // If the target doesn't support this, we have to spill the input vector 643 // to a temporary stack slot, update the element, then reload it. This is 644 // badness. We could also load the value into a vector register (either 645 // with a "move to register" or "extload into register" instruction, then 646 // permute it into place, if the idx is a constant and if the idx is 647 // supported by the target. 648 EVT VT = Tmp1.getValueType(); 649 EVT EltVT = VT.getVectorElementType(); 650 EVT IdxVT = Tmp3.getValueType(); 651 EVT PtrVT = TLI.getPointerTy(); 652 SDValue StackPtr = DAG.CreateStackTemporary(VT); 653 654 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 655 656 // Store the vector. 657 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 658 PseudoSourceValue::getFixedStack(SPFI), 0, 659 false, false, 0); 660 661 // Truncate or zero extend offset to target pointer type. 662 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 663 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 664 // Add the offset to the index. 665 unsigned EltSize = EltVT.getSizeInBits()/8; 666 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 667 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 668 // Store the scalar value. 669 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 670 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT, 671 false, false, 0); 672 // Load the updated vector. 673 return DAG.getLoad(VT, dl, Ch, StackPtr, 674 PseudoSourceValue::getFixedStack(SPFI), 0, 675 false, false, 0); 676} 677 678 679SDValue SelectionDAGLegalize:: 680ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 681 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 682 // SCALAR_TO_VECTOR requires that the type of the value being inserted 683 // match the element type of the vector being created, except for 684 // integers in which case the inserted value can be over width. 685 EVT EltVT = Vec.getValueType().getVectorElementType(); 686 if (Val.getValueType() == EltVT || 687 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 688 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 689 Vec.getValueType(), Val); 690 691 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 692 // We generate a shuffle of InVec and ScVec, so the shuffle mask 693 // should be 0,1,2,3,4,5... with the appropriate element replaced with 694 // elt 0 of the RHS. 695 SmallVector<int, 8> ShufOps; 696 for (unsigned i = 0; i != NumElts; ++i) 697 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 698 699 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 700 &ShufOps[0]); 701 } 702 } 703 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 704} 705 706SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 707 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 708 // FIXME: We shouldn't do this for TargetConstantFP's. 709 // FIXME: move this to the DAG Combiner! Note that we can't regress due 710 // to phase ordering between legalized code and the dag combiner. This 711 // probably means that we need to integrate dag combiner and legalizer 712 // together. 713 // We generally can't do this one for long doubles. 714 SDValue Tmp1 = ST->getChain(); 715 SDValue Tmp2 = ST->getBasePtr(); 716 SDValue Tmp3; 717 int SVOffset = ST->getSrcValueOffset(); 718 unsigned Alignment = ST->getAlignment(); 719 bool isVolatile = ST->isVolatile(); 720 bool isNonTemporal = ST->isNonTemporal(); 721 DebugLoc dl = ST->getDebugLoc(); 722 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 723 if (CFP->getValueType(0) == MVT::f32 && 724 getTypeAction(MVT::i32) == Legal) { 725 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 726 bitcastToAPInt().zextOrTrunc(32), 727 MVT::i32); 728 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 729 SVOffset, isVolatile, isNonTemporal, Alignment); 730 } else if (CFP->getValueType(0) == MVT::f64) { 731 // If this target supports 64-bit registers, do a single 64-bit store. 732 if (getTypeAction(MVT::i64) == Legal) { 733 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 734 zextOrTrunc(64), MVT::i64); 735 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 736 SVOffset, isVolatile, isNonTemporal, Alignment); 737 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 738 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 739 // stores. If the target supports neither 32- nor 64-bits, this 740 // xform is certainly not worth it. 741 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 742 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 743 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 744 if (TLI.isBigEndian()) std::swap(Lo, Hi); 745 746 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 747 SVOffset, isVolatile, isNonTemporal, Alignment); 748 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 749 DAG.getIntPtrConstant(4)); 750 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 751 isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); 752 753 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 754 } 755 } 756 } 757 return SDValue(); 758} 759 760/// LegalizeOp - We know that the specified value has a legal type, and 761/// that its operands are legal. Now ensure that the operation itself 762/// is legal, recursively ensuring that the operands' operations remain 763/// legal. 764SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 765 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 766 return Op; 767 768 SDNode *Node = Op.getNode(); 769 DebugLoc dl = Node->getDebugLoc(); 770 771 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 772 assert(getTypeAction(Node->getValueType(i)) == Legal && 773 "Unexpected illegal type!"); 774 775 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 776 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 777 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 778 "Unexpected illegal type!"); 779 780 // Note that LegalizeOp may be reentered even from single-use nodes, which 781 // means that we always must cache transformed nodes. 782 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 783 if (I != LegalizedNodes.end()) return I->second; 784 785 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 786 SDValue Result = Op; 787 bool isCustom = false; 788 789 // Figure out the correct action; the way to query this varies by opcode 790 TargetLowering::LegalizeAction Action; 791 bool SimpleFinishLegalizing = true; 792 switch (Node->getOpcode()) { 793 case ISD::INTRINSIC_W_CHAIN: 794 case ISD::INTRINSIC_WO_CHAIN: 795 case ISD::INTRINSIC_VOID: 796 case ISD::VAARG: 797 case ISD::STACKSAVE: 798 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 799 break; 800 case ISD::SINT_TO_FP: 801 case ISD::UINT_TO_FP: 802 case ISD::EXTRACT_VECTOR_ELT: 803 Action = TLI.getOperationAction(Node->getOpcode(), 804 Node->getOperand(0).getValueType()); 805 break; 806 case ISD::FP_ROUND_INREG: 807 case ISD::SIGN_EXTEND_INREG: { 808 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 809 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 810 break; 811 } 812 case ISD::SELECT_CC: 813 case ISD::SETCC: 814 case ISD::BR_CC: { 815 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 816 Node->getOpcode() == ISD::SETCC ? 2 : 1; 817 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 818 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 819 ISD::CondCode CCCode = 820 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 821 Action = TLI.getCondCodeAction(CCCode, OpVT); 822 if (Action == TargetLowering::Legal) { 823 if (Node->getOpcode() == ISD::SELECT_CC) 824 Action = TLI.getOperationAction(Node->getOpcode(), 825 Node->getValueType(0)); 826 else 827 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 828 } 829 break; 830 } 831 case ISD::LOAD: 832 case ISD::STORE: 833 // FIXME: Model these properly. LOAD and STORE are complicated, and 834 // STORE expects the unlegalized operand in some cases. 835 SimpleFinishLegalizing = false; 836 break; 837 case ISD::CALLSEQ_START: 838 case ISD::CALLSEQ_END: 839 // FIXME: This shouldn't be necessary. These nodes have special properties 840 // dealing with the recursive nature of legalization. Removing this 841 // special case should be done as part of making LegalizeDAG non-recursive. 842 SimpleFinishLegalizing = false; 843 break; 844 case ISD::EXTRACT_ELEMENT: 845 case ISD::FLT_ROUNDS_: 846 case ISD::SADDO: 847 case ISD::SSUBO: 848 case ISD::UADDO: 849 case ISD::USUBO: 850 case ISD::SMULO: 851 case ISD::UMULO: 852 case ISD::FPOWI: 853 case ISD::MERGE_VALUES: 854 case ISD::EH_RETURN: 855 case ISD::FRAME_TO_ARGS_OFFSET: 856 // These operations lie about being legal: when they claim to be legal, 857 // they should actually be expanded. 858 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 859 if (Action == TargetLowering::Legal) 860 Action = TargetLowering::Expand; 861 break; 862 case ISD::TRAMPOLINE: 863 case ISD::FRAMEADDR: 864 case ISD::RETURNADDR: 865 // These operations lie about being legal: when they claim to be legal, 866 // they should actually be custom-lowered. 867 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 868 if (Action == TargetLowering::Legal) 869 Action = TargetLowering::Custom; 870 break; 871 case ISD::BUILD_VECTOR: 872 // A weird case: legalization for BUILD_VECTOR never legalizes the 873 // operands! 874 // FIXME: This really sucks... changing it isn't semantically incorrect, 875 // but it massively pessimizes the code for floating-point BUILD_VECTORs 876 // because ConstantFP operands get legalized into constant pool loads 877 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 878 // though, because BUILD_VECTORS usually get lowered into other nodes 879 // which get legalized properly. 880 SimpleFinishLegalizing = false; 881 break; 882 default: 883 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 884 Action = TargetLowering::Legal; 885 } else { 886 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 887 } 888 break; 889 } 890 891 if (SimpleFinishLegalizing) { 892 SmallVector<SDValue, 8> Ops, ResultVals; 893 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 894 Ops.push_back(LegalizeOp(Node->getOperand(i))); 895 switch (Node->getOpcode()) { 896 default: break; 897 case ISD::BR: 898 case ISD::BRIND: 899 case ISD::BR_JT: 900 case ISD::BR_CC: 901 case ISD::BRCOND: 902 // Branches tweak the chain to include LastCALLSEQ_END 903 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 904 LastCALLSEQ_END); 905 Ops[0] = LegalizeOp(Ops[0]); 906 LastCALLSEQ_END = DAG.getEntryNode(); 907 break; 908 case ISD::SHL: 909 case ISD::SRL: 910 case ISD::SRA: 911 case ISD::ROTL: 912 case ISD::ROTR: 913 // Legalizing shifts/rotates requires adjusting the shift amount 914 // to the appropriate width. 915 if (!Ops[1].getValueType().isVector()) 916 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 917 break; 918 case ISD::SRL_PARTS: 919 case ISD::SRA_PARTS: 920 case ISD::SHL_PARTS: 921 // Legalizing shifts/rotates requires adjusting the shift amount 922 // to the appropriate width. 923 if (!Ops[2].getValueType().isVector()) 924 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2])); 925 break; 926 } 927 928 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(), 929 Ops.size()); 930 switch (Action) { 931 case TargetLowering::Legal: 932 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 933 ResultVals.push_back(Result.getValue(i)); 934 break; 935 case TargetLowering::Custom: 936 // FIXME: The handling for custom lowering with multiple results is 937 // a complete mess. 938 Tmp1 = TLI.LowerOperation(Result, DAG); 939 if (Tmp1.getNode()) { 940 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 941 if (e == 1) 942 ResultVals.push_back(Tmp1); 943 else 944 ResultVals.push_back(Tmp1.getValue(i)); 945 } 946 break; 947 } 948 949 // FALL THROUGH 950 case TargetLowering::Expand: 951 ExpandNode(Result.getNode(), ResultVals); 952 break; 953 case TargetLowering::Promote: 954 PromoteNode(Result.getNode(), ResultVals); 955 break; 956 } 957 if (!ResultVals.empty()) { 958 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 959 if (ResultVals[i] != SDValue(Node, i)) 960 ResultVals[i] = LegalizeOp(ResultVals[i]); 961 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 962 } 963 return ResultVals[Op.getResNo()]; 964 } 965 } 966 967 switch (Node->getOpcode()) { 968 default: 969#ifndef NDEBUG 970 dbgs() << "NODE: "; 971 Node->dump( &DAG); 972 dbgs() << "\n"; 973#endif 974 assert(0 && "Do not know how to legalize this operator!"); 975 976 case ISD::BUILD_VECTOR: 977 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 978 default: assert(0 && "This action is not supported yet!"); 979 case TargetLowering::Custom: 980 Tmp3 = TLI.LowerOperation(Result, DAG); 981 if (Tmp3.getNode()) { 982 Result = Tmp3; 983 break; 984 } 985 // FALLTHROUGH 986 case TargetLowering::Expand: 987 Result = ExpandBUILD_VECTOR(Result.getNode()); 988 break; 989 } 990 break; 991 case ISD::CALLSEQ_START: { 992 SDNode *CallEnd = FindCallEndFromCallStart(Node); 993 994 // Recursively Legalize all of the inputs of the call end that do not lead 995 // to this call start. This ensures that any libcalls that need be inserted 996 // are inserted *before* the CALLSEQ_START. 997 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 998 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 999 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1000 NodesLeadingTo); 1001 } 1002 1003 // Now that we legalized all of the inputs (which may have inserted 1004 // libcalls) create the new CALLSEQ_START node. 1005 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1006 1007 // Merge in the last call, to ensure that this call start after the last 1008 // call ended. 1009 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1010 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1011 Tmp1, LastCALLSEQ_END); 1012 Tmp1 = LegalizeOp(Tmp1); 1013 } 1014 1015 // Do not try to legalize the target-specific arguments (#1+). 1016 if (Tmp1 != Node->getOperand(0)) { 1017 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1018 Ops[0] = Tmp1; 1019 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1020 } 1021 1022 // Remember that the CALLSEQ_START is legalized. 1023 AddLegalizedOperand(Op.getValue(0), Result); 1024 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1025 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1026 1027 // Now that the callseq_start and all of the non-call nodes above this call 1028 // sequence have been legalized, legalize the call itself. During this 1029 // process, no libcalls can/will be inserted, guaranteeing that no calls 1030 // can overlap. 1031 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1032 // Note that we are selecting this call! 1033 LastCALLSEQ_END = SDValue(CallEnd, 0); 1034 IsLegalizingCall = true; 1035 1036 // Legalize the call, starting from the CALLSEQ_END. 1037 LegalizeOp(LastCALLSEQ_END); 1038 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1039 return Result; 1040 } 1041 case ISD::CALLSEQ_END: 1042 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1043 // will cause this node to be legalized as well as handling libcalls right. 1044 if (LastCALLSEQ_END.getNode() != Node) { 1045 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1046 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1047 assert(I != LegalizedNodes.end() && 1048 "Legalizing the call start should have legalized this node!"); 1049 return I->second; 1050 } 1051 1052 // Otherwise, the call start has been legalized and everything is going 1053 // according to plan. Just legalize ourselves normally here. 1054 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1055 // Do not try to legalize the target-specific arguments (#1+), except for 1056 // an optional flag input. 1057 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1058 if (Tmp1 != Node->getOperand(0)) { 1059 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1060 Ops[0] = Tmp1; 1061 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1062 } 1063 } else { 1064 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1065 if (Tmp1 != Node->getOperand(0) || 1066 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1067 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1068 Ops[0] = Tmp1; 1069 Ops.back() = Tmp2; 1070 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1071 } 1072 } 1073 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1074 // This finishes up call legalization. 1075 IsLegalizingCall = false; 1076 1077 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1078 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1079 if (Node->getNumValues() == 2) 1080 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1081 return Result.getValue(Op.getResNo()); 1082 case ISD::LOAD: { 1083 LoadSDNode *LD = cast<LoadSDNode>(Node); 1084 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1085 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1086 1087 ISD::LoadExtType ExtType = LD->getExtensionType(); 1088 if (ExtType == ISD::NON_EXTLOAD) { 1089 EVT VT = Node->getValueType(0); 1090 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1091 Tmp3 = Result.getValue(0); 1092 Tmp4 = Result.getValue(1); 1093 1094 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1095 default: assert(0 && "This action is not supported yet!"); 1096 case TargetLowering::Legal: 1097 // If this is an unaligned load and the target doesn't support it, 1098 // expand it. 1099 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1100 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1101 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1102 if (LD->getAlignment() < ABIAlignment){ 1103 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1104 DAG, TLI); 1105 Tmp3 = Result.getOperand(0); 1106 Tmp4 = Result.getOperand(1); 1107 Tmp3 = LegalizeOp(Tmp3); 1108 Tmp4 = LegalizeOp(Tmp4); 1109 } 1110 } 1111 break; 1112 case TargetLowering::Custom: 1113 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1114 if (Tmp1.getNode()) { 1115 Tmp3 = LegalizeOp(Tmp1); 1116 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1117 } 1118 break; 1119 case TargetLowering::Promote: { 1120 // Only promote a load of vector type to another. 1121 assert(VT.isVector() && "Cannot promote this load!"); 1122 // Change base type to a different vector type. 1123 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1124 1125 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1126 LD->getSrcValueOffset(), 1127 LD->isVolatile(), LD->isNonTemporal(), 1128 LD->getAlignment()); 1129 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1130 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1131 break; 1132 } 1133 } 1134 // Since loads produce two values, make sure to remember that we 1135 // legalized both of them. 1136 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1137 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1138 return Op.getResNo() ? Tmp4 : Tmp3; 1139 } else { 1140 EVT SrcVT = LD->getMemoryVT(); 1141 unsigned SrcWidth = SrcVT.getSizeInBits(); 1142 int SVOffset = LD->getSrcValueOffset(); 1143 unsigned Alignment = LD->getAlignment(); 1144 bool isVolatile = LD->isVolatile(); 1145 bool isNonTemporal = LD->isNonTemporal(); 1146 1147 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1148 // Some targets pretend to have an i1 loading operation, and actually 1149 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1150 // bits are guaranteed to be zero; it helps the optimizers understand 1151 // that these bits are zero. It is also useful for EXTLOAD, since it 1152 // tells the optimizers that those bits are undefined. It would be 1153 // nice to have an effective generic way of getting these benefits... 1154 // Until such a way is found, don't insist on promoting i1 here. 1155 (SrcVT != MVT::i1 || 1156 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1157 // Promote to a byte-sized load if not loading an integral number of 1158 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1159 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1160 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 1161 SDValue Ch; 1162 1163 // The extra bits are guaranteed to be zero, since we stored them that 1164 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1165 1166 ISD::LoadExtType NewExtType = 1167 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1168 1169 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 1170 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1171 NVT, isVolatile, isNonTemporal, Alignment); 1172 1173 Ch = Result.getValue(1); // The chain. 1174 1175 if (ExtType == ISD::SEXTLOAD) 1176 // Having the top bits zero doesn't help when sign extending. 1177 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1178 Result.getValueType(), 1179 Result, DAG.getValueType(SrcVT)); 1180 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1181 // All the top bits are guaranteed to be zero - inform the optimizers. 1182 Result = DAG.getNode(ISD::AssertZext, dl, 1183 Result.getValueType(), Result, 1184 DAG.getValueType(SrcVT)); 1185 1186 Tmp1 = LegalizeOp(Result); 1187 Tmp2 = LegalizeOp(Ch); 1188 } else if (SrcWidth & (SrcWidth - 1)) { 1189 // If not loading a power-of-2 number of bits, expand as two loads. 1190 assert(!SrcVT.isVector() && "Unsupported extload!"); 1191 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1192 assert(RoundWidth < SrcWidth); 1193 unsigned ExtraWidth = SrcWidth - RoundWidth; 1194 assert(ExtraWidth < RoundWidth); 1195 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1196 "Load size not an integral number of bytes!"); 1197 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1198 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1199 SDValue Lo, Hi, Ch; 1200 unsigned IncrementSize; 1201 1202 if (TLI.isLittleEndian()) { 1203 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1204 // Load the bottom RoundWidth bits. 1205 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1206 Node->getValueType(0), Tmp1, Tmp2, 1207 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1208 isNonTemporal, Alignment); 1209 1210 // Load the remaining ExtraWidth bits. 1211 IncrementSize = RoundWidth / 8; 1212 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1213 DAG.getIntPtrConstant(IncrementSize)); 1214 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1215 LD->getSrcValue(), SVOffset + IncrementSize, 1216 ExtraVT, isVolatile, isNonTemporal, 1217 MinAlign(Alignment, IncrementSize)); 1218 1219 // Build a factor node to remember that this load is independent of the 1220 // other one. 1221 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1222 Hi.getValue(1)); 1223 1224 // Move the top bits to the right place. 1225 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1226 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1227 1228 // Join the hi and lo parts. 1229 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1230 } else { 1231 // Big endian - avoid unaligned loads. 1232 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1233 // Load the top RoundWidth bits. 1234 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1235 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1236 isNonTemporal, Alignment); 1237 1238 // Load the remaining ExtraWidth bits. 1239 IncrementSize = RoundWidth / 8; 1240 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1241 DAG.getIntPtrConstant(IncrementSize)); 1242 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1243 Node->getValueType(0), Tmp1, Tmp2, 1244 LD->getSrcValue(), SVOffset + IncrementSize, 1245 ExtraVT, isVolatile, isNonTemporal, 1246 MinAlign(Alignment, IncrementSize)); 1247 1248 // Build a factor node to remember that this load is independent of the 1249 // other one. 1250 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1251 Hi.getValue(1)); 1252 1253 // Move the top bits to the right place. 1254 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1255 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1256 1257 // Join the hi and lo parts. 1258 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1259 } 1260 1261 Tmp1 = LegalizeOp(Result); 1262 Tmp2 = LegalizeOp(Ch); 1263 } else { 1264 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1265 default: assert(0 && "This action is not supported yet!"); 1266 case TargetLowering::Custom: 1267 isCustom = true; 1268 // FALLTHROUGH 1269 case TargetLowering::Legal: 1270 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1271 Tmp1 = Result.getValue(0); 1272 Tmp2 = Result.getValue(1); 1273 1274 if (isCustom) { 1275 Tmp3 = TLI.LowerOperation(Result, DAG); 1276 if (Tmp3.getNode()) { 1277 Tmp1 = LegalizeOp(Tmp3); 1278 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1279 } 1280 } else { 1281 // If this is an unaligned load and the target doesn't support it, 1282 // expand it. 1283 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1284 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1285 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1286 if (LD->getAlignment() < ABIAlignment){ 1287 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1288 DAG, TLI); 1289 Tmp1 = Result.getOperand(0); 1290 Tmp2 = Result.getOperand(1); 1291 Tmp1 = LegalizeOp(Tmp1); 1292 Tmp2 = LegalizeOp(Tmp2); 1293 } 1294 } 1295 } 1296 break; 1297 case TargetLowering::Expand: 1298 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1299 // f128 = EXTLOAD {f32,f64} too 1300 if ((SrcVT == MVT::f32 && (Node->getValueType(0) == MVT::f64 || 1301 Node->getValueType(0) == MVT::f128)) || 1302 (SrcVT == MVT::f64 && Node->getValueType(0) == MVT::f128)) { 1303 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1304 LD->getSrcValueOffset(), 1305 LD->isVolatile(), LD->isNonTemporal(), 1306 LD->getAlignment()); 1307 Result = DAG.getNode(ISD::FP_EXTEND, dl, 1308 Node->getValueType(0), Load); 1309 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1310 Tmp2 = LegalizeOp(Load.getValue(1)); 1311 break; 1312 } 1313 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1314 // Turn the unsupported load into an EXTLOAD followed by an explicit 1315 // zero/sign extend inreg. 1316 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1317 Tmp1, Tmp2, LD->getSrcValue(), 1318 LD->getSrcValueOffset(), SrcVT, 1319 LD->isVolatile(), LD->isNonTemporal(), 1320 LD->getAlignment()); 1321 SDValue ValRes; 1322 if (ExtType == ISD::SEXTLOAD) 1323 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1324 Result.getValueType(), 1325 Result, DAG.getValueType(SrcVT)); 1326 else 1327 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1328 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1329 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1330 break; 1331 } 1332 } 1333 1334 // Since loads produce two values, make sure to remember that we legalized 1335 // both of them. 1336 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1337 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1338 return Op.getResNo() ? Tmp2 : Tmp1; 1339 } 1340 } 1341 case ISD::STORE: { 1342 StoreSDNode *ST = cast<StoreSDNode>(Node); 1343 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1344 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1345 int SVOffset = ST->getSrcValueOffset(); 1346 unsigned Alignment = ST->getAlignment(); 1347 bool isVolatile = ST->isVolatile(); 1348 bool isNonTemporal = ST->isNonTemporal(); 1349 1350 if (!ST->isTruncatingStore()) { 1351 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1352 Result = SDValue(OptStore, 0); 1353 break; 1354 } 1355 1356 { 1357 Tmp3 = LegalizeOp(ST->getValue()); 1358 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1359 ST->getOffset()); 1360 1361 EVT VT = Tmp3.getValueType(); 1362 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1363 default: assert(0 && "This action is not supported yet!"); 1364 case TargetLowering::Legal: 1365 // If this is an unaligned store and the target doesn't support it, 1366 // expand it. 1367 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1368 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1369 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1370 if (ST->getAlignment() < ABIAlignment) 1371 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1372 DAG, TLI); 1373 } 1374 break; 1375 case TargetLowering::Custom: 1376 Tmp1 = TLI.LowerOperation(Result, DAG); 1377 if (Tmp1.getNode()) Result = Tmp1; 1378 break; 1379 case TargetLowering::Promote: 1380 assert(VT.isVector() && "Unknown legal promote case!"); 1381 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1382 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1383 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1384 ST->getSrcValue(), SVOffset, isVolatile, 1385 isNonTemporal, Alignment); 1386 break; 1387 } 1388 break; 1389 } 1390 } else { 1391 Tmp3 = LegalizeOp(ST->getValue()); 1392 1393 EVT StVT = ST->getMemoryVT(); 1394 unsigned StWidth = StVT.getSizeInBits(); 1395 1396 if (StWidth != StVT.getStoreSizeInBits()) { 1397 // Promote to a byte-sized store with upper bits zero if not 1398 // storing an integral number of bytes. For example, promote 1399 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1400 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), 1401 StVT.getStoreSizeInBits()); 1402 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1403 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1404 SVOffset, NVT, isVolatile, isNonTemporal, 1405 Alignment); 1406 } else if (StWidth & (StWidth - 1)) { 1407 // If not storing a power-of-2 number of bits, expand as two stores. 1408 assert(!StVT.isVector() && "Unsupported truncstore!"); 1409 unsigned RoundWidth = 1 << Log2_32(StWidth); 1410 assert(RoundWidth < StWidth); 1411 unsigned ExtraWidth = StWidth - RoundWidth; 1412 assert(ExtraWidth < RoundWidth); 1413 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1414 "Store size not an integral number of bytes!"); 1415 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1416 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1417 SDValue Lo, Hi; 1418 unsigned IncrementSize; 1419 1420 if (TLI.isLittleEndian()) { 1421 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1422 // Store the bottom RoundWidth bits. 1423 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1424 SVOffset, RoundVT, 1425 isVolatile, isNonTemporal, Alignment); 1426 1427 // Store the remaining ExtraWidth bits. 1428 IncrementSize = RoundWidth / 8; 1429 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1430 DAG.getIntPtrConstant(IncrementSize)); 1431 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1432 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1433 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1434 SVOffset + IncrementSize, ExtraVT, isVolatile, 1435 isNonTemporal, 1436 MinAlign(Alignment, IncrementSize)); 1437 } else { 1438 // Big endian - avoid unaligned stores. 1439 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1440 // Store the top RoundWidth bits. 1441 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1442 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1443 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1444 SVOffset, RoundVT, isVolatile, isNonTemporal, 1445 Alignment); 1446 1447 // Store the remaining ExtraWidth bits. 1448 IncrementSize = RoundWidth / 8; 1449 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1450 DAG.getIntPtrConstant(IncrementSize)); 1451 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1452 SVOffset + IncrementSize, ExtraVT, isVolatile, 1453 isNonTemporal, 1454 MinAlign(Alignment, IncrementSize)); 1455 } 1456 1457 // The order of the stores doesn't matter. 1458 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1459 } else { 1460 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1461 Tmp2 != ST->getBasePtr()) 1462 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1463 ST->getOffset()); 1464 1465 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1466 default: assert(0 && "This action is not supported yet!"); 1467 case TargetLowering::Legal: 1468 // If this is an unaligned store and the target doesn't support it, 1469 // expand it. 1470 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1471 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1472 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1473 if (ST->getAlignment() < ABIAlignment) 1474 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1475 DAG, TLI); 1476 } 1477 break; 1478 case TargetLowering::Custom: 1479 Result = TLI.LowerOperation(Result, DAG); 1480 break; 1481 case Expand: 1482 // TRUNCSTORE:i16 i32 -> STORE i16 1483 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1484 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1485 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1486 SVOffset, isVolatile, isNonTemporal, 1487 Alignment); 1488 break; 1489 } 1490 } 1491 } 1492 break; 1493 } 1494 } 1495 assert(Result.getValueType() == Op.getValueType() && 1496 "Bad legalization!"); 1497 1498 // Make sure that the generated code is itself legal. 1499 if (Result != Op) 1500 Result = LegalizeOp(Result); 1501 1502 // Note that LegalizeOp may be reentered even from single-use nodes, which 1503 // means that we always must cache transformed nodes. 1504 AddLegalizedOperand(Op, Result); 1505 return Result; 1506} 1507 1508SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1509 SDValue Vec = Op.getOperand(0); 1510 SDValue Idx = Op.getOperand(1); 1511 DebugLoc dl = Op.getDebugLoc(); 1512 // Store the value to a temporary stack slot, then LOAD the returned part. 1513 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1514 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0, 1515 false, false, 0); 1516 1517 // Add the offset to the index. 1518 unsigned EltSize = 1519 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1520 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1521 DAG.getConstant(EltSize, Idx.getValueType())); 1522 1523 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1524 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1525 else 1526 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1527 1528 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1529 1530 if (Op.getValueType().isVector()) 1531 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0, 1532 false, false, 0); 1533 else 1534 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1535 NULL, 0, Vec.getValueType().getVectorElementType(), 1536 false, false, 0); 1537} 1538 1539SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1540 // We can't handle this case efficiently. Allocate a sufficiently 1541 // aligned object on the stack, store each element into it, then load 1542 // the result as a vector. 1543 // Create the stack frame object. 1544 EVT VT = Node->getValueType(0); 1545 EVT EltVT = VT.getVectorElementType(); 1546 DebugLoc dl = Node->getDebugLoc(); 1547 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1548 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1549 const Value *SV = PseudoSourceValue::getFixedStack(FI); 1550 1551 // Emit a store of each element to the stack slot. 1552 SmallVector<SDValue, 8> Stores; 1553 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1554 // Store (in the right endianness) the elements to memory. 1555 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1556 // Ignore undef elements. 1557 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1558 1559 unsigned Offset = TypeByteSize*i; 1560 1561 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1562 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1563 1564 // If the destination vector element type is narrower than the source 1565 // element type, only store the bits necessary. 1566 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1567 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1568 Node->getOperand(i), Idx, SV, Offset, 1569 EltVT, false, false, 0)); 1570 } else 1571 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1572 Node->getOperand(i), Idx, SV, Offset, 1573 false, false, 0)); 1574 } 1575 1576 SDValue StoreChain; 1577 if (!Stores.empty()) // Not all undef elements? 1578 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1579 &Stores[0], Stores.size()); 1580 else 1581 StoreChain = DAG.getEntryNode(); 1582 1583 // Result is a load from the stack slot. 1584 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0, false, false, 0); 1585} 1586 1587SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1588 DebugLoc dl = Node->getDebugLoc(); 1589 SDValue Tmp1 = Node->getOperand(0); 1590 SDValue Tmp2 = Node->getOperand(1); 1591 1592 // Get the sign bit of the RHS. First obtain a value that has the same 1593 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1594 SDValue SignBit; 1595 EVT FloatVT = Tmp2.getValueType(); 1596 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1597 if (isTypeLegal(IVT)) { 1598 // Convert to an integer with the same sign bit. 1599 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 1600 } else { 1601 // Store the float to memory, then load the sign part out as an integer. 1602 MVT LoadTy = TLI.getPointerTy(); 1603 // First create a temporary that is aligned for both the load and store. 1604 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1605 // Then store the float to it. 1606 SDValue Ch = 1607 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, NULL, 0, 1608 false, false, 0); 1609 if (TLI.isBigEndian()) { 1610 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1611 // Load out a legal integer with the same sign bit as the float. 1612 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, NULL, 0, false, false, 0); 1613 } else { // Little endian 1614 SDValue LoadPtr = StackPtr; 1615 // The float may be wider than the integer we are going to load. Advance 1616 // the pointer so that the loaded integer will contain the sign bit. 1617 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1618 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1619 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1620 LoadPtr, DAG.getIntPtrConstant(ByteOffset)); 1621 // Load a legal integer containing the sign bit. 1622 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, NULL, 0, false, false, 0); 1623 // Move the sign bit to the top bit of the loaded integer. 1624 unsigned BitShift = LoadTy.getSizeInBits() - 1625 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1626 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1627 if (BitShift) 1628 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1629 DAG.getConstant(BitShift,TLI.getShiftAmountTy())); 1630 } 1631 } 1632 // Now get the sign bit proper, by seeing whether the value is negative. 1633 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1634 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1635 ISD::SETLT); 1636 // Get the absolute value of the result. 1637 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1638 // Select between the nabs and abs value based on the sign bit of 1639 // the input. 1640 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1641 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1642 AbsVal); 1643} 1644 1645void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1646 SmallVectorImpl<SDValue> &Results) { 1647 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1648 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1649 " not tell us which reg is the stack pointer!"); 1650 DebugLoc dl = Node->getDebugLoc(); 1651 EVT VT = Node->getValueType(0); 1652 SDValue Tmp1 = SDValue(Node, 0); 1653 SDValue Tmp2 = SDValue(Node, 1); 1654 SDValue Tmp3 = Node->getOperand(2); 1655 SDValue Chain = Tmp1.getOperand(0); 1656 1657 // Chain the dynamic stack allocation so that it doesn't modify the stack 1658 // pointer when other instructions are using the stack. 1659 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1660 1661 SDValue Size = Tmp2.getOperand(1); 1662 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1663 Chain = SP.getValue(1); 1664 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1665 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); 1666 if (Align > StackAlign) 1667 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1668 DAG.getConstant(-(uint64_t)Align, VT)); 1669 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1670 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1671 1672 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1673 DAG.getIntPtrConstant(0, true), SDValue()); 1674 1675 Results.push_back(Tmp1); 1676 Results.push_back(Tmp2); 1677} 1678 1679/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1680/// condition code CC on the current target. This routine expands SETCC with 1681/// illegal condition code into AND / OR of multiple SETCC values. 1682void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1683 SDValue &LHS, SDValue &RHS, 1684 SDValue &CC, 1685 DebugLoc dl) { 1686 EVT OpVT = LHS.getValueType(); 1687 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1688 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1689 default: assert(0 && "Unknown condition code action!"); 1690 case TargetLowering::Legal: 1691 // Nothing to do. 1692 break; 1693 case TargetLowering::Expand: { 1694 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1695 unsigned Opc = 0; 1696 switch (CCCode) { 1697 default: assert(0 && "Don't know how to expand this condition!"); 1698 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1699 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1700 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1701 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1702 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1703 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1704 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1705 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1706 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1707 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1708 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1709 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1710 // FIXME: Implement more expansions. 1711 } 1712 1713 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1714 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1715 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1716 RHS = SDValue(); 1717 CC = SDValue(); 1718 break; 1719 } 1720 } 1721} 1722 1723/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1724/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1725/// a load from the stack slot to DestVT, extending it if needed. 1726/// The resultant code need not be legal. 1727SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1728 EVT SlotVT, 1729 EVT DestVT, 1730 DebugLoc dl) { 1731 // Create the stack frame object. 1732 unsigned SrcAlign = 1733 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1734 getTypeForEVT(*DAG.getContext())); 1735 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1736 1737 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1738 int SPFI = StackPtrFI->getIndex(); 1739 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1740 1741 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1742 unsigned SlotSize = SlotVT.getSizeInBits(); 1743 unsigned DestSize = DestVT.getSizeInBits(); 1744 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); 1745 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType); 1746 1747 // Emit a store to the stack slot. Use a truncstore if the input value is 1748 // later than DestVT. 1749 SDValue Store; 1750 1751 if (SrcSize > SlotSize) 1752 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1753 SV, 0, SlotVT, false, false, SrcAlign); 1754 else { 1755 assert(SrcSize == SlotSize && "Invalid store"); 1756 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1757 SV, 0, false, false, SrcAlign); 1758 } 1759 1760 // Result is a load from the stack slot. 1761 if (SlotSize == DestSize) 1762 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, false, 1763 DestAlign); 1764 1765 assert(SlotSize < DestSize && "Unknown extension!"); 1766 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, 1767 false, false, DestAlign); 1768} 1769 1770SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1771 DebugLoc dl = Node->getDebugLoc(); 1772 // Create a vector sized/aligned stack slot, store the value to element #0, 1773 // then load the whole vector back out. 1774 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1775 1776 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1777 int SPFI = StackPtrFI->getIndex(); 1778 1779 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1780 StackPtr, 1781 PseudoSourceValue::getFixedStack(SPFI), 0, 1782 Node->getValueType(0).getVectorElementType(), 1783 false, false, 0); 1784 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1785 PseudoSourceValue::getFixedStack(SPFI), 0, 1786 false, false, 0); 1787} 1788 1789 1790/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1791/// support the operation, but do support the resultant vector type. 1792SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1793 unsigned NumElems = Node->getNumOperands(); 1794 SDValue Value1, Value2; 1795 DebugLoc dl = Node->getDebugLoc(); 1796 EVT VT = Node->getValueType(0); 1797 EVT OpVT = Node->getOperand(0).getValueType(); 1798 EVT EltVT = VT.getVectorElementType(); 1799 1800 // If the only non-undef value is the low element, turn this into a 1801 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1802 bool isOnlyLowElement = true; 1803 bool MoreThanTwoValues = false; 1804 bool isConstant = true; 1805 for (unsigned i = 0; i < NumElems; ++i) { 1806 SDValue V = Node->getOperand(i); 1807 if (V.getOpcode() == ISD::UNDEF) 1808 continue; 1809 if (i > 0) 1810 isOnlyLowElement = false; 1811 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1812 isConstant = false; 1813 1814 if (!Value1.getNode()) { 1815 Value1 = V; 1816 } else if (!Value2.getNode()) { 1817 if (V != Value1) 1818 Value2 = V; 1819 } else if (V != Value1 && V != Value2) { 1820 MoreThanTwoValues = true; 1821 } 1822 } 1823 1824 if (!Value1.getNode()) 1825 return DAG.getUNDEF(VT); 1826 1827 if (isOnlyLowElement) 1828 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1829 1830 // If all elements are constants, create a load from the constant pool. 1831 if (isConstant) { 1832 std::vector<Constant*> CV; 1833 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1834 if (ConstantFPSDNode *V = 1835 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1836 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1837 } else if (ConstantSDNode *V = 1838 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1839 if (OpVT==EltVT) 1840 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1841 else { 1842 // If OpVT and EltVT don't match, EltVT is not legal and the 1843 // element values have been promoted/truncated earlier. Undo this; 1844 // we don't want a v16i8 to become a v16i32 for example. 1845 const ConstantInt *CI = V->getConstantIntValue(); 1846 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1847 CI->getZExtValue())); 1848 } 1849 } else { 1850 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1851 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1852 CV.push_back(UndefValue::get(OpNTy)); 1853 } 1854 } 1855 Constant *CP = ConstantVector::get(CV); 1856 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1857 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1858 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1859 PseudoSourceValue::getConstantPool(), 0, 1860 false, false, Alignment); 1861 } 1862 1863 if (!MoreThanTwoValues) { 1864 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1865 for (unsigned i = 0; i < NumElems; ++i) { 1866 SDValue V = Node->getOperand(i); 1867 if (V.getOpcode() == ISD::UNDEF) 1868 continue; 1869 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1870 } 1871 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1872 // Get the splatted value into the low element of a vector register. 1873 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1874 SDValue Vec2; 1875 if (Value2.getNode()) 1876 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1877 else 1878 Vec2 = DAG.getUNDEF(VT); 1879 1880 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1881 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1882 } 1883 } 1884 1885 // Otherwise, we can't handle this case efficiently. 1886 return ExpandVectorBuildThroughStack(Node); 1887} 1888 1889// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1890// does not fit into a register, return the lo part and set the hi part to the 1891// by-reg argument. If it does fit into a single register, return the result 1892// and leave the Hi part unset. 1893SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1894 bool isSigned) { 1895 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1896 // The input chain to this libcall is the entry node of the function. 1897 // Legalizing the call will automatically add the previous call to the 1898 // dependence. 1899 SDValue InChain = DAG.getEntryNode(); 1900 1901 TargetLowering::ArgListTy Args; 1902 TargetLowering::ArgListEntry Entry; 1903 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1904 EVT ArgVT = Node->getOperand(i).getValueType(); 1905 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1906 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1907 Entry.isSExt = isSigned; 1908 Entry.isZExt = !isSigned; 1909 Args.push_back(Entry); 1910 } 1911 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1912 TLI.getPointerTy()); 1913 1914 // Splice the libcall in wherever FindInputOutputChains tells us to. 1915 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1916 std::pair<SDValue, SDValue> CallInfo = 1917 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1918 0, TLI.getLibcallCallingConv(LC), false, 1919 /*isReturnValueUsed=*/true, 1920 Callee, Args, DAG, Node->getDebugLoc()); 1921 1922 // Legalize the call sequence, starting with the chain. This will advance 1923 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1924 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1925 LegalizeOp(CallInfo.second); 1926 return CallInfo.first; 1927} 1928 1929SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 1930 RTLIB::Libcall Call_F32, 1931 RTLIB::Libcall Call_F64, 1932 RTLIB::Libcall Call_F80, 1933 RTLIB::Libcall Call_PPCF128) { 1934 RTLIB::Libcall LC; 1935 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1936 default: assert(0 && "Unexpected request for libcall!"); 1937 case MVT::f32: LC = Call_F32; break; 1938 case MVT::f64: LC = Call_F64; break; 1939 case MVT::f80: LC = Call_F80; break; 1940 case MVT::ppcf128: LC = Call_PPCF128; break; 1941 } 1942 return ExpandLibCall(LC, Node, false); 1943} 1944 1945SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 1946 RTLIB::Libcall Call_I8, 1947 RTLIB::Libcall Call_I16, 1948 RTLIB::Libcall Call_I32, 1949 RTLIB::Libcall Call_I64, 1950 RTLIB::Libcall Call_I128) { 1951 RTLIB::Libcall LC; 1952 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1953 default: assert(0 && "Unexpected request for libcall!"); 1954 case MVT::i8: LC = Call_I8; break; 1955 case MVT::i16: LC = Call_I16; break; 1956 case MVT::i32: LC = Call_I32; break; 1957 case MVT::i64: LC = Call_I64; break; 1958 case MVT::i128: LC = Call_I128; break; 1959 } 1960 return ExpandLibCall(LC, Node, isSigned); 1961} 1962 1963/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 1964/// INT_TO_FP operation of the specified operand when the target requests that 1965/// we expand it. At this point, we know that the result and operand types are 1966/// legal for the target. 1967SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 1968 SDValue Op0, 1969 EVT DestVT, 1970 DebugLoc dl) { 1971 if (Op0.getValueType() == MVT::i32) { 1972 // simple 32-bit [signed|unsigned] integer to float/double expansion 1973 1974 // Get the stack frame index of a 8 byte buffer. 1975 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 1976 1977 // word offset constant for Hi/Lo address computation 1978 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 1979 // set up Hi and Lo (into buffer) address based on endian 1980 SDValue Hi = StackSlot; 1981 SDValue Lo = DAG.getNode(ISD::ADD, dl, 1982 TLI.getPointerTy(), StackSlot, WordOff); 1983 if (TLI.isLittleEndian()) 1984 std::swap(Hi, Lo); 1985 1986 // if signed map to unsigned space 1987 SDValue Op0Mapped; 1988 if (isSigned) { 1989 // constant used to invert sign bit (signed to unsigned mapping) 1990 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 1991 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 1992 } else { 1993 Op0Mapped = Op0; 1994 } 1995 // store the lo of the constructed double - based on integer input 1996 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 1997 Op0Mapped, Lo, NULL, 0, 1998 false, false, 0); 1999 // initial hi portion of constructed double 2000 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 2001 // store the hi of the constructed double - biased exponent 2002 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0, 2003 false, false, 0); 2004 // load the constructed double 2005 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0, 2006 false, false, 0); 2007 // FP constant to bias correct the final result 2008 SDValue Bias = DAG.getConstantFP(isSigned ? 2009 BitsToDouble(0x4330000080000000ULL) : 2010 BitsToDouble(0x4330000000000000ULL), 2011 MVT::f64); 2012 // subtract the bias 2013 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2014 // final result 2015 SDValue Result; 2016 // handle final rounding 2017 if (DestVT == MVT::f64) { 2018 // do nothing 2019 Result = Sub; 2020 } else if (DestVT.bitsLT(MVT::f64)) { 2021 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2022 DAG.getIntPtrConstant(0)); 2023 } else if (DestVT.bitsGT(MVT::f64)) { 2024 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2025 } 2026 return Result; 2027 } 2028 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2029 // Code below here assumes !isSigned without checking again. 2030 2031 // Implementation of unsigned i64 to f64 following the algorithm in 2032 // __floatundidf in compiler_rt. This implementation has the advantage 2033 // of performing rounding correctly, both in the default rounding mode 2034 // and in all alternate rounding modes. 2035 // TODO: Generalize this for use with other types. 2036 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2037 SDValue TwoP52 = 2038 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2039 SDValue TwoP84PlusTwoP52 = 2040 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2041 SDValue TwoP84 = 2042 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2043 2044 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2045 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2046 DAG.getConstant(32, MVT::i64)); 2047 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2048 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2049 SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr); 2050 SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr); 2051 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, TwoP84PlusTwoP52); 2052 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2053 } 2054 2055 // Implementation of unsigned i64 to f32. This implementation has the 2056 // advantage of performing rounding correctly. 2057 // TODO: Generalize this for use with other types. 2058 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) { 2059 EVT SHVT = TLI.getShiftAmountTy(); 2060 2061 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2062 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64)); 2063 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, 2064 DAG.getConstant(UINT64_C(0x800), MVT::i64)); 2065 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2066 DAG.getConstant(UINT64_C(0x7ff), MVT::i64)); 2067 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2068 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); 2069 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0); 2070 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2071 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64), 2072 ISD::SETUGE); 2073 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0); 2074 2075 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, 2076 DAG.getConstant(32, SHVT)); 2077 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh); 2078 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); 2079 SDValue TwoP32 = 2080 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64); 2081 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); 2082 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2); 2083 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo); 2084 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); 2085 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, 2086 DAG.getIntPtrConstant(0)); 2087 2088 } 2089 2090 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2091 2092 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2093 Op0, DAG.getConstant(0, Op0.getValueType()), 2094 ISD::SETLT); 2095 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2096 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2097 SignSet, Four, Zero); 2098 2099 // If the sign bit of the integer is set, the large number will be treated 2100 // as a negative number. To counteract this, the dynamic code adds an 2101 // offset depending on the data type. 2102 uint64_t FF; 2103 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2104 default: assert(0 && "Unsupported integer type!"); 2105 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2106 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2107 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2108 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2109 } 2110 if (TLI.isLittleEndian()) FF <<= 32; 2111 Constant *FudgeFactor = ConstantInt::get( 2112 Type::getInt64Ty(*DAG.getContext()), FF); 2113 2114 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2115 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2116 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2117 Alignment = std::min(Alignment, 4u); 2118 SDValue FudgeInReg; 2119 if (DestVT == MVT::f32) 2120 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2121 PseudoSourceValue::getConstantPool(), 0, 2122 false, false, Alignment); 2123 else { 2124 FudgeInReg = 2125 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2126 DAG.getEntryNode(), CPIdx, 2127 PseudoSourceValue::getConstantPool(), 0, 2128 MVT::f32, false, false, Alignment)); 2129 } 2130 2131 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2132} 2133 2134/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2135/// *INT_TO_FP operation of the specified operand when the target requests that 2136/// we promote it. At this point, we know that the result and operand types are 2137/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2138/// operation that takes a larger input. 2139SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2140 EVT DestVT, 2141 bool isSigned, 2142 DebugLoc dl) { 2143 // First step, figure out the appropriate *INT_TO_FP operation to use. 2144 EVT NewInTy = LegalOp.getValueType(); 2145 2146 unsigned OpToUse = 0; 2147 2148 // Scan for the appropriate larger type to use. 2149 while (1) { 2150 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2151 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2152 2153 // If the target supports SINT_TO_FP of this type, use it. 2154 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2155 OpToUse = ISD::SINT_TO_FP; 2156 break; 2157 } 2158 if (isSigned) continue; 2159 2160 // If the target supports UINT_TO_FP of this type, use it. 2161 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2162 OpToUse = ISD::UINT_TO_FP; 2163 break; 2164 } 2165 2166 // Otherwise, try a larger type. 2167 } 2168 2169 // Okay, we found the operation and type to use. Zero extend our input to the 2170 // desired type then run the operation on it. 2171 return DAG.getNode(OpToUse, dl, DestVT, 2172 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2173 dl, NewInTy, LegalOp)); 2174} 2175 2176/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2177/// FP_TO_*INT operation of the specified operand when the target requests that 2178/// we promote it. At this point, we know that the result and operand types are 2179/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2180/// operation that returns a larger result. 2181SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2182 EVT DestVT, 2183 bool isSigned, 2184 DebugLoc dl) { 2185 // First step, figure out the appropriate FP_TO*INT operation to use. 2186 EVT NewOutTy = DestVT; 2187 2188 unsigned OpToUse = 0; 2189 2190 // Scan for the appropriate larger type to use. 2191 while (1) { 2192 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2193 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2194 2195 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2196 OpToUse = ISD::FP_TO_SINT; 2197 break; 2198 } 2199 2200 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2201 OpToUse = ISD::FP_TO_UINT; 2202 break; 2203 } 2204 2205 // Otherwise, try a larger type. 2206 } 2207 2208 2209 // Okay, we found the operation and type to use. 2210 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2211 2212 // Truncate the result of the extended FP_TO_*INT operation to the desired 2213 // size. 2214 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2215} 2216 2217/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2218/// 2219SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2220 EVT VT = Op.getValueType(); 2221 EVT SHVT = TLI.getShiftAmountTy(); 2222 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2223 switch (VT.getSimpleVT().SimpleTy) { 2224 default: assert(0 && "Unhandled Expand type in BSWAP!"); 2225 case MVT::i16: 2226 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2227 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2228 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2229 case MVT::i32: 2230 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2231 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2232 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2233 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2234 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2235 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2236 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2237 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2238 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2239 case MVT::i64: 2240 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2241 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2242 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2243 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2244 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2245 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2246 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2247 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2248 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2249 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2250 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2251 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2252 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2253 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2254 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2255 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2256 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2257 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2258 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2259 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2260 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2261 } 2262} 2263 2264/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2265/// 2266SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2267 DebugLoc dl) { 2268 switch (Opc) { 2269 default: assert(0 && "Cannot expand this yet!"); 2270 case ISD::CTPOP: { 2271 static const uint64_t mask[6] = { 2272 0x5555555555555555ULL, 0x3333333333333333ULL, 2273 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2274 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2275 }; 2276 EVT VT = Op.getValueType(); 2277 EVT ShVT = TLI.getShiftAmountTy(); 2278 unsigned len = VT.getSizeInBits(); 2279 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2280 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2281 unsigned EltSize = VT.isVector() ? 2282 VT.getVectorElementType().getSizeInBits() : len; 2283 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2284 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2285 Op = DAG.getNode(ISD::ADD, dl, VT, 2286 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2287 DAG.getNode(ISD::AND, dl, VT, 2288 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2289 Tmp2)); 2290 } 2291 return Op; 2292 } 2293 case ISD::CTLZ: { 2294 // for now, we do this: 2295 // x = x | (x >> 1); 2296 // x = x | (x >> 2); 2297 // ... 2298 // x = x | (x >>16); 2299 // x = x | (x >>32); // for 64-bit input 2300 // return popcount(~x); 2301 // 2302 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2303 EVT VT = Op.getValueType(); 2304 EVT ShVT = TLI.getShiftAmountTy(); 2305 unsigned len = VT.getSizeInBits(); 2306 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2307 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2308 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2309 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2310 } 2311 Op = DAG.getNOT(dl, Op, VT); 2312 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2313 } 2314 case ISD::CTTZ: { 2315 // for now, we use: { return popcount(~x & (x - 1)); } 2316 // unless the target has ctlz but not ctpop, in which case we use: 2317 // { return 32 - nlz(~x & (x-1)); } 2318 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2319 EVT VT = Op.getValueType(); 2320 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2321 DAG.getNOT(dl, Op, VT), 2322 DAG.getNode(ISD::SUB, dl, VT, Op, 2323 DAG.getConstant(1, VT))); 2324 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2325 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2326 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2327 return DAG.getNode(ISD::SUB, dl, VT, 2328 DAG.getConstant(VT.getSizeInBits(), VT), 2329 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2330 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2331 } 2332 } 2333} 2334 2335void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2336 SmallVectorImpl<SDValue> &Results) { 2337 DebugLoc dl = Node->getDebugLoc(); 2338 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2339 switch (Node->getOpcode()) { 2340 case ISD::CTPOP: 2341 case ISD::CTLZ: 2342 case ISD::CTTZ: 2343 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2344 Results.push_back(Tmp1); 2345 break; 2346 case ISD::BSWAP: 2347 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2348 break; 2349 case ISD::FRAMEADDR: 2350 case ISD::RETURNADDR: 2351 case ISD::FRAME_TO_ARGS_OFFSET: 2352 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2353 break; 2354 case ISD::FLT_ROUNDS_: 2355 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2356 break; 2357 case ISD::EH_RETURN: 2358 case ISD::EH_LABEL: 2359 case ISD::PREFETCH: 2360 case ISD::MEMBARRIER: 2361 case ISD::VAEND: 2362 Results.push_back(Node->getOperand(0)); 2363 break; 2364 case ISD::DYNAMIC_STACKALLOC: 2365 ExpandDYNAMIC_STACKALLOC(Node, Results); 2366 break; 2367 case ISD::MERGE_VALUES: 2368 for (unsigned i = 0; i < Node->getNumValues(); i++) 2369 Results.push_back(Node->getOperand(i)); 2370 break; 2371 case ISD::UNDEF: { 2372 EVT VT = Node->getValueType(0); 2373 if (VT.isInteger()) 2374 Results.push_back(DAG.getConstant(0, VT)); 2375 else { 2376 assert(VT.isFloatingPoint() && "Unknown value type!"); 2377 Results.push_back(DAG.getConstantFP(0, VT)); 2378 } 2379 break; 2380 } 2381 case ISD::TRAP: { 2382 // If this operation is not supported, lower it to 'abort()' call 2383 TargetLowering::ArgListTy Args; 2384 std::pair<SDValue, SDValue> CallResult = 2385 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2386 false, false, false, false, 0, CallingConv::C, false, 2387 /*isReturnValueUsed=*/true, 2388 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2389 Args, DAG, dl); 2390 Results.push_back(CallResult.second); 2391 break; 2392 } 2393 case ISD::FP_ROUND: 2394 case ISD::BIT_CONVERT: 2395 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2396 Node->getValueType(0), dl); 2397 Results.push_back(Tmp1); 2398 break; 2399 case ISD::FP_EXTEND: 2400 Tmp1 = EmitStackConvert(Node->getOperand(0), 2401 Node->getOperand(0).getValueType(), 2402 Node->getValueType(0), dl); 2403 Results.push_back(Tmp1); 2404 break; 2405 case ISD::SIGN_EXTEND_INREG: { 2406 // NOTE: we could fall back on load/store here too for targets without 2407 // SAR. However, it is doubtful that any exist. 2408 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2409 EVT VT = Node->getValueType(0); 2410 EVT ShiftAmountTy = TLI.getShiftAmountTy(); 2411 if (VT.isVector()) 2412 ShiftAmountTy = VT; 2413 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2414 ExtraVT.getScalarType().getSizeInBits(); 2415 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2416 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2417 Node->getOperand(0), ShiftCst); 2418 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2419 Results.push_back(Tmp1); 2420 break; 2421 } 2422 case ISD::FP_ROUND_INREG: { 2423 // The only way we can lower this is to turn it into a TRUNCSTORE, 2424 // EXTLOAD pair, targetting a temporary location (a stack slot). 2425 2426 // NOTE: there is a choice here between constantly creating new stack 2427 // slots and always reusing the same one. We currently always create 2428 // new ones, as reuse may inhibit scheduling. 2429 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2430 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2431 Node->getValueType(0), dl); 2432 Results.push_back(Tmp1); 2433 break; 2434 } 2435 case ISD::SINT_TO_FP: 2436 case ISD::UINT_TO_FP: 2437 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2438 Node->getOperand(0), Node->getValueType(0), dl); 2439 Results.push_back(Tmp1); 2440 break; 2441 case ISD::FP_TO_UINT: { 2442 SDValue True, False; 2443 EVT VT = Node->getOperand(0).getValueType(); 2444 EVT NVT = Node->getValueType(0); 2445 const uint64_t zero[] = {0, 0}; 2446 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 2447 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2448 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2449 Tmp1 = DAG.getConstantFP(apf, VT); 2450 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2451 Node->getOperand(0), 2452 Tmp1, ISD::SETLT); 2453 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2454 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2455 DAG.getNode(ISD::FSUB, dl, VT, 2456 Node->getOperand(0), Tmp1)); 2457 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2458 DAG.getConstant(x, NVT)); 2459 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2460 Results.push_back(Tmp1); 2461 break; 2462 } 2463 case ISD::VAARG: { 2464 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2465 EVT VT = Node->getValueType(0); 2466 Tmp1 = Node->getOperand(0); 2467 Tmp2 = Node->getOperand(1); 2468 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0, 2469 false, false, 0); 2470 // Increment the pointer, VAList, to the next vaarg 2471 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2472 DAG.getConstant(TLI.getTargetData()-> 2473 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2474 TLI.getPointerTy())); 2475 // Store the incremented VAList to the legalized pointer 2476 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0, 2477 false, false, 0); 2478 // Load the actual argument out of the pointer VAList 2479 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0, 2480 false, false, 0)); 2481 Results.push_back(Results[0].getValue(1)); 2482 break; 2483 } 2484 case ISD::VACOPY: { 2485 // This defaults to loading a pointer from the input and storing it to the 2486 // output, returning the chain. 2487 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2488 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2489 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2490 Node->getOperand(2), VS, 0, false, false, 0); 2491 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0, 2492 false, false, 0); 2493 Results.push_back(Tmp1); 2494 break; 2495 } 2496 case ISD::EXTRACT_VECTOR_ELT: 2497 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2498 // This must be an access of the only element. Return it. 2499 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 2500 Node->getOperand(0)); 2501 else 2502 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2503 Results.push_back(Tmp1); 2504 break; 2505 case ISD::EXTRACT_SUBVECTOR: 2506 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2507 break; 2508 case ISD::CONCAT_VECTORS: { 2509 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2510 break; 2511 } 2512 case ISD::SCALAR_TO_VECTOR: 2513 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2514 break; 2515 case ISD::INSERT_VECTOR_ELT: 2516 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2517 Node->getOperand(1), 2518 Node->getOperand(2), dl)); 2519 break; 2520 case ISD::VECTOR_SHUFFLE: { 2521 SmallVector<int, 8> Mask; 2522 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2523 2524 EVT VT = Node->getValueType(0); 2525 EVT EltVT = VT.getVectorElementType(); 2526 unsigned NumElems = VT.getVectorNumElements(); 2527 SmallVector<SDValue, 8> Ops; 2528 for (unsigned i = 0; i != NumElems; ++i) { 2529 if (Mask[i] < 0) { 2530 Ops.push_back(DAG.getUNDEF(EltVT)); 2531 continue; 2532 } 2533 unsigned Idx = Mask[i]; 2534 if (Idx < NumElems) 2535 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2536 Node->getOperand(0), 2537 DAG.getIntPtrConstant(Idx))); 2538 else 2539 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2540 Node->getOperand(1), 2541 DAG.getIntPtrConstant(Idx - NumElems))); 2542 } 2543 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2544 Results.push_back(Tmp1); 2545 break; 2546 } 2547 case ISD::EXTRACT_ELEMENT: { 2548 EVT OpTy = Node->getOperand(0).getValueType(); 2549 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2550 // 1 -> Hi 2551 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2552 DAG.getConstant(OpTy.getSizeInBits()/2, 2553 TLI.getShiftAmountTy())); 2554 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2555 } else { 2556 // 0 -> Lo 2557 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2558 Node->getOperand(0)); 2559 } 2560 Results.push_back(Tmp1); 2561 break; 2562 } 2563 case ISD::STACKSAVE: 2564 // Expand to CopyFromReg if the target set 2565 // StackPointerRegisterToSaveRestore. 2566 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2567 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2568 Node->getValueType(0))); 2569 Results.push_back(Results[0].getValue(1)); 2570 } else { 2571 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2572 Results.push_back(Node->getOperand(0)); 2573 } 2574 break; 2575 case ISD::STACKRESTORE: 2576 // Expand to CopyToReg if the target set 2577 // StackPointerRegisterToSaveRestore. 2578 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2579 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2580 Node->getOperand(1))); 2581 } else { 2582 Results.push_back(Node->getOperand(0)); 2583 } 2584 break; 2585 case ISD::FCOPYSIGN: 2586 Results.push_back(ExpandFCOPYSIGN(Node)); 2587 break; 2588 case ISD::FNEG: 2589 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2590 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2591 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2592 Node->getOperand(0)); 2593 Results.push_back(Tmp1); 2594 break; 2595 case ISD::FABS: { 2596 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2597 EVT VT = Node->getValueType(0); 2598 Tmp1 = Node->getOperand(0); 2599 Tmp2 = DAG.getConstantFP(0.0, VT); 2600 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2601 Tmp1, Tmp2, ISD::SETUGT); 2602 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2603 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2604 Results.push_back(Tmp1); 2605 break; 2606 } 2607 case ISD::FSQRT: 2608 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2609 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2610 break; 2611 case ISD::FSIN: 2612 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2613 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2614 break; 2615 case ISD::FCOS: 2616 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2617 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2618 break; 2619 case ISD::FLOG: 2620 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2621 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2622 break; 2623 case ISD::FLOG2: 2624 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2625 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2626 break; 2627 case ISD::FLOG10: 2628 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2629 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2630 break; 2631 case ISD::FEXP: 2632 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2633 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2634 break; 2635 case ISD::FEXP2: 2636 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2637 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2638 break; 2639 case ISD::FTRUNC: 2640 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2641 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2642 break; 2643 case ISD::FFLOOR: 2644 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2645 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2646 break; 2647 case ISD::FCEIL: 2648 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2649 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2650 break; 2651 case ISD::FRINT: 2652 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2653 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2654 break; 2655 case ISD::FNEARBYINT: 2656 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2657 RTLIB::NEARBYINT_F64, 2658 RTLIB::NEARBYINT_F80, 2659 RTLIB::NEARBYINT_PPCF128)); 2660 break; 2661 case ISD::FPOWI: 2662 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2663 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2664 break; 2665 case ISD::FPOW: 2666 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 2667 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 2668 break; 2669 case ISD::FDIV: 2670 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 2671 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 2672 break; 2673 case ISD::FREM: 2674 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 2675 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 2676 break; 2677 case ISD::FP16_TO_FP32: 2678 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 2679 break; 2680 case ISD::FP32_TO_FP16: 2681 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 2682 break; 2683 case ISD::ConstantFP: { 2684 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 2685 // Check to see if this FP immediate is already legal. 2686 // If this is a legal constant, turn it into a TargetConstantFP node. 2687 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 2688 Results.push_back(SDValue(Node, 0)); 2689 else 2690 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 2691 break; 2692 } 2693 case ISD::EHSELECTION: { 2694 unsigned Reg = TLI.getExceptionSelectorRegister(); 2695 assert(Reg && "Can't expand to unknown register!"); 2696 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 2697 Node->getValueType(0))); 2698 Results.push_back(Results[0].getValue(1)); 2699 break; 2700 } 2701 case ISD::EXCEPTIONADDR: { 2702 unsigned Reg = TLI.getExceptionAddressRegister(); 2703 assert(Reg && "Can't expand to unknown register!"); 2704 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 2705 Node->getValueType(0))); 2706 Results.push_back(Results[0].getValue(1)); 2707 break; 2708 } 2709 case ISD::SUB: { 2710 EVT VT = Node->getValueType(0); 2711 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 2712 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 2713 "Don't know how to expand this subtraction!"); 2714 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 2715 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 2716 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 2717 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 2718 break; 2719 } 2720 case ISD::UREM: 2721 case ISD::SREM: { 2722 EVT VT = Node->getValueType(0); 2723 SDVTList VTs = DAG.getVTList(VT, VT); 2724 bool isSigned = Node->getOpcode() == ISD::SREM; 2725 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 2726 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2727 Tmp2 = Node->getOperand(0); 2728 Tmp3 = Node->getOperand(1); 2729 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 2730 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 2731 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 2732 // X % Y -> X-X/Y*Y 2733 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 2734 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 2735 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 2736 } else if (isSigned) { 2737 Tmp1 = ExpandIntLibCall(Node, true, 2738 RTLIB::SREM_I8, 2739 RTLIB::SREM_I16, RTLIB::SREM_I32, 2740 RTLIB::SREM_I64, RTLIB::SREM_I128); 2741 } else { 2742 Tmp1 = ExpandIntLibCall(Node, false, 2743 RTLIB::UREM_I8, 2744 RTLIB::UREM_I16, RTLIB::UREM_I32, 2745 RTLIB::UREM_I64, RTLIB::UREM_I128); 2746 } 2747 Results.push_back(Tmp1); 2748 break; 2749 } 2750 case ISD::UDIV: 2751 case ISD::SDIV: { 2752 bool isSigned = Node->getOpcode() == ISD::SDIV; 2753 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2754 EVT VT = Node->getValueType(0); 2755 SDVTList VTs = DAG.getVTList(VT, VT); 2756 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 2757 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 2758 Node->getOperand(1)); 2759 else if (isSigned) 2760 Tmp1 = ExpandIntLibCall(Node, true, 2761 RTLIB::SDIV_I8, 2762 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 2763 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 2764 else 2765 Tmp1 = ExpandIntLibCall(Node, false, 2766 RTLIB::UDIV_I8, 2767 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 2768 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 2769 Results.push_back(Tmp1); 2770 break; 2771 } 2772 case ISD::MULHU: 2773 case ISD::MULHS: { 2774 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 2775 ISD::SMUL_LOHI; 2776 EVT VT = Node->getValueType(0); 2777 SDVTList VTs = DAG.getVTList(VT, VT); 2778 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 2779 "If this wasn't legal, it shouldn't have been created!"); 2780 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 2781 Node->getOperand(1)); 2782 Results.push_back(Tmp1.getValue(1)); 2783 break; 2784 } 2785 case ISD::MUL: { 2786 EVT VT = Node->getValueType(0); 2787 SDVTList VTs = DAG.getVTList(VT, VT); 2788 // See if multiply or divide can be lowered using two-result operations. 2789 // We just need the low half of the multiply; try both the signed 2790 // and unsigned forms. If the target supports both SMUL_LOHI and 2791 // UMUL_LOHI, form a preference by checking which forms of plain 2792 // MULH it supports. 2793 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 2794 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 2795 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 2796 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 2797 unsigned OpToUse = 0; 2798 if (HasSMUL_LOHI && !HasMULHS) { 2799 OpToUse = ISD::SMUL_LOHI; 2800 } else if (HasUMUL_LOHI && !HasMULHU) { 2801 OpToUse = ISD::UMUL_LOHI; 2802 } else if (HasSMUL_LOHI) { 2803 OpToUse = ISD::SMUL_LOHI; 2804 } else if (HasUMUL_LOHI) { 2805 OpToUse = ISD::UMUL_LOHI; 2806 } 2807 if (OpToUse) { 2808 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 2809 Node->getOperand(1))); 2810 break; 2811 } 2812 Tmp1 = ExpandIntLibCall(Node, false, 2813 RTLIB::MUL_I8, 2814 RTLIB::MUL_I16, RTLIB::MUL_I32, 2815 RTLIB::MUL_I64, RTLIB::MUL_I128); 2816 Results.push_back(Tmp1); 2817 break; 2818 } 2819 case ISD::SADDO: 2820 case ISD::SSUBO: { 2821 SDValue LHS = Node->getOperand(0); 2822 SDValue RHS = Node->getOperand(1); 2823 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 2824 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2825 LHS, RHS); 2826 Results.push_back(Sum); 2827 EVT OType = Node->getValueType(1); 2828 2829 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 2830 2831 // LHSSign -> LHS >= 0 2832 // RHSSign -> RHS >= 0 2833 // SumSign -> Sum >= 0 2834 // 2835 // Add: 2836 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 2837 // Sub: 2838 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 2839 // 2840 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 2841 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 2842 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 2843 Node->getOpcode() == ISD::SADDO ? 2844 ISD::SETEQ : ISD::SETNE); 2845 2846 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 2847 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 2848 2849 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 2850 Results.push_back(Cmp); 2851 break; 2852 } 2853 case ISD::UADDO: 2854 case ISD::USUBO: { 2855 SDValue LHS = Node->getOperand(0); 2856 SDValue RHS = Node->getOperand(1); 2857 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 2858 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2859 LHS, RHS); 2860 Results.push_back(Sum); 2861 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 2862 Node->getOpcode () == ISD::UADDO ? 2863 ISD::SETULT : ISD::SETUGT)); 2864 break; 2865 } 2866 case ISD::UMULO: 2867 case ISD::SMULO: { 2868 EVT VT = Node->getValueType(0); 2869 SDValue LHS = Node->getOperand(0); 2870 SDValue RHS = Node->getOperand(1); 2871 SDValue BottomHalf; 2872 SDValue TopHalf; 2873 static const unsigned Ops[2][3] = 2874 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 2875 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 2876 bool isSigned = Node->getOpcode() == ISD::SMULO; 2877 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 2878 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 2879 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 2880 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 2881 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 2882 RHS); 2883 TopHalf = BottomHalf.getValue(1); 2884 } else { 2885 // FIXME: We should be able to fall back to a libcall with an illegal 2886 // type in some cases. 2887 // Also, we can fall back to a division in some cases, but that's a big 2888 // performance hit in the general case. 2889 assert(TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), 2890 VT.getSizeInBits() * 2)) && 2891 "Don't know how to expand this operation yet!"); 2892 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 2893 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 2894 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 2895 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 2896 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2897 DAG.getIntPtrConstant(0)); 2898 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2899 DAG.getIntPtrConstant(1)); 2900 } 2901 if (isSigned) { 2902 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); 2903 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 2904 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 2905 ISD::SETNE); 2906 } else { 2907 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 2908 DAG.getConstant(0, VT), ISD::SETNE); 2909 } 2910 Results.push_back(BottomHalf); 2911 Results.push_back(TopHalf); 2912 break; 2913 } 2914 case ISD::BUILD_PAIR: { 2915 EVT PairTy = Node->getValueType(0); 2916 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 2917 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 2918 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 2919 DAG.getConstant(PairTy.getSizeInBits()/2, 2920 TLI.getShiftAmountTy())); 2921 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 2922 break; 2923 } 2924 case ISD::SELECT: 2925 Tmp1 = Node->getOperand(0); 2926 Tmp2 = Node->getOperand(1); 2927 Tmp3 = Node->getOperand(2); 2928 if (Tmp1.getOpcode() == ISD::SETCC) { 2929 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 2930 Tmp2, Tmp3, 2931 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2932 } else { 2933 Tmp1 = DAG.getSelectCC(dl, Tmp1, 2934 DAG.getConstant(0, Tmp1.getValueType()), 2935 Tmp2, Tmp3, ISD::SETNE); 2936 } 2937 Results.push_back(Tmp1); 2938 break; 2939 case ISD::BR_JT: { 2940 SDValue Chain = Node->getOperand(0); 2941 SDValue Table = Node->getOperand(1); 2942 SDValue Index = Node->getOperand(2); 2943 2944 EVT PTy = TLI.getPointerTy(); 2945 2946 const TargetData &TD = *TLI.getTargetData(); 2947 unsigned EntrySize = 2948 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 2949 2950 Index = DAG.getNode(ISD::MUL, dl, PTy, 2951 Index, DAG.getConstant(EntrySize, PTy)); 2952 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2953 2954 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 2955 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 2956 PseudoSourceValue::getJumpTable(), 0, MemVT, 2957 false, false, 0); 2958 Addr = LD; 2959 if (TM.getRelocationModel() == Reloc::PIC_) { 2960 // For PIC, the sequence is: 2961 // BRIND(load(Jumptable + index) + RelocBase) 2962 // RelocBase can be JumpTable, GOT or some sort of global base. 2963 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 2964 TLI.getPICJumpTableRelocBase(Table, DAG)); 2965 } 2966 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 2967 Results.push_back(Tmp1); 2968 break; 2969 } 2970 case ISD::BRCOND: 2971 // Expand brcond's setcc into its constituent parts and create a BR_CC 2972 // Node. 2973 Tmp1 = Node->getOperand(0); 2974 Tmp2 = Node->getOperand(1); 2975 if (Tmp2.getOpcode() == ISD::SETCC) { 2976 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 2977 Tmp1, Tmp2.getOperand(2), 2978 Tmp2.getOperand(0), Tmp2.getOperand(1), 2979 Node->getOperand(2)); 2980 } else { 2981 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 2982 DAG.getCondCode(ISD::SETNE), Tmp2, 2983 DAG.getConstant(0, Tmp2.getValueType()), 2984 Node->getOperand(2)); 2985 } 2986 Results.push_back(Tmp1); 2987 break; 2988 case ISD::SETCC: { 2989 Tmp1 = Node->getOperand(0); 2990 Tmp2 = Node->getOperand(1); 2991 Tmp3 = Node->getOperand(2); 2992 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 2993 2994 // If we expanded the SETCC into an AND/OR, return the new node 2995 if (Tmp2.getNode() == 0) { 2996 Results.push_back(Tmp1); 2997 break; 2998 } 2999 3000 // Otherwise, SETCC for the given comparison type must be completely 3001 // illegal; expand it into a SELECT_CC. 3002 EVT VT = Node->getValueType(0); 3003 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3004 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 3005 Results.push_back(Tmp1); 3006 break; 3007 } 3008 case ISD::SELECT_CC: { 3009 Tmp1 = Node->getOperand(0); // LHS 3010 Tmp2 = Node->getOperand(1); // RHS 3011 Tmp3 = Node->getOperand(2); // True 3012 Tmp4 = Node->getOperand(3); // False 3013 SDValue CC = Node->getOperand(4); 3014 3015 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 3016 Tmp1, Tmp2, CC, dl); 3017 3018 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 3019 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3020 CC = DAG.getCondCode(ISD::SETNE); 3021 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 3022 Tmp3, Tmp4, CC); 3023 Results.push_back(Tmp1); 3024 break; 3025 } 3026 case ISD::BR_CC: { 3027 Tmp1 = Node->getOperand(0); // Chain 3028 Tmp2 = Node->getOperand(2); // LHS 3029 Tmp3 = Node->getOperand(3); // RHS 3030 Tmp4 = Node->getOperand(1); // CC 3031 3032 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 3033 Tmp2, Tmp3, Tmp4, dl); 3034 LastCALLSEQ_END = DAG.getEntryNode(); 3035 3036 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 3037 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 3038 Tmp4 = DAG.getCondCode(ISD::SETNE); 3039 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 3040 Tmp3, Node->getOperand(4)); 3041 Results.push_back(Tmp1); 3042 break; 3043 } 3044 case ISD::GLOBAL_OFFSET_TABLE: 3045 case ISD::GlobalAddress: 3046 case ISD::GlobalTLSAddress: 3047 case ISD::ExternalSymbol: 3048 case ISD::ConstantPool: 3049 case ISD::JumpTable: 3050 case ISD::INTRINSIC_W_CHAIN: 3051 case ISD::INTRINSIC_WO_CHAIN: 3052 case ISD::INTRINSIC_VOID: 3053 // FIXME: Custom lowering for these operations shouldn't return null! 3054 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3055 Results.push_back(SDValue(Node, i)); 3056 break; 3057 } 3058} 3059void SelectionDAGLegalize::PromoteNode(SDNode *Node, 3060 SmallVectorImpl<SDValue> &Results) { 3061 EVT OVT = Node->getValueType(0); 3062 if (Node->getOpcode() == ISD::UINT_TO_FP || 3063 Node->getOpcode() == ISD::SINT_TO_FP || 3064 Node->getOpcode() == ISD::SETCC) { 3065 OVT = Node->getOperand(0).getValueType(); 3066 } 3067 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3068 DebugLoc dl = Node->getDebugLoc(); 3069 SDValue Tmp1, Tmp2, Tmp3; 3070 switch (Node->getOpcode()) { 3071 case ISD::CTTZ: 3072 case ISD::CTLZ: 3073 case ISD::CTPOP: 3074 // Zero extend the argument. 3075 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3076 // Perform the larger operation. 3077 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3078 if (Node->getOpcode() == ISD::CTTZ) { 3079 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3080 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 3081 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3082 ISD::SETEQ); 3083 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3084 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3085 } else if (Node->getOpcode() == ISD::CTLZ) { 3086 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3087 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3088 DAG.getConstant(NVT.getSizeInBits() - 3089 OVT.getSizeInBits(), NVT)); 3090 } 3091 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3092 break; 3093 case ISD::BSWAP: { 3094 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3095 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3096 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3097 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3098 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3099 Results.push_back(Tmp1); 3100 break; 3101 } 3102 case ISD::FP_TO_UINT: 3103 case ISD::FP_TO_SINT: 3104 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3105 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3106 Results.push_back(Tmp1); 3107 break; 3108 case ISD::UINT_TO_FP: 3109 case ISD::SINT_TO_FP: 3110 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3111 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3112 Results.push_back(Tmp1); 3113 break; 3114 case ISD::AND: 3115 case ISD::OR: 3116 case ISD::XOR: { 3117 unsigned ExtOp, TruncOp; 3118 if (OVT.isVector()) { 3119 ExtOp = ISD::BIT_CONVERT; 3120 TruncOp = ISD::BIT_CONVERT; 3121 } else { 3122 assert(OVT.isInteger() && "Cannot promote logic operation"); 3123 ExtOp = ISD::ANY_EXTEND; 3124 TruncOp = ISD::TRUNCATE; 3125 } 3126 // Promote each of the values to the new type. 3127 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3128 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3129 // Perform the larger operation, then convert back 3130 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3131 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3132 break; 3133 } 3134 case ISD::SELECT: { 3135 unsigned ExtOp, TruncOp; 3136 if (Node->getValueType(0).isVector()) { 3137 ExtOp = ISD::BIT_CONVERT; 3138 TruncOp = ISD::BIT_CONVERT; 3139 } else if (Node->getValueType(0).isInteger()) { 3140 ExtOp = ISD::ANY_EXTEND; 3141 TruncOp = ISD::TRUNCATE; 3142 } else { 3143 ExtOp = ISD::FP_EXTEND; 3144 TruncOp = ISD::FP_ROUND; 3145 } 3146 Tmp1 = Node->getOperand(0); 3147 // Promote each of the values to the new type. 3148 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3149 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3150 // Perform the larger operation, then round down. 3151 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3152 if (TruncOp != ISD::FP_ROUND) 3153 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3154 else 3155 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3156 DAG.getIntPtrConstant(0)); 3157 Results.push_back(Tmp1); 3158 break; 3159 } 3160 case ISD::VECTOR_SHUFFLE: { 3161 SmallVector<int, 8> Mask; 3162 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3163 3164 // Cast the two input vectors. 3165 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3166 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3167 3168 // Convert the shuffle mask to the right # elements. 3169 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3170 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); 3171 Results.push_back(Tmp1); 3172 break; 3173 } 3174 case ISD::SETCC: { 3175 unsigned ExtOp = ISD::FP_EXTEND; 3176 if (NVT.isInteger()) { 3177 ISD::CondCode CCCode = 3178 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3179 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3180 } 3181 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3182 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3183 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3184 Tmp1, Tmp2, Node->getOperand(2))); 3185 break; 3186 } 3187 } 3188} 3189 3190// SelectionDAG::Legalize - This is the entry point for the file. 3191// 3192void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) { 3193 /// run - This is the main entry point to this class. 3194 /// 3195 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3196} 3197 3198