LegalizeDAG.cpp revision 19f229a5aa5fa80405a67fd662e5e53c9a3a451e
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/Target/TargetFrameInfo.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetMachine.h" 22#include "llvm/Target/TargetOptions.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/DerivedTypes.h" 26#include "llvm/Support/MathExtras.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Compiler.h" 29#include "llvm/ADT/DenseMap.h" 30#include "llvm/ADT/SmallVector.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include <map> 33using namespace llvm; 34 35#ifndef NDEBUG 36static cl::opt<bool> 37ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 38 cl::desc("Pop up a window to show dags before legalize")); 39#else 40static const bool ViewLegalizeDAGs = 0; 41#endif 42 43//===----------------------------------------------------------------------===// 44/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 45/// hacks on it until the target machine can handle it. This involves 46/// eliminating value sizes the machine cannot handle (promoting small sizes to 47/// large sizes or splitting up large values into small values) as well as 48/// eliminating operations the machine cannot handle. 49/// 50/// This code also does a small amount of optimization and recognition of idioms 51/// as part of its processing. For example, if a target does not support a 52/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 53/// will attempt merge setcc and brc instructions into brcc's. 54/// 55namespace { 56class VISIBILITY_HIDDEN SelectionDAGLegalize { 57 TargetLowering &TLI; 58 SelectionDAG &DAG; 59 60 // Libcall insertion helpers. 61 62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 63 /// legalized. We use this to ensure that calls are properly serialized 64 /// against each other, including inserted libcalls. 65 SDOperand LastCALLSEQ_END; 66 67 /// IsLegalizingCall - This member is used *only* for purposes of providing 68 /// helpful assertions that a libcall isn't created while another call is 69 /// being legalized (which could lead to non-serialized call sequences). 70 bool IsLegalizingCall; 71 72 enum LegalizeAction { 73 Legal, // The target natively supports this operation. 74 Promote, // This operation should be executed in a larger type. 75 Expand // Try to expand this to other ops, otherwise use a libcall. 76 }; 77 78 /// ValueTypeActions - This is a bitvector that contains two bits for each 79 /// value type, where the two bits correspond to the LegalizeAction enum. 80 /// This can be queried with "getTypeAction(VT)". 81 TargetLowering::ValueTypeActionImpl ValueTypeActions; 82 83 /// LegalizedNodes - For nodes that are of legal width, and that have more 84 /// than one use, this map indicates what regularized operand to use. This 85 /// allows us to avoid legalizing the same thing more than once. 86 DenseMap<SDOperand, SDOperand> LegalizedNodes; 87 88 /// PromotedNodes - For nodes that are below legal width, and that have more 89 /// than one use, this map indicates what promoted value to use. This allows 90 /// us to avoid promoting the same thing more than once. 91 DenseMap<SDOperand, SDOperand> PromotedNodes; 92 93 /// ExpandedNodes - For nodes that need to be expanded this map indicates 94 /// which which operands are the expanded version of the input. This allows 95 /// us to avoid expanding the same node more than once. 96 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 97 98 /// SplitNodes - For vector nodes that need to be split, this map indicates 99 /// which which operands are the split version of the input. This allows us 100 /// to avoid splitting the same node more than once. 101 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 102 103 /// ScalarizedNodes - For nodes that need to be converted from vector types to 104 /// scalar types, this contains the mapping of ones we have already 105 /// processed to the result. 106 std::map<SDOperand, SDOperand> ScalarizedNodes; 107 108 void AddLegalizedOperand(SDOperand From, SDOperand To) { 109 LegalizedNodes.insert(std::make_pair(From, To)); 110 // If someone requests legalization of the new node, return itself. 111 if (From != To) 112 LegalizedNodes.insert(std::make_pair(To, To)); 113 } 114 void AddPromotedOperand(SDOperand From, SDOperand To) { 115 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 116 assert(isNew && "Got into the map somehow?"); 117 // If someone requests legalization of the new node, return itself. 118 LegalizedNodes.insert(std::make_pair(To, To)); 119 } 120 121public: 122 123 SelectionDAGLegalize(SelectionDAG &DAG); 124 125 /// getTypeAction - Return how we should legalize values of this type, either 126 /// it is already legal or we need to expand it into multiple registers of 127 /// smaller integer type, or we need to promote it to a larger type. 128 LegalizeAction getTypeAction(MVT::ValueType VT) const { 129 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 130 } 131 132 /// isTypeLegal - Return true if this type is legal on this target. 133 /// 134 bool isTypeLegal(MVT::ValueType VT) const { 135 return getTypeAction(VT) == Legal; 136 } 137 138 void LegalizeDAG(); 139 140private: 141 /// HandleOp - Legalize, Promote, or Expand the specified operand as 142 /// appropriate for its type. 143 void HandleOp(SDOperand Op); 144 145 /// LegalizeOp - We know that the specified value has a legal type. 146 /// Recursively ensure that the operands have legal types, then return the 147 /// result. 148 SDOperand LegalizeOp(SDOperand O); 149 150 /// UnrollVectorOp - We know that the given vector has a legal type, however 151 /// the operation it performs is not legal and is an operation that we have 152 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 153 /// operating on each element individually. 154 SDOperand UnrollVectorOp(SDOperand O); 155 156 /// PromoteOp - Given an operation that produces a value in an invalid type, 157 /// promote it to compute the value into a larger type. The produced value 158 /// will have the correct bits for the low portion of the register, but no 159 /// guarantee is made about the top bits: it may be zero, sign-extended, or 160 /// garbage. 161 SDOperand PromoteOp(SDOperand O); 162 163 /// ExpandOp - Expand the specified SDOperand into its two component pieces 164 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 165 /// the LegalizeNodes map is filled in for any results that are not expanded, 166 /// the ExpandedNodes map is filled in for any results that are expanded, and 167 /// the Lo/Hi values are returned. This applies to integer types and Vector 168 /// types. 169 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 170 171 /// SplitVectorOp - Given an operand of vector type, break it down into 172 /// two smaller values. 173 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 174 175 /// ScalarizeVectorOp - Given an operand of single-element vector type 176 /// (e.g. v1f32), convert it into the equivalent operation that returns a 177 /// scalar (e.g. f32) value. 178 SDOperand ScalarizeVectorOp(SDOperand O); 179 180 /// isShuffleLegal - Return true if a vector shuffle is legal with the 181 /// specified mask and type. Targets can specify exactly which masks they 182 /// support and the code generator is tasked with not creating illegal masks. 183 /// 184 /// Note that this will also return true for shuffles that are promoted to a 185 /// different type. 186 /// 187 /// If this is a legal shuffle, this method returns the (possibly promoted) 188 /// build_vector Mask. If it's not a legal shuffle, it returns null. 189 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 190 191 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 192 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 193 194 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 195 196 SDOperand CreateStackTemporary(MVT::ValueType VT); 197 198 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 199 SDOperand &Hi); 200 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 201 SDOperand Source); 202 203 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 204 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 205 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 206 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 207 SDOperand LegalOp, 208 MVT::ValueType DestVT); 209 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 210 bool isSigned); 211 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 212 bool isSigned); 213 214 SDOperand ExpandBSWAP(SDOperand Op); 215 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 216 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 217 SDOperand &Lo, SDOperand &Hi); 218 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 219 SDOperand &Lo, SDOperand &Hi); 220 221 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 222 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 223 224 SDOperand getIntPtrConstant(uint64_t Val) { 225 return DAG.getConstant(Val, TLI.getPointerTy()); 226 } 227}; 228} 229 230/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 231/// specified mask and type. Targets can specify exactly which masks they 232/// support and the code generator is tasked with not creating illegal masks. 233/// 234/// Note that this will also return true for shuffles that are promoted to a 235/// different type. 236SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 237 SDOperand Mask) const { 238 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 239 default: return 0; 240 case TargetLowering::Legal: 241 case TargetLowering::Custom: 242 break; 243 case TargetLowering::Promote: { 244 // If this is promoted to a different type, convert the shuffle mask and 245 // ask if it is legal in the promoted type! 246 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 247 248 // If we changed # elements, change the shuffle mask. 249 unsigned NumEltsGrowth = 250 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 251 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 252 if (NumEltsGrowth > 1) { 253 // Renumber the elements. 254 SmallVector<SDOperand, 8> Ops; 255 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 256 SDOperand InOp = Mask.getOperand(i); 257 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 258 if (InOp.getOpcode() == ISD::UNDEF) 259 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 260 else { 261 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 262 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 263 } 264 } 265 } 266 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 267 } 268 VT = NVT; 269 break; 270 } 271 } 272 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 273} 274 275SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 276 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 277 ValueTypeActions(TLI.getValueTypeActions()) { 278 assert(MVT::LAST_VALUETYPE <= 32 && 279 "Too many value types for ValueTypeActions to hold!"); 280} 281 282/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 283/// contains all of a nodes operands before it contains the node. 284static void ComputeTopDownOrdering(SelectionDAG &DAG, 285 SmallVector<SDNode*, 64> &Order) { 286 287 DenseMap<SDNode*, unsigned> Visited; 288 std::vector<SDNode*> Worklist; 289 Worklist.reserve(128); 290 291 // Compute ordering from all of the leaves in the graphs, those (like the 292 // entry node) that have no operands. 293 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 294 E = DAG.allnodes_end(); I != E; ++I) { 295 if (I->getNumOperands() == 0) { 296 Visited[I] = 0 - 1U; 297 Worklist.push_back(I); 298 } 299 } 300 301 while (!Worklist.empty()) { 302 SDNode *N = Worklist.back(); 303 Worklist.pop_back(); 304 305 if (++Visited[N] != N->getNumOperands()) 306 continue; // Haven't visited all operands yet 307 308 Order.push_back(N); 309 310 // Now that we have N in, add anything that uses it if all of their operands 311 // are now done. 312 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 313 UI != E; ++UI) 314 Worklist.push_back(*UI); 315 } 316 317 assert(Order.size() == Visited.size() && 318 Order.size() == 319 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 320 "Error: DAG is cyclic!"); 321} 322 323 324void SelectionDAGLegalize::LegalizeDAG() { 325 LastCALLSEQ_END = DAG.getEntryNode(); 326 IsLegalizingCall = false; 327 328 // The legalize process is inherently a bottom-up recursive process (users 329 // legalize their uses before themselves). Given infinite stack space, we 330 // could just start legalizing on the root and traverse the whole graph. In 331 // practice however, this causes us to run out of stack space on large basic 332 // blocks. To avoid this problem, compute an ordering of the nodes where each 333 // node is only legalized after all of its operands are legalized. 334 SmallVector<SDNode*, 64> Order; 335 ComputeTopDownOrdering(DAG, Order); 336 337 for (unsigned i = 0, e = Order.size(); i != e; ++i) 338 HandleOp(SDOperand(Order[i], 0)); 339 340 // Finally, it's possible the root changed. Get the new root. 341 SDOperand OldRoot = DAG.getRoot(); 342 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 343 DAG.setRoot(LegalizedNodes[OldRoot]); 344 345 ExpandedNodes.clear(); 346 LegalizedNodes.clear(); 347 PromotedNodes.clear(); 348 SplitNodes.clear(); 349 ScalarizedNodes.clear(); 350 351 // Remove dead nodes now. 352 DAG.RemoveDeadNodes(); 353} 354 355 356/// FindCallEndFromCallStart - Given a chained node that is part of a call 357/// sequence, find the CALLSEQ_END node that terminates the call sequence. 358static SDNode *FindCallEndFromCallStart(SDNode *Node) { 359 if (Node->getOpcode() == ISD::CALLSEQ_END) 360 return Node; 361 if (Node->use_empty()) 362 return 0; // No CallSeqEnd 363 364 // The chain is usually at the end. 365 SDOperand TheChain(Node, Node->getNumValues()-1); 366 if (TheChain.getValueType() != MVT::Other) { 367 // Sometimes it's at the beginning. 368 TheChain = SDOperand(Node, 0); 369 if (TheChain.getValueType() != MVT::Other) { 370 // Otherwise, hunt for it. 371 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 372 if (Node->getValueType(i) == MVT::Other) { 373 TheChain = SDOperand(Node, i); 374 break; 375 } 376 377 // Otherwise, we walked into a node without a chain. 378 if (TheChain.getValueType() != MVT::Other) 379 return 0; 380 } 381 } 382 383 for (SDNode::use_iterator UI = Node->use_begin(), 384 E = Node->use_end(); UI != E; ++UI) { 385 386 // Make sure to only follow users of our token chain. 387 SDNode *User = *UI; 388 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 389 if (User->getOperand(i) == TheChain) 390 if (SDNode *Result = FindCallEndFromCallStart(User)) 391 return Result; 392 } 393 return 0; 394} 395 396/// FindCallStartFromCallEnd - Given a chained node that is part of a call 397/// sequence, find the CALLSEQ_START node that initiates the call sequence. 398static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 399 assert(Node && "Didn't find callseq_start for a call??"); 400 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 401 402 assert(Node->getOperand(0).getValueType() == MVT::Other && 403 "Node doesn't have a token chain argument!"); 404 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 405} 406 407/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 408/// see if any uses can reach Dest. If no dest operands can get to dest, 409/// legalize them, legalize ourself, and return false, otherwise, return true. 410/// 411/// Keep track of the nodes we fine that actually do lead to Dest in 412/// NodesLeadingTo. This avoids retraversing them exponential number of times. 413/// 414bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 415 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 416 if (N == Dest) return true; // N certainly leads to Dest :) 417 418 // If we've already processed this node and it does lead to Dest, there is no 419 // need to reprocess it. 420 if (NodesLeadingTo.count(N)) return true; 421 422 // If the first result of this node has been already legalized, then it cannot 423 // reach N. 424 switch (getTypeAction(N->getValueType(0))) { 425 case Legal: 426 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 427 break; 428 case Promote: 429 if (PromotedNodes.count(SDOperand(N, 0))) return false; 430 break; 431 case Expand: 432 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 433 break; 434 } 435 436 // Okay, this node has not already been legalized. Check and legalize all 437 // operands. If none lead to Dest, then we can legalize this node. 438 bool OperandsLeadToDest = false; 439 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 440 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 441 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 442 443 if (OperandsLeadToDest) { 444 NodesLeadingTo.insert(N); 445 return true; 446 } 447 448 // Okay, this node looks safe, legalize it and return false. 449 HandleOp(SDOperand(N, 0)); 450 return false; 451} 452 453/// HandleOp - Legalize, Promote, or Expand the specified operand as 454/// appropriate for its type. 455void SelectionDAGLegalize::HandleOp(SDOperand Op) { 456 MVT::ValueType VT = Op.getValueType(); 457 switch (getTypeAction(VT)) { 458 default: assert(0 && "Bad type action!"); 459 case Legal: (void)LegalizeOp(Op); break; 460 case Promote: (void)PromoteOp(Op); break; 461 case Expand: 462 if (!MVT::isVector(VT)) { 463 // If this is an illegal scalar, expand it into its two component 464 // pieces. 465 SDOperand X, Y; 466 if (Op.getOpcode() == ISD::TargetConstant) 467 break; // Allow illegal target nodes. 468 ExpandOp(Op, X, Y); 469 } else if (MVT::getVectorNumElements(VT) == 1) { 470 // If this is an illegal single element vector, convert it to a 471 // scalar operation. 472 (void)ScalarizeVectorOp(Op); 473 } else { 474 // Otherwise, this is an illegal multiple element vector. 475 // Split it in half and legalize both parts. 476 SDOperand X, Y; 477 SplitVectorOp(Op, X, Y); 478 } 479 break; 480 } 481} 482 483/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 484/// a load from the constant pool. 485static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 486 SelectionDAG &DAG, TargetLowering &TLI) { 487 bool Extend = false; 488 489 // If a FP immediate is precise when represented as a float and if the 490 // target can do an extending load from float to double, we put it into 491 // the constant pool as a float, even if it's is statically typed as a 492 // double. 493 MVT::ValueType VT = CFP->getValueType(0); 494 bool isDouble = VT == MVT::f64; 495 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT), 496 CFP->getValueAPF()); 497 if (!UseCP) { 498 if (VT!=MVT::f64 && VT!=MVT::f32) 499 assert(0 && "Invalid type expansion"); 500 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(), 501 isDouble ? MVT::i64 : MVT::i32); 502 } 503 504 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) && 505 // Only do this if the target has a native EXTLOAD instruction from f32. 506 // Do not try to be clever about long doubles (so far) 507 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 508 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); 509 VT = MVT::f32; 510 Extend = true; 511 } 512 513 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 514 if (Extend) { 515 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 516 CPIdx, NULL, 0, MVT::f32); 517 } else { 518 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 519 } 520} 521 522 523/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 524/// operations. 525static 526SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 527 SelectionDAG &DAG, TargetLowering &TLI) { 528 MVT::ValueType VT = Node->getValueType(0); 529 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 530 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 531 "fcopysign expansion only supported for f32 and f64"); 532 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 533 534 // First get the sign bit of second operand. 535 SDOperand Mask1 = (SrcVT == MVT::f64) 536 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 537 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 538 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 539 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 540 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 541 // Shift right or sign-extend it if the two operands have different types. 542 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 543 if (SizeDiff > 0) { 544 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 545 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 546 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 547 } else if (SizeDiff < 0) 548 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 549 550 // Clear the sign bit of first operand. 551 SDOperand Mask2 = (VT == MVT::f64) 552 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 553 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 554 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 555 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 556 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 557 558 // Or the value with the sign bit. 559 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 560 return Result; 561} 562 563/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 564static 565SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 566 TargetLowering &TLI) { 567 SDOperand Chain = ST->getChain(); 568 SDOperand Ptr = ST->getBasePtr(); 569 SDOperand Val = ST->getValue(); 570 MVT::ValueType VT = Val.getValueType(); 571 int Alignment = ST->getAlignment(); 572 int SVOffset = ST->getSrcValueOffset(); 573 if (MVT::isFloatingPoint(ST->getStoredVT())) { 574 // Expand to a bitconvert of the value to the integer type of the 575 // same size, then a (misaligned) int store. 576 MVT::ValueType intVT; 577 if (VT==MVT::f64) 578 intVT = MVT::i64; 579 else if (VT==MVT::f32) 580 intVT = MVT::i32; 581 else 582 assert(0 && "Unaligned load of unsupported floating point type"); 583 584 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 585 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 586 SVOffset, ST->isVolatile(), Alignment); 587 } 588 assert(MVT::isInteger(ST->getStoredVT()) && 589 "Unaligned store of unknown type."); 590 // Get the half-size VT 591 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1; 592 int NumBits = MVT::getSizeInBits(NewStoredVT); 593 int IncrementSize = NumBits / 8; 594 595 // Divide the stored value in two parts. 596 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 597 SDOperand Lo = Val; 598 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 599 600 // Store the two parts 601 SDOperand Store1, Store2; 602 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 603 ST->getSrcValue(), SVOffset, NewStoredVT, 604 ST->isVolatile(), Alignment); 605 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 606 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 607 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 608 ST->getSrcValue(), SVOffset + IncrementSize, 609 NewStoredVT, ST->isVolatile(), Alignment); 610 611 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 612} 613 614/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 615static 616SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 617 TargetLowering &TLI) { 618 int SVOffset = LD->getSrcValueOffset(); 619 SDOperand Chain = LD->getChain(); 620 SDOperand Ptr = LD->getBasePtr(); 621 MVT::ValueType VT = LD->getValueType(0); 622 MVT::ValueType LoadedVT = LD->getLoadedVT(); 623 if (MVT::isFloatingPoint(VT)) { 624 // Expand to a (misaligned) integer load of the same size, 625 // then bitconvert to floating point. 626 MVT::ValueType intVT; 627 if (LoadedVT==MVT::f64) 628 intVT = MVT::i64; 629 else if (LoadedVT==MVT::f32) 630 intVT = MVT::i32; 631 else 632 assert(0 && "Unaligned load of unsupported floating point type"); 633 634 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 635 SVOffset, LD->isVolatile(), 636 LD->getAlignment()); 637 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 638 if (LoadedVT != VT) 639 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 640 641 SDOperand Ops[] = { Result, Chain }; 642 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 643 Ops, 2); 644 } 645 assert(MVT::isInteger(LoadedVT) && "Unaligned load of unsupported type."); 646 MVT::ValueType NewLoadedVT = LoadedVT - 1; 647 int NumBits = MVT::getSizeInBits(NewLoadedVT); 648 int Alignment = LD->getAlignment(); 649 int IncrementSize = NumBits / 8; 650 ISD::LoadExtType HiExtType = LD->getExtensionType(); 651 652 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 653 if (HiExtType == ISD::NON_EXTLOAD) 654 HiExtType = ISD::ZEXTLOAD; 655 656 // Load the value in two parts 657 SDOperand Lo, Hi; 658 if (TLI.isLittleEndian()) { 659 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 660 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 661 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 662 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 663 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 664 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 665 Alignment); 666 } else { 667 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 668 NewLoadedVT,LD->isVolatile(), Alignment); 669 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 670 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 671 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 672 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 673 Alignment); 674 } 675 676 // aggregate the two parts 677 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 678 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 679 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 680 681 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 682 Hi.getValue(1)); 683 684 SDOperand Ops[] = { Result, TF }; 685 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 686} 687 688/// UnrollVectorOp - We know that the given vector has a legal type, however 689/// the operation it performs is not legal and is an operation that we have 690/// no way of lowering. "Unroll" the vector, splitting out the scalars and 691/// operating on each element individually. 692SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { 693 MVT::ValueType VT = Op.getValueType(); 694 assert(isTypeLegal(VT) && 695 "Caller should expand or promote operands that are not legal!"); 696 assert(Op.Val->getNumValues() == 1 && 697 "Can't unroll a vector with multiple results!"); 698 unsigned NE = MVT::getVectorNumElements(VT); 699 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 700 701 SmallVector<SDOperand, 8> Scalars; 702 SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); 703 for (unsigned i = 0; i != NE; ++i) { 704 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 705 SDOperand Operand = Op.getOperand(j); 706 MVT::ValueType OperandVT = Operand.getValueType(); 707 if (MVT::isVector(OperandVT)) { 708 // A vector operand; extract a single element. 709 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT); 710 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 711 OperandEltVT, 712 Operand, 713 DAG.getConstant(i, MVT::i32)); 714 } else { 715 // A scalar operand; just use it as is. 716 Operands[j] = Operand; 717 } 718 } 719 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 720 &Operands[0], Operands.size())); 721 } 722 723 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 724} 725 726/// LegalizeOp - We know that the specified value has a legal type, and 727/// that its operands are legal. Now ensure that the operation itself 728/// is legal, recursively ensuring that the operands' operations remain 729/// legal. 730SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 731 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 732 return Op; 733 734 assert(isTypeLegal(Op.getValueType()) && 735 "Caller should expand or promote operands that are not legal!"); 736 SDNode *Node = Op.Val; 737 738 // If this operation defines any values that cannot be represented in a 739 // register on this target, make sure to expand or promote them. 740 if (Node->getNumValues() > 1) { 741 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 742 if (getTypeAction(Node->getValueType(i)) != Legal) { 743 HandleOp(Op.getValue(i)); 744 assert(LegalizedNodes.count(Op) && 745 "Handling didn't add legal operands!"); 746 return LegalizedNodes[Op]; 747 } 748 } 749 750 // Note that LegalizeOp may be reentered even from single-use nodes, which 751 // means that we always must cache transformed nodes. 752 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 753 if (I != LegalizedNodes.end()) return I->second; 754 755 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 756 SDOperand Result = Op; 757 bool isCustom = false; 758 759 switch (Node->getOpcode()) { 760 case ISD::FrameIndex: 761 case ISD::EntryToken: 762 case ISD::Register: 763 case ISD::BasicBlock: 764 case ISD::TargetFrameIndex: 765 case ISD::TargetJumpTable: 766 case ISD::TargetConstant: 767 case ISD::TargetConstantFP: 768 case ISD::TargetConstantPool: 769 case ISD::TargetGlobalAddress: 770 case ISD::TargetGlobalTLSAddress: 771 case ISD::TargetExternalSymbol: 772 case ISD::VALUETYPE: 773 case ISD::SRCVALUE: 774 case ISD::STRING: 775 case ISD::CONDCODE: 776 // Primitives must all be legal. 777 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 778 "This must be legal!"); 779 break; 780 default: 781 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 782 // If this is a target node, legalize it by legalizing the operands then 783 // passing it through. 784 SmallVector<SDOperand, 8> Ops; 785 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 786 Ops.push_back(LegalizeOp(Node->getOperand(i))); 787 788 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 789 790 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 791 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 792 return Result.getValue(Op.ResNo); 793 } 794 // Otherwise this is an unhandled builtin node. splat. 795#ifndef NDEBUG 796 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 797#endif 798 assert(0 && "Do not know how to legalize this operator!"); 799 abort(); 800 case ISD::GLOBAL_OFFSET_TABLE: 801 case ISD::GlobalAddress: 802 case ISD::GlobalTLSAddress: 803 case ISD::ExternalSymbol: 804 case ISD::ConstantPool: 805 case ISD::JumpTable: // Nothing to do. 806 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 807 default: assert(0 && "This action is not supported yet!"); 808 case TargetLowering::Custom: 809 Tmp1 = TLI.LowerOperation(Op, DAG); 810 if (Tmp1.Val) Result = Tmp1; 811 // FALLTHROUGH if the target doesn't want to lower this op after all. 812 case TargetLowering::Legal: 813 break; 814 } 815 break; 816 case ISD::FRAMEADDR: 817 case ISD::RETURNADDR: 818 // The only option for these nodes is to custom lower them. If the target 819 // does not custom lower them, then return zero. 820 Tmp1 = TLI.LowerOperation(Op, DAG); 821 if (Tmp1.Val) 822 Result = Tmp1; 823 else 824 Result = DAG.getConstant(0, TLI.getPointerTy()); 825 break; 826 case ISD::FRAME_TO_ARGS_OFFSET: { 827 MVT::ValueType VT = Node->getValueType(0); 828 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 829 default: assert(0 && "This action is not supported yet!"); 830 case TargetLowering::Custom: 831 Result = TLI.LowerOperation(Op, DAG); 832 if (Result.Val) break; 833 // Fall Thru 834 case TargetLowering::Legal: 835 Result = DAG.getConstant(0, VT); 836 break; 837 } 838 } 839 break; 840 case ISD::EXCEPTIONADDR: { 841 Tmp1 = LegalizeOp(Node->getOperand(0)); 842 MVT::ValueType VT = Node->getValueType(0); 843 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 844 default: assert(0 && "This action is not supported yet!"); 845 case TargetLowering::Expand: { 846 unsigned Reg = TLI.getExceptionAddressRegister(); 847 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo); 848 } 849 break; 850 case TargetLowering::Custom: 851 Result = TLI.LowerOperation(Op, DAG); 852 if (Result.Val) break; 853 // Fall Thru 854 case TargetLowering::Legal: { 855 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 856 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 857 Ops, 2).getValue(Op.ResNo); 858 break; 859 } 860 } 861 } 862 break; 863 case ISD::EHSELECTION: { 864 Tmp1 = LegalizeOp(Node->getOperand(0)); 865 Tmp2 = LegalizeOp(Node->getOperand(1)); 866 MVT::ValueType VT = Node->getValueType(0); 867 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 868 default: assert(0 && "This action is not supported yet!"); 869 case TargetLowering::Expand: { 870 unsigned Reg = TLI.getExceptionSelectorRegister(); 871 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo); 872 } 873 break; 874 case TargetLowering::Custom: 875 Result = TLI.LowerOperation(Op, DAG); 876 if (Result.Val) break; 877 // Fall Thru 878 case TargetLowering::Legal: { 879 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 880 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 881 Ops, 2).getValue(Op.ResNo); 882 break; 883 } 884 } 885 } 886 break; 887 case ISD::EH_RETURN: { 888 MVT::ValueType VT = Node->getValueType(0); 889 // The only "good" option for this node is to custom lower it. 890 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 891 default: assert(0 && "This action is not supported at all!"); 892 case TargetLowering::Custom: 893 Result = TLI.LowerOperation(Op, DAG); 894 if (Result.Val) break; 895 // Fall Thru 896 case TargetLowering::Legal: 897 // Target does not know, how to lower this, lower to noop 898 Result = LegalizeOp(Node->getOperand(0)); 899 break; 900 } 901 } 902 break; 903 case ISD::AssertSext: 904 case ISD::AssertZext: 905 Tmp1 = LegalizeOp(Node->getOperand(0)); 906 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 907 break; 908 case ISD::MERGE_VALUES: 909 // Legalize eliminates MERGE_VALUES nodes. 910 Result = Node->getOperand(Op.ResNo); 911 break; 912 case ISD::CopyFromReg: 913 Tmp1 = LegalizeOp(Node->getOperand(0)); 914 Result = Op.getValue(0); 915 if (Node->getNumValues() == 2) { 916 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 917 } else { 918 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 919 if (Node->getNumOperands() == 3) { 920 Tmp2 = LegalizeOp(Node->getOperand(2)); 921 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 922 } else { 923 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 924 } 925 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 926 } 927 // Since CopyFromReg produces two values, make sure to remember that we 928 // legalized both of them. 929 AddLegalizedOperand(Op.getValue(0), Result); 930 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 931 return Result.getValue(Op.ResNo); 932 case ISD::UNDEF: { 933 MVT::ValueType VT = Op.getValueType(); 934 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 935 default: assert(0 && "This action is not supported yet!"); 936 case TargetLowering::Expand: 937 if (MVT::isInteger(VT)) 938 Result = DAG.getConstant(0, VT); 939 else if (MVT::isFloatingPoint(VT)) 940 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)), 941 VT); 942 else 943 assert(0 && "Unknown value type!"); 944 break; 945 case TargetLowering::Legal: 946 break; 947 } 948 break; 949 } 950 951 case ISD::INTRINSIC_W_CHAIN: 952 case ISD::INTRINSIC_WO_CHAIN: 953 case ISD::INTRINSIC_VOID: { 954 SmallVector<SDOperand, 8> Ops; 955 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 956 Ops.push_back(LegalizeOp(Node->getOperand(i))); 957 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 958 959 // Allow the target to custom lower its intrinsics if it wants to. 960 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 961 TargetLowering::Custom) { 962 Tmp3 = TLI.LowerOperation(Result, DAG); 963 if (Tmp3.Val) Result = Tmp3; 964 } 965 966 if (Result.Val->getNumValues() == 1) break; 967 968 // Must have return value and chain result. 969 assert(Result.Val->getNumValues() == 2 && 970 "Cannot return more than two values!"); 971 972 // Since loads produce two values, make sure to remember that we 973 // legalized both of them. 974 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 975 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 976 return Result.getValue(Op.ResNo); 977 } 978 979 case ISD::LOCATION: 980 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 981 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 982 983 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 984 case TargetLowering::Promote: 985 default: assert(0 && "This action is not supported yet!"); 986 case TargetLowering::Expand: { 987 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 988 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 989 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 990 991 if (MMI && (useDEBUG_LOC || useLABEL)) { 992 const std::string &FName = 993 cast<StringSDNode>(Node->getOperand(3))->getValue(); 994 const std::string &DirName = 995 cast<StringSDNode>(Node->getOperand(4))->getValue(); 996 unsigned SrcFile = MMI->RecordSource(DirName, FName); 997 998 SmallVector<SDOperand, 8> Ops; 999 Ops.push_back(Tmp1); // chain 1000 SDOperand LineOp = Node->getOperand(1); 1001 SDOperand ColOp = Node->getOperand(2); 1002 1003 if (useDEBUG_LOC) { 1004 Ops.push_back(LineOp); // line # 1005 Ops.push_back(ColOp); // col # 1006 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 1007 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 1008 } else { 1009 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 1010 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 1011 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile); 1012 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 1013 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size()); 1014 } 1015 } else { 1016 Result = Tmp1; // chain 1017 } 1018 break; 1019 } 1020 case TargetLowering::Legal: 1021 if (Tmp1 != Node->getOperand(0) || 1022 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 1023 SmallVector<SDOperand, 8> Ops; 1024 Ops.push_back(Tmp1); 1025 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 1026 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1027 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1028 } else { 1029 // Otherwise promote them. 1030 Ops.push_back(PromoteOp(Node->getOperand(1))); 1031 Ops.push_back(PromoteOp(Node->getOperand(2))); 1032 } 1033 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1034 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1035 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1036 } 1037 break; 1038 } 1039 break; 1040 1041 case ISD::DEBUG_LOC: 1042 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1043 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1044 default: assert(0 && "This action is not supported yet!"); 1045 case TargetLowering::Legal: 1046 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1047 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1048 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1049 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1050 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1051 break; 1052 } 1053 break; 1054 1055 case ISD::LABEL: 1056 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!"); 1057 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 1058 default: assert(0 && "This action is not supported yet!"); 1059 case TargetLowering::Legal: 1060 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1061 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 1062 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1063 break; 1064 case TargetLowering::Expand: 1065 Result = LegalizeOp(Node->getOperand(0)); 1066 break; 1067 } 1068 break; 1069 1070 case ISD::Constant: { 1071 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1072 unsigned opAction = 1073 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1074 1075 // We know we don't need to expand constants here, constants only have one 1076 // value and we check that it is fine above. 1077 1078 if (opAction == TargetLowering::Custom) { 1079 Tmp1 = TLI.LowerOperation(Result, DAG); 1080 if (Tmp1.Val) 1081 Result = Tmp1; 1082 } 1083 break; 1084 } 1085 case ISD::ConstantFP: { 1086 // Spill FP immediates to the constant pool if the target cannot directly 1087 // codegen them. Targets often have some immediate values that can be 1088 // efficiently generated into an FP register without a load. We explicitly 1089 // leave these constants as ConstantFP nodes for the target to deal with. 1090 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1091 1092 // Check to see if this FP immediate is already legal. 1093 bool isLegal = false; 1094 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1095 E = TLI.legal_fpimm_end(); I != E; ++I) 1096 if (CFP->isExactlyValue(*I)) { 1097 isLegal = true; 1098 break; 1099 } 1100 1101 // If this is a legal constant, turn it into a TargetConstantFP node. 1102 if (isLegal) { 1103 Result = DAG.getTargetConstantFP(CFP->getValueAPF(), 1104 CFP->getValueType(0)); 1105 break; 1106 } 1107 1108 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1109 default: assert(0 && "This action is not supported yet!"); 1110 case TargetLowering::Custom: 1111 Tmp3 = TLI.LowerOperation(Result, DAG); 1112 if (Tmp3.Val) { 1113 Result = Tmp3; 1114 break; 1115 } 1116 // FALLTHROUGH 1117 case TargetLowering::Expand: 1118 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1119 } 1120 break; 1121 } 1122 case ISD::TokenFactor: 1123 if (Node->getNumOperands() == 2) { 1124 Tmp1 = LegalizeOp(Node->getOperand(0)); 1125 Tmp2 = LegalizeOp(Node->getOperand(1)); 1126 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1127 } else if (Node->getNumOperands() == 3) { 1128 Tmp1 = LegalizeOp(Node->getOperand(0)); 1129 Tmp2 = LegalizeOp(Node->getOperand(1)); 1130 Tmp3 = LegalizeOp(Node->getOperand(2)); 1131 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1132 } else { 1133 SmallVector<SDOperand, 8> Ops; 1134 // Legalize the operands. 1135 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1136 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1137 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1138 } 1139 break; 1140 1141 case ISD::FORMAL_ARGUMENTS: 1142 case ISD::CALL: 1143 // The only option for this is to custom lower it. 1144 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1145 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1146 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() && 1147 "Lowering call/formal_arguments produced unexpected # results!"); 1148 1149 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1150 // remember that we legalized all of them, so it doesn't get relegalized. 1151 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1152 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1153 if (Op.ResNo == i) 1154 Tmp2 = Tmp1; 1155 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1156 } 1157 return Tmp2; 1158 case ISD::EXTRACT_SUBREG: { 1159 Tmp1 = LegalizeOp(Node->getOperand(0)); 1160 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1161 assert(idx && "Operand must be a constant"); 1162 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1163 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1164 } 1165 break; 1166 case ISD::INSERT_SUBREG: { 1167 Tmp1 = LegalizeOp(Node->getOperand(0)); 1168 Tmp2 = LegalizeOp(Node->getOperand(1)); 1169 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1170 assert(idx && "Operand must be a constant"); 1171 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1172 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1173 } 1174 break; 1175 case ISD::BUILD_VECTOR: 1176 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1177 default: assert(0 && "This action is not supported yet!"); 1178 case TargetLowering::Custom: 1179 Tmp3 = TLI.LowerOperation(Result, DAG); 1180 if (Tmp3.Val) { 1181 Result = Tmp3; 1182 break; 1183 } 1184 // FALLTHROUGH 1185 case TargetLowering::Expand: 1186 Result = ExpandBUILD_VECTOR(Result.Val); 1187 break; 1188 } 1189 break; 1190 case ISD::INSERT_VECTOR_ELT: 1191 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1192 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 1193 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1194 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1195 1196 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1197 Node->getValueType(0))) { 1198 default: assert(0 && "This action is not supported yet!"); 1199 case TargetLowering::Legal: 1200 break; 1201 case TargetLowering::Custom: 1202 Tmp3 = TLI.LowerOperation(Result, DAG); 1203 if (Tmp3.Val) { 1204 Result = Tmp3; 1205 break; 1206 } 1207 // FALLTHROUGH 1208 case TargetLowering::Expand: { 1209 // If the insert index is a constant, codegen this as a scalar_to_vector, 1210 // then a shuffle that inserts it into the right position in the vector. 1211 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1212 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1213 Tmp1.getValueType(), Tmp2); 1214 1215 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1216 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1217 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); 1218 1219 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 1220 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 1221 // the RHS. 1222 SmallVector<SDOperand, 8> ShufOps; 1223 for (unsigned i = 0; i != NumElts; ++i) { 1224 if (i != InsertPos->getValue()) 1225 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1226 else 1227 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1228 } 1229 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1230 &ShufOps[0], ShufOps.size()); 1231 1232 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1233 Tmp1, ScVec, ShufMask); 1234 Result = LegalizeOp(Result); 1235 break; 1236 } 1237 1238 // If the target doesn't support this, we have to spill the input vector 1239 // to a temporary stack slot, update the element, then reload it. This is 1240 // badness. We could also load the value into a vector register (either 1241 // with a "move to register" or "extload into register" instruction, then 1242 // permute it into place, if the idx is a constant and if the idx is 1243 // supported by the target. 1244 MVT::ValueType VT = Tmp1.getValueType(); 1245 MVT::ValueType EltVT = Tmp2.getValueType(); 1246 MVT::ValueType IdxVT = Tmp3.getValueType(); 1247 MVT::ValueType PtrVT = TLI.getPointerTy(); 1248 SDOperand StackPtr = CreateStackTemporary(VT); 1249 // Store the vector. 1250 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); 1251 1252 // Truncate or zero extend offset to target pointer type. 1253 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1254 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 1255 // Add the offset to the index. 1256 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 1257 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 1258 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 1259 // Store the scalar value. 1260 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); 1261 // Load the updated vector. 1262 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); 1263 break; 1264 } 1265 } 1266 break; 1267 case ISD::SCALAR_TO_VECTOR: 1268 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1269 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1270 break; 1271 } 1272 1273 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1274 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1275 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1276 Node->getValueType(0))) { 1277 default: assert(0 && "This action is not supported yet!"); 1278 case TargetLowering::Legal: 1279 break; 1280 case TargetLowering::Custom: 1281 Tmp3 = TLI.LowerOperation(Result, DAG); 1282 if (Tmp3.Val) { 1283 Result = Tmp3; 1284 break; 1285 } 1286 // FALLTHROUGH 1287 case TargetLowering::Expand: 1288 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1289 break; 1290 } 1291 break; 1292 case ISD::VECTOR_SHUFFLE: 1293 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1294 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1295 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1296 1297 // Allow targets to custom lower the SHUFFLEs they support. 1298 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1299 default: assert(0 && "Unknown operation action!"); 1300 case TargetLowering::Legal: 1301 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1302 "vector shuffle should not be created if not legal!"); 1303 break; 1304 case TargetLowering::Custom: 1305 Tmp3 = TLI.LowerOperation(Result, DAG); 1306 if (Tmp3.Val) { 1307 Result = Tmp3; 1308 break; 1309 } 1310 // FALLTHROUGH 1311 case TargetLowering::Expand: { 1312 MVT::ValueType VT = Node->getValueType(0); 1313 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1314 MVT::ValueType PtrVT = TLI.getPointerTy(); 1315 SDOperand Mask = Node->getOperand(2); 1316 unsigned NumElems = Mask.getNumOperands(); 1317 SmallVector<SDOperand,8> Ops; 1318 for (unsigned i = 0; i != NumElems; ++i) { 1319 SDOperand Arg = Mask.getOperand(i); 1320 if (Arg.getOpcode() == ISD::UNDEF) { 1321 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1322 } else { 1323 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1324 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1325 if (Idx < NumElems) 1326 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1327 DAG.getConstant(Idx, PtrVT))); 1328 else 1329 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1330 DAG.getConstant(Idx - NumElems, PtrVT))); 1331 } 1332 } 1333 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1334 break; 1335 } 1336 case TargetLowering::Promote: { 1337 // Change base type to a different vector type. 1338 MVT::ValueType OVT = Node->getValueType(0); 1339 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1340 1341 // Cast the two input vectors. 1342 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1343 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1344 1345 // Convert the shuffle mask to the right # elements. 1346 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1347 assert(Tmp3.Val && "Shuffle not legal?"); 1348 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1349 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1350 break; 1351 } 1352 } 1353 break; 1354 1355 case ISD::EXTRACT_VECTOR_ELT: 1356 Tmp1 = Node->getOperand(0); 1357 Tmp2 = LegalizeOp(Node->getOperand(1)); 1358 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1359 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1360 break; 1361 1362 case ISD::EXTRACT_SUBVECTOR: 1363 Tmp1 = Node->getOperand(0); 1364 Tmp2 = LegalizeOp(Node->getOperand(1)); 1365 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1366 Result = ExpandEXTRACT_SUBVECTOR(Result); 1367 break; 1368 1369 case ISD::CALLSEQ_START: { 1370 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1371 1372 // Recursively Legalize all of the inputs of the call end that do not lead 1373 // to this call start. This ensures that any libcalls that need be inserted 1374 // are inserted *before* the CALLSEQ_START. 1375 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1376 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1377 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1378 NodesLeadingTo); 1379 } 1380 1381 // Now that we legalized all of the inputs (which may have inserted 1382 // libcalls) create the new CALLSEQ_START node. 1383 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1384 1385 // Merge in the last call, to ensure that this call start after the last 1386 // call ended. 1387 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1388 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1389 Tmp1 = LegalizeOp(Tmp1); 1390 } 1391 1392 // Do not try to legalize the target-specific arguments (#1+). 1393 if (Tmp1 != Node->getOperand(0)) { 1394 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1395 Ops[0] = Tmp1; 1396 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1397 } 1398 1399 // Remember that the CALLSEQ_START is legalized. 1400 AddLegalizedOperand(Op.getValue(0), Result); 1401 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1402 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1403 1404 // Now that the callseq_start and all of the non-call nodes above this call 1405 // sequence have been legalized, legalize the call itself. During this 1406 // process, no libcalls can/will be inserted, guaranteeing that no calls 1407 // can overlap. 1408 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1409 SDOperand InCallSEQ = LastCALLSEQ_END; 1410 // Note that we are selecting this call! 1411 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1412 IsLegalizingCall = true; 1413 1414 // Legalize the call, starting from the CALLSEQ_END. 1415 LegalizeOp(LastCALLSEQ_END); 1416 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1417 return Result; 1418 } 1419 case ISD::CALLSEQ_END: 1420 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1421 // will cause this node to be legalized as well as handling libcalls right. 1422 if (LastCALLSEQ_END.Val != Node) { 1423 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1424 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1425 assert(I != LegalizedNodes.end() && 1426 "Legalizing the call start should have legalized this node!"); 1427 return I->second; 1428 } 1429 1430 // Otherwise, the call start has been legalized and everything is going 1431 // according to plan. Just legalize ourselves normally here. 1432 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1433 // Do not try to legalize the target-specific arguments (#1+), except for 1434 // an optional flag input. 1435 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1436 if (Tmp1 != Node->getOperand(0)) { 1437 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1438 Ops[0] = Tmp1; 1439 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1440 } 1441 } else { 1442 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1443 if (Tmp1 != Node->getOperand(0) || 1444 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1445 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1446 Ops[0] = Tmp1; 1447 Ops.back() = Tmp2; 1448 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1449 } 1450 } 1451 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1452 // This finishes up call legalization. 1453 IsLegalizingCall = false; 1454 1455 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1456 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1457 if (Node->getNumValues() == 2) 1458 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1459 return Result.getValue(Op.ResNo); 1460 case ISD::DYNAMIC_STACKALLOC: { 1461 MVT::ValueType VT = Node->getValueType(0); 1462 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1463 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1464 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1465 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1466 1467 Tmp1 = Result.getValue(0); 1468 Tmp2 = Result.getValue(1); 1469 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1470 default: assert(0 && "This action is not supported yet!"); 1471 case TargetLowering::Expand: { 1472 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1473 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1474 " not tell us which reg is the stack pointer!"); 1475 SDOperand Chain = Tmp1.getOperand(0); 1476 SDOperand Size = Tmp2.getOperand(1); 1477 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1478 Chain = SP.getValue(1); 1479 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1480 unsigned StackAlign = 1481 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1482 if (Align > StackAlign) 1483 SP = DAG.getNode(ISD::AND, VT, SP, 1484 DAG.getConstant(-(uint64_t)Align, VT)); 1485 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1486 Tmp2 = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1487 Tmp1 = LegalizeOp(Tmp1); 1488 Tmp2 = LegalizeOp(Tmp2); 1489 break; 1490 } 1491 case TargetLowering::Custom: 1492 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1493 if (Tmp3.Val) { 1494 Tmp1 = LegalizeOp(Tmp3); 1495 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1496 } 1497 break; 1498 case TargetLowering::Legal: 1499 break; 1500 } 1501 // Since this op produce two values, make sure to remember that we 1502 // legalized both of them. 1503 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1504 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1505 return Op.ResNo ? Tmp2 : Tmp1; 1506 } 1507 case ISD::INLINEASM: { 1508 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1509 bool Changed = false; 1510 // Legalize all of the operands of the inline asm, in case they are nodes 1511 // that need to be expanded or something. Note we skip the asm string and 1512 // all of the TargetConstant flags. 1513 SDOperand Op = LegalizeOp(Ops[0]); 1514 Changed = Op != Ops[0]; 1515 Ops[0] = Op; 1516 1517 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1518 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1519 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1520 for (++i; NumVals; ++i, --NumVals) { 1521 SDOperand Op = LegalizeOp(Ops[i]); 1522 if (Op != Ops[i]) { 1523 Changed = true; 1524 Ops[i] = Op; 1525 } 1526 } 1527 } 1528 1529 if (HasInFlag) { 1530 Op = LegalizeOp(Ops.back()); 1531 Changed |= Op != Ops.back(); 1532 Ops.back() = Op; 1533 } 1534 1535 if (Changed) 1536 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1537 1538 // INLINE asm returns a chain and flag, make sure to add both to the map. 1539 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1540 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1541 return Result.getValue(Op.ResNo); 1542 } 1543 case ISD::BR: 1544 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1545 // Ensure that libcalls are emitted before a branch. 1546 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1547 Tmp1 = LegalizeOp(Tmp1); 1548 LastCALLSEQ_END = DAG.getEntryNode(); 1549 1550 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1551 break; 1552 case ISD::BRIND: 1553 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1554 // Ensure that libcalls are emitted before a branch. 1555 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1556 Tmp1 = LegalizeOp(Tmp1); 1557 LastCALLSEQ_END = DAG.getEntryNode(); 1558 1559 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1560 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1561 case Legal: 1562 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1563 break; 1564 } 1565 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1566 break; 1567 case ISD::BR_JT: 1568 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1569 // Ensure that libcalls are emitted before a branch. 1570 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1571 Tmp1 = LegalizeOp(Tmp1); 1572 LastCALLSEQ_END = DAG.getEntryNode(); 1573 1574 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1575 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1576 1577 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1578 default: assert(0 && "This action is not supported yet!"); 1579 case TargetLowering::Legal: break; 1580 case TargetLowering::Custom: 1581 Tmp1 = TLI.LowerOperation(Result, DAG); 1582 if (Tmp1.Val) Result = Tmp1; 1583 break; 1584 case TargetLowering::Expand: { 1585 SDOperand Chain = Result.getOperand(0); 1586 SDOperand Table = Result.getOperand(1); 1587 SDOperand Index = Result.getOperand(2); 1588 1589 MVT::ValueType PTy = TLI.getPointerTy(); 1590 MachineFunction &MF = DAG.getMachineFunction(); 1591 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1592 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1593 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1594 1595 SDOperand LD; 1596 switch (EntrySize) { 1597 default: assert(0 && "Size of jump table not supported yet."); break; 1598 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; 1599 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; 1600 } 1601 1602 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1603 // For PIC, the sequence is: 1604 // BRIND(load(Jumptable + index) + RelocBase) 1605 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha 1606 SDOperand Reloc; 1607 if (TLI.usesGlobalOffsetTable()) 1608 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy); 1609 else 1610 Reloc = Table; 1611 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD; 1612 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc); 1613 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1614 } else { 1615 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD); 1616 } 1617 } 1618 } 1619 break; 1620 case ISD::BRCOND: 1621 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1622 // Ensure that libcalls are emitted before a return. 1623 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1624 Tmp1 = LegalizeOp(Tmp1); 1625 LastCALLSEQ_END = DAG.getEntryNode(); 1626 1627 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1628 case Expand: assert(0 && "It's impossible to expand bools"); 1629 case Legal: 1630 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1631 break; 1632 case Promote: 1633 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1634 1635 // The top bits of the promoted condition are not necessarily zero, ensure 1636 // that the value is properly zero extended. 1637 if (!DAG.MaskedValueIsZero(Tmp2, 1638 MVT::getIntVTBitMask(Tmp2.getValueType())^1)) 1639 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1640 break; 1641 } 1642 1643 // Basic block destination (Op#2) is always legal. 1644 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1645 1646 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1647 default: assert(0 && "This action is not supported yet!"); 1648 case TargetLowering::Legal: break; 1649 case TargetLowering::Custom: 1650 Tmp1 = TLI.LowerOperation(Result, DAG); 1651 if (Tmp1.Val) Result = Tmp1; 1652 break; 1653 case TargetLowering::Expand: 1654 // Expand brcond's setcc into its constituent parts and create a BR_CC 1655 // Node. 1656 if (Tmp2.getOpcode() == ISD::SETCC) { 1657 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1658 Tmp2.getOperand(0), Tmp2.getOperand(1), 1659 Node->getOperand(2)); 1660 } else { 1661 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1662 DAG.getCondCode(ISD::SETNE), Tmp2, 1663 DAG.getConstant(0, Tmp2.getValueType()), 1664 Node->getOperand(2)); 1665 } 1666 break; 1667 } 1668 break; 1669 case ISD::BR_CC: 1670 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1671 // Ensure that libcalls are emitted before a branch. 1672 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1673 Tmp1 = LegalizeOp(Tmp1); 1674 Tmp2 = Node->getOperand(2); // LHS 1675 Tmp3 = Node->getOperand(3); // RHS 1676 Tmp4 = Node->getOperand(1); // CC 1677 1678 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1679 LastCALLSEQ_END = DAG.getEntryNode(); 1680 1681 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1682 // the LHS is a legal SETCC itself. In this case, we need to compare 1683 // the result against zero to select between true and false values. 1684 if (Tmp3.Val == 0) { 1685 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1686 Tmp4 = DAG.getCondCode(ISD::SETNE); 1687 } 1688 1689 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1690 Node->getOperand(4)); 1691 1692 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1693 default: assert(0 && "Unexpected action for BR_CC!"); 1694 case TargetLowering::Legal: break; 1695 case TargetLowering::Custom: 1696 Tmp4 = TLI.LowerOperation(Result, DAG); 1697 if (Tmp4.Val) Result = Tmp4; 1698 break; 1699 } 1700 break; 1701 case ISD::LOAD: { 1702 LoadSDNode *LD = cast<LoadSDNode>(Node); 1703 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1704 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1705 1706 ISD::LoadExtType ExtType = LD->getExtensionType(); 1707 if (ExtType == ISD::NON_EXTLOAD) { 1708 MVT::ValueType VT = Node->getValueType(0); 1709 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1710 Tmp3 = Result.getValue(0); 1711 Tmp4 = Result.getValue(1); 1712 1713 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1714 default: assert(0 && "This action is not supported yet!"); 1715 case TargetLowering::Legal: 1716 // If this is an unaligned load and the target doesn't support it, 1717 // expand it. 1718 if (!TLI.allowsUnalignedMemoryAccesses()) { 1719 unsigned ABIAlignment = TLI.getTargetData()-> 1720 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1721 if (LD->getAlignment() < ABIAlignment){ 1722 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1723 TLI); 1724 Tmp3 = Result.getOperand(0); 1725 Tmp4 = Result.getOperand(1); 1726 Tmp3 = LegalizeOp(Tmp3); 1727 Tmp4 = LegalizeOp(Tmp4); 1728 } 1729 } 1730 break; 1731 case TargetLowering::Custom: 1732 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1733 if (Tmp1.Val) { 1734 Tmp3 = LegalizeOp(Tmp1); 1735 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1736 } 1737 break; 1738 case TargetLowering::Promote: { 1739 // Only promote a load of vector type to another. 1740 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1741 // Change base type to a different vector type. 1742 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1743 1744 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1745 LD->getSrcValueOffset(), 1746 LD->isVolatile(), LD->getAlignment()); 1747 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1748 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1749 break; 1750 } 1751 } 1752 // Since loads produce two values, make sure to remember that we 1753 // legalized both of them. 1754 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1755 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1756 return Op.ResNo ? Tmp4 : Tmp3; 1757 } else { 1758 MVT::ValueType SrcVT = LD->getLoadedVT(); 1759 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1760 default: assert(0 && "This action is not supported yet!"); 1761 case TargetLowering::Promote: 1762 assert(SrcVT == MVT::i1 && 1763 "Can only promote extending LOAD from i1 -> i8!"); 1764 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1765 LD->getSrcValue(), LD->getSrcValueOffset(), 1766 MVT::i8, LD->isVolatile(), LD->getAlignment()); 1767 Tmp1 = Result.getValue(0); 1768 Tmp2 = Result.getValue(1); 1769 break; 1770 case TargetLowering::Custom: 1771 isCustom = true; 1772 // FALLTHROUGH 1773 case TargetLowering::Legal: 1774 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1775 Tmp1 = Result.getValue(0); 1776 Tmp2 = Result.getValue(1); 1777 1778 if (isCustom) { 1779 Tmp3 = TLI.LowerOperation(Result, DAG); 1780 if (Tmp3.Val) { 1781 Tmp1 = LegalizeOp(Tmp3); 1782 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1783 } 1784 } else { 1785 // If this is an unaligned load and the target doesn't support it, 1786 // expand it. 1787 if (!TLI.allowsUnalignedMemoryAccesses()) { 1788 unsigned ABIAlignment = TLI.getTargetData()-> 1789 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1790 if (LD->getAlignment() < ABIAlignment){ 1791 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1792 TLI); 1793 Tmp1 = Result.getOperand(0); 1794 Tmp2 = Result.getOperand(1); 1795 Tmp1 = LegalizeOp(Tmp1); 1796 Tmp2 = LegalizeOp(Tmp2); 1797 } 1798 } 1799 } 1800 break; 1801 case TargetLowering::Expand: 1802 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1803 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1804 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 1805 LD->getSrcValueOffset(), 1806 LD->isVolatile(), LD->getAlignment()); 1807 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1808 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1809 Tmp2 = LegalizeOp(Load.getValue(1)); 1810 break; 1811 } 1812 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1813 // Turn the unsupported load into an EXTLOAD followed by an explicit 1814 // zero/sign extend inreg. 1815 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1816 Tmp1, Tmp2, LD->getSrcValue(), 1817 LD->getSrcValueOffset(), SrcVT, 1818 LD->isVolatile(), LD->getAlignment()); 1819 SDOperand ValRes; 1820 if (ExtType == ISD::SEXTLOAD) 1821 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1822 Result, DAG.getValueType(SrcVT)); 1823 else 1824 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1825 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1826 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1827 break; 1828 } 1829 // Since loads produce two values, make sure to remember that we legalized 1830 // both of them. 1831 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1832 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1833 return Op.ResNo ? Tmp2 : Tmp1; 1834 } 1835 } 1836 case ISD::EXTRACT_ELEMENT: { 1837 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1838 switch (getTypeAction(OpTy)) { 1839 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1840 case Legal: 1841 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1842 // 1 -> Hi 1843 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1844 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1845 TLI.getShiftAmountTy())); 1846 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1847 } else { 1848 // 0 -> Lo 1849 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1850 Node->getOperand(0)); 1851 } 1852 break; 1853 case Expand: 1854 // Get both the low and high parts. 1855 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1856 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1857 Result = Tmp2; // 1 -> Hi 1858 else 1859 Result = Tmp1; // 0 -> Lo 1860 break; 1861 } 1862 break; 1863 } 1864 1865 case ISD::CopyToReg: 1866 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1867 1868 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1869 "Register type must be legal!"); 1870 // Legalize the incoming value (must be a legal type). 1871 Tmp2 = LegalizeOp(Node->getOperand(2)); 1872 if (Node->getNumValues() == 1) { 1873 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1874 } else { 1875 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1876 if (Node->getNumOperands() == 4) { 1877 Tmp3 = LegalizeOp(Node->getOperand(3)); 1878 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1879 Tmp3); 1880 } else { 1881 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1882 } 1883 1884 // Since this produces two values, make sure to remember that we legalized 1885 // both of them. 1886 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1887 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1888 return Result; 1889 } 1890 break; 1891 1892 case ISD::RET: 1893 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1894 1895 // Ensure that libcalls are emitted before a return. 1896 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1897 Tmp1 = LegalizeOp(Tmp1); 1898 LastCALLSEQ_END = DAG.getEntryNode(); 1899 1900 switch (Node->getNumOperands()) { 1901 case 3: // ret val 1902 Tmp2 = Node->getOperand(1); 1903 Tmp3 = Node->getOperand(2); // Signness 1904 switch (getTypeAction(Tmp2.getValueType())) { 1905 case Legal: 1906 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1907 break; 1908 case Expand: 1909 if (!MVT::isVector(Tmp2.getValueType())) { 1910 SDOperand Lo, Hi; 1911 ExpandOp(Tmp2, Lo, Hi); 1912 1913 // Big endian systems want the hi reg first. 1914 if (!TLI.isLittleEndian()) 1915 std::swap(Lo, Hi); 1916 1917 if (Hi.Val) 1918 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1919 else 1920 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 1921 Result = LegalizeOp(Result); 1922 } else { 1923 SDNode *InVal = Tmp2.Val; 1924 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0)); 1925 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0)); 1926 1927 // Figure out if there is a simple type corresponding to this Vector 1928 // type. If so, convert to the vector type. 1929 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1930 if (TLI.isTypeLegal(TVT)) { 1931 // Turn this into a return of the vector type. 1932 Tmp2 = LegalizeOp(Tmp2); 1933 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1934 } else if (NumElems == 1) { 1935 // Turn this into a return of the scalar type. 1936 Tmp2 = ScalarizeVectorOp(Tmp2); 1937 Tmp2 = LegalizeOp(Tmp2); 1938 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1939 1940 // FIXME: Returns of gcc generic vectors smaller than a legal type 1941 // should be returned in integer registers! 1942 1943 // The scalarized value type may not be legal, e.g. it might require 1944 // promotion or expansion. Relegalize the return. 1945 Result = LegalizeOp(Result); 1946 } else { 1947 // FIXME: Returns of gcc generic vectors larger than a legal vector 1948 // type should be returned by reference! 1949 SDOperand Lo, Hi; 1950 SplitVectorOp(Tmp2, Lo, Hi); 1951 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1952 Result = LegalizeOp(Result); 1953 } 1954 } 1955 break; 1956 case Promote: 1957 Tmp2 = PromoteOp(Node->getOperand(1)); 1958 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1959 Result = LegalizeOp(Result); 1960 break; 1961 } 1962 break; 1963 case 1: // ret void 1964 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1965 break; 1966 default: { // ret <values> 1967 SmallVector<SDOperand, 8> NewValues; 1968 NewValues.push_back(Tmp1); 1969 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 1970 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1971 case Legal: 1972 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1973 NewValues.push_back(Node->getOperand(i+1)); 1974 break; 1975 case Expand: { 1976 SDOperand Lo, Hi; 1977 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && 1978 "FIXME: TODO: implement returning non-legal vector types!"); 1979 ExpandOp(Node->getOperand(i), Lo, Hi); 1980 NewValues.push_back(Lo); 1981 NewValues.push_back(Node->getOperand(i+1)); 1982 if (Hi.Val) { 1983 NewValues.push_back(Hi); 1984 NewValues.push_back(Node->getOperand(i+1)); 1985 } 1986 break; 1987 } 1988 case Promote: 1989 assert(0 && "Can't promote multiple return value yet!"); 1990 } 1991 1992 if (NewValues.size() == Node->getNumOperands()) 1993 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 1994 else 1995 Result = DAG.getNode(ISD::RET, MVT::Other, 1996 &NewValues[0], NewValues.size()); 1997 break; 1998 } 1999 } 2000 2001 if (Result.getOpcode() == ISD::RET) { 2002 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2003 default: assert(0 && "This action is not supported yet!"); 2004 case TargetLowering::Legal: break; 2005 case TargetLowering::Custom: 2006 Tmp1 = TLI.LowerOperation(Result, DAG); 2007 if (Tmp1.Val) Result = Tmp1; 2008 break; 2009 } 2010 } 2011 break; 2012 case ISD::STORE: { 2013 StoreSDNode *ST = cast<StoreSDNode>(Node); 2014 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2015 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2016 int SVOffset = ST->getSrcValueOffset(); 2017 unsigned Alignment = ST->getAlignment(); 2018 bool isVolatile = ST->isVolatile(); 2019 2020 if (!ST->isTruncatingStore()) { 2021 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2022 // FIXME: We shouldn't do this for TargetConstantFP's. 2023 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2024 // to phase ordering between legalized code and the dag combiner. This 2025 // probably means that we need to integrate dag combiner and legalizer 2026 // together. 2027 // We generally can't do this one for long doubles. 2028 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2029 if (CFP->getValueType(0) == MVT::f32 && 2030 getTypeAction(MVT::i32) == Legal) { 2031 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF(). 2032 convertToAPInt().getZExtValue(), 2033 MVT::i32); 2034 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2035 SVOffset, isVolatile, Alignment); 2036 break; 2037 } else if (CFP->getValueType(0) == MVT::f64) { 2038 // If this target supports 64-bit registers, do a single 64-bit store. 2039 if (getTypeAction(MVT::i64) == Legal) { 2040 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2041 getZExtValue(), MVT::i64); 2042 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2043 SVOffset, isVolatile, Alignment); 2044 break; 2045 } else if (getTypeAction(MVT::i32) == Legal) { 2046 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2047 // stores. If the target supports neither 32- nor 64-bits, this 2048 // xform is certainly not worth it. 2049 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue(); 2050 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32); 2051 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32); 2052 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 2053 2054 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2055 SVOffset, isVolatile, Alignment); 2056 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2057 getIntPtrConstant(4)); 2058 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2059 isVolatile, std::max(Alignment, 4U)); 2060 2061 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2062 break; 2063 } 2064 } 2065 } 2066 2067 switch (getTypeAction(ST->getStoredVT())) { 2068 case Legal: { 2069 Tmp3 = LegalizeOp(ST->getValue()); 2070 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2071 ST->getOffset()); 2072 2073 MVT::ValueType VT = Tmp3.getValueType(); 2074 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2075 default: assert(0 && "This action is not supported yet!"); 2076 case TargetLowering::Legal: 2077 // If this is an unaligned store and the target doesn't support it, 2078 // expand it. 2079 if (!TLI.allowsUnalignedMemoryAccesses()) { 2080 unsigned ABIAlignment = TLI.getTargetData()-> 2081 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2082 if (ST->getAlignment() < ABIAlignment) 2083 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2084 TLI); 2085 } 2086 break; 2087 case TargetLowering::Custom: 2088 Tmp1 = TLI.LowerOperation(Result, DAG); 2089 if (Tmp1.Val) Result = Tmp1; 2090 break; 2091 case TargetLowering::Promote: 2092 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 2093 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2094 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2095 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2096 ST->getSrcValue(), SVOffset, isVolatile, 2097 Alignment); 2098 break; 2099 } 2100 break; 2101 } 2102 case Promote: 2103 // Truncate the value and store the result. 2104 Tmp3 = PromoteOp(ST->getValue()); 2105 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2106 SVOffset, ST->getStoredVT(), 2107 isVolatile, Alignment); 2108 break; 2109 2110 case Expand: 2111 unsigned IncrementSize = 0; 2112 SDOperand Lo, Hi; 2113 2114 // If this is a vector type, then we have to calculate the increment as 2115 // the product of the element size in bytes, and the number of elements 2116 // in the high half of the vector. 2117 if (MVT::isVector(ST->getValue().getValueType())) { 2118 SDNode *InVal = ST->getValue().Val; 2119 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0)); 2120 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0)); 2121 2122 // Figure out if there is a simple type corresponding to this Vector 2123 // type. If so, convert to the vector type. 2124 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2125 if (TLI.isTypeLegal(TVT)) { 2126 // Turn this into a normal store of the vector type. 2127 Tmp3 = LegalizeOp(Node->getOperand(1)); 2128 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2129 SVOffset, isVolatile, Alignment); 2130 Result = LegalizeOp(Result); 2131 break; 2132 } else if (NumElems == 1) { 2133 // Turn this into a normal store of the scalar type. 2134 Tmp3 = ScalarizeVectorOp(Node->getOperand(1)); 2135 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2136 SVOffset, isVolatile, Alignment); 2137 // The scalarized value type may not be legal, e.g. it might require 2138 // promotion or expansion. Relegalize the scalar store. 2139 Result = LegalizeOp(Result); 2140 break; 2141 } else { 2142 SplitVectorOp(Node->getOperand(1), Lo, Hi); 2143 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; 2144 } 2145 } else { 2146 ExpandOp(Node->getOperand(1), Lo, Hi); 2147 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 2148 2149 if (!TLI.isLittleEndian()) 2150 std::swap(Lo, Hi); 2151 } 2152 2153 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2154 SVOffset, isVolatile, Alignment); 2155 2156 if (Hi.Val == NULL) { 2157 // Must be int <-> float one-to-one expansion. 2158 Result = Lo; 2159 break; 2160 } 2161 2162 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2163 getIntPtrConstant(IncrementSize)); 2164 assert(isTypeLegal(Tmp2.getValueType()) && 2165 "Pointers must be legal!"); 2166 SVOffset += IncrementSize; 2167 if (Alignment > IncrementSize) 2168 Alignment = IncrementSize; 2169 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2170 SVOffset, isVolatile, Alignment); 2171 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2172 break; 2173 } 2174 } else { 2175 // Truncating store 2176 assert(isTypeLegal(ST->getValue().getValueType()) && 2177 "Cannot handle illegal TRUNCSTORE yet!"); 2178 Tmp3 = LegalizeOp(ST->getValue()); 2179 2180 // The only promote case we handle is TRUNCSTORE:i1 X into 2181 // -> TRUNCSTORE:i8 (and X, 1) 2182 if (ST->getStoredVT() == MVT::i1 && 2183 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) { 2184 // Promote the bool to a mask then store. 2185 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3, 2186 DAG.getConstant(1, Tmp3.getValueType())); 2187 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2188 SVOffset, MVT::i8, 2189 isVolatile, Alignment); 2190 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2191 Tmp2 != ST->getBasePtr()) { 2192 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2193 ST->getOffset()); 2194 } 2195 2196 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT(); 2197 switch (TLI.getStoreXAction(StVT)) { 2198 default: assert(0 && "This action is not supported yet!"); 2199 case TargetLowering::Legal: 2200 // If this is an unaligned store and the target doesn't support it, 2201 // expand it. 2202 if (!TLI.allowsUnalignedMemoryAccesses()) { 2203 unsigned ABIAlignment = TLI.getTargetData()-> 2204 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2205 if (ST->getAlignment() < ABIAlignment) 2206 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2207 TLI); 2208 } 2209 break; 2210 case TargetLowering::Custom: 2211 Tmp1 = TLI.LowerOperation(Result, DAG); 2212 if (Tmp1.Val) Result = Tmp1; 2213 break; 2214 } 2215 } 2216 break; 2217 } 2218 case ISD::PCMARKER: 2219 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2220 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2221 break; 2222 case ISD::STACKSAVE: 2223 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2224 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2225 Tmp1 = Result.getValue(0); 2226 Tmp2 = Result.getValue(1); 2227 2228 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2229 default: assert(0 && "This action is not supported yet!"); 2230 case TargetLowering::Legal: break; 2231 case TargetLowering::Custom: 2232 Tmp3 = TLI.LowerOperation(Result, DAG); 2233 if (Tmp3.Val) { 2234 Tmp1 = LegalizeOp(Tmp3); 2235 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2236 } 2237 break; 2238 case TargetLowering::Expand: 2239 // Expand to CopyFromReg if the target set 2240 // StackPointerRegisterToSaveRestore. 2241 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2242 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2243 Node->getValueType(0)); 2244 Tmp2 = Tmp1.getValue(1); 2245 } else { 2246 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2247 Tmp2 = Node->getOperand(0); 2248 } 2249 break; 2250 } 2251 2252 // Since stacksave produce two values, make sure to remember that we 2253 // legalized both of them. 2254 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2255 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2256 return Op.ResNo ? Tmp2 : Tmp1; 2257 2258 case ISD::STACKRESTORE: 2259 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2260 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2261 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2262 2263 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2264 default: assert(0 && "This action is not supported yet!"); 2265 case TargetLowering::Legal: break; 2266 case TargetLowering::Custom: 2267 Tmp1 = TLI.LowerOperation(Result, DAG); 2268 if (Tmp1.Val) Result = Tmp1; 2269 break; 2270 case TargetLowering::Expand: 2271 // Expand to CopyToReg if the target set 2272 // StackPointerRegisterToSaveRestore. 2273 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2274 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2275 } else { 2276 Result = Tmp1; 2277 } 2278 break; 2279 } 2280 break; 2281 2282 case ISD::READCYCLECOUNTER: 2283 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2284 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2285 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2286 Node->getValueType(0))) { 2287 default: assert(0 && "This action is not supported yet!"); 2288 case TargetLowering::Legal: 2289 Tmp1 = Result.getValue(0); 2290 Tmp2 = Result.getValue(1); 2291 break; 2292 case TargetLowering::Custom: 2293 Result = TLI.LowerOperation(Result, DAG); 2294 Tmp1 = LegalizeOp(Result.getValue(0)); 2295 Tmp2 = LegalizeOp(Result.getValue(1)); 2296 break; 2297 } 2298 2299 // Since rdcc produce two values, make sure to remember that we legalized 2300 // both of them. 2301 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2302 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2303 return Result; 2304 2305 case ISD::SELECT: 2306 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2307 case Expand: assert(0 && "It's impossible to expand bools"); 2308 case Legal: 2309 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2310 break; 2311 case Promote: 2312 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2313 // Make sure the condition is either zero or one. 2314 if (!DAG.MaskedValueIsZero(Tmp1, 2315 MVT::getIntVTBitMask(Tmp1.getValueType())^1)) 2316 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2317 break; 2318 } 2319 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2320 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2321 2322 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2323 2324 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2325 default: assert(0 && "This action is not supported yet!"); 2326 case TargetLowering::Legal: break; 2327 case TargetLowering::Custom: { 2328 Tmp1 = TLI.LowerOperation(Result, DAG); 2329 if (Tmp1.Val) Result = Tmp1; 2330 break; 2331 } 2332 case TargetLowering::Expand: 2333 if (Tmp1.getOpcode() == ISD::SETCC) { 2334 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2335 Tmp2, Tmp3, 2336 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2337 } else { 2338 Result = DAG.getSelectCC(Tmp1, 2339 DAG.getConstant(0, Tmp1.getValueType()), 2340 Tmp2, Tmp3, ISD::SETNE); 2341 } 2342 break; 2343 case TargetLowering::Promote: { 2344 MVT::ValueType NVT = 2345 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2346 unsigned ExtOp, TruncOp; 2347 if (MVT::isVector(Tmp2.getValueType())) { 2348 ExtOp = ISD::BIT_CONVERT; 2349 TruncOp = ISD::BIT_CONVERT; 2350 } else if (MVT::isInteger(Tmp2.getValueType())) { 2351 ExtOp = ISD::ANY_EXTEND; 2352 TruncOp = ISD::TRUNCATE; 2353 } else { 2354 ExtOp = ISD::FP_EXTEND; 2355 TruncOp = ISD::FP_ROUND; 2356 } 2357 // Promote each of the values to the new type. 2358 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2359 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2360 // Perform the larger operation, then round down. 2361 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2362 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2363 break; 2364 } 2365 } 2366 break; 2367 case ISD::SELECT_CC: { 2368 Tmp1 = Node->getOperand(0); // LHS 2369 Tmp2 = Node->getOperand(1); // RHS 2370 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2371 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2372 SDOperand CC = Node->getOperand(4); 2373 2374 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2375 2376 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2377 // the LHS is a legal SETCC itself. In this case, we need to compare 2378 // the result against zero to select between true and false values. 2379 if (Tmp2.Val == 0) { 2380 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2381 CC = DAG.getCondCode(ISD::SETNE); 2382 } 2383 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2384 2385 // Everything is legal, see if we should expand this op or something. 2386 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2387 default: assert(0 && "This action is not supported yet!"); 2388 case TargetLowering::Legal: break; 2389 case TargetLowering::Custom: 2390 Tmp1 = TLI.LowerOperation(Result, DAG); 2391 if (Tmp1.Val) Result = Tmp1; 2392 break; 2393 } 2394 break; 2395 } 2396 case ISD::SETCC: 2397 Tmp1 = Node->getOperand(0); 2398 Tmp2 = Node->getOperand(1); 2399 Tmp3 = Node->getOperand(2); 2400 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2401 2402 // If we had to Expand the SetCC operands into a SELECT node, then it may 2403 // not always be possible to return a true LHS & RHS. In this case, just 2404 // return the value we legalized, returned in the LHS 2405 if (Tmp2.Val == 0) { 2406 Result = Tmp1; 2407 break; 2408 } 2409 2410 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2411 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2412 case TargetLowering::Custom: 2413 isCustom = true; 2414 // FALLTHROUGH. 2415 case TargetLowering::Legal: 2416 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2417 if (isCustom) { 2418 Tmp4 = TLI.LowerOperation(Result, DAG); 2419 if (Tmp4.Val) Result = Tmp4; 2420 } 2421 break; 2422 case TargetLowering::Promote: { 2423 // First step, figure out the appropriate operation to use. 2424 // Allow SETCC to not be supported for all legal data types 2425 // Mostly this targets FP 2426 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2427 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2428 2429 // Scan for the appropriate larger type to use. 2430 while (1) { 2431 NewInTy = (MVT::ValueType)(NewInTy+1); 2432 2433 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2434 "Fell off of the edge of the integer world"); 2435 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2436 "Fell off of the edge of the floating point world"); 2437 2438 // If the target supports SETCC of this type, use it. 2439 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2440 break; 2441 } 2442 if (MVT::isInteger(NewInTy)) 2443 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2444 else { 2445 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2446 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2447 } 2448 Tmp1 = LegalizeOp(Tmp1); 2449 Tmp2 = LegalizeOp(Tmp2); 2450 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2451 Result = LegalizeOp(Result); 2452 break; 2453 } 2454 case TargetLowering::Expand: 2455 // Expand a setcc node into a select_cc of the same condition, lhs, and 2456 // rhs that selects between const 1 (true) and const 0 (false). 2457 MVT::ValueType VT = Node->getValueType(0); 2458 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2459 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2460 Tmp3); 2461 break; 2462 } 2463 break; 2464 case ISD::MEMSET: 2465 case ISD::MEMCPY: 2466 case ISD::MEMMOVE: { 2467 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2468 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2469 2470 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2471 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2472 case Expand: assert(0 && "Cannot expand a byte!"); 2473 case Legal: 2474 Tmp3 = LegalizeOp(Node->getOperand(2)); 2475 break; 2476 case Promote: 2477 Tmp3 = PromoteOp(Node->getOperand(2)); 2478 break; 2479 } 2480 } else { 2481 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2482 } 2483 2484 SDOperand Tmp4; 2485 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2486 case Expand: { 2487 // Length is too big, just take the lo-part of the length. 2488 SDOperand HiPart; 2489 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2490 break; 2491 } 2492 case Legal: 2493 Tmp4 = LegalizeOp(Node->getOperand(3)); 2494 break; 2495 case Promote: 2496 Tmp4 = PromoteOp(Node->getOperand(3)); 2497 break; 2498 } 2499 2500 SDOperand Tmp5; 2501 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2502 case Expand: assert(0 && "Cannot expand this yet!"); 2503 case Legal: 2504 Tmp5 = LegalizeOp(Node->getOperand(4)); 2505 break; 2506 case Promote: 2507 Tmp5 = PromoteOp(Node->getOperand(4)); 2508 break; 2509 } 2510 2511 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2512 default: assert(0 && "This action not implemented for this operation!"); 2513 case TargetLowering::Custom: 2514 isCustom = true; 2515 // FALLTHROUGH 2516 case TargetLowering::Legal: 2517 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 2518 if (isCustom) { 2519 Tmp1 = TLI.LowerOperation(Result, DAG); 2520 if (Tmp1.Val) Result = Tmp1; 2521 } 2522 break; 2523 case TargetLowering::Expand: { 2524 // Otherwise, the target does not support this operation. Lower the 2525 // operation to an explicit libcall as appropriate. 2526 MVT::ValueType IntPtr = TLI.getPointerTy(); 2527 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2528 TargetLowering::ArgListTy Args; 2529 TargetLowering::ArgListEntry Entry; 2530 2531 const char *FnName = 0; 2532 if (Node->getOpcode() == ISD::MEMSET) { 2533 Entry.Node = Tmp2; Entry.Ty = IntPtrTy; 2534 Args.push_back(Entry); 2535 // Extend the (previously legalized) ubyte argument to be an int value 2536 // for the call. 2537 if (Tmp3.getValueType() > MVT::i32) 2538 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2539 else 2540 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2541 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 2542 Args.push_back(Entry); 2543 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false; 2544 Args.push_back(Entry); 2545 2546 FnName = "memset"; 2547 } else if (Node->getOpcode() == ISD::MEMCPY || 2548 Node->getOpcode() == ISD::MEMMOVE) { 2549 Entry.Ty = IntPtrTy; 2550 Entry.Node = Tmp2; Args.push_back(Entry); 2551 Entry.Node = Tmp3; Args.push_back(Entry); 2552 Entry.Node = Tmp4; Args.push_back(Entry); 2553 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2554 } else { 2555 assert(0 && "Unknown op!"); 2556 } 2557 2558 std::pair<SDOperand,SDOperand> CallResult = 2559 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 2560 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2561 Result = CallResult.second; 2562 break; 2563 } 2564 } 2565 break; 2566 } 2567 2568 case ISD::SHL_PARTS: 2569 case ISD::SRA_PARTS: 2570 case ISD::SRL_PARTS: { 2571 SmallVector<SDOperand, 8> Ops; 2572 bool Changed = false; 2573 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2574 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2575 Changed |= Ops.back() != Node->getOperand(i); 2576 } 2577 if (Changed) 2578 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2579 2580 switch (TLI.getOperationAction(Node->getOpcode(), 2581 Node->getValueType(0))) { 2582 default: assert(0 && "This action is not supported yet!"); 2583 case TargetLowering::Legal: break; 2584 case TargetLowering::Custom: 2585 Tmp1 = TLI.LowerOperation(Result, DAG); 2586 if (Tmp1.Val) { 2587 SDOperand Tmp2, RetVal(0, 0); 2588 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2589 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2590 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2591 if (i == Op.ResNo) 2592 RetVal = Tmp2; 2593 } 2594 assert(RetVal.Val && "Illegal result number"); 2595 return RetVal; 2596 } 2597 break; 2598 } 2599 2600 // Since these produce multiple values, make sure to remember that we 2601 // legalized all of them. 2602 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2603 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2604 return Result.getValue(Op.ResNo); 2605 } 2606 2607 // Binary operators 2608 case ISD::ADD: 2609 case ISD::SUB: 2610 case ISD::MUL: 2611 case ISD::MULHS: 2612 case ISD::MULHU: 2613 case ISD::UDIV: 2614 case ISD::SDIV: 2615 case ISD::AND: 2616 case ISD::OR: 2617 case ISD::XOR: 2618 case ISD::SHL: 2619 case ISD::SRL: 2620 case ISD::SRA: 2621 case ISD::FADD: 2622 case ISD::FSUB: 2623 case ISD::FMUL: 2624 case ISD::FDIV: 2625 case ISD::FPOW: 2626 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2627 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2628 case Expand: assert(0 && "Not possible"); 2629 case Legal: 2630 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2631 break; 2632 case Promote: 2633 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2634 break; 2635 } 2636 2637 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2638 2639 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2640 default: assert(0 && "BinOp legalize operation not supported"); 2641 case TargetLowering::Legal: break; 2642 case TargetLowering::Custom: 2643 Tmp1 = TLI.LowerOperation(Result, DAG); 2644 if (Tmp1.Val) Result = Tmp1; 2645 break; 2646 case TargetLowering::Expand: { 2647 MVT::ValueType VT = Op.getValueType(); 2648 2649 // See if multiply or divide can be lowered using two-result operations. 2650 SDVTList VTs = DAG.getVTList(VT, VT); 2651 if (Node->getOpcode() == ISD::MUL) { 2652 // We just need the low half of the multiply; try both the signed 2653 // and unsigned forms. If the target supports both SMUL_LOHI and 2654 // UMUL_LOHI, form a preference by checking which forms of plain 2655 // MULH it supports. 2656 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2657 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2658 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2659 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2660 unsigned OpToUse = 0; 2661 if (HasSMUL_LOHI && !HasMULHS) { 2662 OpToUse = ISD::SMUL_LOHI; 2663 } else if (HasUMUL_LOHI && !HasMULHU) { 2664 OpToUse = ISD::UMUL_LOHI; 2665 } else if (HasSMUL_LOHI) { 2666 OpToUse = ISD::SMUL_LOHI; 2667 } else if (HasUMUL_LOHI) { 2668 OpToUse = ISD::UMUL_LOHI; 2669 } 2670 if (OpToUse) { 2671 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 2672 break; 2673 } 2674 } 2675 if (Node->getOpcode() == ISD::MULHS && 2676 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 2677 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 2678 break; 2679 } 2680 if (Node->getOpcode() == ISD::MULHU && 2681 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 2682 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 2683 break; 2684 } 2685 if (Node->getOpcode() == ISD::SDIV && 2686 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 2687 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 2688 break; 2689 } 2690 if (Node->getOpcode() == ISD::UDIV && 2691 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 2692 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 2693 break; 2694 } 2695 2696 // Check to see if we have a libcall for this operator. 2697 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2698 bool isSigned = false; 2699 switch (Node->getOpcode()) { 2700 case ISD::UDIV: 2701 case ISD::SDIV: 2702 if (VT == MVT::i32) { 2703 LC = Node->getOpcode() == ISD::UDIV 2704 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 2705 isSigned = Node->getOpcode() == ISD::SDIV; 2706 } 2707 break; 2708 case ISD::FPOW: 2709 LC = VT == MVT::f32 ? RTLIB::POW_F32 : 2710 VT == MVT::f64 ? RTLIB::POW_F64 : 2711 VT == MVT::f80 ? RTLIB::POW_F80 : 2712 VT == MVT::ppcf128 ? RTLIB::POW_PPCF128 : 2713 RTLIB::UNKNOWN_LIBCALL; 2714 break; 2715 default: break; 2716 } 2717 if (LC != RTLIB::UNKNOWN_LIBCALL) { 2718 SDOperand Dummy; 2719 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2720 break; 2721 } 2722 2723 assert(MVT::isVector(Node->getValueType(0)) && 2724 "Cannot expand this binary operator!"); 2725 // Expand the operation into a bunch of nasty scalar code. 2726 Result = LegalizeOp(UnrollVectorOp(Op)); 2727 break; 2728 } 2729 case TargetLowering::Promote: { 2730 switch (Node->getOpcode()) { 2731 default: assert(0 && "Do not know how to promote this BinOp!"); 2732 case ISD::AND: 2733 case ISD::OR: 2734 case ISD::XOR: { 2735 MVT::ValueType OVT = Node->getValueType(0); 2736 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2737 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2738 // Bit convert each of the values to the new type. 2739 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2740 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2741 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2742 // Bit convert the result back the original type. 2743 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2744 break; 2745 } 2746 } 2747 } 2748 } 2749 break; 2750 2751 case ISD::SMUL_LOHI: 2752 case ISD::UMUL_LOHI: 2753 case ISD::SDIVREM: 2754 case ISD::UDIVREM: 2755 // These nodes will only be produced by target-specific lowering, so 2756 // they shouldn't be here if they aren't legal. 2757 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 2758 "This must be legal!"); 2759 2760 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2761 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2762 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2763 break; 2764 2765 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2766 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2767 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2768 case Expand: assert(0 && "Not possible"); 2769 case Legal: 2770 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2771 break; 2772 case Promote: 2773 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2774 break; 2775 } 2776 2777 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2778 2779 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2780 default: assert(0 && "Operation not supported"); 2781 case TargetLowering::Custom: 2782 Tmp1 = TLI.LowerOperation(Result, DAG); 2783 if (Tmp1.Val) Result = Tmp1; 2784 break; 2785 case TargetLowering::Legal: break; 2786 case TargetLowering::Expand: { 2787 // If this target supports fabs/fneg natively and select is cheap, 2788 // do this efficiently. 2789 if (!TLI.isSelectExpensive() && 2790 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 2791 TargetLowering::Legal && 2792 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 2793 TargetLowering::Legal) { 2794 // Get the sign bit of the RHS. 2795 MVT::ValueType IVT = 2796 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2797 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2798 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2799 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2800 // Get the absolute value of the result. 2801 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2802 // Select between the nabs and abs value based on the sign bit of 2803 // the input. 2804 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2805 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2806 AbsVal), 2807 AbsVal); 2808 Result = LegalizeOp(Result); 2809 break; 2810 } 2811 2812 // Otherwise, do bitwise ops! 2813 MVT::ValueType NVT = 2814 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 2815 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 2816 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 2817 Result = LegalizeOp(Result); 2818 break; 2819 } 2820 } 2821 break; 2822 2823 case ISD::ADDC: 2824 case ISD::SUBC: 2825 Tmp1 = LegalizeOp(Node->getOperand(0)); 2826 Tmp2 = LegalizeOp(Node->getOperand(1)); 2827 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2828 // Since this produces two values, make sure to remember that we legalized 2829 // both of them. 2830 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2831 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2832 return Result; 2833 2834 case ISD::ADDE: 2835 case ISD::SUBE: 2836 Tmp1 = LegalizeOp(Node->getOperand(0)); 2837 Tmp2 = LegalizeOp(Node->getOperand(1)); 2838 Tmp3 = LegalizeOp(Node->getOperand(2)); 2839 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2840 // Since this produces two values, make sure to remember that we legalized 2841 // both of them. 2842 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2843 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2844 return Result; 2845 2846 case ISD::BUILD_PAIR: { 2847 MVT::ValueType PairTy = Node->getValueType(0); 2848 // TODO: handle the case where the Lo and Hi operands are not of legal type 2849 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2850 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2851 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2852 case TargetLowering::Promote: 2853 case TargetLowering::Custom: 2854 assert(0 && "Cannot promote/custom this yet!"); 2855 case TargetLowering::Legal: 2856 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2857 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2858 break; 2859 case TargetLowering::Expand: 2860 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2861 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2862 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2863 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2864 TLI.getShiftAmountTy())); 2865 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2866 break; 2867 } 2868 break; 2869 } 2870 2871 case ISD::UREM: 2872 case ISD::SREM: 2873 case ISD::FREM: 2874 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2875 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2876 2877 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2878 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2879 case TargetLowering::Custom: 2880 isCustom = true; 2881 // FALLTHROUGH 2882 case TargetLowering::Legal: 2883 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2884 if (isCustom) { 2885 Tmp1 = TLI.LowerOperation(Result, DAG); 2886 if (Tmp1.Val) Result = Tmp1; 2887 } 2888 break; 2889 case TargetLowering::Expand: { 2890 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2891 bool isSigned = DivOpc == ISD::SDIV; 2892 MVT::ValueType VT = Node->getValueType(0); 2893 2894 // See if remainder can be lowered using two-result operations. 2895 SDVTList VTs = DAG.getVTList(VT, VT); 2896 if (Node->getOpcode() == ISD::SREM && 2897 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 2898 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 2899 break; 2900 } 2901 if (Node->getOpcode() == ISD::UREM && 2902 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 2903 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 2904 break; 2905 } 2906 2907 if (MVT::isInteger(VT)) { 2908 if (TLI.getOperationAction(DivOpc, VT) == 2909 TargetLowering::Legal) { 2910 // X % Y -> X-X/Y*Y 2911 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 2912 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2913 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2914 } else { 2915 assert(VT == MVT::i32 && 2916 "Cannot expand this binary operator!"); 2917 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 2918 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 2919 SDOperand Dummy; 2920 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2921 } 2922 } else { 2923 // Floating point mod -> fmod libcall. 2924 RTLIB::Libcall LC = VT == MVT::f32 2925 ? RTLIB::REM_F32 : RTLIB::REM_F64; 2926 SDOperand Dummy; 2927 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2928 false/*sign irrelevant*/, Dummy); 2929 } 2930 break; 2931 } 2932 } 2933 break; 2934 case ISD::VAARG: { 2935 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2936 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2937 2938 MVT::ValueType VT = Node->getValueType(0); 2939 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2940 default: assert(0 && "This action is not supported yet!"); 2941 case TargetLowering::Custom: 2942 isCustom = true; 2943 // FALLTHROUGH 2944 case TargetLowering::Legal: 2945 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2946 Result = Result.getValue(0); 2947 Tmp1 = Result.getValue(1); 2948 2949 if (isCustom) { 2950 Tmp2 = TLI.LowerOperation(Result, DAG); 2951 if (Tmp2.Val) { 2952 Result = LegalizeOp(Tmp2); 2953 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 2954 } 2955 } 2956 break; 2957 case TargetLowering::Expand: { 2958 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 2959 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2960 SV->getValue(), SV->getOffset()); 2961 // Increment the pointer, VAList, to the next vaarg 2962 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2963 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2964 TLI.getPointerTy())); 2965 // Store the incremented VAList to the legalized pointer 2966 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 2967 SV->getOffset()); 2968 // Load the actual argument out of the pointer VAList 2969 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 2970 Tmp1 = LegalizeOp(Result.getValue(1)); 2971 Result = LegalizeOp(Result); 2972 break; 2973 } 2974 } 2975 // Since VAARG produces two values, make sure to remember that we 2976 // legalized both of them. 2977 AddLegalizedOperand(SDOperand(Node, 0), Result); 2978 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 2979 return Op.ResNo ? Tmp1 : Result; 2980 } 2981 2982 case ISD::VACOPY: 2983 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2984 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 2985 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 2986 2987 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 2988 default: assert(0 && "This action is not supported yet!"); 2989 case TargetLowering::Custom: 2990 isCustom = true; 2991 // FALLTHROUGH 2992 case TargetLowering::Legal: 2993 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 2994 Node->getOperand(3), Node->getOperand(4)); 2995 if (isCustom) { 2996 Tmp1 = TLI.LowerOperation(Result, DAG); 2997 if (Tmp1.Val) Result = Tmp1; 2998 } 2999 break; 3000 case TargetLowering::Expand: 3001 // This defaults to loading a pointer from the input and storing it to the 3002 // output, returning the chain. 3003 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); 3004 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); 3005 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), 3006 SVD->getOffset()); 3007 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), 3008 SVS->getOffset()); 3009 break; 3010 } 3011 break; 3012 3013 case ISD::VAEND: 3014 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3015 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3016 3017 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3018 default: assert(0 && "This action is not supported yet!"); 3019 case TargetLowering::Custom: 3020 isCustom = true; 3021 // FALLTHROUGH 3022 case TargetLowering::Legal: 3023 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3024 if (isCustom) { 3025 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3026 if (Tmp1.Val) Result = Tmp1; 3027 } 3028 break; 3029 case TargetLowering::Expand: 3030 Result = Tmp1; // Default to a no-op, return the chain 3031 break; 3032 } 3033 break; 3034 3035 case ISD::VASTART: 3036 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3037 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3038 3039 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3040 3041 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3042 default: assert(0 && "This action is not supported yet!"); 3043 case TargetLowering::Legal: break; 3044 case TargetLowering::Custom: 3045 Tmp1 = TLI.LowerOperation(Result, DAG); 3046 if (Tmp1.Val) Result = Tmp1; 3047 break; 3048 } 3049 break; 3050 3051 case ISD::ROTL: 3052 case ISD::ROTR: 3053 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3054 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3055 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3056 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3057 default: 3058 assert(0 && "ROTL/ROTR legalize operation not supported"); 3059 break; 3060 case TargetLowering::Legal: 3061 break; 3062 case TargetLowering::Custom: 3063 Tmp1 = TLI.LowerOperation(Result, DAG); 3064 if (Tmp1.Val) Result = Tmp1; 3065 break; 3066 case TargetLowering::Promote: 3067 assert(0 && "Do not know how to promote ROTL/ROTR"); 3068 break; 3069 case TargetLowering::Expand: 3070 assert(0 && "Do not know how to expand ROTL/ROTR"); 3071 break; 3072 } 3073 break; 3074 3075 case ISD::BSWAP: 3076 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3077 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3078 case TargetLowering::Custom: 3079 assert(0 && "Cannot custom legalize this yet!"); 3080 case TargetLowering::Legal: 3081 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3082 break; 3083 case TargetLowering::Promote: { 3084 MVT::ValueType OVT = Tmp1.getValueType(); 3085 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3086 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); 3087 3088 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3089 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3090 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3091 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3092 break; 3093 } 3094 case TargetLowering::Expand: 3095 Result = ExpandBSWAP(Tmp1); 3096 break; 3097 } 3098 break; 3099 3100 case ISD::CTPOP: 3101 case ISD::CTTZ: 3102 case ISD::CTLZ: 3103 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3104 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3105 case TargetLowering::Custom: 3106 case TargetLowering::Legal: 3107 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3108 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3109 TargetLowering::Custom) { 3110 Tmp1 = TLI.LowerOperation(Result, DAG); 3111 if (Tmp1.Val) { 3112 Result = Tmp1; 3113 } 3114 } 3115 break; 3116 case TargetLowering::Promote: { 3117 MVT::ValueType OVT = Tmp1.getValueType(); 3118 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3119 3120 // Zero extend the argument. 3121 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3122 // Perform the larger operation, then subtract if needed. 3123 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3124 switch (Node->getOpcode()) { 3125 case ISD::CTPOP: 3126 Result = Tmp1; 3127 break; 3128 case ISD::CTTZ: 3129 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3130 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3131 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 3132 ISD::SETEQ); 3133 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3134 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); 3135 break; 3136 case ISD::CTLZ: 3137 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3138 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3139 DAG.getConstant(MVT::getSizeInBits(NVT) - 3140 MVT::getSizeInBits(OVT), NVT)); 3141 break; 3142 } 3143 break; 3144 } 3145 case TargetLowering::Expand: 3146 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3147 break; 3148 } 3149 break; 3150 3151 // Unary operators 3152 case ISD::FABS: 3153 case ISD::FNEG: 3154 case ISD::FSQRT: 3155 case ISD::FSIN: 3156 case ISD::FCOS: 3157 Tmp1 = LegalizeOp(Node->getOperand(0)); 3158 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3159 case TargetLowering::Promote: 3160 case TargetLowering::Custom: 3161 isCustom = true; 3162 // FALLTHROUGH 3163 case TargetLowering::Legal: 3164 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3165 if (isCustom) { 3166 Tmp1 = TLI.LowerOperation(Result, DAG); 3167 if (Tmp1.Val) Result = Tmp1; 3168 } 3169 break; 3170 case TargetLowering::Expand: 3171 switch (Node->getOpcode()) { 3172 default: assert(0 && "Unreachable!"); 3173 case ISD::FNEG: 3174 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3175 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3176 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3177 break; 3178 case ISD::FABS: { 3179 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3180 MVT::ValueType VT = Node->getValueType(0); 3181 Tmp2 = DAG.getConstantFP(0.0, VT); 3182 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 3183 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3184 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3185 break; 3186 } 3187 case ISD::FSQRT: 3188 case ISD::FSIN: 3189 case ISD::FCOS: { 3190 MVT::ValueType VT = Node->getValueType(0); 3191 3192 // Expand unsupported unary vector operators by unrolling them. 3193 if (MVT::isVector(VT)) { 3194 Result = LegalizeOp(UnrollVectorOp(Op)); 3195 break; 3196 } 3197 3198 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3199 switch(Node->getOpcode()) { 3200 case ISD::FSQRT: 3201 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : 3202 VT == MVT::f64 ? RTLIB::SQRT_F64 : 3203 VT == MVT::f80 ? RTLIB::SQRT_F80 : 3204 VT == MVT::ppcf128 ? RTLIB::SQRT_PPCF128 : 3205 RTLIB::UNKNOWN_LIBCALL; 3206 break; 3207 case ISD::FSIN: 3208 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 3209 break; 3210 case ISD::FCOS: 3211 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64; 3212 break; 3213 default: assert(0 && "Unreachable!"); 3214 } 3215 SDOperand Dummy; 3216 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3217 false/*sign irrelevant*/, Dummy); 3218 break; 3219 } 3220 } 3221 break; 3222 } 3223 break; 3224 case ISD::FPOWI: { 3225 MVT::ValueType VT = Node->getValueType(0); 3226 3227 // Expand unsupported unary vector operators by unrolling them. 3228 if (MVT::isVector(VT)) { 3229 Result = LegalizeOp(UnrollVectorOp(Op)); 3230 break; 3231 } 3232 3233 // We always lower FPOWI into a libcall. No target support for it yet. 3234 RTLIB::Libcall LC = 3235 VT == MVT::f32 ? RTLIB::POWI_F32 : 3236 VT == MVT::f64 ? RTLIB::POWI_F64 : 3237 VT == MVT::f80 ? RTLIB::POWI_F80 : 3238 VT == MVT::ppcf128 ? RTLIB::POWI_PPCF128 : 3239 RTLIB::UNKNOWN_LIBCALL; 3240 SDOperand Dummy; 3241 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3242 false/*sign irrelevant*/, Dummy); 3243 break; 3244 } 3245 case ISD::BIT_CONVERT: 3246 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3247 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3248 } else if (MVT::isVector(Op.getOperand(0).getValueType())) { 3249 // The input has to be a vector type, we have to either scalarize it, pack 3250 // it, or convert it based on whether the input vector type is legal. 3251 SDNode *InVal = Node->getOperand(0).Val; 3252 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0)); 3253 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0)); 3254 3255 // Figure out if there is a simple type corresponding to this Vector 3256 // type. If so, convert to the vector type. 3257 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3258 if (TLI.isTypeLegal(TVT)) { 3259 // Turn this into a bit convert of the vector input. 3260 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3261 LegalizeOp(Node->getOperand(0))); 3262 break; 3263 } else if (NumElems == 1) { 3264 // Turn this into a bit convert of the scalar input. 3265 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3266 ScalarizeVectorOp(Node->getOperand(0))); 3267 break; 3268 } else { 3269 // FIXME: UNIMP! Store then reload 3270 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3271 } 3272 } else { 3273 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3274 Node->getOperand(0).getValueType())) { 3275 default: assert(0 && "Unknown operation action!"); 3276 case TargetLowering::Expand: 3277 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3278 break; 3279 case TargetLowering::Legal: 3280 Tmp1 = LegalizeOp(Node->getOperand(0)); 3281 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3282 break; 3283 } 3284 } 3285 break; 3286 3287 // Conversion operators. The source and destination have different types. 3288 case ISD::SINT_TO_FP: 3289 case ISD::UINT_TO_FP: { 3290 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3291 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3292 case Legal: 3293 switch (TLI.getOperationAction(Node->getOpcode(), 3294 Node->getOperand(0).getValueType())) { 3295 default: assert(0 && "Unknown operation action!"); 3296 case TargetLowering::Custom: 3297 isCustom = true; 3298 // FALLTHROUGH 3299 case TargetLowering::Legal: 3300 Tmp1 = LegalizeOp(Node->getOperand(0)); 3301 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3302 if (isCustom) { 3303 Tmp1 = TLI.LowerOperation(Result, DAG); 3304 if (Tmp1.Val) Result = Tmp1; 3305 } 3306 break; 3307 case TargetLowering::Expand: 3308 Result = ExpandLegalINT_TO_FP(isSigned, 3309 LegalizeOp(Node->getOperand(0)), 3310 Node->getValueType(0)); 3311 break; 3312 case TargetLowering::Promote: 3313 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3314 Node->getValueType(0), 3315 isSigned); 3316 break; 3317 } 3318 break; 3319 case Expand: 3320 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3321 Node->getValueType(0), Node->getOperand(0)); 3322 break; 3323 case Promote: 3324 Tmp1 = PromoteOp(Node->getOperand(0)); 3325 if (isSigned) { 3326 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3327 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3328 } else { 3329 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3330 Node->getOperand(0).getValueType()); 3331 } 3332 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3333 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3334 break; 3335 } 3336 break; 3337 } 3338 case ISD::TRUNCATE: 3339 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3340 case Legal: 3341 Tmp1 = LegalizeOp(Node->getOperand(0)); 3342 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3343 break; 3344 case Expand: 3345 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3346 3347 // Since the result is legal, we should just be able to truncate the low 3348 // part of the source. 3349 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3350 break; 3351 case Promote: 3352 Result = PromoteOp(Node->getOperand(0)); 3353 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3354 break; 3355 } 3356 break; 3357 3358 case ISD::FP_TO_SINT: 3359 case ISD::FP_TO_UINT: 3360 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3361 case Legal: 3362 Tmp1 = LegalizeOp(Node->getOperand(0)); 3363 3364 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3365 default: assert(0 && "Unknown operation action!"); 3366 case TargetLowering::Custom: 3367 isCustom = true; 3368 // FALLTHROUGH 3369 case TargetLowering::Legal: 3370 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3371 if (isCustom) { 3372 Tmp1 = TLI.LowerOperation(Result, DAG); 3373 if (Tmp1.Val) Result = Tmp1; 3374 } 3375 break; 3376 case TargetLowering::Promote: 3377 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3378 Node->getOpcode() == ISD::FP_TO_SINT); 3379 break; 3380 case TargetLowering::Expand: 3381 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3382 SDOperand True, False; 3383 MVT::ValueType VT = Node->getOperand(0).getValueType(); 3384 MVT::ValueType NVT = Node->getValueType(0); 3385 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1; 3386 const uint64_t zero[] = {0, 0}; 3387 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero)); 3388 uint64_t x = 1ULL << ShiftAmt; 3389 (void)apf.convertFromZeroExtendedInteger 3390 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven); 3391 Tmp2 = DAG.getConstantFP(apf, VT); 3392 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 3393 Node->getOperand(0), Tmp2, ISD::SETLT); 3394 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3395 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3396 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3397 Tmp2)); 3398 False = DAG.getNode(ISD::XOR, NVT, False, 3399 DAG.getConstant(1ULL << ShiftAmt, NVT)); 3400 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3401 break; 3402 } else { 3403 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3404 } 3405 break; 3406 } 3407 break; 3408 case Expand: { 3409 MVT::ValueType VT = Op.getValueType(); 3410 MVT::ValueType OVT = Node->getOperand(0).getValueType(); 3411 // Convert ppcf128 to i32 3412 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3413 if (Node->getOpcode()==ISD::FP_TO_SINT) 3414 Result = DAG.getNode(ISD::FP_TO_SINT, VT, 3415 DAG.getNode(ISD::FP_ROUND, MVT::f64, 3416 (DAG.getNode(ISD::FP_ROUND_INREG, 3417 MVT::ppcf128, Node->getOperand(0), 3418 DAG.getValueType(MVT::f64))))); 3419 else { 3420 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3421 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3422 Tmp2 = DAG.getConstantFP(apf, OVT); 3423 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3424 // FIXME: generated code sucks. 3425 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3426 DAG.getNode(ISD::ADD, MVT::i32, 3427 DAG.getNode(ISD::FP_TO_SINT, VT, 3428 DAG.getNode(ISD::FSUB, OVT, 3429 Node->getOperand(0), Tmp2)), 3430 DAG.getConstant(0x80000000, MVT::i32)), 3431 DAG.getNode(ISD::FP_TO_SINT, VT, 3432 Node->getOperand(0)), 3433 DAG.getCondCode(ISD::SETGE)); 3434 } 3435 break; 3436 } 3437 // Convert f32 / f64 to i32 / i64. 3438 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3439 switch (Node->getOpcode()) { 3440 case ISD::FP_TO_SINT: { 3441 if (OVT == MVT::f32) 3442 LC = (VT == MVT::i32) 3443 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3444 else if (OVT == MVT::f64) 3445 LC = (VT == MVT::i32) 3446 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3447 else if (OVT == MVT::f80) { 3448 assert(VT == MVT::i64); 3449 LC = RTLIB::FPTOSINT_F80_I64; 3450 } 3451 else if (OVT == MVT::ppcf128) { 3452 assert(VT == MVT::i64); 3453 LC = RTLIB::FPTOSINT_PPCF128_I64; 3454 } 3455 break; 3456 } 3457 case ISD::FP_TO_UINT: { 3458 if (OVT == MVT::f32) 3459 LC = (VT == MVT::i32) 3460 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3461 else if (OVT == MVT::f64) 3462 LC = (VT == MVT::i32) 3463 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3464 else if (OVT == MVT::f80) { 3465 LC = (VT == MVT::i32) 3466 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64; 3467 } 3468 else if (OVT == MVT::ppcf128) { 3469 assert(VT == MVT::i64); 3470 LC = RTLIB::FPTOUINT_PPCF128_I64; 3471 } 3472 break; 3473 } 3474 default: assert(0 && "Unreachable!"); 3475 } 3476 SDOperand Dummy; 3477 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3478 false/*sign irrelevant*/, Dummy); 3479 break; 3480 } 3481 case Promote: 3482 Tmp1 = PromoteOp(Node->getOperand(0)); 3483 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3484 Result = LegalizeOp(Result); 3485 break; 3486 } 3487 break; 3488 3489 case ISD::FP_EXTEND: 3490 case ISD::FP_ROUND: { 3491 MVT::ValueType newVT = Op.getValueType(); 3492 MVT::ValueType oldVT = Op.getOperand(0).getValueType(); 3493 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) { 3494 if (Node->getOpcode() == ISD::FP_ROUND && oldVT == MVT::ppcf128) { 3495 SDOperand Lo, Hi; 3496 ExpandOp(Node->getOperand(0), Lo, Hi); 3497 if (newVT == MVT::f64) 3498 Result = Hi; 3499 else 3500 Result = DAG.getNode(ISD::FP_ROUND, newVT, Hi); 3501 break; 3502 } else { 3503 // The only other way we can lower this is to turn it into a STORE, 3504 // LOAD pair, targetting a temporary location (a stack slot). 3505 3506 // NOTE: there is a choice here between constantly creating new stack 3507 // slots and always reusing the same one. We currently always create 3508 // new ones, as reuse may inhibit scheduling. 3509 MVT::ValueType slotVT = 3510 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT; 3511 const Type *Ty = MVT::getTypeForValueType(slotVT); 3512 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3513 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3514 MachineFunction &MF = DAG.getMachineFunction(); 3515 int SSFI = 3516 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3517 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3518 if (Node->getOpcode() == ISD::FP_EXTEND) { 3519 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), 3520 StackSlot, NULL, 0); 3521 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT, 3522 Result, StackSlot, NULL, 0, oldVT); 3523 } else { 3524 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3525 StackSlot, NULL, 0, newVT); 3526 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0, newVT); 3527 } 3528 break; 3529 } 3530 } 3531 } 3532 // FALL THROUGH 3533 case ISD::ANY_EXTEND: 3534 case ISD::ZERO_EXTEND: 3535 case ISD::SIGN_EXTEND: 3536 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3537 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3538 case Legal: 3539 Tmp1 = LegalizeOp(Node->getOperand(0)); 3540 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3541 break; 3542 case Promote: 3543 switch (Node->getOpcode()) { 3544 case ISD::ANY_EXTEND: 3545 Tmp1 = PromoteOp(Node->getOperand(0)); 3546 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3547 break; 3548 case ISD::ZERO_EXTEND: 3549 Result = PromoteOp(Node->getOperand(0)); 3550 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3551 Result = DAG.getZeroExtendInReg(Result, 3552 Node->getOperand(0).getValueType()); 3553 break; 3554 case ISD::SIGN_EXTEND: 3555 Result = PromoteOp(Node->getOperand(0)); 3556 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3557 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3558 Result, 3559 DAG.getValueType(Node->getOperand(0).getValueType())); 3560 break; 3561 case ISD::FP_EXTEND: 3562 Result = PromoteOp(Node->getOperand(0)); 3563 if (Result.getValueType() != Op.getValueType()) 3564 // Dynamically dead while we have only 2 FP types. 3565 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 3566 break; 3567 case ISD::FP_ROUND: 3568 Result = PromoteOp(Node->getOperand(0)); 3569 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 3570 break; 3571 } 3572 } 3573 break; 3574 case ISD::FP_ROUND_INREG: 3575 case ISD::SIGN_EXTEND_INREG: { 3576 Tmp1 = LegalizeOp(Node->getOperand(0)); 3577 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3578 3579 // If this operation is not supported, convert it to a shl/shr or load/store 3580 // pair. 3581 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3582 default: assert(0 && "This action not supported for this op yet!"); 3583 case TargetLowering::Legal: 3584 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3585 break; 3586 case TargetLowering::Expand: 3587 // If this is an integer extend and shifts are supported, do that. 3588 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3589 // NOTE: we could fall back on load/store here too for targets without 3590 // SAR. However, it is doubtful that any exist. 3591 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3592 MVT::getSizeInBits(ExtraVT); 3593 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3594 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3595 Node->getOperand(0), ShiftCst); 3596 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3597 Result, ShiftCst); 3598 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3599 // The only way we can lower this is to turn it into a TRUNCSTORE, 3600 // EXTLOAD pair, targetting a temporary location (a stack slot). 3601 3602 // NOTE: there is a choice here between constantly creating new stack 3603 // slots and always reusing the same one. We currently always create 3604 // new ones, as reuse may inhibit scheduling. 3605 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 3606 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3607 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3608 MachineFunction &MF = DAG.getMachineFunction(); 3609 int SSFI = 3610 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3611 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3612 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3613 StackSlot, NULL, 0, ExtraVT); 3614 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 3615 Result, StackSlot, NULL, 0, ExtraVT); 3616 } else { 3617 assert(0 && "Unknown op"); 3618 } 3619 break; 3620 } 3621 break; 3622 } 3623 case ISD::TRAMPOLINE: { 3624 SDOperand Ops[6]; 3625 for (unsigned i = 0; i != 6; ++i) 3626 Ops[i] = LegalizeOp(Node->getOperand(i)); 3627 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3628 // The only option for this node is to custom lower it. 3629 Result = TLI.LowerOperation(Result, DAG); 3630 assert(Result.Val && "Should always custom lower!"); 3631 3632 // Since trampoline produces two values, make sure to remember that we 3633 // legalized both of them. 3634 Tmp1 = LegalizeOp(Result.getValue(1)); 3635 Result = LegalizeOp(Result); 3636 AddLegalizedOperand(SDOperand(Node, 0), Result); 3637 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3638 return Op.ResNo ? Tmp1 : Result; 3639 } 3640 } 3641 3642 assert(Result.getValueType() == Op.getValueType() && 3643 "Bad legalization!"); 3644 3645 // Make sure that the generated code is itself legal. 3646 if (Result != Op) 3647 Result = LegalizeOp(Result); 3648 3649 // Note that LegalizeOp may be reentered even from single-use nodes, which 3650 // means that we always must cache transformed nodes. 3651 AddLegalizedOperand(Op, Result); 3652 return Result; 3653} 3654 3655/// PromoteOp - Given an operation that produces a value in an invalid type, 3656/// promote it to compute the value into a larger type. The produced value will 3657/// have the correct bits for the low portion of the register, but no guarantee 3658/// is made about the top bits: it may be zero, sign-extended, or garbage. 3659SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 3660 MVT::ValueType VT = Op.getValueType(); 3661 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3662 assert(getTypeAction(VT) == Promote && 3663 "Caller should expand or legalize operands that are not promotable!"); 3664 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 3665 "Cannot promote to smaller type!"); 3666 3667 SDOperand Tmp1, Tmp2, Tmp3; 3668 SDOperand Result; 3669 SDNode *Node = Op.Val; 3670 3671 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 3672 if (I != PromotedNodes.end()) return I->second; 3673 3674 switch (Node->getOpcode()) { 3675 case ISD::CopyFromReg: 3676 assert(0 && "CopyFromReg must be legal!"); 3677 default: 3678#ifndef NDEBUG 3679 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 3680#endif 3681 assert(0 && "Do not know how to promote this operator!"); 3682 abort(); 3683 case ISD::UNDEF: 3684 Result = DAG.getNode(ISD::UNDEF, NVT); 3685 break; 3686 case ISD::Constant: 3687 if (VT != MVT::i1) 3688 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 3689 else 3690 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 3691 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 3692 break; 3693 case ISD::ConstantFP: 3694 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 3695 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 3696 break; 3697 3698 case ISD::SETCC: 3699 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 3700 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 3701 Node->getOperand(1), Node->getOperand(2)); 3702 break; 3703 3704 case ISD::TRUNCATE: 3705 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3706 case Legal: 3707 Result = LegalizeOp(Node->getOperand(0)); 3708 assert(Result.getValueType() >= NVT && 3709 "This truncation doesn't make sense!"); 3710 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 3711 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 3712 break; 3713 case Promote: 3714 // The truncation is not required, because we don't guarantee anything 3715 // about high bits anyway. 3716 Result = PromoteOp(Node->getOperand(0)); 3717 break; 3718 case Expand: 3719 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3720 // Truncate the low part of the expanded value to the result type 3721 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 3722 } 3723 break; 3724 case ISD::SIGN_EXTEND: 3725 case ISD::ZERO_EXTEND: 3726 case ISD::ANY_EXTEND: 3727 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3728 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 3729 case Legal: 3730 // Input is legal? Just do extend all the way to the larger type. 3731 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3732 break; 3733 case Promote: 3734 // Promote the reg if it's smaller. 3735 Result = PromoteOp(Node->getOperand(0)); 3736 // The high bits are not guaranteed to be anything. Insert an extend. 3737 if (Node->getOpcode() == ISD::SIGN_EXTEND) 3738 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3739 DAG.getValueType(Node->getOperand(0).getValueType())); 3740 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 3741 Result = DAG.getZeroExtendInReg(Result, 3742 Node->getOperand(0).getValueType()); 3743 break; 3744 } 3745 break; 3746 case ISD::BIT_CONVERT: 3747 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3748 Result = PromoteOp(Result); 3749 break; 3750 3751 case ISD::FP_EXTEND: 3752 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 3753 case ISD::FP_ROUND: 3754 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3755 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 3756 case Promote: assert(0 && "Unreachable with 2 FP types!"); 3757 case Legal: 3758 // Input is legal? Do an FP_ROUND_INREG. 3759 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 3760 DAG.getValueType(VT)); 3761 break; 3762 } 3763 break; 3764 3765 case ISD::SINT_TO_FP: 3766 case ISD::UINT_TO_FP: 3767 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3768 case Legal: 3769 // No extra round required here. 3770 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3771 break; 3772 3773 case Promote: 3774 Result = PromoteOp(Node->getOperand(0)); 3775 if (Node->getOpcode() == ISD::SINT_TO_FP) 3776 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3777 Result, 3778 DAG.getValueType(Node->getOperand(0).getValueType())); 3779 else 3780 Result = DAG.getZeroExtendInReg(Result, 3781 Node->getOperand(0).getValueType()); 3782 // No extra round required here. 3783 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3784 break; 3785 case Expand: 3786 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3787 Node->getOperand(0)); 3788 // Round if we cannot tolerate excess precision. 3789 if (NoExcessFPPrecision) 3790 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3791 DAG.getValueType(VT)); 3792 break; 3793 } 3794 break; 3795 3796 case ISD::SIGN_EXTEND_INREG: 3797 Result = PromoteOp(Node->getOperand(0)); 3798 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3799 Node->getOperand(1)); 3800 break; 3801 case ISD::FP_TO_SINT: 3802 case ISD::FP_TO_UINT: 3803 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3804 case Legal: 3805 case Expand: 3806 Tmp1 = Node->getOperand(0); 3807 break; 3808 case Promote: 3809 // The input result is prerounded, so we don't have to do anything 3810 // special. 3811 Tmp1 = PromoteOp(Node->getOperand(0)); 3812 break; 3813 } 3814 // If we're promoting a UINT to a larger size, check to see if the new node 3815 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3816 // we can use that instead. This allows us to generate better code for 3817 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3818 // legal, such as PowerPC. 3819 if (Node->getOpcode() == ISD::FP_TO_UINT && 3820 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3821 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3822 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3823 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3824 } else { 3825 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3826 } 3827 break; 3828 3829 case ISD::FABS: 3830 case ISD::FNEG: 3831 Tmp1 = PromoteOp(Node->getOperand(0)); 3832 assert(Tmp1.getValueType() == NVT); 3833 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3834 // NOTE: we do not have to do any extra rounding here for 3835 // NoExcessFPPrecision, because we know the input will have the appropriate 3836 // precision, and these operations don't modify precision at all. 3837 break; 3838 3839 case ISD::FSQRT: 3840 case ISD::FSIN: 3841 case ISD::FCOS: 3842 Tmp1 = PromoteOp(Node->getOperand(0)); 3843 assert(Tmp1.getValueType() == NVT); 3844 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3845 if (NoExcessFPPrecision) 3846 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3847 DAG.getValueType(VT)); 3848 break; 3849 3850 case ISD::FPOWI: { 3851 // Promote f32 powi to f64 powi. Note that this could insert a libcall 3852 // directly as well, which may be better. 3853 Tmp1 = PromoteOp(Node->getOperand(0)); 3854 assert(Tmp1.getValueType() == NVT); 3855 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 3856 if (NoExcessFPPrecision) 3857 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3858 DAG.getValueType(VT)); 3859 break; 3860 } 3861 3862 case ISD::AND: 3863 case ISD::OR: 3864 case ISD::XOR: 3865 case ISD::ADD: 3866 case ISD::SUB: 3867 case ISD::MUL: 3868 // The input may have strange things in the top bits of the registers, but 3869 // these operations don't care. They may have weird bits going out, but 3870 // that too is okay if they are integer operations. 3871 Tmp1 = PromoteOp(Node->getOperand(0)); 3872 Tmp2 = PromoteOp(Node->getOperand(1)); 3873 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3874 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3875 break; 3876 case ISD::FADD: 3877 case ISD::FSUB: 3878 case ISD::FMUL: 3879 Tmp1 = PromoteOp(Node->getOperand(0)); 3880 Tmp2 = PromoteOp(Node->getOperand(1)); 3881 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3882 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3883 3884 // Floating point operations will give excess precision that we may not be 3885 // able to tolerate. If we DO allow excess precision, just leave it, 3886 // otherwise excise it. 3887 // FIXME: Why would we need to round FP ops more than integer ones? 3888 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3889 if (NoExcessFPPrecision) 3890 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3891 DAG.getValueType(VT)); 3892 break; 3893 3894 case ISD::SDIV: 3895 case ISD::SREM: 3896 // These operators require that their input be sign extended. 3897 Tmp1 = PromoteOp(Node->getOperand(0)); 3898 Tmp2 = PromoteOp(Node->getOperand(1)); 3899 if (MVT::isInteger(NVT)) { 3900 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3901 DAG.getValueType(VT)); 3902 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3903 DAG.getValueType(VT)); 3904 } 3905 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3906 3907 // Perform FP_ROUND: this is probably overly pessimistic. 3908 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 3909 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3910 DAG.getValueType(VT)); 3911 break; 3912 case ISD::FDIV: 3913 case ISD::FREM: 3914 case ISD::FCOPYSIGN: 3915 // These operators require that their input be fp extended. 3916 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3917 case Legal: 3918 Tmp1 = LegalizeOp(Node->getOperand(0)); 3919 break; 3920 case Promote: 3921 Tmp1 = PromoteOp(Node->getOperand(0)); 3922 break; 3923 case Expand: 3924 assert(0 && "not implemented"); 3925 } 3926 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3927 case Legal: 3928 Tmp2 = LegalizeOp(Node->getOperand(1)); 3929 break; 3930 case Promote: 3931 Tmp2 = PromoteOp(Node->getOperand(1)); 3932 break; 3933 case Expand: 3934 assert(0 && "not implemented"); 3935 } 3936 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3937 3938 // Perform FP_ROUND: this is probably overly pessimistic. 3939 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 3940 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3941 DAG.getValueType(VT)); 3942 break; 3943 3944 case ISD::UDIV: 3945 case ISD::UREM: 3946 // These operators require that their input be zero extended. 3947 Tmp1 = PromoteOp(Node->getOperand(0)); 3948 Tmp2 = PromoteOp(Node->getOperand(1)); 3949 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 3950 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3951 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3952 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3953 break; 3954 3955 case ISD::SHL: 3956 Tmp1 = PromoteOp(Node->getOperand(0)); 3957 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 3958 break; 3959 case ISD::SRA: 3960 // The input value must be properly sign extended. 3961 Tmp1 = PromoteOp(Node->getOperand(0)); 3962 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3963 DAG.getValueType(VT)); 3964 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 3965 break; 3966 case ISD::SRL: 3967 // The input value must be properly zero extended. 3968 Tmp1 = PromoteOp(Node->getOperand(0)); 3969 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3970 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 3971 break; 3972 3973 case ISD::VAARG: 3974 Tmp1 = Node->getOperand(0); // Get the chain. 3975 Tmp2 = Node->getOperand(1); // Get the pointer. 3976 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 3977 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 3978 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 3979 } else { 3980 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 3981 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3982 SV->getValue(), SV->getOffset()); 3983 // Increment the pointer, VAList, to the next vaarg 3984 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3985 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3986 TLI.getPointerTy())); 3987 // Store the incremented VAList to the legalized pointer 3988 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 3989 SV->getOffset()); 3990 // Load the actual argument out of the pointer VAList 3991 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 3992 } 3993 // Remember that we legalized the chain. 3994 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3995 break; 3996 3997 case ISD::LOAD: { 3998 LoadSDNode *LD = cast<LoadSDNode>(Node); 3999 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4000 ? ISD::EXTLOAD : LD->getExtensionType(); 4001 Result = DAG.getExtLoad(ExtType, NVT, 4002 LD->getChain(), LD->getBasePtr(), 4003 LD->getSrcValue(), LD->getSrcValueOffset(), 4004 LD->getLoadedVT(), 4005 LD->isVolatile(), 4006 LD->getAlignment()); 4007 // Remember that we legalized the chain. 4008 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4009 break; 4010 } 4011 case ISD::SELECT: 4012 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4013 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4014 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 4015 break; 4016 case ISD::SELECT_CC: 4017 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4018 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4019 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4020 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4021 break; 4022 case ISD::BSWAP: 4023 Tmp1 = Node->getOperand(0); 4024 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4025 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4026 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4027 DAG.getConstant(MVT::getSizeInBits(NVT) - 4028 MVT::getSizeInBits(VT), 4029 TLI.getShiftAmountTy())); 4030 break; 4031 case ISD::CTPOP: 4032 case ISD::CTTZ: 4033 case ISD::CTLZ: 4034 // Zero extend the argument 4035 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4036 // Perform the larger operation, then subtract if needed. 4037 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4038 switch(Node->getOpcode()) { 4039 case ISD::CTPOP: 4040 Result = Tmp1; 4041 break; 4042 case ISD::CTTZ: 4043 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4044 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 4045 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 4046 ISD::SETEQ); 4047 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4048 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); 4049 break; 4050 case ISD::CTLZ: 4051 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4052 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4053 DAG.getConstant(MVT::getSizeInBits(NVT) - 4054 MVT::getSizeInBits(VT), NVT)); 4055 break; 4056 } 4057 break; 4058 case ISD::EXTRACT_SUBVECTOR: 4059 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4060 break; 4061 case ISD::EXTRACT_VECTOR_ELT: 4062 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4063 break; 4064 } 4065 4066 assert(Result.Val && "Didn't set a result!"); 4067 4068 // Make sure the result is itself legal. 4069 Result = LegalizeOp(Result); 4070 4071 // Remember that we promoted this! 4072 AddPromotedOperand(Op, Result); 4073 return Result; 4074} 4075 4076/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4077/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4078/// based on the vector type. The return type of this matches the element type 4079/// of the vector, which may not be legal for the target. 4080SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 4081 // We know that operand #0 is the Vec vector. If the index is a constant 4082 // or if the invec is a supported hardware type, we can use it. Otherwise, 4083 // lower to a store then an indexed load. 4084 SDOperand Vec = Op.getOperand(0); 4085 SDOperand Idx = Op.getOperand(1); 4086 4087 MVT::ValueType TVT = Vec.getValueType(); 4088 unsigned NumElems = MVT::getVectorNumElements(TVT); 4089 4090 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4091 default: assert(0 && "This action is not supported yet!"); 4092 case TargetLowering::Custom: { 4093 Vec = LegalizeOp(Vec); 4094 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4095 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 4096 if (Tmp3.Val) 4097 return Tmp3; 4098 break; 4099 } 4100 case TargetLowering::Legal: 4101 if (isTypeLegal(TVT)) { 4102 Vec = LegalizeOp(Vec); 4103 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4104 return Op; 4105 } 4106 break; 4107 case TargetLowering::Expand: 4108 break; 4109 } 4110 4111 if (NumElems == 1) { 4112 // This must be an access of the only element. Return it. 4113 Op = ScalarizeVectorOp(Vec); 4114 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4115 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4116 SDOperand Lo, Hi; 4117 SplitVectorOp(Vec, Lo, Hi); 4118 if (CIdx->getValue() < NumElems/2) { 4119 Vec = Lo; 4120 } else { 4121 Vec = Hi; 4122 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, 4123 Idx.getValueType()); 4124 } 4125 4126 // It's now an extract from the appropriate high or low part. Recurse. 4127 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4128 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4129 } else { 4130 // Store the value to a temporary stack slot, then LOAD the scalar 4131 // element back out. 4132 SDOperand StackPtr = CreateStackTemporary(Vec.getValueType()); 4133 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4134 4135 // Add the offset to the index. 4136 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 4137 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4138 DAG.getConstant(EltSize, Idx.getValueType())); 4139 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4140 4141 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4142 } 4143 return Op; 4144} 4145 4146/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4147/// we assume the operation can be split if it is not already legal. 4148SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 4149 // We know that operand #0 is the Vec vector. For now we assume the index 4150 // is a constant and that the extracted result is a supported hardware type. 4151 SDOperand Vec = Op.getOperand(0); 4152 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 4153 4154 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); 4155 4156 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { 4157 // This must be an access of the desired vector length. Return it. 4158 return Vec; 4159 } 4160 4161 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4162 SDOperand Lo, Hi; 4163 SplitVectorOp(Vec, Lo, Hi); 4164 if (CIdx->getValue() < NumElems/2) { 4165 Vec = Lo; 4166 } else { 4167 Vec = Hi; 4168 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4169 } 4170 4171 // It's now an extract from the appropriate high or low part. Recurse. 4172 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4173 return ExpandEXTRACT_SUBVECTOR(Op); 4174} 4175 4176/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4177/// with condition CC on the current target. This usually involves legalizing 4178/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4179/// there may be no choice but to create a new SetCC node to represent the 4180/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4181/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 4182void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 4183 SDOperand &RHS, 4184 SDOperand &CC) { 4185 SDOperand Tmp1, Tmp2, Tmp3, Result; 4186 4187 switch (getTypeAction(LHS.getValueType())) { 4188 case Legal: 4189 Tmp1 = LegalizeOp(LHS); // LHS 4190 Tmp2 = LegalizeOp(RHS); // RHS 4191 break; 4192 case Promote: 4193 Tmp1 = PromoteOp(LHS); // LHS 4194 Tmp2 = PromoteOp(RHS); // RHS 4195 4196 // If this is an FP compare, the operands have already been extended. 4197 if (MVT::isInteger(LHS.getValueType())) { 4198 MVT::ValueType VT = LHS.getValueType(); 4199 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4200 4201 // Otherwise, we have to insert explicit sign or zero extends. Note 4202 // that we could insert sign extends for ALL conditions, but zero extend 4203 // is cheaper on many machines (an AND instead of two shifts), so prefer 4204 // it. 4205 switch (cast<CondCodeSDNode>(CC)->get()) { 4206 default: assert(0 && "Unknown integer comparison!"); 4207 case ISD::SETEQ: 4208 case ISD::SETNE: 4209 case ISD::SETUGE: 4210 case ISD::SETUGT: 4211 case ISD::SETULE: 4212 case ISD::SETULT: 4213 // ALL of these operations will work if we either sign or zero extend 4214 // the operands (including the unsigned comparisons!). Zero extend is 4215 // usually a simpler/cheaper operation, so prefer it. 4216 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4217 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4218 break; 4219 case ISD::SETGE: 4220 case ISD::SETGT: 4221 case ISD::SETLT: 4222 case ISD::SETLE: 4223 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4224 DAG.getValueType(VT)); 4225 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4226 DAG.getValueType(VT)); 4227 break; 4228 } 4229 } 4230 break; 4231 case Expand: { 4232 MVT::ValueType VT = LHS.getValueType(); 4233 if (VT == MVT::f32 || VT == MVT::f64) { 4234 // Expand into one or more soft-fp libcall(s). 4235 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 4236 switch (cast<CondCodeSDNode>(CC)->get()) { 4237 case ISD::SETEQ: 4238 case ISD::SETOEQ: 4239 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4240 break; 4241 case ISD::SETNE: 4242 case ISD::SETUNE: 4243 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4244 break; 4245 case ISD::SETGE: 4246 case ISD::SETOGE: 4247 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4248 break; 4249 case ISD::SETLT: 4250 case ISD::SETOLT: 4251 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4252 break; 4253 case ISD::SETLE: 4254 case ISD::SETOLE: 4255 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4256 break; 4257 case ISD::SETGT: 4258 case ISD::SETOGT: 4259 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4260 break; 4261 case ISD::SETUO: 4262 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4263 break; 4264 case ISD::SETO: 4265 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4266 break; 4267 default: 4268 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4269 switch (cast<CondCodeSDNode>(CC)->get()) { 4270 case ISD::SETONE: 4271 // SETONE = SETOLT | SETOGT 4272 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4273 // Fallthrough 4274 case ISD::SETUGT: 4275 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4276 break; 4277 case ISD::SETUGE: 4278 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4279 break; 4280 case ISD::SETULT: 4281 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4282 break; 4283 case ISD::SETULE: 4284 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4285 break; 4286 case ISD::SETUEQ: 4287 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4288 break; 4289 default: assert(0 && "Unsupported FP setcc!"); 4290 } 4291 } 4292 4293 SDOperand Dummy; 4294 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 4295 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4296 false /*sign irrelevant*/, Dummy); 4297 Tmp2 = DAG.getConstant(0, MVT::i32); 4298 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4299 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4300 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); 4301 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 4302 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4303 false /*sign irrelevant*/, Dummy); 4304 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, 4305 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4306 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4307 Tmp2 = SDOperand(); 4308 } 4309 LHS = Tmp1; 4310 RHS = Tmp2; 4311 return; 4312 } 4313 4314 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4315 ExpandOp(LHS, LHSLo, LHSHi); 4316 ExpandOp(RHS, RHSLo, RHSHi); 4317 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4318 4319 if (VT==MVT::ppcf128) { 4320 // FIXME: This generated code sucks. We want to generate 4321 // FCMP crN, hi1, hi2 4322 // BNE crN, L: 4323 // FCMP crN, lo1, lo2 4324 // The following can be improved, but not that much. 4325 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4326 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode); 4327 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4328 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE); 4329 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode); 4330 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4331 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4332 Tmp2 = SDOperand(); 4333 break; 4334 } 4335 4336 switch (CCCode) { 4337 case ISD::SETEQ: 4338 case ISD::SETNE: 4339 if (RHSLo == RHSHi) 4340 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4341 if (RHSCST->isAllOnesValue()) { 4342 // Comparison to -1. 4343 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4344 Tmp2 = RHSLo; 4345 break; 4346 } 4347 4348 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4349 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4350 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4351 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4352 break; 4353 default: 4354 // If this is a comparison of the sign bit, just look at the top part. 4355 // X > -1, x < 0 4356 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4357 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4358 CST->getValue() == 0) || // X < 0 4359 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4360 CST->isAllOnesValue())) { // X > -1 4361 Tmp1 = LHSHi; 4362 Tmp2 = RHSHi; 4363 break; 4364 } 4365 4366 // FIXME: This generated code sucks. 4367 ISD::CondCode LowCC; 4368 switch (CCCode) { 4369 default: assert(0 && "Unknown integer setcc!"); 4370 case ISD::SETLT: 4371 case ISD::SETULT: LowCC = ISD::SETULT; break; 4372 case ISD::SETGT: 4373 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4374 case ISD::SETLE: 4375 case ISD::SETULE: LowCC = ISD::SETULE; break; 4376 case ISD::SETGE: 4377 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4378 } 4379 4380 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4381 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4382 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4383 4384 // NOTE: on targets without efficient SELECT of bools, we can always use 4385 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4386 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4387 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, 4388 false, DagCombineInfo); 4389 if (!Tmp1.Val) 4390 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 4391 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4392 CCCode, false, DagCombineInfo); 4393 if (!Tmp2.Val) 4394 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC); 4395 4396 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4397 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4398 if ((Tmp1C && Tmp1C->getValue() == 0) || 4399 (Tmp2C && Tmp2C->getValue() == 0 && 4400 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4401 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4402 (Tmp2C && Tmp2C->getValue() == 1 && 4403 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4404 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4405 // low part is known false, returns high part. 4406 // For LE / GE, if high part is known false, ignore the low part. 4407 // For LT / GT, if high part is known true, ignore the low part. 4408 Tmp1 = Tmp2; 4409 Tmp2 = SDOperand(); 4410 } else { 4411 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4412 ISD::SETEQ, false, DagCombineInfo); 4413 if (!Result.Val) 4414 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4415 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4416 Result, Tmp1, Tmp2)); 4417 Tmp1 = Result; 4418 Tmp2 = SDOperand(); 4419 } 4420 } 4421 } 4422 } 4423 LHS = Tmp1; 4424 RHS = Tmp2; 4425} 4426 4427/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 4428/// The resultant code need not be legal. Note that SrcOp is the input operand 4429/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 4430SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 4431 SDOperand SrcOp) { 4432 // Create the stack frame object. 4433 SDOperand FIPtr = CreateStackTemporary(DestVT); 4434 4435 // Emit a store to the stack slot. 4436 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); 4437 // Result is a load from the stack slot. 4438 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4439} 4440 4441SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4442 // Create a vector sized/aligned stack slot, store the value to element #0, 4443 // then load the whole vector back out. 4444 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); 4445 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4446 NULL, 0); 4447 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); 4448} 4449 4450 4451/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4452/// support the operation, but do support the resultant vector type. 4453SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4454 4455 // If the only non-undef value is the low element, turn this into a 4456 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4457 unsigned NumElems = Node->getNumOperands(); 4458 bool isOnlyLowElement = true; 4459 SDOperand SplatValue = Node->getOperand(0); 4460 std::map<SDOperand, std::vector<unsigned> > Values; 4461 Values[SplatValue].push_back(0); 4462 bool isConstant = true; 4463 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4464 SplatValue.getOpcode() != ISD::UNDEF) 4465 isConstant = false; 4466 4467 for (unsigned i = 1; i < NumElems; ++i) { 4468 SDOperand V = Node->getOperand(i); 4469 Values[V].push_back(i); 4470 if (V.getOpcode() != ISD::UNDEF) 4471 isOnlyLowElement = false; 4472 if (SplatValue != V) 4473 SplatValue = SDOperand(0,0); 4474 4475 // If this isn't a constant element or an undef, we can't use a constant 4476 // pool load. 4477 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4478 V.getOpcode() != ISD::UNDEF) 4479 isConstant = false; 4480 } 4481 4482 if (isOnlyLowElement) { 4483 // If the low element is an undef too, then this whole things is an undef. 4484 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4485 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4486 // Otherwise, turn this into a scalar_to_vector node. 4487 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4488 Node->getOperand(0)); 4489 } 4490 4491 // If all elements are constants, create a load from the constant pool. 4492 if (isConstant) { 4493 MVT::ValueType VT = Node->getValueType(0); 4494 const Type *OpNTy = 4495 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 4496 std::vector<Constant*> CV; 4497 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4498 if (ConstantFPSDNode *V = 4499 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4500 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF())); 4501 } else if (ConstantSDNode *V = 4502 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4503 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 4504 } else { 4505 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4506 CV.push_back(UndefValue::get(OpNTy)); 4507 } 4508 } 4509 Constant *CP = ConstantVector::get(CV); 4510 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4511 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 4512 } 4513 4514 if (SplatValue.Val) { // Splat of one value? 4515 // Build the shuffle constant vector: <0, 0, 0, 0> 4516 MVT::ValueType MaskVT = 4517 MVT::getIntVectorWithNumElements(NumElems); 4518 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); 4519 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4520 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4521 &ZeroVec[0], ZeroVec.size()); 4522 4523 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4524 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 4525 // Get the splatted value into the low element of a vector register. 4526 SDOperand LowValVec = 4527 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 4528 4529 // Return shuffle(LowValVec, undef, <0,0,0,0>) 4530 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 4531 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 4532 SplatMask); 4533 } 4534 } 4535 4536 // If there are only two unique elements, we may be able to turn this into a 4537 // vector shuffle. 4538 if (Values.size() == 2) { 4539 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 4540 MVT::ValueType MaskVT = 4541 MVT::getIntVectorWithNumElements(NumElems); 4542 std::vector<SDOperand> MaskVec(NumElems); 4543 unsigned i = 0; 4544 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4545 E = Values.end(); I != E; ++I) { 4546 for (std::vector<unsigned>::iterator II = I->second.begin(), 4547 EE = I->second.end(); II != EE; ++II) 4548 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT)); 4549 i += NumElems; 4550 } 4551 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4552 &MaskVec[0], MaskVec.size()); 4553 4554 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4555 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 4556 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 4557 SmallVector<SDOperand, 8> Ops; 4558 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4559 E = Values.end(); I != E; ++I) { 4560 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4561 I->first); 4562 Ops.push_back(Op); 4563 } 4564 Ops.push_back(ShuffleMask); 4565 4566 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 4567 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 4568 &Ops[0], Ops.size()); 4569 } 4570 } 4571 4572 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 4573 // aligned object on the stack, store each element into it, then load 4574 // the result as a vector. 4575 MVT::ValueType VT = Node->getValueType(0); 4576 // Create the stack frame object. 4577 SDOperand FIPtr = CreateStackTemporary(VT); 4578 4579 // Emit a store of each element to the stack slot. 4580 SmallVector<SDOperand, 8> Stores; 4581 unsigned TypeByteSize = 4582 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 4583 // Store (in the right endianness) the elements to memory. 4584 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4585 // Ignore undef elements. 4586 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4587 4588 unsigned Offset = TypeByteSize*i; 4589 4590 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 4591 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 4592 4593 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 4594 NULL, 0)); 4595 } 4596 4597 SDOperand StoreChain; 4598 if (!Stores.empty()) // Not all undef elements? 4599 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4600 &Stores[0], Stores.size()); 4601 else 4602 StoreChain = DAG.getEntryNode(); 4603 4604 // Result is a load from the stack slot. 4605 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 4606} 4607 4608/// CreateStackTemporary - Create a stack temporary, suitable for holding the 4609/// specified value type. 4610SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) { 4611 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4612 unsigned ByteSize = MVT::getSizeInBits(VT)/8; 4613 const Type *Ty = MVT::getTypeForValueType(VT); 4614 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty); 4615 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 4616 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 4617} 4618 4619void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 4620 SDOperand Op, SDOperand Amt, 4621 SDOperand &Lo, SDOperand &Hi) { 4622 // Expand the subcomponents. 4623 SDOperand LHSL, LHSH; 4624 ExpandOp(Op, LHSL, LHSH); 4625 4626 SDOperand Ops[] = { LHSL, LHSH, Amt }; 4627 MVT::ValueType VT = LHSL.getValueType(); 4628 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 4629 Hi = Lo.getValue(1); 4630} 4631 4632 4633/// ExpandShift - Try to find a clever way to expand this shift operation out to 4634/// smaller elements. If we can't find a way that is more efficient than a 4635/// libcall on this target, return false. Otherwise, return true with the 4636/// low-parts expanded into Lo and Hi. 4637bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 4638 SDOperand &Lo, SDOperand &Hi) { 4639 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 4640 "This is not a shift!"); 4641 4642 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 4643 SDOperand ShAmt = LegalizeOp(Amt); 4644 MVT::ValueType ShTy = ShAmt.getValueType(); 4645 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 4646 unsigned NVTBits = MVT::getSizeInBits(NVT); 4647 4648 // Handle the case when Amt is an immediate. 4649 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 4650 unsigned Cst = CN->getValue(); 4651 // Expand the incoming operand to be shifted, so that we have its parts 4652 SDOperand InL, InH; 4653 ExpandOp(Op, InL, InH); 4654 switch(Opc) { 4655 case ISD::SHL: 4656 if (Cst > VTBits) { 4657 Lo = DAG.getConstant(0, NVT); 4658 Hi = DAG.getConstant(0, NVT); 4659 } else if (Cst > NVTBits) { 4660 Lo = DAG.getConstant(0, NVT); 4661 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 4662 } else if (Cst == NVTBits) { 4663 Lo = DAG.getConstant(0, NVT); 4664 Hi = InL; 4665 } else { 4666 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 4667 Hi = DAG.getNode(ISD::OR, NVT, 4668 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 4669 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 4670 } 4671 return true; 4672 case ISD::SRL: 4673 if (Cst > VTBits) { 4674 Lo = DAG.getConstant(0, NVT); 4675 Hi = DAG.getConstant(0, NVT); 4676 } else if (Cst > NVTBits) { 4677 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 4678 Hi = DAG.getConstant(0, NVT); 4679 } else if (Cst == NVTBits) { 4680 Lo = InH; 4681 Hi = DAG.getConstant(0, NVT); 4682 } else { 4683 Lo = DAG.getNode(ISD::OR, NVT, 4684 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4685 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4686 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 4687 } 4688 return true; 4689 case ISD::SRA: 4690 if (Cst > VTBits) { 4691 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 4692 DAG.getConstant(NVTBits-1, ShTy)); 4693 } else if (Cst > NVTBits) { 4694 Lo = DAG.getNode(ISD::SRA, NVT, InH, 4695 DAG.getConstant(Cst-NVTBits, ShTy)); 4696 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4697 DAG.getConstant(NVTBits-1, ShTy)); 4698 } else if (Cst == NVTBits) { 4699 Lo = InH; 4700 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4701 DAG.getConstant(NVTBits-1, ShTy)); 4702 } else { 4703 Lo = DAG.getNode(ISD::OR, NVT, 4704 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4705 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4706 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 4707 } 4708 return true; 4709 } 4710 } 4711 4712 // Okay, the shift amount isn't constant. However, if we can tell that it is 4713 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 4714 uint64_t Mask = NVTBits, KnownZero, KnownOne; 4715 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 4716 4717 // If we know that the high bit of the shift amount is one, then we can do 4718 // this as a couple of simple shifts. 4719 if (KnownOne & Mask) { 4720 // Mask out the high bit, which we know is set. 4721 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 4722 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4723 4724 // Expand the incoming operand to be shifted, so that we have its parts 4725 SDOperand InL, InH; 4726 ExpandOp(Op, InL, InH); 4727 switch(Opc) { 4728 case ISD::SHL: 4729 Lo = DAG.getConstant(0, NVT); // Low part is zero. 4730 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 4731 return true; 4732 case ISD::SRL: 4733 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 4734 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 4735 return true; 4736 case ISD::SRA: 4737 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 4738 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4739 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 4740 return true; 4741 } 4742 } 4743 4744 // If we know that the high bit of the shift amount is zero, then we can do 4745 // this as a couple of simple shifts. 4746 if (KnownZero & Mask) { 4747 // Compute 32-amt. 4748 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 4749 DAG.getConstant(NVTBits, Amt.getValueType()), 4750 Amt); 4751 4752 // Expand the incoming operand to be shifted, so that we have its parts 4753 SDOperand InL, InH; 4754 ExpandOp(Op, InL, InH); 4755 switch(Opc) { 4756 case ISD::SHL: 4757 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 4758 Hi = DAG.getNode(ISD::OR, NVT, 4759 DAG.getNode(ISD::SHL, NVT, InH, Amt), 4760 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 4761 return true; 4762 case ISD::SRL: 4763 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 4764 Lo = DAG.getNode(ISD::OR, NVT, 4765 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4766 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4767 return true; 4768 case ISD::SRA: 4769 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 4770 Lo = DAG.getNode(ISD::OR, NVT, 4771 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4772 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4773 return true; 4774 } 4775 } 4776 4777 return false; 4778} 4779 4780 4781// ExpandLibCall - Expand a node into a call to a libcall. If the result value 4782// does not fit into a register, return the lo part and set the hi part to the 4783// by-reg argument. If it does fit into a single register, return the result 4784// and leave the Hi part unset. 4785SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 4786 bool isSigned, SDOperand &Hi) { 4787 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 4788 // The input chain to this libcall is the entry node of the function. 4789 // Legalizing the call will automatically add the previous call to the 4790 // dependence. 4791 SDOperand InChain = DAG.getEntryNode(); 4792 4793 TargetLowering::ArgListTy Args; 4794 TargetLowering::ArgListEntry Entry; 4795 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4796 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 4797 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 4798 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 4799 Entry.isSExt = isSigned; 4800 Args.push_back(Entry); 4801 } 4802 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 4803 4804 // Splice the libcall in wherever FindInputOutputChains tells us to. 4805 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 4806 std::pair<SDOperand,SDOperand> CallInfo = 4807 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false, 4808 Callee, Args, DAG); 4809 4810 // Legalize the call sequence, starting with the chain. This will advance 4811 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 4812 // was added by LowerCallTo (guaranteeing proper serialization of calls). 4813 LegalizeOp(CallInfo.second); 4814 SDOperand Result; 4815 switch (getTypeAction(CallInfo.first.getValueType())) { 4816 default: assert(0 && "Unknown thing"); 4817 case Legal: 4818 Result = CallInfo.first; 4819 break; 4820 case Expand: 4821 ExpandOp(CallInfo.first, Result, Hi); 4822 break; 4823 } 4824 return Result; 4825} 4826 4827 4828/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 4829/// 4830SDOperand SelectionDAGLegalize:: 4831ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 4832 assert(getTypeAction(Source.getValueType()) == Expand && 4833 "This is not an expansion!"); 4834 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 4835 4836 if (!isSigned) { 4837 assert(Source.getValueType() == MVT::i64 && 4838 "This only works for 64-bit -> FP"); 4839 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 4840 // incoming integer is set. To handle this, we dynamically test to see if 4841 // it is set, and, if so, add a fudge factor. 4842 SDOperand Lo, Hi; 4843 ExpandOp(Source, Lo, Hi); 4844 4845 // If this is unsigned, and not supported, first perform the conversion to 4846 // signed, then adjust the result if the sign bit is set. 4847 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 4848 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 4849 4850 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 4851 DAG.getConstant(0, Hi.getValueType()), 4852 ISD::SETLT); 4853 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4854 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4855 SignSet, Four, Zero); 4856 uint64_t FF = 0x5f800000ULL; 4857 if (TLI.isLittleEndian()) FF <<= 32; 4858 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4859 4860 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4861 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4862 SDOperand FudgeInReg; 4863 if (DestTy == MVT::f32) 4864 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4865 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) 4866 // FIXME: Avoid the extend by construction the right constantpool? 4867 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 4868 CPIdx, NULL, 0, MVT::f32); 4869 else 4870 assert(0 && "Unexpected conversion"); 4871 4872 MVT::ValueType SCVT = SignedConv.getValueType(); 4873 if (SCVT != DestTy) { 4874 // Destination type needs to be expanded as well. The FADD now we are 4875 // constructing will be expanded into a libcall. 4876 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { 4877 assert(SCVT == MVT::i32 && DestTy == MVT::f64); 4878 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, 4879 SignedConv, SignedConv.getValue(1)); 4880 } 4881 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 4882 } 4883 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 4884 } 4885 4886 // Check to see if the target has a custom way to lower this. If so, use it. 4887 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 4888 default: assert(0 && "This action not implemented for this operation!"); 4889 case TargetLowering::Legal: 4890 case TargetLowering::Expand: 4891 break; // This case is handled below. 4892 case TargetLowering::Custom: { 4893 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 4894 Source), DAG); 4895 if (NV.Val) 4896 return LegalizeOp(NV); 4897 break; // The target decided this was legal after all 4898 } 4899 } 4900 4901 // Expand the source, then glue it back together for the call. We must expand 4902 // the source in case it is shared (this pass of legalize must traverse it). 4903 SDOperand SrcLo, SrcHi; 4904 ExpandOp(Source, SrcLo, SrcHi); 4905 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 4906 4907 RTLIB::Libcall LC; 4908 if (DestTy == MVT::f32) 4909 LC = RTLIB::SINTTOFP_I64_F32; 4910 else { 4911 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 4912 LC = RTLIB::SINTTOFP_I64_F64; 4913 } 4914 4915 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 4916 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 4917 SDOperand UnusedHiPart; 4918 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 4919 UnusedHiPart); 4920} 4921 4922/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 4923/// INT_TO_FP operation of the specified operand when the target requests that 4924/// we expand it. At this point, we know that the result and operand types are 4925/// legal for the target. 4926SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 4927 SDOperand Op0, 4928 MVT::ValueType DestVT) { 4929 if (Op0.getValueType() == MVT::i32) { 4930 // simple 32-bit [signed|unsigned] integer to float/double expansion 4931 4932 // get the stack frame index of a 8 byte buffer, pessimistically aligned 4933 MachineFunction &MF = DAG.getMachineFunction(); 4934 const Type *F64Type = MVT::getTypeForValueType(MVT::f64); 4935 unsigned StackAlign = 4936 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type); 4937 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign); 4938 // get address of 8 byte buffer 4939 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4940 // word offset constant for Hi/Lo address computation 4941 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 4942 // set up Hi and Lo (into buffer) address based on endian 4943 SDOperand Hi = StackSlot; 4944 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 4945 if (TLI.isLittleEndian()) 4946 std::swap(Hi, Lo); 4947 4948 // if signed map to unsigned space 4949 SDOperand Op0Mapped; 4950 if (isSigned) { 4951 // constant used to invert sign bit (signed to unsigned mapping) 4952 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 4953 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 4954 } else { 4955 Op0Mapped = Op0; 4956 } 4957 // store the lo of the constructed double - based on integer input 4958 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 4959 Op0Mapped, Lo, NULL, 0); 4960 // initial hi portion of constructed double 4961 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 4962 // store the hi of the constructed double - biased exponent 4963 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 4964 // load the constructed double 4965 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 4966 // FP constant to bias correct the final result 4967 SDOperand Bias = DAG.getConstantFP(isSigned ? 4968 BitsToDouble(0x4330000080000000ULL) 4969 : BitsToDouble(0x4330000000000000ULL), 4970 MVT::f64); 4971 // subtract the bias 4972 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 4973 // final result 4974 SDOperand Result; 4975 // handle final rounding 4976 if (DestVT == MVT::f64) { 4977 // do nothing 4978 Result = Sub; 4979 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) { 4980 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub); 4981 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) { 4982 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 4983 } 4984 return Result; 4985 } 4986 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 4987 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 4988 4989 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 4990 DAG.getConstant(0, Op0.getValueType()), 4991 ISD::SETLT); 4992 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4993 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4994 SignSet, Four, Zero); 4995 4996 // If the sign bit of the integer is set, the large number will be treated 4997 // as a negative number. To counteract this, the dynamic code adds an 4998 // offset depending on the data type. 4999 uint64_t FF; 5000 switch (Op0.getValueType()) { 5001 default: assert(0 && "Unsupported integer type!"); 5002 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5003 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5004 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5005 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5006 } 5007 if (TLI.isLittleEndian()) FF <<= 32; 5008 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5009 5010 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5011 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5012 SDOperand FudgeInReg; 5013 if (DestVT == MVT::f32) 5014 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 5015 else { 5016 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5017 DAG.getEntryNode(), CPIdx, 5018 NULL, 0, MVT::f32)); 5019 } 5020 5021 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5022} 5023 5024/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5025/// *INT_TO_FP operation of the specified operand when the target requests that 5026/// we promote it. At this point, we know that the result and operand types are 5027/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5028/// operation that takes a larger input. 5029SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 5030 MVT::ValueType DestVT, 5031 bool isSigned) { 5032 // First step, figure out the appropriate *INT_TO_FP operation to use. 5033 MVT::ValueType NewInTy = LegalOp.getValueType(); 5034 5035 unsigned OpToUse = 0; 5036 5037 // Scan for the appropriate larger type to use. 5038 while (1) { 5039 NewInTy = (MVT::ValueType)(NewInTy+1); 5040 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 5041 5042 // If the target supports SINT_TO_FP of this type, use it. 5043 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5044 default: break; 5045 case TargetLowering::Legal: 5046 if (!TLI.isTypeLegal(NewInTy)) 5047 break; // Can't use this datatype. 5048 // FALL THROUGH. 5049 case TargetLowering::Custom: 5050 OpToUse = ISD::SINT_TO_FP; 5051 break; 5052 } 5053 if (OpToUse) break; 5054 if (isSigned) continue; 5055 5056 // If the target supports UINT_TO_FP of this type, use it. 5057 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5058 default: break; 5059 case TargetLowering::Legal: 5060 if (!TLI.isTypeLegal(NewInTy)) 5061 break; // Can't use this datatype. 5062 // FALL THROUGH. 5063 case TargetLowering::Custom: 5064 OpToUse = ISD::UINT_TO_FP; 5065 break; 5066 } 5067 if (OpToUse) break; 5068 5069 // Otherwise, try a larger type. 5070 } 5071 5072 // Okay, we found the operation and type to use. Zero extend our input to the 5073 // desired type then run the operation on it. 5074 return DAG.getNode(OpToUse, DestVT, 5075 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5076 NewInTy, LegalOp)); 5077} 5078 5079/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5080/// FP_TO_*INT operation of the specified operand when the target requests that 5081/// we promote it. At this point, we know that the result and operand types are 5082/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5083/// operation that returns a larger result. 5084SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 5085 MVT::ValueType DestVT, 5086 bool isSigned) { 5087 // First step, figure out the appropriate FP_TO*INT operation to use. 5088 MVT::ValueType NewOutTy = DestVT; 5089 5090 unsigned OpToUse = 0; 5091 5092 // Scan for the appropriate larger type to use. 5093 while (1) { 5094 NewOutTy = (MVT::ValueType)(NewOutTy+1); 5095 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 5096 5097 // If the target supports FP_TO_SINT returning this type, use it. 5098 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5099 default: break; 5100 case TargetLowering::Legal: 5101 if (!TLI.isTypeLegal(NewOutTy)) 5102 break; // Can't use this datatype. 5103 // FALL THROUGH. 5104 case TargetLowering::Custom: 5105 OpToUse = ISD::FP_TO_SINT; 5106 break; 5107 } 5108 if (OpToUse) break; 5109 5110 // If the target supports FP_TO_UINT of this type, use it. 5111 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5112 default: break; 5113 case TargetLowering::Legal: 5114 if (!TLI.isTypeLegal(NewOutTy)) 5115 break; // Can't use this datatype. 5116 // FALL THROUGH. 5117 case TargetLowering::Custom: 5118 OpToUse = ISD::FP_TO_UINT; 5119 break; 5120 } 5121 if (OpToUse) break; 5122 5123 // Otherwise, try a larger type. 5124 } 5125 5126 // Okay, we found the operation and type to use. Truncate the result of the 5127 // extended FP_TO_*INT operation to the desired size. 5128 return DAG.getNode(ISD::TRUNCATE, DestVT, 5129 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 5130} 5131 5132/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5133/// 5134SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 5135 MVT::ValueType VT = Op.getValueType(); 5136 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 5137 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5138 switch (VT) { 5139 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5140 case MVT::i16: 5141 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5142 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5143 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5144 case MVT::i32: 5145 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5146 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5147 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5148 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5149 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5150 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5151 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5152 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5153 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5154 case MVT::i64: 5155 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5156 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5157 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5158 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5159 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5160 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5161 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5162 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5163 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5164 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5165 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5166 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5167 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5168 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5169 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5170 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5171 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5172 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5173 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5174 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5175 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5176 } 5177} 5178 5179/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5180/// 5181SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 5182 switch (Opc) { 5183 default: assert(0 && "Cannot expand this yet!"); 5184 case ISD::CTPOP: { 5185 static const uint64_t mask[6] = { 5186 0x5555555555555555ULL, 0x3333333333333333ULL, 5187 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5188 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5189 }; 5190 MVT::ValueType VT = Op.getValueType(); 5191 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5192 unsigned len = MVT::getSizeInBits(VT); 5193 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5194 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5195 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 5196 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5197 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5198 DAG.getNode(ISD::AND, VT, 5199 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5200 } 5201 return Op; 5202 } 5203 case ISD::CTLZ: { 5204 // for now, we do this: 5205 // x = x | (x >> 1); 5206 // x = x | (x >> 2); 5207 // ... 5208 // x = x | (x >>16); 5209 // x = x | (x >>32); // for 64-bit input 5210 // return popcount(~x); 5211 // 5212 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5213 MVT::ValueType VT = Op.getValueType(); 5214 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5215 unsigned len = MVT::getSizeInBits(VT); 5216 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5217 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5218 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5219 } 5220 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5221 return DAG.getNode(ISD::CTPOP, VT, Op); 5222 } 5223 case ISD::CTTZ: { 5224 // for now, we use: { return popcount(~x & (x - 1)); } 5225 // unless the target has ctlz but not ctpop, in which case we use: 5226 // { return 32 - nlz(~x & (x-1)); } 5227 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5228 MVT::ValueType VT = Op.getValueType(); 5229 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 5230 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 5231 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5232 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5233 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5234 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5235 TLI.isOperationLegal(ISD::CTLZ, VT)) 5236 return DAG.getNode(ISD::SUB, VT, 5237 DAG.getConstant(MVT::getSizeInBits(VT), VT), 5238 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5239 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5240 } 5241 } 5242} 5243 5244/// ExpandOp - Expand the specified SDOperand into its two component pieces 5245/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5246/// LegalizeNodes map is filled in for any results that are not expanded, the 5247/// ExpandedNodes map is filled in for any results that are expanded, and the 5248/// Lo/Hi values are returned. 5249void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 5250 MVT::ValueType VT = Op.getValueType(); 5251 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 5252 SDNode *Node = Op.Val; 5253 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5254 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 5255 MVT::isVector(VT)) && 5256 "Cannot expand to FP value or to larger int value!"); 5257 5258 // See if we already expanded it. 5259 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5260 = ExpandedNodes.find(Op); 5261 if (I != ExpandedNodes.end()) { 5262 Lo = I->second.first; 5263 Hi = I->second.second; 5264 return; 5265 } 5266 5267 switch (Node->getOpcode()) { 5268 case ISD::CopyFromReg: 5269 assert(0 && "CopyFromReg must be legal!"); 5270 case ISD::FP_ROUND_INREG: 5271 if (VT == MVT::ppcf128 && 5272 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5273 TargetLowering::Custom) { 5274 SDOperand SrcLo, SrcHi, Src; 5275 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5276 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5277 SDOperand Result = TLI.LowerOperation( 5278 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5279 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5280 Lo = Result.Val->getOperand(0); 5281 Hi = Result.Val->getOperand(1); 5282 break; 5283 } 5284 // fall through 5285 default: 5286#ifndef NDEBUG 5287 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5288#endif 5289 assert(0 && "Do not know how to expand this operator!"); 5290 abort(); 5291 case ISD::UNDEF: 5292 NVT = TLI.getTypeToExpandTo(VT); 5293 Lo = DAG.getNode(ISD::UNDEF, NVT); 5294 Hi = DAG.getNode(ISD::UNDEF, NVT); 5295 break; 5296 case ISD::Constant: { 5297 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 5298 Lo = DAG.getConstant(Cst, NVT); 5299 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 5300 break; 5301 } 5302 case ISD::ConstantFP: { 5303 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5304 if (CFP->getValueType(0) == MVT::ppcf128) { 5305 APInt api = CFP->getValueAPF().convertToAPInt(); 5306 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5307 MVT::f64); 5308 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5309 MVT::f64); 5310 break; 5311 } 5312 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5313 if (getTypeAction(Lo.getValueType()) == Expand) 5314 ExpandOp(Lo, Lo, Hi); 5315 break; 5316 } 5317 case ISD::BUILD_PAIR: 5318 // Return the operands. 5319 Lo = Node->getOperand(0); 5320 Hi = Node->getOperand(1); 5321 break; 5322 5323 case ISD::SIGN_EXTEND_INREG: 5324 ExpandOp(Node->getOperand(0), Lo, Hi); 5325 // sext_inreg the low part if needed. 5326 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5327 5328 // The high part gets the sign extension from the lo-part. This handles 5329 // things like sextinreg V:i64 from i8. 5330 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5331 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 5332 TLI.getShiftAmountTy())); 5333 break; 5334 5335 case ISD::BSWAP: { 5336 ExpandOp(Node->getOperand(0), Lo, Hi); 5337 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5338 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5339 Lo = TempLo; 5340 break; 5341 } 5342 5343 case ISD::CTPOP: 5344 ExpandOp(Node->getOperand(0), Lo, Hi); 5345 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5346 DAG.getNode(ISD::CTPOP, NVT, Lo), 5347 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5348 Hi = DAG.getConstant(0, NVT); 5349 break; 5350 5351 case ISD::CTLZ: { 5352 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5353 ExpandOp(Node->getOperand(0), Lo, Hi); 5354 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5355 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5356 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 5357 ISD::SETNE); 5358 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5359 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5360 5361 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5362 Hi = DAG.getConstant(0, NVT); 5363 break; 5364 } 5365 5366 case ISD::CTTZ: { 5367 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5368 ExpandOp(Node->getOperand(0), Lo, Hi); 5369 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5370 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5371 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 5372 ISD::SETNE); 5373 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5374 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5375 5376 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5377 Hi = DAG.getConstant(0, NVT); 5378 break; 5379 } 5380 5381 case ISD::VAARG: { 5382 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5383 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5384 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5385 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5386 5387 // Remember that we legalized the chain. 5388 Hi = LegalizeOp(Hi); 5389 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5390 if (!TLI.isLittleEndian()) 5391 std::swap(Lo, Hi); 5392 break; 5393 } 5394 5395 case ISD::LOAD: { 5396 LoadSDNode *LD = cast<LoadSDNode>(Node); 5397 SDOperand Ch = LD->getChain(); // Legalize the chain. 5398 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5399 ISD::LoadExtType ExtType = LD->getExtensionType(); 5400 int SVOffset = LD->getSrcValueOffset(); 5401 unsigned Alignment = LD->getAlignment(); 5402 bool isVolatile = LD->isVolatile(); 5403 5404 if (ExtType == ISD::NON_EXTLOAD) { 5405 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5406 isVolatile, Alignment); 5407 if (VT == MVT::f32 || VT == MVT::f64) { 5408 // f32->i32 or f64->i64 one to one expansion. 5409 // Remember that we legalized the chain. 5410 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5411 // Recursively expand the new load. 5412 if (getTypeAction(NVT) == Expand) 5413 ExpandOp(Lo, Lo, Hi); 5414 break; 5415 } 5416 5417 // Increment the pointer to the other half. 5418 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 5419 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5420 getIntPtrConstant(IncrementSize)); 5421 SVOffset += IncrementSize; 5422 if (Alignment > IncrementSize) 5423 Alignment = IncrementSize; 5424 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5425 isVolatile, Alignment); 5426 5427 // Build a factor node to remember that this load is independent of the 5428 // other one. 5429 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5430 Hi.getValue(1)); 5431 5432 // Remember that we legalized the chain. 5433 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5434 if (!TLI.isLittleEndian()) 5435 std::swap(Lo, Hi); 5436 } else { 5437 MVT::ValueType EVT = LD->getLoadedVT(); 5438 5439 if (VT == MVT::f64 && EVT == MVT::f32) { 5440 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5441 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5442 SVOffset, isVolatile, Alignment); 5443 // Remember that we legalized the chain. 5444 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 5445 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 5446 break; 5447 } 5448 5449 if (EVT == NVT) 5450 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 5451 SVOffset, isVolatile, Alignment); 5452 else 5453 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 5454 SVOffset, EVT, isVolatile, 5455 Alignment); 5456 5457 // Remember that we legalized the chain. 5458 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5459 5460 if (ExtType == ISD::SEXTLOAD) { 5461 // The high part is obtained by SRA'ing all but one of the bits of the 5462 // lo part. 5463 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5464 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5465 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5466 } else if (ExtType == ISD::ZEXTLOAD) { 5467 // The high part is just a zero. 5468 Hi = DAG.getConstant(0, NVT); 5469 } else /* if (ExtType == ISD::EXTLOAD) */ { 5470 // The high part is undefined. 5471 Hi = DAG.getNode(ISD::UNDEF, NVT); 5472 } 5473 } 5474 break; 5475 } 5476 case ISD::AND: 5477 case ISD::OR: 5478 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 5479 SDOperand LL, LH, RL, RH; 5480 ExpandOp(Node->getOperand(0), LL, LH); 5481 ExpandOp(Node->getOperand(1), RL, RH); 5482 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 5483 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 5484 break; 5485 } 5486 case ISD::SELECT: { 5487 SDOperand LL, LH, RL, RH; 5488 ExpandOp(Node->getOperand(1), LL, LH); 5489 ExpandOp(Node->getOperand(2), RL, RH); 5490 if (getTypeAction(NVT) == Expand) 5491 NVT = TLI.getTypeToExpandTo(NVT); 5492 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 5493 if (VT != MVT::f32) 5494 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 5495 break; 5496 } 5497 case ISD::SELECT_CC: { 5498 SDOperand TL, TH, FL, FH; 5499 ExpandOp(Node->getOperand(2), TL, TH); 5500 ExpandOp(Node->getOperand(3), FL, FH); 5501 if (getTypeAction(NVT) == Expand) 5502 NVT = TLI.getTypeToExpandTo(NVT); 5503 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5504 Node->getOperand(1), TL, FL, Node->getOperand(4)); 5505 if (VT != MVT::f32) 5506 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5507 Node->getOperand(1), TH, FH, Node->getOperand(4)); 5508 break; 5509 } 5510 case ISD::ANY_EXTEND: 5511 // The low part is any extension of the input (which degenerates to a copy). 5512 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 5513 // The high part is undefined. 5514 Hi = DAG.getNode(ISD::UNDEF, NVT); 5515 break; 5516 case ISD::SIGN_EXTEND: { 5517 // The low part is just a sign extension of the input (which degenerates to 5518 // a copy). 5519 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 5520 5521 // The high part is obtained by SRA'ing all but one of the bits of the lo 5522 // part. 5523 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5524 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5525 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5526 break; 5527 } 5528 case ISD::ZERO_EXTEND: 5529 // The low part is just a zero extension of the input (which degenerates to 5530 // a copy). 5531 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 5532 5533 // The high part is just a zero. 5534 Hi = DAG.getConstant(0, NVT); 5535 break; 5536 5537 case ISD::TRUNCATE: { 5538 // The input value must be larger than this value. Expand *it*. 5539 SDOperand NewLo; 5540 ExpandOp(Node->getOperand(0), NewLo, Hi); 5541 5542 // The low part is now either the right size, or it is closer. If not the 5543 // right size, make an illegal truncate so we recursively expand it. 5544 if (NewLo.getValueType() != Node->getValueType(0)) 5545 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 5546 ExpandOp(NewLo, Lo, Hi); 5547 break; 5548 } 5549 5550 case ISD::BIT_CONVERT: { 5551 SDOperand Tmp; 5552 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 5553 // If the target wants to, allow it to lower this itself. 5554 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5555 case Expand: assert(0 && "cannot expand FP!"); 5556 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 5557 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 5558 } 5559 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 5560 } 5561 5562 // f32 / f64 must be expanded to i32 / i64. 5563 if (VT == MVT::f32 || VT == MVT::f64) { 5564 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5565 if (getTypeAction(NVT) == Expand) 5566 ExpandOp(Lo, Lo, Hi); 5567 break; 5568 } 5569 5570 // If source operand will be expanded to the same type as VT, i.e. 5571 // i64 <- f64, i32 <- f32, expand the source operand instead. 5572 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 5573 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 5574 ExpandOp(Node->getOperand(0), Lo, Hi); 5575 break; 5576 } 5577 5578 // Turn this into a load/store pair by default. 5579 if (Tmp.Val == 0) 5580 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0)); 5581 5582 ExpandOp(Tmp, Lo, Hi); 5583 break; 5584 } 5585 5586 case ISD::READCYCLECOUNTER: 5587 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 5588 TargetLowering::Custom && 5589 "Must custom expand ReadCycleCounter"); 5590 Lo = TLI.LowerOperation(Op, DAG); 5591 assert(Lo.Val && "Node must be custom expanded!"); 5592 Hi = Lo.getValue(1); 5593 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 5594 LegalizeOp(Lo.getValue(2))); 5595 break; 5596 5597 // These operators cannot be expanded directly, emit them as calls to 5598 // library functions. 5599 case ISD::FP_TO_SINT: { 5600 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 5601 SDOperand Op; 5602 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5603 case Expand: assert(0 && "cannot expand FP!"); 5604 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5605 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5606 } 5607 5608 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 5609 5610 // Now that the custom expander is done, expand the result, which is still 5611 // VT. 5612 if (Op.Val) { 5613 ExpandOp(Op, Lo, Hi); 5614 break; 5615 } 5616 } 5617 5618 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5619 if (Node->getOperand(0).getValueType() == MVT::f32) 5620 LC = RTLIB::FPTOSINT_F32_I64; 5621 else if (Node->getOperand(0).getValueType() == MVT::f64) 5622 LC = RTLIB::FPTOSINT_F64_I64; 5623 else if (Node->getOperand(0).getValueType() == MVT::f80) 5624 LC = RTLIB::FPTOSINT_F80_I64; 5625 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 5626 LC = RTLIB::FPTOSINT_PPCF128_I64; 5627 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5628 false/*sign irrelevant*/, Hi); 5629 break; 5630 } 5631 5632 case ISD::FP_TO_UINT: { 5633 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 5634 SDOperand Op; 5635 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5636 case Expand: assert(0 && "cannot expand FP!"); 5637 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5638 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5639 } 5640 5641 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 5642 5643 // Now that the custom expander is done, expand the result. 5644 if (Op.Val) { 5645 ExpandOp(Op, Lo, Hi); 5646 break; 5647 } 5648 } 5649 5650 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5651 if (Node->getOperand(0).getValueType() == MVT::f32) 5652 LC = RTLIB::FPTOUINT_F32_I64; 5653 else if (Node->getOperand(0).getValueType() == MVT::f64) 5654 LC = RTLIB::FPTOUINT_F64_I64; 5655 else if (Node->getOperand(0).getValueType() == MVT::f80) 5656 LC = RTLIB::FPTOUINT_F80_I64; 5657 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 5658 LC = RTLIB::FPTOUINT_PPCF128_I64; 5659 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5660 false/*sign irrelevant*/, Hi); 5661 break; 5662 } 5663 5664 case ISD::SHL: { 5665 // If the target wants custom lowering, do so. 5666 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5667 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 5668 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 5669 Op = TLI.LowerOperation(Op, DAG); 5670 if (Op.Val) { 5671 // Now that the custom expander is done, expand the result, which is 5672 // still VT. 5673 ExpandOp(Op, Lo, Hi); 5674 break; 5675 } 5676 } 5677 5678 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 5679 // this X << 1 as X+X. 5680 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 5681 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 5682 TLI.isOperationLegal(ISD::ADDE, NVT)) { 5683 SDOperand LoOps[2], HiOps[3]; 5684 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 5685 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 5686 LoOps[1] = LoOps[0]; 5687 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5688 5689 HiOps[1] = HiOps[0]; 5690 HiOps[2] = Lo.getValue(1); 5691 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5692 break; 5693 } 5694 } 5695 5696 // If we can emit an efficient shift operation, do so now. 5697 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5698 break; 5699 5700 // If this target supports SHL_PARTS, use it. 5701 TargetLowering::LegalizeAction Action = 5702 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 5703 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5704 Action == TargetLowering::Custom) { 5705 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5706 break; 5707 } 5708 5709 // Otherwise, emit a libcall. 5710 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 5711 false/*left shift=unsigned*/, Hi); 5712 break; 5713 } 5714 5715 case ISD::SRA: { 5716 // If the target wants custom lowering, do so. 5717 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5718 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 5719 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 5720 Op = TLI.LowerOperation(Op, DAG); 5721 if (Op.Val) { 5722 // Now that the custom expander is done, expand the result, which is 5723 // still VT. 5724 ExpandOp(Op, Lo, Hi); 5725 break; 5726 } 5727 } 5728 5729 // If we can emit an efficient shift operation, do so now. 5730 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5731 break; 5732 5733 // If this target supports SRA_PARTS, use it. 5734 TargetLowering::LegalizeAction Action = 5735 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 5736 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5737 Action == TargetLowering::Custom) { 5738 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5739 break; 5740 } 5741 5742 // Otherwise, emit a libcall. 5743 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 5744 true/*ashr is signed*/, Hi); 5745 break; 5746 } 5747 5748 case ISD::SRL: { 5749 // If the target wants custom lowering, do so. 5750 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5751 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 5752 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 5753 Op = TLI.LowerOperation(Op, DAG); 5754 if (Op.Val) { 5755 // Now that the custom expander is done, expand the result, which is 5756 // still VT. 5757 ExpandOp(Op, Lo, Hi); 5758 break; 5759 } 5760 } 5761 5762 // If we can emit an efficient shift operation, do so now. 5763 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5764 break; 5765 5766 // If this target supports SRL_PARTS, use it. 5767 TargetLowering::LegalizeAction Action = 5768 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 5769 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5770 Action == TargetLowering::Custom) { 5771 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5772 break; 5773 } 5774 5775 // Otherwise, emit a libcall. 5776 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 5777 false/*lshr is unsigned*/, Hi); 5778 break; 5779 } 5780 5781 case ISD::ADD: 5782 case ISD::SUB: { 5783 // If the target wants to custom expand this, let them. 5784 if (TLI.getOperationAction(Node->getOpcode(), VT) == 5785 TargetLowering::Custom) { 5786 Op = TLI.LowerOperation(Op, DAG); 5787 if (Op.Val) { 5788 ExpandOp(Op, Lo, Hi); 5789 break; 5790 } 5791 } 5792 5793 // Expand the subcomponents. 5794 SDOperand LHSL, LHSH, RHSL, RHSH; 5795 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5796 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5797 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5798 SDOperand LoOps[2], HiOps[3]; 5799 LoOps[0] = LHSL; 5800 LoOps[1] = RHSL; 5801 HiOps[0] = LHSH; 5802 HiOps[1] = RHSH; 5803 if (Node->getOpcode() == ISD::ADD) { 5804 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5805 HiOps[2] = Lo.getValue(1); 5806 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5807 } else { 5808 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5809 HiOps[2] = Lo.getValue(1); 5810 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5811 } 5812 break; 5813 } 5814 5815 case ISD::ADDC: 5816 case ISD::SUBC: { 5817 // Expand the subcomponents. 5818 SDOperand LHSL, LHSH, RHSL, RHSH; 5819 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5820 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5821 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5822 SDOperand LoOps[2] = { LHSL, RHSL }; 5823 SDOperand HiOps[3] = { LHSH, RHSH }; 5824 5825 if (Node->getOpcode() == ISD::ADDC) { 5826 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5827 HiOps[2] = Lo.getValue(1); 5828 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5829 } else { 5830 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5831 HiOps[2] = Lo.getValue(1); 5832 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5833 } 5834 // Remember that we legalized the flag. 5835 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5836 break; 5837 } 5838 case ISD::ADDE: 5839 case ISD::SUBE: { 5840 // Expand the subcomponents. 5841 SDOperand LHSL, LHSH, RHSL, RHSH; 5842 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5843 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5844 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5845 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 5846 SDOperand HiOps[3] = { LHSH, RHSH }; 5847 5848 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 5849 HiOps[2] = Lo.getValue(1); 5850 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 5851 5852 // Remember that we legalized the flag. 5853 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5854 break; 5855 } 5856 case ISD::MUL: { 5857 // If the target wants to custom expand this, let them. 5858 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 5859 SDOperand New = TLI.LowerOperation(Op, DAG); 5860 if (New.Val) { 5861 ExpandOp(New, Lo, Hi); 5862 break; 5863 } 5864 } 5865 5866 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 5867 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 5868 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 5869 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 5870 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 5871 SDOperand LL, LH, RL, RH; 5872 ExpandOp(Node->getOperand(0), LL, LH); 5873 ExpandOp(Node->getOperand(1), RL, RH); 5874 unsigned BitSize = MVT::getSizeInBits(RH.getValueType()); 5875 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 5876 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 5877 // FIXME: generalize this to handle other bit sizes 5878 if (LHSSB == 32 && RHSSB == 32 && 5879 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) && 5880 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) { 5881 // The inputs are both zero-extended. 5882 if (HasUMUL_LOHI) { 5883 // We can emit a umul_lohi. 5884 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 5885 Hi = SDOperand(Lo.Val, 1); 5886 break; 5887 } 5888 if (HasMULHU) { 5889 // We can emit a mulhu+mul. 5890 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5891 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 5892 break; 5893 } 5894 } 5895 if (LHSSB > BitSize && RHSSB > BitSize) { 5896 // The input values are both sign-extended. 5897 if (HasSMUL_LOHI) { 5898 // We can emit a smul_lohi. 5899 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 5900 Hi = SDOperand(Lo.Val, 1); 5901 break; 5902 } 5903 if (HasMULHS) { 5904 // We can emit a mulhs+mul. 5905 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5906 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 5907 break; 5908 } 5909 } 5910 if (HasUMUL_LOHI) { 5911 // Lo,Hi = umul LHS, RHS. 5912 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 5913 DAG.getVTList(NVT, NVT), LL, RL); 5914 Lo = UMulLOHI; 5915 Hi = UMulLOHI.getValue(1); 5916 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 5917 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 5918 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 5919 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 5920 break; 5921 } 5922 } 5923 5924 // If nothing else, we can make a libcall. 5925 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 5926 false/*sign irrelevant*/, Hi); 5927 break; 5928 } 5929 case ISD::SDIV: 5930 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 5931 break; 5932 case ISD::UDIV: 5933 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 5934 break; 5935 case ISD::SREM: 5936 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 5937 break; 5938 case ISD::UREM: 5939 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 5940 break; 5941 5942 case ISD::FADD: 5943 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::ADD_F32 : 5944 VT == MVT::f64 ? RTLIB::ADD_F64 : 5945 VT == MVT::ppcf128 ? 5946 RTLIB::ADD_PPCF128 : 5947 RTLIB::UNKNOWN_LIBCALL), 5948 Node, false, Hi); 5949 break; 5950 case ISD::FSUB: 5951 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::SUB_F32 : 5952 VT == MVT::f64 ? RTLIB::SUB_F64 : 5953 VT == MVT::ppcf128 ? 5954 RTLIB::SUB_PPCF128 : 5955 RTLIB::UNKNOWN_LIBCALL), 5956 Node, false, Hi); 5957 break; 5958 case ISD::FMUL: 5959 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::MUL_F32 : 5960 VT == MVT::f64 ? RTLIB::MUL_F64 : 5961 VT == MVT::ppcf128 ? 5962 RTLIB::MUL_PPCF128 : 5963 RTLIB::UNKNOWN_LIBCALL), 5964 Node, false, Hi); 5965 break; 5966 case ISD::FDIV: 5967 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::DIV_F32 : 5968 VT == MVT::f64 ? RTLIB::DIV_F64 : 5969 VT == MVT::ppcf128 ? 5970 RTLIB::DIV_PPCF128 : 5971 RTLIB::UNKNOWN_LIBCALL), 5972 Node, false, Hi); 5973 break; 5974 case ISD::FP_EXTEND: 5975 if (VT == MVT::ppcf128) { 5976 assert(Node->getOperand(0).getValueType()==MVT::f32 || 5977 Node->getOperand(0).getValueType()==MVT::f64); 5978 const uint64_t zero = 0; 5979 if (Node->getOperand(0).getValueType()==MVT::f32) 5980 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 5981 else 5982 Hi = Node->getOperand(0); 5983 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 5984 break; 5985 } 5986 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 5987 break; 5988 case ISD::FP_ROUND: 5989 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 5990 break; 5991 case ISD::FPOWI: 5992 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) ? RTLIB::POWI_F32 : 5993 (VT == MVT::f64) ? RTLIB::POWI_F64 : 5994 (VT == MVT::f80) ? RTLIB::POWI_F80 : 5995 (VT == MVT::ppcf128) ? 5996 RTLIB::POWI_PPCF128 : 5997 RTLIB::UNKNOWN_LIBCALL), 5998 Node, false, Hi); 5999 break; 6000 case ISD::FSQRT: 6001 case ISD::FSIN: 6002 case ISD::FCOS: { 6003 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6004 switch(Node->getOpcode()) { 6005 case ISD::FSQRT: 6006 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : 6007 (VT == MVT::f64) ? RTLIB::SQRT_F64 : 6008 (VT == MVT::f80) ? RTLIB::SQRT_F80 : 6009 (VT == MVT::ppcf128) ? RTLIB::SQRT_PPCF128 : 6010 RTLIB::UNKNOWN_LIBCALL; 6011 break; 6012 case ISD::FSIN: 6013 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 6014 break; 6015 case ISD::FCOS: 6016 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64; 6017 break; 6018 default: assert(0 && "Unreachable!"); 6019 } 6020 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 6021 break; 6022 } 6023 case ISD::FABS: { 6024 if (VT == MVT::ppcf128) { 6025 SDOperand Tmp; 6026 ExpandOp(Node->getOperand(0), Lo, Tmp); 6027 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6028 // lo = hi==fabs(hi) ? lo : -lo; 6029 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6030 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6031 DAG.getCondCode(ISD::SETEQ)); 6032 break; 6033 } 6034 SDOperand Mask = (VT == MVT::f64) 6035 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6036 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6037 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6038 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6039 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6040 if (getTypeAction(NVT) == Expand) 6041 ExpandOp(Lo, Lo, Hi); 6042 break; 6043 } 6044 case ISD::FNEG: { 6045 if (VT == MVT::ppcf128) { 6046 ExpandOp(Node->getOperand(0), Lo, Hi); 6047 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6048 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6049 break; 6050 } 6051 SDOperand Mask = (VT == MVT::f64) 6052 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6053 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6054 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6055 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6056 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6057 if (getTypeAction(NVT) == Expand) 6058 ExpandOp(Lo, Lo, Hi); 6059 break; 6060 } 6061 case ISD::FCOPYSIGN: { 6062 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6063 if (getTypeAction(NVT) == Expand) 6064 ExpandOp(Lo, Lo, Hi); 6065 break; 6066 } 6067 case ISD::SINT_TO_FP: 6068 case ISD::UINT_TO_FP: { 6069 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6070 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 6071 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) { 6072 static uint64_t zero = 0; 6073 if (isSigned) { 6074 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6075 Node->getOperand(0))); 6076 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6077 } else { 6078 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6079 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6080 Node->getOperand(0))); 6081 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6082 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6083 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6084 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6085 DAG.getConstant(0, MVT::i32), 6086 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6087 DAG.getConstantFP( 6088 APFloat(APInt(128, 2, TwoE32)), 6089 MVT::ppcf128)), 6090 Hi, 6091 DAG.getCondCode(ISD::SETLT)), 6092 Lo, Hi); 6093 } 6094 break; 6095 } 6096 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6097 // si64->ppcf128 done by libcall, below 6098 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6099 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6100 Lo, Hi); 6101 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6102 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6103 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6104 DAG.getConstant(0, MVT::i64), 6105 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6106 DAG.getConstantFP( 6107 APFloat(APInt(128, 2, TwoE64)), 6108 MVT::ppcf128)), 6109 Hi, 6110 DAG.getCondCode(ISD::SETLT)), 6111 Lo, Hi); 6112 break; 6113 } 6114 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6115 if (Node->getOperand(0).getValueType() == MVT::i64) { 6116 if (VT == MVT::f32) 6117 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; 6118 else if (VT == MVT::f64) 6119 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; 6120 else if (VT == MVT::f80) { 6121 assert(isSigned); 6122 LC = RTLIB::SINTTOFP_I64_F80; 6123 } 6124 else if (VT == MVT::ppcf128) { 6125 assert(isSigned); 6126 LC = RTLIB::SINTTOFP_I64_PPCF128; 6127 } 6128 } else { 6129 if (VT == MVT::f32) 6130 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 6131 else 6132 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 6133 } 6134 6135 // Promote the operand if needed. 6136 if (getTypeAction(SrcVT) == Promote) { 6137 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 6138 Tmp = isSigned 6139 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6140 DAG.getValueType(SrcVT)) 6141 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6142 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6143 } 6144 6145 const char *LibCall = TLI.getLibcallName(LC); 6146 if (LibCall) 6147 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi); 6148 else { 6149 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6150 Node->getOperand(0)); 6151 if (getTypeAction(Lo.getValueType()) == Expand) 6152 ExpandOp(Lo, Lo, Hi); 6153 } 6154 break; 6155 } 6156 } 6157 6158 // Make sure the resultant values have been legalized themselves, unless this 6159 // is a type that requires multi-step expansion. 6160 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6161 Lo = LegalizeOp(Lo); 6162 if (Hi.Val) 6163 // Don't legalize the high part if it is expanded to a single node. 6164 Hi = LegalizeOp(Hi); 6165 } 6166 6167 // Remember in a map if the values will be reused later. 6168 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 6169 assert(isNew && "Value already expanded?!?"); 6170} 6171 6172/// SplitVectorOp - Given an operand of vector type, break it down into 6173/// two smaller values, still of vector type. 6174void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 6175 SDOperand &Hi) { 6176 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); 6177 SDNode *Node = Op.Val; 6178 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType()); 6179 assert(NumElements > 1 && "Cannot split a single element vector!"); 6180 unsigned NewNumElts = NumElements/2; 6181 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType()); 6182 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts); 6183 6184 // See if we already split it. 6185 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 6186 = SplitNodes.find(Op); 6187 if (I != SplitNodes.end()) { 6188 Lo = I->second.first; 6189 Hi = I->second.second; 6190 return; 6191 } 6192 6193 switch (Node->getOpcode()) { 6194 default: 6195#ifndef NDEBUG 6196 Node->dump(&DAG); 6197#endif 6198 assert(0 && "Unhandled operation in SplitVectorOp!"); 6199 case ISD::BUILD_PAIR: 6200 Lo = Node->getOperand(0); 6201 Hi = Node->getOperand(1); 6202 break; 6203 case ISD::INSERT_VECTOR_ELT: { 6204 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6205 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 6206 SDOperand ScalarOp = Node->getOperand(1); 6207 if (Index < NewNumElts) 6208 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, Lo, ScalarOp, 6209 DAG.getConstant(Index, TLI.getPointerTy())); 6210 else 6211 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, Hi, ScalarOp, 6212 DAG.getConstant(Index - NewNumElts, TLI.getPointerTy())); 6213 break; 6214 } 6215 case ISD::BUILD_VECTOR: { 6216 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6217 Node->op_begin()+NewNumElts); 6218 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size()); 6219 6220 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts, 6221 Node->op_end()); 6222 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size()); 6223 break; 6224 } 6225 case ISD::CONCAT_VECTORS: { 6226 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6227 if (NewNumSubvectors == 1) { 6228 Lo = Node->getOperand(0); 6229 Hi = Node->getOperand(1); 6230 } else { 6231 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6232 Node->op_begin()+NewNumSubvectors); 6233 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size()); 6234 6235 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6236 Node->op_end()); 6237 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size()); 6238 } 6239 break; 6240 } 6241 case ISD::ADD: 6242 case ISD::SUB: 6243 case ISD::MUL: 6244 case ISD::FADD: 6245 case ISD::FSUB: 6246 case ISD::FMUL: 6247 case ISD::SDIV: 6248 case ISD::UDIV: 6249 case ISD::FDIV: 6250 case ISD::FPOW: 6251 case ISD::AND: 6252 case ISD::OR: 6253 case ISD::XOR: { 6254 SDOperand LL, LH, RL, RH; 6255 SplitVectorOp(Node->getOperand(0), LL, LH); 6256 SplitVectorOp(Node->getOperand(1), RL, RH); 6257 6258 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL); 6259 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH); 6260 break; 6261 } 6262 case ISD::FPOWI: { 6263 SDOperand L, H; 6264 SplitVectorOp(Node->getOperand(0), L, H); 6265 6266 Lo = DAG.getNode(Node->getOpcode(), NewVT, L, Node->getOperand(1)); 6267 Hi = DAG.getNode(Node->getOpcode(), NewVT, H, Node->getOperand(1)); 6268 break; 6269 } 6270 case ISD::CTTZ: 6271 case ISD::CTLZ: 6272 case ISD::CTPOP: 6273 case ISD::FNEG: 6274 case ISD::FABS: 6275 case ISD::FSQRT: 6276 case ISD::FSIN: 6277 case ISD::FCOS: { 6278 SDOperand L, H; 6279 SplitVectorOp(Node->getOperand(0), L, H); 6280 6281 Lo = DAG.getNode(Node->getOpcode(), NewVT, L); 6282 Hi = DAG.getNode(Node->getOpcode(), NewVT, H); 6283 break; 6284 } 6285 case ISD::LOAD: { 6286 LoadSDNode *LD = cast<LoadSDNode>(Node); 6287 SDOperand Ch = LD->getChain(); 6288 SDOperand Ptr = LD->getBasePtr(); 6289 const Value *SV = LD->getSrcValue(); 6290 int SVOffset = LD->getSrcValueOffset(); 6291 unsigned Alignment = LD->getAlignment(); 6292 bool isVolatile = LD->isVolatile(); 6293 6294 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6295 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8; 6296 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6297 getIntPtrConstant(IncrementSize)); 6298 SVOffset += IncrementSize; 6299 if (Alignment > IncrementSize) 6300 Alignment = IncrementSize; 6301 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6302 6303 // Build a factor node to remember that this load is independent of the 6304 // other one. 6305 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6306 Hi.getValue(1)); 6307 6308 // Remember that we legalized the chain. 6309 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6310 break; 6311 } 6312 case ISD::BIT_CONVERT: { 6313 // We know the result is a vector. The input may be either a vector or a 6314 // scalar value. 6315 SDOperand InOp = Node->getOperand(0); 6316 if (!MVT::isVector(InOp.getValueType()) || 6317 MVT::getVectorNumElements(InOp.getValueType()) == 1) { 6318 // The input is a scalar or single-element vector. 6319 // Lower to a store/load so that it can be split. 6320 // FIXME: this could be improved probably. 6321 SDOperand Ptr = CreateStackTemporary(InOp.getValueType()); 6322 6323 SDOperand St = DAG.getStore(DAG.getEntryNode(), 6324 InOp, Ptr, NULL, 0); 6325 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0); 6326 } 6327 // Split the vector and convert each of the pieces now. 6328 SplitVectorOp(InOp, Lo, Hi); 6329 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo); 6330 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi); 6331 break; 6332 } 6333 } 6334 6335 // Remember in a map if the values will be reused later. 6336 bool isNew = 6337 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 6338 assert(isNew && "Value already split?!?"); 6339} 6340 6341 6342/// ScalarizeVectorOp - Given an operand of single-element vector type 6343/// (e.g. v1f32), convert it into the equivalent operation that returns a 6344/// scalar (e.g. f32) value. 6345SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 6346 assert(MVT::isVector(Op.getValueType()) && 6347 "Bad ScalarizeVectorOp invocation!"); 6348 SDNode *Node = Op.Val; 6349 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); 6350 assert(MVT::getVectorNumElements(Op.getValueType()) == 1); 6351 6352 // See if we already scalarized it. 6353 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 6354 if (I != ScalarizedNodes.end()) return I->second; 6355 6356 SDOperand Result; 6357 switch (Node->getOpcode()) { 6358 default: 6359#ifndef NDEBUG 6360 Node->dump(&DAG); cerr << "\n"; 6361#endif 6362 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 6363 case ISD::ADD: 6364 case ISD::FADD: 6365 case ISD::SUB: 6366 case ISD::FSUB: 6367 case ISD::MUL: 6368 case ISD::FMUL: 6369 case ISD::SDIV: 6370 case ISD::UDIV: 6371 case ISD::FDIV: 6372 case ISD::SREM: 6373 case ISD::UREM: 6374 case ISD::FREM: 6375 case ISD::FPOW: 6376 case ISD::AND: 6377 case ISD::OR: 6378 case ISD::XOR: 6379 Result = DAG.getNode(Node->getOpcode(), 6380 NewVT, 6381 ScalarizeVectorOp(Node->getOperand(0)), 6382 ScalarizeVectorOp(Node->getOperand(1))); 6383 break; 6384 case ISD::FNEG: 6385 case ISD::FABS: 6386 case ISD::FSQRT: 6387 case ISD::FSIN: 6388 case ISD::FCOS: 6389 Result = DAG.getNode(Node->getOpcode(), 6390 NewVT, 6391 ScalarizeVectorOp(Node->getOperand(0))); 6392 break; 6393 case ISD::FPOWI: 6394 Result = DAG.getNode(Node->getOpcode(), 6395 NewVT, 6396 ScalarizeVectorOp(Node->getOperand(0)), 6397 Node->getOperand(1)); 6398 break; 6399 case ISD::LOAD: { 6400 LoadSDNode *LD = cast<LoadSDNode>(Node); 6401 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 6402 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 6403 6404 const Value *SV = LD->getSrcValue(); 6405 int SVOffset = LD->getSrcValueOffset(); 6406 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 6407 LD->isVolatile(), LD->getAlignment()); 6408 6409 // Remember that we legalized the chain. 6410 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 6411 break; 6412 } 6413 case ISD::BUILD_VECTOR: 6414 Result = Node->getOperand(0); 6415 break; 6416 case ISD::INSERT_VECTOR_ELT: 6417 // Returning the inserted scalar element. 6418 Result = Node->getOperand(1); 6419 break; 6420 case ISD::CONCAT_VECTORS: 6421 assert(Node->getOperand(0).getValueType() == NewVT && 6422 "Concat of non-legal vectors not yet supported!"); 6423 Result = Node->getOperand(0); 6424 break; 6425 case ISD::VECTOR_SHUFFLE: { 6426 // Figure out if the scalar is the LHS or RHS and return it. 6427 SDOperand EltNum = Node->getOperand(2).getOperand(0); 6428 if (cast<ConstantSDNode>(EltNum)->getValue()) 6429 Result = ScalarizeVectorOp(Node->getOperand(1)); 6430 else 6431 Result = ScalarizeVectorOp(Node->getOperand(0)); 6432 break; 6433 } 6434 case ISD::EXTRACT_SUBVECTOR: 6435 Result = Node->getOperand(0); 6436 assert(Result.getValueType() == NewVT); 6437 break; 6438 case ISD::BIT_CONVERT: 6439 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 6440 break; 6441 case ISD::SELECT: 6442 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 6443 ScalarizeVectorOp(Op.getOperand(1)), 6444 ScalarizeVectorOp(Op.getOperand(2))); 6445 break; 6446 } 6447 6448 if (TLI.isTypeLegal(NewVT)) 6449 Result = LegalizeOp(Result); 6450 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 6451 assert(isNew && "Value already scalarized?"); 6452 return Result; 6453} 6454 6455 6456// SelectionDAG::Legalize - This is the entry point for the file. 6457// 6458void SelectionDAG::Legalize() { 6459 if (ViewLegalizeDAGs) viewGraph(); 6460 6461 /// run - This is the main entry point to this class. 6462 /// 6463 SelectionDAGLegalize(*this).LegalizeDAG(); 6464} 6465 6466