LegalizeDAG.cpp revision 22c5c1b2dfcb1da6a7ebfebea903401fc77d56e6
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetFrameInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/CallingConv.h" 26#include "llvm/Constants.h" 27#include "llvm/DerivedTypes.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Compiler.h" 30#include "llvm/Support/MathExtras.h" 31#include "llvm/ADT/DenseMap.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/SmallPtrSet.h" 34#include <map> 35using namespace llvm; 36 37#ifndef NDEBUG 38static cl::opt<bool> 39ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 40 cl::desc("Pop up a window to show dags before legalize")); 41#else 42static const bool ViewLegalizeDAGs = 0; 43#endif 44 45//===----------------------------------------------------------------------===// 46/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 47/// hacks on it until the target machine can handle it. This involves 48/// eliminating value sizes the machine cannot handle (promoting small sizes to 49/// large sizes or splitting up large values into small values) as well as 50/// eliminating operations the machine cannot handle. 51/// 52/// This code also does a small amount of optimization and recognition of idioms 53/// as part of its processing. For example, if a target does not support a 54/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 55/// will attempt merge setcc and brc instructions into brcc's. 56/// 57namespace { 58class VISIBILITY_HIDDEN SelectionDAGLegalize { 59 TargetLowering &TLI; 60 SelectionDAG &DAG; 61 62 // Libcall insertion helpers. 63 64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 65 /// legalized. We use this to ensure that calls are properly serialized 66 /// against each other, including inserted libcalls. 67 SDOperand LastCALLSEQ_END; 68 69 /// IsLegalizingCall - This member is used *only* for purposes of providing 70 /// helpful assertions that a libcall isn't created while another call is 71 /// being legalized (which could lead to non-serialized call sequences). 72 bool IsLegalizingCall; 73 74 enum LegalizeAction { 75 Legal, // The target natively supports this operation. 76 Promote, // This operation should be executed in a larger type. 77 Expand // Try to expand this to other ops, otherwise use a libcall. 78 }; 79 80 /// ValueTypeActions - This is a bitvector that contains two bits for each 81 /// value type, where the two bits correspond to the LegalizeAction enum. 82 /// This can be queried with "getTypeAction(VT)". 83 TargetLowering::ValueTypeActionImpl ValueTypeActions; 84 85 /// LegalizedNodes - For nodes that are of legal width, and that have more 86 /// than one use, this map indicates what regularized operand to use. This 87 /// allows us to avoid legalizing the same thing more than once. 88 DenseMap<SDOperand, SDOperand> LegalizedNodes; 89 90 /// PromotedNodes - For nodes that are below legal width, and that have more 91 /// than one use, this map indicates what promoted value to use. This allows 92 /// us to avoid promoting the same thing more than once. 93 DenseMap<SDOperand, SDOperand> PromotedNodes; 94 95 /// ExpandedNodes - For nodes that need to be expanded this map indicates 96 /// which which operands are the expanded version of the input. This allows 97 /// us to avoid expanding the same node more than once. 98 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 99 100 /// SplitNodes - For vector nodes that need to be split, this map indicates 101 /// which which operands are the split version of the input. This allows us 102 /// to avoid splitting the same node more than once. 103 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 104 105 /// ScalarizedNodes - For nodes that need to be converted from vector types to 106 /// scalar types, this contains the mapping of ones we have already 107 /// processed to the result. 108 std::map<SDOperand, SDOperand> ScalarizedNodes; 109 110 void AddLegalizedOperand(SDOperand From, SDOperand To) { 111 LegalizedNodes.insert(std::make_pair(From, To)); 112 // If someone requests legalization of the new node, return itself. 113 if (From != To) 114 LegalizedNodes.insert(std::make_pair(To, To)); 115 } 116 void AddPromotedOperand(SDOperand From, SDOperand To) { 117 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 118 assert(isNew && "Got into the map somehow?"); 119 // If someone requests legalization of the new node, return itself. 120 LegalizedNodes.insert(std::make_pair(To, To)); 121 } 122 123public: 124 125 SelectionDAGLegalize(SelectionDAG &DAG); 126 127 /// getTypeAction - Return how we should legalize values of this type, either 128 /// it is already legal or we need to expand it into multiple registers of 129 /// smaller integer type, or we need to promote it to a larger type. 130 LegalizeAction getTypeAction(MVT::ValueType VT) const { 131 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 132 } 133 134 /// isTypeLegal - Return true if this type is legal on this target. 135 /// 136 bool isTypeLegal(MVT::ValueType VT) const { 137 return getTypeAction(VT) == Legal; 138 } 139 140 void LegalizeDAG(); 141 142private: 143 /// HandleOp - Legalize, Promote, or Expand the specified operand as 144 /// appropriate for its type. 145 void HandleOp(SDOperand Op); 146 147 /// LegalizeOp - We know that the specified value has a legal type. 148 /// Recursively ensure that the operands have legal types, then return the 149 /// result. 150 SDOperand LegalizeOp(SDOperand O); 151 152 /// UnrollVectorOp - We know that the given vector has a legal type, however 153 /// the operation it performs is not legal and is an operation that we have 154 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 155 /// operating on each element individually. 156 SDOperand UnrollVectorOp(SDOperand O); 157 158 /// PromoteOp - Given an operation that produces a value in an invalid type, 159 /// promote it to compute the value into a larger type. The produced value 160 /// will have the correct bits for the low portion of the register, but no 161 /// guarantee is made about the top bits: it may be zero, sign-extended, or 162 /// garbage. 163 SDOperand PromoteOp(SDOperand O); 164 165 /// ExpandOp - Expand the specified SDOperand into its two component pieces 166 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 167 /// the LegalizeNodes map is filled in for any results that are not expanded, 168 /// the ExpandedNodes map is filled in for any results that are expanded, and 169 /// the Lo/Hi values are returned. This applies to integer types and Vector 170 /// types. 171 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 172 173 /// SplitVectorOp - Given an operand of vector type, break it down into 174 /// two smaller values. 175 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 176 177 /// ScalarizeVectorOp - Given an operand of single-element vector type 178 /// (e.g. v1f32), convert it into the equivalent operation that returns a 179 /// scalar (e.g. f32) value. 180 SDOperand ScalarizeVectorOp(SDOperand O); 181 182 /// isShuffleLegal - Return true if a vector shuffle is legal with the 183 /// specified mask and type. Targets can specify exactly which masks they 184 /// support and the code generator is tasked with not creating illegal masks. 185 /// 186 /// Note that this will also return true for shuffles that are promoted to a 187 /// different type. 188 /// 189 /// If this is a legal shuffle, this method returns the (possibly promoted) 190 /// build_vector Mask. If it's not a legal shuffle, it returns null. 191 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 192 193 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 194 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 195 196 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 197 198 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 199 SDOperand &Hi); 200 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 201 SDOperand Source); 202 203 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT, 204 MVT::ValueType DestVT); 205 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 206 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 207 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 208 SDOperand LegalOp, 209 MVT::ValueType DestVT); 210 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 211 bool isSigned); 212 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 213 bool isSigned); 214 215 SDOperand ExpandBSWAP(SDOperand Op); 216 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 217 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 218 SDOperand &Lo, SDOperand &Hi); 219 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 220 SDOperand &Lo, SDOperand &Hi); 221 222 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 223 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 224}; 225} 226 227/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 228/// specified mask and type. Targets can specify exactly which masks they 229/// support and the code generator is tasked with not creating illegal masks. 230/// 231/// Note that this will also return true for shuffles that are promoted to a 232/// different type. 233SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 234 SDOperand Mask) const { 235 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 236 default: return 0; 237 case TargetLowering::Legal: 238 case TargetLowering::Custom: 239 break; 240 case TargetLowering::Promote: { 241 // If this is promoted to a different type, convert the shuffle mask and 242 // ask if it is legal in the promoted type! 243 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 244 245 // If we changed # elements, change the shuffle mask. 246 unsigned NumEltsGrowth = 247 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 248 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 249 if (NumEltsGrowth > 1) { 250 // Renumber the elements. 251 SmallVector<SDOperand, 8> Ops; 252 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 253 SDOperand InOp = Mask.getOperand(i); 254 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 255 if (InOp.getOpcode() == ISD::UNDEF) 256 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 257 else { 258 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 259 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 260 } 261 } 262 } 263 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 264 } 265 VT = NVT; 266 break; 267 } 268 } 269 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 270} 271 272SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 273 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 274 ValueTypeActions(TLI.getValueTypeActions()) { 275 assert(MVT::LAST_VALUETYPE <= 32 && 276 "Too many value types for ValueTypeActions to hold!"); 277} 278 279/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 280/// contains all of a nodes operands before it contains the node. 281static void ComputeTopDownOrdering(SelectionDAG &DAG, 282 SmallVector<SDNode*, 64> &Order) { 283 284 DenseMap<SDNode*, unsigned> Visited; 285 std::vector<SDNode*> Worklist; 286 Worklist.reserve(128); 287 288 // Compute ordering from all of the leaves in the graphs, those (like the 289 // entry node) that have no operands. 290 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 291 E = DAG.allnodes_end(); I != E; ++I) { 292 if (I->getNumOperands() == 0) { 293 Visited[I] = 0 - 1U; 294 Worklist.push_back(I); 295 } 296 } 297 298 while (!Worklist.empty()) { 299 SDNode *N = Worklist.back(); 300 Worklist.pop_back(); 301 302 if (++Visited[N] != N->getNumOperands()) 303 continue; // Haven't visited all operands yet 304 305 Order.push_back(N); 306 307 // Now that we have N in, add anything that uses it if all of their operands 308 // are now done. 309 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 310 UI != E; ++UI) 311 Worklist.push_back(*UI); 312 } 313 314 assert(Order.size() == Visited.size() && 315 Order.size() == 316 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 317 "Error: DAG is cyclic!"); 318} 319 320 321void SelectionDAGLegalize::LegalizeDAG() { 322 LastCALLSEQ_END = DAG.getEntryNode(); 323 IsLegalizingCall = false; 324 325 // The legalize process is inherently a bottom-up recursive process (users 326 // legalize their uses before themselves). Given infinite stack space, we 327 // could just start legalizing on the root and traverse the whole graph. In 328 // practice however, this causes us to run out of stack space on large basic 329 // blocks. To avoid this problem, compute an ordering of the nodes where each 330 // node is only legalized after all of its operands are legalized. 331 SmallVector<SDNode*, 64> Order; 332 ComputeTopDownOrdering(DAG, Order); 333 334 for (unsigned i = 0, e = Order.size(); i != e; ++i) 335 HandleOp(SDOperand(Order[i], 0)); 336 337 // Finally, it's possible the root changed. Get the new root. 338 SDOperand OldRoot = DAG.getRoot(); 339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 340 DAG.setRoot(LegalizedNodes[OldRoot]); 341 342 ExpandedNodes.clear(); 343 LegalizedNodes.clear(); 344 PromotedNodes.clear(); 345 SplitNodes.clear(); 346 ScalarizedNodes.clear(); 347 348 // Remove dead nodes now. 349 DAG.RemoveDeadNodes(); 350} 351 352 353/// FindCallEndFromCallStart - Given a chained node that is part of a call 354/// sequence, find the CALLSEQ_END node that terminates the call sequence. 355static SDNode *FindCallEndFromCallStart(SDNode *Node) { 356 if (Node->getOpcode() == ISD::CALLSEQ_END) 357 return Node; 358 if (Node->use_empty()) 359 return 0; // No CallSeqEnd 360 361 // The chain is usually at the end. 362 SDOperand TheChain(Node, Node->getNumValues()-1); 363 if (TheChain.getValueType() != MVT::Other) { 364 // Sometimes it's at the beginning. 365 TheChain = SDOperand(Node, 0); 366 if (TheChain.getValueType() != MVT::Other) { 367 // Otherwise, hunt for it. 368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 369 if (Node->getValueType(i) == MVT::Other) { 370 TheChain = SDOperand(Node, i); 371 break; 372 } 373 374 // Otherwise, we walked into a node without a chain. 375 if (TheChain.getValueType() != MVT::Other) 376 return 0; 377 } 378 } 379 380 for (SDNode::use_iterator UI = Node->use_begin(), 381 E = Node->use_end(); UI != E; ++UI) { 382 383 // Make sure to only follow users of our token chain. 384 SDNode *User = *UI; 385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 386 if (User->getOperand(i) == TheChain) 387 if (SDNode *Result = FindCallEndFromCallStart(User)) 388 return Result; 389 } 390 return 0; 391} 392 393/// FindCallStartFromCallEnd - Given a chained node that is part of a call 394/// sequence, find the CALLSEQ_START node that initiates the call sequence. 395static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 396 assert(Node && "Didn't find callseq_start for a call??"); 397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 398 399 assert(Node->getOperand(0).getValueType() == MVT::Other && 400 "Node doesn't have a token chain argument!"); 401 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 402} 403 404/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 405/// see if any uses can reach Dest. If no dest operands can get to dest, 406/// legalize them, legalize ourself, and return false, otherwise, return true. 407/// 408/// Keep track of the nodes we fine that actually do lead to Dest in 409/// NodesLeadingTo. This avoids retraversing them exponential number of times. 410/// 411bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 413 if (N == Dest) return true; // N certainly leads to Dest :) 414 415 // If we've already processed this node and it does lead to Dest, there is no 416 // need to reprocess it. 417 if (NodesLeadingTo.count(N)) return true; 418 419 // If the first result of this node has been already legalized, then it cannot 420 // reach N. 421 switch (getTypeAction(N->getValueType(0))) { 422 case Legal: 423 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 424 break; 425 case Promote: 426 if (PromotedNodes.count(SDOperand(N, 0))) return false; 427 break; 428 case Expand: 429 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 430 break; 431 } 432 433 // Okay, this node has not already been legalized. Check and legalize all 434 // operands. If none lead to Dest, then we can legalize this node. 435 bool OperandsLeadToDest = false; 436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 437 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 439 440 if (OperandsLeadToDest) { 441 NodesLeadingTo.insert(N); 442 return true; 443 } 444 445 // Okay, this node looks safe, legalize it and return false. 446 HandleOp(SDOperand(N, 0)); 447 return false; 448} 449 450/// HandleOp - Legalize, Promote, or Expand the specified operand as 451/// appropriate for its type. 452void SelectionDAGLegalize::HandleOp(SDOperand Op) { 453 MVT::ValueType VT = Op.getValueType(); 454 switch (getTypeAction(VT)) { 455 default: assert(0 && "Bad type action!"); 456 case Legal: (void)LegalizeOp(Op); break; 457 case Promote: (void)PromoteOp(Op); break; 458 case Expand: 459 if (!MVT::isVector(VT)) { 460 // If this is an illegal scalar, expand it into its two component 461 // pieces. 462 SDOperand X, Y; 463 if (Op.getOpcode() == ISD::TargetConstant) 464 break; // Allow illegal target nodes. 465 ExpandOp(Op, X, Y); 466 } else if (MVT::getVectorNumElements(VT) == 1) { 467 // If this is an illegal single element vector, convert it to a 468 // scalar operation. 469 (void)ScalarizeVectorOp(Op); 470 } else { 471 // Otherwise, this is an illegal multiple element vector. 472 // Split it in half and legalize both parts. 473 SDOperand X, Y; 474 SplitVectorOp(Op, X, Y); 475 } 476 break; 477 } 478} 479 480/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 481/// a load from the constant pool. 482static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 483 SelectionDAG &DAG, TargetLowering &TLI) { 484 bool Extend = false; 485 486 // If a FP immediate is precise when represented as a float and if the 487 // target can do an extending load from float to double, we put it into 488 // the constant pool as a float, even if it's is statically typed as a 489 // double. 490 MVT::ValueType VT = CFP->getValueType(0); 491 bool isDouble = VT == MVT::f64; 492 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT), 493 CFP->getValueAPF()); 494 if (!UseCP) { 495 if (VT!=MVT::f64 && VT!=MVT::f32) 496 assert(0 && "Invalid type expansion"); 497 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(), 498 isDouble ? MVT::i64 : MVT::i32); 499 } 500 501 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) && 502 // Only do this if the target has a native EXTLOAD instruction from f32. 503 // Do not try to be clever about long doubles (so far) 504 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 505 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); 506 VT = MVT::f32; 507 Extend = true; 508 } 509 510 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 511 if (Extend) { 512 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 513 CPIdx, PseudoSourceValue::getConstantPool(), 514 0, MVT::f32); 515 } else { 516 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 517 PseudoSourceValue::getConstantPool(), 0); 518 } 519} 520 521 522/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 523/// operations. 524static 525SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 526 SelectionDAG &DAG, TargetLowering &TLI) { 527 MVT::ValueType VT = Node->getValueType(0); 528 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 529 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 530 "fcopysign expansion only supported for f32 and f64"); 531 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 532 533 // First get the sign bit of second operand. 534 SDOperand Mask1 = (SrcVT == MVT::f64) 535 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 536 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 537 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 538 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 539 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 540 // Shift right or sign-extend it if the two operands have different types. 541 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 542 if (SizeDiff > 0) { 543 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 544 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 545 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 546 } else if (SizeDiff < 0) 547 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 548 549 // Clear the sign bit of first operand. 550 SDOperand Mask2 = (VT == MVT::f64) 551 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 552 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 553 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 554 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 555 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 556 557 // Or the value with the sign bit. 558 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 559 return Result; 560} 561 562/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 563static 564SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 565 TargetLowering &TLI) { 566 SDOperand Chain = ST->getChain(); 567 SDOperand Ptr = ST->getBasePtr(); 568 SDOperand Val = ST->getValue(); 569 MVT::ValueType VT = Val.getValueType(); 570 int Alignment = ST->getAlignment(); 571 int SVOffset = ST->getSrcValueOffset(); 572 if (MVT::isFloatingPoint(ST->getMemoryVT())) { 573 // Expand to a bitconvert of the value to the integer type of the 574 // same size, then a (misaligned) int store. 575 MVT::ValueType intVT; 576 if (VT==MVT::f64) 577 intVT = MVT::i64; 578 else if (VT==MVT::f32) 579 intVT = MVT::i32; 580 else 581 assert(0 && "Unaligned load of unsupported floating point type"); 582 583 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 584 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 585 SVOffset, ST->isVolatile(), Alignment); 586 } 587 assert(MVT::isInteger(ST->getMemoryVT()) && 588 "Unaligned store of unknown type."); 589 // Get the half-size VT 590 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1; 591 int NumBits = MVT::getSizeInBits(NewStoredVT); 592 int IncrementSize = NumBits / 8; 593 594 // Divide the stored value in two parts. 595 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 596 SDOperand Lo = Val; 597 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 598 599 // Store the two parts 600 SDOperand Store1, Store2; 601 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 602 ST->getSrcValue(), SVOffset, NewStoredVT, 603 ST->isVolatile(), Alignment); 604 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 605 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 606 Alignment = MinAlign(Alignment, IncrementSize); 607 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 608 ST->getSrcValue(), SVOffset + IncrementSize, 609 NewStoredVT, ST->isVolatile(), Alignment); 610 611 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 612} 613 614/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 615static 616SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 617 TargetLowering &TLI) { 618 int SVOffset = LD->getSrcValueOffset(); 619 SDOperand Chain = LD->getChain(); 620 SDOperand Ptr = LD->getBasePtr(); 621 MVT::ValueType VT = LD->getValueType(0); 622 MVT::ValueType LoadedVT = LD->getMemoryVT(); 623 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) { 624 // Expand to a (misaligned) integer load of the same size, 625 // then bitconvert to floating point. 626 MVT::ValueType intVT; 627 if (LoadedVT == MVT::f64) 628 intVT = MVT::i64; 629 else if (LoadedVT == MVT::f32) 630 intVT = MVT::i32; 631 else 632 assert(0 && "Unaligned load of unsupported floating point type"); 633 634 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 635 SVOffset, LD->isVolatile(), 636 LD->getAlignment()); 637 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 638 if (LoadedVT != VT) 639 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 640 641 SDOperand Ops[] = { Result, Chain }; 642 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 643 Ops, 2); 644 } 645 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) && 646 "Unaligned load of unsupported type."); 647 648 // Compute the new VT that is half the size of the old one. We either have an 649 // integer MVT or we have a vector MVT. 650 unsigned NumBits = MVT::getSizeInBits(LoadedVT); 651 MVT::ValueType NewLoadedVT; 652 if (!MVT::isVector(LoadedVT)) { 653 NewLoadedVT = MVT::getIntegerType(NumBits/2); 654 } else { 655 // FIXME: This is not right for <1 x anything> it is also not right for 656 // non-power-of-two vectors. 657 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT), 658 MVT::getVectorNumElements(LoadedVT)/2); 659 } 660 NumBits >>= 1; 661 662 unsigned Alignment = LD->getAlignment(); 663 unsigned IncrementSize = NumBits / 8; 664 ISD::LoadExtType HiExtType = LD->getExtensionType(); 665 666 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 667 if (HiExtType == ISD::NON_EXTLOAD) 668 HiExtType = ISD::ZEXTLOAD; 669 670 // Load the value in two parts 671 SDOperand Lo, Hi; 672 if (TLI.isLittleEndian()) { 673 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 674 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 675 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 676 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 677 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 678 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 679 MinAlign(Alignment, IncrementSize)); 680 } else { 681 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 682 NewLoadedVT,LD->isVolatile(), Alignment); 683 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 684 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 685 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 686 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 687 MinAlign(Alignment, IncrementSize)); 688 } 689 690 // aggregate the two parts 691 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 692 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 693 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 694 695 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 696 Hi.getValue(1)); 697 698 SDOperand Ops[] = { Result, TF }; 699 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 700} 701 702/// UnrollVectorOp - We know that the given vector has a legal type, however 703/// the operation it performs is not legal and is an operation that we have 704/// no way of lowering. "Unroll" the vector, splitting out the scalars and 705/// operating on each element individually. 706SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { 707 MVT::ValueType VT = Op.getValueType(); 708 assert(isTypeLegal(VT) && 709 "Caller should expand or promote operands that are not legal!"); 710 assert(Op.Val->getNumValues() == 1 && 711 "Can't unroll a vector with multiple results!"); 712 unsigned NE = MVT::getVectorNumElements(VT); 713 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 714 715 SmallVector<SDOperand, 8> Scalars; 716 SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); 717 for (unsigned i = 0; i != NE; ++i) { 718 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 719 SDOperand Operand = Op.getOperand(j); 720 MVT::ValueType OperandVT = Operand.getValueType(); 721 if (MVT::isVector(OperandVT)) { 722 // A vector operand; extract a single element. 723 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT); 724 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 725 OperandEltVT, 726 Operand, 727 DAG.getConstant(i, MVT::i32)); 728 } else { 729 // A scalar operand; just use it as is. 730 Operands[j] = Operand; 731 } 732 } 733 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 734 &Operands[0], Operands.size())); 735 } 736 737 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 738} 739 740/// GetFPLibCall - Return the right libcall for the given floating point type. 741static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT, 742 RTLIB::Libcall Call_F32, 743 RTLIB::Libcall Call_F64, 744 RTLIB::Libcall Call_F80, 745 RTLIB::Libcall Call_PPCF128) { 746 return 747 VT == MVT::f32 ? Call_F32 : 748 VT == MVT::f64 ? Call_F64 : 749 VT == MVT::f80 ? Call_F80 : 750 VT == MVT::ppcf128 ? Call_PPCF128 : 751 RTLIB::UNKNOWN_LIBCALL; 752} 753 754/// LegalizeOp - We know that the specified value has a legal type, and 755/// that its operands are legal. Now ensure that the operation itself 756/// is legal, recursively ensuring that the operands' operations remain 757/// legal. 758SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 759 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 760 return Op; 761 762 assert(isTypeLegal(Op.getValueType()) && 763 "Caller should expand or promote operands that are not legal!"); 764 SDNode *Node = Op.Val; 765 766 // If this operation defines any values that cannot be represented in a 767 // register on this target, make sure to expand or promote them. 768 if (Node->getNumValues() > 1) { 769 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 770 if (getTypeAction(Node->getValueType(i)) != Legal) { 771 HandleOp(Op.getValue(i)); 772 assert(LegalizedNodes.count(Op) && 773 "Handling didn't add legal operands!"); 774 return LegalizedNodes[Op]; 775 } 776 } 777 778 // Note that LegalizeOp may be reentered even from single-use nodes, which 779 // means that we always must cache transformed nodes. 780 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 781 if (I != LegalizedNodes.end()) return I->second; 782 783 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 784 SDOperand Result = Op; 785 bool isCustom = false; 786 787 switch (Node->getOpcode()) { 788 case ISD::FrameIndex: 789 case ISD::EntryToken: 790 case ISD::Register: 791 case ISD::BasicBlock: 792 case ISD::TargetFrameIndex: 793 case ISD::TargetJumpTable: 794 case ISD::TargetConstant: 795 case ISD::TargetConstantFP: 796 case ISD::TargetConstantPool: 797 case ISD::TargetGlobalAddress: 798 case ISD::TargetGlobalTLSAddress: 799 case ISD::TargetExternalSymbol: 800 case ISD::VALUETYPE: 801 case ISD::SRCVALUE: 802 case ISD::MEMOPERAND: 803 case ISD::STRING: 804 case ISD::CONDCODE: 805 // Primitives must all be legal. 806 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 807 "This must be legal!"); 808 break; 809 default: 810 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 811 // If this is a target node, legalize it by legalizing the operands then 812 // passing it through. 813 SmallVector<SDOperand, 8> Ops; 814 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 815 Ops.push_back(LegalizeOp(Node->getOperand(i))); 816 817 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 818 819 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 820 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 821 return Result.getValue(Op.ResNo); 822 } 823 // Otherwise this is an unhandled builtin node. splat. 824#ifndef NDEBUG 825 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 826#endif 827 assert(0 && "Do not know how to legalize this operator!"); 828 abort(); 829 case ISD::GLOBAL_OFFSET_TABLE: 830 case ISD::GlobalAddress: 831 case ISD::GlobalTLSAddress: 832 case ISD::ExternalSymbol: 833 case ISD::ConstantPool: 834 case ISD::JumpTable: // Nothing to do. 835 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 836 default: assert(0 && "This action is not supported yet!"); 837 case TargetLowering::Custom: 838 Tmp1 = TLI.LowerOperation(Op, DAG); 839 if (Tmp1.Val) Result = Tmp1; 840 // FALLTHROUGH if the target doesn't want to lower this op after all. 841 case TargetLowering::Legal: 842 break; 843 } 844 break; 845 case ISD::FRAMEADDR: 846 case ISD::RETURNADDR: 847 // The only option for these nodes is to custom lower them. If the target 848 // does not custom lower them, then return zero. 849 Tmp1 = TLI.LowerOperation(Op, DAG); 850 if (Tmp1.Val) 851 Result = Tmp1; 852 else 853 Result = DAG.getConstant(0, TLI.getPointerTy()); 854 break; 855 case ISD::FRAME_TO_ARGS_OFFSET: { 856 MVT::ValueType VT = Node->getValueType(0); 857 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 858 default: assert(0 && "This action is not supported yet!"); 859 case TargetLowering::Custom: 860 Result = TLI.LowerOperation(Op, DAG); 861 if (Result.Val) break; 862 // Fall Thru 863 case TargetLowering::Legal: 864 Result = DAG.getConstant(0, VT); 865 break; 866 } 867 } 868 break; 869 case ISD::EXCEPTIONADDR: { 870 Tmp1 = LegalizeOp(Node->getOperand(0)); 871 MVT::ValueType VT = Node->getValueType(0); 872 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 873 default: assert(0 && "This action is not supported yet!"); 874 case TargetLowering::Expand: { 875 unsigned Reg = TLI.getExceptionAddressRegister(); 876 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 877 } 878 break; 879 case TargetLowering::Custom: 880 Result = TLI.LowerOperation(Op, DAG); 881 if (Result.Val) break; 882 // Fall Thru 883 case TargetLowering::Legal: { 884 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 885 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 886 Ops, 2); 887 break; 888 } 889 } 890 } 891 if (Result.Val->getNumValues() == 1) break; 892 893 assert(Result.Val->getNumValues() == 2 && 894 "Cannot return more than two values!"); 895 896 // Since we produced two values, make sure to remember that we 897 // legalized both of them. 898 Tmp1 = LegalizeOp(Result); 899 Tmp2 = LegalizeOp(Result.getValue(1)); 900 AddLegalizedOperand(Op.getValue(0), Tmp1); 901 AddLegalizedOperand(Op.getValue(1), Tmp2); 902 return Op.ResNo ? Tmp2 : Tmp1; 903 case ISD::EHSELECTION: { 904 Tmp1 = LegalizeOp(Node->getOperand(0)); 905 Tmp2 = LegalizeOp(Node->getOperand(1)); 906 MVT::ValueType VT = Node->getValueType(0); 907 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 908 default: assert(0 && "This action is not supported yet!"); 909 case TargetLowering::Expand: { 910 unsigned Reg = TLI.getExceptionSelectorRegister(); 911 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 912 } 913 break; 914 case TargetLowering::Custom: 915 Result = TLI.LowerOperation(Op, DAG); 916 if (Result.Val) break; 917 // Fall Thru 918 case TargetLowering::Legal: { 919 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 920 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 921 Ops, 2); 922 break; 923 } 924 } 925 } 926 if (Result.Val->getNumValues() == 1) break; 927 928 assert(Result.Val->getNumValues() == 2 && 929 "Cannot return more than two values!"); 930 931 // Since we produced two values, make sure to remember that we 932 // legalized both of them. 933 Tmp1 = LegalizeOp(Result); 934 Tmp2 = LegalizeOp(Result.getValue(1)); 935 AddLegalizedOperand(Op.getValue(0), Tmp1); 936 AddLegalizedOperand(Op.getValue(1), Tmp2); 937 return Op.ResNo ? Tmp2 : Tmp1; 938 case ISD::EH_RETURN: { 939 MVT::ValueType VT = Node->getValueType(0); 940 // The only "good" option for this node is to custom lower it. 941 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 942 default: assert(0 && "This action is not supported at all!"); 943 case TargetLowering::Custom: 944 Result = TLI.LowerOperation(Op, DAG); 945 if (Result.Val) break; 946 // Fall Thru 947 case TargetLowering::Legal: 948 // Target does not know, how to lower this, lower to noop 949 Result = LegalizeOp(Node->getOperand(0)); 950 break; 951 } 952 } 953 break; 954 case ISD::AssertSext: 955 case ISD::AssertZext: 956 Tmp1 = LegalizeOp(Node->getOperand(0)); 957 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 958 break; 959 case ISD::MERGE_VALUES: 960 // Legalize eliminates MERGE_VALUES nodes. 961 Result = Node->getOperand(Op.ResNo); 962 break; 963 case ISD::CopyFromReg: 964 Tmp1 = LegalizeOp(Node->getOperand(0)); 965 Result = Op.getValue(0); 966 if (Node->getNumValues() == 2) { 967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 968 } else { 969 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 970 if (Node->getNumOperands() == 3) { 971 Tmp2 = LegalizeOp(Node->getOperand(2)); 972 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 973 } else { 974 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 975 } 976 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 977 } 978 // Since CopyFromReg produces two values, make sure to remember that we 979 // legalized both of them. 980 AddLegalizedOperand(Op.getValue(0), Result); 981 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 982 return Result.getValue(Op.ResNo); 983 case ISD::UNDEF: { 984 MVT::ValueType VT = Op.getValueType(); 985 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 986 default: assert(0 && "This action is not supported yet!"); 987 case TargetLowering::Expand: 988 if (MVT::isInteger(VT)) 989 Result = DAG.getConstant(0, VT); 990 else if (MVT::isFloatingPoint(VT)) 991 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)), 992 VT); 993 else 994 assert(0 && "Unknown value type!"); 995 break; 996 case TargetLowering::Legal: 997 break; 998 } 999 break; 1000 } 1001 1002 case ISD::INTRINSIC_W_CHAIN: 1003 case ISD::INTRINSIC_WO_CHAIN: 1004 case ISD::INTRINSIC_VOID: { 1005 SmallVector<SDOperand, 8> Ops; 1006 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1007 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1008 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1009 1010 // Allow the target to custom lower its intrinsics if it wants to. 1011 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1012 TargetLowering::Custom) { 1013 Tmp3 = TLI.LowerOperation(Result, DAG); 1014 if (Tmp3.Val) Result = Tmp3; 1015 } 1016 1017 if (Result.Val->getNumValues() == 1) break; 1018 1019 // Must have return value and chain result. 1020 assert(Result.Val->getNumValues() == 2 && 1021 "Cannot return more than two values!"); 1022 1023 // Since loads produce two values, make sure to remember that we 1024 // legalized both of them. 1025 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1026 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1027 return Result.getValue(Op.ResNo); 1028 } 1029 1030 case ISD::LOCATION: 1031 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 1032 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1033 1034 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 1035 case TargetLowering::Promote: 1036 default: assert(0 && "This action is not supported yet!"); 1037 case TargetLowering::Expand: { 1038 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1039 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1040 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 1041 1042 if (MMI && (useDEBUG_LOC || useLABEL)) { 1043 const std::string &FName = 1044 cast<StringSDNode>(Node->getOperand(3))->getValue(); 1045 const std::string &DirName = 1046 cast<StringSDNode>(Node->getOperand(4))->getValue(); 1047 unsigned SrcFile = MMI->RecordSource(DirName, FName); 1048 1049 SmallVector<SDOperand, 8> Ops; 1050 Ops.push_back(Tmp1); // chain 1051 SDOperand LineOp = Node->getOperand(1); 1052 SDOperand ColOp = Node->getOperand(2); 1053 1054 if (useDEBUG_LOC) { 1055 Ops.push_back(LineOp); // line # 1056 Ops.push_back(ColOp); // col # 1057 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 1058 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 1059 } else { 1060 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 1061 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 1062 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); 1063 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 1064 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label 1065 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size()); 1066 } 1067 } else { 1068 Result = Tmp1; // chain 1069 } 1070 break; 1071 } 1072 case TargetLowering::Legal: 1073 if (Tmp1 != Node->getOperand(0) || 1074 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 1075 SmallVector<SDOperand, 8> Ops; 1076 Ops.push_back(Tmp1); 1077 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 1078 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1079 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1080 } else { 1081 // Otherwise promote them. 1082 Ops.push_back(PromoteOp(Node->getOperand(1))); 1083 Ops.push_back(PromoteOp(Node->getOperand(2))); 1084 } 1085 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1086 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1087 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1088 } 1089 break; 1090 } 1091 break; 1092 1093 case ISD::DECLARE: 1094 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1095 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1096 default: assert(0 && "This action is not supported yet!"); 1097 case TargetLowering::Legal: 1098 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1099 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1100 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1102 break; 1103 } 1104 break; 1105 1106 case ISD::DEBUG_LOC: 1107 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1108 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1109 default: assert(0 && "This action is not supported yet!"); 1110 case TargetLowering::Legal: 1111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1112 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1113 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1114 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1116 break; 1117 } 1118 break; 1119 1120 case ISD::LABEL: 1121 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!"); 1122 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 1123 default: assert(0 && "This action is not supported yet!"); 1124 case TargetLowering::Legal: 1125 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1126 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 1127 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand. 1128 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1129 break; 1130 case TargetLowering::Expand: 1131 Result = LegalizeOp(Node->getOperand(0)); 1132 break; 1133 } 1134 break; 1135 1136 case ISD::MEMBARRIER: { 1137 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1138 SDOperand Ops[6]; 1139 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1140 for (int x = 1; x < 6; ++x) 1141 Ops[x] = PromoteOp(Node->getOperand(x)); 1142 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1143 break; 1144 } 1145 1146 case ISD::Constant: { 1147 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1148 unsigned opAction = 1149 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1150 1151 // We know we don't need to expand constants here, constants only have one 1152 // value and we check that it is fine above. 1153 1154 if (opAction == TargetLowering::Custom) { 1155 Tmp1 = TLI.LowerOperation(Result, DAG); 1156 if (Tmp1.Val) 1157 Result = Tmp1; 1158 } 1159 break; 1160 } 1161 case ISD::ConstantFP: { 1162 // Spill FP immediates to the constant pool if the target cannot directly 1163 // codegen them. Targets often have some immediate values that can be 1164 // efficiently generated into an FP register without a load. We explicitly 1165 // leave these constants as ConstantFP nodes for the target to deal with. 1166 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1167 1168 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1169 default: assert(0 && "This action is not supported yet!"); 1170 case TargetLowering::Legal: 1171 break; 1172 case TargetLowering::Custom: 1173 Tmp3 = TLI.LowerOperation(Result, DAG); 1174 if (Tmp3.Val) { 1175 Result = Tmp3; 1176 break; 1177 } 1178 // FALLTHROUGH 1179 case TargetLowering::Expand: { 1180 // Check to see if this FP immediate is already legal. 1181 bool isLegal = false; 1182 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1183 E = TLI.legal_fpimm_end(); I != E; ++I) { 1184 if (CFP->isExactlyValue(*I)) { 1185 isLegal = true; 1186 break; 1187 } 1188 } 1189 // If this is a legal constant, turn it into a TargetConstantFP node. 1190 if (isLegal) 1191 break; 1192 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1193 } 1194 } 1195 break; 1196 } 1197 case ISD::TokenFactor: 1198 if (Node->getNumOperands() == 2) { 1199 Tmp1 = LegalizeOp(Node->getOperand(0)); 1200 Tmp2 = LegalizeOp(Node->getOperand(1)); 1201 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1202 } else if (Node->getNumOperands() == 3) { 1203 Tmp1 = LegalizeOp(Node->getOperand(0)); 1204 Tmp2 = LegalizeOp(Node->getOperand(1)); 1205 Tmp3 = LegalizeOp(Node->getOperand(2)); 1206 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1207 } else { 1208 SmallVector<SDOperand, 8> Ops; 1209 // Legalize the operands. 1210 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1211 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1212 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1213 } 1214 break; 1215 1216 case ISD::FORMAL_ARGUMENTS: 1217 case ISD::CALL: 1218 // The only option for this is to custom lower it. 1219 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1220 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1221 1222 // The number of incoming and outgoing values should match; unless the final 1223 // outgoing value is a flag. 1224 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || 1225 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && 1226 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == 1227 MVT::Flag)) && 1228 "Lowering call/formal_arguments produced unexpected # results!"); 1229 1230 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1231 // remember that we legalized all of them, so it doesn't get relegalized. 1232 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1233 if (Tmp3.Val->getValueType(i) == MVT::Flag) 1234 continue; 1235 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1236 if (Op.ResNo == i) 1237 Tmp2 = Tmp1; 1238 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1239 } 1240 return Tmp2; 1241 case ISD::EXTRACT_SUBREG: { 1242 Tmp1 = LegalizeOp(Node->getOperand(0)); 1243 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1244 assert(idx && "Operand must be a constant"); 1245 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1246 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1247 } 1248 break; 1249 case ISD::INSERT_SUBREG: { 1250 Tmp1 = LegalizeOp(Node->getOperand(0)); 1251 Tmp2 = LegalizeOp(Node->getOperand(1)); 1252 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1253 assert(idx && "Operand must be a constant"); 1254 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1255 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1256 } 1257 break; 1258 case ISD::BUILD_VECTOR: 1259 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1260 default: assert(0 && "This action is not supported yet!"); 1261 case TargetLowering::Custom: 1262 Tmp3 = TLI.LowerOperation(Result, DAG); 1263 if (Tmp3.Val) { 1264 Result = Tmp3; 1265 break; 1266 } 1267 // FALLTHROUGH 1268 case TargetLowering::Expand: 1269 Result = ExpandBUILD_VECTOR(Result.Val); 1270 break; 1271 } 1272 break; 1273 case ISD::INSERT_VECTOR_ELT: 1274 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1275 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1276 1277 // The type of the value to insert may not be legal, even though the vector 1278 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1279 // here. 1280 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1281 default: assert(0 && "Cannot expand insert element operand"); 1282 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1283 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1284 } 1285 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1286 1287 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1288 Node->getValueType(0))) { 1289 default: assert(0 && "This action is not supported yet!"); 1290 case TargetLowering::Legal: 1291 break; 1292 case TargetLowering::Custom: 1293 Tmp4 = TLI.LowerOperation(Result, DAG); 1294 if (Tmp4.Val) { 1295 Result = Tmp4; 1296 break; 1297 } 1298 // FALLTHROUGH 1299 case TargetLowering::Expand: { 1300 // If the insert index is a constant, codegen this as a scalar_to_vector, 1301 // then a shuffle that inserts it into the right position in the vector. 1302 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1303 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1304 // match the element type of the vector being created. 1305 if (Tmp2.getValueType() == 1306 MVT::getVectorElementType(Op.getValueType())) { 1307 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1308 Tmp1.getValueType(), Tmp2); 1309 1310 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1311 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1312 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); 1313 1314 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1315 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1316 // elt 0 of the RHS. 1317 SmallVector<SDOperand, 8> ShufOps; 1318 for (unsigned i = 0; i != NumElts; ++i) { 1319 if (i != InsertPos->getValue()) 1320 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1321 else 1322 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1323 } 1324 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1325 &ShufOps[0], ShufOps.size()); 1326 1327 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1328 Tmp1, ScVec, ShufMask); 1329 Result = LegalizeOp(Result); 1330 break; 1331 } 1332 } 1333 1334 // If the target doesn't support this, we have to spill the input vector 1335 // to a temporary stack slot, update the element, then reload it. This is 1336 // badness. We could also load the value into a vector register (either 1337 // with a "move to register" or "extload into register" instruction, then 1338 // permute it into place, if the idx is a constant and if the idx is 1339 // supported by the target. 1340 MVT::ValueType VT = Tmp1.getValueType(); 1341 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1342 MVT::ValueType IdxVT = Tmp3.getValueType(); 1343 MVT::ValueType PtrVT = TLI.getPointerTy(); 1344 SDOperand StackPtr = DAG.CreateStackTemporary(VT); 1345 1346 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val); 1347 int SPFI = StackPtrFI->getIndex(); 1348 1349 // Store the vector. 1350 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, 1351 PseudoSourceValue::getFixedStack(), 1352 SPFI); 1353 1354 // Truncate or zero extend offset to target pointer type. 1355 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1356 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 1357 // Add the offset to the index. 1358 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 1359 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 1360 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 1361 // Store the scalar value. 1362 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, 1363 PseudoSourceValue::getFixedStack(), SPFI, EltVT); 1364 // Load the updated vector. 1365 Result = DAG.getLoad(VT, Ch, StackPtr, 1366 PseudoSourceValue::getFixedStack(), SPFI); 1367 break; 1368 } 1369 } 1370 break; 1371 case ISD::SCALAR_TO_VECTOR: 1372 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1373 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1374 break; 1375 } 1376 1377 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1378 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1379 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1380 Node->getValueType(0))) { 1381 default: assert(0 && "This action is not supported yet!"); 1382 case TargetLowering::Legal: 1383 break; 1384 case TargetLowering::Custom: 1385 Tmp3 = TLI.LowerOperation(Result, DAG); 1386 if (Tmp3.Val) { 1387 Result = Tmp3; 1388 break; 1389 } 1390 // FALLTHROUGH 1391 case TargetLowering::Expand: 1392 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1393 break; 1394 } 1395 break; 1396 case ISD::VECTOR_SHUFFLE: 1397 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1398 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1399 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1400 1401 // Allow targets to custom lower the SHUFFLEs they support. 1402 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1403 default: assert(0 && "Unknown operation action!"); 1404 case TargetLowering::Legal: 1405 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1406 "vector shuffle should not be created if not legal!"); 1407 break; 1408 case TargetLowering::Custom: 1409 Tmp3 = TLI.LowerOperation(Result, DAG); 1410 if (Tmp3.Val) { 1411 Result = Tmp3; 1412 break; 1413 } 1414 // FALLTHROUGH 1415 case TargetLowering::Expand: { 1416 MVT::ValueType VT = Node->getValueType(0); 1417 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1418 MVT::ValueType PtrVT = TLI.getPointerTy(); 1419 SDOperand Mask = Node->getOperand(2); 1420 unsigned NumElems = Mask.getNumOperands(); 1421 SmallVector<SDOperand,8> Ops; 1422 for (unsigned i = 0; i != NumElems; ++i) { 1423 SDOperand Arg = Mask.getOperand(i); 1424 if (Arg.getOpcode() == ISD::UNDEF) { 1425 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1426 } else { 1427 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1428 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1429 if (Idx < NumElems) 1430 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1431 DAG.getConstant(Idx, PtrVT))); 1432 else 1433 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1434 DAG.getConstant(Idx - NumElems, PtrVT))); 1435 } 1436 } 1437 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1438 break; 1439 } 1440 case TargetLowering::Promote: { 1441 // Change base type to a different vector type. 1442 MVT::ValueType OVT = Node->getValueType(0); 1443 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1444 1445 // Cast the two input vectors. 1446 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1447 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1448 1449 // Convert the shuffle mask to the right # elements. 1450 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1451 assert(Tmp3.Val && "Shuffle not legal?"); 1452 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1453 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1454 break; 1455 } 1456 } 1457 break; 1458 1459 case ISD::EXTRACT_VECTOR_ELT: 1460 Tmp1 = Node->getOperand(0); 1461 Tmp2 = LegalizeOp(Node->getOperand(1)); 1462 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1463 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1464 break; 1465 1466 case ISD::EXTRACT_SUBVECTOR: 1467 Tmp1 = Node->getOperand(0); 1468 Tmp2 = LegalizeOp(Node->getOperand(1)); 1469 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1470 Result = ExpandEXTRACT_SUBVECTOR(Result); 1471 break; 1472 1473 case ISD::CALLSEQ_START: { 1474 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1475 1476 // Recursively Legalize all of the inputs of the call end that do not lead 1477 // to this call start. This ensures that any libcalls that need be inserted 1478 // are inserted *before* the CALLSEQ_START. 1479 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1480 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1481 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1482 NodesLeadingTo); 1483 } 1484 1485 // Now that we legalized all of the inputs (which may have inserted 1486 // libcalls) create the new CALLSEQ_START node. 1487 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1488 1489 // Merge in the last call, to ensure that this call start after the last 1490 // call ended. 1491 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1492 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1493 Tmp1 = LegalizeOp(Tmp1); 1494 } 1495 1496 // Do not try to legalize the target-specific arguments (#1+). 1497 if (Tmp1 != Node->getOperand(0)) { 1498 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1499 Ops[0] = Tmp1; 1500 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1501 } 1502 1503 // Remember that the CALLSEQ_START is legalized. 1504 AddLegalizedOperand(Op.getValue(0), Result); 1505 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1506 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1507 1508 // Now that the callseq_start and all of the non-call nodes above this call 1509 // sequence have been legalized, legalize the call itself. During this 1510 // process, no libcalls can/will be inserted, guaranteeing that no calls 1511 // can overlap. 1512 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1513 SDOperand InCallSEQ = LastCALLSEQ_END; 1514 // Note that we are selecting this call! 1515 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1516 IsLegalizingCall = true; 1517 1518 // Legalize the call, starting from the CALLSEQ_END. 1519 LegalizeOp(LastCALLSEQ_END); 1520 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1521 return Result; 1522 } 1523 case ISD::CALLSEQ_END: 1524 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1525 // will cause this node to be legalized as well as handling libcalls right. 1526 if (LastCALLSEQ_END.Val != Node) { 1527 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1528 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1529 assert(I != LegalizedNodes.end() && 1530 "Legalizing the call start should have legalized this node!"); 1531 return I->second; 1532 } 1533 1534 // Otherwise, the call start has been legalized and everything is going 1535 // according to plan. Just legalize ourselves normally here. 1536 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1537 // Do not try to legalize the target-specific arguments (#1+), except for 1538 // an optional flag input. 1539 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1540 if (Tmp1 != Node->getOperand(0)) { 1541 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1542 Ops[0] = Tmp1; 1543 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1544 } 1545 } else { 1546 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1547 if (Tmp1 != Node->getOperand(0) || 1548 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1549 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1550 Ops[0] = Tmp1; 1551 Ops.back() = Tmp2; 1552 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1553 } 1554 } 1555 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1556 // This finishes up call legalization. 1557 IsLegalizingCall = false; 1558 1559 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1560 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1561 if (Node->getNumValues() == 2) 1562 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1563 return Result.getValue(Op.ResNo); 1564 case ISD::DYNAMIC_STACKALLOC: { 1565 MVT::ValueType VT = Node->getValueType(0); 1566 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1567 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1568 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1569 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1570 1571 Tmp1 = Result.getValue(0); 1572 Tmp2 = Result.getValue(1); 1573 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1574 default: assert(0 && "This action is not supported yet!"); 1575 case TargetLowering::Expand: { 1576 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1577 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1578 " not tell us which reg is the stack pointer!"); 1579 SDOperand Chain = Tmp1.getOperand(0); 1580 1581 // Chain the dynamic stack allocation so that it doesn't modify the stack 1582 // pointer when other instructions are using the stack. 1583 Chain = DAG.getCALLSEQ_START(Chain, 1584 DAG.getConstant(0, TLI.getPointerTy())); 1585 1586 SDOperand Size = Tmp2.getOperand(1); 1587 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1588 Chain = SP.getValue(1); 1589 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1590 unsigned StackAlign = 1591 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1592 if (Align > StackAlign) 1593 SP = DAG.getNode(ISD::AND, VT, SP, 1594 DAG.getConstant(-(uint64_t)Align, VT)); 1595 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1596 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1597 1598 Tmp2 = 1599 DAG.getCALLSEQ_END(Chain, 1600 DAG.getConstant(0, TLI.getPointerTy()), 1601 DAG.getConstant(0, TLI.getPointerTy()), 1602 SDOperand()); 1603 1604 Tmp1 = LegalizeOp(Tmp1); 1605 Tmp2 = LegalizeOp(Tmp2); 1606 break; 1607 } 1608 case TargetLowering::Custom: 1609 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1610 if (Tmp3.Val) { 1611 Tmp1 = LegalizeOp(Tmp3); 1612 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1613 } 1614 break; 1615 case TargetLowering::Legal: 1616 break; 1617 } 1618 // Since this op produce two values, make sure to remember that we 1619 // legalized both of them. 1620 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1621 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1622 return Op.ResNo ? Tmp2 : Tmp1; 1623 } 1624 case ISD::INLINEASM: { 1625 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1626 bool Changed = false; 1627 // Legalize all of the operands of the inline asm, in case they are nodes 1628 // that need to be expanded or something. Note we skip the asm string and 1629 // all of the TargetConstant flags. 1630 SDOperand Op = LegalizeOp(Ops[0]); 1631 Changed = Op != Ops[0]; 1632 Ops[0] = Op; 1633 1634 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1635 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1636 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1637 for (++i; NumVals; ++i, --NumVals) { 1638 SDOperand Op = LegalizeOp(Ops[i]); 1639 if (Op != Ops[i]) { 1640 Changed = true; 1641 Ops[i] = Op; 1642 } 1643 } 1644 } 1645 1646 if (HasInFlag) { 1647 Op = LegalizeOp(Ops.back()); 1648 Changed |= Op != Ops.back(); 1649 Ops.back() = Op; 1650 } 1651 1652 if (Changed) 1653 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1654 1655 // INLINE asm returns a chain and flag, make sure to add both to the map. 1656 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1657 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1658 return Result.getValue(Op.ResNo); 1659 } 1660 case ISD::BR: 1661 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1662 // Ensure that libcalls are emitted before a branch. 1663 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1664 Tmp1 = LegalizeOp(Tmp1); 1665 LastCALLSEQ_END = DAG.getEntryNode(); 1666 1667 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1668 break; 1669 case ISD::BRIND: 1670 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1671 // Ensure that libcalls are emitted before a branch. 1672 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1673 Tmp1 = LegalizeOp(Tmp1); 1674 LastCALLSEQ_END = DAG.getEntryNode(); 1675 1676 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1677 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1678 case Legal: 1679 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1680 break; 1681 } 1682 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1683 break; 1684 case ISD::BR_JT: 1685 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1686 // Ensure that libcalls are emitted before a branch. 1687 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1688 Tmp1 = LegalizeOp(Tmp1); 1689 LastCALLSEQ_END = DAG.getEntryNode(); 1690 1691 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1692 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1693 1694 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1695 default: assert(0 && "This action is not supported yet!"); 1696 case TargetLowering::Legal: break; 1697 case TargetLowering::Custom: 1698 Tmp1 = TLI.LowerOperation(Result, DAG); 1699 if (Tmp1.Val) Result = Tmp1; 1700 break; 1701 case TargetLowering::Expand: { 1702 SDOperand Chain = Result.getOperand(0); 1703 SDOperand Table = Result.getOperand(1); 1704 SDOperand Index = Result.getOperand(2); 1705 1706 MVT::ValueType PTy = TLI.getPointerTy(); 1707 MachineFunction &MF = DAG.getMachineFunction(); 1708 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1709 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1710 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1711 1712 SDOperand LD; 1713 switch (EntrySize) { 1714 default: assert(0 && "Size of jump table not supported yet."); break; 1715 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, 1716 PseudoSourceValue::getJumpTable(), 0); break; 1717 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, 1718 PseudoSourceValue::getJumpTable(), 0); break; 1719 } 1720 1721 Addr = LD; 1722 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1723 // For PIC, the sequence is: 1724 // BRIND(load(Jumptable + index) + RelocBase) 1725 // RelocBase can be JumpTable, GOT or some sort of global base. 1726 if (PTy != MVT::i32) 1727 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1728 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1729 TLI.getPICJumpTableRelocBase(Table, DAG)); 1730 } 1731 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1732 } 1733 } 1734 break; 1735 case ISD::BRCOND: 1736 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1737 // Ensure that libcalls are emitted before a return. 1738 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1739 Tmp1 = LegalizeOp(Tmp1); 1740 LastCALLSEQ_END = DAG.getEntryNode(); 1741 1742 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1743 case Expand: assert(0 && "It's impossible to expand bools"); 1744 case Legal: 1745 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1746 break; 1747 case Promote: 1748 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1749 1750 // The top bits of the promoted condition are not necessarily zero, ensure 1751 // that the value is properly zero extended. 1752 if (!DAG.MaskedValueIsZero(Tmp2, 1753 MVT::getIntVTBitMask(Tmp2.getValueType())^1)) 1754 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1755 break; 1756 } 1757 1758 // Basic block destination (Op#2) is always legal. 1759 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1760 1761 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1762 default: assert(0 && "This action is not supported yet!"); 1763 case TargetLowering::Legal: break; 1764 case TargetLowering::Custom: 1765 Tmp1 = TLI.LowerOperation(Result, DAG); 1766 if (Tmp1.Val) Result = Tmp1; 1767 break; 1768 case TargetLowering::Expand: 1769 // Expand brcond's setcc into its constituent parts and create a BR_CC 1770 // Node. 1771 if (Tmp2.getOpcode() == ISD::SETCC) { 1772 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1773 Tmp2.getOperand(0), Tmp2.getOperand(1), 1774 Node->getOperand(2)); 1775 } else { 1776 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1777 DAG.getCondCode(ISD::SETNE), Tmp2, 1778 DAG.getConstant(0, Tmp2.getValueType()), 1779 Node->getOperand(2)); 1780 } 1781 break; 1782 } 1783 break; 1784 case ISD::BR_CC: 1785 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1786 // Ensure that libcalls are emitted before a branch. 1787 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1788 Tmp1 = LegalizeOp(Tmp1); 1789 Tmp2 = Node->getOperand(2); // LHS 1790 Tmp3 = Node->getOperand(3); // RHS 1791 Tmp4 = Node->getOperand(1); // CC 1792 1793 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1794 LastCALLSEQ_END = DAG.getEntryNode(); 1795 1796 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1797 // the LHS is a legal SETCC itself. In this case, we need to compare 1798 // the result against zero to select between true and false values. 1799 if (Tmp3.Val == 0) { 1800 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1801 Tmp4 = DAG.getCondCode(ISD::SETNE); 1802 } 1803 1804 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1805 Node->getOperand(4)); 1806 1807 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1808 default: assert(0 && "Unexpected action for BR_CC!"); 1809 case TargetLowering::Legal: break; 1810 case TargetLowering::Custom: 1811 Tmp4 = TLI.LowerOperation(Result, DAG); 1812 if (Tmp4.Val) Result = Tmp4; 1813 break; 1814 } 1815 break; 1816 case ISD::LOAD: { 1817 LoadSDNode *LD = cast<LoadSDNode>(Node); 1818 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1819 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1820 1821 ISD::LoadExtType ExtType = LD->getExtensionType(); 1822 if (ExtType == ISD::NON_EXTLOAD) { 1823 MVT::ValueType VT = Node->getValueType(0); 1824 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1825 Tmp3 = Result.getValue(0); 1826 Tmp4 = Result.getValue(1); 1827 1828 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1829 default: assert(0 && "This action is not supported yet!"); 1830 case TargetLowering::Legal: 1831 // If this is an unaligned load and the target doesn't support it, 1832 // expand it. 1833 if (!TLI.allowsUnalignedMemoryAccesses()) { 1834 unsigned ABIAlignment = TLI.getTargetData()-> 1835 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT())); 1836 if (LD->getAlignment() < ABIAlignment){ 1837 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1838 TLI); 1839 Tmp3 = Result.getOperand(0); 1840 Tmp4 = Result.getOperand(1); 1841 Tmp3 = LegalizeOp(Tmp3); 1842 Tmp4 = LegalizeOp(Tmp4); 1843 } 1844 } 1845 break; 1846 case TargetLowering::Custom: 1847 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1848 if (Tmp1.Val) { 1849 Tmp3 = LegalizeOp(Tmp1); 1850 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1851 } 1852 break; 1853 case TargetLowering::Promote: { 1854 // Only promote a load of vector type to another. 1855 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1856 // Change base type to a different vector type. 1857 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1858 1859 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1860 LD->getSrcValueOffset(), 1861 LD->isVolatile(), LD->getAlignment()); 1862 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1863 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1864 break; 1865 } 1866 } 1867 // Since loads produce two values, make sure to remember that we 1868 // legalized both of them. 1869 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1870 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1871 return Op.ResNo ? Tmp4 : Tmp3; 1872 } else { 1873 MVT::ValueType SrcVT = LD->getMemoryVT(); 1874 unsigned SrcWidth = MVT::getSizeInBits(SrcVT); 1875 int SVOffset = LD->getSrcValueOffset(); 1876 unsigned Alignment = LD->getAlignment(); 1877 bool isVolatile = LD->isVolatile(); 1878 1879 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) && 1880 // Some targets pretend to have an i1 loading operation, and actually 1881 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1882 // bits are guaranteed to be zero; it helps the optimizers understand 1883 // that these bits are zero. It is also useful for EXTLOAD, since it 1884 // tells the optimizers that those bits are undefined. It would be 1885 // nice to have an effective generic way of getting these benefits... 1886 // Until such a way is found, don't insist on promoting i1 here. 1887 (SrcVT != MVT::i1 || 1888 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1889 // Promote to a byte-sized load if not loading an integral number of 1890 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1891 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT); 1892 MVT::ValueType NVT = MVT::getIntegerType(NewWidth); 1893 SDOperand Ch; 1894 1895 // The extra bits are guaranteed to be zero, since we stored them that 1896 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1897 1898 ISD::LoadExtType NewExtType = 1899 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1900 1901 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), 1902 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1903 NVT, isVolatile, Alignment); 1904 1905 Ch = Result.getValue(1); // The chain. 1906 1907 if (ExtType == ISD::SEXTLOAD) 1908 // Having the top bits zero doesn't help when sign extending. 1909 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1910 Result, DAG.getValueType(SrcVT)); 1911 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1912 // All the top bits are guaranteed to be zero - inform the optimizers. 1913 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, 1914 DAG.getValueType(SrcVT)); 1915 1916 Tmp1 = LegalizeOp(Result); 1917 Tmp2 = LegalizeOp(Ch); 1918 } else if (SrcWidth & (SrcWidth - 1)) { 1919 // If not loading a power-of-2 number of bits, expand as two loads. 1920 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) && 1921 "Unsupported extload!"); 1922 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1923 assert(RoundWidth < SrcWidth); 1924 unsigned ExtraWidth = SrcWidth - RoundWidth; 1925 assert(ExtraWidth < RoundWidth); 1926 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1927 "Load size not an integral number of bytes!"); 1928 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth); 1929 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth); 1930 SDOperand Lo, Hi, Ch; 1931 unsigned IncrementSize; 1932 1933 if (TLI.isLittleEndian()) { 1934 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1935 // Load the bottom RoundWidth bits. 1936 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 1937 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1938 Alignment); 1939 1940 // Load the remaining ExtraWidth bits. 1941 IncrementSize = RoundWidth / 8; 1942 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1943 DAG.getIntPtrConstant(IncrementSize)); 1944 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1945 LD->getSrcValue(), SVOffset + IncrementSize, 1946 ExtraVT, isVolatile, 1947 MinAlign(Alignment, IncrementSize)); 1948 1949 // Build a factor node to remember that this load is independent of the 1950 // other one. 1951 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1952 Hi.getValue(1)); 1953 1954 // Move the top bits to the right place. 1955 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 1956 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1957 1958 // Join the hi and lo parts. 1959 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 1960 } else { 1961 // Big endian - avoid unaligned loads. 1962 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1963 // Load the top RoundWidth bits. 1964 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1965 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1966 Alignment); 1967 1968 // Load the remaining ExtraWidth bits. 1969 IncrementSize = RoundWidth / 8; 1970 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1971 DAG.getIntPtrConstant(IncrementSize)); 1972 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 1973 LD->getSrcValue(), SVOffset + IncrementSize, 1974 ExtraVT, isVolatile, 1975 MinAlign(Alignment, IncrementSize)); 1976 1977 // Build a factor node to remember that this load is independent of the 1978 // other one. 1979 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1980 Hi.getValue(1)); 1981 1982 // Move the top bits to the right place. 1983 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 1984 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1985 1986 // Join the hi and lo parts. 1987 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 1988 } 1989 1990 Tmp1 = LegalizeOp(Result); 1991 Tmp2 = LegalizeOp(Ch); 1992 } else { 1993 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1994 default: assert(0 && "This action is not supported yet!"); 1995 case TargetLowering::Custom: 1996 isCustom = true; 1997 // FALLTHROUGH 1998 case TargetLowering::Legal: 1999 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2000 Tmp1 = Result.getValue(0); 2001 Tmp2 = Result.getValue(1); 2002 2003 if (isCustom) { 2004 Tmp3 = TLI.LowerOperation(Result, DAG); 2005 if (Tmp3.Val) { 2006 Tmp1 = LegalizeOp(Tmp3); 2007 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2008 } 2009 } else { 2010 // If this is an unaligned load and the target doesn't support it, 2011 // expand it. 2012 if (!TLI.allowsUnalignedMemoryAccesses()) { 2013 unsigned ABIAlignment = TLI.getTargetData()-> 2014 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT())); 2015 if (LD->getAlignment() < ABIAlignment){ 2016 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 2017 TLI); 2018 Tmp1 = Result.getOperand(0); 2019 Tmp2 = Result.getOperand(1); 2020 Tmp1 = LegalizeOp(Tmp1); 2021 Tmp2 = LegalizeOp(Tmp2); 2022 } 2023 } 2024 } 2025 break; 2026 case TargetLowering::Expand: 2027 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2028 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2029 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 2030 LD->getSrcValueOffset(), 2031 LD->isVolatile(), LD->getAlignment()); 2032 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 2033 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2034 Tmp2 = LegalizeOp(Load.getValue(1)); 2035 break; 2036 } 2037 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2038 // Turn the unsupported load into an EXTLOAD followed by an explicit 2039 // zero/sign extend inreg. 2040 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2041 Tmp1, Tmp2, LD->getSrcValue(), 2042 LD->getSrcValueOffset(), SrcVT, 2043 LD->isVolatile(), LD->getAlignment()); 2044 SDOperand ValRes; 2045 if (ExtType == ISD::SEXTLOAD) 2046 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2047 Result, DAG.getValueType(SrcVT)); 2048 else 2049 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 2050 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2051 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2052 break; 2053 } 2054 } 2055 2056 // Since loads produce two values, make sure to remember that we legalized 2057 // both of them. 2058 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2059 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2060 return Op.ResNo ? Tmp2 : Tmp1; 2061 } 2062 } 2063 case ISD::EXTRACT_ELEMENT: { 2064 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 2065 switch (getTypeAction(OpTy)) { 2066 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2067 case Legal: 2068 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 2069 // 1 -> Hi 2070 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 2071 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 2072 TLI.getShiftAmountTy())); 2073 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 2074 } else { 2075 // 0 -> Lo 2076 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 2077 Node->getOperand(0)); 2078 } 2079 break; 2080 case Expand: 2081 // Get both the low and high parts. 2082 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2083 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 2084 Result = Tmp2; // 1 -> Hi 2085 else 2086 Result = Tmp1; // 0 -> Lo 2087 break; 2088 } 2089 break; 2090 } 2091 2092 case ISD::CopyToReg: 2093 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2094 2095 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2096 "Register type must be legal!"); 2097 // Legalize the incoming value (must be a legal type). 2098 Tmp2 = LegalizeOp(Node->getOperand(2)); 2099 if (Node->getNumValues() == 1) { 2100 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2101 } else { 2102 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2103 if (Node->getNumOperands() == 4) { 2104 Tmp3 = LegalizeOp(Node->getOperand(3)); 2105 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2106 Tmp3); 2107 } else { 2108 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2109 } 2110 2111 // Since this produces two values, make sure to remember that we legalized 2112 // both of them. 2113 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2114 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2115 return Result; 2116 } 2117 break; 2118 2119 case ISD::RET: 2120 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2121 2122 // Ensure that libcalls are emitted before a return. 2123 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2124 Tmp1 = LegalizeOp(Tmp1); 2125 LastCALLSEQ_END = DAG.getEntryNode(); 2126 2127 switch (Node->getNumOperands()) { 2128 case 3: // ret val 2129 Tmp2 = Node->getOperand(1); 2130 Tmp3 = Node->getOperand(2); // Signness 2131 switch (getTypeAction(Tmp2.getValueType())) { 2132 case Legal: 2133 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2134 break; 2135 case Expand: 2136 if (!MVT::isVector(Tmp2.getValueType())) { 2137 SDOperand Lo, Hi; 2138 ExpandOp(Tmp2, Lo, Hi); 2139 2140 // Big endian systems want the hi reg first. 2141 if (TLI.isBigEndian()) 2142 std::swap(Lo, Hi); 2143 2144 if (Hi.Val) 2145 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2146 else 2147 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 2148 Result = LegalizeOp(Result); 2149 } else { 2150 SDNode *InVal = Tmp2.Val; 2151 int InIx = Tmp2.ResNo; 2152 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 2153 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 2154 2155 // Figure out if there is a simple type corresponding to this Vector 2156 // type. If so, convert to the vector type. 2157 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2158 if (TLI.isTypeLegal(TVT)) { 2159 // Turn this into a return of the vector type. 2160 Tmp2 = LegalizeOp(Tmp2); 2161 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2162 } else if (NumElems == 1) { 2163 // Turn this into a return of the scalar type. 2164 Tmp2 = ScalarizeVectorOp(Tmp2); 2165 Tmp2 = LegalizeOp(Tmp2); 2166 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2167 2168 // FIXME: Returns of gcc generic vectors smaller than a legal type 2169 // should be returned in integer registers! 2170 2171 // The scalarized value type may not be legal, e.g. it might require 2172 // promotion or expansion. Relegalize the return. 2173 Result = LegalizeOp(Result); 2174 } else { 2175 // FIXME: Returns of gcc generic vectors larger than a legal vector 2176 // type should be returned by reference! 2177 SDOperand Lo, Hi; 2178 SplitVectorOp(Tmp2, Lo, Hi); 2179 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2180 Result = LegalizeOp(Result); 2181 } 2182 } 2183 break; 2184 case Promote: 2185 Tmp2 = PromoteOp(Node->getOperand(1)); 2186 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2187 Result = LegalizeOp(Result); 2188 break; 2189 } 2190 break; 2191 case 1: // ret void 2192 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2193 break; 2194 default: { // ret <values> 2195 SmallVector<SDOperand, 8> NewValues; 2196 NewValues.push_back(Tmp1); 2197 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2198 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2199 case Legal: 2200 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2201 NewValues.push_back(Node->getOperand(i+1)); 2202 break; 2203 case Expand: { 2204 SDOperand Lo, Hi; 2205 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && 2206 "FIXME: TODO: implement returning non-legal vector types!"); 2207 ExpandOp(Node->getOperand(i), Lo, Hi); 2208 NewValues.push_back(Lo); 2209 NewValues.push_back(Node->getOperand(i+1)); 2210 if (Hi.Val) { 2211 NewValues.push_back(Hi); 2212 NewValues.push_back(Node->getOperand(i+1)); 2213 } 2214 break; 2215 } 2216 case Promote: 2217 assert(0 && "Can't promote multiple return value yet!"); 2218 } 2219 2220 if (NewValues.size() == Node->getNumOperands()) 2221 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2222 else 2223 Result = DAG.getNode(ISD::RET, MVT::Other, 2224 &NewValues[0], NewValues.size()); 2225 break; 2226 } 2227 } 2228 2229 if (Result.getOpcode() == ISD::RET) { 2230 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2231 default: assert(0 && "This action is not supported yet!"); 2232 case TargetLowering::Legal: break; 2233 case TargetLowering::Custom: 2234 Tmp1 = TLI.LowerOperation(Result, DAG); 2235 if (Tmp1.Val) Result = Tmp1; 2236 break; 2237 } 2238 } 2239 break; 2240 case ISD::STORE: { 2241 StoreSDNode *ST = cast<StoreSDNode>(Node); 2242 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2243 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2244 int SVOffset = ST->getSrcValueOffset(); 2245 unsigned Alignment = ST->getAlignment(); 2246 bool isVolatile = ST->isVolatile(); 2247 2248 if (!ST->isTruncatingStore()) { 2249 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2250 // FIXME: We shouldn't do this for TargetConstantFP's. 2251 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2252 // to phase ordering between legalized code and the dag combiner. This 2253 // probably means that we need to integrate dag combiner and legalizer 2254 // together. 2255 // We generally can't do this one for long doubles. 2256 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2257 if (CFP->getValueType(0) == MVT::f32 && 2258 getTypeAction(MVT::i32) == Legal) { 2259 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF(). 2260 convertToAPInt().getZExtValue(), 2261 MVT::i32); 2262 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2263 SVOffset, isVolatile, Alignment); 2264 break; 2265 } else if (CFP->getValueType(0) == MVT::f64) { 2266 // If this target supports 64-bit registers, do a single 64-bit store. 2267 if (getTypeAction(MVT::i64) == Legal) { 2268 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2269 getZExtValue(), MVT::i64); 2270 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2271 SVOffset, isVolatile, Alignment); 2272 break; 2273 } else if (getTypeAction(MVT::i32) == Legal) { 2274 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2275 // stores. If the target supports neither 32- nor 64-bits, this 2276 // xform is certainly not worth it. 2277 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue(); 2278 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32); 2279 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32); 2280 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2281 2282 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2283 SVOffset, isVolatile, Alignment); 2284 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2285 DAG.getIntPtrConstant(4)); 2286 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2287 isVolatile, MinAlign(Alignment, 4U)); 2288 2289 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2290 break; 2291 } 2292 } 2293 } 2294 2295 switch (getTypeAction(ST->getMemoryVT())) { 2296 case Legal: { 2297 Tmp3 = LegalizeOp(ST->getValue()); 2298 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2299 ST->getOffset()); 2300 2301 MVT::ValueType VT = Tmp3.getValueType(); 2302 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2303 default: assert(0 && "This action is not supported yet!"); 2304 case TargetLowering::Legal: 2305 // If this is an unaligned store and the target doesn't support it, 2306 // expand it. 2307 if (!TLI.allowsUnalignedMemoryAccesses()) { 2308 unsigned ABIAlignment = TLI.getTargetData()-> 2309 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT())); 2310 if (ST->getAlignment() < ABIAlignment) 2311 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2312 TLI); 2313 } 2314 break; 2315 case TargetLowering::Custom: 2316 Tmp1 = TLI.LowerOperation(Result, DAG); 2317 if (Tmp1.Val) Result = Tmp1; 2318 break; 2319 case TargetLowering::Promote: 2320 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 2321 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2322 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2323 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2324 ST->getSrcValue(), SVOffset, isVolatile, 2325 Alignment); 2326 break; 2327 } 2328 break; 2329 } 2330 case Promote: 2331 // Truncate the value and store the result. 2332 Tmp3 = PromoteOp(ST->getValue()); 2333 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2334 SVOffset, ST->getMemoryVT(), 2335 isVolatile, Alignment); 2336 break; 2337 2338 case Expand: 2339 unsigned IncrementSize = 0; 2340 SDOperand Lo, Hi; 2341 2342 // If this is a vector type, then we have to calculate the increment as 2343 // the product of the element size in bytes, and the number of elements 2344 // in the high half of the vector. 2345 if (MVT::isVector(ST->getValue().getValueType())) { 2346 SDNode *InVal = ST->getValue().Val; 2347 int InIx = ST->getValue().ResNo; 2348 MVT::ValueType InVT = InVal->getValueType(InIx); 2349 unsigned NumElems = MVT::getVectorNumElements(InVT); 2350 MVT::ValueType EVT = MVT::getVectorElementType(InVT); 2351 2352 // Figure out if there is a simple type corresponding to this Vector 2353 // type. If so, convert to the vector type. 2354 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2355 if (TLI.isTypeLegal(TVT)) { 2356 // Turn this into a normal store of the vector type. 2357 Tmp3 = LegalizeOp(ST->getValue()); 2358 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2359 SVOffset, isVolatile, Alignment); 2360 Result = LegalizeOp(Result); 2361 break; 2362 } else if (NumElems == 1) { 2363 // Turn this into a normal store of the scalar type. 2364 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2365 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2366 SVOffset, isVolatile, Alignment); 2367 // The scalarized value type may not be legal, e.g. it might require 2368 // promotion or expansion. Relegalize the scalar store. 2369 Result = LegalizeOp(Result); 2370 break; 2371 } else { 2372 SplitVectorOp(ST->getValue(), Lo, Hi); 2373 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) * 2374 MVT::getSizeInBits(EVT)/8; 2375 } 2376 } else { 2377 ExpandOp(ST->getValue(), Lo, Hi); 2378 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 2379 2380 if (TLI.isBigEndian()) 2381 std::swap(Lo, Hi); 2382 } 2383 2384 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2385 SVOffset, isVolatile, Alignment); 2386 2387 if (Hi.Val == NULL) { 2388 // Must be int <-> float one-to-one expansion. 2389 Result = Lo; 2390 break; 2391 } 2392 2393 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2394 DAG.getIntPtrConstant(IncrementSize)); 2395 assert(isTypeLegal(Tmp2.getValueType()) && 2396 "Pointers must be legal!"); 2397 SVOffset += IncrementSize; 2398 Alignment = MinAlign(Alignment, IncrementSize); 2399 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2400 SVOffset, isVolatile, Alignment); 2401 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2402 break; 2403 } 2404 } else { 2405 switch (getTypeAction(ST->getValue().getValueType())) { 2406 case Legal: 2407 Tmp3 = LegalizeOp(ST->getValue()); 2408 break; 2409 case Promote: 2410 // We can promote the value, the truncstore will still take care of it. 2411 Tmp3 = PromoteOp(ST->getValue()); 2412 break; 2413 case Expand: 2414 // Just store the low part. This may become a non-trunc store, so make 2415 // sure to use getTruncStore, not UpdateNodeOperands below. 2416 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2417 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2418 SVOffset, MVT::i8, isVolatile, Alignment); 2419 } 2420 2421 MVT::ValueType StVT = ST->getMemoryVT(); 2422 unsigned StWidth = MVT::getSizeInBits(StVT); 2423 2424 if (StWidth != MVT::getStoreSizeInBits(StVT)) { 2425 // Promote to a byte-sized store with upper bits zero if not 2426 // storing an integral number of bytes. For example, promote 2427 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2428 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT)); 2429 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); 2430 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2431 SVOffset, NVT, isVolatile, Alignment); 2432 } else if (StWidth & (StWidth - 1)) { 2433 // If not storing a power-of-2 number of bits, expand as two stores. 2434 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) && 2435 "Unsupported truncstore!"); 2436 unsigned RoundWidth = 1 << Log2_32(StWidth); 2437 assert(RoundWidth < StWidth); 2438 unsigned ExtraWidth = StWidth - RoundWidth; 2439 assert(ExtraWidth < RoundWidth); 2440 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2441 "Store size not an integral number of bytes!"); 2442 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth); 2443 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth); 2444 SDOperand Lo, Hi; 2445 unsigned IncrementSize; 2446 2447 if (TLI.isLittleEndian()) { 2448 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2449 // Store the bottom RoundWidth bits. 2450 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2451 SVOffset, RoundVT, 2452 isVolatile, Alignment); 2453 2454 // Store the remaining ExtraWidth bits. 2455 IncrementSize = RoundWidth / 8; 2456 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2457 DAG.getIntPtrConstant(IncrementSize)); 2458 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2459 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2460 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2461 SVOffset + IncrementSize, ExtraVT, isVolatile, 2462 MinAlign(Alignment, IncrementSize)); 2463 } else { 2464 // Big endian - avoid unaligned stores. 2465 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2466 // Store the top RoundWidth bits. 2467 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2468 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2469 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, 2470 RoundVT, isVolatile, Alignment); 2471 2472 // Store the remaining ExtraWidth bits. 2473 IncrementSize = RoundWidth / 8; 2474 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2475 DAG.getIntPtrConstant(IncrementSize)); 2476 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2477 SVOffset + IncrementSize, ExtraVT, isVolatile, 2478 MinAlign(Alignment, IncrementSize)); 2479 } 2480 2481 // The order of the stores doesn't matter. 2482 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2483 } else { 2484 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2485 Tmp2 != ST->getBasePtr()) 2486 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2487 ST->getOffset()); 2488 2489 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2490 default: assert(0 && "This action is not supported yet!"); 2491 case TargetLowering::Legal: 2492 // If this is an unaligned store and the target doesn't support it, 2493 // expand it. 2494 if (!TLI.allowsUnalignedMemoryAccesses()) { 2495 unsigned ABIAlignment = TLI.getTargetData()-> 2496 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT())); 2497 if (ST->getAlignment() < ABIAlignment) 2498 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2499 TLI); 2500 } 2501 break; 2502 case TargetLowering::Custom: 2503 Result = TLI.LowerOperation(Result, DAG); 2504 break; 2505 case Expand: 2506 // TRUNCSTORE:i16 i32 -> STORE i16 2507 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2508 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); 2509 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, 2510 isVolatile, Alignment); 2511 break; 2512 } 2513 } 2514 } 2515 break; 2516 } 2517 case ISD::PCMARKER: 2518 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2519 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2520 break; 2521 case ISD::STACKSAVE: 2522 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2523 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2524 Tmp1 = Result.getValue(0); 2525 Tmp2 = Result.getValue(1); 2526 2527 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2528 default: assert(0 && "This action is not supported yet!"); 2529 case TargetLowering::Legal: break; 2530 case TargetLowering::Custom: 2531 Tmp3 = TLI.LowerOperation(Result, DAG); 2532 if (Tmp3.Val) { 2533 Tmp1 = LegalizeOp(Tmp3); 2534 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2535 } 2536 break; 2537 case TargetLowering::Expand: 2538 // Expand to CopyFromReg if the target set 2539 // StackPointerRegisterToSaveRestore. 2540 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2541 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2542 Node->getValueType(0)); 2543 Tmp2 = Tmp1.getValue(1); 2544 } else { 2545 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2546 Tmp2 = Node->getOperand(0); 2547 } 2548 break; 2549 } 2550 2551 // Since stacksave produce two values, make sure to remember that we 2552 // legalized both of them. 2553 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2554 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2555 return Op.ResNo ? Tmp2 : Tmp1; 2556 2557 case ISD::STACKRESTORE: 2558 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2559 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2560 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2561 2562 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2563 default: assert(0 && "This action is not supported yet!"); 2564 case TargetLowering::Legal: break; 2565 case TargetLowering::Custom: 2566 Tmp1 = TLI.LowerOperation(Result, DAG); 2567 if (Tmp1.Val) Result = Tmp1; 2568 break; 2569 case TargetLowering::Expand: 2570 // Expand to CopyToReg if the target set 2571 // StackPointerRegisterToSaveRestore. 2572 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2573 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2574 } else { 2575 Result = Tmp1; 2576 } 2577 break; 2578 } 2579 break; 2580 2581 case ISD::READCYCLECOUNTER: 2582 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2583 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2584 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2585 Node->getValueType(0))) { 2586 default: assert(0 && "This action is not supported yet!"); 2587 case TargetLowering::Legal: 2588 Tmp1 = Result.getValue(0); 2589 Tmp2 = Result.getValue(1); 2590 break; 2591 case TargetLowering::Custom: 2592 Result = TLI.LowerOperation(Result, DAG); 2593 Tmp1 = LegalizeOp(Result.getValue(0)); 2594 Tmp2 = LegalizeOp(Result.getValue(1)); 2595 break; 2596 } 2597 2598 // Since rdcc produce two values, make sure to remember that we legalized 2599 // both of them. 2600 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2601 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2602 return Result; 2603 2604 case ISD::SELECT: 2605 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2606 case Expand: assert(0 && "It's impossible to expand bools"); 2607 case Legal: 2608 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2609 break; 2610 case Promote: 2611 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2612 // Make sure the condition is either zero or one. 2613 if (!DAG.MaskedValueIsZero(Tmp1, 2614 MVT::getIntVTBitMask(Tmp1.getValueType())^1)) 2615 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2616 break; 2617 } 2618 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2619 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2620 2621 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2622 2623 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2624 default: assert(0 && "This action is not supported yet!"); 2625 case TargetLowering::Legal: break; 2626 case TargetLowering::Custom: { 2627 Tmp1 = TLI.LowerOperation(Result, DAG); 2628 if (Tmp1.Val) Result = Tmp1; 2629 break; 2630 } 2631 case TargetLowering::Expand: 2632 if (Tmp1.getOpcode() == ISD::SETCC) { 2633 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2634 Tmp2, Tmp3, 2635 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2636 } else { 2637 Result = DAG.getSelectCC(Tmp1, 2638 DAG.getConstant(0, Tmp1.getValueType()), 2639 Tmp2, Tmp3, ISD::SETNE); 2640 } 2641 break; 2642 case TargetLowering::Promote: { 2643 MVT::ValueType NVT = 2644 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2645 unsigned ExtOp, TruncOp; 2646 if (MVT::isVector(Tmp2.getValueType())) { 2647 ExtOp = ISD::BIT_CONVERT; 2648 TruncOp = ISD::BIT_CONVERT; 2649 } else if (MVT::isInteger(Tmp2.getValueType())) { 2650 ExtOp = ISD::ANY_EXTEND; 2651 TruncOp = ISD::TRUNCATE; 2652 } else { 2653 ExtOp = ISD::FP_EXTEND; 2654 TruncOp = ISD::FP_ROUND; 2655 } 2656 // Promote each of the values to the new type. 2657 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2658 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2659 // Perform the larger operation, then round down. 2660 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2661 if (TruncOp != ISD::FP_ROUND) 2662 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2663 else 2664 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2665 DAG.getIntPtrConstant(0)); 2666 break; 2667 } 2668 } 2669 break; 2670 case ISD::SELECT_CC: { 2671 Tmp1 = Node->getOperand(0); // LHS 2672 Tmp2 = Node->getOperand(1); // RHS 2673 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2674 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2675 SDOperand CC = Node->getOperand(4); 2676 2677 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2678 2679 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2680 // the LHS is a legal SETCC itself. In this case, we need to compare 2681 // the result against zero to select between true and false values. 2682 if (Tmp2.Val == 0) { 2683 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2684 CC = DAG.getCondCode(ISD::SETNE); 2685 } 2686 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2687 2688 // Everything is legal, see if we should expand this op or something. 2689 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2690 default: assert(0 && "This action is not supported yet!"); 2691 case TargetLowering::Legal: break; 2692 case TargetLowering::Custom: 2693 Tmp1 = TLI.LowerOperation(Result, DAG); 2694 if (Tmp1.Val) Result = Tmp1; 2695 break; 2696 } 2697 break; 2698 } 2699 case ISD::SETCC: 2700 Tmp1 = Node->getOperand(0); 2701 Tmp2 = Node->getOperand(1); 2702 Tmp3 = Node->getOperand(2); 2703 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2704 2705 // If we had to Expand the SetCC operands into a SELECT node, then it may 2706 // not always be possible to return a true LHS & RHS. In this case, just 2707 // return the value we legalized, returned in the LHS 2708 if (Tmp2.Val == 0) { 2709 Result = Tmp1; 2710 break; 2711 } 2712 2713 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2714 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2715 case TargetLowering::Custom: 2716 isCustom = true; 2717 // FALLTHROUGH. 2718 case TargetLowering::Legal: 2719 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2720 if (isCustom) { 2721 Tmp4 = TLI.LowerOperation(Result, DAG); 2722 if (Tmp4.Val) Result = Tmp4; 2723 } 2724 break; 2725 case TargetLowering::Promote: { 2726 // First step, figure out the appropriate operation to use. 2727 // Allow SETCC to not be supported for all legal data types 2728 // Mostly this targets FP 2729 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2730 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2731 2732 // Scan for the appropriate larger type to use. 2733 while (1) { 2734 NewInTy = (MVT::ValueType)(NewInTy+1); 2735 2736 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2737 "Fell off of the edge of the integer world"); 2738 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2739 "Fell off of the edge of the floating point world"); 2740 2741 // If the target supports SETCC of this type, use it. 2742 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2743 break; 2744 } 2745 if (MVT::isInteger(NewInTy)) 2746 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2747 else { 2748 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2749 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2750 } 2751 Tmp1 = LegalizeOp(Tmp1); 2752 Tmp2 = LegalizeOp(Tmp2); 2753 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2754 Result = LegalizeOp(Result); 2755 break; 2756 } 2757 case TargetLowering::Expand: 2758 // Expand a setcc node into a select_cc of the same condition, lhs, and 2759 // rhs that selects between const 1 (true) and const 0 (false). 2760 MVT::ValueType VT = Node->getValueType(0); 2761 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2762 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2763 Tmp3); 2764 break; 2765 } 2766 break; 2767 case ISD::MEMSET: 2768 case ISD::MEMCPY: 2769 case ISD::MEMMOVE: { 2770 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2771 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2772 2773 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2774 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2775 case Expand: assert(0 && "Cannot expand a byte!"); 2776 case Legal: 2777 Tmp3 = LegalizeOp(Node->getOperand(2)); 2778 break; 2779 case Promote: 2780 Tmp3 = PromoteOp(Node->getOperand(2)); 2781 break; 2782 } 2783 } else { 2784 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2785 } 2786 2787 SDOperand Tmp4; 2788 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2789 case Expand: { 2790 // Length is too big, just take the lo-part of the length. 2791 SDOperand HiPart; 2792 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2793 break; 2794 } 2795 case Legal: 2796 Tmp4 = LegalizeOp(Node->getOperand(3)); 2797 break; 2798 case Promote: 2799 Tmp4 = PromoteOp(Node->getOperand(3)); 2800 break; 2801 } 2802 2803 SDOperand Tmp5; 2804 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2805 case Expand: assert(0 && "Cannot expand this yet!"); 2806 case Legal: 2807 Tmp5 = LegalizeOp(Node->getOperand(4)); 2808 break; 2809 case Promote: 2810 Tmp5 = PromoteOp(Node->getOperand(4)); 2811 break; 2812 } 2813 2814 SDOperand Tmp6; 2815 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool 2816 case Expand: assert(0 && "Cannot expand this yet!"); 2817 case Legal: 2818 Tmp6 = LegalizeOp(Node->getOperand(5)); 2819 break; 2820 case Promote: 2821 Tmp6 = PromoteOp(Node->getOperand(5)); 2822 break; 2823 } 2824 2825 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2826 default: assert(0 && "This action not implemented for this operation!"); 2827 case TargetLowering::Custom: 2828 isCustom = true; 2829 // FALLTHROUGH 2830 case TargetLowering::Legal: { 2831 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 }; 2832 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 2833 if (isCustom) { 2834 Tmp1 = TLI.LowerOperation(Result, DAG); 2835 if (Tmp1.Val) Result = Tmp1; 2836 } 2837 break; 2838 } 2839 case TargetLowering::Expand: { 2840 // Otherwise, the target does not support this operation. Lower the 2841 // operation to an explicit libcall as appropriate. 2842 MVT::ValueType IntPtr = TLI.getPointerTy(); 2843 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2844 TargetLowering::ArgListTy Args; 2845 TargetLowering::ArgListEntry Entry; 2846 2847 const char *FnName = 0; 2848 if (Node->getOpcode() == ISD::MEMSET) { 2849 Entry.Node = Tmp2; Entry.Ty = IntPtrTy; 2850 Args.push_back(Entry); 2851 // Extend the (previously legalized) ubyte argument to be an int value 2852 // for the call. 2853 if (Tmp3.getValueType() > MVT::i32) 2854 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2855 else 2856 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2857 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 2858 Args.push_back(Entry); 2859 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false; 2860 Args.push_back(Entry); 2861 2862 FnName = "memset"; 2863 } else if (Node->getOpcode() == ISD::MEMCPY || 2864 Node->getOpcode() == ISD::MEMMOVE) { 2865 Entry.Ty = IntPtrTy; 2866 Entry.Node = Tmp2; Args.push_back(Entry); 2867 Entry.Node = Tmp3; Args.push_back(Entry); 2868 Entry.Node = Tmp4; Args.push_back(Entry); 2869 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2870 } else { 2871 assert(0 && "Unknown op!"); 2872 } 2873 2874 std::pair<SDOperand,SDOperand> CallResult = 2875 TLI.LowerCallTo(Tmp1, Type::VoidTy, 2876 false, false, false, CallingConv::C, false, 2877 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2878 Result = CallResult.second; 2879 break; 2880 } 2881 } 2882 break; 2883 } 2884 2885 case ISD::SHL_PARTS: 2886 case ISD::SRA_PARTS: 2887 case ISD::SRL_PARTS: { 2888 SmallVector<SDOperand, 8> Ops; 2889 bool Changed = false; 2890 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2891 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2892 Changed |= Ops.back() != Node->getOperand(i); 2893 } 2894 if (Changed) 2895 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2896 2897 switch (TLI.getOperationAction(Node->getOpcode(), 2898 Node->getValueType(0))) { 2899 default: assert(0 && "This action is not supported yet!"); 2900 case TargetLowering::Legal: break; 2901 case TargetLowering::Custom: 2902 Tmp1 = TLI.LowerOperation(Result, DAG); 2903 if (Tmp1.Val) { 2904 SDOperand Tmp2, RetVal(0, 0); 2905 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2906 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2907 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2908 if (i == Op.ResNo) 2909 RetVal = Tmp2; 2910 } 2911 assert(RetVal.Val && "Illegal result number"); 2912 return RetVal; 2913 } 2914 break; 2915 } 2916 2917 // Since these produce multiple values, make sure to remember that we 2918 // legalized all of them. 2919 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2920 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2921 return Result.getValue(Op.ResNo); 2922 } 2923 2924 // Binary operators 2925 case ISD::ADD: 2926 case ISD::SUB: 2927 case ISD::MUL: 2928 case ISD::MULHS: 2929 case ISD::MULHU: 2930 case ISD::UDIV: 2931 case ISD::SDIV: 2932 case ISD::AND: 2933 case ISD::OR: 2934 case ISD::XOR: 2935 case ISD::SHL: 2936 case ISD::SRL: 2937 case ISD::SRA: 2938 case ISD::FADD: 2939 case ISD::FSUB: 2940 case ISD::FMUL: 2941 case ISD::FDIV: 2942 case ISD::FPOW: 2943 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2944 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2945 case Expand: assert(0 && "Not possible"); 2946 case Legal: 2947 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2948 break; 2949 case Promote: 2950 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2951 break; 2952 } 2953 2954 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2955 2956 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2957 default: assert(0 && "BinOp legalize operation not supported"); 2958 case TargetLowering::Legal: break; 2959 case TargetLowering::Custom: 2960 Tmp1 = TLI.LowerOperation(Result, DAG); 2961 if (Tmp1.Val) Result = Tmp1; 2962 break; 2963 case TargetLowering::Expand: { 2964 MVT::ValueType VT = Op.getValueType(); 2965 2966 // See if multiply or divide can be lowered using two-result operations. 2967 SDVTList VTs = DAG.getVTList(VT, VT); 2968 if (Node->getOpcode() == ISD::MUL) { 2969 // We just need the low half of the multiply; try both the signed 2970 // and unsigned forms. If the target supports both SMUL_LOHI and 2971 // UMUL_LOHI, form a preference by checking which forms of plain 2972 // MULH it supports. 2973 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2974 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2975 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2976 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2977 unsigned OpToUse = 0; 2978 if (HasSMUL_LOHI && !HasMULHS) { 2979 OpToUse = ISD::SMUL_LOHI; 2980 } else if (HasUMUL_LOHI && !HasMULHU) { 2981 OpToUse = ISD::UMUL_LOHI; 2982 } else if (HasSMUL_LOHI) { 2983 OpToUse = ISD::SMUL_LOHI; 2984 } else if (HasUMUL_LOHI) { 2985 OpToUse = ISD::UMUL_LOHI; 2986 } 2987 if (OpToUse) { 2988 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 2989 break; 2990 } 2991 } 2992 if (Node->getOpcode() == ISD::MULHS && 2993 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 2994 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 2995 break; 2996 } 2997 if (Node->getOpcode() == ISD::MULHU && 2998 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 2999 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3000 break; 3001 } 3002 if (Node->getOpcode() == ISD::SDIV && 3003 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3004 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3005 break; 3006 } 3007 if (Node->getOpcode() == ISD::UDIV && 3008 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3009 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3010 break; 3011 } 3012 3013 // Check to see if we have a libcall for this operator. 3014 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3015 bool isSigned = false; 3016 switch (Node->getOpcode()) { 3017 case ISD::UDIV: 3018 case ISD::SDIV: 3019 if (VT == MVT::i32) { 3020 LC = Node->getOpcode() == ISD::UDIV 3021 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3022 isSigned = Node->getOpcode() == ISD::SDIV; 3023 } 3024 break; 3025 case ISD::FPOW: 3026 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3027 RTLIB::POW_PPCF128); 3028 break; 3029 default: break; 3030 } 3031 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3032 SDOperand Dummy; 3033 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 3034 break; 3035 } 3036 3037 assert(MVT::isVector(Node->getValueType(0)) && 3038 "Cannot expand this binary operator!"); 3039 // Expand the operation into a bunch of nasty scalar code. 3040 Result = LegalizeOp(UnrollVectorOp(Op)); 3041 break; 3042 } 3043 case TargetLowering::Promote: { 3044 switch (Node->getOpcode()) { 3045 default: assert(0 && "Do not know how to promote this BinOp!"); 3046 case ISD::AND: 3047 case ISD::OR: 3048 case ISD::XOR: { 3049 MVT::ValueType OVT = Node->getValueType(0); 3050 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3051 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 3052 // Bit convert each of the values to the new type. 3053 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 3054 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 3055 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3056 // Bit convert the result back the original type. 3057 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 3058 break; 3059 } 3060 } 3061 } 3062 } 3063 break; 3064 3065 case ISD::SMUL_LOHI: 3066 case ISD::UMUL_LOHI: 3067 case ISD::SDIVREM: 3068 case ISD::UDIVREM: 3069 // These nodes will only be produced by target-specific lowering, so 3070 // they shouldn't be here if they aren't legal. 3071 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3072 "This must be legal!"); 3073 3074 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3075 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3076 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3077 break; 3078 3079 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3080 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3081 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3082 case Expand: assert(0 && "Not possible"); 3083 case Legal: 3084 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3085 break; 3086 case Promote: 3087 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3088 break; 3089 } 3090 3091 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3092 3093 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3094 default: assert(0 && "Operation not supported"); 3095 case TargetLowering::Custom: 3096 Tmp1 = TLI.LowerOperation(Result, DAG); 3097 if (Tmp1.Val) Result = Tmp1; 3098 break; 3099 case TargetLowering::Legal: break; 3100 case TargetLowering::Expand: { 3101 // If this target supports fabs/fneg natively and select is cheap, 3102 // do this efficiently. 3103 if (!TLI.isSelectExpensive() && 3104 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3105 TargetLowering::Legal && 3106 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3107 TargetLowering::Legal) { 3108 // Get the sign bit of the RHS. 3109 MVT::ValueType IVT = 3110 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3111 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 3112 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 3113 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3114 // Get the absolute value of the result. 3115 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 3116 // Select between the nabs and abs value based on the sign bit of 3117 // the input. 3118 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 3119 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3120 AbsVal), 3121 AbsVal); 3122 Result = LegalizeOp(Result); 3123 break; 3124 } 3125 3126 // Otherwise, do bitwise ops! 3127 MVT::ValueType NVT = 3128 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3129 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3130 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 3131 Result = LegalizeOp(Result); 3132 break; 3133 } 3134 } 3135 break; 3136 3137 case ISD::ADDC: 3138 case ISD::SUBC: 3139 Tmp1 = LegalizeOp(Node->getOperand(0)); 3140 Tmp2 = LegalizeOp(Node->getOperand(1)); 3141 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3142 // Since this produces two values, make sure to remember that we legalized 3143 // both of them. 3144 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3145 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3146 return Result; 3147 3148 case ISD::ADDE: 3149 case ISD::SUBE: 3150 Tmp1 = LegalizeOp(Node->getOperand(0)); 3151 Tmp2 = LegalizeOp(Node->getOperand(1)); 3152 Tmp3 = LegalizeOp(Node->getOperand(2)); 3153 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3154 // Since this produces two values, make sure to remember that we legalized 3155 // both of them. 3156 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3157 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3158 return Result; 3159 3160 case ISD::BUILD_PAIR: { 3161 MVT::ValueType PairTy = Node->getValueType(0); 3162 // TODO: handle the case where the Lo and Hi operands are not of legal type 3163 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3164 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3165 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3166 case TargetLowering::Promote: 3167 case TargetLowering::Custom: 3168 assert(0 && "Cannot promote/custom this yet!"); 3169 case TargetLowering::Legal: 3170 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3171 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 3172 break; 3173 case TargetLowering::Expand: 3174 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 3175 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 3176 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 3177 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 3178 TLI.getShiftAmountTy())); 3179 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 3180 break; 3181 } 3182 break; 3183 } 3184 3185 case ISD::UREM: 3186 case ISD::SREM: 3187 case ISD::FREM: 3188 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3189 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3190 3191 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3192 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3193 case TargetLowering::Custom: 3194 isCustom = true; 3195 // FALLTHROUGH 3196 case TargetLowering::Legal: 3197 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3198 if (isCustom) { 3199 Tmp1 = TLI.LowerOperation(Result, DAG); 3200 if (Tmp1.Val) Result = Tmp1; 3201 } 3202 break; 3203 case TargetLowering::Expand: { 3204 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3205 bool isSigned = DivOpc == ISD::SDIV; 3206 MVT::ValueType VT = Node->getValueType(0); 3207 3208 // See if remainder can be lowered using two-result operations. 3209 SDVTList VTs = DAG.getVTList(VT, VT); 3210 if (Node->getOpcode() == ISD::SREM && 3211 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3212 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3213 break; 3214 } 3215 if (Node->getOpcode() == ISD::UREM && 3216 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3217 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3218 break; 3219 } 3220 3221 if (MVT::isInteger(VT)) { 3222 if (TLI.getOperationAction(DivOpc, VT) == 3223 TargetLowering::Legal) { 3224 // X % Y -> X-X/Y*Y 3225 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3226 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3227 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3228 } else if (MVT::isVector(VT)) { 3229 Result = LegalizeOp(UnrollVectorOp(Op)); 3230 } else { 3231 assert(VT == MVT::i32 && 3232 "Cannot expand this binary operator!"); 3233 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3234 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3235 SDOperand Dummy; 3236 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 3237 } 3238 } else { 3239 assert(MVT::isFloatingPoint(VT) && 3240 "remainder op must have integer or floating-point type"); 3241 if (MVT::isVector(VT)) { 3242 Result = LegalizeOp(UnrollVectorOp(Op)); 3243 } else { 3244 // Floating point mod -> fmod libcall. 3245 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3246 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3247 SDOperand Dummy; 3248 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3249 false/*sign irrelevant*/, Dummy); 3250 } 3251 } 3252 break; 3253 } 3254 } 3255 break; 3256 case ISD::VAARG: { 3257 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3258 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3259 3260 MVT::ValueType VT = Node->getValueType(0); 3261 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3262 default: assert(0 && "This action is not supported yet!"); 3263 case TargetLowering::Custom: 3264 isCustom = true; 3265 // FALLTHROUGH 3266 case TargetLowering::Legal: 3267 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3268 Result = Result.getValue(0); 3269 Tmp1 = Result.getValue(1); 3270 3271 if (isCustom) { 3272 Tmp2 = TLI.LowerOperation(Result, DAG); 3273 if (Tmp2.Val) { 3274 Result = LegalizeOp(Tmp2); 3275 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3276 } 3277 } 3278 break; 3279 case TargetLowering::Expand: { 3280 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3281 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 3282 // Increment the pointer, VAList, to the next vaarg 3283 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3284 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3285 TLI.getPointerTy())); 3286 // Store the incremented VAList to the legalized pointer 3287 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 3288 // Load the actual argument out of the pointer VAList 3289 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3290 Tmp1 = LegalizeOp(Result.getValue(1)); 3291 Result = LegalizeOp(Result); 3292 break; 3293 } 3294 } 3295 // Since VAARG produces two values, make sure to remember that we 3296 // legalized both of them. 3297 AddLegalizedOperand(SDOperand(Node, 0), Result); 3298 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3299 return Op.ResNo ? Tmp1 : Result; 3300 } 3301 3302 case ISD::VACOPY: 3303 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3304 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3305 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3306 3307 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3308 default: assert(0 && "This action is not supported yet!"); 3309 case TargetLowering::Custom: 3310 isCustom = true; 3311 // FALLTHROUGH 3312 case TargetLowering::Legal: 3313 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3314 Node->getOperand(3), Node->getOperand(4)); 3315 if (isCustom) { 3316 Tmp1 = TLI.LowerOperation(Result, DAG); 3317 if (Tmp1.Val) Result = Tmp1; 3318 } 3319 break; 3320 case TargetLowering::Expand: 3321 // This defaults to loading a pointer from the input and storing it to the 3322 // output, returning the chain. 3323 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3324 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3325 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0); 3326 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0); 3327 break; 3328 } 3329 break; 3330 3331 case ISD::VAEND: 3332 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3333 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3334 3335 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3336 default: assert(0 && "This action is not supported yet!"); 3337 case TargetLowering::Custom: 3338 isCustom = true; 3339 // FALLTHROUGH 3340 case TargetLowering::Legal: 3341 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3342 if (isCustom) { 3343 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3344 if (Tmp1.Val) Result = Tmp1; 3345 } 3346 break; 3347 case TargetLowering::Expand: 3348 Result = Tmp1; // Default to a no-op, return the chain 3349 break; 3350 } 3351 break; 3352 3353 case ISD::VASTART: 3354 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3355 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3356 3357 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3358 3359 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3360 default: assert(0 && "This action is not supported yet!"); 3361 case TargetLowering::Legal: break; 3362 case TargetLowering::Custom: 3363 Tmp1 = TLI.LowerOperation(Result, DAG); 3364 if (Tmp1.Val) Result = Tmp1; 3365 break; 3366 } 3367 break; 3368 3369 case ISD::ROTL: 3370 case ISD::ROTR: 3371 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3372 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3373 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3374 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3375 default: 3376 assert(0 && "ROTL/ROTR legalize operation not supported"); 3377 break; 3378 case TargetLowering::Legal: 3379 break; 3380 case TargetLowering::Custom: 3381 Tmp1 = TLI.LowerOperation(Result, DAG); 3382 if (Tmp1.Val) Result = Tmp1; 3383 break; 3384 case TargetLowering::Promote: 3385 assert(0 && "Do not know how to promote ROTL/ROTR"); 3386 break; 3387 case TargetLowering::Expand: 3388 assert(0 && "Do not know how to expand ROTL/ROTR"); 3389 break; 3390 } 3391 break; 3392 3393 case ISD::BSWAP: 3394 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3395 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3396 case TargetLowering::Custom: 3397 assert(0 && "Cannot custom legalize this yet!"); 3398 case TargetLowering::Legal: 3399 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3400 break; 3401 case TargetLowering::Promote: { 3402 MVT::ValueType OVT = Tmp1.getValueType(); 3403 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3404 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); 3405 3406 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3407 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3408 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3409 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3410 break; 3411 } 3412 case TargetLowering::Expand: 3413 Result = ExpandBSWAP(Tmp1); 3414 break; 3415 } 3416 break; 3417 3418 case ISD::CTPOP: 3419 case ISD::CTTZ: 3420 case ISD::CTLZ: 3421 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3422 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3423 case TargetLowering::Custom: 3424 case TargetLowering::Legal: 3425 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3426 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3427 TargetLowering::Custom) { 3428 Tmp1 = TLI.LowerOperation(Result, DAG); 3429 if (Tmp1.Val) { 3430 Result = Tmp1; 3431 } 3432 } 3433 break; 3434 case TargetLowering::Promote: { 3435 MVT::ValueType OVT = Tmp1.getValueType(); 3436 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3437 3438 // Zero extend the argument. 3439 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3440 // Perform the larger operation, then subtract if needed. 3441 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3442 switch (Node->getOpcode()) { 3443 case ISD::CTPOP: 3444 Result = Tmp1; 3445 break; 3446 case ISD::CTTZ: 3447 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3448 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3449 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 3450 ISD::SETEQ); 3451 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3452 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); 3453 break; 3454 case ISD::CTLZ: 3455 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3456 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3457 DAG.getConstant(MVT::getSizeInBits(NVT) - 3458 MVT::getSizeInBits(OVT), NVT)); 3459 break; 3460 } 3461 break; 3462 } 3463 case TargetLowering::Expand: 3464 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3465 break; 3466 } 3467 break; 3468 3469 // Unary operators 3470 case ISD::FABS: 3471 case ISD::FNEG: 3472 case ISD::FSQRT: 3473 case ISD::FSIN: 3474 case ISD::FCOS: 3475 Tmp1 = LegalizeOp(Node->getOperand(0)); 3476 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3477 case TargetLowering::Promote: 3478 case TargetLowering::Custom: 3479 isCustom = true; 3480 // FALLTHROUGH 3481 case TargetLowering::Legal: 3482 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3483 if (isCustom) { 3484 Tmp1 = TLI.LowerOperation(Result, DAG); 3485 if (Tmp1.Val) Result = Tmp1; 3486 } 3487 break; 3488 case TargetLowering::Expand: 3489 switch (Node->getOpcode()) { 3490 default: assert(0 && "Unreachable!"); 3491 case ISD::FNEG: 3492 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3493 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3494 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3495 break; 3496 case ISD::FABS: { 3497 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3498 MVT::ValueType VT = Node->getValueType(0); 3499 Tmp2 = DAG.getConstantFP(0.0, VT); 3500 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 3501 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3502 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3503 break; 3504 } 3505 case ISD::FSQRT: 3506 case ISD::FSIN: 3507 case ISD::FCOS: { 3508 MVT::ValueType VT = Node->getValueType(0); 3509 3510 // Expand unsupported unary vector operators by unrolling them. 3511 if (MVT::isVector(VT)) { 3512 Result = LegalizeOp(UnrollVectorOp(Op)); 3513 break; 3514 } 3515 3516 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3517 switch(Node->getOpcode()) { 3518 case ISD::FSQRT: 3519 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3520 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3521 break; 3522 case ISD::FSIN: 3523 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3524 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3525 break; 3526 case ISD::FCOS: 3527 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3528 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3529 break; 3530 default: assert(0 && "Unreachable!"); 3531 } 3532 SDOperand Dummy; 3533 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3534 false/*sign irrelevant*/, Dummy); 3535 break; 3536 } 3537 } 3538 break; 3539 } 3540 break; 3541 case ISD::FPOWI: { 3542 MVT::ValueType VT = Node->getValueType(0); 3543 3544 // Expand unsupported unary vector operators by unrolling them. 3545 if (MVT::isVector(VT)) { 3546 Result = LegalizeOp(UnrollVectorOp(Op)); 3547 break; 3548 } 3549 3550 // We always lower FPOWI into a libcall. No target support for it yet. 3551 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3552 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3553 SDOperand Dummy; 3554 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3555 false/*sign irrelevant*/, Dummy); 3556 break; 3557 } 3558 case ISD::BIT_CONVERT: 3559 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3560 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3561 Node->getValueType(0)); 3562 } else if (MVT::isVector(Op.getOperand(0).getValueType())) { 3563 // The input has to be a vector type, we have to either scalarize it, pack 3564 // it, or convert it based on whether the input vector type is legal. 3565 SDNode *InVal = Node->getOperand(0).Val; 3566 int InIx = Node->getOperand(0).ResNo; 3567 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 3568 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 3569 3570 // Figure out if there is a simple type corresponding to this Vector 3571 // type. If so, convert to the vector type. 3572 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3573 if (TLI.isTypeLegal(TVT)) { 3574 // Turn this into a bit convert of the vector input. 3575 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3576 LegalizeOp(Node->getOperand(0))); 3577 break; 3578 } else if (NumElems == 1) { 3579 // Turn this into a bit convert of the scalar input. 3580 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3581 ScalarizeVectorOp(Node->getOperand(0))); 3582 break; 3583 } else { 3584 // FIXME: UNIMP! Store then reload 3585 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3586 } 3587 } else { 3588 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3589 Node->getOperand(0).getValueType())) { 3590 default: assert(0 && "Unknown operation action!"); 3591 case TargetLowering::Expand: 3592 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3593 Node->getValueType(0)); 3594 break; 3595 case TargetLowering::Legal: 3596 Tmp1 = LegalizeOp(Node->getOperand(0)); 3597 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3598 break; 3599 } 3600 } 3601 break; 3602 3603 // Conversion operators. The source and destination have different types. 3604 case ISD::SINT_TO_FP: 3605 case ISD::UINT_TO_FP: { 3606 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3607 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3608 case Legal: 3609 switch (TLI.getOperationAction(Node->getOpcode(), 3610 Node->getOperand(0).getValueType())) { 3611 default: assert(0 && "Unknown operation action!"); 3612 case TargetLowering::Custom: 3613 isCustom = true; 3614 // FALLTHROUGH 3615 case TargetLowering::Legal: 3616 Tmp1 = LegalizeOp(Node->getOperand(0)); 3617 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3618 if (isCustom) { 3619 Tmp1 = TLI.LowerOperation(Result, DAG); 3620 if (Tmp1.Val) Result = Tmp1; 3621 } 3622 break; 3623 case TargetLowering::Expand: 3624 Result = ExpandLegalINT_TO_FP(isSigned, 3625 LegalizeOp(Node->getOperand(0)), 3626 Node->getValueType(0)); 3627 break; 3628 case TargetLowering::Promote: 3629 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3630 Node->getValueType(0), 3631 isSigned); 3632 break; 3633 } 3634 break; 3635 case Expand: 3636 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3637 Node->getValueType(0), Node->getOperand(0)); 3638 break; 3639 case Promote: 3640 Tmp1 = PromoteOp(Node->getOperand(0)); 3641 if (isSigned) { 3642 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3643 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3644 } else { 3645 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3646 Node->getOperand(0).getValueType()); 3647 } 3648 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3649 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3650 break; 3651 } 3652 break; 3653 } 3654 case ISD::TRUNCATE: 3655 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3656 case Legal: 3657 Tmp1 = LegalizeOp(Node->getOperand(0)); 3658 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3659 break; 3660 case Expand: 3661 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3662 3663 // Since the result is legal, we should just be able to truncate the low 3664 // part of the source. 3665 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3666 break; 3667 case Promote: 3668 Result = PromoteOp(Node->getOperand(0)); 3669 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3670 break; 3671 } 3672 break; 3673 3674 case ISD::FP_TO_SINT: 3675 case ISD::FP_TO_UINT: 3676 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3677 case Legal: 3678 Tmp1 = LegalizeOp(Node->getOperand(0)); 3679 3680 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3681 default: assert(0 && "Unknown operation action!"); 3682 case TargetLowering::Custom: 3683 isCustom = true; 3684 // FALLTHROUGH 3685 case TargetLowering::Legal: 3686 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3687 if (isCustom) { 3688 Tmp1 = TLI.LowerOperation(Result, DAG); 3689 if (Tmp1.Val) Result = Tmp1; 3690 } 3691 break; 3692 case TargetLowering::Promote: 3693 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3694 Node->getOpcode() == ISD::FP_TO_SINT); 3695 break; 3696 case TargetLowering::Expand: 3697 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3698 SDOperand True, False; 3699 MVT::ValueType VT = Node->getOperand(0).getValueType(); 3700 MVT::ValueType NVT = Node->getValueType(0); 3701 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1; 3702 const uint64_t zero[] = {0, 0}; 3703 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero)); 3704 uint64_t x = 1ULL << ShiftAmt; 3705 (void)apf.convertFromZeroExtendedInteger 3706 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven); 3707 Tmp2 = DAG.getConstantFP(apf, VT); 3708 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 3709 Node->getOperand(0), Tmp2, ISD::SETLT); 3710 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3711 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3712 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3713 Tmp2)); 3714 False = DAG.getNode(ISD::XOR, NVT, False, 3715 DAG.getConstant(1ULL << ShiftAmt, NVT)); 3716 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3717 break; 3718 } else { 3719 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3720 } 3721 break; 3722 } 3723 break; 3724 case Expand: { 3725 MVT::ValueType VT = Op.getValueType(); 3726 MVT::ValueType OVT = Node->getOperand(0).getValueType(); 3727 // Convert ppcf128 to i32 3728 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3729 if (Node->getOpcode() == ISD::FP_TO_SINT) { 3730 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 3731 Node->getOperand(0), DAG.getValueType(MVT::f64)); 3732 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 3733 DAG.getIntPtrConstant(1)); 3734 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 3735 } else { 3736 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3737 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3738 Tmp2 = DAG.getConstantFP(apf, OVT); 3739 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3740 // FIXME: generated code sucks. 3741 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3742 DAG.getNode(ISD::ADD, MVT::i32, 3743 DAG.getNode(ISD::FP_TO_SINT, VT, 3744 DAG.getNode(ISD::FSUB, OVT, 3745 Node->getOperand(0), Tmp2)), 3746 DAG.getConstant(0x80000000, MVT::i32)), 3747 DAG.getNode(ISD::FP_TO_SINT, VT, 3748 Node->getOperand(0)), 3749 DAG.getCondCode(ISD::SETGE)); 3750 } 3751 break; 3752 } 3753 // Convert f32 / f64 to i32 / i64. 3754 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3755 switch (Node->getOpcode()) { 3756 case ISD::FP_TO_SINT: { 3757 if (OVT == MVT::f32) 3758 LC = (VT == MVT::i32) 3759 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3760 else if (OVT == MVT::f64) 3761 LC = (VT == MVT::i32) 3762 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3763 else if (OVT == MVT::f80) { 3764 assert(VT == MVT::i64); 3765 LC = RTLIB::FPTOSINT_F80_I64; 3766 } 3767 else if (OVT == MVT::ppcf128) { 3768 assert(VT == MVT::i64); 3769 LC = RTLIB::FPTOSINT_PPCF128_I64; 3770 } 3771 break; 3772 } 3773 case ISD::FP_TO_UINT: { 3774 if (OVT == MVT::f32) 3775 LC = (VT == MVT::i32) 3776 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3777 else if (OVT == MVT::f64) 3778 LC = (VT == MVT::i32) 3779 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3780 else if (OVT == MVT::f80) { 3781 LC = (VT == MVT::i32) 3782 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64; 3783 } 3784 else if (OVT == MVT::ppcf128) { 3785 assert(VT == MVT::i64); 3786 LC = RTLIB::FPTOUINT_PPCF128_I64; 3787 } 3788 break; 3789 } 3790 default: assert(0 && "Unreachable!"); 3791 } 3792 SDOperand Dummy; 3793 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3794 false/*sign irrelevant*/, Dummy); 3795 break; 3796 } 3797 case Promote: 3798 Tmp1 = PromoteOp(Node->getOperand(0)); 3799 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3800 Result = LegalizeOp(Result); 3801 break; 3802 } 3803 break; 3804 3805 case ISD::FP_EXTEND: { 3806 MVT::ValueType DstVT = Op.getValueType(); 3807 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 3808 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3809 // The only other way we can lower this is to turn it into a STORE, 3810 // LOAD pair, targetting a temporary location (a stack slot). 3811 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 3812 break; 3813 } 3814 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3815 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3816 case Legal: 3817 Tmp1 = LegalizeOp(Node->getOperand(0)); 3818 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3819 break; 3820 case Promote: 3821 Tmp1 = PromoteOp(Node->getOperand(0)); 3822 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 3823 break; 3824 } 3825 break; 3826 } 3827 case ISD::FP_ROUND: { 3828 MVT::ValueType DstVT = Op.getValueType(); 3829 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 3830 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3831 if (SrcVT == MVT::ppcf128) { 3832 SDOperand Lo; 3833 ExpandOp(Node->getOperand(0), Lo, Result); 3834 // Round it the rest of the way (e.g. to f32) if needed. 3835 if (DstVT!=MVT::f64) 3836 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 3837 break; 3838 } 3839 // The only other way we can lower this is to turn it into a STORE, 3840 // LOAD pair, targetting a temporary location (a stack slot). 3841 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 3842 break; 3843 } 3844 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3845 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3846 case Legal: 3847 Tmp1 = LegalizeOp(Node->getOperand(0)); 3848 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3849 break; 3850 case Promote: 3851 Tmp1 = PromoteOp(Node->getOperand(0)); 3852 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 3853 Node->getOperand(1)); 3854 break; 3855 } 3856 break; 3857 } 3858 case ISD::ANY_EXTEND: 3859 case ISD::ZERO_EXTEND: 3860 case ISD::SIGN_EXTEND: 3861 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3862 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3863 case Legal: 3864 Tmp1 = LegalizeOp(Node->getOperand(0)); 3865 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3866 TargetLowering::Custom) { 3867 Tmp2 = TLI.LowerOperation(Result, DAG); 3868 if (Tmp2.Val) { 3869 Tmp1 = Tmp2; 3870 } 3871 } 3872 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3873 break; 3874 case Promote: 3875 switch (Node->getOpcode()) { 3876 case ISD::ANY_EXTEND: 3877 Tmp1 = PromoteOp(Node->getOperand(0)); 3878 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3879 break; 3880 case ISD::ZERO_EXTEND: 3881 Result = PromoteOp(Node->getOperand(0)); 3882 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3883 Result = DAG.getZeroExtendInReg(Result, 3884 Node->getOperand(0).getValueType()); 3885 break; 3886 case ISD::SIGN_EXTEND: 3887 Result = PromoteOp(Node->getOperand(0)); 3888 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3889 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3890 Result, 3891 DAG.getValueType(Node->getOperand(0).getValueType())); 3892 break; 3893 } 3894 } 3895 break; 3896 case ISD::FP_ROUND_INREG: 3897 case ISD::SIGN_EXTEND_INREG: { 3898 Tmp1 = LegalizeOp(Node->getOperand(0)); 3899 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3900 3901 // If this operation is not supported, convert it to a shl/shr or load/store 3902 // pair. 3903 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3904 default: assert(0 && "This action not supported for this op yet!"); 3905 case TargetLowering::Legal: 3906 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3907 break; 3908 case TargetLowering::Expand: 3909 // If this is an integer extend and shifts are supported, do that. 3910 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3911 // NOTE: we could fall back on load/store here too for targets without 3912 // SAR. However, it is doubtful that any exist. 3913 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3914 MVT::getSizeInBits(ExtraVT); 3915 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3916 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3917 Node->getOperand(0), ShiftCst); 3918 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3919 Result, ShiftCst); 3920 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3921 // The only way we can lower this is to turn it into a TRUNCSTORE, 3922 // EXTLOAD pair, targetting a temporary location (a stack slot). 3923 3924 // NOTE: there is a choice here between constantly creating new stack 3925 // slots and always reusing the same one. We currently always create 3926 // new ones, as reuse may inhibit scheduling. 3927 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 3928 Node->getValueType(0)); 3929 } else { 3930 assert(0 && "Unknown op"); 3931 } 3932 break; 3933 } 3934 break; 3935 } 3936 case ISD::TRAMPOLINE: { 3937 SDOperand Ops[6]; 3938 for (unsigned i = 0; i != 6; ++i) 3939 Ops[i] = LegalizeOp(Node->getOperand(i)); 3940 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3941 // The only option for this node is to custom lower it. 3942 Result = TLI.LowerOperation(Result, DAG); 3943 assert(Result.Val && "Should always custom lower!"); 3944 3945 // Since trampoline produces two values, make sure to remember that we 3946 // legalized both of them. 3947 Tmp1 = LegalizeOp(Result.getValue(1)); 3948 Result = LegalizeOp(Result); 3949 AddLegalizedOperand(SDOperand(Node, 0), Result); 3950 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3951 return Op.ResNo ? Tmp1 : Result; 3952 } 3953 case ISD::FLT_ROUNDS_: { 3954 MVT::ValueType VT = Node->getValueType(0); 3955 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3956 default: assert(0 && "This action not supported for this op yet!"); 3957 case TargetLowering::Custom: 3958 Result = TLI.LowerOperation(Op, DAG); 3959 if (Result.Val) break; 3960 // Fall Thru 3961 case TargetLowering::Legal: 3962 // If this operation is not supported, lower it to constant 1 3963 Result = DAG.getConstant(1, VT); 3964 break; 3965 } 3966 } 3967 case ISD::TRAP: { 3968 MVT::ValueType VT = Node->getValueType(0); 3969 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3970 default: assert(0 && "This action not supported for this op yet!"); 3971 case TargetLowering::Legal: 3972 Tmp1 = LegalizeOp(Node->getOperand(0)); 3973 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3974 break; 3975 case TargetLowering::Custom: 3976 Result = TLI.LowerOperation(Op, DAG); 3977 if (Result.Val) break; 3978 // Fall Thru 3979 case TargetLowering::Expand: 3980 // If this operation is not supported, lower it to 'abort()' call 3981 Tmp1 = LegalizeOp(Node->getOperand(0)); 3982 TargetLowering::ArgListTy Args; 3983 std::pair<SDOperand,SDOperand> CallResult = 3984 TLI.LowerCallTo(Tmp1, Type::VoidTy, 3985 false, false, false, CallingConv::C, false, 3986 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 3987 Args, DAG); 3988 Result = CallResult.second; 3989 break; 3990 } 3991 break; 3992 } 3993 } 3994 3995 assert(Result.getValueType() == Op.getValueType() && 3996 "Bad legalization!"); 3997 3998 // Make sure that the generated code is itself legal. 3999 if (Result != Op) 4000 Result = LegalizeOp(Result); 4001 4002 // Note that LegalizeOp may be reentered even from single-use nodes, which 4003 // means that we always must cache transformed nodes. 4004 AddLegalizedOperand(Op, Result); 4005 return Result; 4006} 4007 4008/// PromoteOp - Given an operation that produces a value in an invalid type, 4009/// promote it to compute the value into a larger type. The produced value will 4010/// have the correct bits for the low portion of the register, but no guarantee 4011/// is made about the top bits: it may be zero, sign-extended, or garbage. 4012SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 4013 MVT::ValueType VT = Op.getValueType(); 4014 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4015 assert(getTypeAction(VT) == Promote && 4016 "Caller should expand or legalize operands that are not promotable!"); 4017 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 4018 "Cannot promote to smaller type!"); 4019 4020 SDOperand Tmp1, Tmp2, Tmp3; 4021 SDOperand Result; 4022 SDNode *Node = Op.Val; 4023 4024 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 4025 if (I != PromotedNodes.end()) return I->second; 4026 4027 switch (Node->getOpcode()) { 4028 case ISD::CopyFromReg: 4029 assert(0 && "CopyFromReg must be legal!"); 4030 default: 4031#ifndef NDEBUG 4032 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4033#endif 4034 assert(0 && "Do not know how to promote this operator!"); 4035 abort(); 4036 case ISD::UNDEF: 4037 Result = DAG.getNode(ISD::UNDEF, NVT); 4038 break; 4039 case ISD::Constant: 4040 if (VT != MVT::i1) 4041 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 4042 else 4043 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 4044 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4045 break; 4046 case ISD::ConstantFP: 4047 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 4048 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4049 break; 4050 4051 case ISD::SETCC: 4052 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 4053 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 4054 Node->getOperand(1), Node->getOperand(2)); 4055 break; 4056 4057 case ISD::TRUNCATE: 4058 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4059 case Legal: 4060 Result = LegalizeOp(Node->getOperand(0)); 4061 assert(Result.getValueType() >= NVT && 4062 "This truncation doesn't make sense!"); 4063 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 4064 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 4065 break; 4066 case Promote: 4067 // The truncation is not required, because we don't guarantee anything 4068 // about high bits anyway. 4069 Result = PromoteOp(Node->getOperand(0)); 4070 break; 4071 case Expand: 4072 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4073 // Truncate the low part of the expanded value to the result type 4074 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 4075 } 4076 break; 4077 case ISD::SIGN_EXTEND: 4078 case ISD::ZERO_EXTEND: 4079 case ISD::ANY_EXTEND: 4080 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4081 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4082 case Legal: 4083 // Input is legal? Just do extend all the way to the larger type. 4084 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4085 break; 4086 case Promote: 4087 // Promote the reg if it's smaller. 4088 Result = PromoteOp(Node->getOperand(0)); 4089 // The high bits are not guaranteed to be anything. Insert an extend. 4090 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4091 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4092 DAG.getValueType(Node->getOperand(0).getValueType())); 4093 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4094 Result = DAG.getZeroExtendInReg(Result, 4095 Node->getOperand(0).getValueType()); 4096 break; 4097 } 4098 break; 4099 case ISD::BIT_CONVERT: 4100 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4101 Node->getValueType(0)); 4102 Result = PromoteOp(Result); 4103 break; 4104 4105 case ISD::FP_EXTEND: 4106 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4107 case ISD::FP_ROUND: 4108 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4109 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4110 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4111 case Legal: 4112 if (Node->getConstantOperandVal(1) == 0) { 4113 // Input is legal? Do an FP_ROUND_INREG. 4114 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 4115 DAG.getValueType(VT)); 4116 } else { 4117 // Just remove the truncate, it isn't affecting the value. 4118 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 4119 Node->getOperand(1)); 4120 } 4121 break; 4122 } 4123 break; 4124 case ISD::SINT_TO_FP: 4125 case ISD::UINT_TO_FP: 4126 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4127 case Legal: 4128 // No extra round required here. 4129 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4130 break; 4131 4132 case Promote: 4133 Result = PromoteOp(Node->getOperand(0)); 4134 if (Node->getOpcode() == ISD::SINT_TO_FP) 4135 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4136 Result, 4137 DAG.getValueType(Node->getOperand(0).getValueType())); 4138 else 4139 Result = DAG.getZeroExtendInReg(Result, 4140 Node->getOperand(0).getValueType()); 4141 // No extra round required here. 4142 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 4143 break; 4144 case Expand: 4145 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4146 Node->getOperand(0)); 4147 // Round if we cannot tolerate excess precision. 4148 if (NoExcessFPPrecision) 4149 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4150 DAG.getValueType(VT)); 4151 break; 4152 } 4153 break; 4154 4155 case ISD::SIGN_EXTEND_INREG: 4156 Result = PromoteOp(Node->getOperand(0)); 4157 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4158 Node->getOperand(1)); 4159 break; 4160 case ISD::FP_TO_SINT: 4161 case ISD::FP_TO_UINT: 4162 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4163 case Legal: 4164 case Expand: 4165 Tmp1 = Node->getOperand(0); 4166 break; 4167 case Promote: 4168 // The input result is prerounded, so we don't have to do anything 4169 // special. 4170 Tmp1 = PromoteOp(Node->getOperand(0)); 4171 break; 4172 } 4173 // If we're promoting a UINT to a larger size, check to see if the new node 4174 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4175 // we can use that instead. This allows us to generate better code for 4176 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4177 // legal, such as PowerPC. 4178 if (Node->getOpcode() == ISD::FP_TO_UINT && 4179 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 4180 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 4181 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4182 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 4183 } else { 4184 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4185 } 4186 break; 4187 4188 case ISD::FABS: 4189 case ISD::FNEG: 4190 Tmp1 = PromoteOp(Node->getOperand(0)); 4191 assert(Tmp1.getValueType() == NVT); 4192 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4193 // NOTE: we do not have to do any extra rounding here for 4194 // NoExcessFPPrecision, because we know the input will have the appropriate 4195 // precision, and these operations don't modify precision at all. 4196 break; 4197 4198 case ISD::FSQRT: 4199 case ISD::FSIN: 4200 case ISD::FCOS: 4201 Tmp1 = PromoteOp(Node->getOperand(0)); 4202 assert(Tmp1.getValueType() == NVT); 4203 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4204 if (NoExcessFPPrecision) 4205 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4206 DAG.getValueType(VT)); 4207 break; 4208 4209 case ISD::FPOWI: { 4210 // Promote f32 powi to f64 powi. Note that this could insert a libcall 4211 // directly as well, which may be better. 4212 Tmp1 = PromoteOp(Node->getOperand(0)); 4213 assert(Tmp1.getValueType() == NVT); 4214 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 4215 if (NoExcessFPPrecision) 4216 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4217 DAG.getValueType(VT)); 4218 break; 4219 } 4220 4221 case ISD::AND: 4222 case ISD::OR: 4223 case ISD::XOR: 4224 case ISD::ADD: 4225 case ISD::SUB: 4226 case ISD::MUL: 4227 // The input may have strange things in the top bits of the registers, but 4228 // these operations don't care. They may have weird bits going out, but 4229 // that too is okay if they are integer operations. 4230 Tmp1 = PromoteOp(Node->getOperand(0)); 4231 Tmp2 = PromoteOp(Node->getOperand(1)); 4232 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4233 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4234 break; 4235 case ISD::FADD: 4236 case ISD::FSUB: 4237 case ISD::FMUL: 4238 Tmp1 = PromoteOp(Node->getOperand(0)); 4239 Tmp2 = PromoteOp(Node->getOperand(1)); 4240 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4241 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4242 4243 // Floating point operations will give excess precision that we may not be 4244 // able to tolerate. If we DO allow excess precision, just leave it, 4245 // otherwise excise it. 4246 // FIXME: Why would we need to round FP ops more than integer ones? 4247 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4248 if (NoExcessFPPrecision) 4249 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4250 DAG.getValueType(VT)); 4251 break; 4252 4253 case ISD::SDIV: 4254 case ISD::SREM: 4255 // These operators require that their input be sign extended. 4256 Tmp1 = PromoteOp(Node->getOperand(0)); 4257 Tmp2 = PromoteOp(Node->getOperand(1)); 4258 if (MVT::isInteger(NVT)) { 4259 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4260 DAG.getValueType(VT)); 4261 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4262 DAG.getValueType(VT)); 4263 } 4264 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4265 4266 // Perform FP_ROUND: this is probably overly pessimistic. 4267 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 4268 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4269 DAG.getValueType(VT)); 4270 break; 4271 case ISD::FDIV: 4272 case ISD::FREM: 4273 case ISD::FCOPYSIGN: 4274 // These operators require that their input be fp extended. 4275 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4276 case Expand: assert(0 && "not implemented"); 4277 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4278 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4279 } 4280 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4281 case Expand: assert(0 && "not implemented"); 4282 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4283 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4284 } 4285 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4286 4287 // Perform FP_ROUND: this is probably overly pessimistic. 4288 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4289 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4290 DAG.getValueType(VT)); 4291 break; 4292 4293 case ISD::UDIV: 4294 case ISD::UREM: 4295 // These operators require that their input be zero extended. 4296 Tmp1 = PromoteOp(Node->getOperand(0)); 4297 Tmp2 = PromoteOp(Node->getOperand(1)); 4298 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 4299 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4300 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4301 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4302 break; 4303 4304 case ISD::SHL: 4305 Tmp1 = PromoteOp(Node->getOperand(0)); 4306 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4307 break; 4308 case ISD::SRA: 4309 // The input value must be properly sign extended. 4310 Tmp1 = PromoteOp(Node->getOperand(0)); 4311 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4312 DAG.getValueType(VT)); 4313 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4314 break; 4315 case ISD::SRL: 4316 // The input value must be properly zero extended. 4317 Tmp1 = PromoteOp(Node->getOperand(0)); 4318 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4319 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4320 break; 4321 4322 case ISD::VAARG: 4323 Tmp1 = Node->getOperand(0); // Get the chain. 4324 Tmp2 = Node->getOperand(1); // Get the pointer. 4325 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4326 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4327 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 4328 } else { 4329 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4330 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 4331 // Increment the pointer, VAList, to the next vaarg 4332 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4333 DAG.getConstant(MVT::getSizeInBits(VT)/8, 4334 TLI.getPointerTy())); 4335 // Store the incremented VAList to the legalized pointer 4336 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 4337 // Load the actual argument out of the pointer VAList 4338 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4339 } 4340 // Remember that we legalized the chain. 4341 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4342 break; 4343 4344 case ISD::LOAD: { 4345 LoadSDNode *LD = cast<LoadSDNode>(Node); 4346 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4347 ? ISD::EXTLOAD : LD->getExtensionType(); 4348 Result = DAG.getExtLoad(ExtType, NVT, 4349 LD->getChain(), LD->getBasePtr(), 4350 LD->getSrcValue(), LD->getSrcValueOffset(), 4351 LD->getMemoryVT(), 4352 LD->isVolatile(), 4353 LD->getAlignment()); 4354 // Remember that we legalized the chain. 4355 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4356 break; 4357 } 4358 case ISD::SELECT: 4359 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4360 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4361 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 4362 break; 4363 case ISD::SELECT_CC: 4364 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4365 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4366 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4367 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4368 break; 4369 case ISD::BSWAP: 4370 Tmp1 = Node->getOperand(0); 4371 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4372 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4373 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4374 DAG.getConstant(MVT::getSizeInBits(NVT) - 4375 MVT::getSizeInBits(VT), 4376 TLI.getShiftAmountTy())); 4377 break; 4378 case ISD::CTPOP: 4379 case ISD::CTTZ: 4380 case ISD::CTLZ: 4381 // Zero extend the argument 4382 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4383 // Perform the larger operation, then subtract if needed. 4384 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4385 switch(Node->getOpcode()) { 4386 case ISD::CTPOP: 4387 Result = Tmp1; 4388 break; 4389 case ISD::CTTZ: 4390 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4391 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 4392 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 4393 ISD::SETEQ); 4394 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4395 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); 4396 break; 4397 case ISD::CTLZ: 4398 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4399 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4400 DAG.getConstant(MVT::getSizeInBits(NVT) - 4401 MVT::getSizeInBits(VT), NVT)); 4402 break; 4403 } 4404 break; 4405 case ISD::EXTRACT_SUBVECTOR: 4406 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4407 break; 4408 case ISD::EXTRACT_VECTOR_ELT: 4409 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4410 break; 4411 } 4412 4413 assert(Result.Val && "Didn't set a result!"); 4414 4415 // Make sure the result is itself legal. 4416 Result = LegalizeOp(Result); 4417 4418 // Remember that we promoted this! 4419 AddPromotedOperand(Op, Result); 4420 return Result; 4421} 4422 4423/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4424/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4425/// based on the vector type. The return type of this matches the element type 4426/// of the vector, which may not be legal for the target. 4427SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 4428 // We know that operand #0 is the Vec vector. If the index is a constant 4429 // or if the invec is a supported hardware type, we can use it. Otherwise, 4430 // lower to a store then an indexed load. 4431 SDOperand Vec = Op.getOperand(0); 4432 SDOperand Idx = Op.getOperand(1); 4433 4434 MVT::ValueType TVT = Vec.getValueType(); 4435 unsigned NumElems = MVT::getVectorNumElements(TVT); 4436 4437 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4438 default: assert(0 && "This action is not supported yet!"); 4439 case TargetLowering::Custom: { 4440 Vec = LegalizeOp(Vec); 4441 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4442 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 4443 if (Tmp3.Val) 4444 return Tmp3; 4445 break; 4446 } 4447 case TargetLowering::Legal: 4448 if (isTypeLegal(TVT)) { 4449 Vec = LegalizeOp(Vec); 4450 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4451 return Op; 4452 } 4453 break; 4454 case TargetLowering::Expand: 4455 break; 4456 } 4457 4458 if (NumElems == 1) { 4459 // This must be an access of the only element. Return it. 4460 Op = ScalarizeVectorOp(Vec); 4461 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4462 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 4463 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4464 SDOperand Lo, Hi; 4465 SplitVectorOp(Vec, Lo, Hi); 4466 if (CIdx->getValue() < NumLoElts) { 4467 Vec = Lo; 4468 } else { 4469 Vec = Hi; 4470 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts, 4471 Idx.getValueType()); 4472 } 4473 4474 // It's now an extract from the appropriate high or low part. Recurse. 4475 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4476 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4477 } else { 4478 // Store the value to a temporary stack slot, then LOAD the scalar 4479 // element back out. 4480 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4481 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4482 4483 // Add the offset to the index. 4484 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 4485 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4486 DAG.getConstant(EltSize, Idx.getValueType())); 4487 4488 if (MVT::getSizeInBits(Idx.getValueType()) > 4489 MVT::getSizeInBits(TLI.getPointerTy())) 4490 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4491 else 4492 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4493 4494 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4495 4496 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4497 } 4498 return Op; 4499} 4500 4501/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4502/// we assume the operation can be split if it is not already legal. 4503SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 4504 // We know that operand #0 is the Vec vector. For now we assume the index 4505 // is a constant and that the extracted result is a supported hardware type. 4506 SDOperand Vec = Op.getOperand(0); 4507 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 4508 4509 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); 4510 4511 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { 4512 // This must be an access of the desired vector length. Return it. 4513 return Vec; 4514 } 4515 4516 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4517 SDOperand Lo, Hi; 4518 SplitVectorOp(Vec, Lo, Hi); 4519 if (CIdx->getValue() < NumElems/2) { 4520 Vec = Lo; 4521 } else { 4522 Vec = Hi; 4523 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4524 } 4525 4526 // It's now an extract from the appropriate high or low part. Recurse. 4527 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4528 return ExpandEXTRACT_SUBVECTOR(Op); 4529} 4530 4531/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4532/// with condition CC on the current target. This usually involves legalizing 4533/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4534/// there may be no choice but to create a new SetCC node to represent the 4535/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4536/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 4537void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 4538 SDOperand &RHS, 4539 SDOperand &CC) { 4540 SDOperand Tmp1, Tmp2, Tmp3, Result; 4541 4542 switch (getTypeAction(LHS.getValueType())) { 4543 case Legal: 4544 Tmp1 = LegalizeOp(LHS); // LHS 4545 Tmp2 = LegalizeOp(RHS); // RHS 4546 break; 4547 case Promote: 4548 Tmp1 = PromoteOp(LHS); // LHS 4549 Tmp2 = PromoteOp(RHS); // RHS 4550 4551 // If this is an FP compare, the operands have already been extended. 4552 if (MVT::isInteger(LHS.getValueType())) { 4553 MVT::ValueType VT = LHS.getValueType(); 4554 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4555 4556 // Otherwise, we have to insert explicit sign or zero extends. Note 4557 // that we could insert sign extends for ALL conditions, but zero extend 4558 // is cheaper on many machines (an AND instead of two shifts), so prefer 4559 // it. 4560 switch (cast<CondCodeSDNode>(CC)->get()) { 4561 default: assert(0 && "Unknown integer comparison!"); 4562 case ISD::SETEQ: 4563 case ISD::SETNE: 4564 case ISD::SETUGE: 4565 case ISD::SETUGT: 4566 case ISD::SETULE: 4567 case ISD::SETULT: 4568 // ALL of these operations will work if we either sign or zero extend 4569 // the operands (including the unsigned comparisons!). Zero extend is 4570 // usually a simpler/cheaper operation, so prefer it. 4571 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4572 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4573 break; 4574 case ISD::SETGE: 4575 case ISD::SETGT: 4576 case ISD::SETLT: 4577 case ISD::SETLE: 4578 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4579 DAG.getValueType(VT)); 4580 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4581 DAG.getValueType(VT)); 4582 break; 4583 } 4584 } 4585 break; 4586 case Expand: { 4587 MVT::ValueType VT = LHS.getValueType(); 4588 if (VT == MVT::f32 || VT == MVT::f64) { 4589 // Expand into one or more soft-fp libcall(s). 4590 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 4591 switch (cast<CondCodeSDNode>(CC)->get()) { 4592 case ISD::SETEQ: 4593 case ISD::SETOEQ: 4594 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4595 break; 4596 case ISD::SETNE: 4597 case ISD::SETUNE: 4598 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4599 break; 4600 case ISD::SETGE: 4601 case ISD::SETOGE: 4602 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4603 break; 4604 case ISD::SETLT: 4605 case ISD::SETOLT: 4606 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4607 break; 4608 case ISD::SETLE: 4609 case ISD::SETOLE: 4610 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4611 break; 4612 case ISD::SETGT: 4613 case ISD::SETOGT: 4614 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4615 break; 4616 case ISD::SETUO: 4617 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4618 break; 4619 case ISD::SETO: 4620 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4621 break; 4622 default: 4623 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4624 switch (cast<CondCodeSDNode>(CC)->get()) { 4625 case ISD::SETONE: 4626 // SETONE = SETOLT | SETOGT 4627 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4628 // Fallthrough 4629 case ISD::SETUGT: 4630 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4631 break; 4632 case ISD::SETUGE: 4633 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4634 break; 4635 case ISD::SETULT: 4636 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4637 break; 4638 case ISD::SETULE: 4639 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4640 break; 4641 case ISD::SETUEQ: 4642 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4643 break; 4644 default: assert(0 && "Unsupported FP setcc!"); 4645 } 4646 } 4647 4648 SDOperand Dummy; 4649 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 4650 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4651 false /*sign irrelevant*/, Dummy); 4652 Tmp2 = DAG.getConstant(0, MVT::i32); 4653 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4654 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4655 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); 4656 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 4657 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4658 false /*sign irrelevant*/, Dummy); 4659 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, 4660 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4661 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4662 Tmp2 = SDOperand(); 4663 } 4664 LHS = Tmp1; 4665 RHS = Tmp2; 4666 return; 4667 } 4668 4669 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4670 ExpandOp(LHS, LHSLo, LHSHi); 4671 ExpandOp(RHS, RHSLo, RHSHi); 4672 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4673 4674 if (VT==MVT::ppcf128) { 4675 // FIXME: This generated code sucks. We want to generate 4676 // FCMP crN, hi1, hi2 4677 // BNE crN, L: 4678 // FCMP crN, lo1, lo2 4679 // The following can be improved, but not that much. 4680 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4681 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode); 4682 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4683 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE); 4684 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode); 4685 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4686 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4687 Tmp2 = SDOperand(); 4688 break; 4689 } 4690 4691 switch (CCCode) { 4692 case ISD::SETEQ: 4693 case ISD::SETNE: 4694 if (RHSLo == RHSHi) 4695 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4696 if (RHSCST->isAllOnesValue()) { 4697 // Comparison to -1. 4698 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4699 Tmp2 = RHSLo; 4700 break; 4701 } 4702 4703 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4704 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4705 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4706 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4707 break; 4708 default: 4709 // If this is a comparison of the sign bit, just look at the top part. 4710 // X > -1, x < 0 4711 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4712 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4713 CST->getValue() == 0) || // X < 0 4714 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4715 CST->isAllOnesValue())) { // X > -1 4716 Tmp1 = LHSHi; 4717 Tmp2 = RHSHi; 4718 break; 4719 } 4720 4721 // FIXME: This generated code sucks. 4722 ISD::CondCode LowCC; 4723 switch (CCCode) { 4724 default: assert(0 && "Unknown integer setcc!"); 4725 case ISD::SETLT: 4726 case ISD::SETULT: LowCC = ISD::SETULT; break; 4727 case ISD::SETGT: 4728 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4729 case ISD::SETLE: 4730 case ISD::SETULE: LowCC = ISD::SETULE; break; 4731 case ISD::SETGE: 4732 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4733 } 4734 4735 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4736 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4737 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4738 4739 // NOTE: on targets without efficient SELECT of bools, we can always use 4740 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4741 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4742 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, 4743 false, DagCombineInfo); 4744 if (!Tmp1.Val) 4745 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 4746 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4747 CCCode, false, DagCombineInfo); 4748 if (!Tmp2.Val) 4749 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC); 4750 4751 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4752 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4753 if ((Tmp1C && Tmp1C->getValue() == 0) || 4754 (Tmp2C && Tmp2C->getValue() == 0 && 4755 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4756 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4757 (Tmp2C && Tmp2C->getValue() == 1 && 4758 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4759 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4760 // low part is known false, returns high part. 4761 // For LE / GE, if high part is known false, ignore the low part. 4762 // For LT / GT, if high part is known true, ignore the low part. 4763 Tmp1 = Tmp2; 4764 Tmp2 = SDOperand(); 4765 } else { 4766 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4767 ISD::SETEQ, false, DagCombineInfo); 4768 if (!Result.Val) 4769 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4770 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4771 Result, Tmp1, Tmp2)); 4772 Tmp1 = Result; 4773 Tmp2 = SDOperand(); 4774 } 4775 } 4776 } 4777 } 4778 LHS = Tmp1; 4779 RHS = Tmp2; 4780} 4781 4782/// EmitStackConvert - Emit a store/load combination to the stack. This stores 4783/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 4784/// a load from the stack slot to DestVT, extending it if needed. 4785/// The resultant code need not be legal. 4786SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, 4787 MVT::ValueType SlotVT, 4788 MVT::ValueType DestVT) { 4789 // Create the stack frame object. 4790 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); 4791 4792 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 4793 int SPFI = StackPtrFI->getIndex(); 4794 4795 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType()); 4796 unsigned SlotSize = MVT::getSizeInBits(SlotVT); 4797 unsigned DestSize = MVT::getSizeInBits(DestVT); 4798 4799 // Emit a store to the stack slot. Use a truncstore if the input value is 4800 // later than DestVT. 4801 SDOperand Store; 4802 if (SrcSize > SlotSize) 4803 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, 4804 PseudoSourceValue::getFixedStack(), 4805 SPFI, SlotVT); 4806 else { 4807 assert(SrcSize == SlotSize && "Invalid store"); 4808 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, 4809 PseudoSourceValue::getFixedStack(), 4810 SPFI, SlotVT); 4811 } 4812 4813 // Result is a load from the stack slot. 4814 if (SlotSize == DestSize) 4815 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4816 4817 assert(SlotSize < DestSize && "Unknown extension!"); 4818 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT); 4819} 4820 4821SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4822 // Create a vector sized/aligned stack slot, store the value to element #0, 4823 // then load the whole vector back out. 4824 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4825 4826 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 4827 int SPFI = StackPtrFI->getIndex(); 4828 4829 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4830 PseudoSourceValue::getFixedStack(), SPFI); 4831 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, 4832 PseudoSourceValue::getFixedStack(), SPFI); 4833} 4834 4835 4836/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4837/// support the operation, but do support the resultant vector type. 4838SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4839 4840 // If the only non-undef value is the low element, turn this into a 4841 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4842 unsigned NumElems = Node->getNumOperands(); 4843 bool isOnlyLowElement = true; 4844 SDOperand SplatValue = Node->getOperand(0); 4845 std::map<SDOperand, std::vector<unsigned> > Values; 4846 Values[SplatValue].push_back(0); 4847 bool isConstant = true; 4848 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4849 SplatValue.getOpcode() != ISD::UNDEF) 4850 isConstant = false; 4851 4852 for (unsigned i = 1; i < NumElems; ++i) { 4853 SDOperand V = Node->getOperand(i); 4854 Values[V].push_back(i); 4855 if (V.getOpcode() != ISD::UNDEF) 4856 isOnlyLowElement = false; 4857 if (SplatValue != V) 4858 SplatValue = SDOperand(0,0); 4859 4860 // If this isn't a constant element or an undef, we can't use a constant 4861 // pool load. 4862 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4863 V.getOpcode() != ISD::UNDEF) 4864 isConstant = false; 4865 } 4866 4867 if (isOnlyLowElement) { 4868 // If the low element is an undef too, then this whole things is an undef. 4869 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4870 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4871 // Otherwise, turn this into a scalar_to_vector node. 4872 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4873 Node->getOperand(0)); 4874 } 4875 4876 // If all elements are constants, create a load from the constant pool. 4877 if (isConstant) { 4878 MVT::ValueType VT = Node->getValueType(0); 4879 const Type *OpNTy = 4880 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 4881 std::vector<Constant*> CV; 4882 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4883 if (ConstantFPSDNode *V = 4884 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4885 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF())); 4886 } else if (ConstantSDNode *V = 4887 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4888 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 4889 } else { 4890 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4891 CV.push_back(UndefValue::get(OpNTy)); 4892 } 4893 } 4894 Constant *CP = ConstantVector::get(CV); 4895 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4896 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4897 PseudoSourceValue::getConstantPool(), 0); 4898 } 4899 4900 if (SplatValue.Val) { // Splat of one value? 4901 // Build the shuffle constant vector: <0, 0, 0, 0> 4902 MVT::ValueType MaskVT = 4903 MVT::getIntVectorWithNumElements(NumElems); 4904 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); 4905 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4906 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4907 &ZeroVec[0], ZeroVec.size()); 4908 4909 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4910 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 4911 // Get the splatted value into the low element of a vector register. 4912 SDOperand LowValVec = 4913 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 4914 4915 // Return shuffle(LowValVec, undef, <0,0,0,0>) 4916 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 4917 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 4918 SplatMask); 4919 } 4920 } 4921 4922 // If there are only two unique elements, we may be able to turn this into a 4923 // vector shuffle. 4924 if (Values.size() == 2) { 4925 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 4926 MVT::ValueType MaskVT = 4927 MVT::getIntVectorWithNumElements(NumElems); 4928 std::vector<SDOperand> MaskVec(NumElems); 4929 unsigned i = 0; 4930 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4931 E = Values.end(); I != E; ++I) { 4932 for (std::vector<unsigned>::iterator II = I->second.begin(), 4933 EE = I->second.end(); II != EE; ++II) 4934 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT)); 4935 i += NumElems; 4936 } 4937 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4938 &MaskVec[0], MaskVec.size()); 4939 4940 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4941 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 4942 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 4943 SmallVector<SDOperand, 8> Ops; 4944 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4945 E = Values.end(); I != E; ++I) { 4946 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4947 I->first); 4948 Ops.push_back(Op); 4949 } 4950 Ops.push_back(ShuffleMask); 4951 4952 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 4953 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 4954 &Ops[0], Ops.size()); 4955 } 4956 } 4957 4958 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 4959 // aligned object on the stack, store each element into it, then load 4960 // the result as a vector. 4961 MVT::ValueType VT = Node->getValueType(0); 4962 // Create the stack frame object. 4963 SDOperand FIPtr = DAG.CreateStackTemporary(VT); 4964 4965 // Emit a store of each element to the stack slot. 4966 SmallVector<SDOperand, 8> Stores; 4967 unsigned TypeByteSize = 4968 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 4969 // Store (in the right endianness) the elements to memory. 4970 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4971 // Ignore undef elements. 4972 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4973 4974 unsigned Offset = TypeByteSize*i; 4975 4976 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 4977 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 4978 4979 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 4980 NULL, 0)); 4981 } 4982 4983 SDOperand StoreChain; 4984 if (!Stores.empty()) // Not all undef elements? 4985 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4986 &Stores[0], Stores.size()); 4987 else 4988 StoreChain = DAG.getEntryNode(); 4989 4990 // Result is a load from the stack slot. 4991 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 4992} 4993 4994void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 4995 SDOperand Op, SDOperand Amt, 4996 SDOperand &Lo, SDOperand &Hi) { 4997 // Expand the subcomponents. 4998 SDOperand LHSL, LHSH; 4999 ExpandOp(Op, LHSL, LHSH); 5000 5001 SDOperand Ops[] = { LHSL, LHSH, Amt }; 5002 MVT::ValueType VT = LHSL.getValueType(); 5003 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5004 Hi = Lo.getValue(1); 5005} 5006 5007 5008/// ExpandShift - Try to find a clever way to expand this shift operation out to 5009/// smaller elements. If we can't find a way that is more efficient than a 5010/// libcall on this target, return false. Otherwise, return true with the 5011/// low-parts expanded into Lo and Hi. 5012bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 5013 SDOperand &Lo, SDOperand &Hi) { 5014 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5015 "This is not a shift!"); 5016 5017 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5018 SDOperand ShAmt = LegalizeOp(Amt); 5019 MVT::ValueType ShTy = ShAmt.getValueType(); 5020 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 5021 unsigned NVTBits = MVT::getSizeInBits(NVT); 5022 5023 // Handle the case when Amt is an immediate. 5024 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 5025 unsigned Cst = CN->getValue(); 5026 // Expand the incoming operand to be shifted, so that we have its parts 5027 SDOperand InL, InH; 5028 ExpandOp(Op, InL, InH); 5029 switch(Opc) { 5030 case ISD::SHL: 5031 if (Cst > VTBits) { 5032 Lo = DAG.getConstant(0, NVT); 5033 Hi = DAG.getConstant(0, NVT); 5034 } else if (Cst > NVTBits) { 5035 Lo = DAG.getConstant(0, NVT); 5036 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5037 } else if (Cst == NVTBits) { 5038 Lo = DAG.getConstant(0, NVT); 5039 Hi = InL; 5040 } else { 5041 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 5042 Hi = DAG.getNode(ISD::OR, NVT, 5043 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 5044 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 5045 } 5046 return true; 5047 case ISD::SRL: 5048 if (Cst > VTBits) { 5049 Lo = DAG.getConstant(0, NVT); 5050 Hi = DAG.getConstant(0, NVT); 5051 } else if (Cst > NVTBits) { 5052 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5053 Hi = DAG.getConstant(0, NVT); 5054 } else if (Cst == NVTBits) { 5055 Lo = InH; 5056 Hi = DAG.getConstant(0, NVT); 5057 } else { 5058 Lo = DAG.getNode(ISD::OR, NVT, 5059 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5060 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5061 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 5062 } 5063 return true; 5064 case ISD::SRA: 5065 if (Cst > VTBits) { 5066 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 5067 DAG.getConstant(NVTBits-1, ShTy)); 5068 } else if (Cst > NVTBits) { 5069 Lo = DAG.getNode(ISD::SRA, NVT, InH, 5070 DAG.getConstant(Cst-NVTBits, ShTy)); 5071 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5072 DAG.getConstant(NVTBits-1, ShTy)); 5073 } else if (Cst == NVTBits) { 5074 Lo = InH; 5075 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5076 DAG.getConstant(NVTBits-1, ShTy)); 5077 } else { 5078 Lo = DAG.getNode(ISD::OR, NVT, 5079 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5080 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5081 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 5082 } 5083 return true; 5084 } 5085 } 5086 5087 // Okay, the shift amount isn't constant. However, if we can tell that it is 5088 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5089 uint64_t Mask = NVTBits, KnownZero, KnownOne; 5090 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5091 5092 // If we know that the high bit of the shift amount is one, then we can do 5093 // this as a couple of simple shifts. 5094 if (KnownOne & Mask) { 5095 // Mask out the high bit, which we know is set. 5096 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 5097 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5098 5099 // Expand the incoming operand to be shifted, so that we have its parts 5100 SDOperand InL, InH; 5101 ExpandOp(Op, InL, InH); 5102 switch(Opc) { 5103 case ISD::SHL: 5104 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5105 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 5106 return true; 5107 case ISD::SRL: 5108 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5109 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 5110 return true; 5111 case ISD::SRA: 5112 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 5113 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5114 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 5115 return true; 5116 } 5117 } 5118 5119 // If we know that the high bit of the shift amount is zero, then we can do 5120 // this as a couple of simple shifts. 5121 if (KnownZero & Mask) { 5122 // Compute 32-amt. 5123 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 5124 DAG.getConstant(NVTBits, Amt.getValueType()), 5125 Amt); 5126 5127 // Expand the incoming operand to be shifted, so that we have its parts 5128 SDOperand InL, InH; 5129 ExpandOp(Op, InL, InH); 5130 switch(Opc) { 5131 case ISD::SHL: 5132 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 5133 Hi = DAG.getNode(ISD::OR, NVT, 5134 DAG.getNode(ISD::SHL, NVT, InH, Amt), 5135 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 5136 return true; 5137 case ISD::SRL: 5138 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 5139 Lo = DAG.getNode(ISD::OR, NVT, 5140 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5141 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5142 return true; 5143 case ISD::SRA: 5144 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 5145 Lo = DAG.getNode(ISD::OR, NVT, 5146 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5147 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5148 return true; 5149 } 5150 } 5151 5152 return false; 5153} 5154 5155 5156// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5157// does not fit into a register, return the lo part and set the hi part to the 5158// by-reg argument. If it does fit into a single register, return the result 5159// and leave the Hi part unset. 5160SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 5161 bool isSigned, SDOperand &Hi) { 5162 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5163 // The input chain to this libcall is the entry node of the function. 5164 // Legalizing the call will automatically add the previous call to the 5165 // dependence. 5166 SDOperand InChain = DAG.getEntryNode(); 5167 5168 TargetLowering::ArgListTy Args; 5169 TargetLowering::ArgListEntry Entry; 5170 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5171 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 5172 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 5173 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5174 Entry.isSExt = isSigned; 5175 Entry.isZExt = !isSigned; 5176 Args.push_back(Entry); 5177 } 5178 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 5179 5180 // Splice the libcall in wherever FindInputOutputChains tells us to. 5181 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 5182 std::pair<SDOperand,SDOperand> CallInfo = 5183 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C, 5184 false, Callee, Args, DAG); 5185 5186 // Legalize the call sequence, starting with the chain. This will advance 5187 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5188 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5189 LegalizeOp(CallInfo.second); 5190 SDOperand Result; 5191 switch (getTypeAction(CallInfo.first.getValueType())) { 5192 default: assert(0 && "Unknown thing"); 5193 case Legal: 5194 Result = CallInfo.first; 5195 break; 5196 case Expand: 5197 ExpandOp(CallInfo.first, Result, Hi); 5198 break; 5199 } 5200 return Result; 5201} 5202 5203 5204/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5205/// 5206SDOperand SelectionDAGLegalize:: 5207ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 5208 assert(getTypeAction(Source.getValueType()) == Expand && 5209 "This is not an expansion!"); 5210 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 5211 5212 if (!isSigned) { 5213 assert(Source.getValueType() == MVT::i64 && 5214 "This only works for 64-bit -> FP"); 5215 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 5216 // incoming integer is set. To handle this, we dynamically test to see if 5217 // it is set, and, if so, add a fudge factor. 5218 SDOperand Lo, Hi; 5219 ExpandOp(Source, Lo, Hi); 5220 5221 // If this is unsigned, and not supported, first perform the conversion to 5222 // signed, then adjust the result if the sign bit is set. 5223 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 5224 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 5225 5226 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 5227 DAG.getConstant(0, Hi.getValueType()), 5228 ISD::SETLT); 5229 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5230 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5231 SignSet, Four, Zero); 5232 uint64_t FF = 0x5f800000ULL; 5233 if (TLI.isLittleEndian()) FF <<= 32; 5234 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5235 5236 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5237 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5238 SDOperand FudgeInReg; 5239 if (DestTy == MVT::f32) 5240 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5241 PseudoSourceValue::getConstantPool(), 0); 5242 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) 5243 // FIXME: Avoid the extend by construction the right constantpool? 5244 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5245 CPIdx, 5246 PseudoSourceValue::getConstantPool(), 0, 5247 MVT::f32); 5248 else 5249 assert(0 && "Unexpected conversion"); 5250 5251 MVT::ValueType SCVT = SignedConv.getValueType(); 5252 if (SCVT != DestTy) { 5253 // Destination type needs to be expanded as well. The FADD now we are 5254 // constructing will be expanded into a libcall. 5255 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { 5256 assert(SCVT == MVT::i32 && DestTy == MVT::f64); 5257 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, 5258 SignedConv, SignedConv.getValue(1)); 5259 } 5260 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5261 } 5262 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5263 } 5264 5265 // Check to see if the target has a custom way to lower this. If so, use it. 5266 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 5267 default: assert(0 && "This action not implemented for this operation!"); 5268 case TargetLowering::Legal: 5269 case TargetLowering::Expand: 5270 break; // This case is handled below. 5271 case TargetLowering::Custom: { 5272 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5273 Source), DAG); 5274 if (NV.Val) 5275 return LegalizeOp(NV); 5276 break; // The target decided this was legal after all 5277 } 5278 } 5279 5280 // Expand the source, then glue it back together for the call. We must expand 5281 // the source in case it is shared (this pass of legalize must traverse it). 5282 SDOperand SrcLo, SrcHi; 5283 ExpandOp(Source, SrcLo, SrcHi); 5284 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 5285 5286 RTLIB::Libcall LC; 5287 if (DestTy == MVT::f32) 5288 LC = RTLIB::SINTTOFP_I64_F32; 5289 else { 5290 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 5291 LC = RTLIB::SINTTOFP_I64_F64; 5292 } 5293 5294 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 5295 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5296 SDOperand UnusedHiPart; 5297 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 5298 UnusedHiPart); 5299} 5300 5301/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5302/// INT_TO_FP operation of the specified operand when the target requests that 5303/// we expand it. At this point, we know that the result and operand types are 5304/// legal for the target. 5305SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5306 SDOperand Op0, 5307 MVT::ValueType DestVT) { 5308 if (Op0.getValueType() == MVT::i32) { 5309 // simple 32-bit [signed|unsigned] integer to float/double expansion 5310 5311 // Get the stack frame index of a 8 byte buffer. 5312 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64); 5313 5314 // word offset constant for Hi/Lo address computation 5315 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5316 // set up Hi and Lo (into buffer) address based on endian 5317 SDOperand Hi = StackSlot; 5318 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5319 if (TLI.isLittleEndian()) 5320 std::swap(Hi, Lo); 5321 5322 // if signed map to unsigned space 5323 SDOperand Op0Mapped; 5324 if (isSigned) { 5325 // constant used to invert sign bit (signed to unsigned mapping) 5326 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5327 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5328 } else { 5329 Op0Mapped = Op0; 5330 } 5331 // store the lo of the constructed double - based on integer input 5332 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 5333 Op0Mapped, Lo, NULL, 0); 5334 // initial hi portion of constructed double 5335 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5336 // store the hi of the constructed double - biased exponent 5337 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5338 // load the constructed double 5339 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5340 // FP constant to bias correct the final result 5341 SDOperand Bias = DAG.getConstantFP(isSigned ? 5342 BitsToDouble(0x4330000080000000ULL) 5343 : BitsToDouble(0x4330000000000000ULL), 5344 MVT::f64); 5345 // subtract the bias 5346 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5347 // final result 5348 SDOperand Result; 5349 // handle final rounding 5350 if (DestVT == MVT::f64) { 5351 // do nothing 5352 Result = Sub; 5353 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) { 5354 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 5355 DAG.getIntPtrConstant(0)); 5356 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) { 5357 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5358 } 5359 return Result; 5360 } 5361 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5362 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5363 5364 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 5365 DAG.getConstant(0, Op0.getValueType()), 5366 ISD::SETLT); 5367 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5368 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5369 SignSet, Four, Zero); 5370 5371 // If the sign bit of the integer is set, the large number will be treated 5372 // as a negative number. To counteract this, the dynamic code adds an 5373 // offset depending on the data type. 5374 uint64_t FF; 5375 switch (Op0.getValueType()) { 5376 default: assert(0 && "Unsupported integer type!"); 5377 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5378 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5379 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5380 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5381 } 5382 if (TLI.isLittleEndian()) FF <<= 32; 5383 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5384 5385 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5386 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5387 SDOperand FudgeInReg; 5388 if (DestVT == MVT::f32) 5389 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5390 PseudoSourceValue::getConstantPool(), 0); 5391 else { 5392 FudgeInReg = 5393 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5394 DAG.getEntryNode(), CPIdx, 5395 PseudoSourceValue::getConstantPool(), 0, 5396 MVT::f32)); 5397 } 5398 5399 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5400} 5401 5402/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5403/// *INT_TO_FP operation of the specified operand when the target requests that 5404/// we promote it. At this point, we know that the result and operand types are 5405/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5406/// operation that takes a larger input. 5407SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 5408 MVT::ValueType DestVT, 5409 bool isSigned) { 5410 // First step, figure out the appropriate *INT_TO_FP operation to use. 5411 MVT::ValueType NewInTy = LegalOp.getValueType(); 5412 5413 unsigned OpToUse = 0; 5414 5415 // Scan for the appropriate larger type to use. 5416 while (1) { 5417 NewInTy = (MVT::ValueType)(NewInTy+1); 5418 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 5419 5420 // If the target supports SINT_TO_FP of this type, use it. 5421 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5422 default: break; 5423 case TargetLowering::Legal: 5424 if (!TLI.isTypeLegal(NewInTy)) 5425 break; // Can't use this datatype. 5426 // FALL THROUGH. 5427 case TargetLowering::Custom: 5428 OpToUse = ISD::SINT_TO_FP; 5429 break; 5430 } 5431 if (OpToUse) break; 5432 if (isSigned) continue; 5433 5434 // If the target supports UINT_TO_FP of this type, use it. 5435 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5436 default: break; 5437 case TargetLowering::Legal: 5438 if (!TLI.isTypeLegal(NewInTy)) 5439 break; // Can't use this datatype. 5440 // FALL THROUGH. 5441 case TargetLowering::Custom: 5442 OpToUse = ISD::UINT_TO_FP; 5443 break; 5444 } 5445 if (OpToUse) break; 5446 5447 // Otherwise, try a larger type. 5448 } 5449 5450 // Okay, we found the operation and type to use. Zero extend our input to the 5451 // desired type then run the operation on it. 5452 return DAG.getNode(OpToUse, DestVT, 5453 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5454 NewInTy, LegalOp)); 5455} 5456 5457/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5458/// FP_TO_*INT operation of the specified operand when the target requests that 5459/// we promote it. At this point, we know that the result and operand types are 5460/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5461/// operation that returns a larger result. 5462SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 5463 MVT::ValueType DestVT, 5464 bool isSigned) { 5465 // First step, figure out the appropriate FP_TO*INT operation to use. 5466 MVT::ValueType NewOutTy = DestVT; 5467 5468 unsigned OpToUse = 0; 5469 5470 // Scan for the appropriate larger type to use. 5471 while (1) { 5472 NewOutTy = (MVT::ValueType)(NewOutTy+1); 5473 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 5474 5475 // If the target supports FP_TO_SINT returning this type, use it. 5476 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5477 default: break; 5478 case TargetLowering::Legal: 5479 if (!TLI.isTypeLegal(NewOutTy)) 5480 break; // Can't use this datatype. 5481 // FALL THROUGH. 5482 case TargetLowering::Custom: 5483 OpToUse = ISD::FP_TO_SINT; 5484 break; 5485 } 5486 if (OpToUse) break; 5487 5488 // If the target supports FP_TO_UINT of this type, use it. 5489 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5490 default: break; 5491 case TargetLowering::Legal: 5492 if (!TLI.isTypeLegal(NewOutTy)) 5493 break; // Can't use this datatype. 5494 // FALL THROUGH. 5495 case TargetLowering::Custom: 5496 OpToUse = ISD::FP_TO_UINT; 5497 break; 5498 } 5499 if (OpToUse) break; 5500 5501 // Otherwise, try a larger type. 5502 } 5503 5504 5505 // Okay, we found the operation and type to use. 5506 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5507 5508 // If the operation produces an invalid type, it must be custom lowered. Use 5509 // the target lowering hooks to expand it. Just keep the low part of the 5510 // expanded operation, we know that we're truncating anyway. 5511 if (getTypeAction(NewOutTy) == Expand) { 5512 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0); 5513 assert(Operation.Val && "Didn't return anything"); 5514 } 5515 5516 // Truncate the result of the extended FP_TO_*INT operation to the desired 5517 // size. 5518 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5519} 5520 5521/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5522/// 5523SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 5524 MVT::ValueType VT = Op.getValueType(); 5525 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 5526 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5527 switch (VT) { 5528 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5529 case MVT::i16: 5530 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5531 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5532 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5533 case MVT::i32: 5534 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5535 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5536 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5537 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5538 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5539 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5540 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5541 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5542 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5543 case MVT::i64: 5544 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5545 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5546 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5547 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5548 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5549 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5550 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5551 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5552 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5553 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5554 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5555 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5556 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5557 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5558 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5559 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5560 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5561 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5562 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5563 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5564 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5565 } 5566} 5567 5568/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5569/// 5570SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 5571 switch (Opc) { 5572 default: assert(0 && "Cannot expand this yet!"); 5573 case ISD::CTPOP: { 5574 static const uint64_t mask[6] = { 5575 0x5555555555555555ULL, 0x3333333333333333ULL, 5576 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5577 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5578 }; 5579 MVT::ValueType VT = Op.getValueType(); 5580 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5581 unsigned len = MVT::getSizeInBits(VT); 5582 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5583 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5584 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 5585 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5586 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5587 DAG.getNode(ISD::AND, VT, 5588 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5589 } 5590 return Op; 5591 } 5592 case ISD::CTLZ: { 5593 // for now, we do this: 5594 // x = x | (x >> 1); 5595 // x = x | (x >> 2); 5596 // ... 5597 // x = x | (x >>16); 5598 // x = x | (x >>32); // for 64-bit input 5599 // return popcount(~x); 5600 // 5601 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5602 MVT::ValueType VT = Op.getValueType(); 5603 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5604 unsigned len = MVT::getSizeInBits(VT); 5605 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5606 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5607 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5608 } 5609 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5610 return DAG.getNode(ISD::CTPOP, VT, Op); 5611 } 5612 case ISD::CTTZ: { 5613 // for now, we use: { return popcount(~x & (x - 1)); } 5614 // unless the target has ctlz but not ctpop, in which case we use: 5615 // { return 32 - nlz(~x & (x-1)); } 5616 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5617 MVT::ValueType VT = Op.getValueType(); 5618 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 5619 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 5620 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5621 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5622 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5623 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5624 TLI.isOperationLegal(ISD::CTLZ, VT)) 5625 return DAG.getNode(ISD::SUB, VT, 5626 DAG.getConstant(MVT::getSizeInBits(VT), VT), 5627 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5628 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5629 } 5630 } 5631} 5632 5633/// ExpandOp - Expand the specified SDOperand into its two component pieces 5634/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5635/// LegalizeNodes map is filled in for any results that are not expanded, the 5636/// ExpandedNodes map is filled in for any results that are expanded, and the 5637/// Lo/Hi values are returned. 5638void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 5639 MVT::ValueType VT = Op.getValueType(); 5640 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 5641 SDNode *Node = Op.Val; 5642 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5643 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 5644 MVT::isVector(VT)) && 5645 "Cannot expand to FP value or to larger int value!"); 5646 5647 // See if we already expanded it. 5648 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5649 = ExpandedNodes.find(Op); 5650 if (I != ExpandedNodes.end()) { 5651 Lo = I->second.first; 5652 Hi = I->second.second; 5653 return; 5654 } 5655 5656 switch (Node->getOpcode()) { 5657 case ISD::CopyFromReg: 5658 assert(0 && "CopyFromReg must be legal!"); 5659 case ISD::FP_ROUND_INREG: 5660 if (VT == MVT::ppcf128 && 5661 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5662 TargetLowering::Custom) { 5663 SDOperand SrcLo, SrcHi, Src; 5664 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5665 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5666 SDOperand Result = TLI.LowerOperation( 5667 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5668 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5669 Lo = Result.Val->getOperand(0); 5670 Hi = Result.Val->getOperand(1); 5671 break; 5672 } 5673 // fall through 5674 default: 5675#ifndef NDEBUG 5676 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5677#endif 5678 assert(0 && "Do not know how to expand this operator!"); 5679 abort(); 5680 case ISD::EXTRACT_VECTOR_ELT: 5681 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5682 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5683 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5684 return ExpandOp(Lo, Lo, Hi); 5685 case ISD::UNDEF: 5686 NVT = TLI.getTypeToExpandTo(VT); 5687 Lo = DAG.getNode(ISD::UNDEF, NVT); 5688 Hi = DAG.getNode(ISD::UNDEF, NVT); 5689 break; 5690 case ISD::Constant: { 5691 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 5692 Lo = DAG.getConstant(Cst, NVT); 5693 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 5694 break; 5695 } 5696 case ISD::ConstantFP: { 5697 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5698 if (CFP->getValueType(0) == MVT::ppcf128) { 5699 APInt api = CFP->getValueAPF().convertToAPInt(); 5700 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5701 MVT::f64); 5702 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5703 MVT::f64); 5704 break; 5705 } 5706 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5707 if (getTypeAction(Lo.getValueType()) == Expand) 5708 ExpandOp(Lo, Lo, Hi); 5709 break; 5710 } 5711 case ISD::BUILD_PAIR: 5712 // Return the operands. 5713 Lo = Node->getOperand(0); 5714 Hi = Node->getOperand(1); 5715 break; 5716 5717 case ISD::MERGE_VALUES: 5718 if (Node->getNumValues() == 1) { 5719 ExpandOp(Op.getOperand(0), Lo, Hi); 5720 break; 5721 } 5722 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5723 assert(Op.ResNo == 0 && Node->getNumValues() == 2 && 5724 Op.getValue(1).getValueType() == MVT::Other && 5725 "unhandled MERGE_VALUES"); 5726 ExpandOp(Op.getOperand(0), Lo, Hi); 5727 // Remember that we legalized the chain. 5728 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5729 break; 5730 5731 case ISD::SIGN_EXTEND_INREG: 5732 ExpandOp(Node->getOperand(0), Lo, Hi); 5733 // sext_inreg the low part if needed. 5734 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5735 5736 // The high part gets the sign extension from the lo-part. This handles 5737 // things like sextinreg V:i64 from i8. 5738 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5739 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 5740 TLI.getShiftAmountTy())); 5741 break; 5742 5743 case ISD::BSWAP: { 5744 ExpandOp(Node->getOperand(0), Lo, Hi); 5745 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5746 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5747 Lo = TempLo; 5748 break; 5749 } 5750 5751 case ISD::CTPOP: 5752 ExpandOp(Node->getOperand(0), Lo, Hi); 5753 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5754 DAG.getNode(ISD::CTPOP, NVT, Lo), 5755 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5756 Hi = DAG.getConstant(0, NVT); 5757 break; 5758 5759 case ISD::CTLZ: { 5760 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5761 ExpandOp(Node->getOperand(0), Lo, Hi); 5762 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5763 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5764 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 5765 ISD::SETNE); 5766 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5767 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5768 5769 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5770 Hi = DAG.getConstant(0, NVT); 5771 break; 5772 } 5773 5774 case ISD::CTTZ: { 5775 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5776 ExpandOp(Node->getOperand(0), Lo, Hi); 5777 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5778 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5779 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 5780 ISD::SETNE); 5781 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5782 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5783 5784 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5785 Hi = DAG.getConstant(0, NVT); 5786 break; 5787 } 5788 5789 case ISD::VAARG: { 5790 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5791 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5792 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5793 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5794 5795 // Remember that we legalized the chain. 5796 Hi = LegalizeOp(Hi); 5797 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5798 if (TLI.isBigEndian()) 5799 std::swap(Lo, Hi); 5800 break; 5801 } 5802 5803 case ISD::LOAD: { 5804 LoadSDNode *LD = cast<LoadSDNode>(Node); 5805 SDOperand Ch = LD->getChain(); // Legalize the chain. 5806 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5807 ISD::LoadExtType ExtType = LD->getExtensionType(); 5808 int SVOffset = LD->getSrcValueOffset(); 5809 unsigned Alignment = LD->getAlignment(); 5810 bool isVolatile = LD->isVolatile(); 5811 5812 if (ExtType == ISD::NON_EXTLOAD) { 5813 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5814 isVolatile, Alignment); 5815 if (VT == MVT::f32 || VT == MVT::f64) { 5816 // f32->i32 or f64->i64 one to one expansion. 5817 // Remember that we legalized the chain. 5818 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5819 // Recursively expand the new load. 5820 if (getTypeAction(NVT) == Expand) 5821 ExpandOp(Lo, Lo, Hi); 5822 break; 5823 } 5824 5825 // Increment the pointer to the other half. 5826 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 5827 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5828 DAG.getIntPtrConstant(IncrementSize)); 5829 SVOffset += IncrementSize; 5830 Alignment = MinAlign(Alignment, IncrementSize); 5831 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5832 isVolatile, Alignment); 5833 5834 // Build a factor node to remember that this load is independent of the 5835 // other one. 5836 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5837 Hi.getValue(1)); 5838 5839 // Remember that we legalized the chain. 5840 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5841 if (TLI.isBigEndian()) 5842 std::swap(Lo, Hi); 5843 } else { 5844 MVT::ValueType EVT = LD->getMemoryVT(); 5845 5846 if ((VT == MVT::f64 && EVT == MVT::f32) || 5847 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 5848 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5849 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5850 SVOffset, isVolatile, Alignment); 5851 // Remember that we legalized the chain. 5852 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 5853 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 5854 break; 5855 } 5856 5857 if (EVT == NVT) 5858 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 5859 SVOffset, isVolatile, Alignment); 5860 else 5861 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 5862 SVOffset, EVT, isVolatile, 5863 Alignment); 5864 5865 // Remember that we legalized the chain. 5866 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5867 5868 if (ExtType == ISD::SEXTLOAD) { 5869 // The high part is obtained by SRA'ing all but one of the bits of the 5870 // lo part. 5871 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5872 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5873 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5874 } else if (ExtType == ISD::ZEXTLOAD) { 5875 // The high part is just a zero. 5876 Hi = DAG.getConstant(0, NVT); 5877 } else /* if (ExtType == ISD::EXTLOAD) */ { 5878 // The high part is undefined. 5879 Hi = DAG.getNode(ISD::UNDEF, NVT); 5880 } 5881 } 5882 break; 5883 } 5884 case ISD::AND: 5885 case ISD::OR: 5886 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 5887 SDOperand LL, LH, RL, RH; 5888 ExpandOp(Node->getOperand(0), LL, LH); 5889 ExpandOp(Node->getOperand(1), RL, RH); 5890 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 5891 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 5892 break; 5893 } 5894 case ISD::SELECT: { 5895 SDOperand LL, LH, RL, RH; 5896 ExpandOp(Node->getOperand(1), LL, LH); 5897 ExpandOp(Node->getOperand(2), RL, RH); 5898 if (getTypeAction(NVT) == Expand) 5899 NVT = TLI.getTypeToExpandTo(NVT); 5900 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 5901 if (VT != MVT::f32) 5902 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 5903 break; 5904 } 5905 case ISD::SELECT_CC: { 5906 SDOperand TL, TH, FL, FH; 5907 ExpandOp(Node->getOperand(2), TL, TH); 5908 ExpandOp(Node->getOperand(3), FL, FH); 5909 if (getTypeAction(NVT) == Expand) 5910 NVT = TLI.getTypeToExpandTo(NVT); 5911 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5912 Node->getOperand(1), TL, FL, Node->getOperand(4)); 5913 if (VT != MVT::f32) 5914 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5915 Node->getOperand(1), TH, FH, Node->getOperand(4)); 5916 break; 5917 } 5918 case ISD::ANY_EXTEND: 5919 // The low part is any extension of the input (which degenerates to a copy). 5920 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 5921 // The high part is undefined. 5922 Hi = DAG.getNode(ISD::UNDEF, NVT); 5923 break; 5924 case ISD::SIGN_EXTEND: { 5925 // The low part is just a sign extension of the input (which degenerates to 5926 // a copy). 5927 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 5928 5929 // The high part is obtained by SRA'ing all but one of the bits of the lo 5930 // part. 5931 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5932 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5933 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5934 break; 5935 } 5936 case ISD::ZERO_EXTEND: 5937 // The low part is just a zero extension of the input (which degenerates to 5938 // a copy). 5939 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 5940 5941 // The high part is just a zero. 5942 Hi = DAG.getConstant(0, NVT); 5943 break; 5944 5945 case ISD::TRUNCATE: { 5946 // The input value must be larger than this value. Expand *it*. 5947 SDOperand NewLo; 5948 ExpandOp(Node->getOperand(0), NewLo, Hi); 5949 5950 // The low part is now either the right size, or it is closer. If not the 5951 // right size, make an illegal truncate so we recursively expand it. 5952 if (NewLo.getValueType() != Node->getValueType(0)) 5953 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 5954 ExpandOp(NewLo, Lo, Hi); 5955 break; 5956 } 5957 5958 case ISD::BIT_CONVERT: { 5959 SDOperand Tmp; 5960 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 5961 // If the target wants to, allow it to lower this itself. 5962 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5963 case Expand: assert(0 && "cannot expand FP!"); 5964 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 5965 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 5966 } 5967 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 5968 } 5969 5970 // f32 / f64 must be expanded to i32 / i64. 5971 if (VT == MVT::f32 || VT == MVT::f64) { 5972 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5973 if (getTypeAction(NVT) == Expand) 5974 ExpandOp(Lo, Lo, Hi); 5975 break; 5976 } 5977 5978 // If source operand will be expanded to the same type as VT, i.e. 5979 // i64 <- f64, i32 <- f32, expand the source operand instead. 5980 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 5981 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 5982 ExpandOp(Node->getOperand(0), Lo, Hi); 5983 break; 5984 } 5985 5986 // Turn this into a load/store pair by default. 5987 if (Tmp.Val == 0) 5988 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 5989 5990 ExpandOp(Tmp, Lo, Hi); 5991 break; 5992 } 5993 5994 case ISD::READCYCLECOUNTER: { 5995 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 5996 TargetLowering::Custom && 5997 "Must custom expand ReadCycleCounter"); 5998 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 5999 assert(Tmp.Val && "Node must be custom expanded!"); 6000 ExpandOp(Tmp.getValue(0), Lo, Hi); 6001 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 6002 LegalizeOp(Tmp.getValue(1))); 6003 break; 6004 } 6005 6006 // These operators cannot be expanded directly, emit them as calls to 6007 // library functions. 6008 case ISD::FP_TO_SINT: { 6009 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6010 SDOperand Op; 6011 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6012 case Expand: assert(0 && "cannot expand FP!"); 6013 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6014 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6015 } 6016 6017 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 6018 6019 // Now that the custom expander is done, expand the result, which is still 6020 // VT. 6021 if (Op.Val) { 6022 ExpandOp(Op, Lo, Hi); 6023 break; 6024 } 6025 } 6026 6027 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6028 if (Node->getOperand(0).getValueType() == MVT::f32) 6029 LC = RTLIB::FPTOSINT_F32_I64; 6030 else if (Node->getOperand(0).getValueType() == MVT::f64) 6031 LC = RTLIB::FPTOSINT_F64_I64; 6032 else if (Node->getOperand(0).getValueType() == MVT::f80) 6033 LC = RTLIB::FPTOSINT_F80_I64; 6034 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6035 LC = RTLIB::FPTOSINT_PPCF128_I64; 6036 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 6037 false/*sign irrelevant*/, Hi); 6038 break; 6039 } 6040 6041 case ISD::FP_TO_UINT: { 6042 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6043 SDOperand Op; 6044 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6045 case Expand: assert(0 && "cannot expand FP!"); 6046 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6047 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6048 } 6049 6050 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 6051 6052 // Now that the custom expander is done, expand the result. 6053 if (Op.Val) { 6054 ExpandOp(Op, Lo, Hi); 6055 break; 6056 } 6057 } 6058 6059 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6060 if (Node->getOperand(0).getValueType() == MVT::f32) 6061 LC = RTLIB::FPTOUINT_F32_I64; 6062 else if (Node->getOperand(0).getValueType() == MVT::f64) 6063 LC = RTLIB::FPTOUINT_F64_I64; 6064 else if (Node->getOperand(0).getValueType() == MVT::f80) 6065 LC = RTLIB::FPTOUINT_F80_I64; 6066 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6067 LC = RTLIB::FPTOUINT_PPCF128_I64; 6068 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 6069 false/*sign irrelevant*/, Hi); 6070 break; 6071 } 6072 6073 case ISD::SHL: { 6074 // If the target wants custom lowering, do so. 6075 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6076 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6077 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 6078 Op = TLI.LowerOperation(Op, DAG); 6079 if (Op.Val) { 6080 // Now that the custom expander is done, expand the result, which is 6081 // still VT. 6082 ExpandOp(Op, Lo, Hi); 6083 break; 6084 } 6085 } 6086 6087 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6088 // this X << 1 as X+X. 6089 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6090 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 6091 TLI.isOperationLegal(ISD::ADDE, NVT)) { 6092 SDOperand LoOps[2], HiOps[3]; 6093 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6094 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6095 LoOps[1] = LoOps[0]; 6096 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6097 6098 HiOps[1] = HiOps[0]; 6099 HiOps[2] = Lo.getValue(1); 6100 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6101 break; 6102 } 6103 } 6104 6105 // If we can emit an efficient shift operation, do so now. 6106 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6107 break; 6108 6109 // If this target supports SHL_PARTS, use it. 6110 TargetLowering::LegalizeAction Action = 6111 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6112 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6113 Action == TargetLowering::Custom) { 6114 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6115 break; 6116 } 6117 6118 // Otherwise, emit a libcall. 6119 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 6120 false/*left shift=unsigned*/, Hi); 6121 break; 6122 } 6123 6124 case ISD::SRA: { 6125 // If the target wants custom lowering, do so. 6126 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6127 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6128 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6129 Op = TLI.LowerOperation(Op, DAG); 6130 if (Op.Val) { 6131 // Now that the custom expander is done, expand the result, which is 6132 // still VT. 6133 ExpandOp(Op, Lo, Hi); 6134 break; 6135 } 6136 } 6137 6138 // If we can emit an efficient shift operation, do so now. 6139 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6140 break; 6141 6142 // If this target supports SRA_PARTS, use it. 6143 TargetLowering::LegalizeAction Action = 6144 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6145 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6146 Action == TargetLowering::Custom) { 6147 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6148 break; 6149 } 6150 6151 // Otherwise, emit a libcall. 6152 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 6153 true/*ashr is signed*/, Hi); 6154 break; 6155 } 6156 6157 case ISD::SRL: { 6158 // If the target wants custom lowering, do so. 6159 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6160 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6161 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 6162 Op = TLI.LowerOperation(Op, DAG); 6163 if (Op.Val) { 6164 // Now that the custom expander is done, expand the result, which is 6165 // still VT. 6166 ExpandOp(Op, Lo, Hi); 6167 break; 6168 } 6169 } 6170 6171 // If we can emit an efficient shift operation, do so now. 6172 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6173 break; 6174 6175 // If this target supports SRL_PARTS, use it. 6176 TargetLowering::LegalizeAction Action = 6177 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6178 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6179 Action == TargetLowering::Custom) { 6180 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6181 break; 6182 } 6183 6184 // Otherwise, emit a libcall. 6185 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 6186 false/*lshr is unsigned*/, Hi); 6187 break; 6188 } 6189 6190 case ISD::ADD: 6191 case ISD::SUB: { 6192 // If the target wants to custom expand this, let them. 6193 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6194 TargetLowering::Custom) { 6195 Op = TLI.LowerOperation(Op, DAG); 6196 if (Op.Val) { 6197 ExpandOp(Op, Lo, Hi); 6198 break; 6199 } 6200 } 6201 6202 // Expand the subcomponents. 6203 SDOperand LHSL, LHSH, RHSL, RHSH; 6204 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6205 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6206 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6207 SDOperand LoOps[2], HiOps[3]; 6208 LoOps[0] = LHSL; 6209 LoOps[1] = RHSL; 6210 HiOps[0] = LHSH; 6211 HiOps[1] = RHSH; 6212 if (Node->getOpcode() == ISD::ADD) { 6213 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6214 HiOps[2] = Lo.getValue(1); 6215 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6216 } else { 6217 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6218 HiOps[2] = Lo.getValue(1); 6219 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6220 } 6221 break; 6222 } 6223 6224 case ISD::ADDC: 6225 case ISD::SUBC: { 6226 // Expand the subcomponents. 6227 SDOperand LHSL, LHSH, RHSL, RHSH; 6228 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6229 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6230 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6231 SDOperand LoOps[2] = { LHSL, RHSL }; 6232 SDOperand HiOps[3] = { LHSH, RHSH }; 6233 6234 if (Node->getOpcode() == ISD::ADDC) { 6235 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6236 HiOps[2] = Lo.getValue(1); 6237 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6238 } else { 6239 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6240 HiOps[2] = Lo.getValue(1); 6241 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6242 } 6243 // Remember that we legalized the flag. 6244 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6245 break; 6246 } 6247 case ISD::ADDE: 6248 case ISD::SUBE: { 6249 // Expand the subcomponents. 6250 SDOperand LHSL, LHSH, RHSL, RHSH; 6251 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6252 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6253 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6254 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 6255 SDOperand HiOps[3] = { LHSH, RHSH }; 6256 6257 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 6258 HiOps[2] = Lo.getValue(1); 6259 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 6260 6261 // Remember that we legalized the flag. 6262 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6263 break; 6264 } 6265 case ISD::MUL: { 6266 // If the target wants to custom expand this, let them. 6267 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 6268 SDOperand New = TLI.LowerOperation(Op, DAG); 6269 if (New.Val) { 6270 ExpandOp(New, Lo, Hi); 6271 break; 6272 } 6273 } 6274 6275 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 6276 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 6277 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 6278 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 6279 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 6280 SDOperand LL, LH, RL, RH; 6281 ExpandOp(Node->getOperand(0), LL, LH); 6282 ExpandOp(Node->getOperand(1), RL, RH); 6283 unsigned BitSize = MVT::getSizeInBits(RH.getValueType()); 6284 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 6285 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 6286 // FIXME: generalize this to handle other bit sizes 6287 if (LHSSB == 32 && RHSSB == 32 && 6288 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) && 6289 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) { 6290 // The inputs are both zero-extended. 6291 if (HasUMUL_LOHI) { 6292 // We can emit a umul_lohi. 6293 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6294 Hi = SDOperand(Lo.Val, 1); 6295 break; 6296 } 6297 if (HasMULHU) { 6298 // We can emit a mulhu+mul. 6299 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6300 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6301 break; 6302 } 6303 } 6304 if (LHSSB > BitSize && RHSSB > BitSize) { 6305 // The input values are both sign-extended. 6306 if (HasSMUL_LOHI) { 6307 // We can emit a smul_lohi. 6308 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6309 Hi = SDOperand(Lo.Val, 1); 6310 break; 6311 } 6312 if (HasMULHS) { 6313 // We can emit a mulhs+mul. 6314 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6315 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6316 break; 6317 } 6318 } 6319 if (HasUMUL_LOHI) { 6320 // Lo,Hi = umul LHS, RHS. 6321 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6322 DAG.getVTList(NVT, NVT), LL, RL); 6323 Lo = UMulLOHI; 6324 Hi = UMulLOHI.getValue(1); 6325 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6326 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6327 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6328 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6329 break; 6330 } 6331 if (HasMULHU) { 6332 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6333 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6334 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6335 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6336 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6337 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6338 break; 6339 } 6340 } 6341 6342 // If nothing else, we can make a libcall. 6343 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 6344 false/*sign irrelevant*/, Hi); 6345 break; 6346 } 6347 case ISD::SDIV: 6348 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 6349 break; 6350 case ISD::UDIV: 6351 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 6352 break; 6353 case ISD::SREM: 6354 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 6355 break; 6356 case ISD::UREM: 6357 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 6358 break; 6359 6360 case ISD::FADD: 6361 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32, 6362 RTLIB::ADD_F64, 6363 RTLIB::ADD_F80, 6364 RTLIB::ADD_PPCF128)), 6365 Node, false, Hi); 6366 break; 6367 case ISD::FSUB: 6368 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32, 6369 RTLIB::SUB_F64, 6370 RTLIB::SUB_F80, 6371 RTLIB::SUB_PPCF128)), 6372 Node, false, Hi); 6373 break; 6374 case ISD::FMUL: 6375 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32, 6376 RTLIB::MUL_F64, 6377 RTLIB::MUL_F80, 6378 RTLIB::MUL_PPCF128)), 6379 Node, false, Hi); 6380 break; 6381 case ISD::FDIV: 6382 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32, 6383 RTLIB::DIV_F64, 6384 RTLIB::DIV_F80, 6385 RTLIB::DIV_PPCF128)), 6386 Node, false, Hi); 6387 break; 6388 case ISD::FP_EXTEND: 6389 if (VT == MVT::ppcf128) { 6390 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6391 Node->getOperand(0).getValueType()==MVT::f64); 6392 const uint64_t zero = 0; 6393 if (Node->getOperand(0).getValueType()==MVT::f32) 6394 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6395 else 6396 Hi = Node->getOperand(0); 6397 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6398 break; 6399 } 6400 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 6401 break; 6402 case ISD::FP_ROUND: 6403 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 6404 break; 6405 case ISD::FPOWI: 6406 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32, 6407 RTLIB::POWI_F64, 6408 RTLIB::POWI_F80, 6409 RTLIB::POWI_PPCF128)), 6410 Node, false, Hi); 6411 break; 6412 case ISD::FSQRT: 6413 case ISD::FSIN: 6414 case ISD::FCOS: { 6415 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6416 switch(Node->getOpcode()) { 6417 case ISD::FSQRT: 6418 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 6419 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 6420 break; 6421 case ISD::FSIN: 6422 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 6423 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 6424 break; 6425 case ISD::FCOS: 6426 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 6427 RTLIB::COS_F80, RTLIB::COS_PPCF128); 6428 break; 6429 default: assert(0 && "Unreachable!"); 6430 } 6431 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 6432 break; 6433 } 6434 case ISD::FABS: { 6435 if (VT == MVT::ppcf128) { 6436 SDOperand Tmp; 6437 ExpandOp(Node->getOperand(0), Lo, Tmp); 6438 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6439 // lo = hi==fabs(hi) ? lo : -lo; 6440 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6441 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6442 DAG.getCondCode(ISD::SETEQ)); 6443 break; 6444 } 6445 SDOperand Mask = (VT == MVT::f64) 6446 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6447 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6448 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6449 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6450 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6451 if (getTypeAction(NVT) == Expand) 6452 ExpandOp(Lo, Lo, Hi); 6453 break; 6454 } 6455 case ISD::FNEG: { 6456 if (VT == MVT::ppcf128) { 6457 ExpandOp(Node->getOperand(0), Lo, Hi); 6458 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6459 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6460 break; 6461 } 6462 SDOperand Mask = (VT == MVT::f64) 6463 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6464 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6465 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6466 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6467 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6468 if (getTypeAction(NVT) == Expand) 6469 ExpandOp(Lo, Lo, Hi); 6470 break; 6471 } 6472 case ISD::FCOPYSIGN: { 6473 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6474 if (getTypeAction(NVT) == Expand) 6475 ExpandOp(Lo, Lo, Hi); 6476 break; 6477 } 6478 case ISD::SINT_TO_FP: 6479 case ISD::UINT_TO_FP: { 6480 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6481 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 6482 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) { 6483 static uint64_t zero = 0; 6484 if (isSigned) { 6485 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6486 Node->getOperand(0))); 6487 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6488 } else { 6489 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6490 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6491 Node->getOperand(0))); 6492 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6493 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6494 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6495 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6496 DAG.getConstant(0, MVT::i32), 6497 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6498 DAG.getConstantFP( 6499 APFloat(APInt(128, 2, TwoE32)), 6500 MVT::ppcf128)), 6501 Hi, 6502 DAG.getCondCode(ISD::SETLT)), 6503 Lo, Hi); 6504 } 6505 break; 6506 } 6507 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6508 // si64->ppcf128 done by libcall, below 6509 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6510 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6511 Lo, Hi); 6512 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6513 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6514 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6515 DAG.getConstant(0, MVT::i64), 6516 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6517 DAG.getConstantFP( 6518 APFloat(APInt(128, 2, TwoE64)), 6519 MVT::ppcf128)), 6520 Hi, 6521 DAG.getCondCode(ISD::SETLT)), 6522 Lo, Hi); 6523 break; 6524 } 6525 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6526 if (Node->getOperand(0).getValueType() == MVT::i64) { 6527 if (VT == MVT::f32) 6528 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; 6529 else if (VT == MVT::f64) 6530 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; 6531 else if (VT == MVT::f80) { 6532 assert(isSigned); 6533 LC = RTLIB::SINTTOFP_I64_F80; 6534 } 6535 else if (VT == MVT::ppcf128) { 6536 assert(isSigned); 6537 LC = RTLIB::SINTTOFP_I64_PPCF128; 6538 } 6539 } else { 6540 if (VT == MVT::f32) 6541 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 6542 else 6543 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 6544 } 6545 6546 // Promote the operand if needed. 6547 if (getTypeAction(SrcVT) == Promote) { 6548 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 6549 Tmp = isSigned 6550 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6551 DAG.getValueType(SrcVT)) 6552 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6553 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6554 } 6555 6556 const char *LibCall = TLI.getLibcallName(LC); 6557 if (LibCall) 6558 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi); 6559 else { 6560 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6561 Node->getOperand(0)); 6562 if (getTypeAction(Lo.getValueType()) == Expand) 6563 ExpandOp(Lo, Lo, Hi); 6564 } 6565 break; 6566 } 6567 } 6568 6569 // Make sure the resultant values have been legalized themselves, unless this 6570 // is a type that requires multi-step expansion. 6571 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6572 Lo = LegalizeOp(Lo); 6573 if (Hi.Val) 6574 // Don't legalize the high part if it is expanded to a single node. 6575 Hi = LegalizeOp(Hi); 6576 } 6577 6578 // Remember in a map if the values will be reused later. 6579 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 6580 assert(isNew && "Value already expanded?!?"); 6581} 6582 6583/// SplitVectorOp - Given an operand of vector type, break it down into 6584/// two smaller values, still of vector type. 6585void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 6586 SDOperand &Hi) { 6587 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); 6588 SDNode *Node = Op.Val; 6589 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType()); 6590 assert(NumElements > 1 && "Cannot split a single element vector!"); 6591 6592 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType()); 6593 6594 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6595 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6596 6597 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo); 6598 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi); 6599 6600 // See if we already split it. 6601 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 6602 = SplitNodes.find(Op); 6603 if (I != SplitNodes.end()) { 6604 Lo = I->second.first; 6605 Hi = I->second.second; 6606 return; 6607 } 6608 6609 switch (Node->getOpcode()) { 6610 default: 6611#ifndef NDEBUG 6612 Node->dump(&DAG); 6613#endif 6614 assert(0 && "Unhandled operation in SplitVectorOp!"); 6615 case ISD::UNDEF: 6616 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6617 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6618 break; 6619 case ISD::BUILD_PAIR: 6620 Lo = Node->getOperand(0); 6621 Hi = Node->getOperand(1); 6622 break; 6623 case ISD::INSERT_VECTOR_ELT: { 6624 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6625 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 6626 SDOperand ScalarOp = Node->getOperand(1); 6627 if (Index < NewNumElts_Lo) 6628 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6629 DAG.getConstant(Index, TLI.getPointerTy())); 6630 else 6631 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6632 DAG.getConstant(Index - NewNumElts_Lo, 6633 TLI.getPointerTy())); 6634 break; 6635 } 6636 case ISD::VECTOR_SHUFFLE: { 6637 // Build the low part. 6638 SDOperand Mask = Node->getOperand(2); 6639 SmallVector<SDOperand, 8> Ops; 6640 MVT::ValueType PtrVT = TLI.getPointerTy(); 6641 6642 // Insert all of the elements from the input that are needed. We use 6643 // buildvector of extractelement here because the input vectors will have 6644 // to be legalized, so this makes the code simpler. 6645 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 6646 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 6647 SDOperand InVec = Node->getOperand(0); 6648 if (Idx >= NumElements) { 6649 InVec = Node->getOperand(1); 6650 Idx -= NumElements; 6651 } 6652 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6653 DAG.getConstant(Idx, PtrVT))); 6654 } 6655 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6656 Ops.clear(); 6657 6658 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 6659 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 6660 SDOperand InVec = Node->getOperand(0); 6661 if (Idx >= NumElements) { 6662 InVec = Node->getOperand(1); 6663 Idx -= NumElements; 6664 } 6665 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6666 DAG.getConstant(Idx, PtrVT))); 6667 } 6668 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6669 break; 6670 } 6671 case ISD::BUILD_VECTOR: { 6672 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6673 Node->op_begin()+NewNumElts_Lo); 6674 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 6675 6676 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 6677 Node->op_end()); 6678 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 6679 break; 6680 } 6681 case ISD::CONCAT_VECTORS: { 6682 // FIXME: Handle non-power-of-two vectors? 6683 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6684 if (NewNumSubvectors == 1) { 6685 Lo = Node->getOperand(0); 6686 Hi = Node->getOperand(1); 6687 } else { 6688 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6689 Node->op_begin()+NewNumSubvectors); 6690 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 6691 6692 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6693 Node->op_end()); 6694 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 6695 } 6696 break; 6697 } 6698 case ISD::SELECT: { 6699 SDOperand Cond = Node->getOperand(0); 6700 6701 SDOperand LL, LH, RL, RH; 6702 SplitVectorOp(Node->getOperand(1), LL, LH); 6703 SplitVectorOp(Node->getOperand(2), RL, RH); 6704 6705 if (MVT::isVector(Cond.getValueType())) { 6706 // Handle a vector merge. 6707 SDOperand CL, CH; 6708 SplitVectorOp(Cond, CL, CH); 6709 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 6710 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 6711 } else { 6712 // Handle a simple select with vector operands. 6713 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 6714 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 6715 } 6716 break; 6717 } 6718 case ISD::ADD: 6719 case ISD::SUB: 6720 case ISD::MUL: 6721 case ISD::FADD: 6722 case ISD::FSUB: 6723 case ISD::FMUL: 6724 case ISD::SDIV: 6725 case ISD::UDIV: 6726 case ISD::FDIV: 6727 case ISD::FPOW: 6728 case ISD::AND: 6729 case ISD::OR: 6730 case ISD::XOR: 6731 case ISD::UREM: 6732 case ISD::SREM: 6733 case ISD::FREM: { 6734 SDOperand LL, LH, RL, RH; 6735 SplitVectorOp(Node->getOperand(0), LL, LH); 6736 SplitVectorOp(Node->getOperand(1), RL, RH); 6737 6738 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 6739 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 6740 break; 6741 } 6742 case ISD::FPOWI: { 6743 SDOperand L, H; 6744 SplitVectorOp(Node->getOperand(0), L, H); 6745 6746 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 6747 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 6748 break; 6749 } 6750 case ISD::CTTZ: 6751 case ISD::CTLZ: 6752 case ISD::CTPOP: 6753 case ISD::FNEG: 6754 case ISD::FABS: 6755 case ISD::FSQRT: 6756 case ISD::FSIN: 6757 case ISD::FCOS: 6758 case ISD::FP_TO_SINT: 6759 case ISD::FP_TO_UINT: 6760 case ISD::SINT_TO_FP: 6761 case ISD::UINT_TO_FP: { 6762 SDOperand L, H; 6763 SplitVectorOp(Node->getOperand(0), L, H); 6764 6765 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 6766 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 6767 break; 6768 } 6769 case ISD::LOAD: { 6770 LoadSDNode *LD = cast<LoadSDNode>(Node); 6771 SDOperand Ch = LD->getChain(); 6772 SDOperand Ptr = LD->getBasePtr(); 6773 const Value *SV = LD->getSrcValue(); 6774 int SVOffset = LD->getSrcValueOffset(); 6775 unsigned Alignment = LD->getAlignment(); 6776 bool isVolatile = LD->isVolatile(); 6777 6778 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6779 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8; 6780 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6781 DAG.getIntPtrConstant(IncrementSize)); 6782 SVOffset += IncrementSize; 6783 Alignment = MinAlign(Alignment, IncrementSize); 6784 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6785 6786 // Build a factor node to remember that this load is independent of the 6787 // other one. 6788 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6789 Hi.getValue(1)); 6790 6791 // Remember that we legalized the chain. 6792 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6793 break; 6794 } 6795 case ISD::BIT_CONVERT: { 6796 // We know the result is a vector. The input may be either a vector or a 6797 // scalar value. 6798 SDOperand InOp = Node->getOperand(0); 6799 if (!MVT::isVector(InOp.getValueType()) || 6800 MVT::getVectorNumElements(InOp.getValueType()) == 1) { 6801 // The input is a scalar or single-element vector. 6802 // Lower to a store/load so that it can be split. 6803 // FIXME: this could be improved probably. 6804 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); 6805 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val); 6806 6807 SDOperand St = DAG.getStore(DAG.getEntryNode(), 6808 InOp, Ptr, 6809 PseudoSourceValue::getFixedStack(), 6810 FI->getIndex()); 6811 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, 6812 PseudoSourceValue::getFixedStack(), 6813 FI->getIndex()); 6814 } 6815 // Split the vector and convert each of the pieces now. 6816 SplitVectorOp(InOp, Lo, Hi); 6817 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 6818 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 6819 break; 6820 } 6821 } 6822 6823 // Remember in a map if the values will be reused later. 6824 bool isNew = 6825 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 6826 assert(isNew && "Value already split?!?"); 6827} 6828 6829 6830/// ScalarizeVectorOp - Given an operand of single-element vector type 6831/// (e.g. v1f32), convert it into the equivalent operation that returns a 6832/// scalar (e.g. f32) value. 6833SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 6834 assert(MVT::isVector(Op.getValueType()) && 6835 "Bad ScalarizeVectorOp invocation!"); 6836 SDNode *Node = Op.Val; 6837 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); 6838 assert(MVT::getVectorNumElements(Op.getValueType()) == 1); 6839 6840 // See if we already scalarized it. 6841 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 6842 if (I != ScalarizedNodes.end()) return I->second; 6843 6844 SDOperand Result; 6845 switch (Node->getOpcode()) { 6846 default: 6847#ifndef NDEBUG 6848 Node->dump(&DAG); cerr << "\n"; 6849#endif 6850 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 6851 case ISD::ADD: 6852 case ISD::FADD: 6853 case ISD::SUB: 6854 case ISD::FSUB: 6855 case ISD::MUL: 6856 case ISD::FMUL: 6857 case ISD::SDIV: 6858 case ISD::UDIV: 6859 case ISD::FDIV: 6860 case ISD::SREM: 6861 case ISD::UREM: 6862 case ISD::FREM: 6863 case ISD::FPOW: 6864 case ISD::AND: 6865 case ISD::OR: 6866 case ISD::XOR: 6867 Result = DAG.getNode(Node->getOpcode(), 6868 NewVT, 6869 ScalarizeVectorOp(Node->getOperand(0)), 6870 ScalarizeVectorOp(Node->getOperand(1))); 6871 break; 6872 case ISD::FNEG: 6873 case ISD::FABS: 6874 case ISD::FSQRT: 6875 case ISD::FSIN: 6876 case ISD::FCOS: 6877 Result = DAG.getNode(Node->getOpcode(), 6878 NewVT, 6879 ScalarizeVectorOp(Node->getOperand(0))); 6880 break; 6881 case ISD::FPOWI: 6882 Result = DAG.getNode(Node->getOpcode(), 6883 NewVT, 6884 ScalarizeVectorOp(Node->getOperand(0)), 6885 Node->getOperand(1)); 6886 break; 6887 case ISD::LOAD: { 6888 LoadSDNode *LD = cast<LoadSDNode>(Node); 6889 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 6890 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 6891 6892 const Value *SV = LD->getSrcValue(); 6893 int SVOffset = LD->getSrcValueOffset(); 6894 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 6895 LD->isVolatile(), LD->getAlignment()); 6896 6897 // Remember that we legalized the chain. 6898 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 6899 break; 6900 } 6901 case ISD::BUILD_VECTOR: 6902 Result = Node->getOperand(0); 6903 break; 6904 case ISD::INSERT_VECTOR_ELT: 6905 // Returning the inserted scalar element. 6906 Result = Node->getOperand(1); 6907 break; 6908 case ISD::CONCAT_VECTORS: 6909 assert(Node->getOperand(0).getValueType() == NewVT && 6910 "Concat of non-legal vectors not yet supported!"); 6911 Result = Node->getOperand(0); 6912 break; 6913 case ISD::VECTOR_SHUFFLE: { 6914 // Figure out if the scalar is the LHS or RHS and return it. 6915 SDOperand EltNum = Node->getOperand(2).getOperand(0); 6916 if (cast<ConstantSDNode>(EltNum)->getValue()) 6917 Result = ScalarizeVectorOp(Node->getOperand(1)); 6918 else 6919 Result = ScalarizeVectorOp(Node->getOperand(0)); 6920 break; 6921 } 6922 case ISD::EXTRACT_SUBVECTOR: 6923 Result = Node->getOperand(0); 6924 assert(Result.getValueType() == NewVT); 6925 break; 6926 case ISD::BIT_CONVERT: 6927 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 6928 break; 6929 case ISD::SELECT: 6930 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 6931 ScalarizeVectorOp(Op.getOperand(1)), 6932 ScalarizeVectorOp(Op.getOperand(2))); 6933 break; 6934 } 6935 6936 if (TLI.isTypeLegal(NewVT)) 6937 Result = LegalizeOp(Result); 6938 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 6939 assert(isNew && "Value already scalarized?"); 6940 return Result; 6941} 6942 6943 6944// SelectionDAG::Legalize - This is the entry point for the file. 6945// 6946void SelectionDAG::Legalize() { 6947 if (ViewLegalizeDAGs) viewGraph(); 6948 6949 /// run - This is the main entry point to this class. 6950 /// 6951 SelectionDAGLegalize(*this).LegalizeDAG(); 6952} 6953 6954