LegalizeDAG.cpp revision 232ee95a09a583b7d66b90ee7ddf7fdb9c194a04
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineConstantPool.h" 16#include "llvm/CodeGen/MachineFunction.h" 17#include "llvm/CodeGen/MachineFrameInfo.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/Constants.h" 22#include <iostream> 23using namespace llvm; 24 25//===----------------------------------------------------------------------===// 26/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 27/// hacks on it until the target machine can handle it. This involves 28/// eliminating value sizes the machine cannot handle (promoting small sizes to 29/// large sizes or splitting up large values into small values) as well as 30/// eliminating operations the machine cannot handle. 31/// 32/// This code also does a small amount of optimization and recognition of idioms 33/// as part of its processing. For example, if a target does not support a 34/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 35/// will attempt merge setcc and brc instructions into brcc's. 36/// 37namespace { 38class SelectionDAGLegalize { 39 TargetLowering &TLI; 40 SelectionDAG &DAG; 41 42 /// LegalizeAction - This enum indicates what action we should take for each 43 /// value type the can occur in the program. 44 enum LegalizeAction { 45 Legal, // The target natively supports this value type. 46 Promote, // This should be promoted to the next larger type. 47 Expand, // This integer type should be broken into smaller pieces. 48 }; 49 50 /// ValueTypeActions - This is a bitvector that contains two bits for each 51 /// value type, where the two bits correspond to the LegalizeAction enum. 52 /// This can be queried with "getTypeAction(VT)". 53 unsigned ValueTypeActions; 54 55 /// NeedsAnotherIteration - This is set when we expand a large integer 56 /// operation into smaller integer operations, but the smaller operations are 57 /// not set. This occurs only rarely in practice, for targets that don't have 58 /// 32-bit or larger integer registers. 59 bool NeedsAnotherIteration; 60 61 /// LegalizedNodes - For nodes that are of legal width, and that have more 62 /// than one use, this map indicates what regularized operand to use. This 63 /// allows us to avoid legalizing the same thing more than once. 64 std::map<SDOperand, SDOperand> LegalizedNodes; 65 66 /// PromotedNodes - For nodes that are below legal width, and that have more 67 /// than one use, this map indicates what promoted value to use. This allows 68 /// us to avoid promoting the same thing more than once. 69 std::map<SDOperand, SDOperand> PromotedNodes; 70 71 /// ExpandedNodes - For nodes that need to be expanded, and which have more 72 /// than one use, this map indicates which which operands are the expanded 73 /// version of the input. This allows us to avoid expanding the same node 74 /// more than once. 75 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 76 77 void AddLegalizedOperand(SDOperand From, SDOperand To) { 78 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second; 79 assert(isNew && "Got into the map somehow?"); 80 } 81 void AddPromotedOperand(SDOperand From, SDOperand To) { 82 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 83 assert(isNew && "Got into the map somehow?"); 84 } 85 86public: 87 88 SelectionDAGLegalize(SelectionDAG &DAG); 89 90 /// Run - While there is still lowering to do, perform a pass over the DAG. 91 /// Most regularization can be done in a single pass, but targets that require 92 /// large values to be split into registers multiple times (e.g. i64 -> 4x 93 /// i16) require iteration for these values (the first iteration will demote 94 /// to i32, the second will demote to i16). 95 void Run() { 96 do { 97 NeedsAnotherIteration = false; 98 LegalizeDAG(); 99 } while (NeedsAnotherIteration); 100 } 101 102 /// getTypeAction - Return how we should legalize values of this type, either 103 /// it is already legal or we need to expand it into multiple registers of 104 /// smaller integer type, or we need to promote it to a larger type. 105 LegalizeAction getTypeAction(MVT::ValueType VT) const { 106 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 107 } 108 109 /// isTypeLegal - Return true if this type is legal on this target. 110 /// 111 bool isTypeLegal(MVT::ValueType VT) const { 112 return getTypeAction(VT) == Legal; 113 } 114 115private: 116 void LegalizeDAG(); 117 118 SDOperand LegalizeOp(SDOperand O); 119 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 120 SDOperand PromoteOp(SDOperand O); 121 122 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 123 SDOperand &Hi); 124 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 125 SDOperand Source); 126 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 127 SDOperand &Lo, SDOperand &Hi); 128 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 129 SDOperand &Lo, SDOperand &Hi); 130 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 131 SDOperand &Lo, SDOperand &Hi); 132 133 SDOperand getIntPtrConstant(uint64_t Val) { 134 return DAG.getConstant(Val, TLI.getPointerTy()); 135 } 136}; 137} 138 139 140SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 141 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 142 ValueTypeActions(TLI.getValueTypeActions()) { 143 assert(MVT::LAST_VALUETYPE <= 16 && 144 "Too many value types for ValueTypeActions to hold!"); 145} 146 147void SelectionDAGLegalize::LegalizeDAG() { 148 SDOperand OldRoot = DAG.getRoot(); 149 SDOperand NewRoot = LegalizeOp(OldRoot); 150 DAG.setRoot(NewRoot); 151 152 ExpandedNodes.clear(); 153 LegalizedNodes.clear(); 154 PromotedNodes.clear(); 155 156 // Remove dead nodes now. 157 DAG.RemoveDeadNodes(OldRoot.Val); 158} 159 160SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 161 assert(getTypeAction(Op.getValueType()) == Legal && 162 "Caller should expand or promote operands that are not legal!"); 163 164 // If this operation defines any values that cannot be represented in a 165 // register on this target, make sure to expand or promote them. 166 if (Op.Val->getNumValues() > 1) { 167 for (unsigned i = 0, e = Op.Val->getNumValues(); i != e; ++i) 168 switch (getTypeAction(Op.Val->getValueType(i))) { 169 case Legal: break; // Nothing to do. 170 case Expand: { 171 SDOperand T1, T2; 172 ExpandOp(Op.getValue(i), T1, T2); 173 assert(LegalizedNodes.count(Op) && 174 "Expansion didn't add legal operands!"); 175 return LegalizedNodes[Op]; 176 } 177 case Promote: 178 PromoteOp(Op.getValue(i)); 179 assert(LegalizedNodes.count(Op) && 180 "Expansion didn't add legal operands!"); 181 return LegalizedNodes[Op]; 182 } 183 } 184 185 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 186 if (I != LegalizedNodes.end()) return I->second; 187 188 SDOperand Tmp1, Tmp2, Tmp3; 189 190 SDOperand Result = Op; 191 SDNode *Node = Op.Val; 192 193 switch (Node->getOpcode()) { 194 default: 195 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 196 assert(0 && "Do not know how to legalize this operator!"); 197 abort(); 198 case ISD::EntryToken: 199 case ISD::FrameIndex: 200 case ISD::GlobalAddress: 201 case ISD::ExternalSymbol: 202 case ISD::ConstantPool: // Nothing to do. 203 assert(getTypeAction(Node->getValueType(0)) == Legal && 204 "This must be legal!"); 205 break; 206 case ISD::CopyFromReg: 207 Tmp1 = LegalizeOp(Node->getOperand(0)); 208 if (Tmp1 != Node->getOperand(0)) 209 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), 210 Node->getValueType(0), Tmp1); 211 else 212 Result = Op.getValue(0); 213 214 // Since CopyFromReg produces two values, make sure to remember that we 215 // legalized both of them. 216 AddLegalizedOperand(Op.getValue(0), Result); 217 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 218 return Result.getValue(Op.ResNo); 219 case ISD::ImplicitDef: 220 Tmp1 = LegalizeOp(Node->getOperand(0)); 221 if (Tmp1 != Node->getOperand(0)) 222 Result = DAG.getImplicitDef(Tmp1, cast<RegSDNode>(Node)->getReg()); 223 break; 224 case ISD::UNDEF: { 225 MVT::ValueType VT = Op.getValueType(); 226 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 227 default: assert(0 && "This action is not supported yet!"); 228 case TargetLowering::Expand: 229 case TargetLowering::Promote: 230 if (MVT::isInteger(VT)) 231 Result = DAG.getConstant(0, VT); 232 else if (MVT::isFloatingPoint(VT)) 233 Result = DAG.getConstantFP(0, VT); 234 else 235 assert(0 && "Unknown value type!"); 236 break; 237 case TargetLowering::Legal: 238 break; 239 } 240 break; 241 } 242 case ISD::Constant: 243 // We know we don't need to expand constants here, constants only have one 244 // value and we check that it is fine above. 245 246 // FIXME: Maybe we should handle things like targets that don't support full 247 // 32-bit immediates? 248 break; 249 case ISD::ConstantFP: { 250 // Spill FP immediates to the constant pool if the target cannot directly 251 // codegen them. Targets often have some immediate values that can be 252 // efficiently generated into an FP register without a load. We explicitly 253 // leave these constants as ConstantFP nodes for the target to deal with. 254 255 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 256 257 // Check to see if this FP immediate is already legal. 258 bool isLegal = false; 259 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 260 E = TLI.legal_fpimm_end(); I != E; ++I) 261 if (CFP->isExactlyValue(*I)) { 262 isLegal = true; 263 break; 264 } 265 266 if (!isLegal) { 267 // Otherwise we need to spill the constant to memory. 268 MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool(); 269 270 bool Extend = false; 271 272 // If a FP immediate is precise when represented as a float, we put it 273 // into the constant pool as a float, even if it's is statically typed 274 // as a double. 275 MVT::ValueType VT = CFP->getValueType(0); 276 bool isDouble = VT == MVT::f64; 277 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 278 Type::FloatTy, CFP->getValue()); 279 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 280 // Only do this if the target has a native EXTLOAD instruction from 281 // f32. 282 TLI.getOperationAction(ISD::EXTLOAD, 283 MVT::f32) == TargetLowering::Legal) { 284 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 285 VT = MVT::f32; 286 Extend = true; 287 } 288 289 SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(LLVMC), 290 TLI.getPointerTy()); 291 if (Extend) { 292 Result = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), CPIdx, 293 MVT::f32); 294 } else { 295 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx); 296 } 297 } 298 break; 299 } 300 case ISD::TokenFactor: { 301 std::vector<SDOperand> Ops; 302 bool Changed = false; 303 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 304 SDOperand Op = Node->getOperand(i); 305 // Fold single-use TokenFactor nodes into this token factor as we go. 306 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 307 Changed = true; 308 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 309 Ops.push_back(LegalizeOp(Op.getOperand(j))); 310 } else { 311 Ops.push_back(LegalizeOp(Op)); // Legalize the operands 312 Changed |= Ops[i] != Op; 313 } 314 } 315 if (Changed) 316 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 317 break; 318 } 319 320 case ISD::ADJCALLSTACKDOWN: 321 case ISD::ADJCALLSTACKUP: 322 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 323 // There is no need to legalize the size argument (Operand #1) 324 if (Tmp1 != Node->getOperand(0)) 325 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 326 Node->getOperand(1)); 327 break; 328 case ISD::DYNAMIC_STACKALLOC: 329 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 330 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 331 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 332 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 333 Tmp3 != Node->getOperand(2)) 334 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, Node->getValueType(0), 335 Tmp1, Tmp2, Tmp3); 336 else 337 Result = Op.getValue(0); 338 339 // Since this op produces two values, make sure to remember that we 340 // legalized both of them. 341 AddLegalizedOperand(SDOperand(Node, 0), Result); 342 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 343 return Result.getValue(Op.ResNo); 344 345 case ISD::CALL: { 346 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 347 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 348 349 bool Changed = false; 350 std::vector<SDOperand> Ops; 351 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 352 Ops.push_back(LegalizeOp(Node->getOperand(i))); 353 Changed |= Ops.back() != Node->getOperand(i); 354 } 355 356 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 357 std::vector<MVT::ValueType> RetTyVTs; 358 RetTyVTs.reserve(Node->getNumValues()); 359 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 360 RetTyVTs.push_back(Node->getValueType(i)); 361 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops), 0); 362 } else { 363 Result = Result.getValue(0); 364 } 365 // Since calls produce multiple values, make sure to remember that we 366 // legalized all of them. 367 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 368 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 369 return Result.getValue(Op.ResNo); 370 } 371 case ISD::BR: 372 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 373 if (Tmp1 != Node->getOperand(0)) 374 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 375 break; 376 377 case ISD::BRCOND: 378 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 379 380 switch (getTypeAction(Node->getOperand(1).getValueType())) { 381 case Expand: assert(0 && "It's impossible to expand bools"); 382 case Legal: 383 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 384 break; 385 case Promote: 386 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 387 break; 388 } 389 // Basic block destination (Op#2) is always legal. 390 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 391 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 392 Node->getOperand(2)); 393 break; 394 case ISD::BRCONDTWOWAY: 395 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 396 switch (getTypeAction(Node->getOperand(1).getValueType())) { 397 case Expand: assert(0 && "It's impossible to expand bools"); 398 case Legal: 399 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 400 break; 401 case Promote: 402 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 403 break; 404 } 405 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 406 // pair. 407 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 408 case TargetLowering::Promote: 409 default: assert(0 && "This action is not supported yet!"); 410 case TargetLowering::Legal: 411 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 412 std::vector<SDOperand> Ops; 413 Ops.push_back(Tmp1); 414 Ops.push_back(Tmp2); 415 Ops.push_back(Node->getOperand(2)); 416 Ops.push_back(Node->getOperand(3)); 417 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 418 } 419 break; 420 case TargetLowering::Expand: 421 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 422 Node->getOperand(2)); 423 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 424 break; 425 } 426 break; 427 428 case ISD::LOAD: 429 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 430 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 431 if (Tmp1 != Node->getOperand(0) || 432 Tmp2 != Node->getOperand(1)) 433 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2); 434 else 435 Result = SDOperand(Node, 0); 436 437 // Since loads produce two values, make sure to remember that we legalized 438 // both of them. 439 AddLegalizedOperand(SDOperand(Node, 0), Result); 440 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 441 return Result.getValue(Op.ResNo); 442 443 case ISD::EXTLOAD: 444 case ISD::SEXTLOAD: 445 case ISD::ZEXTLOAD: 446 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 447 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 448 if (Tmp1 != Node->getOperand(0) || 449 Tmp2 != Node->getOperand(1)) 450 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2, 451 cast<MVTSDNode>(Node)->getExtraValueType()); 452 else 453 Result = SDOperand(Node, 0); 454 455 // Since loads produce two values, make sure to remember that we legalized 456 // both of them. 457 AddLegalizedOperand(SDOperand(Node, 0), Result); 458 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 459 return Result.getValue(Op.ResNo); 460 461 case ISD::EXTRACT_ELEMENT: 462 // Get both the low and high parts. 463 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 464 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 465 Result = Tmp2; // 1 -> Hi 466 else 467 Result = Tmp1; // 0 -> Lo 468 break; 469 470 case ISD::CopyToReg: 471 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 472 473 switch (getTypeAction(Node->getOperand(1).getValueType())) { 474 case Legal: 475 // Legalize the incoming value (must be legal). 476 Tmp2 = LegalizeOp(Node->getOperand(1)); 477 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 478 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg()); 479 break; 480 case Promote: 481 Tmp2 = PromoteOp(Node->getOperand(1)); 482 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg()); 483 break; 484 case Expand: 485 SDOperand Lo, Hi; 486 ExpandOp(Node->getOperand(1), Lo, Hi); 487 unsigned Reg = cast<RegSDNode>(Node)->getReg(); 488 Lo = DAG.getCopyToReg(Tmp1, Lo, Reg); 489 Hi = DAG.getCopyToReg(Tmp1, Hi, Reg+1); 490 // Note that the copytoreg nodes are independent of each other. 491 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 492 assert(isTypeLegal(Result.getValueType()) && 493 "Cannot expand multiple times yet (i64 -> i16)"); 494 break; 495 } 496 break; 497 498 case ISD::RET: 499 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 500 switch (Node->getNumOperands()) { 501 case 2: // ret val 502 switch (getTypeAction(Node->getOperand(1).getValueType())) { 503 case Legal: 504 Tmp2 = LegalizeOp(Node->getOperand(1)); 505 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 506 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 507 break; 508 case Expand: { 509 SDOperand Lo, Hi; 510 ExpandOp(Node->getOperand(1), Lo, Hi); 511 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 512 break; 513 } 514 case Promote: 515 Tmp2 = PromoteOp(Node->getOperand(1)); 516 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 517 break; 518 } 519 break; 520 case 1: // ret void 521 if (Tmp1 != Node->getOperand(0)) 522 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 523 break; 524 default: { // ret <values> 525 std::vector<SDOperand> NewValues; 526 NewValues.push_back(Tmp1); 527 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 528 switch (getTypeAction(Node->getOperand(i).getValueType())) { 529 case Legal: 530 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 531 break; 532 case Expand: { 533 SDOperand Lo, Hi; 534 ExpandOp(Node->getOperand(i), Lo, Hi); 535 NewValues.push_back(Lo); 536 NewValues.push_back(Hi); 537 break; 538 } 539 case Promote: 540 assert(0 && "Can't promote multiple return value yet!"); 541 } 542 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 543 break; 544 } 545 } 546 break; 547 case ISD::STORE: 548 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 549 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 550 551 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 552 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 553 if (CFP->getValueType(0) == MVT::f32) { 554 union { 555 unsigned I; 556 float F; 557 } V; 558 V.F = CFP->getValue(); 559 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 560 DAG.getConstant(V.I, MVT::i32), Tmp2); 561 } else { 562 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 563 union { 564 uint64_t I; 565 double F; 566 } V; 567 V.F = CFP->getValue(); 568 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 569 DAG.getConstant(V.I, MVT::i64), Tmp2); 570 } 571 Node = Result.Val; 572 } 573 574 switch (getTypeAction(Node->getOperand(1).getValueType())) { 575 case Legal: { 576 SDOperand Val = LegalizeOp(Node->getOperand(1)); 577 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 578 Tmp2 != Node->getOperand(2)) 579 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2); 580 break; 581 } 582 case Promote: 583 // Truncate the value and store the result. 584 Tmp3 = PromoteOp(Node->getOperand(1)); 585 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 586 Node->getOperand(1).getValueType()); 587 break; 588 589 case Expand: 590 SDOperand Lo, Hi; 591 ExpandOp(Node->getOperand(1), Lo, Hi); 592 593 if (!TLI.isLittleEndian()) 594 std::swap(Lo, Hi); 595 596 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2); 597 598 unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 599 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 600 getIntPtrConstant(IncrementSize)); 601 assert(isTypeLegal(Tmp2.getValueType()) && 602 "Pointers must be legal!"); 603 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2); 604 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 605 break; 606 } 607 break; 608 case ISD::PCMARKER: 609 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 610 if (Tmp1 != Node->getOperand(0)) 611 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 612 break; 613 case ISD::TRUNCSTORE: 614 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 615 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 616 617 switch (getTypeAction(Node->getOperand(1).getValueType())) { 618 case Legal: 619 Tmp2 = LegalizeOp(Node->getOperand(1)); 620 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 621 Tmp3 != Node->getOperand(2)) 622 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 623 cast<MVTSDNode>(Node)->getExtraValueType()); 624 break; 625 case Promote: 626 case Expand: 627 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 628 } 629 break; 630 case ISD::SELECT: 631 switch (getTypeAction(Node->getOperand(0).getValueType())) { 632 case Expand: assert(0 && "It's impossible to expand bools"); 633 case Legal: 634 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 635 break; 636 case Promote: 637 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 638 break; 639 } 640 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 641 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 642 643 switch (TLI.getOperationAction(Node->getOpcode(), Tmp2.getValueType())) { 644 default: assert(0 && "This action is not supported yet!"); 645 case TargetLowering::Legal: 646 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 647 Tmp3 != Node->getOperand(2)) 648 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 649 Tmp1, Tmp2, Tmp3); 650 break; 651 case TargetLowering::Promote: { 652 MVT::ValueType NVT = 653 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 654 unsigned ExtOp, TruncOp; 655 if (MVT::isInteger(Tmp2.getValueType())) { 656 ExtOp = ISD::ZERO_EXTEND; 657 TruncOp = ISD::TRUNCATE; 658 } else { 659 ExtOp = ISD::FP_EXTEND; 660 TruncOp = ISD::FP_ROUND; 661 } 662 // Promote each of the values to the new type. 663 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 664 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 665 // Perform the larger operation, then round down. 666 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 667 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 668 break; 669 } 670 } 671 break; 672 case ISD::SETCC: 673 switch (getTypeAction(Node->getOperand(0).getValueType())) { 674 case Legal: 675 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 676 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 677 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 678 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 679 Node->getValueType(0), Tmp1, Tmp2); 680 break; 681 case Promote: 682 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 683 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 684 685 // If this is an FP compare, the operands have already been extended. 686 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 687 MVT::ValueType VT = Node->getOperand(0).getValueType(); 688 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 689 690 // Otherwise, we have to insert explicit sign or zero extends. Note 691 // that we could insert sign extends for ALL conditions, but zero extend 692 // is cheaper on many machines (an AND instead of two shifts), so prefer 693 // it. 694 switch (cast<SetCCSDNode>(Node)->getCondition()) { 695 default: assert(0 && "Unknown integer comparison!"); 696 case ISD::SETEQ: 697 case ISD::SETNE: 698 case ISD::SETUGE: 699 case ISD::SETUGT: 700 case ISD::SETULE: 701 case ISD::SETULT: 702 // ALL of these operations will work if we either sign or zero extend 703 // the operands (including the unsigned comparisons!). Zero extend is 704 // usually a simpler/cheaper operation, so prefer it. 705 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp1, VT); 706 Tmp2 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp2, VT); 707 break; 708 case ISD::SETGE: 709 case ISD::SETGT: 710 case ISD::SETLT: 711 case ISD::SETLE: 712 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 713 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT); 714 break; 715 } 716 717 } 718 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 719 Node->getValueType(0), Tmp1, Tmp2); 720 break; 721 case Expand: 722 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 723 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 724 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 725 switch (cast<SetCCSDNode>(Node)->getCondition()) { 726 case ISD::SETEQ: 727 case ISD::SETNE: 728 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 729 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 730 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 731 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 732 Node->getValueType(0), Tmp1, 733 DAG.getConstant(0, Tmp1.getValueType())); 734 break; 735 default: 736 // FIXME: This generated code sucks. 737 ISD::CondCode LowCC; 738 switch (cast<SetCCSDNode>(Node)->getCondition()) { 739 default: assert(0 && "Unknown integer setcc!"); 740 case ISD::SETLT: 741 case ISD::SETULT: LowCC = ISD::SETULT; break; 742 case ISD::SETGT: 743 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 744 case ISD::SETLE: 745 case ISD::SETULE: LowCC = ISD::SETULE; break; 746 case ISD::SETGE: 747 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 748 } 749 750 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 751 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 752 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 753 754 // NOTE: on targets without efficient SELECT of bools, we can always use 755 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 756 Tmp1 = DAG.getSetCC(LowCC, Node->getValueType(0), LHSLo, RHSLo); 757 Tmp2 = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 758 Node->getValueType(0), LHSHi, RHSHi); 759 Result = DAG.getSetCC(ISD::SETEQ, Node->getValueType(0), LHSHi, RHSHi); 760 Result = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 761 Result, Tmp1, Tmp2); 762 break; 763 } 764 } 765 break; 766 767 case ISD::MEMSET: 768 case ISD::MEMCPY: 769 case ISD::MEMMOVE: { 770 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 771 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 772 773 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 774 switch (getTypeAction(Node->getOperand(2).getValueType())) { 775 case Expand: assert(0 && "Cannot expand a byte!"); 776 case Legal: 777 Tmp3 = LegalizeOp(Node->getOperand(2)); 778 break; 779 case Promote: 780 Tmp3 = PromoteOp(Node->getOperand(2)); 781 break; 782 } 783 } else { 784 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 785 } 786 787 SDOperand Tmp4; 788 switch (getTypeAction(Node->getOperand(3).getValueType())) { 789 case Expand: assert(0 && "Cannot expand this yet!"); 790 case Legal: 791 Tmp4 = LegalizeOp(Node->getOperand(3)); 792 break; 793 case Promote: 794 Tmp4 = PromoteOp(Node->getOperand(3)); 795 break; 796 } 797 798 SDOperand Tmp5; 799 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 800 case Expand: assert(0 && "Cannot expand this yet!"); 801 case Legal: 802 Tmp5 = LegalizeOp(Node->getOperand(4)); 803 break; 804 case Promote: 805 Tmp5 = PromoteOp(Node->getOperand(4)); 806 break; 807 } 808 809 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 810 default: assert(0 && "This action not implemented for this operation!"); 811 case TargetLowering::Legal: 812 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 813 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 814 Tmp5 != Node->getOperand(4)) { 815 std::vector<SDOperand> Ops; 816 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 817 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 818 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 819 } 820 break; 821 case TargetLowering::Expand: { 822 // Otherwise, the target does not support this operation. Lower the 823 // operation to an explicit libcall as appropriate. 824 MVT::ValueType IntPtr = TLI.getPointerTy(); 825 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 826 std::vector<std::pair<SDOperand, const Type*> > Args; 827 828 const char *FnName = 0; 829 if (Node->getOpcode() == ISD::MEMSET) { 830 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 831 // Extend the ubyte argument to be an int value for the call. 832 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 833 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 834 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 835 836 FnName = "memset"; 837 } else if (Node->getOpcode() == ISD::MEMCPY || 838 Node->getOpcode() == ISD::MEMMOVE) { 839 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 840 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 841 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 842 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 843 } else { 844 assert(0 && "Unknown op!"); 845 } 846 std::pair<SDOperand,SDOperand> CallResult = 847 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, 848 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 849 Result = LegalizeOp(CallResult.second); 850 break; 851 } 852 case TargetLowering::Custom: 853 std::vector<SDOperand> Ops; 854 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 855 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 856 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 857 Result = TLI.LowerOperation(Result); 858 Result = LegalizeOp(Result); 859 break; 860 } 861 break; 862 } 863 case ISD::ADD_PARTS: 864 case ISD::SUB_PARTS: 865 case ISD::SHL_PARTS: 866 case ISD::SRA_PARTS: 867 case ISD::SRL_PARTS: { 868 std::vector<SDOperand> Ops; 869 bool Changed = false; 870 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 871 Ops.push_back(LegalizeOp(Node->getOperand(i))); 872 Changed |= Ops.back() != Node->getOperand(i); 873 } 874 if (Changed) 875 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 876 877 // Since these produce multiple values, make sure to remember that we 878 // legalized all of them. 879 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 880 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 881 return Result.getValue(Op.ResNo); 882 } 883 884 // Binary operators 885 case ISD::ADD: 886 case ISD::SUB: 887 case ISD::MUL: 888 case ISD::UDIV: 889 case ISD::SDIV: 890 case ISD::AND: 891 case ISD::OR: 892 case ISD::XOR: 893 case ISD::SHL: 894 case ISD::SRL: 895 case ISD::SRA: 896 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 897 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 898 if (Tmp1 != Node->getOperand(0) || 899 Tmp2 != Node->getOperand(1)) 900 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 901 break; 902 903 case ISD::UREM: 904 case ISD::SREM: 905 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 906 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 907 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 908 case TargetLowering::Legal: 909 if (Tmp1 != Node->getOperand(0) || 910 Tmp2 != Node->getOperand(1)) 911 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 912 Tmp2); 913 break; 914 case TargetLowering::Promote: 915 case TargetLowering::Custom: 916 assert(0 && "Cannot promote/custom handle this yet!"); 917 case TargetLowering::Expand: { 918 MVT::ValueType VT = Node->getValueType(0); 919 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 920 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 921 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 922 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 923 } 924 break; 925 } 926 break; 927 928 // Unary operators 929 case ISD::FABS: 930 case ISD::FNEG: 931 Tmp1 = LegalizeOp(Node->getOperand(0)); 932 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 933 case TargetLowering::Legal: 934 if (Tmp1 != Node->getOperand(0)) 935 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 936 break; 937 case TargetLowering::Promote: 938 case TargetLowering::Custom: 939 assert(0 && "Cannot promote/custom handle this yet!"); 940 case TargetLowering::Expand: 941 if (Node->getOpcode() == ISD::FNEG) { 942 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 943 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 944 Result = LegalizeOp(DAG.getNode(ISD::SUB, Node->getValueType(0), 945 Tmp2, Tmp1)); 946 } else if (Node->getOpcode() == ISD::FABS) { 947 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 948 MVT::ValueType VT = Node->getValueType(0); 949 Tmp2 = DAG.getConstantFP(0.0, VT); 950 Tmp2 = DAG.getSetCC(ISD::SETUGT, TLI.getSetCCResultTy(), Tmp1, Tmp2); 951 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 952 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 953 Result = LegalizeOp(Result); 954 } else { 955 assert(0 && "Unreachable!"); 956 } 957 break; 958 } 959 break; 960 961 // Conversion operators. The source and destination have different types. 962 case ISD::ZERO_EXTEND: 963 case ISD::SIGN_EXTEND: 964 case ISD::TRUNCATE: 965 case ISD::FP_EXTEND: 966 case ISD::FP_ROUND: 967 case ISD::FP_TO_SINT: 968 case ISD::FP_TO_UINT: 969 case ISD::SINT_TO_FP: 970 case ISD::UINT_TO_FP: 971 switch (getTypeAction(Node->getOperand(0).getValueType())) { 972 case Legal: 973 Tmp1 = LegalizeOp(Node->getOperand(0)); 974 if (Tmp1 != Node->getOperand(0)) 975 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 976 break; 977 case Expand: 978 if (Node->getOpcode() == ISD::SINT_TO_FP || 979 Node->getOpcode() == ISD::UINT_TO_FP) { 980 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 981 Node->getValueType(0), Node->getOperand(0)); 982 Result = LegalizeOp(Result); 983 break; 984 } else if (Node->getOpcode() == ISD::TRUNCATE) { 985 // In the expand case, we must be dealing with a truncate, because 986 // otherwise the result would be larger than the source. 987 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 988 989 // Since the result is legal, we should just be able to truncate the low 990 // part of the source. 991 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 992 break; 993 } 994 assert(0 && "Shouldn't need to expand other operators here!"); 995 996 case Promote: 997 switch (Node->getOpcode()) { 998 case ISD::ZERO_EXTEND: 999 Result = PromoteOp(Node->getOperand(0)); 1000 // NOTE: Any extend would work here... 1001 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result); 1002 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Op.getValueType(), 1003 Result, Node->getOperand(0).getValueType()); 1004 break; 1005 case ISD::SIGN_EXTEND: 1006 Result = PromoteOp(Node->getOperand(0)); 1007 // NOTE: Any extend would work here... 1008 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result); 1009 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1010 Result, Node->getOperand(0).getValueType()); 1011 break; 1012 case ISD::TRUNCATE: 1013 Result = PromoteOp(Node->getOperand(0)); 1014 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 1015 break; 1016 case ISD::FP_EXTEND: 1017 Result = PromoteOp(Node->getOperand(0)); 1018 if (Result.getValueType() != Op.getValueType()) 1019 // Dynamically dead while we have only 2 FP types. 1020 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 1021 break; 1022 case ISD::FP_ROUND: 1023 case ISD::FP_TO_SINT: 1024 case ISD::FP_TO_UINT: 1025 Result = PromoteOp(Node->getOperand(0)); 1026 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 1027 break; 1028 case ISD::SINT_TO_FP: 1029 Result = PromoteOp(Node->getOperand(0)); 1030 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1031 Result, Node->getOperand(0).getValueType()); 1032 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 1033 break; 1034 case ISD::UINT_TO_FP: 1035 Result = PromoteOp(Node->getOperand(0)); 1036 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Result.getValueType(), 1037 Result, Node->getOperand(0).getValueType()); 1038 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 1039 break; 1040 } 1041 } 1042 break; 1043 case ISD::FP_ROUND_INREG: 1044 case ISD::SIGN_EXTEND_INREG: 1045 case ISD::ZERO_EXTEND_INREG: { 1046 Tmp1 = LegalizeOp(Node->getOperand(0)); 1047 MVT::ValueType ExtraVT = cast<MVTSDNode>(Node)->getExtraValueType(); 1048 1049 // If this operation is not supported, convert it to a shl/shr or load/store 1050 // pair. 1051 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 1052 default: assert(0 && "This action not supported for this op yet!"); 1053 case TargetLowering::Legal: 1054 if (Tmp1 != Node->getOperand(0)) 1055 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 1056 ExtraVT); 1057 break; 1058 case TargetLowering::Expand: 1059 // If this is an integer extend and shifts are supported, do that. 1060 if (Node->getOpcode() == ISD::ZERO_EXTEND_INREG) { 1061 // NOTE: we could fall back on load/store here too for targets without 1062 // AND. However, it is doubtful that any exist. 1063 // AND out the appropriate bits. 1064 SDOperand Mask = 1065 DAG.getConstant((1ULL << MVT::getSizeInBits(ExtraVT))-1, 1066 Node->getValueType(0)); 1067 Result = DAG.getNode(ISD::AND, Node->getValueType(0), 1068 Node->getOperand(0), Mask); 1069 } else if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 1070 // NOTE: we could fall back on load/store here too for targets without 1071 // SAR. However, it is doubtful that any exist. 1072 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 1073 MVT::getSizeInBits(ExtraVT); 1074 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 1075 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 1076 Node->getOperand(0), ShiftCst); 1077 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 1078 Result, ShiftCst); 1079 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 1080 // The only way we can lower this is to turn it into a STORETRUNC, 1081 // EXTLOAD pair, targetting a temporary location (a stack slot). 1082 1083 // NOTE: there is a choice here between constantly creating new stack 1084 // slots and always reusing the same one. We currently always create 1085 // new ones, as reuse may inhibit scheduling. 1086 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 1087 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 1088 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 1089 MachineFunction &MF = DAG.getMachineFunction(); 1090 int SSFI = 1091 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 1092 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 1093 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 1094 Node->getOperand(0), StackSlot, ExtraVT); 1095 Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0), 1096 Result, StackSlot, ExtraVT); 1097 } else { 1098 assert(0 && "Unknown op"); 1099 } 1100 Result = LegalizeOp(Result); 1101 break; 1102 } 1103 break; 1104 } 1105 } 1106 1107 if (!Op.Val->hasOneUse()) 1108 AddLegalizedOperand(Op, Result); 1109 1110 return Result; 1111} 1112 1113/// PromoteOp - Given an operation that produces a value in an invalid type, 1114/// promote it to compute the value into a larger type. The produced value will 1115/// have the correct bits for the low portion of the register, but no guarantee 1116/// is made about the top bits: it may be zero, sign-extended, or garbage. 1117SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 1118 MVT::ValueType VT = Op.getValueType(); 1119 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1120 assert(getTypeAction(VT) == Promote && 1121 "Caller should expand or legalize operands that are not promotable!"); 1122 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 1123 "Cannot promote to smaller type!"); 1124 1125 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 1126 if (I != PromotedNodes.end()) return I->second; 1127 1128 SDOperand Tmp1, Tmp2, Tmp3; 1129 1130 SDOperand Result; 1131 SDNode *Node = Op.Val; 1132 1133 // Promotion needs an optimization step to clean up after it, and is not 1134 // careful to avoid operations the target does not support. Make sure that 1135 // all generated operations are legalized in the next iteration. 1136 NeedsAnotherIteration = true; 1137 1138 switch (Node->getOpcode()) { 1139 default: 1140 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 1141 assert(0 && "Do not know how to promote this operator!"); 1142 abort(); 1143 case ISD::UNDEF: 1144 Result = DAG.getNode(ISD::UNDEF, NVT); 1145 break; 1146 case ISD::Constant: 1147 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 1148 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 1149 break; 1150 case ISD::ConstantFP: 1151 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 1152 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 1153 break; 1154 case ISD::CopyFromReg: 1155 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), NVT, 1156 Node->getOperand(0)); 1157 // Remember that we legalized the chain. 1158 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1159 break; 1160 1161 case ISD::SETCC: 1162 assert(getTypeAction(TLI.getSetCCResultTy()) == Legal && 1163 "SetCC type is not legal??"); 1164 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 1165 TLI.getSetCCResultTy(), Node->getOperand(0), 1166 Node->getOperand(1)); 1167 Result = LegalizeOp(Result); 1168 break; 1169 1170 case ISD::TRUNCATE: 1171 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1172 case Legal: 1173 Result = LegalizeOp(Node->getOperand(0)); 1174 assert(Result.getValueType() >= NVT && 1175 "This truncation doesn't make sense!"); 1176 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 1177 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 1178 break; 1179 case Promote: 1180 // The truncation is not required, because we don't guarantee anything 1181 // about high bits anyway. 1182 Result = PromoteOp(Node->getOperand(0)); 1183 break; 1184 case Expand: 1185 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1186 // Truncate the low part of the expanded value to the result type 1187 Result = DAG.getNode(ISD::TRUNCATE, VT, Tmp1); 1188 } 1189 break; 1190 case ISD::SIGN_EXTEND: 1191 case ISD::ZERO_EXTEND: 1192 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1193 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 1194 case Legal: 1195 // Input is legal? Just do extend all the way to the larger type. 1196 Result = LegalizeOp(Node->getOperand(0)); 1197 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 1198 break; 1199 case Promote: 1200 // Promote the reg if it's smaller. 1201 Result = PromoteOp(Node->getOperand(0)); 1202 // The high bits are not guaranteed to be anything. Insert an extend. 1203 if (Node->getOpcode() == ISD::SIGN_EXTEND) 1204 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 1205 Node->getOperand(0).getValueType()); 1206 else 1207 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Result, 1208 Node->getOperand(0).getValueType()); 1209 break; 1210 } 1211 break; 1212 1213 case ISD::FP_EXTEND: 1214 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 1215 case ISD::FP_ROUND: 1216 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1217 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 1218 case Promote: assert(0 && "Unreachable with 2 FP types!"); 1219 case Legal: 1220 // Input is legal? Do an FP_ROUND_INREG. 1221 Result = LegalizeOp(Node->getOperand(0)); 1222 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1223 break; 1224 } 1225 break; 1226 1227 case ISD::SINT_TO_FP: 1228 case ISD::UINT_TO_FP: 1229 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1230 case Legal: 1231 Result = LegalizeOp(Node->getOperand(0)); 1232 // No extra round required here. 1233 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 1234 break; 1235 1236 case Promote: 1237 Result = PromoteOp(Node->getOperand(0)); 1238 if (Node->getOpcode() == ISD::SINT_TO_FP) 1239 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1240 Result, Node->getOperand(0).getValueType()); 1241 else 1242 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Result.getValueType(), 1243 Result, Node->getOperand(0).getValueType()); 1244 // No extra round required here. 1245 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 1246 break; 1247 case Expand: 1248 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 1249 Node->getOperand(0)); 1250 Result = LegalizeOp(Result); 1251 1252 // Round if we cannot tolerate excess precision. 1253 if (NoExcessFPPrecision) 1254 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1255 break; 1256 } 1257 break; 1258 1259 case ISD::FP_TO_SINT: 1260 case ISD::FP_TO_UINT: 1261 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1262 case Legal: 1263 Tmp1 = LegalizeOp(Node->getOperand(0)); 1264 break; 1265 case Promote: 1266 // The input result is prerounded, so we don't have to do anything 1267 // special. 1268 Tmp1 = PromoteOp(Node->getOperand(0)); 1269 break; 1270 case Expand: 1271 assert(0 && "not implemented"); 1272 } 1273 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 1274 break; 1275 1276 case ISD::FABS: 1277 case ISD::FNEG: 1278 Tmp1 = PromoteOp(Node->getOperand(0)); 1279 assert(Tmp1.getValueType() == NVT); 1280 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 1281 // NOTE: we do not have to do any extra rounding here for 1282 // NoExcessFPPrecision, because we know the input will have the appropriate 1283 // precision, and these operations don't modify precision at all. 1284 break; 1285 1286 case ISD::AND: 1287 case ISD::OR: 1288 case ISD::XOR: 1289 case ISD::ADD: 1290 case ISD::SUB: 1291 case ISD::MUL: 1292 // The input may have strange things in the top bits of the registers, but 1293 // these operations don't care. They may have wierd bits going out, but 1294 // that too is okay if they are integer operations. 1295 Tmp1 = PromoteOp(Node->getOperand(0)); 1296 Tmp2 = PromoteOp(Node->getOperand(1)); 1297 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 1298 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1299 1300 // However, if this is a floating point operation, they will give excess 1301 // precision that we may not be able to tolerate. If we DO allow excess 1302 // precision, just leave it, otherwise excise it. 1303 // FIXME: Why would we need to round FP ops more than integer ones? 1304 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 1305 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 1306 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1307 break; 1308 1309 case ISD::SDIV: 1310 case ISD::SREM: 1311 // These operators require that their input be sign extended. 1312 Tmp1 = PromoteOp(Node->getOperand(0)); 1313 Tmp2 = PromoteOp(Node->getOperand(1)); 1314 if (MVT::isInteger(NVT)) { 1315 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 1316 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT); 1317 } 1318 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1319 1320 // Perform FP_ROUND: this is probably overly pessimistic. 1321 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 1322 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1323 break; 1324 1325 case ISD::UDIV: 1326 case ISD::UREM: 1327 // These operators require that their input be zero extended. 1328 Tmp1 = PromoteOp(Node->getOperand(0)); 1329 Tmp2 = PromoteOp(Node->getOperand(1)); 1330 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 1331 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp1, VT); 1332 Tmp2 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp2, VT); 1333 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1334 break; 1335 1336 case ISD::SHL: 1337 Tmp1 = PromoteOp(Node->getOperand(0)); 1338 Tmp2 = LegalizeOp(Node->getOperand(1)); 1339 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 1340 break; 1341 case ISD::SRA: 1342 // The input value must be properly sign extended. 1343 Tmp1 = PromoteOp(Node->getOperand(0)); 1344 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 1345 Tmp2 = LegalizeOp(Node->getOperand(1)); 1346 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 1347 break; 1348 case ISD::SRL: 1349 // The input value must be properly zero extended. 1350 Tmp1 = PromoteOp(Node->getOperand(0)); 1351 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp1, VT); 1352 Tmp2 = LegalizeOp(Node->getOperand(1)); 1353 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 1354 break; 1355 case ISD::LOAD: 1356 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1357 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1358 // FIXME: When the DAG combiner exists, change this to use EXTLOAD! 1359 Result = DAG.getNode(ISD::ZEXTLOAD, NVT, Tmp1, Tmp2, VT); 1360 1361 // Remember that we legalized the chain. 1362 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1363 break; 1364 case ISD::SELECT: 1365 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1366 case Expand: assert(0 && "It's impossible to expand bools"); 1367 case Legal: 1368 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 1369 break; 1370 case Promote: 1371 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1372 break; 1373 } 1374 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 1375 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 1376 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 1377 break; 1378 case ISD::CALL: { 1379 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1380 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 1381 1382 std::vector<SDOperand> Ops; 1383 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 1384 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1385 1386 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 1387 "Can only promote single result calls"); 1388 std::vector<MVT::ValueType> RetTyVTs; 1389 RetTyVTs.reserve(2); 1390 RetTyVTs.push_back(NVT); 1391 RetTyVTs.push_back(MVT::Other); 1392 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops); 1393 Result = SDOperand(NC, 0); 1394 1395 // Insert the new chain mapping. 1396 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1397 break; 1398 } 1399 } 1400 1401 assert(Result.Val && "Didn't set a result!"); 1402 AddPromotedOperand(Op, Result); 1403 return Result; 1404} 1405 1406/// ExpandAddSub - Find a clever way to expand this add operation into 1407/// subcomponents. 1408void SelectionDAGLegalize:: 1409ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 1410 SDOperand &Lo, SDOperand &Hi) { 1411 // Expand the subcomponents. 1412 SDOperand LHSL, LHSH, RHSL, RHSH; 1413 ExpandOp(LHS, LHSL, LHSH); 1414 ExpandOp(RHS, RHSL, RHSH); 1415 1416 // Convert this add to the appropriate ADDC pair. The low part has no carry 1417 // in. 1418 std::vector<SDOperand> Ops; 1419 Ops.push_back(LHSL); 1420 Ops.push_back(LHSH); 1421 Ops.push_back(RHSL); 1422 Ops.push_back(RHSH); 1423 Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops); 1424 Hi = Lo.getValue(1); 1425} 1426 1427void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 1428 SDOperand Op, SDOperand Amt, 1429 SDOperand &Lo, SDOperand &Hi) { 1430 // Expand the subcomponents. 1431 SDOperand LHSL, LHSH; 1432 ExpandOp(Op, LHSL, LHSH); 1433 1434 std::vector<SDOperand> Ops; 1435 Ops.push_back(LHSL); 1436 Ops.push_back(LHSH); 1437 Ops.push_back(Amt); 1438 Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops); 1439 Hi = Lo.getValue(1); 1440} 1441 1442 1443/// ExpandShift - Try to find a clever way to expand this shift operation out to 1444/// smaller elements. If we can't find a way that is more efficient than a 1445/// libcall on this target, return false. Otherwise, return true with the 1446/// low-parts expanded into Lo and Hi. 1447bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 1448 SDOperand &Lo, SDOperand &Hi) { 1449 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 1450 "This is not a shift!"); 1451 1452 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 1453 SDOperand ShAmt = LegalizeOp(Amt); 1454 MVT::ValueType ShTy = ShAmt.getValueType(); 1455 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 1456 unsigned NVTBits = MVT::getSizeInBits(NVT); 1457 1458 // Handle the case when Amt is an immediate. Other cases are currently broken 1459 // and are disabled. 1460 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 1461 unsigned Cst = CN->getValue(); 1462 // Expand the incoming operand to be shifted, so that we have its parts 1463 SDOperand InL, InH; 1464 ExpandOp(Op, InL, InH); 1465 switch(Opc) { 1466 case ISD::SHL: 1467 if (Cst > VTBits) { 1468 Lo = DAG.getConstant(0, NVT); 1469 Hi = DAG.getConstant(0, NVT); 1470 } else if (Cst > NVTBits) { 1471 Lo = DAG.getConstant(0, NVT); 1472 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 1473 } else { 1474 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 1475 Hi = DAG.getNode(ISD::OR, NVT, 1476 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 1477 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 1478 } 1479 return true; 1480 case ISD::SRL: 1481 if (Cst > VTBits) { 1482 Lo = DAG.getConstant(0, NVT); 1483 Hi = DAG.getConstant(0, NVT); 1484 } else if (Cst > NVTBits) { 1485 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 1486 Hi = DAG.getConstant(0, NVT); 1487 } else { 1488 Lo = DAG.getNode(ISD::OR, NVT, 1489 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 1490 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 1491 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 1492 } 1493 return true; 1494 case ISD::SRA: 1495 if (Cst > VTBits) { 1496 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 1497 DAG.getConstant(NVTBits-1, ShTy)); 1498 } else if (Cst > NVTBits) { 1499 Lo = DAG.getNode(ISD::SRA, NVT, InH, 1500 DAG.getConstant(Cst-NVTBits, ShTy)); 1501 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1502 DAG.getConstant(NVTBits-1, ShTy)); 1503 } else { 1504 Lo = DAG.getNode(ISD::OR, NVT, 1505 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 1506 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 1507 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 1508 } 1509 return true; 1510 } 1511 } 1512 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 1513 // so disable it for now. Currently targets are handling this via SHL_PARTS 1514 // and friends. 1515 return false; 1516 1517 // If we have an efficient select operation (or if the selects will all fold 1518 // away), lower to some complex code, otherwise just emit the libcall. 1519 if (TLI.getOperationAction(ISD::SELECT, NVT) != TargetLowering::Legal && 1520 !isa<ConstantSDNode>(Amt)) 1521 return false; 1522 1523 SDOperand InL, InH; 1524 ExpandOp(Op, InL, InH); 1525 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 1526 DAG.getConstant(NVTBits, ShTy), ShAmt); 1527 1528 // Compare the unmasked shift amount against 32. 1529 SDOperand Cond = DAG.getSetCC(ISD::SETGE, TLI.getSetCCResultTy(), ShAmt, 1530 DAG.getConstant(NVTBits, ShTy)); 1531 1532 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 1533 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 1534 DAG.getConstant(NVTBits-1, ShTy)); 1535 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 1536 DAG.getConstant(NVTBits-1, ShTy)); 1537 } 1538 1539 if (Opc == ISD::SHL) { 1540 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 1541 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 1542 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 1543 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 1544 1545 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 1546 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 1547 } else { 1548 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 1549 DAG.getSetCC(ISD::SETEQ, 1550 TLI.getSetCCResultTy(), NAmt, 1551 DAG.getConstant(32, ShTy)), 1552 DAG.getConstant(0, NVT), 1553 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 1554 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 1555 HiLoPart, 1556 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 1557 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 1558 1559 SDOperand HiPart; 1560 if (Opc == ISD::SRA) 1561 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 1562 DAG.getConstant(NVTBits-1, ShTy)); 1563 else 1564 HiPart = DAG.getConstant(0, NVT); 1565 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 1566 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 1567 } 1568 return true; 1569} 1570 1571/// FindLatestAdjCallStackDown - Scan up the dag to find the latest (highest 1572/// NodeDepth) node that is an AdjCallStackDown operation and occurs later than 1573/// Found. 1574static void FindLatestAdjCallStackDown(SDNode *Node, SDNode *&Found) { 1575 if (Node->getNodeDepth() <= Found->getNodeDepth()) return; 1576 1577 // If we found an ADJCALLSTACKDOWN, we already know this node occurs later 1578 // than the Found node. Just remember this node and return. 1579 if (Node->getOpcode() == ISD::ADJCALLSTACKDOWN) { 1580 Found = Node; 1581 return; 1582 } 1583 1584 // Otherwise, scan the operands of Node to see if any of them is a call. 1585 assert(Node->getNumOperands() != 0 && 1586 "All leaves should have depth equal to the entry node!"); 1587 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 1588 FindLatestAdjCallStackDown(Node->getOperand(i).Val, Found); 1589 1590 // Tail recurse for the last iteration. 1591 FindLatestAdjCallStackDown(Node->getOperand(Node->getNumOperands()-1).Val, 1592 Found); 1593} 1594 1595 1596/// FindEarliestAdjCallStackUp - Scan down the dag to find the earliest (lowest 1597/// NodeDepth) node that is an AdjCallStackUp operation and occurs more recent 1598/// than Found. 1599static void FindEarliestAdjCallStackUp(SDNode *Node, SDNode *&Found) { 1600 if (Found && Node->getNodeDepth() >= Found->getNodeDepth()) return; 1601 1602 // If we found an ADJCALLSTACKUP, we already know this node occurs earlier 1603 // than the Found node. Just remember this node and return. 1604 if (Node->getOpcode() == ISD::ADJCALLSTACKUP) { 1605 Found = Node; 1606 return; 1607 } 1608 1609 // Otherwise, scan the operands of Node to see if any of them is a call. 1610 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 1611 if (UI == E) return; 1612 for (--E; UI != E; ++UI) 1613 FindEarliestAdjCallStackUp(*UI, Found); 1614 1615 // Tail recurse for the last iteration. 1616 FindEarliestAdjCallStackUp(*UI, Found); 1617} 1618 1619/// FindAdjCallStackUp - Given a chained node that is part of a call sequence, 1620/// find the ADJCALLSTACKUP node that terminates the call sequence. 1621static SDNode *FindAdjCallStackUp(SDNode *Node) { 1622 if (Node->getOpcode() == ISD::ADJCALLSTACKUP) 1623 return Node; 1624 if (Node->use_empty()) 1625 return 0; // No adjcallstackup 1626 1627 if (Node->hasOneUse()) // Simple case, only has one user to check. 1628 return FindAdjCallStackUp(*Node->use_begin()); 1629 1630 SDOperand TheChain(Node, Node->getNumValues()-1); 1631 assert(TheChain.getValueType() == MVT::Other && "Is not a token chain!"); 1632 1633 for (SDNode::use_iterator UI = Node->use_begin(), 1634 E = Node->use_end(); ; ++UI) { 1635 assert(UI != E && "Didn't find a user of the tokchain, no ADJCALLSTACKUP!"); 1636 1637 // Make sure to only follow users of our token chain. 1638 SDNode *User = *UI; 1639 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 1640 if (User->getOperand(i) == TheChain) 1641 return FindAdjCallStackUp(User); 1642 } 1643 assert(0 && "Unreachable"); 1644 abort(); 1645} 1646 1647/// FindInputOutputChains - If we are replacing an operation with a call we need 1648/// to find the call that occurs before and the call that occurs after it to 1649/// properly serialize the calls in the block. 1650static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 1651 SDOperand Entry) { 1652 SDNode *LatestAdjCallStackDown = Entry.Val; 1653 FindLatestAdjCallStackDown(OpNode, LatestAdjCallStackDown); 1654 //std::cerr << "Found node: "; LatestAdjCallStackDown->dump(); std::cerr <<"\n"; 1655 1656 SDNode *LatestAdjCallStackUp = FindAdjCallStackUp(LatestAdjCallStackDown); 1657 1658 1659 SDNode *EarliestAdjCallStackUp = 0; 1660 FindEarliestAdjCallStackUp(OpNode, EarliestAdjCallStackUp); 1661 1662 if (EarliestAdjCallStackUp) { 1663 //std::cerr << "Found node: "; 1664 //EarliestAdjCallStackUp->dump(); std::cerr <<"\n"; 1665 } 1666 1667 return SDOperand(LatestAdjCallStackUp, 0); 1668} 1669 1670 1671 1672// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1673// does not fit into a register, return the lo part and set the hi part to the 1674// by-reg argument. If it does fit into a single register, return the result 1675// and leave the Hi part unset. 1676SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 1677 SDOperand &Hi) { 1678 SDNode *OutChain; 1679 SDOperand InChain = FindInputOutputChains(Node, OutChain, 1680 DAG.getEntryNode()); 1681 if (InChain.Val == 0) 1682 InChain = DAG.getEntryNode(); 1683 1684 TargetLowering::ArgListTy Args; 1685 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1686 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 1687 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 1688 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 1689 } 1690 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 1691 1692 // We don't care about token chains for libcalls. We just use the entry 1693 // node as our input and ignore the output chain. This allows us to place 1694 // calls wherever we need them to satisfy data dependences. 1695 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 1696 SDOperand Result = TLI.LowerCallTo(InChain, RetTy, false, Callee, 1697 Args, DAG).first; 1698 switch (getTypeAction(Result.getValueType())) { 1699 default: assert(0 && "Unknown thing"); 1700 case Legal: 1701 return Result; 1702 case Promote: 1703 assert(0 && "Cannot promote this yet!"); 1704 case Expand: 1705 SDOperand Lo; 1706 ExpandOp(Result, Lo, Hi); 1707 return Lo; 1708 } 1709} 1710 1711 1712/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 1713/// destination type is legal. 1714SDOperand SelectionDAGLegalize:: 1715ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 1716 assert(getTypeAction(DestTy) == Legal && "Destination type is not legal!"); 1717 assert(getTypeAction(Source.getValueType()) == Expand && 1718 "This is not an expansion!"); 1719 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 1720 1721 SDNode *OutChain; 1722 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 1723 DAG.getEntryNode()); 1724 1725 const char *FnName = 0; 1726 if (isSigned) { 1727 if (DestTy == MVT::f32) 1728 FnName = "__floatdisf"; 1729 else { 1730 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 1731 FnName = "__floatdidf"; 1732 } 1733 } else { 1734 // If this is unsigned, and not supported, first perform the conversion to 1735 // signed, then adjust the result if the sign bit is set. 1736 SDOperand SignedConv = ExpandIntToFP(false, DestTy, Source); 1737 1738 assert(0 && "Unsigned casts not supported yet!"); 1739 } 1740 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 1741 1742 TargetLowering::ArgListTy Args; 1743 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 1744 Args.push_back(std::make_pair(Source, ArgTy)); 1745 1746 // We don't care about token chains for libcalls. We just use the entry 1747 // node as our input and ignore the output chain. This allows us to place 1748 // calls wherever we need them to satisfy data dependences. 1749 const Type *RetTy = MVT::getTypeForValueType(DestTy); 1750 return TLI.LowerCallTo(InChain, RetTy, false, Callee, Args, DAG).first; 1751 1752} 1753 1754 1755 1756/// ExpandOp - Expand the specified SDOperand into its two component pieces 1757/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 1758/// LegalizeNodes map is filled in for any results that are not expanded, the 1759/// ExpandedNodes map is filled in for any results that are expanded, and the 1760/// Lo/Hi values are returned. 1761void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 1762 MVT::ValueType VT = Op.getValueType(); 1763 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1764 SDNode *Node = Op.Val; 1765 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 1766 assert(MVT::isInteger(VT) && "Cannot expand FP values!"); 1767 assert(MVT::isInteger(NVT) && NVT < VT && 1768 "Cannot expand to FP value or to larger int value!"); 1769 1770 // If there is more than one use of this, see if we already expanded it. 1771 // There is no use remembering values that only have a single use, as the map 1772 // entries will never be reused. 1773 if (!Node->hasOneUse()) { 1774 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 1775 = ExpandedNodes.find(Op); 1776 if (I != ExpandedNodes.end()) { 1777 Lo = I->second.first; 1778 Hi = I->second.second; 1779 return; 1780 } 1781 } 1782 1783 // Expanding to multiple registers needs to perform an optimization step, and 1784 // is not careful to avoid operations the target does not support. Make sure 1785 // that all generated operations are legalized in the next iteration. 1786 NeedsAnotherIteration = true; 1787 1788 switch (Node->getOpcode()) { 1789 default: 1790 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 1791 assert(0 && "Do not know how to expand this operator!"); 1792 abort(); 1793 case ISD::UNDEF: 1794 Lo = DAG.getNode(ISD::UNDEF, NVT); 1795 Hi = DAG.getNode(ISD::UNDEF, NVT); 1796 break; 1797 case ISD::Constant: { 1798 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 1799 Lo = DAG.getConstant(Cst, NVT); 1800 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 1801 break; 1802 } 1803 1804 case ISD::CopyFromReg: { 1805 unsigned Reg = cast<RegSDNode>(Node)->getReg(); 1806 // Aggregate register values are always in consequtive pairs. 1807 Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0)); 1808 Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1)); 1809 1810 // Remember that we legalized the chain. 1811 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 1812 1813 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 1814 break; 1815 } 1816 1817 case ISD::BUILD_PAIR: 1818 // Legalize both operands. FIXME: in the future we should handle the case 1819 // where the two elements are not legal. 1820 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 1821 Lo = LegalizeOp(Node->getOperand(0)); 1822 Hi = LegalizeOp(Node->getOperand(1)); 1823 break; 1824 1825 case ISD::LOAD: { 1826 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1827 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1828 Lo = DAG.getLoad(NVT, Ch, Ptr); 1829 1830 // Increment the pointer to the other half. 1831 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 1832 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1833 getIntPtrConstant(IncrementSize)); 1834 Hi = DAG.getLoad(NVT, Ch, Ptr); 1835 1836 // Build a factor node to remember that this load is independent of the 1837 // other one. 1838 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1839 Hi.getValue(1)); 1840 1841 // Remember that we legalized the chain. 1842 AddLegalizedOperand(Op.getValue(1), TF); 1843 if (!TLI.isLittleEndian()) 1844 std::swap(Lo, Hi); 1845 break; 1846 } 1847 case ISD::CALL: { 1848 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1849 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 1850 1851 bool Changed = false; 1852 std::vector<SDOperand> Ops; 1853 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 1854 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1855 Changed |= Ops.back() != Node->getOperand(i); 1856 } 1857 1858 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 1859 "Can only expand a call once so far, not i64 -> i16!"); 1860 1861 std::vector<MVT::ValueType> RetTyVTs; 1862 RetTyVTs.reserve(3); 1863 RetTyVTs.push_back(NVT); 1864 RetTyVTs.push_back(NVT); 1865 RetTyVTs.push_back(MVT::Other); 1866 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops); 1867 Lo = SDOperand(NC, 0); 1868 Hi = SDOperand(NC, 1); 1869 1870 // Insert the new chain mapping. 1871 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 1872 break; 1873 } 1874 case ISD::AND: 1875 case ISD::OR: 1876 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 1877 SDOperand LL, LH, RL, RH; 1878 ExpandOp(Node->getOperand(0), LL, LH); 1879 ExpandOp(Node->getOperand(1), RL, RH); 1880 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 1881 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 1882 break; 1883 } 1884 case ISD::SELECT: { 1885 SDOperand C, LL, LH, RL, RH; 1886 1887 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1888 case Expand: assert(0 && "It's impossible to expand bools"); 1889 case Legal: 1890 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1891 break; 1892 case Promote: 1893 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 1894 break; 1895 } 1896 ExpandOp(Node->getOperand(1), LL, LH); 1897 ExpandOp(Node->getOperand(2), RL, RH); 1898 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 1899 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 1900 break; 1901 } 1902 case ISD::SIGN_EXTEND: { 1903 SDOperand In; 1904 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1905 case Expand: assert(0 && "expand-expand not implemented yet!"); 1906 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 1907 case Promote: 1908 In = PromoteOp(Node->getOperand(0)); 1909 // Emit the appropriate sign_extend_inreg to get the value we want. 1910 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 1911 Node->getOperand(0).getValueType()); 1912 break; 1913 } 1914 1915 // The low part is just a sign extension of the input (which degenerates to 1916 // a copy). 1917 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 1918 1919 // The high part is obtained by SRA'ing all but one of the bits of the lo 1920 // part. 1921 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 1922 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 1923 TLI.getShiftAmountTy())); 1924 break; 1925 } 1926 case ISD::ZERO_EXTEND: { 1927 SDOperand In; 1928 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1929 case Expand: assert(0 && "expand-expand not implemented yet!"); 1930 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 1931 case Promote: 1932 In = PromoteOp(Node->getOperand(0)); 1933 // Emit the appropriate zero_extend_inreg to get the value we want. 1934 In = DAG.getNode(ISD::ZERO_EXTEND_INREG, In.getValueType(), In, 1935 Node->getOperand(0).getValueType()); 1936 break; 1937 } 1938 1939 // The low part is just a zero extension of the input (which degenerates to 1940 // a copy). 1941 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 1942 1943 // The high part is just a zero. 1944 Hi = DAG.getConstant(0, NVT); 1945 break; 1946 } 1947 // These operators cannot be expanded directly, emit them as calls to 1948 // library functions. 1949 case ISD::FP_TO_SINT: 1950 if (Node->getOperand(0).getValueType() == MVT::f32) 1951 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 1952 else 1953 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 1954 break; 1955 case ISD::FP_TO_UINT: 1956 if (Node->getOperand(0).getValueType() == MVT::f32) 1957 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 1958 else 1959 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 1960 break; 1961 1962 case ISD::SHL: 1963 // If we can emit an efficient shift operation, do so now. 1964 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 1965 break; 1966 1967 // If this target supports SHL_PARTS, use it. 1968 if (TLI.getOperationAction(ISD::SHL_PARTS, NVT) == TargetLowering::Legal) { 1969 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 1970 Lo, Hi); 1971 break; 1972 } 1973 1974 // Otherwise, emit a libcall. 1975 Lo = ExpandLibCall("__ashldi3", Node, Hi); 1976 break; 1977 1978 case ISD::SRA: 1979 // If we can emit an efficient shift operation, do so now. 1980 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 1981 break; 1982 1983 // If this target supports SRA_PARTS, use it. 1984 if (TLI.getOperationAction(ISD::SRA_PARTS, NVT) == TargetLowering::Legal) { 1985 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 1986 Lo, Hi); 1987 break; 1988 } 1989 1990 // Otherwise, emit a libcall. 1991 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 1992 break; 1993 case ISD::SRL: 1994 // If we can emit an efficient shift operation, do so now. 1995 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 1996 break; 1997 1998 // If this target supports SRL_PARTS, use it. 1999 if (TLI.getOperationAction(ISD::SRL_PARTS, NVT) == TargetLowering::Legal) { 2000 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 2001 Lo, Hi); 2002 break; 2003 } 2004 2005 // Otherwise, emit a libcall. 2006 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 2007 break; 2008 2009 case ISD::ADD: 2010 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 2011 Lo, Hi); 2012 break; 2013 case ISD::SUB: 2014 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 2015 Lo, Hi); 2016 break; 2017 case ISD::MUL: Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 2018 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 2019 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 2020 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 2021 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 2022 } 2023 2024 // Remember in a map if the values will be reused later. 2025 if (!Node->hasOneUse()) { 2026 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 2027 std::make_pair(Lo, Hi))).second; 2028 assert(isNew && "Value already expanded?!?"); 2029 } 2030} 2031 2032 2033// SelectionDAG::Legalize - This is the entry point for the file. 2034// 2035void SelectionDAG::Legalize() { 2036 /// run - This is the main entry point to this class. 2037 /// 2038 SelectionDAGLegalize(*this).Run(); 2039} 2040 2041