LegalizeDAG.cpp revision 24dc346a16397bf740d8d961cd1ebec8d2f46957
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetFrameInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/Target/TargetSubtarget.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Compiler.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/ADT/DenseMap.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/SmallPtrSet.h" 35#include <map> 36using namespace llvm; 37 38//===----------------------------------------------------------------------===// 39/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 40/// hacks on it until the target machine can handle it. This involves 41/// eliminating value sizes the machine cannot handle (promoting small sizes to 42/// large sizes or splitting up large values into small values) as well as 43/// eliminating operations the machine cannot handle. 44/// 45/// This code also does a small amount of optimization and recognition of idioms 46/// as part of its processing. For example, if a target does not support a 47/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 48/// will attempt merge setcc and brc instructions into brcc's. 49/// 50namespace { 51class VISIBILITY_HIDDEN SelectionDAGLegalize { 52 TargetLowering &TLI; 53 SelectionDAG &DAG; 54 55 // Libcall insertion helpers. 56 57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 58 /// legalized. We use this to ensure that calls are properly serialized 59 /// against each other, including inserted libcalls. 60 SDValue LastCALLSEQ_END; 61 62 /// IsLegalizingCall - This member is used *only* for purposes of providing 63 /// helpful assertions that a libcall isn't created while another call is 64 /// being legalized (which could lead to non-serialized call sequences). 65 bool IsLegalizingCall; 66 67 enum LegalizeAction { 68 Legal, // The target natively supports this operation. 69 Promote, // This operation should be executed in a larger type. 70 Expand // Try to expand this to other ops, otherwise use a libcall. 71 }; 72 73 /// ValueTypeActions - This is a bitvector that contains two bits for each 74 /// value type, where the two bits correspond to the LegalizeAction enum. 75 /// This can be queried with "getTypeAction(VT)". 76 TargetLowering::ValueTypeActionImpl ValueTypeActions; 77 78 /// LegalizedNodes - For nodes that are of legal width, and that have more 79 /// than one use, this map indicates what regularized operand to use. This 80 /// allows us to avoid legalizing the same thing more than once. 81 DenseMap<SDValue, SDValue> LegalizedNodes; 82 83 /// PromotedNodes - For nodes that are below legal width, and that have more 84 /// than one use, this map indicates what promoted value to use. This allows 85 /// us to avoid promoting the same thing more than once. 86 DenseMap<SDValue, SDValue> PromotedNodes; 87 88 /// ExpandedNodes - For nodes that need to be expanded this map indicates 89 /// which which operands are the expanded version of the input. This allows 90 /// us to avoid expanding the same node more than once. 91 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes; 92 93 /// SplitNodes - For vector nodes that need to be split, this map indicates 94 /// which which operands are the split version of the input. This allows us 95 /// to avoid splitting the same node more than once. 96 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes; 97 98 /// ScalarizedNodes - For nodes that need to be converted from vector types to 99 /// scalar types, this contains the mapping of ones we have already 100 /// processed to the result. 101 std::map<SDValue, SDValue> ScalarizedNodes; 102 103 void AddLegalizedOperand(SDValue From, SDValue To) { 104 LegalizedNodes.insert(std::make_pair(From, To)); 105 // If someone requests legalization of the new node, return itself. 106 if (From != To) 107 LegalizedNodes.insert(std::make_pair(To, To)); 108 } 109 void AddPromotedOperand(SDValue From, SDValue To) { 110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 111 assert(isNew && "Got into the map somehow?"); 112 // If someone requests legalization of the new node, return itself. 113 LegalizedNodes.insert(std::make_pair(To, To)); 114 } 115 116public: 117 explicit SelectionDAGLegalize(SelectionDAG &DAG); 118 119 /// getTypeAction - Return how we should legalize values of this type, either 120 /// it is already legal or we need to expand it into multiple registers of 121 /// smaller integer type, or we need to promote it to a larger type. 122 LegalizeAction getTypeAction(MVT VT) const { 123 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 124 } 125 126 /// isTypeLegal - Return true if this type is legal on this target. 127 /// 128 bool isTypeLegal(MVT VT) const { 129 return getTypeAction(VT) == Legal; 130 } 131 132 void LegalizeDAG(); 133 134private: 135 /// HandleOp - Legalize, Promote, or Expand the specified operand as 136 /// appropriate for its type. 137 void HandleOp(SDValue Op); 138 139 /// LegalizeOp - We know that the specified value has a legal type. 140 /// Recursively ensure that the operands have legal types, then return the 141 /// result. 142 SDValue LegalizeOp(SDValue O); 143 144 /// UnrollVectorOp - We know that the given vector has a legal type, however 145 /// the operation it performs is not legal and is an operation that we have 146 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 147 /// operating on each element individually. 148 SDValue UnrollVectorOp(SDValue O); 149 150 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 151 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 152 /// is necessary to spill the vector being inserted into to memory, perform 153 /// the insert there, and then read the result back. 154 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 155 SDValue Idx); 156 157 /// PromoteOp - Given an operation that produces a value in an invalid type, 158 /// promote it to compute the value into a larger type. The produced value 159 /// will have the correct bits for the low portion of the register, but no 160 /// guarantee is made about the top bits: it may be zero, sign-extended, or 161 /// garbage. 162 SDValue PromoteOp(SDValue O); 163 164 /// ExpandOp - Expand the specified SDValue into its two component pieces 165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 166 /// the LegalizeNodes map is filled in for any results that are not expanded, 167 /// the ExpandedNodes map is filled in for any results that are expanded, and 168 /// the Lo/Hi values are returned. This applies to integer types and Vector 169 /// types. 170 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi); 171 172 /// SplitVectorOp - Given an operand of vector type, break it down into 173 /// two smaller values. 174 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi); 175 176 /// ScalarizeVectorOp - Given an operand of single-element vector type 177 /// (e.g. v1f32), convert it into the equivalent operation that returns a 178 /// scalar (e.g. f32) value. 179 SDValue ScalarizeVectorOp(SDValue O); 180 181 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the 182 /// specified mask and type. Targets can specify exactly which masks they 183 /// support and the code generator is tasked with not creating illegal masks. 184 /// 185 /// Note that this will also return true for shuffles that are promoted to a 186 /// different type. 187 /// 188 /// If this is a legal shuffle, this method returns the (possibly promoted) 189 /// build_vector Mask. If it's not a legal shuffle, it returns null. 190 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const; 191 192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 194 195 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC); 196 197 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, 198 SDValue &Hi); 199 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source); 200 201 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT); 202 SDValue ExpandBUILD_VECTOR(SDNode *Node); 203 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 204 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT); 205 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned); 206 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned); 207 208 SDValue ExpandBSWAP(SDValue Op); 209 SDValue ExpandBitCount(unsigned Opc, SDValue Op); 210 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt, 211 SDValue &Lo, SDValue &Hi); 212 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt, 213 SDValue &Lo, SDValue &Hi); 214 215 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op); 216 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op); 217}; 218} 219 220/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 221/// specified mask and type. Targets can specify exactly which masks they 222/// support and the code generator is tasked with not creating illegal masks. 223/// 224/// Note that this will also return true for shuffles that are promoted to a 225/// different type. 226SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const { 227 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 228 default: return 0; 229 case TargetLowering::Legal: 230 case TargetLowering::Custom: 231 break; 232 case TargetLowering::Promote: { 233 // If this is promoted to a different type, convert the shuffle mask and 234 // ask if it is legal in the promoted type! 235 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 236 MVT EltVT = NVT.getVectorElementType(); 237 238 // If we changed # elements, change the shuffle mask. 239 unsigned NumEltsGrowth = 240 NVT.getVectorNumElements() / VT.getVectorNumElements(); 241 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 242 if (NumEltsGrowth > 1) { 243 // Renumber the elements. 244 SmallVector<SDValue, 8> Ops; 245 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 246 SDValue InOp = Mask.getOperand(i); 247 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 248 if (InOp.getOpcode() == ISD::UNDEF) 249 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 250 else { 251 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 252 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT)); 253 } 254 } 255 } 256 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 257 } 258 VT = NVT; 259 break; 260 } 261 } 262 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 263} 264 265SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 266 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 267 ValueTypeActions(TLI.getValueTypeActions()) { 268 assert(MVT::LAST_VALUETYPE <= 32 && 269 "Too many value types for ValueTypeActions to hold!"); 270} 271 272/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 273/// contains all of a nodes operands before it contains the node. 274static void ComputeTopDownOrdering(SelectionDAG &DAG, 275 SmallVector<SDNode*, 64> &Order) { 276 277 DenseMap<SDNode*, unsigned> Visited; 278 std::vector<SDNode*> Worklist; 279 Worklist.reserve(128); 280 281 // Compute ordering from all of the leaves in the graphs, those (like the 282 // entry node) that have no operands. 283 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 284 E = DAG.allnodes_end(); I != E; ++I) { 285 if (I->getNumOperands() == 0) { 286 Visited[I] = 0 - 1U; 287 Worklist.push_back(I); 288 } 289 } 290 291 while (!Worklist.empty()) { 292 SDNode *N = Worklist.back(); 293 Worklist.pop_back(); 294 295 if (++Visited[N] != N->getNumOperands()) 296 continue; // Haven't visited all operands yet 297 298 Order.push_back(N); 299 300 // Now that we have N in, add anything that uses it if all of their operands 301 // are now done. 302 Worklist.insert(Worklist.end(), N->use_begin(), N->use_end()); 303 } 304 305 assert(Order.size() == Visited.size() && 306 Order.size() == DAG.allnodes_size() && 307 "Error: DAG is cyclic!"); 308} 309 310 311void SelectionDAGLegalize::LegalizeDAG() { 312 LastCALLSEQ_END = DAG.getEntryNode(); 313 IsLegalizingCall = false; 314 315 // The legalize process is inherently a bottom-up recursive process (users 316 // legalize their uses before themselves). Given infinite stack space, we 317 // could just start legalizing on the root and traverse the whole graph. In 318 // practice however, this causes us to run out of stack space on large basic 319 // blocks. To avoid this problem, compute an ordering of the nodes where each 320 // node is only legalized after all of its operands are legalized. 321 SmallVector<SDNode*, 64> Order; 322 ComputeTopDownOrdering(DAG, Order); 323 324 for (unsigned i = 0, e = Order.size(); i != e; ++i) 325 HandleOp(SDValue(Order[i], 0)); 326 327 // Finally, it's possible the root changed. Get the new root. 328 SDValue OldRoot = DAG.getRoot(); 329 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 330 DAG.setRoot(LegalizedNodes[OldRoot]); 331 332 ExpandedNodes.clear(); 333 LegalizedNodes.clear(); 334 PromotedNodes.clear(); 335 SplitNodes.clear(); 336 ScalarizedNodes.clear(); 337 338 // Remove dead nodes now. 339 DAG.RemoveDeadNodes(); 340} 341 342 343/// FindCallEndFromCallStart - Given a chained node that is part of a call 344/// sequence, find the CALLSEQ_END node that terminates the call sequence. 345static SDNode *FindCallEndFromCallStart(SDNode *Node) { 346 if (Node->getOpcode() == ISD::CALLSEQ_END) 347 return Node; 348 if (Node->use_empty()) 349 return 0; // No CallSeqEnd 350 351 // The chain is usually at the end. 352 SDValue TheChain(Node, Node->getNumValues()-1); 353 if (TheChain.getValueType() != MVT::Other) { 354 // Sometimes it's at the beginning. 355 TheChain = SDValue(Node, 0); 356 if (TheChain.getValueType() != MVT::Other) { 357 // Otherwise, hunt for it. 358 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 359 if (Node->getValueType(i) == MVT::Other) { 360 TheChain = SDValue(Node, i); 361 break; 362 } 363 364 // Otherwise, we walked into a node without a chain. 365 if (TheChain.getValueType() != MVT::Other) 366 return 0; 367 } 368 } 369 370 for (SDNode::use_iterator UI = Node->use_begin(), 371 E = Node->use_end(); UI != E; ++UI) { 372 373 // Make sure to only follow users of our token chain. 374 SDNode *User = *UI; 375 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 376 if (User->getOperand(i) == TheChain) 377 if (SDNode *Result = FindCallEndFromCallStart(User)) 378 return Result; 379 } 380 return 0; 381} 382 383/// FindCallStartFromCallEnd - Given a chained node that is part of a call 384/// sequence, find the CALLSEQ_START node that initiates the call sequence. 385static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 386 assert(Node && "Didn't find callseq_start for a call??"); 387 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 388 389 assert(Node->getOperand(0).getValueType() == MVT::Other && 390 "Node doesn't have a token chain argument!"); 391 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 392} 393 394/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 395/// see if any uses can reach Dest. If no dest operands can get to dest, 396/// legalize them, legalize ourself, and return false, otherwise, return true. 397/// 398/// Keep track of the nodes we fine that actually do lead to Dest in 399/// NodesLeadingTo. This avoids retraversing them exponential number of times. 400/// 401bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 402 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 403 if (N == Dest) return true; // N certainly leads to Dest :) 404 405 // If we've already processed this node and it does lead to Dest, there is no 406 // need to reprocess it. 407 if (NodesLeadingTo.count(N)) return true; 408 409 // If the first result of this node has been already legalized, then it cannot 410 // reach N. 411 switch (getTypeAction(N->getValueType(0))) { 412 case Legal: 413 if (LegalizedNodes.count(SDValue(N, 0))) return false; 414 break; 415 case Promote: 416 if (PromotedNodes.count(SDValue(N, 0))) return false; 417 break; 418 case Expand: 419 if (ExpandedNodes.count(SDValue(N, 0))) return false; 420 break; 421 } 422 423 // Okay, this node has not already been legalized. Check and legalize all 424 // operands. If none lead to Dest, then we can legalize this node. 425 bool OperandsLeadToDest = false; 426 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 427 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 428 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 429 430 if (OperandsLeadToDest) { 431 NodesLeadingTo.insert(N); 432 return true; 433 } 434 435 // Okay, this node looks safe, legalize it and return false. 436 HandleOp(SDValue(N, 0)); 437 return false; 438} 439 440/// HandleOp - Legalize, Promote, or Expand the specified operand as 441/// appropriate for its type. 442void SelectionDAGLegalize::HandleOp(SDValue Op) { 443 MVT VT = Op.getValueType(); 444 switch (getTypeAction(VT)) { 445 default: assert(0 && "Bad type action!"); 446 case Legal: (void)LegalizeOp(Op); break; 447 case Promote: (void)PromoteOp(Op); break; 448 case Expand: 449 if (!VT.isVector()) { 450 // If this is an illegal scalar, expand it into its two component 451 // pieces. 452 SDValue X, Y; 453 if (Op.getOpcode() == ISD::TargetConstant) 454 break; // Allow illegal target nodes. 455 ExpandOp(Op, X, Y); 456 } else if (VT.getVectorNumElements() == 1) { 457 // If this is an illegal single element vector, convert it to a 458 // scalar operation. 459 (void)ScalarizeVectorOp(Op); 460 } else { 461 // Otherwise, this is an illegal multiple element vector. 462 // Split it in half and legalize both parts. 463 SDValue X, Y; 464 SplitVectorOp(Op, X, Y); 465 } 466 break; 467 } 468} 469 470/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 471/// a load from the constant pool. 472static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 473 SelectionDAG &DAG, TargetLowering &TLI) { 474 bool Extend = false; 475 476 // If a FP immediate is precise when represented as a float and if the 477 // target can do an extending load from float to double, we put it into 478 // the constant pool as a float, even if it's is statically typed as a 479 // double. This shrinks FP constants and canonicalizes them for targets where 480 // an FP extending load is the same cost as a normal load (such as on the x87 481 // fp stack or PPC FP unit). 482 MVT VT = CFP->getValueType(0); 483 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF()); 484 if (!UseCP) { 485 if (VT!=MVT::f64 && VT!=MVT::f32) 486 assert(0 && "Invalid type expansion"); 487 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(), 488 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 489 } 490 491 MVT OrigVT = VT; 492 MVT SVT = VT; 493 while (SVT != MVT::f32) { 494 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 495 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 496 // Only do this if the target has a native EXTLOAD instruction from 497 // smaller type. 498 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) && 499 TLI.ShouldShrinkFPConstant(OrigVT)) { 500 const Type *SType = SVT.getTypeForMVT(); 501 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 502 VT = SVT; 503 Extend = true; 504 } 505 } 506 507 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 508 if (Extend) 509 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), 510 CPIdx, PseudoSourceValue::getConstantPool(), 511 0, VT); 512 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, 513 PseudoSourceValue::getConstantPool(), 0); 514} 515 516 517/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 518/// operations. 519static 520SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, 521 SelectionDAG &DAG, TargetLowering &TLI) { 522 MVT VT = Node->getValueType(0); 523 MVT SrcVT = Node->getOperand(1).getValueType(); 524 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 525 "fcopysign expansion only supported for f32 and f64"); 526 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 527 528 // First get the sign bit of second operand. 529 SDValue Mask1 = (SrcVT == MVT::f64) 530 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 531 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 532 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 533 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 534 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 535 // Shift right or sign-extend it if the two operands have different types. 536 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); 537 if (SizeDiff > 0) { 538 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 539 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 540 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 541 } else if (SizeDiff < 0) { 542 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit); 543 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit, 544 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy())); 545 } 546 547 // Clear the sign bit of first operand. 548 SDValue Mask2 = (VT == MVT::f64) 549 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 550 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 551 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 552 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 553 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 554 555 // Or the value with the sign bit. 556 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 557 return Result; 558} 559 560/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 561static 562SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 563 TargetLowering &TLI) { 564 SDValue Chain = ST->getChain(); 565 SDValue Ptr = ST->getBasePtr(); 566 SDValue Val = ST->getValue(); 567 MVT VT = Val.getValueType(); 568 int Alignment = ST->getAlignment(); 569 int SVOffset = ST->getSrcValueOffset(); 570 if (ST->getMemoryVT().isFloatingPoint() || 571 ST->getMemoryVT().isVector()) { 572 // Expand to a bitconvert of the value to the integer type of the 573 // same size, then a (misaligned) int store. 574 MVT intVT; 575 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128) 576 intVT = MVT::i128; 577 else if (VT.is64BitVector() || VT==MVT::f64) 578 intVT = MVT::i64; 579 else if (VT==MVT::f32) 580 intVT = MVT::i32; 581 else 582 assert(0 && "Unaligned store of unsupported type"); 583 584 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 585 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 586 SVOffset, ST->isVolatile(), Alignment); 587 } 588 assert(ST->getMemoryVT().isInteger() && 589 !ST->getMemoryVT().isVector() && 590 "Unaligned store of unknown type."); 591 // Get the half-size VT 592 MVT NewStoredVT = 593 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 594 int NumBits = NewStoredVT.getSizeInBits(); 595 int IncrementSize = NumBits / 8; 596 597 // Divide the stored value in two parts. 598 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 599 SDValue Lo = Val; 600 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 601 602 // Store the two parts 603 SDValue Store1, Store2; 604 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 605 ST->getSrcValue(), SVOffset, NewStoredVT, 606 ST->isVolatile(), Alignment); 607 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 608 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 609 Alignment = MinAlign(Alignment, IncrementSize); 610 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 611 ST->getSrcValue(), SVOffset + IncrementSize, 612 NewStoredVT, ST->isVolatile(), Alignment); 613 614 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 615} 616 617/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 618static 619SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 620 TargetLowering &TLI) { 621 int SVOffset = LD->getSrcValueOffset(); 622 SDValue Chain = LD->getChain(); 623 SDValue Ptr = LD->getBasePtr(); 624 MVT VT = LD->getValueType(0); 625 MVT LoadedVT = LD->getMemoryVT(); 626 if (VT.isFloatingPoint() || VT.isVector()) { 627 // Expand to a (misaligned) integer load of the same size, 628 // then bitconvert to floating point or vector. 629 MVT intVT; 630 if (LoadedVT.is128BitVector() || 631 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128) 632 intVT = MVT::i128; 633 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64) 634 intVT = MVT::i64; 635 else if (LoadedVT == MVT::f32) 636 intVT = MVT::i32; 637 else 638 assert(0 && "Unaligned load of unsupported type"); 639 640 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 641 SVOffset, LD->isVolatile(), 642 LD->getAlignment()); 643 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 644 if (VT.isFloatingPoint() && LoadedVT != VT) 645 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 646 647 SDValue Ops[] = { Result, Chain }; 648 return DAG.getMergeValues(Ops, 2); 649 } 650 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 651 "Unaligned load of unsupported type."); 652 653 // Compute the new VT that is half the size of the old one. This is an 654 // integer MVT. 655 unsigned NumBits = LoadedVT.getSizeInBits(); 656 MVT NewLoadedVT; 657 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 658 NumBits >>= 1; 659 660 unsigned Alignment = LD->getAlignment(); 661 unsigned IncrementSize = NumBits / 8; 662 ISD::LoadExtType HiExtType = LD->getExtensionType(); 663 664 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 665 if (HiExtType == ISD::NON_EXTLOAD) 666 HiExtType = ISD::ZEXTLOAD; 667 668 // Load the value in two parts 669 SDValue Lo, Hi; 670 if (TLI.isLittleEndian()) { 671 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 672 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 673 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 674 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 675 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 676 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 677 MinAlign(Alignment, IncrementSize)); 678 } else { 679 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 680 NewLoadedVT,LD->isVolatile(), Alignment); 681 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 682 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 683 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 684 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 685 MinAlign(Alignment, IncrementSize)); 686 } 687 688 // aggregate the two parts 689 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 690 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 691 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 692 693 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 694 Hi.getValue(1)); 695 696 SDValue Ops[] = { Result, TF }; 697 return DAG.getMergeValues(Ops, 2); 698} 699 700/// UnrollVectorOp - We know that the given vector has a legal type, however 701/// the operation it performs is not legal and is an operation that we have 702/// no way of lowering. "Unroll" the vector, splitting out the scalars and 703/// operating on each element individually. 704SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) { 705 MVT VT = Op.getValueType(); 706 assert(isTypeLegal(VT) && 707 "Caller should expand or promote operands that are not legal!"); 708 assert(Op.Val->getNumValues() == 1 && 709 "Can't unroll a vector with multiple results!"); 710 unsigned NE = VT.getVectorNumElements(); 711 MVT EltVT = VT.getVectorElementType(); 712 713 SmallVector<SDValue, 8> Scalars; 714 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 715 for (unsigned i = 0; i != NE; ++i) { 716 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 717 SDValue Operand = Op.getOperand(j); 718 MVT OperandVT = Operand.getValueType(); 719 if (OperandVT.isVector()) { 720 // A vector operand; extract a single element. 721 MVT OperandEltVT = OperandVT.getVectorElementType(); 722 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 723 OperandEltVT, 724 Operand, 725 DAG.getConstant(i, MVT::i32)); 726 } else { 727 // A scalar operand; just use it as is. 728 Operands[j] = Operand; 729 } 730 } 731 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 732 &Operands[0], Operands.size())); 733 } 734 735 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 736} 737 738/// GetFPLibCall - Return the right libcall for the given floating point type. 739static RTLIB::Libcall GetFPLibCall(MVT VT, 740 RTLIB::Libcall Call_F32, 741 RTLIB::Libcall Call_F64, 742 RTLIB::Libcall Call_F80, 743 RTLIB::Libcall Call_PPCF128) { 744 return 745 VT == MVT::f32 ? Call_F32 : 746 VT == MVT::f64 ? Call_F64 : 747 VT == MVT::f80 ? Call_F80 : 748 VT == MVT::ppcf128 ? Call_PPCF128 : 749 RTLIB::UNKNOWN_LIBCALL; 750} 751 752/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 753/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 754/// is necessary to spill the vector being inserted into to memory, perform 755/// the insert there, and then read the result back. 756SDValue SelectionDAGLegalize:: 757PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) { 758 SDValue Tmp1 = Vec; 759 SDValue Tmp2 = Val; 760 SDValue Tmp3 = Idx; 761 762 // If the target doesn't support this, we have to spill the input vector 763 // to a temporary stack slot, update the element, then reload it. This is 764 // badness. We could also load the value into a vector register (either 765 // with a "move to register" or "extload into register" instruction, then 766 // permute it into place, if the idx is a constant and if the idx is 767 // supported by the target. 768 MVT VT = Tmp1.getValueType(); 769 MVT EltVT = VT.getVectorElementType(); 770 MVT IdxVT = Tmp3.getValueType(); 771 MVT PtrVT = TLI.getPointerTy(); 772 SDValue StackPtr = DAG.CreateStackTemporary(VT); 773 774 int SPFI = cast<FrameIndexSDNode>(StackPtr.Val)->getIndex(); 775 776 // Store the vector. 777 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, 778 PseudoSourceValue::getFixedStack(SPFI), 0); 779 780 // Truncate or zero extend offset to target pointer type. 781 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 782 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 783 // Add the offset to the index. 784 unsigned EltSize = EltVT.getSizeInBits()/8; 785 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 786 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 787 // Store the scalar value. 788 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, 789 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); 790 // Load the updated vector. 791 return DAG.getLoad(VT, Ch, StackPtr, 792 PseudoSourceValue::getFixedStack(SPFI), 0); 793} 794 795/// LegalizeOp - We know that the specified value has a legal type, and 796/// that its operands are legal. Now ensure that the operation itself 797/// is legal, recursively ensuring that the operands' operations remain 798/// legal. 799SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 800 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 801 return Op; 802 803 assert(isTypeLegal(Op.getValueType()) && 804 "Caller should expand or promote operands that are not legal!"); 805 SDNode *Node = Op.Val; 806 807 // If this operation defines any values that cannot be represented in a 808 // register on this target, make sure to expand or promote them. 809 if (Node->getNumValues() > 1) { 810 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 811 if (getTypeAction(Node->getValueType(i)) != Legal) { 812 HandleOp(Op.getValue(i)); 813 assert(LegalizedNodes.count(Op) && 814 "Handling didn't add legal operands!"); 815 return LegalizedNodes[Op]; 816 } 817 } 818 819 // Note that LegalizeOp may be reentered even from single-use nodes, which 820 // means that we always must cache transformed nodes. 821 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 822 if (I != LegalizedNodes.end()) return I->second; 823 824 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 825 SDValue Result = Op; 826 bool isCustom = false; 827 828 switch (Node->getOpcode()) { 829 case ISD::FrameIndex: 830 case ISD::EntryToken: 831 case ISD::Register: 832 case ISD::BasicBlock: 833 case ISD::TargetFrameIndex: 834 case ISD::TargetJumpTable: 835 case ISD::TargetConstant: 836 case ISD::TargetConstantFP: 837 case ISD::TargetConstantPool: 838 case ISD::TargetGlobalAddress: 839 case ISD::TargetGlobalTLSAddress: 840 case ISD::TargetExternalSymbol: 841 case ISD::VALUETYPE: 842 case ISD::SRCVALUE: 843 case ISD::MEMOPERAND: 844 case ISD::CONDCODE: 845 case ISD::ARG_FLAGS: 846 // Primitives must all be legal. 847 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 848 "This must be legal!"); 849 break; 850 default: 851 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 852 // If this is a target node, legalize it by legalizing the operands then 853 // passing it through. 854 SmallVector<SDValue, 8> Ops; 855 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 856 Ops.push_back(LegalizeOp(Node->getOperand(i))); 857 858 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 859 860 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 861 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 862 return Result.getValue(Op.ResNo); 863 } 864 // Otherwise this is an unhandled builtin node. splat. 865#ifndef NDEBUG 866 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 867#endif 868 assert(0 && "Do not know how to legalize this operator!"); 869 abort(); 870 case ISD::GLOBAL_OFFSET_TABLE: 871 case ISD::GlobalAddress: 872 case ISD::GlobalTLSAddress: 873 case ISD::ExternalSymbol: 874 case ISD::ConstantPool: 875 case ISD::JumpTable: // Nothing to do. 876 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 877 default: assert(0 && "This action is not supported yet!"); 878 case TargetLowering::Custom: 879 Tmp1 = TLI.LowerOperation(Op, DAG); 880 if (Tmp1.Val) Result = Tmp1; 881 // FALLTHROUGH if the target doesn't want to lower this op after all. 882 case TargetLowering::Legal: 883 break; 884 } 885 break; 886 case ISD::FRAMEADDR: 887 case ISD::RETURNADDR: 888 // The only option for these nodes is to custom lower them. If the target 889 // does not custom lower them, then return zero. 890 Tmp1 = TLI.LowerOperation(Op, DAG); 891 if (Tmp1.Val) 892 Result = Tmp1; 893 else 894 Result = DAG.getConstant(0, TLI.getPointerTy()); 895 break; 896 case ISD::FRAME_TO_ARGS_OFFSET: { 897 MVT VT = Node->getValueType(0); 898 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 899 default: assert(0 && "This action is not supported yet!"); 900 case TargetLowering::Custom: 901 Result = TLI.LowerOperation(Op, DAG); 902 if (Result.Val) break; 903 // Fall Thru 904 case TargetLowering::Legal: 905 Result = DAG.getConstant(0, VT); 906 break; 907 } 908 } 909 break; 910 case ISD::EXCEPTIONADDR: { 911 Tmp1 = LegalizeOp(Node->getOperand(0)); 912 MVT VT = Node->getValueType(0); 913 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 914 default: assert(0 && "This action is not supported yet!"); 915 case TargetLowering::Expand: { 916 unsigned Reg = TLI.getExceptionAddressRegister(); 917 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 918 } 919 break; 920 case TargetLowering::Custom: 921 Result = TLI.LowerOperation(Op, DAG); 922 if (Result.Val) break; 923 // Fall Thru 924 case TargetLowering::Legal: { 925 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 926 Result = DAG.getMergeValues(Ops, 2); 927 break; 928 } 929 } 930 } 931 if (Result.Val->getNumValues() == 1) break; 932 933 assert(Result.Val->getNumValues() == 2 && 934 "Cannot return more than two values!"); 935 936 // Since we produced two values, make sure to remember that we 937 // legalized both of them. 938 Tmp1 = LegalizeOp(Result); 939 Tmp2 = LegalizeOp(Result.getValue(1)); 940 AddLegalizedOperand(Op.getValue(0), Tmp1); 941 AddLegalizedOperand(Op.getValue(1), Tmp2); 942 return Op.ResNo ? Tmp2 : Tmp1; 943 case ISD::EHSELECTION: { 944 Tmp1 = LegalizeOp(Node->getOperand(0)); 945 Tmp2 = LegalizeOp(Node->getOperand(1)); 946 MVT VT = Node->getValueType(0); 947 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 948 default: assert(0 && "This action is not supported yet!"); 949 case TargetLowering::Expand: { 950 unsigned Reg = TLI.getExceptionSelectorRegister(); 951 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 952 } 953 break; 954 case TargetLowering::Custom: 955 Result = TLI.LowerOperation(Op, DAG); 956 if (Result.Val) break; 957 // Fall Thru 958 case TargetLowering::Legal: { 959 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 960 Result = DAG.getMergeValues(Ops, 2); 961 break; 962 } 963 } 964 } 965 if (Result.Val->getNumValues() == 1) break; 966 967 assert(Result.Val->getNumValues() == 2 && 968 "Cannot return more than two values!"); 969 970 // Since we produced two values, make sure to remember that we 971 // legalized both of them. 972 Tmp1 = LegalizeOp(Result); 973 Tmp2 = LegalizeOp(Result.getValue(1)); 974 AddLegalizedOperand(Op.getValue(0), Tmp1); 975 AddLegalizedOperand(Op.getValue(1), Tmp2); 976 return Op.ResNo ? Tmp2 : Tmp1; 977 case ISD::EH_RETURN: { 978 MVT VT = Node->getValueType(0); 979 // The only "good" option for this node is to custom lower it. 980 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 981 default: assert(0 && "This action is not supported at all!"); 982 case TargetLowering::Custom: 983 Result = TLI.LowerOperation(Op, DAG); 984 if (Result.Val) break; 985 // Fall Thru 986 case TargetLowering::Legal: 987 // Target does not know, how to lower this, lower to noop 988 Result = LegalizeOp(Node->getOperand(0)); 989 break; 990 } 991 } 992 break; 993 case ISD::AssertSext: 994 case ISD::AssertZext: 995 Tmp1 = LegalizeOp(Node->getOperand(0)); 996 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 997 break; 998 case ISD::MERGE_VALUES: 999 // Legalize eliminates MERGE_VALUES nodes. 1000 Result = Node->getOperand(Op.ResNo); 1001 break; 1002 case ISD::CopyFromReg: 1003 Tmp1 = LegalizeOp(Node->getOperand(0)); 1004 Result = Op.getValue(0); 1005 if (Node->getNumValues() == 2) { 1006 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1007 } else { 1008 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 1009 if (Node->getNumOperands() == 3) { 1010 Tmp2 = LegalizeOp(Node->getOperand(2)); 1011 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1012 } else { 1013 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1014 } 1015 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 1016 } 1017 // Since CopyFromReg produces two values, make sure to remember that we 1018 // legalized both of them. 1019 AddLegalizedOperand(Op.getValue(0), Result); 1020 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1021 return Result.getValue(Op.ResNo); 1022 case ISD::UNDEF: { 1023 MVT VT = Op.getValueType(); 1024 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 1025 default: assert(0 && "This action is not supported yet!"); 1026 case TargetLowering::Expand: 1027 if (VT.isInteger()) 1028 Result = DAG.getConstant(0, VT); 1029 else if (VT.isFloatingPoint()) 1030 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), 1031 VT); 1032 else 1033 assert(0 && "Unknown value type!"); 1034 break; 1035 case TargetLowering::Legal: 1036 break; 1037 } 1038 break; 1039 } 1040 1041 case ISD::INTRINSIC_W_CHAIN: 1042 case ISD::INTRINSIC_WO_CHAIN: 1043 case ISD::INTRINSIC_VOID: { 1044 SmallVector<SDValue, 8> Ops; 1045 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1046 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1047 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1048 1049 // Allow the target to custom lower its intrinsics if it wants to. 1050 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1051 TargetLowering::Custom) { 1052 Tmp3 = TLI.LowerOperation(Result, DAG); 1053 if (Tmp3.Val) Result = Tmp3; 1054 } 1055 1056 if (Result.Val->getNumValues() == 1) break; 1057 1058 // Must have return value and chain result. 1059 assert(Result.Val->getNumValues() == 2 && 1060 "Cannot return more than two values!"); 1061 1062 // Since loads produce two values, make sure to remember that we 1063 // legalized both of them. 1064 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1065 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1066 return Result.getValue(Op.ResNo); 1067 } 1068 1069 case ISD::DBG_STOPPOINT: 1070 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!"); 1071 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1072 1073 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) { 1074 case TargetLowering::Promote: 1075 default: assert(0 && "This action is not supported yet!"); 1076 case TargetLowering::Expand: { 1077 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1078 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1079 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other); 1080 1081 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 1082 if (MMI && (useDEBUG_LOC || useLABEL)) { 1083 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit(); 1084 unsigned SrcFile = MMI->RecordSource(CompileUnit); 1085 1086 unsigned Line = DSP->getLine(); 1087 unsigned Col = DSP->getColumn(); 1088 1089 if (useDEBUG_LOC) { 1090 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32), 1091 DAG.getConstant(Col, MVT::i32), 1092 DAG.getConstant(SrcFile, MVT::i32) }; 1093 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4); 1094 } else { 1095 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); 1096 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID); 1097 } 1098 } else { 1099 Result = Tmp1; // chain 1100 } 1101 break; 1102 } 1103 case TargetLowering::Legal: { 1104 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1105 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1106 break; 1107 1108 SmallVector<SDValue, 8> Ops; 1109 Ops.push_back(Tmp1); 1110 if (Action == Legal) { 1111 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1112 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1113 } else { 1114 // Otherwise promote them. 1115 Ops.push_back(PromoteOp(Node->getOperand(1))); 1116 Ops.push_back(PromoteOp(Node->getOperand(2))); 1117 } 1118 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1119 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1120 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1121 break; 1122 } 1123 } 1124 break; 1125 1126 case ISD::DECLARE: 1127 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1128 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1129 default: assert(0 && "This action is not supported yet!"); 1130 case TargetLowering::Legal: 1131 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1132 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1133 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1134 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1135 break; 1136 case TargetLowering::Expand: 1137 Result = LegalizeOp(Node->getOperand(0)); 1138 break; 1139 } 1140 break; 1141 1142 case ISD::DEBUG_LOC: 1143 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1144 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1145 default: assert(0 && "This action is not supported yet!"); 1146 case TargetLowering::Legal: { 1147 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1148 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1149 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1150 break; 1151 if (Action == Legal) { 1152 Tmp2 = Node->getOperand(1); 1153 Tmp3 = Node->getOperand(2); 1154 Tmp4 = Node->getOperand(3); 1155 } else { 1156 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1157 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1158 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1159 } 1160 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1161 break; 1162 } 1163 } 1164 break; 1165 1166 case ISD::DBG_LABEL: 1167 case ISD::EH_LABEL: 1168 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!"); 1169 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1170 default: assert(0 && "This action is not supported yet!"); 1171 case TargetLowering::Legal: 1172 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1173 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1174 break; 1175 case TargetLowering::Expand: 1176 Result = LegalizeOp(Node->getOperand(0)); 1177 break; 1178 } 1179 break; 1180 1181 case ISD::PREFETCH: 1182 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1183 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1184 default: assert(0 && "This action is not supported yet!"); 1185 case TargetLowering::Legal: 1186 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1187 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1188 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1189 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1190 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1191 break; 1192 case TargetLowering::Expand: 1193 // It's a noop. 1194 Result = LegalizeOp(Node->getOperand(0)); 1195 break; 1196 } 1197 break; 1198 1199 case ISD::MEMBARRIER: { 1200 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1201 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1202 default: assert(0 && "This action is not supported yet!"); 1203 case TargetLowering::Legal: { 1204 SDValue Ops[6]; 1205 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1206 for (int x = 1; x < 6; ++x) { 1207 Ops[x] = Node->getOperand(x); 1208 if (!isTypeLegal(Ops[x].getValueType())) 1209 Ops[x] = PromoteOp(Ops[x]); 1210 } 1211 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1212 break; 1213 } 1214 case TargetLowering::Expand: 1215 //There is no libgcc call for this op 1216 Result = Node->getOperand(0); // Noop 1217 break; 1218 } 1219 break; 1220 } 1221 1222 case ISD::ATOMIC_CMP_SWAP: { 1223 unsigned int num_operands = 4; 1224 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1225 SDValue Ops[4]; 1226 for (unsigned int x = 0; x < num_operands; ++x) 1227 Ops[x] = LegalizeOp(Node->getOperand(x)); 1228 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1229 1230 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1231 default: assert(0 && "This action is not supported yet!"); 1232 case TargetLowering::Custom: 1233 Result = TLI.LowerOperation(Result, DAG); 1234 break; 1235 case TargetLowering::Legal: 1236 break; 1237 } 1238 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1239 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1240 return Result.getValue(Op.ResNo); 1241 } 1242 case ISD::ATOMIC_LOAD_ADD: 1243 case ISD::ATOMIC_LOAD_SUB: 1244 case ISD::ATOMIC_LOAD_AND: 1245 case ISD::ATOMIC_LOAD_OR: 1246 case ISD::ATOMIC_LOAD_XOR: 1247 case ISD::ATOMIC_LOAD_NAND: 1248 case ISD::ATOMIC_LOAD_MIN: 1249 case ISD::ATOMIC_LOAD_MAX: 1250 case ISD::ATOMIC_LOAD_UMIN: 1251 case ISD::ATOMIC_LOAD_UMAX: 1252 case ISD::ATOMIC_SWAP: { 1253 unsigned int num_operands = 3; 1254 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1255 SDValue Ops[3]; 1256 for (unsigned int x = 0; x < num_operands; ++x) 1257 Ops[x] = LegalizeOp(Node->getOperand(x)); 1258 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1259 1260 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1261 default: assert(0 && "This action is not supported yet!"); 1262 case TargetLowering::Custom: 1263 Result = TLI.LowerOperation(Result, DAG); 1264 break; 1265 case TargetLowering::Expand: 1266 Result = SDValue(TLI.ReplaceNodeResults(Op.Val, DAG),0); 1267 break; 1268 case TargetLowering::Legal: 1269 break; 1270 } 1271 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1272 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1273 return Result.getValue(Op.ResNo); 1274 } 1275 case ISD::Constant: { 1276 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1277 unsigned opAction = 1278 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1279 1280 // We know we don't need to expand constants here, constants only have one 1281 // value and we check that it is fine above. 1282 1283 if (opAction == TargetLowering::Custom) { 1284 Tmp1 = TLI.LowerOperation(Result, DAG); 1285 if (Tmp1.Val) 1286 Result = Tmp1; 1287 } 1288 break; 1289 } 1290 case ISD::ConstantFP: { 1291 // Spill FP immediates to the constant pool if the target cannot directly 1292 // codegen them. Targets often have some immediate values that can be 1293 // efficiently generated into an FP register without a load. We explicitly 1294 // leave these constants as ConstantFP nodes for the target to deal with. 1295 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1296 1297 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1298 default: assert(0 && "This action is not supported yet!"); 1299 case TargetLowering::Legal: 1300 break; 1301 case TargetLowering::Custom: 1302 Tmp3 = TLI.LowerOperation(Result, DAG); 1303 if (Tmp3.Val) { 1304 Result = Tmp3; 1305 break; 1306 } 1307 // FALLTHROUGH 1308 case TargetLowering::Expand: { 1309 // Check to see if this FP immediate is already legal. 1310 bool isLegal = false; 1311 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1312 E = TLI.legal_fpimm_end(); I != E; ++I) { 1313 if (CFP->isExactlyValue(*I)) { 1314 isLegal = true; 1315 break; 1316 } 1317 } 1318 // If this is a legal constant, turn it into a TargetConstantFP node. 1319 if (isLegal) 1320 break; 1321 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1322 } 1323 } 1324 break; 1325 } 1326 case ISD::TokenFactor: 1327 if (Node->getNumOperands() == 2) { 1328 Tmp1 = LegalizeOp(Node->getOperand(0)); 1329 Tmp2 = LegalizeOp(Node->getOperand(1)); 1330 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1331 } else if (Node->getNumOperands() == 3) { 1332 Tmp1 = LegalizeOp(Node->getOperand(0)); 1333 Tmp2 = LegalizeOp(Node->getOperand(1)); 1334 Tmp3 = LegalizeOp(Node->getOperand(2)); 1335 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1336 } else { 1337 SmallVector<SDValue, 8> Ops; 1338 // Legalize the operands. 1339 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1340 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1341 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1342 } 1343 break; 1344 1345 case ISD::FORMAL_ARGUMENTS: 1346 case ISD::CALL: 1347 // The only option for this is to custom lower it. 1348 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1349 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1350 // A call within a calling sequence must be legalized to something 1351 // other than the normal CALLSEQ_END. Violating this gets Legalize 1352 // into an infinite loop. 1353 assert ((!IsLegalizingCall || 1354 Node->getOpcode() != ISD::CALL || 1355 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) && 1356 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1357 1358 // The number of incoming and outgoing values should match; unless the final 1359 // outgoing value is a flag. 1360 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || 1361 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && 1362 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == 1363 MVT::Flag)) && 1364 "Lowering call/formal_arguments produced unexpected # results!"); 1365 1366 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1367 // remember that we legalized all of them, so it doesn't get relegalized. 1368 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1369 if (Tmp3.Val->getValueType(i) == MVT::Flag) 1370 continue; 1371 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1372 if (Op.ResNo == i) 1373 Tmp2 = Tmp1; 1374 AddLegalizedOperand(SDValue(Node, i), Tmp1); 1375 } 1376 return Tmp2; 1377 case ISD::EXTRACT_SUBREG: { 1378 Tmp1 = LegalizeOp(Node->getOperand(0)); 1379 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1380 assert(idx && "Operand must be a constant"); 1381 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1382 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1383 } 1384 break; 1385 case ISD::INSERT_SUBREG: { 1386 Tmp1 = LegalizeOp(Node->getOperand(0)); 1387 Tmp2 = LegalizeOp(Node->getOperand(1)); 1388 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1389 assert(idx && "Operand must be a constant"); 1390 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1391 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1392 } 1393 break; 1394 case ISD::BUILD_VECTOR: 1395 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1396 default: assert(0 && "This action is not supported yet!"); 1397 case TargetLowering::Custom: 1398 Tmp3 = TLI.LowerOperation(Result, DAG); 1399 if (Tmp3.Val) { 1400 Result = Tmp3; 1401 break; 1402 } 1403 // FALLTHROUGH 1404 case TargetLowering::Expand: 1405 Result = ExpandBUILD_VECTOR(Result.Val); 1406 break; 1407 } 1408 break; 1409 case ISD::INSERT_VECTOR_ELT: 1410 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1411 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1412 1413 // The type of the value to insert may not be legal, even though the vector 1414 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1415 // here. 1416 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1417 default: assert(0 && "Cannot expand insert element operand"); 1418 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1419 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1420 } 1421 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1422 1423 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1424 Node->getValueType(0))) { 1425 default: assert(0 && "This action is not supported yet!"); 1426 case TargetLowering::Legal: 1427 break; 1428 case TargetLowering::Custom: 1429 Tmp4 = TLI.LowerOperation(Result, DAG); 1430 if (Tmp4.Val) { 1431 Result = Tmp4; 1432 break; 1433 } 1434 // FALLTHROUGH 1435 case TargetLowering::Expand: { 1436 // If the insert index is a constant, codegen this as a scalar_to_vector, 1437 // then a shuffle that inserts it into the right position in the vector. 1438 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1439 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1440 // match the element type of the vector being created. 1441 if (Tmp2.getValueType() == 1442 Op.getValueType().getVectorElementType()) { 1443 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1444 Tmp1.getValueType(), Tmp2); 1445 1446 unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); 1447 MVT ShufMaskVT = 1448 MVT::getIntVectorWithNumElements(NumElts); 1449 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType(); 1450 1451 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1452 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1453 // elt 0 of the RHS. 1454 SmallVector<SDValue, 8> ShufOps; 1455 for (unsigned i = 0; i != NumElts; ++i) { 1456 if (i != InsertPos->getValue()) 1457 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1458 else 1459 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1460 } 1461 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1462 &ShufOps[0], ShufOps.size()); 1463 1464 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1465 Tmp1, ScVec, ShufMask); 1466 Result = LegalizeOp(Result); 1467 break; 1468 } 1469 } 1470 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3); 1471 break; 1472 } 1473 } 1474 break; 1475 case ISD::SCALAR_TO_VECTOR: 1476 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1477 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1478 break; 1479 } 1480 1481 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1482 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1483 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1484 Node->getValueType(0))) { 1485 default: assert(0 && "This action is not supported yet!"); 1486 case TargetLowering::Legal: 1487 break; 1488 case TargetLowering::Custom: 1489 Tmp3 = TLI.LowerOperation(Result, DAG); 1490 if (Tmp3.Val) { 1491 Result = Tmp3; 1492 break; 1493 } 1494 // FALLTHROUGH 1495 case TargetLowering::Expand: 1496 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1497 break; 1498 } 1499 break; 1500 case ISD::VECTOR_SHUFFLE: 1501 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1502 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1503 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1504 1505 // Allow targets to custom lower the SHUFFLEs they support. 1506 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1507 default: assert(0 && "Unknown operation action!"); 1508 case TargetLowering::Legal: 1509 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1510 "vector shuffle should not be created if not legal!"); 1511 break; 1512 case TargetLowering::Custom: 1513 Tmp3 = TLI.LowerOperation(Result, DAG); 1514 if (Tmp3.Val) { 1515 Result = Tmp3; 1516 break; 1517 } 1518 // FALLTHROUGH 1519 case TargetLowering::Expand: { 1520 MVT VT = Node->getValueType(0); 1521 MVT EltVT = VT.getVectorElementType(); 1522 MVT PtrVT = TLI.getPointerTy(); 1523 SDValue Mask = Node->getOperand(2); 1524 unsigned NumElems = Mask.getNumOperands(); 1525 SmallVector<SDValue,8> Ops; 1526 for (unsigned i = 0; i != NumElems; ++i) { 1527 SDValue Arg = Mask.getOperand(i); 1528 if (Arg.getOpcode() == ISD::UNDEF) { 1529 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1530 } else { 1531 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1532 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1533 if (Idx < NumElems) 1534 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1535 DAG.getConstant(Idx, PtrVT))); 1536 else 1537 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1538 DAG.getConstant(Idx - NumElems, PtrVT))); 1539 } 1540 } 1541 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1542 break; 1543 } 1544 case TargetLowering::Promote: { 1545 // Change base type to a different vector type. 1546 MVT OVT = Node->getValueType(0); 1547 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1548 1549 // Cast the two input vectors. 1550 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1551 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1552 1553 // Convert the shuffle mask to the right # elements. 1554 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1555 assert(Tmp3.Val && "Shuffle not legal?"); 1556 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1557 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1558 break; 1559 } 1560 } 1561 break; 1562 1563 case ISD::EXTRACT_VECTOR_ELT: 1564 Tmp1 = Node->getOperand(0); 1565 Tmp2 = LegalizeOp(Node->getOperand(1)); 1566 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1567 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1568 break; 1569 1570 case ISD::EXTRACT_SUBVECTOR: 1571 Tmp1 = Node->getOperand(0); 1572 Tmp2 = LegalizeOp(Node->getOperand(1)); 1573 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1574 Result = ExpandEXTRACT_SUBVECTOR(Result); 1575 break; 1576 1577 case ISD::CALLSEQ_START: { 1578 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1579 1580 // Recursively Legalize all of the inputs of the call end that do not lead 1581 // to this call start. This ensures that any libcalls that need be inserted 1582 // are inserted *before* the CALLSEQ_START. 1583 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1584 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1585 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1586 NodesLeadingTo); 1587 } 1588 1589 // Now that we legalized all of the inputs (which may have inserted 1590 // libcalls) create the new CALLSEQ_START node. 1591 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1592 1593 // Merge in the last call, to ensure that this call start after the last 1594 // call ended. 1595 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1596 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1597 Tmp1 = LegalizeOp(Tmp1); 1598 } 1599 1600 // Do not try to legalize the target-specific arguments (#1+). 1601 if (Tmp1 != Node->getOperand(0)) { 1602 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1603 Ops[0] = Tmp1; 1604 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1605 } 1606 1607 // Remember that the CALLSEQ_START is legalized. 1608 AddLegalizedOperand(Op.getValue(0), Result); 1609 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1610 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1611 1612 // Now that the callseq_start and all of the non-call nodes above this call 1613 // sequence have been legalized, legalize the call itself. During this 1614 // process, no libcalls can/will be inserted, guaranteeing that no calls 1615 // can overlap. 1616 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1617 // Note that we are selecting this call! 1618 LastCALLSEQ_END = SDValue(CallEnd, 0); 1619 IsLegalizingCall = true; 1620 1621 // Legalize the call, starting from the CALLSEQ_END. 1622 LegalizeOp(LastCALLSEQ_END); 1623 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1624 return Result; 1625 } 1626 case ISD::CALLSEQ_END: 1627 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1628 // will cause this node to be legalized as well as handling libcalls right. 1629 if (LastCALLSEQ_END.Val != Node) { 1630 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1631 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1632 assert(I != LegalizedNodes.end() && 1633 "Legalizing the call start should have legalized this node!"); 1634 return I->second; 1635 } 1636 1637 // Otherwise, the call start has been legalized and everything is going 1638 // according to plan. Just legalize ourselves normally here. 1639 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1640 // Do not try to legalize the target-specific arguments (#1+), except for 1641 // an optional flag input. 1642 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1643 if (Tmp1 != Node->getOperand(0)) { 1644 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1645 Ops[0] = Tmp1; 1646 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1647 } 1648 } else { 1649 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1650 if (Tmp1 != Node->getOperand(0) || 1651 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1652 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1653 Ops[0] = Tmp1; 1654 Ops.back() = Tmp2; 1655 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1656 } 1657 } 1658 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1659 // This finishes up call legalization. 1660 IsLegalizingCall = false; 1661 1662 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1663 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1664 if (Node->getNumValues() == 2) 1665 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1666 return Result.getValue(Op.ResNo); 1667 case ISD::DYNAMIC_STACKALLOC: { 1668 MVT VT = Node->getValueType(0); 1669 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1670 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1671 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1672 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1673 1674 Tmp1 = Result.getValue(0); 1675 Tmp2 = Result.getValue(1); 1676 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1677 default: assert(0 && "This action is not supported yet!"); 1678 case TargetLowering::Expand: { 1679 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1680 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1681 " not tell us which reg is the stack pointer!"); 1682 SDValue Chain = Tmp1.getOperand(0); 1683 1684 // Chain the dynamic stack allocation so that it doesn't modify the stack 1685 // pointer when other instructions are using the stack. 1686 Chain = DAG.getCALLSEQ_START(Chain, 1687 DAG.getConstant(0, TLI.getPointerTy())); 1688 1689 SDValue Size = Tmp2.getOperand(1); 1690 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1691 Chain = SP.getValue(1); 1692 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1693 unsigned StackAlign = 1694 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1695 if (Align > StackAlign) 1696 SP = DAG.getNode(ISD::AND, VT, SP, 1697 DAG.getConstant(-(uint64_t)Align, VT)); 1698 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1699 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1700 1701 Tmp2 = 1702 DAG.getCALLSEQ_END(Chain, 1703 DAG.getConstant(0, TLI.getPointerTy()), 1704 DAG.getConstant(0, TLI.getPointerTy()), 1705 SDValue()); 1706 1707 Tmp1 = LegalizeOp(Tmp1); 1708 Tmp2 = LegalizeOp(Tmp2); 1709 break; 1710 } 1711 case TargetLowering::Custom: 1712 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1713 if (Tmp3.Val) { 1714 Tmp1 = LegalizeOp(Tmp3); 1715 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1716 } 1717 break; 1718 case TargetLowering::Legal: 1719 break; 1720 } 1721 // Since this op produce two values, make sure to remember that we 1722 // legalized both of them. 1723 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1724 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1725 return Op.ResNo ? Tmp2 : Tmp1; 1726 } 1727 case ISD::INLINEASM: { 1728 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1729 bool Changed = false; 1730 // Legalize all of the operands of the inline asm, in case they are nodes 1731 // that need to be expanded or something. Note we skip the asm string and 1732 // all of the TargetConstant flags. 1733 SDValue Op = LegalizeOp(Ops[0]); 1734 Changed = Op != Ops[0]; 1735 Ops[0] = Op; 1736 1737 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1738 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1739 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1740 for (++i; NumVals; ++i, --NumVals) { 1741 SDValue Op = LegalizeOp(Ops[i]); 1742 if (Op != Ops[i]) { 1743 Changed = true; 1744 Ops[i] = Op; 1745 } 1746 } 1747 } 1748 1749 if (HasInFlag) { 1750 Op = LegalizeOp(Ops.back()); 1751 Changed |= Op != Ops.back(); 1752 Ops.back() = Op; 1753 } 1754 1755 if (Changed) 1756 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1757 1758 // INLINE asm returns a chain and flag, make sure to add both to the map. 1759 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1760 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1761 return Result.getValue(Op.ResNo); 1762 } 1763 case ISD::BR: 1764 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1765 // Ensure that libcalls are emitted before a branch. 1766 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1767 Tmp1 = LegalizeOp(Tmp1); 1768 LastCALLSEQ_END = DAG.getEntryNode(); 1769 1770 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1771 break; 1772 case ISD::BRIND: 1773 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1774 // Ensure that libcalls are emitted before a branch. 1775 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1776 Tmp1 = LegalizeOp(Tmp1); 1777 LastCALLSEQ_END = DAG.getEntryNode(); 1778 1779 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1780 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1781 case Legal: 1782 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1783 break; 1784 } 1785 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1786 break; 1787 case ISD::BR_JT: 1788 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1789 // Ensure that libcalls are emitted before a branch. 1790 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1791 Tmp1 = LegalizeOp(Tmp1); 1792 LastCALLSEQ_END = DAG.getEntryNode(); 1793 1794 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1795 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1796 1797 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1798 default: assert(0 && "This action is not supported yet!"); 1799 case TargetLowering::Legal: break; 1800 case TargetLowering::Custom: 1801 Tmp1 = TLI.LowerOperation(Result, DAG); 1802 if (Tmp1.Val) Result = Tmp1; 1803 break; 1804 case TargetLowering::Expand: { 1805 SDValue Chain = Result.getOperand(0); 1806 SDValue Table = Result.getOperand(1); 1807 SDValue Index = Result.getOperand(2); 1808 1809 MVT PTy = TLI.getPointerTy(); 1810 MachineFunction &MF = DAG.getMachineFunction(); 1811 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1812 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1813 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1814 1815 SDValue LD; 1816 switch (EntrySize) { 1817 default: assert(0 && "Size of jump table not supported yet."); break; 1818 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, 1819 PseudoSourceValue::getJumpTable(), 0); break; 1820 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, 1821 PseudoSourceValue::getJumpTable(), 0); break; 1822 } 1823 1824 Addr = LD; 1825 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1826 // For PIC, the sequence is: 1827 // BRIND(load(Jumptable + index) + RelocBase) 1828 // RelocBase can be JumpTable, GOT or some sort of global base. 1829 if (PTy != MVT::i32) 1830 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1831 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1832 TLI.getPICJumpTableRelocBase(Table, DAG)); 1833 } 1834 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1835 } 1836 } 1837 break; 1838 case ISD::BRCOND: 1839 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1840 // Ensure that libcalls are emitted before a return. 1841 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1842 Tmp1 = LegalizeOp(Tmp1); 1843 LastCALLSEQ_END = DAG.getEntryNode(); 1844 1845 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1846 case Expand: assert(0 && "It's impossible to expand bools"); 1847 case Legal: 1848 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1849 break; 1850 case Promote: { 1851 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1852 1853 // The top bits of the promoted condition are not necessarily zero, ensure 1854 // that the value is properly zero extended. 1855 unsigned BitWidth = Tmp2.getValueSizeInBits(); 1856 if (!DAG.MaskedValueIsZero(Tmp2, 1857 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 1858 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1859 break; 1860 } 1861 } 1862 1863 // Basic block destination (Op#2) is always legal. 1864 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1865 1866 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1867 default: assert(0 && "This action is not supported yet!"); 1868 case TargetLowering::Legal: break; 1869 case TargetLowering::Custom: 1870 Tmp1 = TLI.LowerOperation(Result, DAG); 1871 if (Tmp1.Val) Result = Tmp1; 1872 break; 1873 case TargetLowering::Expand: 1874 // Expand brcond's setcc into its constituent parts and create a BR_CC 1875 // Node. 1876 if (Tmp2.getOpcode() == ISD::SETCC) { 1877 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1878 Tmp2.getOperand(0), Tmp2.getOperand(1), 1879 Node->getOperand(2)); 1880 } else { 1881 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1882 DAG.getCondCode(ISD::SETNE), Tmp2, 1883 DAG.getConstant(0, Tmp2.getValueType()), 1884 Node->getOperand(2)); 1885 } 1886 break; 1887 } 1888 break; 1889 case ISD::BR_CC: 1890 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1891 // Ensure that libcalls are emitted before a branch. 1892 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1893 Tmp1 = LegalizeOp(Tmp1); 1894 Tmp2 = Node->getOperand(2); // LHS 1895 Tmp3 = Node->getOperand(3); // RHS 1896 Tmp4 = Node->getOperand(1); // CC 1897 1898 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1899 LastCALLSEQ_END = DAG.getEntryNode(); 1900 1901 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1902 // the LHS is a legal SETCC itself. In this case, we need to compare 1903 // the result against zero to select between true and false values. 1904 if (Tmp3.Val == 0) { 1905 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1906 Tmp4 = DAG.getCondCode(ISD::SETNE); 1907 } 1908 1909 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1910 Node->getOperand(4)); 1911 1912 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1913 default: assert(0 && "Unexpected action for BR_CC!"); 1914 case TargetLowering::Legal: break; 1915 case TargetLowering::Custom: 1916 Tmp4 = TLI.LowerOperation(Result, DAG); 1917 if (Tmp4.Val) Result = Tmp4; 1918 break; 1919 } 1920 break; 1921 case ISD::LOAD: { 1922 LoadSDNode *LD = cast<LoadSDNode>(Node); 1923 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1924 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1925 1926 ISD::LoadExtType ExtType = LD->getExtensionType(); 1927 if (ExtType == ISD::NON_EXTLOAD) { 1928 MVT VT = Node->getValueType(0); 1929 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1930 Tmp3 = Result.getValue(0); 1931 Tmp4 = Result.getValue(1); 1932 1933 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1934 default: assert(0 && "This action is not supported yet!"); 1935 case TargetLowering::Legal: 1936 // If this is an unaligned load and the target doesn't support it, 1937 // expand it. 1938 if (!TLI.allowsUnalignedMemoryAccesses()) { 1939 unsigned ABIAlignment = TLI.getTargetData()-> 1940 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 1941 if (LD->getAlignment() < ABIAlignment){ 1942 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1943 TLI); 1944 Tmp3 = Result.getOperand(0); 1945 Tmp4 = Result.getOperand(1); 1946 Tmp3 = LegalizeOp(Tmp3); 1947 Tmp4 = LegalizeOp(Tmp4); 1948 } 1949 } 1950 break; 1951 case TargetLowering::Custom: 1952 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1953 if (Tmp1.Val) { 1954 Tmp3 = LegalizeOp(Tmp1); 1955 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1956 } 1957 break; 1958 case TargetLowering::Promote: { 1959 // Only promote a load of vector type to another. 1960 assert(VT.isVector() && "Cannot promote this load!"); 1961 // Change base type to a different vector type. 1962 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1963 1964 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1965 LD->getSrcValueOffset(), 1966 LD->isVolatile(), LD->getAlignment()); 1967 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1968 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1969 break; 1970 } 1971 } 1972 // Since loads produce two values, make sure to remember that we 1973 // legalized both of them. 1974 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1975 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1976 return Op.ResNo ? Tmp4 : Tmp3; 1977 } else { 1978 MVT SrcVT = LD->getMemoryVT(); 1979 unsigned SrcWidth = SrcVT.getSizeInBits(); 1980 int SVOffset = LD->getSrcValueOffset(); 1981 unsigned Alignment = LD->getAlignment(); 1982 bool isVolatile = LD->isVolatile(); 1983 1984 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1985 // Some targets pretend to have an i1 loading operation, and actually 1986 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1987 // bits are guaranteed to be zero; it helps the optimizers understand 1988 // that these bits are zero. It is also useful for EXTLOAD, since it 1989 // tells the optimizers that those bits are undefined. It would be 1990 // nice to have an effective generic way of getting these benefits... 1991 // Until such a way is found, don't insist on promoting i1 here. 1992 (SrcVT != MVT::i1 || 1993 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1994 // Promote to a byte-sized load if not loading an integral number of 1995 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1996 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1997 MVT NVT = MVT::getIntegerVT(NewWidth); 1998 SDValue Ch; 1999 2000 // The extra bits are guaranteed to be zero, since we stored them that 2001 // way. A zext load from NVT thus automatically gives zext from SrcVT. 2002 2003 ISD::LoadExtType NewExtType = 2004 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 2005 2006 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), 2007 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 2008 NVT, isVolatile, Alignment); 2009 2010 Ch = Result.getValue(1); // The chain. 2011 2012 if (ExtType == ISD::SEXTLOAD) 2013 // Having the top bits zero doesn't help when sign extending. 2014 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2015 Result, DAG.getValueType(SrcVT)); 2016 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 2017 // All the top bits are guaranteed to be zero - inform the optimizers. 2018 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, 2019 DAG.getValueType(SrcVT)); 2020 2021 Tmp1 = LegalizeOp(Result); 2022 Tmp2 = LegalizeOp(Ch); 2023 } else if (SrcWidth & (SrcWidth - 1)) { 2024 // If not loading a power-of-2 number of bits, expand as two loads. 2025 assert(SrcVT.isExtended() && !SrcVT.isVector() && 2026 "Unsupported extload!"); 2027 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 2028 assert(RoundWidth < SrcWidth); 2029 unsigned ExtraWidth = SrcWidth - RoundWidth; 2030 assert(ExtraWidth < RoundWidth); 2031 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2032 "Load size not an integral number of bytes!"); 2033 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2034 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2035 SDValue Lo, Hi, Ch; 2036 unsigned IncrementSize; 2037 2038 if (TLI.isLittleEndian()) { 2039 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2040 // Load the bottom RoundWidth bits. 2041 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2042 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2043 Alignment); 2044 2045 // Load the remaining ExtraWidth bits. 2046 IncrementSize = RoundWidth / 8; 2047 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2048 DAG.getIntPtrConstant(IncrementSize)); 2049 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2050 LD->getSrcValue(), SVOffset + IncrementSize, 2051 ExtraVT, isVolatile, 2052 MinAlign(Alignment, IncrementSize)); 2053 2054 // Build a factor node to remember that this load is independent of the 2055 // other one. 2056 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2057 Hi.getValue(1)); 2058 2059 // Move the top bits to the right place. 2060 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2061 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2062 2063 // Join the hi and lo parts. 2064 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2065 } else { 2066 // Big endian - avoid unaligned loads. 2067 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2068 // Load the top RoundWidth bits. 2069 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2070 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2071 Alignment); 2072 2073 // Load the remaining ExtraWidth bits. 2074 IncrementSize = RoundWidth / 8; 2075 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2076 DAG.getIntPtrConstant(IncrementSize)); 2077 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2078 LD->getSrcValue(), SVOffset + IncrementSize, 2079 ExtraVT, isVolatile, 2080 MinAlign(Alignment, IncrementSize)); 2081 2082 // Build a factor node to remember that this load is independent of the 2083 // other one. 2084 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2085 Hi.getValue(1)); 2086 2087 // Move the top bits to the right place. 2088 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2089 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2090 2091 // Join the hi and lo parts. 2092 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2093 } 2094 2095 Tmp1 = LegalizeOp(Result); 2096 Tmp2 = LegalizeOp(Ch); 2097 } else { 2098 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 2099 default: assert(0 && "This action is not supported yet!"); 2100 case TargetLowering::Custom: 2101 isCustom = true; 2102 // FALLTHROUGH 2103 case TargetLowering::Legal: 2104 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2105 Tmp1 = Result.getValue(0); 2106 Tmp2 = Result.getValue(1); 2107 2108 if (isCustom) { 2109 Tmp3 = TLI.LowerOperation(Result, DAG); 2110 if (Tmp3.Val) { 2111 Tmp1 = LegalizeOp(Tmp3); 2112 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2113 } 2114 } else { 2115 // If this is an unaligned load and the target doesn't support it, 2116 // expand it. 2117 if (!TLI.allowsUnalignedMemoryAccesses()) { 2118 unsigned ABIAlignment = TLI.getTargetData()-> 2119 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2120 if (LD->getAlignment() < ABIAlignment){ 2121 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 2122 TLI); 2123 Tmp1 = Result.getOperand(0); 2124 Tmp2 = Result.getOperand(1); 2125 Tmp1 = LegalizeOp(Tmp1); 2126 Tmp2 = LegalizeOp(Tmp2); 2127 } 2128 } 2129 } 2130 break; 2131 case TargetLowering::Expand: 2132 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2133 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2134 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 2135 LD->getSrcValueOffset(), 2136 LD->isVolatile(), LD->getAlignment()); 2137 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 2138 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2139 Tmp2 = LegalizeOp(Load.getValue(1)); 2140 break; 2141 } 2142 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2143 // Turn the unsupported load into an EXTLOAD followed by an explicit 2144 // zero/sign extend inreg. 2145 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2146 Tmp1, Tmp2, LD->getSrcValue(), 2147 LD->getSrcValueOffset(), SrcVT, 2148 LD->isVolatile(), LD->getAlignment()); 2149 SDValue ValRes; 2150 if (ExtType == ISD::SEXTLOAD) 2151 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2152 Result, DAG.getValueType(SrcVT)); 2153 else 2154 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 2155 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2156 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2157 break; 2158 } 2159 } 2160 2161 // Since loads produce two values, make sure to remember that we legalized 2162 // both of them. 2163 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2164 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2165 return Op.ResNo ? Tmp2 : Tmp1; 2166 } 2167 } 2168 case ISD::EXTRACT_ELEMENT: { 2169 MVT OpTy = Node->getOperand(0).getValueType(); 2170 switch (getTypeAction(OpTy)) { 2171 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2172 case Legal: 2173 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 2174 // 1 -> Hi 2175 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 2176 DAG.getConstant(OpTy.getSizeInBits()/2, 2177 TLI.getShiftAmountTy())); 2178 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 2179 } else { 2180 // 0 -> Lo 2181 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 2182 Node->getOperand(0)); 2183 } 2184 break; 2185 case Expand: 2186 // Get both the low and high parts. 2187 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2188 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 2189 Result = Tmp2; // 1 -> Hi 2190 else 2191 Result = Tmp1; // 0 -> Lo 2192 break; 2193 } 2194 break; 2195 } 2196 2197 case ISD::CopyToReg: 2198 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2199 2200 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2201 "Register type must be legal!"); 2202 // Legalize the incoming value (must be a legal type). 2203 Tmp2 = LegalizeOp(Node->getOperand(2)); 2204 if (Node->getNumValues() == 1) { 2205 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2206 } else { 2207 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2208 if (Node->getNumOperands() == 4) { 2209 Tmp3 = LegalizeOp(Node->getOperand(3)); 2210 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2211 Tmp3); 2212 } else { 2213 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2214 } 2215 2216 // Since this produces two values, make sure to remember that we legalized 2217 // both of them. 2218 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 2219 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 2220 return Result; 2221 } 2222 break; 2223 2224 case ISD::RET: 2225 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2226 2227 // Ensure that libcalls are emitted before a return. 2228 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2229 Tmp1 = LegalizeOp(Tmp1); 2230 LastCALLSEQ_END = DAG.getEntryNode(); 2231 2232 switch (Node->getNumOperands()) { 2233 case 3: // ret val 2234 Tmp2 = Node->getOperand(1); 2235 Tmp3 = Node->getOperand(2); // Signness 2236 switch (getTypeAction(Tmp2.getValueType())) { 2237 case Legal: 2238 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2239 break; 2240 case Expand: 2241 if (!Tmp2.getValueType().isVector()) { 2242 SDValue Lo, Hi; 2243 ExpandOp(Tmp2, Lo, Hi); 2244 2245 // Big endian systems want the hi reg first. 2246 if (TLI.isBigEndian()) 2247 std::swap(Lo, Hi); 2248 2249 if (Hi.Val) 2250 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2251 else 2252 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 2253 Result = LegalizeOp(Result); 2254 } else { 2255 SDNode *InVal = Tmp2.Val; 2256 int InIx = Tmp2.ResNo; 2257 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 2258 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 2259 2260 // Figure out if there is a simple type corresponding to this Vector 2261 // type. If so, convert to the vector type. 2262 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2263 if (TLI.isTypeLegal(TVT)) { 2264 // Turn this into a return of the vector type. 2265 Tmp2 = LegalizeOp(Tmp2); 2266 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2267 } else if (NumElems == 1) { 2268 // Turn this into a return of the scalar type. 2269 Tmp2 = ScalarizeVectorOp(Tmp2); 2270 Tmp2 = LegalizeOp(Tmp2); 2271 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2272 2273 // FIXME: Returns of gcc generic vectors smaller than a legal type 2274 // should be returned in integer registers! 2275 2276 // The scalarized value type may not be legal, e.g. it might require 2277 // promotion or expansion. Relegalize the return. 2278 Result = LegalizeOp(Result); 2279 } else { 2280 // FIXME: Returns of gcc generic vectors larger than a legal vector 2281 // type should be returned by reference! 2282 SDValue Lo, Hi; 2283 SplitVectorOp(Tmp2, Lo, Hi); 2284 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2285 Result = LegalizeOp(Result); 2286 } 2287 } 2288 break; 2289 case Promote: 2290 Tmp2 = PromoteOp(Node->getOperand(1)); 2291 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2292 Result = LegalizeOp(Result); 2293 break; 2294 } 2295 break; 2296 case 1: // ret void 2297 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2298 break; 2299 default: { // ret <values> 2300 SmallVector<SDValue, 8> NewValues; 2301 NewValues.push_back(Tmp1); 2302 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2303 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2304 case Legal: 2305 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2306 NewValues.push_back(Node->getOperand(i+1)); 2307 break; 2308 case Expand: { 2309 SDValue Lo, Hi; 2310 assert(!Node->getOperand(i).getValueType().isExtended() && 2311 "FIXME: TODO: implement returning non-legal vector types!"); 2312 ExpandOp(Node->getOperand(i), Lo, Hi); 2313 NewValues.push_back(Lo); 2314 NewValues.push_back(Node->getOperand(i+1)); 2315 if (Hi.Val) { 2316 NewValues.push_back(Hi); 2317 NewValues.push_back(Node->getOperand(i+1)); 2318 } 2319 break; 2320 } 2321 case Promote: 2322 assert(0 && "Can't promote multiple return value yet!"); 2323 } 2324 2325 if (NewValues.size() == Node->getNumOperands()) 2326 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2327 else 2328 Result = DAG.getNode(ISD::RET, MVT::Other, 2329 &NewValues[0], NewValues.size()); 2330 break; 2331 } 2332 } 2333 2334 if (Result.getOpcode() == ISD::RET) { 2335 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2336 default: assert(0 && "This action is not supported yet!"); 2337 case TargetLowering::Legal: break; 2338 case TargetLowering::Custom: 2339 Tmp1 = TLI.LowerOperation(Result, DAG); 2340 if (Tmp1.Val) Result = Tmp1; 2341 break; 2342 } 2343 } 2344 break; 2345 case ISD::STORE: { 2346 StoreSDNode *ST = cast<StoreSDNode>(Node); 2347 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2348 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2349 int SVOffset = ST->getSrcValueOffset(); 2350 unsigned Alignment = ST->getAlignment(); 2351 bool isVolatile = ST->isVolatile(); 2352 2353 if (!ST->isTruncatingStore()) { 2354 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2355 // FIXME: We shouldn't do this for TargetConstantFP's. 2356 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2357 // to phase ordering between legalized code and the dag combiner. This 2358 // probably means that we need to integrate dag combiner and legalizer 2359 // together. 2360 // We generally can't do this one for long doubles. 2361 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2362 if (CFP->getValueType(0) == MVT::f32 && 2363 getTypeAction(MVT::i32) == Legal) { 2364 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2365 convertToAPInt().zextOrTrunc(32), 2366 MVT::i32); 2367 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2368 SVOffset, isVolatile, Alignment); 2369 break; 2370 } else if (CFP->getValueType(0) == MVT::f64) { 2371 // If this target supports 64-bit registers, do a single 64-bit store. 2372 if (getTypeAction(MVT::i64) == Legal) { 2373 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2374 zextOrTrunc(64), MVT::i64); 2375 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2376 SVOffset, isVolatile, Alignment); 2377 break; 2378 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 2379 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2380 // stores. If the target supports neither 32- nor 64-bits, this 2381 // xform is certainly not worth it. 2382 const APInt &IntVal =CFP->getValueAPF().convertToAPInt(); 2383 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2384 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2385 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2386 2387 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2388 SVOffset, isVolatile, Alignment); 2389 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2390 DAG.getIntPtrConstant(4)); 2391 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2392 isVolatile, MinAlign(Alignment, 4U)); 2393 2394 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2395 break; 2396 } 2397 } 2398 } 2399 2400 switch (getTypeAction(ST->getMemoryVT())) { 2401 case Legal: { 2402 Tmp3 = LegalizeOp(ST->getValue()); 2403 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2404 ST->getOffset()); 2405 2406 MVT VT = Tmp3.getValueType(); 2407 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2408 default: assert(0 && "This action is not supported yet!"); 2409 case TargetLowering::Legal: 2410 // If this is an unaligned store and the target doesn't support it, 2411 // expand it. 2412 if (!TLI.allowsUnalignedMemoryAccesses()) { 2413 unsigned ABIAlignment = TLI.getTargetData()-> 2414 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2415 if (ST->getAlignment() < ABIAlignment) 2416 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2417 TLI); 2418 } 2419 break; 2420 case TargetLowering::Custom: 2421 Tmp1 = TLI.LowerOperation(Result, DAG); 2422 if (Tmp1.Val) Result = Tmp1; 2423 break; 2424 case TargetLowering::Promote: 2425 assert(VT.isVector() && "Unknown legal promote case!"); 2426 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2427 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2428 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2429 ST->getSrcValue(), SVOffset, isVolatile, 2430 Alignment); 2431 break; 2432 } 2433 break; 2434 } 2435 case Promote: 2436 // Truncate the value and store the result. 2437 Tmp3 = PromoteOp(ST->getValue()); 2438 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2439 SVOffset, ST->getMemoryVT(), 2440 isVolatile, Alignment); 2441 break; 2442 2443 case Expand: 2444 unsigned IncrementSize = 0; 2445 SDValue Lo, Hi; 2446 2447 // If this is a vector type, then we have to calculate the increment as 2448 // the product of the element size in bytes, and the number of elements 2449 // in the high half of the vector. 2450 if (ST->getValue().getValueType().isVector()) { 2451 SDNode *InVal = ST->getValue().Val; 2452 int InIx = ST->getValue().ResNo; 2453 MVT InVT = InVal->getValueType(InIx); 2454 unsigned NumElems = InVT.getVectorNumElements(); 2455 MVT EVT = InVT.getVectorElementType(); 2456 2457 // Figure out if there is a simple type corresponding to this Vector 2458 // type. If so, convert to the vector type. 2459 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2460 if (TLI.isTypeLegal(TVT)) { 2461 // Turn this into a normal store of the vector type. 2462 Tmp3 = LegalizeOp(ST->getValue()); 2463 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2464 SVOffset, isVolatile, Alignment); 2465 Result = LegalizeOp(Result); 2466 break; 2467 } else if (NumElems == 1) { 2468 // Turn this into a normal store of the scalar type. 2469 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2470 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2471 SVOffset, isVolatile, Alignment); 2472 // The scalarized value type may not be legal, e.g. it might require 2473 // promotion or expansion. Relegalize the scalar store. 2474 Result = LegalizeOp(Result); 2475 break; 2476 } else { 2477 SplitVectorOp(ST->getValue(), Lo, Hi); 2478 IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() * 2479 EVT.getSizeInBits()/8; 2480 } 2481 } else { 2482 ExpandOp(ST->getValue(), Lo, Hi); 2483 IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0; 2484 2485 if (TLI.isBigEndian()) 2486 std::swap(Lo, Hi); 2487 } 2488 2489 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2490 SVOffset, isVolatile, Alignment); 2491 2492 if (Hi.Val == NULL) { 2493 // Must be int <-> float one-to-one expansion. 2494 Result = Lo; 2495 break; 2496 } 2497 2498 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2499 DAG.getIntPtrConstant(IncrementSize)); 2500 assert(isTypeLegal(Tmp2.getValueType()) && 2501 "Pointers must be legal!"); 2502 SVOffset += IncrementSize; 2503 Alignment = MinAlign(Alignment, IncrementSize); 2504 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2505 SVOffset, isVolatile, Alignment); 2506 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2507 break; 2508 } 2509 } else { 2510 switch (getTypeAction(ST->getValue().getValueType())) { 2511 case Legal: 2512 Tmp3 = LegalizeOp(ST->getValue()); 2513 break; 2514 case Promote: 2515 // We can promote the value, the truncstore will still take care of it. 2516 Tmp3 = PromoteOp(ST->getValue()); 2517 break; 2518 case Expand: 2519 // Just store the low part. This may become a non-trunc store, so make 2520 // sure to use getTruncStore, not UpdateNodeOperands below. 2521 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2522 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2523 SVOffset, MVT::i8, isVolatile, Alignment); 2524 } 2525 2526 MVT StVT = ST->getMemoryVT(); 2527 unsigned StWidth = StVT.getSizeInBits(); 2528 2529 if (StWidth != StVT.getStoreSizeInBits()) { 2530 // Promote to a byte-sized store with upper bits zero if not 2531 // storing an integral number of bytes. For example, promote 2532 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2533 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 2534 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); 2535 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2536 SVOffset, NVT, isVolatile, Alignment); 2537 } else if (StWidth & (StWidth - 1)) { 2538 // If not storing a power-of-2 number of bits, expand as two stores. 2539 assert(StVT.isExtended() && !StVT.isVector() && 2540 "Unsupported truncstore!"); 2541 unsigned RoundWidth = 1 << Log2_32(StWidth); 2542 assert(RoundWidth < StWidth); 2543 unsigned ExtraWidth = StWidth - RoundWidth; 2544 assert(ExtraWidth < RoundWidth); 2545 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2546 "Store size not an integral number of bytes!"); 2547 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2548 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2549 SDValue Lo, Hi; 2550 unsigned IncrementSize; 2551 2552 if (TLI.isLittleEndian()) { 2553 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2554 // Store the bottom RoundWidth bits. 2555 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2556 SVOffset, RoundVT, 2557 isVolatile, Alignment); 2558 2559 // Store the remaining ExtraWidth bits. 2560 IncrementSize = RoundWidth / 8; 2561 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2562 DAG.getIntPtrConstant(IncrementSize)); 2563 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2564 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2565 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2566 SVOffset + IncrementSize, ExtraVT, isVolatile, 2567 MinAlign(Alignment, IncrementSize)); 2568 } else { 2569 // Big endian - avoid unaligned stores. 2570 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2571 // Store the top RoundWidth bits. 2572 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2573 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2574 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, 2575 RoundVT, isVolatile, Alignment); 2576 2577 // Store the remaining ExtraWidth bits. 2578 IncrementSize = RoundWidth / 8; 2579 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2580 DAG.getIntPtrConstant(IncrementSize)); 2581 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2582 SVOffset + IncrementSize, ExtraVT, isVolatile, 2583 MinAlign(Alignment, IncrementSize)); 2584 } 2585 2586 // The order of the stores doesn't matter. 2587 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2588 } else { 2589 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2590 Tmp2 != ST->getBasePtr()) 2591 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2592 ST->getOffset()); 2593 2594 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2595 default: assert(0 && "This action is not supported yet!"); 2596 case TargetLowering::Legal: 2597 // If this is an unaligned store and the target doesn't support it, 2598 // expand it. 2599 if (!TLI.allowsUnalignedMemoryAccesses()) { 2600 unsigned ABIAlignment = TLI.getTargetData()-> 2601 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2602 if (ST->getAlignment() < ABIAlignment) 2603 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2604 TLI); 2605 } 2606 break; 2607 case TargetLowering::Custom: 2608 Result = TLI.LowerOperation(Result, DAG); 2609 break; 2610 case Expand: 2611 // TRUNCSTORE:i16 i32 -> STORE i16 2612 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2613 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); 2614 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, 2615 isVolatile, Alignment); 2616 break; 2617 } 2618 } 2619 } 2620 break; 2621 } 2622 case ISD::PCMARKER: 2623 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2624 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2625 break; 2626 case ISD::STACKSAVE: 2627 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2628 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2629 Tmp1 = Result.getValue(0); 2630 Tmp2 = Result.getValue(1); 2631 2632 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2633 default: assert(0 && "This action is not supported yet!"); 2634 case TargetLowering::Legal: break; 2635 case TargetLowering::Custom: 2636 Tmp3 = TLI.LowerOperation(Result, DAG); 2637 if (Tmp3.Val) { 2638 Tmp1 = LegalizeOp(Tmp3); 2639 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2640 } 2641 break; 2642 case TargetLowering::Expand: 2643 // Expand to CopyFromReg if the target set 2644 // StackPointerRegisterToSaveRestore. 2645 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2646 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2647 Node->getValueType(0)); 2648 Tmp2 = Tmp1.getValue(1); 2649 } else { 2650 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2651 Tmp2 = Node->getOperand(0); 2652 } 2653 break; 2654 } 2655 2656 // Since stacksave produce two values, make sure to remember that we 2657 // legalized both of them. 2658 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2659 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2660 return Op.ResNo ? Tmp2 : Tmp1; 2661 2662 case ISD::STACKRESTORE: 2663 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2664 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2665 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2666 2667 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2668 default: assert(0 && "This action is not supported yet!"); 2669 case TargetLowering::Legal: break; 2670 case TargetLowering::Custom: 2671 Tmp1 = TLI.LowerOperation(Result, DAG); 2672 if (Tmp1.Val) Result = Tmp1; 2673 break; 2674 case TargetLowering::Expand: 2675 // Expand to CopyToReg if the target set 2676 // StackPointerRegisterToSaveRestore. 2677 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2678 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2679 } else { 2680 Result = Tmp1; 2681 } 2682 break; 2683 } 2684 break; 2685 2686 case ISD::READCYCLECOUNTER: 2687 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2688 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2689 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2690 Node->getValueType(0))) { 2691 default: assert(0 && "This action is not supported yet!"); 2692 case TargetLowering::Legal: 2693 Tmp1 = Result.getValue(0); 2694 Tmp2 = Result.getValue(1); 2695 break; 2696 case TargetLowering::Custom: 2697 Result = TLI.LowerOperation(Result, DAG); 2698 Tmp1 = LegalizeOp(Result.getValue(0)); 2699 Tmp2 = LegalizeOp(Result.getValue(1)); 2700 break; 2701 } 2702 2703 // Since rdcc produce two values, make sure to remember that we legalized 2704 // both of them. 2705 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2706 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2707 return Result; 2708 2709 case ISD::SELECT: 2710 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2711 case Expand: assert(0 && "It's impossible to expand bools"); 2712 case Legal: 2713 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2714 break; 2715 case Promote: { 2716 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2717 // Make sure the condition is either zero or one. 2718 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2719 if (!DAG.MaskedValueIsZero(Tmp1, 2720 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2721 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2722 break; 2723 } 2724 } 2725 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2726 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2727 2728 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2729 2730 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2731 default: assert(0 && "This action is not supported yet!"); 2732 case TargetLowering::Legal: break; 2733 case TargetLowering::Custom: { 2734 Tmp1 = TLI.LowerOperation(Result, DAG); 2735 if (Tmp1.Val) Result = Tmp1; 2736 break; 2737 } 2738 case TargetLowering::Expand: 2739 if (Tmp1.getOpcode() == ISD::SETCC) { 2740 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2741 Tmp2, Tmp3, 2742 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2743 } else { 2744 Result = DAG.getSelectCC(Tmp1, 2745 DAG.getConstant(0, Tmp1.getValueType()), 2746 Tmp2, Tmp3, ISD::SETNE); 2747 } 2748 break; 2749 case TargetLowering::Promote: { 2750 MVT NVT = 2751 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2752 unsigned ExtOp, TruncOp; 2753 if (Tmp2.getValueType().isVector()) { 2754 ExtOp = ISD::BIT_CONVERT; 2755 TruncOp = ISD::BIT_CONVERT; 2756 } else if (Tmp2.getValueType().isInteger()) { 2757 ExtOp = ISD::ANY_EXTEND; 2758 TruncOp = ISD::TRUNCATE; 2759 } else { 2760 ExtOp = ISD::FP_EXTEND; 2761 TruncOp = ISD::FP_ROUND; 2762 } 2763 // Promote each of the values to the new type. 2764 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2765 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2766 // Perform the larger operation, then round down. 2767 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2768 if (TruncOp != ISD::FP_ROUND) 2769 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2770 else 2771 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2772 DAG.getIntPtrConstant(0)); 2773 break; 2774 } 2775 } 2776 break; 2777 case ISD::SELECT_CC: { 2778 Tmp1 = Node->getOperand(0); // LHS 2779 Tmp2 = Node->getOperand(1); // RHS 2780 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2781 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2782 SDValue CC = Node->getOperand(4); 2783 2784 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2785 2786 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2787 // the LHS is a legal SETCC itself. In this case, we need to compare 2788 // the result against zero to select between true and false values. 2789 if (Tmp2.Val == 0) { 2790 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2791 CC = DAG.getCondCode(ISD::SETNE); 2792 } 2793 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2794 2795 // Everything is legal, see if we should expand this op or something. 2796 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2797 default: assert(0 && "This action is not supported yet!"); 2798 case TargetLowering::Legal: break; 2799 case TargetLowering::Custom: 2800 Tmp1 = TLI.LowerOperation(Result, DAG); 2801 if (Tmp1.Val) Result = Tmp1; 2802 break; 2803 } 2804 break; 2805 } 2806 case ISD::SETCC: 2807 Tmp1 = Node->getOperand(0); 2808 Tmp2 = Node->getOperand(1); 2809 Tmp3 = Node->getOperand(2); 2810 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2811 2812 // If we had to Expand the SetCC operands into a SELECT node, then it may 2813 // not always be possible to return a true LHS & RHS. In this case, just 2814 // return the value we legalized, returned in the LHS 2815 if (Tmp2.Val == 0) { 2816 Result = Tmp1; 2817 break; 2818 } 2819 2820 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2821 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2822 case TargetLowering::Custom: 2823 isCustom = true; 2824 // FALLTHROUGH. 2825 case TargetLowering::Legal: 2826 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2827 if (isCustom) { 2828 Tmp4 = TLI.LowerOperation(Result, DAG); 2829 if (Tmp4.Val) Result = Tmp4; 2830 } 2831 break; 2832 case TargetLowering::Promote: { 2833 // First step, figure out the appropriate operation to use. 2834 // Allow SETCC to not be supported for all legal data types 2835 // Mostly this targets FP 2836 MVT NewInTy = Node->getOperand(0).getValueType(); 2837 MVT OldVT = NewInTy; OldVT = OldVT; 2838 2839 // Scan for the appropriate larger type to use. 2840 while (1) { 2841 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 2842 2843 assert(NewInTy.isInteger() == OldVT.isInteger() && 2844 "Fell off of the edge of the integer world"); 2845 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 2846 "Fell off of the edge of the floating point world"); 2847 2848 // If the target supports SETCC of this type, use it. 2849 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2850 break; 2851 } 2852 if (NewInTy.isInteger()) 2853 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2854 else { 2855 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2856 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2857 } 2858 Tmp1 = LegalizeOp(Tmp1); 2859 Tmp2 = LegalizeOp(Tmp2); 2860 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2861 Result = LegalizeOp(Result); 2862 break; 2863 } 2864 case TargetLowering::Expand: 2865 // Expand a setcc node into a select_cc of the same condition, lhs, and 2866 // rhs that selects between const 1 (true) and const 0 (false). 2867 MVT VT = Node->getValueType(0); 2868 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2869 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2870 Tmp3); 2871 break; 2872 } 2873 break; 2874 case ISD::VSETCC: { 2875 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2876 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2877 SDValue CC = Node->getOperand(2); 2878 2879 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC); 2880 2881 // Everything is legal, see if we should expand this op or something. 2882 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) { 2883 default: assert(0 && "This action is not supported yet!"); 2884 case TargetLowering::Legal: break; 2885 case TargetLowering::Custom: 2886 Tmp1 = TLI.LowerOperation(Result, DAG); 2887 if (Tmp1.Val) Result = Tmp1; 2888 break; 2889 } 2890 break; 2891 } 2892 2893 case ISD::SHL_PARTS: 2894 case ISD::SRA_PARTS: 2895 case ISD::SRL_PARTS: { 2896 SmallVector<SDValue, 8> Ops; 2897 bool Changed = false; 2898 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2899 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2900 Changed |= Ops.back() != Node->getOperand(i); 2901 } 2902 if (Changed) 2903 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2904 2905 switch (TLI.getOperationAction(Node->getOpcode(), 2906 Node->getValueType(0))) { 2907 default: assert(0 && "This action is not supported yet!"); 2908 case TargetLowering::Legal: break; 2909 case TargetLowering::Custom: 2910 Tmp1 = TLI.LowerOperation(Result, DAG); 2911 if (Tmp1.Val) { 2912 SDValue Tmp2, RetVal(0, 0); 2913 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2914 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2915 AddLegalizedOperand(SDValue(Node, i), Tmp2); 2916 if (i == Op.ResNo) 2917 RetVal = Tmp2; 2918 } 2919 assert(RetVal.Val && "Illegal result number"); 2920 return RetVal; 2921 } 2922 break; 2923 } 2924 2925 // Since these produce multiple values, make sure to remember that we 2926 // legalized all of them. 2927 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2928 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i)); 2929 return Result.getValue(Op.ResNo); 2930 } 2931 2932 // Binary operators 2933 case ISD::ADD: 2934 case ISD::SUB: 2935 case ISD::MUL: 2936 case ISD::MULHS: 2937 case ISD::MULHU: 2938 case ISD::UDIV: 2939 case ISD::SDIV: 2940 case ISD::AND: 2941 case ISD::OR: 2942 case ISD::XOR: 2943 case ISD::SHL: 2944 case ISD::SRL: 2945 case ISD::SRA: 2946 case ISD::FADD: 2947 case ISD::FSUB: 2948 case ISD::FMUL: 2949 case ISD::FDIV: 2950 case ISD::FPOW: 2951 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2952 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2953 case Expand: assert(0 && "Not possible"); 2954 case Legal: 2955 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2956 break; 2957 case Promote: 2958 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2959 break; 2960 } 2961 2962 if ((Node->getOpcode() == ISD::SHL || 2963 Node->getOpcode() == ISD::SRL || 2964 Node->getOpcode() == ISD::SRA) && 2965 !Node->getValueType(0).isVector()) { 2966 if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType())) 2967 Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2); 2968 else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType())) 2969 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2); 2970 } 2971 2972 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2973 2974 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2975 default: assert(0 && "BinOp legalize operation not supported"); 2976 case TargetLowering::Legal: break; 2977 case TargetLowering::Custom: 2978 Tmp1 = TLI.LowerOperation(Result, DAG); 2979 if (Tmp1.Val) { 2980 Result = Tmp1; 2981 break; 2982 } 2983 // Fall through if the custom lower can't deal with the operation 2984 case TargetLowering::Expand: { 2985 MVT VT = Op.getValueType(); 2986 2987 // See if multiply or divide can be lowered using two-result operations. 2988 SDVTList VTs = DAG.getVTList(VT, VT); 2989 if (Node->getOpcode() == ISD::MUL) { 2990 // We just need the low half of the multiply; try both the signed 2991 // and unsigned forms. If the target supports both SMUL_LOHI and 2992 // UMUL_LOHI, form a preference by checking which forms of plain 2993 // MULH it supports. 2994 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2995 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2996 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2997 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2998 unsigned OpToUse = 0; 2999 if (HasSMUL_LOHI && !HasMULHS) { 3000 OpToUse = ISD::SMUL_LOHI; 3001 } else if (HasUMUL_LOHI && !HasMULHU) { 3002 OpToUse = ISD::UMUL_LOHI; 3003 } else if (HasSMUL_LOHI) { 3004 OpToUse = ISD::SMUL_LOHI; 3005 } else if (HasUMUL_LOHI) { 3006 OpToUse = ISD::UMUL_LOHI; 3007 } 3008 if (OpToUse) { 3009 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 3010 break; 3011 } 3012 } 3013 if (Node->getOpcode() == ISD::MULHS && 3014 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 3015 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3016 break; 3017 } 3018 if (Node->getOpcode() == ISD::MULHU && 3019 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 3020 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3021 break; 3022 } 3023 if (Node->getOpcode() == ISD::SDIV && 3024 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3025 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3026 break; 3027 } 3028 if (Node->getOpcode() == ISD::UDIV && 3029 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3030 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3031 break; 3032 } 3033 3034 // Check to see if we have a libcall for this operator. 3035 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3036 bool isSigned = false; 3037 switch (Node->getOpcode()) { 3038 case ISD::UDIV: 3039 case ISD::SDIV: 3040 if (VT == MVT::i32) { 3041 LC = Node->getOpcode() == ISD::UDIV 3042 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3043 isSigned = Node->getOpcode() == ISD::SDIV; 3044 } 3045 break; 3046 case ISD::FPOW: 3047 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3048 RTLIB::POW_PPCF128); 3049 break; 3050 default: break; 3051 } 3052 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3053 SDValue Dummy; 3054 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3055 break; 3056 } 3057 3058 assert(Node->getValueType(0).isVector() && 3059 "Cannot expand this binary operator!"); 3060 // Expand the operation into a bunch of nasty scalar code. 3061 Result = LegalizeOp(UnrollVectorOp(Op)); 3062 break; 3063 } 3064 case TargetLowering::Promote: { 3065 switch (Node->getOpcode()) { 3066 default: assert(0 && "Do not know how to promote this BinOp!"); 3067 case ISD::AND: 3068 case ISD::OR: 3069 case ISD::XOR: { 3070 MVT OVT = Node->getValueType(0); 3071 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3072 assert(OVT.isVector() && "Cannot promote this BinOp!"); 3073 // Bit convert each of the values to the new type. 3074 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 3075 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 3076 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3077 // Bit convert the result back the original type. 3078 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 3079 break; 3080 } 3081 } 3082 } 3083 } 3084 break; 3085 3086 case ISD::SMUL_LOHI: 3087 case ISD::UMUL_LOHI: 3088 case ISD::SDIVREM: 3089 case ISD::UDIVREM: 3090 // These nodes will only be produced by target-specific lowering, so 3091 // they shouldn't be here if they aren't legal. 3092 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3093 "This must be legal!"); 3094 3095 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3096 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3097 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3098 break; 3099 3100 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3101 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3102 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3103 case Expand: assert(0 && "Not possible"); 3104 case Legal: 3105 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3106 break; 3107 case Promote: 3108 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3109 break; 3110 } 3111 3112 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3113 3114 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3115 default: assert(0 && "Operation not supported"); 3116 case TargetLowering::Custom: 3117 Tmp1 = TLI.LowerOperation(Result, DAG); 3118 if (Tmp1.Val) Result = Tmp1; 3119 break; 3120 case TargetLowering::Legal: break; 3121 case TargetLowering::Expand: { 3122 // If this target supports fabs/fneg natively and select is cheap, 3123 // do this efficiently. 3124 if (!TLI.isSelectExpensive() && 3125 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3126 TargetLowering::Legal && 3127 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3128 TargetLowering::Legal) { 3129 // Get the sign bit of the RHS. 3130 MVT IVT = 3131 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3132 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 3133 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), 3134 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3135 // Get the absolute value of the result. 3136 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 3137 // Select between the nabs and abs value based on the sign bit of 3138 // the input. 3139 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 3140 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3141 AbsVal), 3142 AbsVal); 3143 Result = LegalizeOp(Result); 3144 break; 3145 } 3146 3147 // Otherwise, do bitwise ops! 3148 MVT NVT = 3149 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3150 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3151 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 3152 Result = LegalizeOp(Result); 3153 break; 3154 } 3155 } 3156 break; 3157 3158 case ISD::ADDC: 3159 case ISD::SUBC: 3160 Tmp1 = LegalizeOp(Node->getOperand(0)); 3161 Tmp2 = LegalizeOp(Node->getOperand(1)); 3162 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3163 // Since this produces two values, make sure to remember that we legalized 3164 // both of them. 3165 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 3166 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 3167 return Result; 3168 3169 case ISD::ADDE: 3170 case ISD::SUBE: 3171 Tmp1 = LegalizeOp(Node->getOperand(0)); 3172 Tmp2 = LegalizeOp(Node->getOperand(1)); 3173 Tmp3 = LegalizeOp(Node->getOperand(2)); 3174 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3175 // Since this produces two values, make sure to remember that we legalized 3176 // both of them. 3177 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 3178 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 3179 return Result; 3180 3181 case ISD::BUILD_PAIR: { 3182 MVT PairTy = Node->getValueType(0); 3183 // TODO: handle the case where the Lo and Hi operands are not of legal type 3184 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3185 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3186 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3187 case TargetLowering::Promote: 3188 case TargetLowering::Custom: 3189 assert(0 && "Cannot promote/custom this yet!"); 3190 case TargetLowering::Legal: 3191 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3192 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 3193 break; 3194 case TargetLowering::Expand: 3195 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 3196 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 3197 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 3198 DAG.getConstant(PairTy.getSizeInBits()/2, 3199 TLI.getShiftAmountTy())); 3200 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 3201 break; 3202 } 3203 break; 3204 } 3205 3206 case ISD::UREM: 3207 case ISD::SREM: 3208 case ISD::FREM: 3209 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3210 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3211 3212 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3213 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3214 case TargetLowering::Custom: 3215 isCustom = true; 3216 // FALLTHROUGH 3217 case TargetLowering::Legal: 3218 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3219 if (isCustom) { 3220 Tmp1 = TLI.LowerOperation(Result, DAG); 3221 if (Tmp1.Val) Result = Tmp1; 3222 } 3223 break; 3224 case TargetLowering::Expand: { 3225 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3226 bool isSigned = DivOpc == ISD::SDIV; 3227 MVT VT = Node->getValueType(0); 3228 3229 // See if remainder can be lowered using two-result operations. 3230 SDVTList VTs = DAG.getVTList(VT, VT); 3231 if (Node->getOpcode() == ISD::SREM && 3232 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3233 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3234 break; 3235 } 3236 if (Node->getOpcode() == ISD::UREM && 3237 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3238 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3239 break; 3240 } 3241 3242 if (VT.isInteger()) { 3243 if (TLI.getOperationAction(DivOpc, VT) == 3244 TargetLowering::Legal) { 3245 // X % Y -> X-X/Y*Y 3246 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3247 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3248 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3249 } else if (VT.isVector()) { 3250 Result = LegalizeOp(UnrollVectorOp(Op)); 3251 } else { 3252 assert(VT == MVT::i32 && 3253 "Cannot expand this binary operator!"); 3254 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3255 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3256 SDValue Dummy; 3257 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3258 } 3259 } else { 3260 assert(VT.isFloatingPoint() && 3261 "remainder op must have integer or floating-point type"); 3262 if (VT.isVector()) { 3263 Result = LegalizeOp(UnrollVectorOp(Op)); 3264 } else { 3265 // Floating point mod -> fmod libcall. 3266 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3267 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3268 SDValue Dummy; 3269 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3270 } 3271 } 3272 break; 3273 } 3274 } 3275 break; 3276 case ISD::VAARG: { 3277 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3278 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3279 3280 MVT VT = Node->getValueType(0); 3281 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3282 default: assert(0 && "This action is not supported yet!"); 3283 case TargetLowering::Custom: 3284 isCustom = true; 3285 // FALLTHROUGH 3286 case TargetLowering::Legal: 3287 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3288 Result = Result.getValue(0); 3289 Tmp1 = Result.getValue(1); 3290 3291 if (isCustom) { 3292 Tmp2 = TLI.LowerOperation(Result, DAG); 3293 if (Tmp2.Val) { 3294 Result = LegalizeOp(Tmp2); 3295 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3296 } 3297 } 3298 break; 3299 case TargetLowering::Expand: { 3300 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3301 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 3302 // Increment the pointer, VAList, to the next vaarg 3303 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3304 DAG.getConstant(VT.getSizeInBits()/8, 3305 TLI.getPointerTy())); 3306 // Store the incremented VAList to the legalized pointer 3307 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 3308 // Load the actual argument out of the pointer VAList 3309 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3310 Tmp1 = LegalizeOp(Result.getValue(1)); 3311 Result = LegalizeOp(Result); 3312 break; 3313 } 3314 } 3315 // Since VAARG produces two values, make sure to remember that we 3316 // legalized both of them. 3317 AddLegalizedOperand(SDValue(Node, 0), Result); 3318 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 3319 return Op.ResNo ? Tmp1 : Result; 3320 } 3321 3322 case ISD::VACOPY: 3323 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3324 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3325 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3326 3327 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3328 default: assert(0 && "This action is not supported yet!"); 3329 case TargetLowering::Custom: 3330 isCustom = true; 3331 // FALLTHROUGH 3332 case TargetLowering::Legal: 3333 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3334 Node->getOperand(3), Node->getOperand(4)); 3335 if (isCustom) { 3336 Tmp1 = TLI.LowerOperation(Result, DAG); 3337 if (Tmp1.Val) Result = Tmp1; 3338 } 3339 break; 3340 case TargetLowering::Expand: 3341 // This defaults to loading a pointer from the input and storing it to the 3342 // output, returning the chain. 3343 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3344 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3345 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0); 3346 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0); 3347 break; 3348 } 3349 break; 3350 3351 case ISD::VAEND: 3352 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3353 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3354 3355 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3356 default: assert(0 && "This action is not supported yet!"); 3357 case TargetLowering::Custom: 3358 isCustom = true; 3359 // FALLTHROUGH 3360 case TargetLowering::Legal: 3361 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3362 if (isCustom) { 3363 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3364 if (Tmp1.Val) Result = Tmp1; 3365 } 3366 break; 3367 case TargetLowering::Expand: 3368 Result = Tmp1; // Default to a no-op, return the chain 3369 break; 3370 } 3371 break; 3372 3373 case ISD::VASTART: 3374 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3375 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3376 3377 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3378 3379 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3380 default: assert(0 && "This action is not supported yet!"); 3381 case TargetLowering::Legal: break; 3382 case TargetLowering::Custom: 3383 Tmp1 = TLI.LowerOperation(Result, DAG); 3384 if (Tmp1.Val) Result = Tmp1; 3385 break; 3386 } 3387 break; 3388 3389 case ISD::ROTL: 3390 case ISD::ROTR: 3391 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3392 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3393 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3394 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3395 default: 3396 assert(0 && "ROTL/ROTR legalize operation not supported"); 3397 break; 3398 case TargetLowering::Legal: 3399 break; 3400 case TargetLowering::Custom: 3401 Tmp1 = TLI.LowerOperation(Result, DAG); 3402 if (Tmp1.Val) Result = Tmp1; 3403 break; 3404 case TargetLowering::Promote: 3405 assert(0 && "Do not know how to promote ROTL/ROTR"); 3406 break; 3407 case TargetLowering::Expand: 3408 assert(0 && "Do not know how to expand ROTL/ROTR"); 3409 break; 3410 } 3411 break; 3412 3413 case ISD::BSWAP: 3414 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3415 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3416 case TargetLowering::Custom: 3417 assert(0 && "Cannot custom legalize this yet!"); 3418 case TargetLowering::Legal: 3419 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3420 break; 3421 case TargetLowering::Promote: { 3422 MVT OVT = Tmp1.getValueType(); 3423 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3424 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3425 3426 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3427 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3428 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3429 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3430 break; 3431 } 3432 case TargetLowering::Expand: 3433 Result = ExpandBSWAP(Tmp1); 3434 break; 3435 } 3436 break; 3437 3438 case ISD::CTPOP: 3439 case ISD::CTTZ: 3440 case ISD::CTLZ: 3441 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3442 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3443 case TargetLowering::Custom: 3444 case TargetLowering::Legal: 3445 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3446 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3447 TargetLowering::Custom) { 3448 Tmp1 = TLI.LowerOperation(Result, DAG); 3449 if (Tmp1.Val) { 3450 Result = Tmp1; 3451 } 3452 } 3453 break; 3454 case TargetLowering::Promote: { 3455 MVT OVT = Tmp1.getValueType(); 3456 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3457 3458 // Zero extend the argument. 3459 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3460 // Perform the larger operation, then subtract if needed. 3461 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3462 switch (Node->getOpcode()) { 3463 case ISD::CTPOP: 3464 Result = Tmp1; 3465 break; 3466 case ISD::CTTZ: 3467 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3468 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 3469 DAG.getConstant(NVT.getSizeInBits(), NVT), 3470 ISD::SETEQ); 3471 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3472 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3473 break; 3474 case ISD::CTLZ: 3475 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3476 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3477 DAG.getConstant(NVT.getSizeInBits() - 3478 OVT.getSizeInBits(), NVT)); 3479 break; 3480 } 3481 break; 3482 } 3483 case TargetLowering::Expand: 3484 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3485 break; 3486 } 3487 break; 3488 3489 // Unary operators 3490 case ISD::FABS: 3491 case ISD::FNEG: 3492 case ISD::FSQRT: 3493 case ISD::FSIN: 3494 case ISD::FCOS: 3495 Tmp1 = LegalizeOp(Node->getOperand(0)); 3496 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3497 case TargetLowering::Promote: 3498 case TargetLowering::Custom: 3499 isCustom = true; 3500 // FALLTHROUGH 3501 case TargetLowering::Legal: 3502 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3503 if (isCustom) { 3504 Tmp1 = TLI.LowerOperation(Result, DAG); 3505 if (Tmp1.Val) Result = Tmp1; 3506 } 3507 break; 3508 case TargetLowering::Expand: 3509 switch (Node->getOpcode()) { 3510 default: assert(0 && "Unreachable!"); 3511 case ISD::FNEG: 3512 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3513 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3514 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3515 break; 3516 case ISD::FABS: { 3517 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3518 MVT VT = Node->getValueType(0); 3519 Tmp2 = DAG.getConstantFP(0.0, VT); 3520 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 3521 ISD::SETUGT); 3522 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3523 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3524 break; 3525 } 3526 case ISD::FSQRT: 3527 case ISD::FSIN: 3528 case ISD::FCOS: { 3529 MVT VT = Node->getValueType(0); 3530 3531 // Expand unsupported unary vector operators by unrolling them. 3532 if (VT.isVector()) { 3533 Result = LegalizeOp(UnrollVectorOp(Op)); 3534 break; 3535 } 3536 3537 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3538 switch(Node->getOpcode()) { 3539 case ISD::FSQRT: 3540 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3541 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3542 break; 3543 case ISD::FSIN: 3544 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3545 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3546 break; 3547 case ISD::FCOS: 3548 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3549 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3550 break; 3551 default: assert(0 && "Unreachable!"); 3552 } 3553 SDValue Dummy; 3554 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3555 break; 3556 } 3557 } 3558 break; 3559 } 3560 break; 3561 case ISD::FPOWI: { 3562 MVT VT = Node->getValueType(0); 3563 3564 // Expand unsupported unary vector operators by unrolling them. 3565 if (VT.isVector()) { 3566 Result = LegalizeOp(UnrollVectorOp(Op)); 3567 break; 3568 } 3569 3570 // We always lower FPOWI into a libcall. No target support for it yet. 3571 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3572 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3573 SDValue Dummy; 3574 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3575 break; 3576 } 3577 case ISD::BIT_CONVERT: 3578 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3579 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3580 Node->getValueType(0)); 3581 } else if (Op.getOperand(0).getValueType().isVector()) { 3582 // The input has to be a vector type, we have to either scalarize it, pack 3583 // it, or convert it based on whether the input vector type is legal. 3584 SDNode *InVal = Node->getOperand(0).Val; 3585 int InIx = Node->getOperand(0).ResNo; 3586 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 3587 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 3588 3589 // Figure out if there is a simple type corresponding to this Vector 3590 // type. If so, convert to the vector type. 3591 MVT TVT = MVT::getVectorVT(EVT, NumElems); 3592 if (TLI.isTypeLegal(TVT)) { 3593 // Turn this into a bit convert of the vector input. 3594 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3595 LegalizeOp(Node->getOperand(0))); 3596 break; 3597 } else if (NumElems == 1) { 3598 // Turn this into a bit convert of the scalar input. 3599 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3600 ScalarizeVectorOp(Node->getOperand(0))); 3601 break; 3602 } else { 3603 // FIXME: UNIMP! Store then reload 3604 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3605 } 3606 } else { 3607 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3608 Node->getOperand(0).getValueType())) { 3609 default: assert(0 && "Unknown operation action!"); 3610 case TargetLowering::Expand: 3611 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3612 Node->getValueType(0)); 3613 break; 3614 case TargetLowering::Legal: 3615 Tmp1 = LegalizeOp(Node->getOperand(0)); 3616 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3617 break; 3618 } 3619 } 3620 break; 3621 3622 // Conversion operators. The source and destination have different types. 3623 case ISD::SINT_TO_FP: 3624 case ISD::UINT_TO_FP: { 3625 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3626 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3627 case Legal: 3628 switch (TLI.getOperationAction(Node->getOpcode(), 3629 Node->getOperand(0).getValueType())) { 3630 default: assert(0 && "Unknown operation action!"); 3631 case TargetLowering::Custom: 3632 isCustom = true; 3633 // FALLTHROUGH 3634 case TargetLowering::Legal: 3635 Tmp1 = LegalizeOp(Node->getOperand(0)); 3636 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3637 if (isCustom) { 3638 Tmp1 = TLI.LowerOperation(Result, DAG); 3639 if (Tmp1.Val) Result = Tmp1; 3640 } 3641 break; 3642 case TargetLowering::Expand: 3643 Result = ExpandLegalINT_TO_FP(isSigned, 3644 LegalizeOp(Node->getOperand(0)), 3645 Node->getValueType(0)); 3646 break; 3647 case TargetLowering::Promote: 3648 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3649 Node->getValueType(0), 3650 isSigned); 3651 break; 3652 } 3653 break; 3654 case Expand: 3655 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3656 Node->getValueType(0), Node->getOperand(0)); 3657 break; 3658 case Promote: 3659 Tmp1 = PromoteOp(Node->getOperand(0)); 3660 if (isSigned) { 3661 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3662 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3663 } else { 3664 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3665 Node->getOperand(0).getValueType()); 3666 } 3667 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3668 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3669 break; 3670 } 3671 break; 3672 } 3673 case ISD::TRUNCATE: 3674 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3675 case Legal: 3676 Tmp1 = LegalizeOp(Node->getOperand(0)); 3677 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3678 break; 3679 case Expand: 3680 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3681 3682 // Since the result is legal, we should just be able to truncate the low 3683 // part of the source. 3684 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3685 break; 3686 case Promote: 3687 Result = PromoteOp(Node->getOperand(0)); 3688 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3689 break; 3690 } 3691 break; 3692 3693 case ISD::FP_TO_SINT: 3694 case ISD::FP_TO_UINT: 3695 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3696 case Legal: 3697 Tmp1 = LegalizeOp(Node->getOperand(0)); 3698 3699 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3700 default: assert(0 && "Unknown operation action!"); 3701 case TargetLowering::Custom: 3702 isCustom = true; 3703 // FALLTHROUGH 3704 case TargetLowering::Legal: 3705 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3706 if (isCustom) { 3707 Tmp1 = TLI.LowerOperation(Result, DAG); 3708 if (Tmp1.Val) Result = Tmp1; 3709 } 3710 break; 3711 case TargetLowering::Promote: 3712 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3713 Node->getOpcode() == ISD::FP_TO_SINT); 3714 break; 3715 case TargetLowering::Expand: 3716 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3717 SDValue True, False; 3718 MVT VT = Node->getOperand(0).getValueType(); 3719 MVT NVT = Node->getValueType(0); 3720 const uint64_t zero[] = {0, 0}; 3721 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 3722 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 3723 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 3724 Tmp2 = DAG.getConstantFP(apf, VT); 3725 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)), 3726 Node->getOperand(0), Tmp2, ISD::SETLT); 3727 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3728 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3729 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3730 Tmp2)); 3731 False = DAG.getNode(ISD::XOR, NVT, False, 3732 DAG.getConstant(x, NVT)); 3733 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3734 break; 3735 } else { 3736 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3737 } 3738 break; 3739 } 3740 break; 3741 case Expand: { 3742 MVT VT = Op.getValueType(); 3743 MVT OVT = Node->getOperand(0).getValueType(); 3744 // Convert ppcf128 to i32 3745 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3746 if (Node->getOpcode() == ISD::FP_TO_SINT) { 3747 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 3748 Node->getOperand(0), DAG.getValueType(MVT::f64)); 3749 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 3750 DAG.getIntPtrConstant(1)); 3751 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 3752 } else { 3753 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3754 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3755 Tmp2 = DAG.getConstantFP(apf, OVT); 3756 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3757 // FIXME: generated code sucks. 3758 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3759 DAG.getNode(ISD::ADD, MVT::i32, 3760 DAG.getNode(ISD::FP_TO_SINT, VT, 3761 DAG.getNode(ISD::FSUB, OVT, 3762 Node->getOperand(0), Tmp2)), 3763 DAG.getConstant(0x80000000, MVT::i32)), 3764 DAG.getNode(ISD::FP_TO_SINT, VT, 3765 Node->getOperand(0)), 3766 DAG.getCondCode(ISD::SETGE)); 3767 } 3768 break; 3769 } 3770 // Convert f32 / f64 to i32 / i64 / i128. 3771 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ? 3772 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT); 3773 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!"); 3774 SDValue Dummy; 3775 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3776 break; 3777 } 3778 case Promote: 3779 Tmp1 = PromoteOp(Node->getOperand(0)); 3780 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3781 Result = LegalizeOp(Result); 3782 break; 3783 } 3784 break; 3785 3786 case ISD::FP_EXTEND: { 3787 MVT DstVT = Op.getValueType(); 3788 MVT SrcVT = Op.getOperand(0).getValueType(); 3789 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3790 // The only other way we can lower this is to turn it into a STORE, 3791 // LOAD pair, targetting a temporary location (a stack slot). 3792 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 3793 break; 3794 } 3795 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3796 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3797 case Legal: 3798 Tmp1 = LegalizeOp(Node->getOperand(0)); 3799 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3800 break; 3801 case Promote: 3802 Tmp1 = PromoteOp(Node->getOperand(0)); 3803 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 3804 break; 3805 } 3806 break; 3807 } 3808 case ISD::FP_ROUND: { 3809 MVT DstVT = Op.getValueType(); 3810 MVT SrcVT = Op.getOperand(0).getValueType(); 3811 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3812 if (SrcVT == MVT::ppcf128) { 3813 SDValue Lo; 3814 ExpandOp(Node->getOperand(0), Lo, Result); 3815 // Round it the rest of the way (e.g. to f32) if needed. 3816 if (DstVT!=MVT::f64) 3817 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 3818 break; 3819 } 3820 // The only other way we can lower this is to turn it into a STORE, 3821 // LOAD pair, targetting a temporary location (a stack slot). 3822 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 3823 break; 3824 } 3825 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3826 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3827 case Legal: 3828 Tmp1 = LegalizeOp(Node->getOperand(0)); 3829 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3830 break; 3831 case Promote: 3832 Tmp1 = PromoteOp(Node->getOperand(0)); 3833 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 3834 Node->getOperand(1)); 3835 break; 3836 } 3837 break; 3838 } 3839 case ISD::ANY_EXTEND: 3840 case ISD::ZERO_EXTEND: 3841 case ISD::SIGN_EXTEND: 3842 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3843 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3844 case Legal: 3845 Tmp1 = LegalizeOp(Node->getOperand(0)); 3846 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3847 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3848 TargetLowering::Custom) { 3849 Tmp1 = TLI.LowerOperation(Result, DAG); 3850 if (Tmp1.Val) Result = Tmp1; 3851 } 3852 break; 3853 case Promote: 3854 switch (Node->getOpcode()) { 3855 case ISD::ANY_EXTEND: 3856 Tmp1 = PromoteOp(Node->getOperand(0)); 3857 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3858 break; 3859 case ISD::ZERO_EXTEND: 3860 Result = PromoteOp(Node->getOperand(0)); 3861 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3862 Result = DAG.getZeroExtendInReg(Result, 3863 Node->getOperand(0).getValueType()); 3864 break; 3865 case ISD::SIGN_EXTEND: 3866 Result = PromoteOp(Node->getOperand(0)); 3867 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3868 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3869 Result, 3870 DAG.getValueType(Node->getOperand(0).getValueType())); 3871 break; 3872 } 3873 } 3874 break; 3875 case ISD::FP_ROUND_INREG: 3876 case ISD::SIGN_EXTEND_INREG: { 3877 Tmp1 = LegalizeOp(Node->getOperand(0)); 3878 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3879 3880 // If this operation is not supported, convert it to a shl/shr or load/store 3881 // pair. 3882 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3883 default: assert(0 && "This action not supported for this op yet!"); 3884 case TargetLowering::Legal: 3885 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3886 break; 3887 case TargetLowering::Expand: 3888 // If this is an integer extend and shifts are supported, do that. 3889 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3890 // NOTE: we could fall back on load/store here too for targets without 3891 // SAR. However, it is doubtful that any exist. 3892 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 3893 ExtraVT.getSizeInBits(); 3894 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3895 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3896 Node->getOperand(0), ShiftCst); 3897 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3898 Result, ShiftCst); 3899 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3900 // The only way we can lower this is to turn it into a TRUNCSTORE, 3901 // EXTLOAD pair, targetting a temporary location (a stack slot). 3902 3903 // NOTE: there is a choice here between constantly creating new stack 3904 // slots and always reusing the same one. We currently always create 3905 // new ones, as reuse may inhibit scheduling. 3906 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 3907 Node->getValueType(0)); 3908 } else { 3909 assert(0 && "Unknown op"); 3910 } 3911 break; 3912 } 3913 break; 3914 } 3915 case ISD::TRAMPOLINE: { 3916 SDValue Ops[6]; 3917 for (unsigned i = 0; i != 6; ++i) 3918 Ops[i] = LegalizeOp(Node->getOperand(i)); 3919 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3920 // The only option for this node is to custom lower it. 3921 Result = TLI.LowerOperation(Result, DAG); 3922 assert(Result.Val && "Should always custom lower!"); 3923 3924 // Since trampoline produces two values, make sure to remember that we 3925 // legalized both of them. 3926 Tmp1 = LegalizeOp(Result.getValue(1)); 3927 Result = LegalizeOp(Result); 3928 AddLegalizedOperand(SDValue(Node, 0), Result); 3929 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 3930 return Op.ResNo ? Tmp1 : Result; 3931 } 3932 case ISD::FLT_ROUNDS_: { 3933 MVT VT = Node->getValueType(0); 3934 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3935 default: assert(0 && "This action not supported for this op yet!"); 3936 case TargetLowering::Custom: 3937 Result = TLI.LowerOperation(Op, DAG); 3938 if (Result.Val) break; 3939 // Fall Thru 3940 case TargetLowering::Legal: 3941 // If this operation is not supported, lower it to constant 1 3942 Result = DAG.getConstant(1, VT); 3943 break; 3944 } 3945 break; 3946 } 3947 case ISD::TRAP: { 3948 MVT VT = Node->getValueType(0); 3949 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3950 default: assert(0 && "This action not supported for this op yet!"); 3951 case TargetLowering::Legal: 3952 Tmp1 = LegalizeOp(Node->getOperand(0)); 3953 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3954 break; 3955 case TargetLowering::Custom: 3956 Result = TLI.LowerOperation(Op, DAG); 3957 if (Result.Val) break; 3958 // Fall Thru 3959 case TargetLowering::Expand: 3960 // If this operation is not supported, lower it to 'abort()' call 3961 Tmp1 = LegalizeOp(Node->getOperand(0)); 3962 TargetLowering::ArgListTy Args; 3963 std::pair<SDValue,SDValue> CallResult = 3964 TLI.LowerCallTo(Tmp1, Type::VoidTy, 3965 false, false, false, CallingConv::C, false, 3966 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 3967 Args, DAG); 3968 Result = CallResult.second; 3969 break; 3970 } 3971 break; 3972 } 3973 } 3974 3975 assert(Result.getValueType() == Op.getValueType() && 3976 "Bad legalization!"); 3977 3978 // Make sure that the generated code is itself legal. 3979 if (Result != Op) 3980 Result = LegalizeOp(Result); 3981 3982 // Note that LegalizeOp may be reentered even from single-use nodes, which 3983 // means that we always must cache transformed nodes. 3984 AddLegalizedOperand(Op, Result); 3985 return Result; 3986} 3987 3988/// PromoteOp - Given an operation that produces a value in an invalid type, 3989/// promote it to compute the value into a larger type. The produced value will 3990/// have the correct bits for the low portion of the register, but no guarantee 3991/// is made about the top bits: it may be zero, sign-extended, or garbage. 3992SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { 3993 MVT VT = Op.getValueType(); 3994 MVT NVT = TLI.getTypeToTransformTo(VT); 3995 assert(getTypeAction(VT) == Promote && 3996 "Caller should expand or legalize operands that are not promotable!"); 3997 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() && 3998 "Cannot promote to smaller type!"); 3999 4000 SDValue Tmp1, Tmp2, Tmp3; 4001 SDValue Result; 4002 SDNode *Node = Op.Val; 4003 4004 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op); 4005 if (I != PromotedNodes.end()) return I->second; 4006 4007 switch (Node->getOpcode()) { 4008 case ISD::CopyFromReg: 4009 assert(0 && "CopyFromReg must be legal!"); 4010 default: 4011#ifndef NDEBUG 4012 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4013#endif 4014 assert(0 && "Do not know how to promote this operator!"); 4015 abort(); 4016 case ISD::UNDEF: 4017 Result = DAG.getNode(ISD::UNDEF, NVT); 4018 break; 4019 case ISD::Constant: 4020 if (VT != MVT::i1) 4021 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 4022 else 4023 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 4024 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4025 break; 4026 case ISD::ConstantFP: 4027 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 4028 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4029 break; 4030 4031 case ISD::SETCC: 4032 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0))) 4033 && "SetCC type is not legal??"); 4034 Result = DAG.getNode(ISD::SETCC, 4035 TLI.getSetCCResultType(Node->getOperand(0)), 4036 Node->getOperand(0), Node->getOperand(1), 4037 Node->getOperand(2)); 4038 break; 4039 4040 case ISD::TRUNCATE: 4041 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4042 case Legal: 4043 Result = LegalizeOp(Node->getOperand(0)); 4044 assert(Result.getValueType().bitsGE(NVT) && 4045 "This truncation doesn't make sense!"); 4046 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT 4047 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 4048 break; 4049 case Promote: 4050 // The truncation is not required, because we don't guarantee anything 4051 // about high bits anyway. 4052 Result = PromoteOp(Node->getOperand(0)); 4053 break; 4054 case Expand: 4055 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4056 // Truncate the low part of the expanded value to the result type 4057 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 4058 } 4059 break; 4060 case ISD::SIGN_EXTEND: 4061 case ISD::ZERO_EXTEND: 4062 case ISD::ANY_EXTEND: 4063 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4064 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4065 case Legal: 4066 // Input is legal? Just do extend all the way to the larger type. 4067 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4068 break; 4069 case Promote: 4070 // Promote the reg if it's smaller. 4071 Result = PromoteOp(Node->getOperand(0)); 4072 // The high bits are not guaranteed to be anything. Insert an extend. 4073 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4074 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4075 DAG.getValueType(Node->getOperand(0).getValueType())); 4076 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4077 Result = DAG.getZeroExtendInReg(Result, 4078 Node->getOperand(0).getValueType()); 4079 break; 4080 } 4081 break; 4082 case ISD::BIT_CONVERT: 4083 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4084 Node->getValueType(0)); 4085 Result = PromoteOp(Result); 4086 break; 4087 4088 case ISD::FP_EXTEND: 4089 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4090 case ISD::FP_ROUND: 4091 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4092 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4093 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4094 case Legal: 4095 if (Node->getConstantOperandVal(1) == 0) { 4096 // Input is legal? Do an FP_ROUND_INREG. 4097 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 4098 DAG.getValueType(VT)); 4099 } else { 4100 // Just remove the truncate, it isn't affecting the value. 4101 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 4102 Node->getOperand(1)); 4103 } 4104 break; 4105 } 4106 break; 4107 case ISD::SINT_TO_FP: 4108 case ISD::UINT_TO_FP: 4109 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4110 case Legal: 4111 // No extra round required here. 4112 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4113 break; 4114 4115 case Promote: 4116 Result = PromoteOp(Node->getOperand(0)); 4117 if (Node->getOpcode() == ISD::SINT_TO_FP) 4118 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4119 Result, 4120 DAG.getValueType(Node->getOperand(0).getValueType())); 4121 else 4122 Result = DAG.getZeroExtendInReg(Result, 4123 Node->getOperand(0).getValueType()); 4124 // No extra round required here. 4125 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 4126 break; 4127 case Expand: 4128 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4129 Node->getOperand(0)); 4130 // Round if we cannot tolerate excess precision. 4131 if (NoExcessFPPrecision) 4132 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4133 DAG.getValueType(VT)); 4134 break; 4135 } 4136 break; 4137 4138 case ISD::SIGN_EXTEND_INREG: 4139 Result = PromoteOp(Node->getOperand(0)); 4140 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4141 Node->getOperand(1)); 4142 break; 4143 case ISD::FP_TO_SINT: 4144 case ISD::FP_TO_UINT: 4145 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4146 case Legal: 4147 case Expand: 4148 Tmp1 = Node->getOperand(0); 4149 break; 4150 case Promote: 4151 // The input result is prerounded, so we don't have to do anything 4152 // special. 4153 Tmp1 = PromoteOp(Node->getOperand(0)); 4154 break; 4155 } 4156 // If we're promoting a UINT to a larger size, check to see if the new node 4157 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4158 // we can use that instead. This allows us to generate better code for 4159 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4160 // legal, such as PowerPC. 4161 if (Node->getOpcode() == ISD::FP_TO_UINT && 4162 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 4163 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 4164 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4165 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 4166 } else { 4167 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4168 } 4169 break; 4170 4171 case ISD::FABS: 4172 case ISD::FNEG: 4173 Tmp1 = PromoteOp(Node->getOperand(0)); 4174 assert(Tmp1.getValueType() == NVT); 4175 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4176 // NOTE: we do not have to do any extra rounding here for 4177 // NoExcessFPPrecision, because we know the input will have the appropriate 4178 // precision, and these operations don't modify precision at all. 4179 break; 4180 4181 case ISD::FSQRT: 4182 case ISD::FSIN: 4183 case ISD::FCOS: 4184 Tmp1 = PromoteOp(Node->getOperand(0)); 4185 assert(Tmp1.getValueType() == NVT); 4186 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4187 if (NoExcessFPPrecision) 4188 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4189 DAG.getValueType(VT)); 4190 break; 4191 4192 case ISD::FPOWI: { 4193 // Promote f32 powi to f64 powi. Note that this could insert a libcall 4194 // directly as well, which may be better. 4195 Tmp1 = PromoteOp(Node->getOperand(0)); 4196 assert(Tmp1.getValueType() == NVT); 4197 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 4198 if (NoExcessFPPrecision) 4199 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4200 DAG.getValueType(VT)); 4201 break; 4202 } 4203 4204 case ISD::ATOMIC_CMP_SWAP: { 4205 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4206 Tmp2 = PromoteOp(Node->getOperand(2)); 4207 Tmp3 = PromoteOp(Node->getOperand(3)); 4208 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 4209 AtomNode->getBasePtr(), Tmp2, Tmp3, 4210 AtomNode->getSrcValue(), 4211 AtomNode->getAlignment()); 4212 // Remember that we legalized the chain. 4213 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4214 break; 4215 } 4216 case ISD::ATOMIC_LOAD_ADD: 4217 case ISD::ATOMIC_LOAD_SUB: 4218 case ISD::ATOMIC_LOAD_AND: 4219 case ISD::ATOMIC_LOAD_OR: 4220 case ISD::ATOMIC_LOAD_XOR: 4221 case ISD::ATOMIC_LOAD_NAND: 4222 case ISD::ATOMIC_LOAD_MIN: 4223 case ISD::ATOMIC_LOAD_MAX: 4224 case ISD::ATOMIC_LOAD_UMIN: 4225 case ISD::ATOMIC_LOAD_UMAX: 4226 case ISD::ATOMIC_SWAP: { 4227 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4228 Tmp2 = PromoteOp(Node->getOperand(2)); 4229 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 4230 AtomNode->getBasePtr(), Tmp2, 4231 AtomNode->getSrcValue(), 4232 AtomNode->getAlignment()); 4233 // Remember that we legalized the chain. 4234 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4235 break; 4236 } 4237 4238 case ISD::AND: 4239 case ISD::OR: 4240 case ISD::XOR: 4241 case ISD::ADD: 4242 case ISD::SUB: 4243 case ISD::MUL: 4244 // The input may have strange things in the top bits of the registers, but 4245 // these operations don't care. They may have weird bits going out, but 4246 // that too is okay if they are integer operations. 4247 Tmp1 = PromoteOp(Node->getOperand(0)); 4248 Tmp2 = PromoteOp(Node->getOperand(1)); 4249 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4250 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4251 break; 4252 case ISD::FADD: 4253 case ISD::FSUB: 4254 case ISD::FMUL: 4255 Tmp1 = PromoteOp(Node->getOperand(0)); 4256 Tmp2 = PromoteOp(Node->getOperand(1)); 4257 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4258 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4259 4260 // Floating point operations will give excess precision that we may not be 4261 // able to tolerate. If we DO allow excess precision, just leave it, 4262 // otherwise excise it. 4263 // FIXME: Why would we need to round FP ops more than integer ones? 4264 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4265 if (NoExcessFPPrecision) 4266 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4267 DAG.getValueType(VT)); 4268 break; 4269 4270 case ISD::SDIV: 4271 case ISD::SREM: 4272 // These operators require that their input be sign extended. 4273 Tmp1 = PromoteOp(Node->getOperand(0)); 4274 Tmp2 = PromoteOp(Node->getOperand(1)); 4275 if (NVT.isInteger()) { 4276 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4277 DAG.getValueType(VT)); 4278 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4279 DAG.getValueType(VT)); 4280 } 4281 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4282 4283 // Perform FP_ROUND: this is probably overly pessimistic. 4284 if (NVT.isFloatingPoint() && NoExcessFPPrecision) 4285 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4286 DAG.getValueType(VT)); 4287 break; 4288 case ISD::FDIV: 4289 case ISD::FREM: 4290 case ISD::FCOPYSIGN: 4291 // These operators require that their input be fp extended. 4292 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4293 case Expand: assert(0 && "not implemented"); 4294 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4295 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4296 } 4297 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4298 case Expand: assert(0 && "not implemented"); 4299 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4300 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4301 } 4302 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4303 4304 // Perform FP_ROUND: this is probably overly pessimistic. 4305 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4306 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4307 DAG.getValueType(VT)); 4308 break; 4309 4310 case ISD::UDIV: 4311 case ISD::UREM: 4312 // These operators require that their input be zero extended. 4313 Tmp1 = PromoteOp(Node->getOperand(0)); 4314 Tmp2 = PromoteOp(Node->getOperand(1)); 4315 assert(NVT.isInteger() && "Operators don't apply to FP!"); 4316 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4317 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4318 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4319 break; 4320 4321 case ISD::SHL: 4322 Tmp1 = PromoteOp(Node->getOperand(0)); 4323 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4324 break; 4325 case ISD::SRA: 4326 // The input value must be properly sign extended. 4327 Tmp1 = PromoteOp(Node->getOperand(0)); 4328 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4329 DAG.getValueType(VT)); 4330 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4331 break; 4332 case ISD::SRL: 4333 // The input value must be properly zero extended. 4334 Tmp1 = PromoteOp(Node->getOperand(0)); 4335 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4336 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4337 break; 4338 4339 case ISD::VAARG: 4340 Tmp1 = Node->getOperand(0); // Get the chain. 4341 Tmp2 = Node->getOperand(1); // Get the pointer. 4342 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4343 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4344 Result = TLI.LowerOperation(Tmp3, DAG); 4345 } else { 4346 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4347 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 4348 // Increment the pointer, VAList, to the next vaarg 4349 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4350 DAG.getConstant(VT.getSizeInBits()/8, 4351 TLI.getPointerTy())); 4352 // Store the incremented VAList to the legalized pointer 4353 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 4354 // Load the actual argument out of the pointer VAList 4355 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4356 } 4357 // Remember that we legalized the chain. 4358 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4359 break; 4360 4361 case ISD::LOAD: { 4362 LoadSDNode *LD = cast<LoadSDNode>(Node); 4363 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4364 ? ISD::EXTLOAD : LD->getExtensionType(); 4365 Result = DAG.getExtLoad(ExtType, NVT, 4366 LD->getChain(), LD->getBasePtr(), 4367 LD->getSrcValue(), LD->getSrcValueOffset(), 4368 LD->getMemoryVT(), 4369 LD->isVolatile(), 4370 LD->getAlignment()); 4371 // Remember that we legalized the chain. 4372 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4373 break; 4374 } 4375 case ISD::SELECT: { 4376 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4377 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4378 4379 MVT VT2 = Tmp2.getValueType(); 4380 assert(VT2 == Tmp3.getValueType() 4381 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); 4382 // Ensure that the resulting node is at least the same size as the operands' 4383 // value types, because we cannot assume that TLI.getSetCCValueType() is 4384 // constant. 4385 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3); 4386 break; 4387 } 4388 case ISD::SELECT_CC: 4389 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4390 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4391 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4392 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4393 break; 4394 case ISD::BSWAP: 4395 Tmp1 = Node->getOperand(0); 4396 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4397 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4398 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4399 DAG.getConstant(NVT.getSizeInBits() - 4400 VT.getSizeInBits(), 4401 TLI.getShiftAmountTy())); 4402 break; 4403 case ISD::CTPOP: 4404 case ISD::CTTZ: 4405 case ISD::CTLZ: 4406 // Zero extend the argument 4407 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4408 // Perform the larger operation, then subtract if needed. 4409 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4410 switch(Node->getOpcode()) { 4411 case ISD::CTPOP: 4412 Result = Tmp1; 4413 break; 4414 case ISD::CTTZ: 4415 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4416 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 4417 DAG.getConstant(NVT.getSizeInBits(), NVT), 4418 ISD::SETEQ); 4419 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4420 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); 4421 break; 4422 case ISD::CTLZ: 4423 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4424 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4425 DAG.getConstant(NVT.getSizeInBits() - 4426 VT.getSizeInBits(), NVT)); 4427 break; 4428 } 4429 break; 4430 case ISD::EXTRACT_SUBVECTOR: 4431 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4432 break; 4433 case ISD::EXTRACT_VECTOR_ELT: 4434 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4435 break; 4436 } 4437 4438 assert(Result.Val && "Didn't set a result!"); 4439 4440 // Make sure the result is itself legal. 4441 Result = LegalizeOp(Result); 4442 4443 // Remember that we promoted this! 4444 AddPromotedOperand(Op, Result); 4445 return Result; 4446} 4447 4448/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4449/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4450/// based on the vector type. The return type of this matches the element type 4451/// of the vector, which may not be legal for the target. 4452SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) { 4453 // We know that operand #0 is the Vec vector. If the index is a constant 4454 // or if the invec is a supported hardware type, we can use it. Otherwise, 4455 // lower to a store then an indexed load. 4456 SDValue Vec = Op.getOperand(0); 4457 SDValue Idx = Op.getOperand(1); 4458 4459 MVT TVT = Vec.getValueType(); 4460 unsigned NumElems = TVT.getVectorNumElements(); 4461 4462 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4463 default: assert(0 && "This action is not supported yet!"); 4464 case TargetLowering::Custom: { 4465 Vec = LegalizeOp(Vec); 4466 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4467 SDValue Tmp3 = TLI.LowerOperation(Op, DAG); 4468 if (Tmp3.Val) 4469 return Tmp3; 4470 break; 4471 } 4472 case TargetLowering::Legal: 4473 if (isTypeLegal(TVT)) { 4474 Vec = LegalizeOp(Vec); 4475 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4476 return Op; 4477 } 4478 break; 4479 case TargetLowering::Expand: 4480 break; 4481 } 4482 4483 if (NumElems == 1) { 4484 // This must be an access of the only element. Return it. 4485 Op = ScalarizeVectorOp(Vec); 4486 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4487 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 4488 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4489 SDValue Lo, Hi; 4490 SplitVectorOp(Vec, Lo, Hi); 4491 if (CIdx->getValue() < NumLoElts) { 4492 Vec = Lo; 4493 } else { 4494 Vec = Hi; 4495 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts, 4496 Idx.getValueType()); 4497 } 4498 4499 // It's now an extract from the appropriate high or low part. Recurse. 4500 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4501 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4502 } else { 4503 // Store the value to a temporary stack slot, then LOAD the scalar 4504 // element back out. 4505 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4506 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4507 4508 // Add the offset to the index. 4509 unsigned EltSize = Op.getValueType().getSizeInBits()/8; 4510 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4511 DAG.getConstant(EltSize, Idx.getValueType())); 4512 4513 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 4514 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4515 else 4516 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4517 4518 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4519 4520 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4521 } 4522 return Op; 4523} 4524 4525/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4526/// we assume the operation can be split if it is not already legal. 4527SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) { 4528 // We know that operand #0 is the Vec vector. For now we assume the index 4529 // is a constant and that the extracted result is a supported hardware type. 4530 SDValue Vec = Op.getOperand(0); 4531 SDValue Idx = LegalizeOp(Op.getOperand(1)); 4532 4533 unsigned NumElems = Vec.getValueType().getVectorNumElements(); 4534 4535 if (NumElems == Op.getValueType().getVectorNumElements()) { 4536 // This must be an access of the desired vector length. Return it. 4537 return Vec; 4538 } 4539 4540 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4541 SDValue Lo, Hi; 4542 SplitVectorOp(Vec, Lo, Hi); 4543 if (CIdx->getValue() < NumElems/2) { 4544 Vec = Lo; 4545 } else { 4546 Vec = Hi; 4547 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4548 } 4549 4550 // It's now an extract from the appropriate high or low part. Recurse. 4551 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4552 return ExpandEXTRACT_SUBVECTOR(Op); 4553} 4554 4555/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4556/// with condition CC on the current target. This usually involves legalizing 4557/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4558/// there may be no choice but to create a new SetCC node to represent the 4559/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4560/// LHS, and the SDValue returned in RHS has a nil SDNode value. 4561void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS, 4562 SDValue &RHS, 4563 SDValue &CC) { 4564 SDValue Tmp1, Tmp2, Tmp3, Result; 4565 4566 switch (getTypeAction(LHS.getValueType())) { 4567 case Legal: 4568 Tmp1 = LegalizeOp(LHS); // LHS 4569 Tmp2 = LegalizeOp(RHS); // RHS 4570 break; 4571 case Promote: 4572 Tmp1 = PromoteOp(LHS); // LHS 4573 Tmp2 = PromoteOp(RHS); // RHS 4574 4575 // If this is an FP compare, the operands have already been extended. 4576 if (LHS.getValueType().isInteger()) { 4577 MVT VT = LHS.getValueType(); 4578 MVT NVT = TLI.getTypeToTransformTo(VT); 4579 4580 // Otherwise, we have to insert explicit sign or zero extends. Note 4581 // that we could insert sign extends for ALL conditions, but zero extend 4582 // is cheaper on many machines (an AND instead of two shifts), so prefer 4583 // it. 4584 switch (cast<CondCodeSDNode>(CC)->get()) { 4585 default: assert(0 && "Unknown integer comparison!"); 4586 case ISD::SETEQ: 4587 case ISD::SETNE: 4588 case ISD::SETUGE: 4589 case ISD::SETUGT: 4590 case ISD::SETULE: 4591 case ISD::SETULT: 4592 // ALL of these operations will work if we either sign or zero extend 4593 // the operands (including the unsigned comparisons!). Zero extend is 4594 // usually a simpler/cheaper operation, so prefer it. 4595 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4596 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4597 break; 4598 case ISD::SETGE: 4599 case ISD::SETGT: 4600 case ISD::SETLT: 4601 case ISD::SETLE: 4602 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4603 DAG.getValueType(VT)); 4604 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4605 DAG.getValueType(VT)); 4606 break; 4607 } 4608 } 4609 break; 4610 case Expand: { 4611 MVT VT = LHS.getValueType(); 4612 if (VT == MVT::f32 || VT == MVT::f64) { 4613 // Expand into one or more soft-fp libcall(s). 4614 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; 4615 switch (cast<CondCodeSDNode>(CC)->get()) { 4616 case ISD::SETEQ: 4617 case ISD::SETOEQ: 4618 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4619 break; 4620 case ISD::SETNE: 4621 case ISD::SETUNE: 4622 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4623 break; 4624 case ISD::SETGE: 4625 case ISD::SETOGE: 4626 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4627 break; 4628 case ISD::SETLT: 4629 case ISD::SETOLT: 4630 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4631 break; 4632 case ISD::SETLE: 4633 case ISD::SETOLE: 4634 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4635 break; 4636 case ISD::SETGT: 4637 case ISD::SETOGT: 4638 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4639 break; 4640 case ISD::SETUO: 4641 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4642 break; 4643 case ISD::SETO: 4644 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4645 break; 4646 default: 4647 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4648 switch (cast<CondCodeSDNode>(CC)->get()) { 4649 case ISD::SETONE: 4650 // SETONE = SETOLT | SETOGT 4651 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4652 // Fallthrough 4653 case ISD::SETUGT: 4654 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4655 break; 4656 case ISD::SETUGE: 4657 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4658 break; 4659 case ISD::SETULT: 4660 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4661 break; 4662 case ISD::SETULE: 4663 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4664 break; 4665 case ISD::SETUEQ: 4666 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4667 break; 4668 default: assert(0 && "Unsupported FP setcc!"); 4669 } 4670 } 4671 4672 SDValue Dummy; 4673 SDValue Ops[2] = { LHS, RHS }; 4674 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val, 4675 false /*sign irrelevant*/, Dummy); 4676 Tmp2 = DAG.getConstant(0, MVT::i32); 4677 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4678 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4679 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 4680 CC); 4681 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val, 4682 false /*sign irrelevant*/, Dummy); 4683 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2, 4684 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4685 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4686 Tmp2 = SDValue(); 4687 } 4688 LHS = LegalizeOp(Tmp1); 4689 RHS = Tmp2; 4690 return; 4691 } 4692 4693 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 4694 ExpandOp(LHS, LHSLo, LHSHi); 4695 ExpandOp(RHS, RHSLo, RHSHi); 4696 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4697 4698 if (VT==MVT::ppcf128) { 4699 // FIXME: This generated code sucks. We want to generate 4700 // FCMP crN, hi1, hi2 4701 // BNE crN, L: 4702 // FCMP crN, lo1, lo2 4703 // The following can be improved, but not that much. 4704 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ); 4705 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode); 4706 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4707 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE); 4708 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode); 4709 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4710 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4711 Tmp2 = SDValue(); 4712 break; 4713 } 4714 4715 switch (CCCode) { 4716 case ISD::SETEQ: 4717 case ISD::SETNE: 4718 if (RHSLo == RHSHi) 4719 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4720 if (RHSCST->isAllOnesValue()) { 4721 // Comparison to -1. 4722 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4723 Tmp2 = RHSLo; 4724 break; 4725 } 4726 4727 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4728 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4729 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4730 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4731 break; 4732 default: 4733 // If this is a comparison of the sign bit, just look at the top part. 4734 // X > -1, x < 0 4735 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4736 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4737 CST->isNullValue()) || // X < 0 4738 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4739 CST->isAllOnesValue())) { // X > -1 4740 Tmp1 = LHSHi; 4741 Tmp2 = RHSHi; 4742 break; 4743 } 4744 4745 // FIXME: This generated code sucks. 4746 ISD::CondCode LowCC; 4747 switch (CCCode) { 4748 default: assert(0 && "Unknown integer setcc!"); 4749 case ISD::SETLT: 4750 case ISD::SETULT: LowCC = ISD::SETULT; break; 4751 case ISD::SETGT: 4752 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4753 case ISD::SETLE: 4754 case ISD::SETULE: LowCC = ISD::SETULE; break; 4755 case ISD::SETGE: 4756 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4757 } 4758 4759 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4760 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4761 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4762 4763 // NOTE: on targets without efficient SELECT of bools, we can always use 4764 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4765 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4766 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, 4767 LowCC, false, DagCombineInfo); 4768 if (!Tmp1.Val) 4769 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 4770 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4771 CCCode, false, DagCombineInfo); 4772 if (!Tmp2.Val) 4773 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, 4774 RHSHi,CC); 4775 4776 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4777 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4778 if ((Tmp1C && Tmp1C->isNullValue()) || 4779 (Tmp2C && Tmp2C->isNullValue() && 4780 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4781 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4782 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 4783 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4784 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4785 // low part is known false, returns high part. 4786 // For LE / GE, if high part is known false, ignore the low part. 4787 // For LT / GT, if high part is known true, ignore the low part. 4788 Tmp1 = Tmp2; 4789 Tmp2 = SDValue(); 4790 } else { 4791 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4792 ISD::SETEQ, false, DagCombineInfo); 4793 if (!Result.Val) 4794 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4795 ISD::SETEQ); 4796 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4797 Result, Tmp1, Tmp2)); 4798 Tmp1 = Result; 4799 Tmp2 = SDValue(); 4800 } 4801 } 4802 } 4803 } 4804 LHS = Tmp1; 4805 RHS = Tmp2; 4806} 4807 4808/// EmitStackConvert - Emit a store/load combination to the stack. This stores 4809/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 4810/// a load from the stack slot to DestVT, extending it if needed. 4811/// The resultant code need not be legal. 4812SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 4813 MVT SlotVT, 4814 MVT DestVT) { 4815 // Create the stack frame object. 4816 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment( 4817 SrcOp.getValueType().getTypeForMVT()); 4818 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 4819 4820 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 4821 int SPFI = StackPtrFI->getIndex(); 4822 4823 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 4824 unsigned SlotSize = SlotVT.getSizeInBits(); 4825 unsigned DestSize = DestVT.getSizeInBits(); 4826 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment( 4827 DestVT.getTypeForMVT()); 4828 4829 // Emit a store to the stack slot. Use a truncstore if the input value is 4830 // later than DestVT. 4831 SDValue Store; 4832 4833 if (SrcSize > SlotSize) 4834 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, 4835 PseudoSourceValue::getFixedStack(SPFI), 0, 4836 SlotVT, false, SrcAlign); 4837 else { 4838 assert(SrcSize == SlotSize && "Invalid store"); 4839 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, 4840 PseudoSourceValue::getFixedStack(SPFI), 0, 4841 false, SrcAlign); 4842 } 4843 4844 // Result is a load from the stack slot. 4845 if (SlotSize == DestSize) 4846 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign); 4847 4848 assert(SlotSize < DestSize && "Unknown extension!"); 4849 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT, 4850 false, DestAlign); 4851} 4852 4853SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4854 // Create a vector sized/aligned stack slot, store the value to element #0, 4855 // then load the whole vector back out. 4856 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4857 4858 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 4859 int SPFI = StackPtrFI->getIndex(); 4860 4861 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4862 PseudoSourceValue::getFixedStack(SPFI), 0); 4863 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, 4864 PseudoSourceValue::getFixedStack(SPFI), 0); 4865} 4866 4867 4868/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4869/// support the operation, but do support the resultant vector type. 4870SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4871 4872 // If the only non-undef value is the low element, turn this into a 4873 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4874 unsigned NumElems = Node->getNumOperands(); 4875 bool isOnlyLowElement = true; 4876 SDValue SplatValue = Node->getOperand(0); 4877 4878 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t> 4879 // and use a bitmask instead of a list of elements. 4880 std::map<SDValue, std::vector<unsigned> > Values; 4881 Values[SplatValue].push_back(0); 4882 bool isConstant = true; 4883 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4884 SplatValue.getOpcode() != ISD::UNDEF) 4885 isConstant = false; 4886 4887 for (unsigned i = 1; i < NumElems; ++i) { 4888 SDValue V = Node->getOperand(i); 4889 Values[V].push_back(i); 4890 if (V.getOpcode() != ISD::UNDEF) 4891 isOnlyLowElement = false; 4892 if (SplatValue != V) 4893 SplatValue = SDValue(0,0); 4894 4895 // If this isn't a constant element or an undef, we can't use a constant 4896 // pool load. 4897 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4898 V.getOpcode() != ISD::UNDEF) 4899 isConstant = false; 4900 } 4901 4902 if (isOnlyLowElement) { 4903 // If the low element is an undef too, then this whole things is an undef. 4904 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4905 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4906 // Otherwise, turn this into a scalar_to_vector node. 4907 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4908 Node->getOperand(0)); 4909 } 4910 4911 // If all elements are constants, create a load from the constant pool. 4912 if (isConstant) { 4913 MVT VT = Node->getValueType(0); 4914 std::vector<Constant*> CV; 4915 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4916 if (ConstantFPSDNode *V = 4917 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4918 CV.push_back(ConstantFP::get(V->getValueAPF())); 4919 } else if (ConstantSDNode *V = 4920 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4921 CV.push_back(ConstantInt::get(V->getAPIntValue())); 4922 } else { 4923 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4924 const Type *OpNTy = 4925 Node->getOperand(0).getValueType().getTypeForMVT(); 4926 CV.push_back(UndefValue::get(OpNTy)); 4927 } 4928 } 4929 Constant *CP = ConstantVector::get(CV); 4930 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4931 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4932 PseudoSourceValue::getConstantPool(), 0); 4933 } 4934 4935 if (SplatValue.Val) { // Splat of one value? 4936 // Build the shuffle constant vector: <0, 0, 0, 0> 4937 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 4938 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); 4939 std::vector<SDValue> ZeroVec(NumElems, Zero); 4940 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4941 &ZeroVec[0], ZeroVec.size()); 4942 4943 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4944 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 4945 // Get the splatted value into the low element of a vector register. 4946 SDValue LowValVec = 4947 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 4948 4949 // Return shuffle(LowValVec, undef, <0,0,0,0>) 4950 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 4951 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 4952 SplatMask); 4953 } 4954 } 4955 4956 // If there are only two unique elements, we may be able to turn this into a 4957 // vector shuffle. 4958 if (Values.size() == 2) { 4959 // Get the two values in deterministic order. 4960 SDValue Val1 = Node->getOperand(1); 4961 SDValue Val2; 4962 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin(); 4963 if (MI->first != Val1) 4964 Val2 = MI->first; 4965 else 4966 Val2 = (++MI)->first; 4967 4968 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our 4969 // vector shuffle has the undef vector on the RHS. 4970 if (Val1.getOpcode() == ISD::UNDEF) 4971 std::swap(Val1, Val2); 4972 4973 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 4974 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 4975 MVT MaskEltVT = MaskVT.getVectorElementType(); 4976 std::vector<SDValue> MaskVec(NumElems); 4977 4978 // Set elements of the shuffle mask for Val1. 4979 std::vector<unsigned> &Val1Elts = Values[Val1]; 4980 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 4981 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT); 4982 4983 // Set elements of the shuffle mask for Val2. 4984 std::vector<unsigned> &Val2Elts = Values[Val2]; 4985 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 4986 if (Val2.getOpcode() != ISD::UNDEF) 4987 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); 4988 else 4989 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); 4990 4991 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4992 &MaskVec[0], MaskVec.size()); 4993 4994 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 4995 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 4996 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 4997 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); 4998 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); 4999 SDValue Ops[] = { Val1, Val2, ShuffleMask }; 5000 5001 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 5002 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); 5003 } 5004 } 5005 5006 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5007 // aligned object on the stack, store each element into it, then load 5008 // the result as a vector. 5009 MVT VT = Node->getValueType(0); 5010 // Create the stack frame object. 5011 SDValue FIPtr = DAG.CreateStackTemporary(VT); 5012 5013 // Emit a store of each element to the stack slot. 5014 SmallVector<SDValue, 8> Stores; 5015 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8; 5016 // Store (in the right endianness) the elements to memory. 5017 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5018 // Ignore undef elements. 5019 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5020 5021 unsigned Offset = TypeByteSize*i; 5022 5023 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5024 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 5025 5026 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 5027 NULL, 0)); 5028 } 5029 5030 SDValue StoreChain; 5031 if (!Stores.empty()) // Not all undef elements? 5032 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5033 &Stores[0], Stores.size()); 5034 else 5035 StoreChain = DAG.getEntryNode(); 5036 5037 // Result is a load from the stack slot. 5038 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 5039} 5040 5041void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5042 SDValue Op, SDValue Amt, 5043 SDValue &Lo, SDValue &Hi) { 5044 // Expand the subcomponents. 5045 SDValue LHSL, LHSH; 5046 ExpandOp(Op, LHSL, LHSH); 5047 5048 SDValue Ops[] = { LHSL, LHSH, Amt }; 5049 MVT VT = LHSL.getValueType(); 5050 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5051 Hi = Lo.getValue(1); 5052} 5053 5054 5055/// ExpandShift - Try to find a clever way to expand this shift operation out to 5056/// smaller elements. If we can't find a way that is more efficient than a 5057/// libcall on this target, return false. Otherwise, return true with the 5058/// low-parts expanded into Lo and Hi. 5059bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, 5060 SDValue &Lo, SDValue &Hi) { 5061 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5062 "This is not a shift!"); 5063 5064 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5065 SDValue ShAmt = LegalizeOp(Amt); 5066 MVT ShTy = ShAmt.getValueType(); 5067 unsigned ShBits = ShTy.getSizeInBits(); 5068 unsigned VTBits = Op.getValueType().getSizeInBits(); 5069 unsigned NVTBits = NVT.getSizeInBits(); 5070 5071 // Handle the case when Amt is an immediate. 5072 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 5073 unsigned Cst = CN->getValue(); 5074 // Expand the incoming operand to be shifted, so that we have its parts 5075 SDValue InL, InH; 5076 ExpandOp(Op, InL, InH); 5077 switch(Opc) { 5078 case ISD::SHL: 5079 if (Cst > VTBits) { 5080 Lo = DAG.getConstant(0, NVT); 5081 Hi = DAG.getConstant(0, NVT); 5082 } else if (Cst > NVTBits) { 5083 Lo = DAG.getConstant(0, NVT); 5084 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5085 } else if (Cst == NVTBits) { 5086 Lo = DAG.getConstant(0, NVT); 5087 Hi = InL; 5088 } else { 5089 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 5090 Hi = DAG.getNode(ISD::OR, NVT, 5091 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 5092 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 5093 } 5094 return true; 5095 case ISD::SRL: 5096 if (Cst > VTBits) { 5097 Lo = DAG.getConstant(0, NVT); 5098 Hi = DAG.getConstant(0, NVT); 5099 } else if (Cst > NVTBits) { 5100 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5101 Hi = DAG.getConstant(0, NVT); 5102 } else if (Cst == NVTBits) { 5103 Lo = InH; 5104 Hi = DAG.getConstant(0, NVT); 5105 } else { 5106 Lo = DAG.getNode(ISD::OR, NVT, 5107 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5108 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5109 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 5110 } 5111 return true; 5112 case ISD::SRA: 5113 if (Cst > VTBits) { 5114 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 5115 DAG.getConstant(NVTBits-1, ShTy)); 5116 } else if (Cst > NVTBits) { 5117 Lo = DAG.getNode(ISD::SRA, NVT, InH, 5118 DAG.getConstant(Cst-NVTBits, ShTy)); 5119 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5120 DAG.getConstant(NVTBits-1, ShTy)); 5121 } else if (Cst == NVTBits) { 5122 Lo = InH; 5123 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5124 DAG.getConstant(NVTBits-1, ShTy)); 5125 } else { 5126 Lo = DAG.getNode(ISD::OR, NVT, 5127 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5128 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5129 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 5130 } 5131 return true; 5132 } 5133 } 5134 5135 // Okay, the shift amount isn't constant. However, if we can tell that it is 5136 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5137 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5138 APInt KnownZero, KnownOne; 5139 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5140 5141 // If we know that if any of the high bits of the shift amount are one, then 5142 // we can do this as a couple of simple shifts. 5143 if (KnownOne.intersects(Mask)) { 5144 // Mask out the high bit, which we know is set. 5145 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 5146 DAG.getConstant(~Mask, Amt.getValueType())); 5147 5148 // Expand the incoming operand to be shifted, so that we have its parts 5149 SDValue InL, InH; 5150 ExpandOp(Op, InL, InH); 5151 switch(Opc) { 5152 case ISD::SHL: 5153 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5154 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 5155 return true; 5156 case ISD::SRL: 5157 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5158 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 5159 return true; 5160 case ISD::SRA: 5161 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 5162 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5163 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 5164 return true; 5165 } 5166 } 5167 5168 // If we know that the high bits of the shift amount are all zero, then we can 5169 // do this as a couple of simple shifts. 5170 if ((KnownZero & Mask) == Mask) { 5171 // Compute 32-amt. 5172 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 5173 DAG.getConstant(NVTBits, Amt.getValueType()), 5174 Amt); 5175 5176 // Expand the incoming operand to be shifted, so that we have its parts 5177 SDValue InL, InH; 5178 ExpandOp(Op, InL, InH); 5179 switch(Opc) { 5180 case ISD::SHL: 5181 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 5182 Hi = DAG.getNode(ISD::OR, NVT, 5183 DAG.getNode(ISD::SHL, NVT, InH, Amt), 5184 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 5185 return true; 5186 case ISD::SRL: 5187 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 5188 Lo = DAG.getNode(ISD::OR, NVT, 5189 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5190 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5191 return true; 5192 case ISD::SRA: 5193 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 5194 Lo = DAG.getNode(ISD::OR, NVT, 5195 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5196 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5197 return true; 5198 } 5199 } 5200 5201 return false; 5202} 5203 5204 5205// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5206// does not fit into a register, return the lo part and set the hi part to the 5207// by-reg argument. If it does fit into a single register, return the result 5208// and leave the Hi part unset. 5209SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 5210 bool isSigned, SDValue &Hi) { 5211 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5212 // The input chain to this libcall is the entry node of the function. 5213 // Legalizing the call will automatically add the previous call to the 5214 // dependence. 5215 SDValue InChain = DAG.getEntryNode(); 5216 5217 TargetLowering::ArgListTy Args; 5218 TargetLowering::ArgListEntry Entry; 5219 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5220 MVT ArgVT = Node->getOperand(i).getValueType(); 5221 const Type *ArgTy = ArgVT.getTypeForMVT(); 5222 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5223 Entry.isSExt = isSigned; 5224 Entry.isZExt = !isSigned; 5225 Args.push_back(Entry); 5226 } 5227 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 5228 TLI.getPointerTy()); 5229 5230 // Splice the libcall in wherever FindInputOutputChains tells us to. 5231 const Type *RetTy = Node->getValueType(0).getTypeForMVT(); 5232 std::pair<SDValue,SDValue> CallInfo = 5233 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C, 5234 false, Callee, Args, DAG); 5235 5236 // Legalize the call sequence, starting with the chain. This will advance 5237 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5238 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5239 LegalizeOp(CallInfo.second); 5240 SDValue Result; 5241 switch (getTypeAction(CallInfo.first.getValueType())) { 5242 default: assert(0 && "Unknown thing"); 5243 case Legal: 5244 Result = CallInfo.first; 5245 break; 5246 case Expand: 5247 ExpandOp(CallInfo.first, Result, Hi); 5248 break; 5249 } 5250 return Result; 5251} 5252 5253 5254/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5255/// 5256SDValue SelectionDAGLegalize:: 5257ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) { 5258 MVT SourceVT = Source.getValueType(); 5259 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5260 5261 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. 5262 if (!isSigned && SourceVT != MVT::i32) { 5263 // The integer value loaded will be incorrectly if the 'sign bit' of the 5264 // incoming integer is set. To handle this, we dynamically test to see if 5265 // it is set, and, if so, add a fudge factor. 5266 SDValue Hi; 5267 if (ExpandSource) { 5268 SDValue Lo; 5269 ExpandOp(Source, Lo, Hi); 5270 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi); 5271 } else { 5272 // The comparison for the sign bit will use the entire operand. 5273 Hi = Source; 5274 } 5275 5276 // If this is unsigned, and not supported, first perform the conversion to 5277 // signed, then adjust the result if the sign bit is set. 5278 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source); 5279 5280 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 5281 DAG.getConstant(0, Hi.getValueType()), 5282 ISD::SETLT); 5283 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5284 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5285 SignSet, Four, Zero); 5286 uint64_t FF = 0x5f800000ULL; 5287 if (TLI.isLittleEndian()) FF <<= 32; 5288 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5289 5290 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5291 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5292 SDValue FudgeInReg; 5293 if (DestTy == MVT::f32) 5294 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5295 PseudoSourceValue::getConstantPool(), 0); 5296 else if (DestTy.bitsGT(MVT::f32)) 5297 // FIXME: Avoid the extend by construction the right constantpool? 5298 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5299 CPIdx, 5300 PseudoSourceValue::getConstantPool(), 0, 5301 MVT::f32); 5302 else 5303 assert(0 && "Unexpected conversion"); 5304 5305 MVT SCVT = SignedConv.getValueType(); 5306 if (SCVT != DestTy) { 5307 // Destination type needs to be expanded as well. The FADD now we are 5308 // constructing will be expanded into a libcall. 5309 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { 5310 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); 5311 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, 5312 SignedConv, SignedConv.getValue(1)); 5313 } 5314 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5315 } 5316 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5317 } 5318 5319 // Check to see if the target has a custom way to lower this. If so, use it. 5320 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 5321 default: assert(0 && "This action not implemented for this operation!"); 5322 case TargetLowering::Legal: 5323 case TargetLowering::Expand: 5324 break; // This case is handled below. 5325 case TargetLowering::Custom: { 5326 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5327 Source), DAG); 5328 if (NV.Val) 5329 return LegalizeOp(NV); 5330 break; // The target decided this was legal after all 5331 } 5332 } 5333 5334 // Expand the source, then glue it back together for the call. We must expand 5335 // the source in case it is shared (this pass of legalize must traverse it). 5336 if (ExpandSource) { 5337 SDValue SrcLo, SrcHi; 5338 ExpandOp(Source, SrcLo, SrcHi); 5339 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); 5340 } 5341 5342 RTLIB::Libcall LC = isSigned ? 5343 RTLIB::getSINTTOFP(SourceVT, DestTy) : 5344 RTLIB::getUINTTOFP(SourceVT, DestTy); 5345 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type"); 5346 5347 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5348 SDValue HiPart; 5349 SDValue Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart); 5350 if (Result.getValueType() != DestTy && HiPart.Val) 5351 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart); 5352 return Result; 5353} 5354 5355/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5356/// INT_TO_FP operation of the specified operand when the target requests that 5357/// we expand it. At this point, we know that the result and operand types are 5358/// legal for the target. 5359SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5360 SDValue Op0, 5361 MVT DestVT) { 5362 if (Op0.getValueType() == MVT::i32) { 5363 // simple 32-bit [signed|unsigned] integer to float/double expansion 5364 5365 // Get the stack frame index of a 8 byte buffer. 5366 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 5367 5368 // word offset constant for Hi/Lo address computation 5369 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5370 // set up Hi and Lo (into buffer) address based on endian 5371 SDValue Hi = StackSlot; 5372 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5373 if (TLI.isLittleEndian()) 5374 std::swap(Hi, Lo); 5375 5376 // if signed map to unsigned space 5377 SDValue Op0Mapped; 5378 if (isSigned) { 5379 // constant used to invert sign bit (signed to unsigned mapping) 5380 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5381 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5382 } else { 5383 Op0Mapped = Op0; 5384 } 5385 // store the lo of the constructed double - based on integer input 5386 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), 5387 Op0Mapped, Lo, NULL, 0); 5388 // initial hi portion of constructed double 5389 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5390 // store the hi of the constructed double - biased exponent 5391 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5392 // load the constructed double 5393 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5394 // FP constant to bias correct the final result 5395 SDValue Bias = DAG.getConstantFP(isSigned ? 5396 BitsToDouble(0x4330000080000000ULL) 5397 : BitsToDouble(0x4330000000000000ULL), 5398 MVT::f64); 5399 // subtract the bias 5400 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5401 // final result 5402 SDValue Result; 5403 // handle final rounding 5404 if (DestVT == MVT::f64) { 5405 // do nothing 5406 Result = Sub; 5407 } else if (DestVT.bitsLT(MVT::f64)) { 5408 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 5409 DAG.getIntPtrConstant(0)); 5410 } else if (DestVT.bitsGT(MVT::f64)) { 5411 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5412 } 5413 return Result; 5414 } 5415 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5416 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5417 5418 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0, 5419 DAG.getConstant(0, Op0.getValueType()), 5420 ISD::SETLT); 5421 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5422 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5423 SignSet, Four, Zero); 5424 5425 // If the sign bit of the integer is set, the large number will be treated 5426 // as a negative number. To counteract this, the dynamic code adds an 5427 // offset depending on the data type. 5428 uint64_t FF; 5429 switch (Op0.getValueType().getSimpleVT()) { 5430 default: assert(0 && "Unsupported integer type!"); 5431 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5432 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5433 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5434 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5435 } 5436 if (TLI.isLittleEndian()) FF <<= 32; 5437 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5438 5439 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5440 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5441 SDValue FudgeInReg; 5442 if (DestVT == MVT::f32) 5443 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5444 PseudoSourceValue::getConstantPool(), 0); 5445 else { 5446 FudgeInReg = 5447 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5448 DAG.getEntryNode(), CPIdx, 5449 PseudoSourceValue::getConstantPool(), 0, 5450 MVT::f32)); 5451 } 5452 5453 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5454} 5455 5456/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5457/// *INT_TO_FP operation of the specified operand when the target requests that 5458/// we promote it. At this point, we know that the result and operand types are 5459/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5460/// operation that takes a larger input. 5461SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 5462 MVT DestVT, 5463 bool isSigned) { 5464 // First step, figure out the appropriate *INT_TO_FP operation to use. 5465 MVT NewInTy = LegalOp.getValueType(); 5466 5467 unsigned OpToUse = 0; 5468 5469 // Scan for the appropriate larger type to use. 5470 while (1) { 5471 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 5472 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 5473 5474 // If the target supports SINT_TO_FP of this type, use it. 5475 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5476 default: break; 5477 case TargetLowering::Legal: 5478 if (!TLI.isTypeLegal(NewInTy)) 5479 break; // Can't use this datatype. 5480 // FALL THROUGH. 5481 case TargetLowering::Custom: 5482 OpToUse = ISD::SINT_TO_FP; 5483 break; 5484 } 5485 if (OpToUse) break; 5486 if (isSigned) continue; 5487 5488 // If the target supports UINT_TO_FP of this type, use it. 5489 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5490 default: break; 5491 case TargetLowering::Legal: 5492 if (!TLI.isTypeLegal(NewInTy)) 5493 break; // Can't use this datatype. 5494 // FALL THROUGH. 5495 case TargetLowering::Custom: 5496 OpToUse = ISD::UINT_TO_FP; 5497 break; 5498 } 5499 if (OpToUse) break; 5500 5501 // Otherwise, try a larger type. 5502 } 5503 5504 // Okay, we found the operation and type to use. Zero extend our input to the 5505 // desired type then run the operation on it. 5506 return DAG.getNode(OpToUse, DestVT, 5507 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5508 NewInTy, LegalOp)); 5509} 5510 5511/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5512/// FP_TO_*INT operation of the specified operand when the target requests that 5513/// we promote it. At this point, we know that the result and operand types are 5514/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5515/// operation that returns a larger result. 5516SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 5517 MVT DestVT, 5518 bool isSigned) { 5519 // First step, figure out the appropriate FP_TO*INT operation to use. 5520 MVT NewOutTy = DestVT; 5521 5522 unsigned OpToUse = 0; 5523 5524 // Scan for the appropriate larger type to use. 5525 while (1) { 5526 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 5527 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 5528 5529 // If the target supports FP_TO_SINT returning this type, use it. 5530 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5531 default: break; 5532 case TargetLowering::Legal: 5533 if (!TLI.isTypeLegal(NewOutTy)) 5534 break; // Can't use this datatype. 5535 // FALL THROUGH. 5536 case TargetLowering::Custom: 5537 OpToUse = ISD::FP_TO_SINT; 5538 break; 5539 } 5540 if (OpToUse) break; 5541 5542 // If the target supports FP_TO_UINT of this type, use it. 5543 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5544 default: break; 5545 case TargetLowering::Legal: 5546 if (!TLI.isTypeLegal(NewOutTy)) 5547 break; // Can't use this datatype. 5548 // FALL THROUGH. 5549 case TargetLowering::Custom: 5550 OpToUse = ISD::FP_TO_UINT; 5551 break; 5552 } 5553 if (OpToUse) break; 5554 5555 // Otherwise, try a larger type. 5556 } 5557 5558 5559 // Okay, we found the operation and type to use. 5560 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5561 5562 // If the operation produces an invalid type, it must be custom lowered. Use 5563 // the target lowering hooks to expand it. Just keep the low part of the 5564 // expanded operation, we know that we're truncating anyway. 5565 if (getTypeAction(NewOutTy) == Expand) { 5566 Operation = SDValue(TLI.ReplaceNodeResults(Operation.Val, DAG), 0); 5567 assert(Operation.Val && "Didn't return anything"); 5568 } 5569 5570 // Truncate the result of the extended FP_TO_*INT operation to the desired 5571 // size. 5572 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5573} 5574 5575/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5576/// 5577SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) { 5578 MVT VT = Op.getValueType(); 5579 MVT SHVT = TLI.getShiftAmountTy(); 5580 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5581 switch (VT.getSimpleVT()) { 5582 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5583 case MVT::i16: 5584 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5585 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5586 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5587 case MVT::i32: 5588 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5589 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5590 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5591 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5592 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5593 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5594 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5595 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5596 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5597 case MVT::i64: 5598 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5599 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5600 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5601 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5602 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5603 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5604 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5605 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5606 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5607 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5608 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5609 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5610 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5611 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5612 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5613 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5614 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5615 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5616 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5617 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5618 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5619 } 5620} 5621 5622/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5623/// 5624SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) { 5625 switch (Opc) { 5626 default: assert(0 && "Cannot expand this yet!"); 5627 case ISD::CTPOP: { 5628 static const uint64_t mask[6] = { 5629 0x5555555555555555ULL, 0x3333333333333333ULL, 5630 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5631 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5632 }; 5633 MVT VT = Op.getValueType(); 5634 MVT ShVT = TLI.getShiftAmountTy(); 5635 unsigned len = VT.getSizeInBits(); 5636 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5637 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5638 SDValue Tmp2 = DAG.getConstant(mask[i], VT); 5639 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5640 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5641 DAG.getNode(ISD::AND, VT, 5642 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5643 } 5644 return Op; 5645 } 5646 case ISD::CTLZ: { 5647 // for now, we do this: 5648 // x = x | (x >> 1); 5649 // x = x | (x >> 2); 5650 // ... 5651 // x = x | (x >>16); 5652 // x = x | (x >>32); // for 64-bit input 5653 // return popcount(~x); 5654 // 5655 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5656 MVT VT = Op.getValueType(); 5657 MVT ShVT = TLI.getShiftAmountTy(); 5658 unsigned len = VT.getSizeInBits(); 5659 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5660 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5661 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5662 } 5663 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5664 return DAG.getNode(ISD::CTPOP, VT, Op); 5665 } 5666 case ISD::CTTZ: { 5667 // for now, we use: { return popcount(~x & (x - 1)); } 5668 // unless the target has ctlz but not ctpop, in which case we use: 5669 // { return 32 - nlz(~x & (x-1)); } 5670 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5671 MVT VT = Op.getValueType(); 5672 SDValue Tmp2 = DAG.getConstant(~0ULL, VT); 5673 SDValue Tmp3 = DAG.getNode(ISD::AND, VT, 5674 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5675 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5676 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5677 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5678 TLI.isOperationLegal(ISD::CTLZ, VT)) 5679 return DAG.getNode(ISD::SUB, VT, 5680 DAG.getConstant(VT.getSizeInBits(), VT), 5681 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5682 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5683 } 5684 } 5685} 5686 5687/// ExpandOp - Expand the specified SDValue into its two component pieces 5688/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5689/// LegalizeNodes map is filled in for any results that are not expanded, the 5690/// ExpandedNodes map is filled in for any results that are expanded, and the 5691/// Lo/Hi values are returned. 5692void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){ 5693 MVT VT = Op.getValueType(); 5694 MVT NVT = TLI.getTypeToTransformTo(VT); 5695 SDNode *Node = Op.Val; 5696 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5697 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() || 5698 VT.isVector()) && "Cannot expand to FP value or to larger int value!"); 5699 5700 // See if we already expanded it. 5701 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I 5702 = ExpandedNodes.find(Op); 5703 if (I != ExpandedNodes.end()) { 5704 Lo = I->second.first; 5705 Hi = I->second.second; 5706 return; 5707 } 5708 5709 switch (Node->getOpcode()) { 5710 case ISD::CopyFromReg: 5711 assert(0 && "CopyFromReg must be legal!"); 5712 case ISD::FP_ROUND_INREG: 5713 if (VT == MVT::ppcf128 && 5714 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5715 TargetLowering::Custom) { 5716 SDValue SrcLo, SrcHi, Src; 5717 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5718 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5719 SDValue Result = TLI.LowerOperation( 5720 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5721 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5722 Lo = Result.Val->getOperand(0); 5723 Hi = Result.Val->getOperand(1); 5724 break; 5725 } 5726 // fall through 5727 default: 5728#ifndef NDEBUG 5729 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5730#endif 5731 assert(0 && "Do not know how to expand this operator!"); 5732 abort(); 5733 case ISD::EXTRACT_ELEMENT: 5734 ExpandOp(Node->getOperand(0), Lo, Hi); 5735 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 5736 return ExpandOp(Hi, Lo, Hi); 5737 return ExpandOp(Lo, Lo, Hi); 5738 case ISD::EXTRACT_VECTOR_ELT: 5739 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5740 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5741 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5742 return ExpandOp(Lo, Lo, Hi); 5743 case ISD::UNDEF: 5744 Lo = DAG.getNode(ISD::UNDEF, NVT); 5745 Hi = DAG.getNode(ISD::UNDEF, NVT); 5746 break; 5747 case ISD::Constant: { 5748 unsigned NVTBits = NVT.getSizeInBits(); 5749 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 5750 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 5751 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 5752 break; 5753 } 5754 case ISD::ConstantFP: { 5755 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5756 if (CFP->getValueType(0) == MVT::ppcf128) { 5757 APInt api = CFP->getValueAPF().convertToAPInt(); 5758 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5759 MVT::f64); 5760 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5761 MVT::f64); 5762 break; 5763 } 5764 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5765 if (getTypeAction(Lo.getValueType()) == Expand) 5766 ExpandOp(Lo, Lo, Hi); 5767 break; 5768 } 5769 case ISD::BUILD_PAIR: 5770 // Return the operands. 5771 Lo = Node->getOperand(0); 5772 Hi = Node->getOperand(1); 5773 break; 5774 5775 case ISD::MERGE_VALUES: 5776 if (Node->getNumValues() == 1) { 5777 ExpandOp(Op.getOperand(0), Lo, Hi); 5778 break; 5779 } 5780 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5781 assert(Op.ResNo == 0 && Node->getNumValues() == 2 && 5782 Op.getValue(1).getValueType() == MVT::Other && 5783 "unhandled MERGE_VALUES"); 5784 ExpandOp(Op.getOperand(0), Lo, Hi); 5785 // Remember that we legalized the chain. 5786 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5787 break; 5788 5789 case ISD::SIGN_EXTEND_INREG: 5790 ExpandOp(Node->getOperand(0), Lo, Hi); 5791 // sext_inreg the low part if needed. 5792 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5793 5794 // The high part gets the sign extension from the lo-part. This handles 5795 // things like sextinreg V:i64 from i8. 5796 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5797 DAG.getConstant(NVT.getSizeInBits()-1, 5798 TLI.getShiftAmountTy())); 5799 break; 5800 5801 case ISD::BSWAP: { 5802 ExpandOp(Node->getOperand(0), Lo, Hi); 5803 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5804 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5805 Lo = TempLo; 5806 break; 5807 } 5808 5809 case ISD::CTPOP: 5810 ExpandOp(Node->getOperand(0), Lo, Hi); 5811 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5812 DAG.getNode(ISD::CTPOP, NVT, Lo), 5813 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5814 Hi = DAG.getConstant(0, NVT); 5815 break; 5816 5817 case ISD::CTLZ: { 5818 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5819 ExpandOp(Node->getOperand(0), Lo, Hi); 5820 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 5821 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5822 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC, 5823 ISD::SETNE); 5824 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5825 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5826 5827 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5828 Hi = DAG.getConstant(0, NVT); 5829 break; 5830 } 5831 5832 case ISD::CTTZ: { 5833 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5834 ExpandOp(Node->getOperand(0), Lo, Hi); 5835 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 5836 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5837 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC, 5838 ISD::SETNE); 5839 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5840 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5841 5842 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5843 Hi = DAG.getConstant(0, NVT); 5844 break; 5845 } 5846 5847 case ISD::VAARG: { 5848 SDValue Ch = Node->getOperand(0); // Legalize the chain. 5849 SDValue Ptr = Node->getOperand(1); // Legalize the pointer. 5850 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5851 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5852 5853 // Remember that we legalized the chain. 5854 Hi = LegalizeOp(Hi); 5855 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5856 if (TLI.isBigEndian()) 5857 std::swap(Lo, Hi); 5858 break; 5859 } 5860 5861 case ISD::LOAD: { 5862 LoadSDNode *LD = cast<LoadSDNode>(Node); 5863 SDValue Ch = LD->getChain(); // Legalize the chain. 5864 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer. 5865 ISD::LoadExtType ExtType = LD->getExtensionType(); 5866 int SVOffset = LD->getSrcValueOffset(); 5867 unsigned Alignment = LD->getAlignment(); 5868 bool isVolatile = LD->isVolatile(); 5869 5870 if (ExtType == ISD::NON_EXTLOAD) { 5871 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5872 isVolatile, Alignment); 5873 if (VT == MVT::f32 || VT == MVT::f64) { 5874 // f32->i32 or f64->i64 one to one expansion. 5875 // Remember that we legalized the chain. 5876 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 5877 // Recursively expand the new load. 5878 if (getTypeAction(NVT) == Expand) 5879 ExpandOp(Lo, Lo, Hi); 5880 break; 5881 } 5882 5883 // Increment the pointer to the other half. 5884 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; 5885 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5886 DAG.getIntPtrConstant(IncrementSize)); 5887 SVOffset += IncrementSize; 5888 Alignment = MinAlign(Alignment, IncrementSize); 5889 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5890 isVolatile, Alignment); 5891 5892 // Build a factor node to remember that this load is independent of the 5893 // other one. 5894 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5895 Hi.getValue(1)); 5896 5897 // Remember that we legalized the chain. 5898 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5899 if (TLI.isBigEndian()) 5900 std::swap(Lo, Hi); 5901 } else { 5902 MVT EVT = LD->getMemoryVT(); 5903 5904 if ((VT == MVT::f64 && EVT == MVT::f32) || 5905 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 5906 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5907 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5908 SVOffset, isVolatile, Alignment); 5909 // Remember that we legalized the chain. 5910 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1))); 5911 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 5912 break; 5913 } 5914 5915 if (EVT == NVT) 5916 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 5917 SVOffset, isVolatile, Alignment); 5918 else 5919 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 5920 SVOffset, EVT, isVolatile, 5921 Alignment); 5922 5923 // Remember that we legalized the chain. 5924 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 5925 5926 if (ExtType == ISD::SEXTLOAD) { 5927 // The high part is obtained by SRA'ing all but one of the bits of the 5928 // lo part. 5929 unsigned LoSize = Lo.getValueType().getSizeInBits(); 5930 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5931 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5932 } else if (ExtType == ISD::ZEXTLOAD) { 5933 // The high part is just a zero. 5934 Hi = DAG.getConstant(0, NVT); 5935 } else /* if (ExtType == ISD::EXTLOAD) */ { 5936 // The high part is undefined. 5937 Hi = DAG.getNode(ISD::UNDEF, NVT); 5938 } 5939 } 5940 break; 5941 } 5942 case ISD::AND: 5943 case ISD::OR: 5944 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 5945 SDValue LL, LH, RL, RH; 5946 ExpandOp(Node->getOperand(0), LL, LH); 5947 ExpandOp(Node->getOperand(1), RL, RH); 5948 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 5949 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 5950 break; 5951 } 5952 case ISD::SELECT: { 5953 SDValue LL, LH, RL, RH; 5954 ExpandOp(Node->getOperand(1), LL, LH); 5955 ExpandOp(Node->getOperand(2), RL, RH); 5956 if (getTypeAction(NVT) == Expand) 5957 NVT = TLI.getTypeToExpandTo(NVT); 5958 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 5959 if (VT != MVT::f32) 5960 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 5961 break; 5962 } 5963 case ISD::SELECT_CC: { 5964 SDValue TL, TH, FL, FH; 5965 ExpandOp(Node->getOperand(2), TL, TH); 5966 ExpandOp(Node->getOperand(3), FL, FH); 5967 if (getTypeAction(NVT) == Expand) 5968 NVT = TLI.getTypeToExpandTo(NVT); 5969 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5970 Node->getOperand(1), TL, FL, Node->getOperand(4)); 5971 if (VT != MVT::f32) 5972 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5973 Node->getOperand(1), TH, FH, Node->getOperand(4)); 5974 break; 5975 } 5976 case ISD::ANY_EXTEND: 5977 // The low part is any extension of the input (which degenerates to a copy). 5978 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 5979 // The high part is undefined. 5980 Hi = DAG.getNode(ISD::UNDEF, NVT); 5981 break; 5982 case ISD::SIGN_EXTEND: { 5983 // The low part is just a sign extension of the input (which degenerates to 5984 // a copy). 5985 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 5986 5987 // The high part is obtained by SRA'ing all but one of the bits of the lo 5988 // part. 5989 unsigned LoSize = Lo.getValueType().getSizeInBits(); 5990 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5991 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5992 break; 5993 } 5994 case ISD::ZERO_EXTEND: 5995 // The low part is just a zero extension of the input (which degenerates to 5996 // a copy). 5997 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 5998 5999 // The high part is just a zero. 6000 Hi = DAG.getConstant(0, NVT); 6001 break; 6002 6003 case ISD::TRUNCATE: { 6004 // The input value must be larger than this value. Expand *it*. 6005 SDValue NewLo; 6006 ExpandOp(Node->getOperand(0), NewLo, Hi); 6007 6008 // The low part is now either the right size, or it is closer. If not the 6009 // right size, make an illegal truncate so we recursively expand it. 6010 if (NewLo.getValueType() != Node->getValueType(0)) 6011 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 6012 ExpandOp(NewLo, Lo, Hi); 6013 break; 6014 } 6015 6016 case ISD::BIT_CONVERT: { 6017 SDValue Tmp; 6018 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6019 // If the target wants to, allow it to lower this itself. 6020 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6021 case Expand: assert(0 && "cannot expand FP!"); 6022 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6023 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6024 } 6025 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 6026 } 6027 6028 // f32 / f64 must be expanded to i32 / i64. 6029 if (VT == MVT::f32 || VT == MVT::f64) { 6030 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6031 if (getTypeAction(NVT) == Expand) 6032 ExpandOp(Lo, Lo, Hi); 6033 break; 6034 } 6035 6036 // If source operand will be expanded to the same type as VT, i.e. 6037 // i64 <- f64, i32 <- f32, expand the source operand instead. 6038 MVT VT0 = Node->getOperand(0).getValueType(); 6039 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6040 ExpandOp(Node->getOperand(0), Lo, Hi); 6041 break; 6042 } 6043 6044 // Turn this into a load/store pair by default. 6045 if (Tmp.Val == 0) 6046 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 6047 6048 ExpandOp(Tmp, Lo, Hi); 6049 break; 6050 } 6051 6052 case ISD::READCYCLECOUNTER: { 6053 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6054 TargetLowering::Custom && 6055 "Must custom expand ReadCycleCounter"); 6056 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6057 assert(Tmp.Val && "Node must be custom expanded!"); 6058 ExpandOp(Tmp.getValue(0), Lo, Hi); 6059 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6060 LegalizeOp(Tmp.getValue(1))); 6061 break; 6062 } 6063 6064 case ISD::ATOMIC_CMP_SWAP: { 6065 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6066 assert(Tmp.Val && "Node must be custom expanded!"); 6067 ExpandOp(Tmp.getValue(0), Lo, Hi); 6068 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6069 LegalizeOp(Tmp.getValue(1))); 6070 break; 6071 } 6072 6073 6074 6075 // These operators cannot be expanded directly, emit them as calls to 6076 // library functions. 6077 case ISD::FP_TO_SINT: { 6078 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6079 SDValue Op; 6080 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6081 case Expand: assert(0 && "cannot expand FP!"); 6082 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6083 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6084 } 6085 6086 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 6087 6088 // Now that the custom expander is done, expand the result, which is still 6089 // VT. 6090 if (Op.Val) { 6091 ExpandOp(Op, Lo, Hi); 6092 break; 6093 } 6094 } 6095 6096 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(), 6097 VT); 6098 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!"); 6099 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6100 break; 6101 } 6102 6103 case ISD::FP_TO_UINT: { 6104 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6105 SDValue Op; 6106 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6107 case Expand: assert(0 && "cannot expand FP!"); 6108 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6109 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6110 } 6111 6112 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 6113 6114 // Now that the custom expander is done, expand the result. 6115 if (Op.Val) { 6116 ExpandOp(Op, Lo, Hi); 6117 break; 6118 } 6119 } 6120 6121 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(), 6122 VT); 6123 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 6124 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6125 break; 6126 } 6127 6128 case ISD::SHL: { 6129 // If the target wants custom lowering, do so. 6130 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6131 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6132 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 6133 Op = TLI.LowerOperation(Op, DAG); 6134 if (Op.Val) { 6135 // Now that the custom expander is done, expand the result, which is 6136 // still VT. 6137 ExpandOp(Op, Lo, Hi); 6138 break; 6139 } 6140 } 6141 6142 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6143 // this X << 1 as X+X. 6144 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6145 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 6146 TLI.isOperationLegal(ISD::ADDE, NVT)) { 6147 SDValue LoOps[2], HiOps[3]; 6148 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6149 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6150 LoOps[1] = LoOps[0]; 6151 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6152 6153 HiOps[1] = HiOps[0]; 6154 HiOps[2] = Lo.getValue(1); 6155 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6156 break; 6157 } 6158 } 6159 6160 // If we can emit an efficient shift operation, do so now. 6161 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6162 break; 6163 6164 // If this target supports SHL_PARTS, use it. 6165 TargetLowering::LegalizeAction Action = 6166 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6167 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6168 Action == TargetLowering::Custom) { 6169 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6170 break; 6171 } 6172 6173 // Otherwise, emit a libcall. 6174 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi); 6175 break; 6176 } 6177 6178 case ISD::SRA: { 6179 // If the target wants custom lowering, do so. 6180 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6181 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6182 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6183 Op = TLI.LowerOperation(Op, DAG); 6184 if (Op.Val) { 6185 // Now that the custom expander is done, expand the result, which is 6186 // still VT. 6187 ExpandOp(Op, Lo, Hi); 6188 break; 6189 } 6190 } 6191 6192 // If we can emit an efficient shift operation, do so now. 6193 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6194 break; 6195 6196 // If this target supports SRA_PARTS, use it. 6197 TargetLowering::LegalizeAction Action = 6198 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6199 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6200 Action == TargetLowering::Custom) { 6201 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6202 break; 6203 } 6204 6205 // Otherwise, emit a libcall. 6206 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi); 6207 break; 6208 } 6209 6210 case ISD::SRL: { 6211 // If the target wants custom lowering, do so. 6212 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6213 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6214 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 6215 Op = TLI.LowerOperation(Op, DAG); 6216 if (Op.Val) { 6217 // Now that the custom expander is done, expand the result, which is 6218 // still VT. 6219 ExpandOp(Op, Lo, Hi); 6220 break; 6221 } 6222 } 6223 6224 // If we can emit an efficient shift operation, do so now. 6225 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6226 break; 6227 6228 // If this target supports SRL_PARTS, use it. 6229 TargetLowering::LegalizeAction Action = 6230 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6231 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6232 Action == TargetLowering::Custom) { 6233 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6234 break; 6235 } 6236 6237 // Otherwise, emit a libcall. 6238 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi); 6239 break; 6240 } 6241 6242 case ISD::ADD: 6243 case ISD::SUB: { 6244 // If the target wants to custom expand this, let them. 6245 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6246 TargetLowering::Custom) { 6247 SDValue Result = TLI.LowerOperation(Op, DAG); 6248 if (Result.Val) { 6249 ExpandOp(Result, Lo, Hi); 6250 break; 6251 } 6252 } 6253 6254 // Expand the subcomponents. 6255 SDValue LHSL, LHSH, RHSL, RHSH; 6256 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6257 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6258 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6259 SDValue LoOps[2], HiOps[3]; 6260 LoOps[0] = LHSL; 6261 LoOps[1] = RHSL; 6262 HiOps[0] = LHSH; 6263 HiOps[1] = RHSH; 6264 if (Node->getOpcode() == ISD::ADD) { 6265 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6266 HiOps[2] = Lo.getValue(1); 6267 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6268 } else { 6269 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6270 HiOps[2] = Lo.getValue(1); 6271 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6272 } 6273 break; 6274 } 6275 6276 case ISD::ADDC: 6277 case ISD::SUBC: { 6278 // Expand the subcomponents. 6279 SDValue LHSL, LHSH, RHSL, RHSH; 6280 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6281 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6282 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6283 SDValue LoOps[2] = { LHSL, RHSL }; 6284 SDValue HiOps[3] = { LHSH, RHSH }; 6285 6286 if (Node->getOpcode() == ISD::ADDC) { 6287 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6288 HiOps[2] = Lo.getValue(1); 6289 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6290 } else { 6291 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6292 HiOps[2] = Lo.getValue(1); 6293 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6294 } 6295 // Remember that we legalized the flag. 6296 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6297 break; 6298 } 6299 case ISD::ADDE: 6300 case ISD::SUBE: { 6301 // Expand the subcomponents. 6302 SDValue LHSL, LHSH, RHSL, RHSH; 6303 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6304 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6305 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6306 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 6307 SDValue HiOps[3] = { LHSH, RHSH }; 6308 6309 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 6310 HiOps[2] = Lo.getValue(1); 6311 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 6312 6313 // Remember that we legalized the flag. 6314 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6315 break; 6316 } 6317 case ISD::MUL: { 6318 // If the target wants to custom expand this, let them. 6319 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 6320 SDValue New = TLI.LowerOperation(Op, DAG); 6321 if (New.Val) { 6322 ExpandOp(New, Lo, Hi); 6323 break; 6324 } 6325 } 6326 6327 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 6328 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 6329 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 6330 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 6331 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 6332 SDValue LL, LH, RL, RH; 6333 ExpandOp(Node->getOperand(0), LL, LH); 6334 ExpandOp(Node->getOperand(1), RL, RH); 6335 unsigned OuterBitSize = Op.getValueSizeInBits(); 6336 unsigned InnerBitSize = RH.getValueSizeInBits(); 6337 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 6338 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 6339 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 6340 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 6341 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 6342 // The inputs are both zero-extended. 6343 if (HasUMUL_LOHI) { 6344 // We can emit a umul_lohi. 6345 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6346 Hi = SDValue(Lo.Val, 1); 6347 break; 6348 } 6349 if (HasMULHU) { 6350 // We can emit a mulhu+mul. 6351 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6352 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6353 break; 6354 } 6355 } 6356 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 6357 // The input values are both sign-extended. 6358 if (HasSMUL_LOHI) { 6359 // We can emit a smul_lohi. 6360 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6361 Hi = SDValue(Lo.Val, 1); 6362 break; 6363 } 6364 if (HasMULHS) { 6365 // We can emit a mulhs+mul. 6366 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6367 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6368 break; 6369 } 6370 } 6371 if (HasUMUL_LOHI) { 6372 // Lo,Hi = umul LHS, RHS. 6373 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6374 DAG.getVTList(NVT, NVT), LL, RL); 6375 Lo = UMulLOHI; 6376 Hi = UMulLOHI.getValue(1); 6377 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6378 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6379 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6380 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6381 break; 6382 } 6383 if (HasMULHU) { 6384 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6385 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6386 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6387 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6388 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6389 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6390 break; 6391 } 6392 } 6393 6394 // If nothing else, we can make a libcall. 6395 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi); 6396 break; 6397 } 6398 case ISD::SDIV: 6399 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi); 6400 break; 6401 case ISD::UDIV: 6402 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi); 6403 break; 6404 case ISD::SREM: 6405 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi); 6406 break; 6407 case ISD::UREM: 6408 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi); 6409 break; 6410 6411 case ISD::FADD: 6412 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32, 6413 RTLIB::ADD_F64, 6414 RTLIB::ADD_F80, 6415 RTLIB::ADD_PPCF128), 6416 Node, false, Hi); 6417 break; 6418 case ISD::FSUB: 6419 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32, 6420 RTLIB::SUB_F64, 6421 RTLIB::SUB_F80, 6422 RTLIB::SUB_PPCF128), 6423 Node, false, Hi); 6424 break; 6425 case ISD::FMUL: 6426 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32, 6427 RTLIB::MUL_F64, 6428 RTLIB::MUL_F80, 6429 RTLIB::MUL_PPCF128), 6430 Node, false, Hi); 6431 break; 6432 case ISD::FDIV: 6433 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32, 6434 RTLIB::DIV_F64, 6435 RTLIB::DIV_F80, 6436 RTLIB::DIV_PPCF128), 6437 Node, false, Hi); 6438 break; 6439 case ISD::FP_EXTEND: { 6440 if (VT == MVT::ppcf128) { 6441 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6442 Node->getOperand(0).getValueType()==MVT::f64); 6443 const uint64_t zero = 0; 6444 if (Node->getOperand(0).getValueType()==MVT::f32) 6445 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6446 else 6447 Hi = Node->getOperand(0); 6448 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6449 break; 6450 } 6451 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT); 6452 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!"); 6453 Lo = ExpandLibCall(LC, Node, true, Hi); 6454 break; 6455 } 6456 case ISD::FP_ROUND: { 6457 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(), 6458 VT); 6459 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!"); 6460 Lo = ExpandLibCall(LC, Node, true, Hi); 6461 break; 6462 } 6463 case ISD::FPOWI: 6464 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32, 6465 RTLIB::POWI_F64, 6466 RTLIB::POWI_F80, 6467 RTLIB::POWI_PPCF128), 6468 Node, false, Hi); 6469 break; 6470 case ISD::FSQRT: 6471 case ISD::FSIN: 6472 case ISD::FCOS: { 6473 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6474 switch(Node->getOpcode()) { 6475 case ISD::FSQRT: 6476 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 6477 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 6478 break; 6479 case ISD::FSIN: 6480 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 6481 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 6482 break; 6483 case ISD::FCOS: 6484 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 6485 RTLIB::COS_F80, RTLIB::COS_PPCF128); 6486 break; 6487 default: assert(0 && "Unreachable!"); 6488 } 6489 Lo = ExpandLibCall(LC, Node, false, Hi); 6490 break; 6491 } 6492 case ISD::FABS: { 6493 if (VT == MVT::ppcf128) { 6494 SDValue Tmp; 6495 ExpandOp(Node->getOperand(0), Lo, Tmp); 6496 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6497 // lo = hi==fabs(hi) ? lo : -lo; 6498 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6499 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6500 DAG.getCondCode(ISD::SETEQ)); 6501 break; 6502 } 6503 SDValue Mask = (VT == MVT::f64) 6504 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6505 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6506 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6507 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6508 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6509 if (getTypeAction(NVT) == Expand) 6510 ExpandOp(Lo, Lo, Hi); 6511 break; 6512 } 6513 case ISD::FNEG: { 6514 if (VT == MVT::ppcf128) { 6515 ExpandOp(Node->getOperand(0), Lo, Hi); 6516 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6517 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6518 break; 6519 } 6520 SDValue Mask = (VT == MVT::f64) 6521 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6522 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6523 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6524 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6525 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6526 if (getTypeAction(NVT) == Expand) 6527 ExpandOp(Lo, Lo, Hi); 6528 break; 6529 } 6530 case ISD::FCOPYSIGN: { 6531 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6532 if (getTypeAction(NVT) == Expand) 6533 ExpandOp(Lo, Lo, Hi); 6534 break; 6535 } 6536 case ISD::SINT_TO_FP: 6537 case ISD::UINT_TO_FP: { 6538 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6539 MVT SrcVT = Node->getOperand(0).getValueType(); 6540 6541 // Promote the operand if needed. Do this before checking for 6542 // ppcf128 so conversions of i16 and i8 work. 6543 if (getTypeAction(SrcVT) == Promote) { 6544 SDValue Tmp = PromoteOp(Node->getOperand(0)); 6545 Tmp = isSigned 6546 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6547 DAG.getValueType(SrcVT)) 6548 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6549 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6550 SrcVT = Node->getOperand(0).getValueType(); 6551 } 6552 6553 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 6554 static const uint64_t zero = 0; 6555 if (isSigned) { 6556 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6557 Node->getOperand(0))); 6558 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6559 } else { 6560 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6561 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6562 Node->getOperand(0))); 6563 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6564 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6565 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6566 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6567 DAG.getConstant(0, MVT::i32), 6568 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6569 DAG.getConstantFP( 6570 APFloat(APInt(128, 2, TwoE32)), 6571 MVT::ppcf128)), 6572 Hi, 6573 DAG.getCondCode(ISD::SETLT)), 6574 Lo, Hi); 6575 } 6576 break; 6577 } 6578 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6579 // si64->ppcf128 done by libcall, below 6580 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6581 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6582 Lo, Hi); 6583 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6584 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6585 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6586 DAG.getConstant(0, MVT::i64), 6587 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6588 DAG.getConstantFP( 6589 APFloat(APInt(128, 2, TwoE64)), 6590 MVT::ppcf128)), 6591 Hi, 6592 DAG.getCondCode(ISD::SETLT)), 6593 Lo, Hi); 6594 break; 6595 } 6596 6597 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6598 Node->getOperand(0)); 6599 if (getTypeAction(Lo.getValueType()) == Expand) 6600 // float to i32 etc. can be 'expanded' to a single node. 6601 ExpandOp(Lo, Lo, Hi); 6602 break; 6603 } 6604 } 6605 6606 // Make sure the resultant values have been legalized themselves, unless this 6607 // is a type that requires multi-step expansion. 6608 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6609 Lo = LegalizeOp(Lo); 6610 if (Hi.Val) 6611 // Don't legalize the high part if it is expanded to a single node. 6612 Hi = LegalizeOp(Hi); 6613 } 6614 6615 // Remember in a map if the values will be reused later. 6616 bool isNew = 6617 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 6618 assert(isNew && "Value already expanded?!?"); 6619} 6620 6621/// SplitVectorOp - Given an operand of vector type, break it down into 6622/// two smaller values, still of vector type. 6623void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo, 6624 SDValue &Hi) { 6625 assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); 6626 SDNode *Node = Op.Val; 6627 unsigned NumElements = Op.getValueType().getVectorNumElements(); 6628 assert(NumElements > 1 && "Cannot split a single element vector!"); 6629 6630 MVT NewEltVT = Op.getValueType().getVectorElementType(); 6631 6632 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6633 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6634 6635 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); 6636 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); 6637 6638 // See if we already split it. 6639 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I 6640 = SplitNodes.find(Op); 6641 if (I != SplitNodes.end()) { 6642 Lo = I->second.first; 6643 Hi = I->second.second; 6644 return; 6645 } 6646 6647 switch (Node->getOpcode()) { 6648 default: 6649#ifndef NDEBUG 6650 Node->dump(&DAG); 6651#endif 6652 assert(0 && "Unhandled operation in SplitVectorOp!"); 6653 case ISD::UNDEF: 6654 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6655 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6656 break; 6657 case ISD::BUILD_PAIR: 6658 Lo = Node->getOperand(0); 6659 Hi = Node->getOperand(1); 6660 break; 6661 case ISD::INSERT_VECTOR_ELT: { 6662 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 6663 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6664 unsigned Index = Idx->getValue(); 6665 SDValue ScalarOp = Node->getOperand(1); 6666 if (Index < NewNumElts_Lo) 6667 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6668 DAG.getIntPtrConstant(Index)); 6669 else 6670 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6671 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 6672 break; 6673 } 6674 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), 6675 Node->getOperand(1), 6676 Node->getOperand(2)); 6677 SplitVectorOp(Tmp, Lo, Hi); 6678 break; 6679 } 6680 case ISD::VECTOR_SHUFFLE: { 6681 // Build the low part. 6682 SDValue Mask = Node->getOperand(2); 6683 SmallVector<SDValue, 8> Ops; 6684 MVT PtrVT = TLI.getPointerTy(); 6685 6686 // Insert all of the elements from the input that are needed. We use 6687 // buildvector of extractelement here because the input vectors will have 6688 // to be legalized, so this makes the code simpler. 6689 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 6690 SDValue IdxNode = Mask.getOperand(i); 6691 if (IdxNode.getOpcode() == ISD::UNDEF) { 6692 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6693 continue; 6694 } 6695 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6696 SDValue InVec = Node->getOperand(0); 6697 if (Idx >= NumElements) { 6698 InVec = Node->getOperand(1); 6699 Idx -= NumElements; 6700 } 6701 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6702 DAG.getConstant(Idx, PtrVT))); 6703 } 6704 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6705 Ops.clear(); 6706 6707 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 6708 SDValue IdxNode = Mask.getOperand(i); 6709 if (IdxNode.getOpcode() == ISD::UNDEF) { 6710 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6711 continue; 6712 } 6713 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6714 SDValue InVec = Node->getOperand(0); 6715 if (Idx >= NumElements) { 6716 InVec = Node->getOperand(1); 6717 Idx -= NumElements; 6718 } 6719 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6720 DAG.getConstant(Idx, PtrVT))); 6721 } 6722 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size()); 6723 break; 6724 } 6725 case ISD::BUILD_VECTOR: { 6726 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 6727 Node->op_begin()+NewNumElts_Lo); 6728 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 6729 6730 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 6731 Node->op_end()); 6732 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 6733 break; 6734 } 6735 case ISD::CONCAT_VECTORS: { 6736 // FIXME: Handle non-power-of-two vectors? 6737 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6738 if (NewNumSubvectors == 1) { 6739 Lo = Node->getOperand(0); 6740 Hi = Node->getOperand(1); 6741 } else { 6742 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 6743 Node->op_begin()+NewNumSubvectors); 6744 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 6745 6746 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6747 Node->op_end()); 6748 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 6749 } 6750 break; 6751 } 6752 case ISD::SELECT: { 6753 SDValue Cond = Node->getOperand(0); 6754 6755 SDValue LL, LH, RL, RH; 6756 SplitVectorOp(Node->getOperand(1), LL, LH); 6757 SplitVectorOp(Node->getOperand(2), RL, RH); 6758 6759 if (Cond.getValueType().isVector()) { 6760 // Handle a vector merge. 6761 SDValue CL, CH; 6762 SplitVectorOp(Cond, CL, CH); 6763 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 6764 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 6765 } else { 6766 // Handle a simple select with vector operands. 6767 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 6768 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 6769 } 6770 break; 6771 } 6772 case ISD::SELECT_CC: { 6773 SDValue CondLHS = Node->getOperand(0); 6774 SDValue CondRHS = Node->getOperand(1); 6775 SDValue CondCode = Node->getOperand(4); 6776 6777 SDValue LL, LH, RL, RH; 6778 SplitVectorOp(Node->getOperand(2), LL, LH); 6779 SplitVectorOp(Node->getOperand(3), RL, RH); 6780 6781 // Handle a simple select with vector operands. 6782 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS, 6783 LL, RL, CondCode); 6784 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS, 6785 LH, RH, CondCode); 6786 break; 6787 } 6788 case ISD::VSETCC: { 6789 SDValue LL, LH, RL, RH; 6790 SplitVectorOp(Node->getOperand(0), LL, LH); 6791 SplitVectorOp(Node->getOperand(1), RL, RH); 6792 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2)); 6793 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2)); 6794 break; 6795 } 6796 case ISD::ADD: 6797 case ISD::SUB: 6798 case ISD::MUL: 6799 case ISD::FADD: 6800 case ISD::FSUB: 6801 case ISD::FMUL: 6802 case ISD::SDIV: 6803 case ISD::UDIV: 6804 case ISD::FDIV: 6805 case ISD::FPOW: 6806 case ISD::AND: 6807 case ISD::OR: 6808 case ISD::XOR: 6809 case ISD::UREM: 6810 case ISD::SREM: 6811 case ISD::FREM: { 6812 SDValue LL, LH, RL, RH; 6813 SplitVectorOp(Node->getOperand(0), LL, LH); 6814 SplitVectorOp(Node->getOperand(1), RL, RH); 6815 6816 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 6817 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 6818 break; 6819 } 6820 case ISD::FPOWI: { 6821 SDValue L, H; 6822 SplitVectorOp(Node->getOperand(0), L, H); 6823 6824 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 6825 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 6826 break; 6827 } 6828 case ISD::CTTZ: 6829 case ISD::CTLZ: 6830 case ISD::CTPOP: 6831 case ISD::FNEG: 6832 case ISD::FABS: 6833 case ISD::FSQRT: 6834 case ISD::FSIN: 6835 case ISD::FCOS: 6836 case ISD::FP_TO_SINT: 6837 case ISD::FP_TO_UINT: 6838 case ISD::SINT_TO_FP: 6839 case ISD::UINT_TO_FP: { 6840 SDValue L, H; 6841 SplitVectorOp(Node->getOperand(0), L, H); 6842 6843 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 6844 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 6845 break; 6846 } 6847 case ISD::LOAD: { 6848 LoadSDNode *LD = cast<LoadSDNode>(Node); 6849 SDValue Ch = LD->getChain(); 6850 SDValue Ptr = LD->getBasePtr(); 6851 const Value *SV = LD->getSrcValue(); 6852 int SVOffset = LD->getSrcValueOffset(); 6853 unsigned Alignment = LD->getAlignment(); 6854 bool isVolatile = LD->isVolatile(); 6855 6856 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6857 unsigned IncrementSize = NewNumElts_Lo * NewEltVT.getSizeInBits()/8; 6858 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6859 DAG.getIntPtrConstant(IncrementSize)); 6860 SVOffset += IncrementSize; 6861 Alignment = MinAlign(Alignment, IncrementSize); 6862 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6863 6864 // Build a factor node to remember that this load is independent of the 6865 // other one. 6866 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6867 Hi.getValue(1)); 6868 6869 // Remember that we legalized the chain. 6870 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6871 break; 6872 } 6873 case ISD::BIT_CONVERT: { 6874 // We know the result is a vector. The input may be either a vector or a 6875 // scalar value. 6876 SDValue InOp = Node->getOperand(0); 6877 if (!InOp.getValueType().isVector() || 6878 InOp.getValueType().getVectorNumElements() == 1) { 6879 // The input is a scalar or single-element vector. 6880 // Lower to a store/load so that it can be split. 6881 // FIXME: this could be improved probably. 6882 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment( 6883 Op.getValueType().getTypeForMVT()); 6884 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign); 6885 int FI = cast<FrameIndexSDNode>(Ptr.Val)->getIndex(); 6886 6887 SDValue St = DAG.getStore(DAG.getEntryNode(), 6888 InOp, Ptr, 6889 PseudoSourceValue::getFixedStack(FI), 0); 6890 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, 6891 PseudoSourceValue::getFixedStack(FI), 0); 6892 } 6893 // Split the vector and convert each of the pieces now. 6894 SplitVectorOp(InOp, Lo, Hi); 6895 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 6896 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 6897 break; 6898 } 6899 } 6900 6901 // Remember in a map if the values will be reused later. 6902 bool isNew = 6903 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 6904 assert(isNew && "Value already split?!?"); 6905} 6906 6907 6908/// ScalarizeVectorOp - Given an operand of single-element vector type 6909/// (e.g. v1f32), convert it into the equivalent operation that returns a 6910/// scalar (e.g. f32) value. 6911SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) { 6912 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); 6913 SDNode *Node = Op.Val; 6914 MVT NewVT = Op.getValueType().getVectorElementType(); 6915 assert(Op.getValueType().getVectorNumElements() == 1); 6916 6917 // See if we already scalarized it. 6918 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op); 6919 if (I != ScalarizedNodes.end()) return I->second; 6920 6921 SDValue Result; 6922 switch (Node->getOpcode()) { 6923 default: 6924#ifndef NDEBUG 6925 Node->dump(&DAG); cerr << "\n"; 6926#endif 6927 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 6928 case ISD::ADD: 6929 case ISD::FADD: 6930 case ISD::SUB: 6931 case ISD::FSUB: 6932 case ISD::MUL: 6933 case ISD::FMUL: 6934 case ISD::SDIV: 6935 case ISD::UDIV: 6936 case ISD::FDIV: 6937 case ISD::SREM: 6938 case ISD::UREM: 6939 case ISD::FREM: 6940 case ISD::FPOW: 6941 case ISD::AND: 6942 case ISD::OR: 6943 case ISD::XOR: 6944 Result = DAG.getNode(Node->getOpcode(), 6945 NewVT, 6946 ScalarizeVectorOp(Node->getOperand(0)), 6947 ScalarizeVectorOp(Node->getOperand(1))); 6948 break; 6949 case ISD::FNEG: 6950 case ISD::FABS: 6951 case ISD::FSQRT: 6952 case ISD::FSIN: 6953 case ISD::FCOS: 6954 Result = DAG.getNode(Node->getOpcode(), 6955 NewVT, 6956 ScalarizeVectorOp(Node->getOperand(0))); 6957 break; 6958 case ISD::FPOWI: 6959 Result = DAG.getNode(Node->getOpcode(), 6960 NewVT, 6961 ScalarizeVectorOp(Node->getOperand(0)), 6962 Node->getOperand(1)); 6963 break; 6964 case ISD::LOAD: { 6965 LoadSDNode *LD = cast<LoadSDNode>(Node); 6966 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 6967 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 6968 6969 const Value *SV = LD->getSrcValue(); 6970 int SVOffset = LD->getSrcValueOffset(); 6971 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 6972 LD->isVolatile(), LD->getAlignment()); 6973 6974 // Remember that we legalized the chain. 6975 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 6976 break; 6977 } 6978 case ISD::BUILD_VECTOR: 6979 Result = Node->getOperand(0); 6980 break; 6981 case ISD::INSERT_VECTOR_ELT: 6982 // Returning the inserted scalar element. 6983 Result = Node->getOperand(1); 6984 break; 6985 case ISD::CONCAT_VECTORS: 6986 assert(Node->getOperand(0).getValueType() == NewVT && 6987 "Concat of non-legal vectors not yet supported!"); 6988 Result = Node->getOperand(0); 6989 break; 6990 case ISD::VECTOR_SHUFFLE: { 6991 // Figure out if the scalar is the LHS or RHS and return it. 6992 SDValue EltNum = Node->getOperand(2).getOperand(0); 6993 if (cast<ConstantSDNode>(EltNum)->getValue()) 6994 Result = ScalarizeVectorOp(Node->getOperand(1)); 6995 else 6996 Result = ScalarizeVectorOp(Node->getOperand(0)); 6997 break; 6998 } 6999 case ISD::EXTRACT_SUBVECTOR: 7000 Result = Node->getOperand(0); 7001 assert(Result.getValueType() == NewVT); 7002 break; 7003 case ISD::BIT_CONVERT: { 7004 SDValue Op0 = Op.getOperand(0); 7005 if (Op0.getValueType().getVectorNumElements() == 1) 7006 Op0 = ScalarizeVectorOp(Op0); 7007 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0); 7008 break; 7009 } 7010 case ISD::SELECT: 7011 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 7012 ScalarizeVectorOp(Op.getOperand(1)), 7013 ScalarizeVectorOp(Op.getOperand(2))); 7014 break; 7015 case ISD::SELECT_CC: 7016 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0), 7017 Node->getOperand(1), 7018 ScalarizeVectorOp(Op.getOperand(2)), 7019 ScalarizeVectorOp(Op.getOperand(3)), 7020 Node->getOperand(4)); 7021 break; 7022 case ISD::VSETCC: { 7023 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0)); 7024 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1)); 7025 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1, 7026 Op.getOperand(2)); 7027 Result = DAG.getNode(ISD::SELECT, NewVT, Result, 7028 DAG.getConstant(-1ULL, NewVT), 7029 DAG.getConstant(0ULL, NewVT)); 7030 break; 7031 } 7032 } 7033 7034 if (TLI.isTypeLegal(NewVT)) 7035 Result = LegalizeOp(Result); 7036 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7037 assert(isNew && "Value already scalarized?"); 7038 return Result; 7039} 7040 7041 7042// SelectionDAG::Legalize - This is the entry point for the file. 7043// 7044void SelectionDAG::Legalize() { 7045 /// run - This is the main entry point to this class. 7046 /// 7047 SelectionDAGLegalize(*this).LegalizeDAG(); 7048} 7049 7050