LegalizeDAG.cpp revision 2cc16e768c63832cfabaf3ba69e0f43a148cdffb
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetFrameInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/Target/TargetSubtarget.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Compiler.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/ADT/DenseMap.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/SmallPtrSet.h" 35#include <map> 36using namespace llvm; 37 38#ifndef NDEBUG 39static cl::opt<bool> 40ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 41 cl::desc("Pop up a window to show dags before legalize")); 42#else 43static const bool ViewLegalizeDAGs = 0; 44#endif 45 46//===----------------------------------------------------------------------===// 47/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 48/// hacks on it until the target machine can handle it. This involves 49/// eliminating value sizes the machine cannot handle (promoting small sizes to 50/// large sizes or splitting up large values into small values) as well as 51/// eliminating operations the machine cannot handle. 52/// 53/// This code also does a small amount of optimization and recognition of idioms 54/// as part of its processing. For example, if a target does not support a 55/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 56/// will attempt merge setcc and brc instructions into brcc's. 57/// 58namespace { 59class VISIBILITY_HIDDEN SelectionDAGLegalize { 60 TargetLowering &TLI; 61 SelectionDAG &DAG; 62 63 // Libcall insertion helpers. 64 65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 66 /// legalized. We use this to ensure that calls are properly serialized 67 /// against each other, including inserted libcalls. 68 SDOperand LastCALLSEQ_END; 69 70 /// IsLegalizingCall - This member is used *only* for purposes of providing 71 /// helpful assertions that a libcall isn't created while another call is 72 /// being legalized (which could lead to non-serialized call sequences). 73 bool IsLegalizingCall; 74 75 enum LegalizeAction { 76 Legal, // The target natively supports this operation. 77 Promote, // This operation should be executed in a larger type. 78 Expand // Try to expand this to other ops, otherwise use a libcall. 79 }; 80 81 /// ValueTypeActions - This is a bitvector that contains two bits for each 82 /// value type, where the two bits correspond to the LegalizeAction enum. 83 /// This can be queried with "getTypeAction(VT)". 84 TargetLowering::ValueTypeActionImpl ValueTypeActions; 85 86 /// LegalizedNodes - For nodes that are of legal width, and that have more 87 /// than one use, this map indicates what regularized operand to use. This 88 /// allows us to avoid legalizing the same thing more than once. 89 DenseMap<SDOperand, SDOperand> LegalizedNodes; 90 91 /// PromotedNodes - For nodes that are below legal width, and that have more 92 /// than one use, this map indicates what promoted value to use. This allows 93 /// us to avoid promoting the same thing more than once. 94 DenseMap<SDOperand, SDOperand> PromotedNodes; 95 96 /// ExpandedNodes - For nodes that need to be expanded this map indicates 97 /// which which operands are the expanded version of the input. This allows 98 /// us to avoid expanding the same node more than once. 99 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 100 101 /// SplitNodes - For vector nodes that need to be split, this map indicates 102 /// which which operands are the split version of the input. This allows us 103 /// to avoid splitting the same node more than once. 104 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 105 106 /// ScalarizedNodes - For nodes that need to be converted from vector types to 107 /// scalar types, this contains the mapping of ones we have already 108 /// processed to the result. 109 std::map<SDOperand, SDOperand> ScalarizedNodes; 110 111 void AddLegalizedOperand(SDOperand From, SDOperand To) { 112 LegalizedNodes.insert(std::make_pair(From, To)); 113 // If someone requests legalization of the new node, return itself. 114 if (From != To) 115 LegalizedNodes.insert(std::make_pair(To, To)); 116 } 117 void AddPromotedOperand(SDOperand From, SDOperand To) { 118 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 119 assert(isNew && "Got into the map somehow?"); 120 // If someone requests legalization of the new node, return itself. 121 LegalizedNodes.insert(std::make_pair(To, To)); 122 } 123 124public: 125 126 SelectionDAGLegalize(SelectionDAG &DAG); 127 128 /// getTypeAction - Return how we should legalize values of this type, either 129 /// it is already legal or we need to expand it into multiple registers of 130 /// smaller integer type, or we need to promote it to a larger type. 131 LegalizeAction getTypeAction(MVT::ValueType VT) const { 132 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 133 } 134 135 /// isTypeLegal - Return true if this type is legal on this target. 136 /// 137 bool isTypeLegal(MVT::ValueType VT) const { 138 return getTypeAction(VT) == Legal; 139 } 140 141 void LegalizeDAG(); 142 143private: 144 /// HandleOp - Legalize, Promote, or Expand the specified operand as 145 /// appropriate for its type. 146 void HandleOp(SDOperand Op); 147 148 /// LegalizeOp - We know that the specified value has a legal type. 149 /// Recursively ensure that the operands have legal types, then return the 150 /// result. 151 SDOperand LegalizeOp(SDOperand O); 152 153 /// UnrollVectorOp - We know that the given vector has a legal type, however 154 /// the operation it performs is not legal and is an operation that we have 155 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 156 /// operating on each element individually. 157 SDOperand UnrollVectorOp(SDOperand O); 158 159 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 160 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 161 /// is necessary to spill the vector being inserted into to memory, perform 162 /// the insert there, and then read the result back. 163 SDOperand PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, 164 SDOperand Idx); 165 166 /// PromoteOp - Given an operation that produces a value in an invalid type, 167 /// promote it to compute the value into a larger type. The produced value 168 /// will have the correct bits for the low portion of the register, but no 169 /// guarantee is made about the top bits: it may be zero, sign-extended, or 170 /// garbage. 171 SDOperand PromoteOp(SDOperand O); 172 173 /// ExpandOp - Expand the specified SDOperand into its two component pieces 174 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 175 /// the LegalizeNodes map is filled in for any results that are not expanded, 176 /// the ExpandedNodes map is filled in for any results that are expanded, and 177 /// the Lo/Hi values are returned. This applies to integer types and Vector 178 /// types. 179 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 180 181 /// SplitVectorOp - Given an operand of vector type, break it down into 182 /// two smaller values. 183 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 184 185 /// ScalarizeVectorOp - Given an operand of single-element vector type 186 /// (e.g. v1f32), convert it into the equivalent operation that returns a 187 /// scalar (e.g. f32) value. 188 SDOperand ScalarizeVectorOp(SDOperand O); 189 190 /// isShuffleLegal - Return true if a vector shuffle is legal with the 191 /// specified mask and type. Targets can specify exactly which masks they 192 /// support and the code generator is tasked with not creating illegal masks. 193 /// 194 /// Note that this will also return true for shuffles that are promoted to a 195 /// different type. 196 /// 197 /// If this is a legal shuffle, this method returns the (possibly promoted) 198 /// build_vector Mask. If it's not a legal shuffle, it returns null. 199 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 200 201 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 202 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 203 204 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 205 206 SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, 207 SDOperand &Hi); 208 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 209 SDOperand Source); 210 211 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT, 212 MVT::ValueType DestVT); 213 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 214 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 215 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 216 SDOperand LegalOp, 217 MVT::ValueType DestVT); 218 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 219 bool isSigned); 220 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 221 bool isSigned); 222 223 SDOperand ExpandBSWAP(SDOperand Op); 224 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 225 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 226 SDOperand &Lo, SDOperand &Hi); 227 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 228 SDOperand &Lo, SDOperand &Hi); 229 230 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 231 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 232}; 233} 234 235/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 236/// specified mask and type. Targets can specify exactly which masks they 237/// support and the code generator is tasked with not creating illegal masks. 238/// 239/// Note that this will also return true for shuffles that are promoted to a 240/// different type. 241SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 242 SDOperand Mask) const { 243 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 244 default: return 0; 245 case TargetLowering::Legal: 246 case TargetLowering::Custom: 247 break; 248 case TargetLowering::Promote: { 249 // If this is promoted to a different type, convert the shuffle mask and 250 // ask if it is legal in the promoted type! 251 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 252 253 // If we changed # elements, change the shuffle mask. 254 unsigned NumEltsGrowth = 255 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 256 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 257 if (NumEltsGrowth > 1) { 258 // Renumber the elements. 259 SmallVector<SDOperand, 8> Ops; 260 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 261 SDOperand InOp = Mask.getOperand(i); 262 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 263 if (InOp.getOpcode() == ISD::UNDEF) 264 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 265 else { 266 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 267 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 268 } 269 } 270 } 271 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 272 } 273 VT = NVT; 274 break; 275 } 276 } 277 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 278} 279 280SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 281 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 282 ValueTypeActions(TLI.getValueTypeActions()) { 283 assert(MVT::LAST_VALUETYPE <= 32 && 284 "Too many value types for ValueTypeActions to hold!"); 285} 286 287/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 288/// contains all of a nodes operands before it contains the node. 289static void ComputeTopDownOrdering(SelectionDAG &DAG, 290 SmallVector<SDNode*, 64> &Order) { 291 292 DenseMap<SDNode*, unsigned> Visited; 293 std::vector<SDNode*> Worklist; 294 Worklist.reserve(128); 295 296 // Compute ordering from all of the leaves in the graphs, those (like the 297 // entry node) that have no operands. 298 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 299 E = DAG.allnodes_end(); I != E; ++I) { 300 if (I->getNumOperands() == 0) { 301 Visited[I] = 0 - 1U; 302 Worklist.push_back(I); 303 } 304 } 305 306 while (!Worklist.empty()) { 307 SDNode *N = Worklist.back(); 308 Worklist.pop_back(); 309 310 if (++Visited[N] != N->getNumOperands()) 311 continue; // Haven't visited all operands yet 312 313 Order.push_back(N); 314 315 // Now that we have N in, add anything that uses it if all of their operands 316 // are now done. 317 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 318 UI != E; ++UI) 319 Worklist.push_back(UI->getUser()); 320 } 321 322 assert(Order.size() == Visited.size() && 323 Order.size() == 324 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 325 "Error: DAG is cyclic!"); 326} 327 328 329void SelectionDAGLegalize::LegalizeDAG() { 330 LastCALLSEQ_END = DAG.getEntryNode(); 331 IsLegalizingCall = false; 332 333 // The legalize process is inherently a bottom-up recursive process (users 334 // legalize their uses before themselves). Given infinite stack space, we 335 // could just start legalizing on the root and traverse the whole graph. In 336 // practice however, this causes us to run out of stack space on large basic 337 // blocks. To avoid this problem, compute an ordering of the nodes where each 338 // node is only legalized after all of its operands are legalized. 339 SmallVector<SDNode*, 64> Order; 340 ComputeTopDownOrdering(DAG, Order); 341 342 for (unsigned i = 0, e = Order.size(); i != e; ++i) 343 HandleOp(SDOperand(Order[i], 0)); 344 345 // Finally, it's possible the root changed. Get the new root. 346 SDOperand OldRoot = DAG.getRoot(); 347 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 348 DAG.setRoot(LegalizedNodes[OldRoot]); 349 350 ExpandedNodes.clear(); 351 LegalizedNodes.clear(); 352 PromotedNodes.clear(); 353 SplitNodes.clear(); 354 ScalarizedNodes.clear(); 355 356 // Remove dead nodes now. 357 DAG.RemoveDeadNodes(); 358} 359 360 361/// FindCallEndFromCallStart - Given a chained node that is part of a call 362/// sequence, find the CALLSEQ_END node that terminates the call sequence. 363static SDNode *FindCallEndFromCallStart(SDNode *Node) { 364 if (Node->getOpcode() == ISD::CALLSEQ_END) 365 return Node; 366 if (Node->use_empty()) 367 return 0; // No CallSeqEnd 368 369 // The chain is usually at the end. 370 SDOperand TheChain(Node, Node->getNumValues()-1); 371 if (TheChain.getValueType() != MVT::Other) { 372 // Sometimes it's at the beginning. 373 TheChain = SDOperand(Node, 0); 374 if (TheChain.getValueType() != MVT::Other) { 375 // Otherwise, hunt for it. 376 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 377 if (Node->getValueType(i) == MVT::Other) { 378 TheChain = SDOperand(Node, i); 379 break; 380 } 381 382 // Otherwise, we walked into a node without a chain. 383 if (TheChain.getValueType() != MVT::Other) 384 return 0; 385 } 386 } 387 388 for (SDNode::use_iterator UI = Node->use_begin(), 389 E = Node->use_end(); UI != E; ++UI) { 390 391 // Make sure to only follow users of our token chain. 392 SDNode *User = UI->getUser(); 393 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 394 if (User->getOperand(i) == TheChain) 395 if (SDNode *Result = FindCallEndFromCallStart(User)) 396 return Result; 397 } 398 return 0; 399} 400 401/// FindCallStartFromCallEnd - Given a chained node that is part of a call 402/// sequence, find the CALLSEQ_START node that initiates the call sequence. 403static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 404 assert(Node && "Didn't find callseq_start for a call??"); 405 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 406 407 assert(Node->getOperand(0).getValueType() == MVT::Other && 408 "Node doesn't have a token chain argument!"); 409 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 410} 411 412/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 413/// see if any uses can reach Dest. If no dest operands can get to dest, 414/// legalize them, legalize ourself, and return false, otherwise, return true. 415/// 416/// Keep track of the nodes we fine that actually do lead to Dest in 417/// NodesLeadingTo. This avoids retraversing them exponential number of times. 418/// 419bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 420 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 421 if (N == Dest) return true; // N certainly leads to Dest :) 422 423 // If we've already processed this node and it does lead to Dest, there is no 424 // need to reprocess it. 425 if (NodesLeadingTo.count(N)) return true; 426 427 // If the first result of this node has been already legalized, then it cannot 428 // reach N. 429 switch (getTypeAction(N->getValueType(0))) { 430 case Legal: 431 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 432 break; 433 case Promote: 434 if (PromotedNodes.count(SDOperand(N, 0))) return false; 435 break; 436 case Expand: 437 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 438 break; 439 } 440 441 // Okay, this node has not already been legalized. Check and legalize all 442 // operands. If none lead to Dest, then we can legalize this node. 443 bool OperandsLeadToDest = false; 444 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 445 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 446 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 447 448 if (OperandsLeadToDest) { 449 NodesLeadingTo.insert(N); 450 return true; 451 } 452 453 // Okay, this node looks safe, legalize it and return false. 454 HandleOp(SDOperand(N, 0)); 455 return false; 456} 457 458/// HandleOp - Legalize, Promote, or Expand the specified operand as 459/// appropriate for its type. 460void SelectionDAGLegalize::HandleOp(SDOperand Op) { 461 MVT::ValueType VT = Op.getValueType(); 462 switch (getTypeAction(VT)) { 463 default: assert(0 && "Bad type action!"); 464 case Legal: (void)LegalizeOp(Op); break; 465 case Promote: (void)PromoteOp(Op); break; 466 case Expand: 467 if (!MVT::isVector(VT)) { 468 // If this is an illegal scalar, expand it into its two component 469 // pieces. 470 SDOperand X, Y; 471 if (Op.getOpcode() == ISD::TargetConstant) 472 break; // Allow illegal target nodes. 473 ExpandOp(Op, X, Y); 474 } else if (MVT::getVectorNumElements(VT) == 1) { 475 // If this is an illegal single element vector, convert it to a 476 // scalar operation. 477 (void)ScalarizeVectorOp(Op); 478 } else { 479 // Otherwise, this is an illegal multiple element vector. 480 // Split it in half and legalize both parts. 481 SDOperand X, Y; 482 SplitVectorOp(Op, X, Y); 483 } 484 break; 485 } 486} 487 488/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 489/// a load from the constant pool. 490static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 491 SelectionDAG &DAG, TargetLowering &TLI) { 492 bool Extend = false; 493 494 // If a FP immediate is precise when represented as a float and if the 495 // target can do an extending load from float to double, we put it into 496 // the constant pool as a float, even if it's is statically typed as a 497 // double. This shrinks FP constants and canonicalizes them for targets where 498 // an FP extending load is the same cost as a normal load (such as on the x87 499 // fp stack or PPC FP unit). 500 MVT::ValueType VT = CFP->getValueType(0); 501 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF()); 502 if (!UseCP) { 503 if (VT!=MVT::f64 && VT!=MVT::f32) 504 assert(0 && "Invalid type expansion"); 505 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(), 506 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 507 } 508 509 MVT::ValueType OrigVT = VT; 510 MVT::ValueType SVT = VT; 511 while (SVT != MVT::f32) { 512 SVT = (unsigned)SVT - 1; 513 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 514 // Only do this if the target has a native EXTLOAD instruction from 515 // smaller type. 516 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) && 517 TLI.ShouldShrinkFPConstant(OrigVT)) { 518 const Type *SType = MVT::getTypeForValueType(SVT); 519 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 520 VT = SVT; 521 Extend = true; 522 } 523 } 524 525 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 526 if (Extend) 527 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), 528 CPIdx, PseudoSourceValue::getConstantPool(), 529 0, VT); 530 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, 531 PseudoSourceValue::getConstantPool(), 0); 532} 533 534 535/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 536/// operations. 537static 538SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 539 SelectionDAG &DAG, TargetLowering &TLI) { 540 MVT::ValueType VT = Node->getValueType(0); 541 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 542 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 543 "fcopysign expansion only supported for f32 and f64"); 544 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 545 546 // First get the sign bit of second operand. 547 SDOperand Mask1 = (SrcVT == MVT::f64) 548 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 549 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 550 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 551 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 552 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 553 // Shift right or sign-extend it if the two operands have different types. 554 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 555 if (SizeDiff > 0) { 556 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 557 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 558 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 559 } else if (SizeDiff < 0) 560 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 561 562 // Clear the sign bit of first operand. 563 SDOperand Mask2 = (VT == MVT::f64) 564 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 565 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 566 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 567 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 568 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 569 570 // Or the value with the sign bit. 571 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 572 return Result; 573} 574 575/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 576static 577SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 578 TargetLowering &TLI) { 579 SDOperand Chain = ST->getChain(); 580 SDOperand Ptr = ST->getBasePtr(); 581 SDOperand Val = ST->getValue(); 582 MVT::ValueType VT = Val.getValueType(); 583 int Alignment = ST->getAlignment(); 584 int SVOffset = ST->getSrcValueOffset(); 585 if (MVT::isFloatingPoint(ST->getMemoryVT()) || 586 MVT::isVector(ST->getMemoryVT())) { 587 // Expand to a bitconvert of the value to the integer type of the 588 // same size, then a (misaligned) int store. 589 MVT::ValueType intVT; 590 if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128) 591 intVT = MVT::i128; 592 else if (MVT::is64BitVector(VT) || VT==MVT::f64) 593 intVT = MVT::i64; 594 else if (VT==MVT::f32) 595 intVT = MVT::i32; 596 else 597 assert(0 && "Unaligned store of unsupported type"); 598 599 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 600 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 601 SVOffset, ST->isVolatile(), Alignment); 602 } 603 assert(MVT::isInteger(ST->getMemoryVT()) && 604 !MVT::isVector(ST->getMemoryVT()) && 605 "Unaligned store of unknown type."); 606 // Get the half-size VT 607 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1; 608 int NumBits = MVT::getSizeInBits(NewStoredVT); 609 int IncrementSize = NumBits / 8; 610 611 // Divide the stored value in two parts. 612 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 613 SDOperand Lo = Val; 614 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 615 616 // Store the two parts 617 SDOperand Store1, Store2; 618 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 619 ST->getSrcValue(), SVOffset, NewStoredVT, 620 ST->isVolatile(), Alignment); 621 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 622 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 623 Alignment = MinAlign(Alignment, IncrementSize); 624 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 625 ST->getSrcValue(), SVOffset + IncrementSize, 626 NewStoredVT, ST->isVolatile(), Alignment); 627 628 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 629} 630 631/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 632static 633SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 634 TargetLowering &TLI) { 635 int SVOffset = LD->getSrcValueOffset(); 636 SDOperand Chain = LD->getChain(); 637 SDOperand Ptr = LD->getBasePtr(); 638 MVT::ValueType VT = LD->getValueType(0); 639 MVT::ValueType LoadedVT = LD->getMemoryVT(); 640 if (MVT::isFloatingPoint(VT) || MVT::isVector(VT)) { 641 // Expand to a (misaligned) integer load of the same size, 642 // then bitconvert to floating point or vector. 643 MVT::ValueType intVT; 644 if (MVT::is128BitVector(LoadedVT) || 645 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128) 646 intVT = MVT::i128; 647 else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64) 648 intVT = MVT::i64; 649 else if (LoadedVT == MVT::f32) 650 intVT = MVT::i32; 651 else 652 assert(0 && "Unaligned load of unsupported type"); 653 654 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 655 SVOffset, LD->isVolatile(), 656 LD->getAlignment()); 657 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 658 if (MVT::isFloatingPoint(VT) && LoadedVT != VT) 659 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 660 661 SDOperand Ops[] = { Result, Chain }; 662 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 663 Ops, 2); 664 } 665 assert(MVT::isInteger(LoadedVT) && !MVT::isVector(LoadedVT) && 666 "Unaligned load of unsupported type."); 667 668 // Compute the new VT that is half the size of the old one. This is an 669 // integer MVT. 670 unsigned NumBits = MVT::getSizeInBits(LoadedVT); 671 MVT::ValueType NewLoadedVT; 672 NewLoadedVT = MVT::getIntegerType(NumBits/2); 673 NumBits >>= 1; 674 675 unsigned Alignment = LD->getAlignment(); 676 unsigned IncrementSize = NumBits / 8; 677 ISD::LoadExtType HiExtType = LD->getExtensionType(); 678 679 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 680 if (HiExtType == ISD::NON_EXTLOAD) 681 HiExtType = ISD::ZEXTLOAD; 682 683 // Load the value in two parts 684 SDOperand Lo, Hi; 685 if (TLI.isLittleEndian()) { 686 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 687 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 688 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 689 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 690 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 691 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 692 MinAlign(Alignment, IncrementSize)); 693 } else { 694 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 695 NewLoadedVT,LD->isVolatile(), Alignment); 696 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 697 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 698 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 699 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 700 MinAlign(Alignment, IncrementSize)); 701 } 702 703 // aggregate the two parts 704 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 705 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 706 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 707 708 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 709 Hi.getValue(1)); 710 711 SDOperand Ops[] = { Result, TF }; 712 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 713} 714 715/// UnrollVectorOp - We know that the given vector has a legal type, however 716/// the operation it performs is not legal and is an operation that we have 717/// no way of lowering. "Unroll" the vector, splitting out the scalars and 718/// operating on each element individually. 719SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { 720 MVT::ValueType VT = Op.getValueType(); 721 assert(isTypeLegal(VT) && 722 "Caller should expand or promote operands that are not legal!"); 723 assert(Op.Val->getNumValues() == 1 && 724 "Can't unroll a vector with multiple results!"); 725 unsigned NE = MVT::getVectorNumElements(VT); 726 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 727 728 SmallVector<SDOperand, 8> Scalars; 729 SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); 730 for (unsigned i = 0; i != NE; ++i) { 731 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 732 SDOperand Operand = Op.getOperand(j); 733 MVT::ValueType OperandVT = Operand.getValueType(); 734 if (MVT::isVector(OperandVT)) { 735 // A vector operand; extract a single element. 736 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT); 737 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 738 OperandEltVT, 739 Operand, 740 DAG.getConstant(i, MVT::i32)); 741 } else { 742 // A scalar operand; just use it as is. 743 Operands[j] = Operand; 744 } 745 } 746 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 747 &Operands[0], Operands.size())); 748 } 749 750 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 751} 752 753/// GetFPLibCall - Return the right libcall for the given floating point type. 754static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT, 755 RTLIB::Libcall Call_F32, 756 RTLIB::Libcall Call_F64, 757 RTLIB::Libcall Call_F80, 758 RTLIB::Libcall Call_PPCF128) { 759 return 760 VT == MVT::f32 ? Call_F32 : 761 VT == MVT::f64 ? Call_F64 : 762 VT == MVT::f80 ? Call_F80 : 763 VT == MVT::ppcf128 ? Call_PPCF128 : 764 RTLIB::UNKNOWN_LIBCALL; 765} 766 767/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 768/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 769/// is necessary to spill the vector being inserted into to memory, perform 770/// the insert there, and then read the result back. 771SDOperand SelectionDAGLegalize:: 772PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) { 773 SDOperand Tmp1 = Vec; 774 SDOperand Tmp2 = Val; 775 SDOperand Tmp3 = Idx; 776 777 // If the target doesn't support this, we have to spill the input vector 778 // to a temporary stack slot, update the element, then reload it. This is 779 // badness. We could also load the value into a vector register (either 780 // with a "move to register" or "extload into register" instruction, then 781 // permute it into place, if the idx is a constant and if the idx is 782 // supported by the target. 783 MVT::ValueType VT = Tmp1.getValueType(); 784 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 785 MVT::ValueType IdxVT = Tmp3.getValueType(); 786 MVT::ValueType PtrVT = TLI.getPointerTy(); 787 SDOperand StackPtr = DAG.CreateStackTemporary(VT); 788 789 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val); 790 int SPFI = StackPtrFI->getIndex(); 791 792 // Store the vector. 793 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, 794 PseudoSourceValue::getFixedStack(), 795 SPFI); 796 797 // Truncate or zero extend offset to target pointer type. 798 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 799 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 800 // Add the offset to the index. 801 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 802 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 803 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 804 // Store the scalar value. 805 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, 806 PseudoSourceValue::getFixedStack(), SPFI, EltVT); 807 // Load the updated vector. 808 return DAG.getLoad(VT, Ch, StackPtr, PseudoSourceValue::getFixedStack(),SPFI); 809} 810 811/// LegalizeOp - We know that the specified value has a legal type, and 812/// that its operands are legal. Now ensure that the operation itself 813/// is legal, recursively ensuring that the operands' operations remain 814/// legal. 815SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 816 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 817 return Op; 818 819 assert(isTypeLegal(Op.getValueType()) && 820 "Caller should expand or promote operands that are not legal!"); 821 SDNode *Node = Op.Val; 822 823 // If this operation defines any values that cannot be represented in a 824 // register on this target, make sure to expand or promote them. 825 if (Node->getNumValues() > 1) { 826 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 827 if (getTypeAction(Node->getValueType(i)) != Legal) { 828 HandleOp(Op.getValue(i)); 829 assert(LegalizedNodes.count(Op) && 830 "Handling didn't add legal operands!"); 831 return LegalizedNodes[Op]; 832 } 833 } 834 835 // Note that LegalizeOp may be reentered even from single-use nodes, which 836 // means that we always must cache transformed nodes. 837 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 838 if (I != LegalizedNodes.end()) return I->second; 839 840 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 841 SDOperand Result = Op; 842 bool isCustom = false; 843 844 switch (Node->getOpcode()) { 845 case ISD::FrameIndex: 846 case ISD::EntryToken: 847 case ISD::Register: 848 case ISD::BasicBlock: 849 case ISD::TargetFrameIndex: 850 case ISD::TargetJumpTable: 851 case ISD::TargetConstant: 852 case ISD::TargetConstantFP: 853 case ISD::TargetConstantPool: 854 case ISD::TargetGlobalAddress: 855 case ISD::TargetGlobalTLSAddress: 856 case ISD::TargetExternalSymbol: 857 case ISD::VALUETYPE: 858 case ISD::SRCVALUE: 859 case ISD::MEMOPERAND: 860 case ISD::STRING: 861 case ISD::CONDCODE: 862 case ISD::ARG_FLAGS: 863 // Primitives must all be legal. 864 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 865 "This must be legal!"); 866 break; 867 default: 868 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 869 // If this is a target node, legalize it by legalizing the operands then 870 // passing it through. 871 SmallVector<SDOperand, 8> Ops; 872 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 873 Ops.push_back(LegalizeOp(Node->getOperand(i))); 874 875 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 876 877 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 878 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 879 return Result.getValue(Op.ResNo); 880 } 881 // Otherwise this is an unhandled builtin node. splat. 882#ifndef NDEBUG 883 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 884#endif 885 assert(0 && "Do not know how to legalize this operator!"); 886 abort(); 887 case ISD::GLOBAL_OFFSET_TABLE: 888 case ISD::GlobalAddress: 889 case ISD::GlobalTLSAddress: 890 case ISD::ExternalSymbol: 891 case ISD::ConstantPool: 892 case ISD::JumpTable: // Nothing to do. 893 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 894 default: assert(0 && "This action is not supported yet!"); 895 case TargetLowering::Custom: 896 Tmp1 = TLI.LowerOperation(Op, DAG); 897 if (Tmp1.Val) Result = Tmp1; 898 // FALLTHROUGH if the target doesn't want to lower this op after all. 899 case TargetLowering::Legal: 900 break; 901 } 902 break; 903 case ISD::FRAMEADDR: 904 case ISD::RETURNADDR: 905 // The only option for these nodes is to custom lower them. If the target 906 // does not custom lower them, then return zero. 907 Tmp1 = TLI.LowerOperation(Op, DAG); 908 if (Tmp1.Val) 909 Result = Tmp1; 910 else 911 Result = DAG.getConstant(0, TLI.getPointerTy()); 912 break; 913 case ISD::FRAME_TO_ARGS_OFFSET: { 914 MVT::ValueType VT = Node->getValueType(0); 915 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 916 default: assert(0 && "This action is not supported yet!"); 917 case TargetLowering::Custom: 918 Result = TLI.LowerOperation(Op, DAG); 919 if (Result.Val) break; 920 // Fall Thru 921 case TargetLowering::Legal: 922 Result = DAG.getConstant(0, VT); 923 break; 924 } 925 } 926 break; 927 case ISD::EXCEPTIONADDR: { 928 Tmp1 = LegalizeOp(Node->getOperand(0)); 929 MVT::ValueType VT = Node->getValueType(0); 930 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 931 default: assert(0 && "This action is not supported yet!"); 932 case TargetLowering::Expand: { 933 unsigned Reg = TLI.getExceptionAddressRegister(); 934 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 935 } 936 break; 937 case TargetLowering::Custom: 938 Result = TLI.LowerOperation(Op, DAG); 939 if (Result.Val) break; 940 // Fall Thru 941 case TargetLowering::Legal: { 942 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 943 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 944 Ops, 2); 945 break; 946 } 947 } 948 } 949 if (Result.Val->getNumValues() == 1) break; 950 951 assert(Result.Val->getNumValues() == 2 && 952 "Cannot return more than two values!"); 953 954 // Since we produced two values, make sure to remember that we 955 // legalized both of them. 956 Tmp1 = LegalizeOp(Result); 957 Tmp2 = LegalizeOp(Result.getValue(1)); 958 AddLegalizedOperand(Op.getValue(0), Tmp1); 959 AddLegalizedOperand(Op.getValue(1), Tmp2); 960 return Op.ResNo ? Tmp2 : Tmp1; 961 case ISD::EHSELECTION: { 962 Tmp1 = LegalizeOp(Node->getOperand(0)); 963 Tmp2 = LegalizeOp(Node->getOperand(1)); 964 MVT::ValueType VT = Node->getValueType(0); 965 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 966 default: assert(0 && "This action is not supported yet!"); 967 case TargetLowering::Expand: { 968 unsigned Reg = TLI.getExceptionSelectorRegister(); 969 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 970 } 971 break; 972 case TargetLowering::Custom: 973 Result = TLI.LowerOperation(Op, DAG); 974 if (Result.Val) break; 975 // Fall Thru 976 case TargetLowering::Legal: { 977 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 978 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 979 Ops, 2); 980 break; 981 } 982 } 983 } 984 if (Result.Val->getNumValues() == 1) break; 985 986 assert(Result.Val->getNumValues() == 2 && 987 "Cannot return more than two values!"); 988 989 // Since we produced two values, make sure to remember that we 990 // legalized both of them. 991 Tmp1 = LegalizeOp(Result); 992 Tmp2 = LegalizeOp(Result.getValue(1)); 993 AddLegalizedOperand(Op.getValue(0), Tmp1); 994 AddLegalizedOperand(Op.getValue(1), Tmp2); 995 return Op.ResNo ? Tmp2 : Tmp1; 996 case ISD::EH_RETURN: { 997 MVT::ValueType VT = Node->getValueType(0); 998 // The only "good" option for this node is to custom lower it. 999 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1000 default: assert(0 && "This action is not supported at all!"); 1001 case TargetLowering::Custom: 1002 Result = TLI.LowerOperation(Op, DAG); 1003 if (Result.Val) break; 1004 // Fall Thru 1005 case TargetLowering::Legal: 1006 // Target does not know, how to lower this, lower to noop 1007 Result = LegalizeOp(Node->getOperand(0)); 1008 break; 1009 } 1010 } 1011 break; 1012 case ISD::AssertSext: 1013 case ISD::AssertZext: 1014 Tmp1 = LegalizeOp(Node->getOperand(0)); 1015 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1016 break; 1017 case ISD::MERGE_VALUES: 1018 // Legalize eliminates MERGE_VALUES nodes. 1019 Result = Node->getOperand(Op.ResNo); 1020 break; 1021 case ISD::CopyFromReg: 1022 Tmp1 = LegalizeOp(Node->getOperand(0)); 1023 Result = Op.getValue(0); 1024 if (Node->getNumValues() == 2) { 1025 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1026 } else { 1027 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 1028 if (Node->getNumOperands() == 3) { 1029 Tmp2 = LegalizeOp(Node->getOperand(2)); 1030 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1031 } else { 1032 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1033 } 1034 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 1035 } 1036 // Since CopyFromReg produces two values, make sure to remember that we 1037 // legalized both of them. 1038 AddLegalizedOperand(Op.getValue(0), Result); 1039 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1040 return Result.getValue(Op.ResNo); 1041 case ISD::UNDEF: { 1042 MVT::ValueType VT = Op.getValueType(); 1043 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 1044 default: assert(0 && "This action is not supported yet!"); 1045 case TargetLowering::Expand: 1046 if (MVT::isInteger(VT)) 1047 Result = DAG.getConstant(0, VT); 1048 else if (MVT::isFloatingPoint(VT)) 1049 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)), 1050 VT); 1051 else 1052 assert(0 && "Unknown value type!"); 1053 break; 1054 case TargetLowering::Legal: 1055 break; 1056 } 1057 break; 1058 } 1059 1060 case ISD::INTRINSIC_W_CHAIN: 1061 case ISD::INTRINSIC_WO_CHAIN: 1062 case ISD::INTRINSIC_VOID: { 1063 SmallVector<SDOperand, 8> Ops; 1064 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1065 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1066 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1067 1068 // Allow the target to custom lower its intrinsics if it wants to. 1069 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1070 TargetLowering::Custom) { 1071 Tmp3 = TLI.LowerOperation(Result, DAG); 1072 if (Tmp3.Val) Result = Tmp3; 1073 } 1074 1075 if (Result.Val->getNumValues() == 1) break; 1076 1077 // Must have return value and chain result. 1078 assert(Result.Val->getNumValues() == 2 && 1079 "Cannot return more than two values!"); 1080 1081 // Since loads produce two values, make sure to remember that we 1082 // legalized both of them. 1083 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1084 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1085 return Result.getValue(Op.ResNo); 1086 } 1087 1088 case ISD::LOCATION: 1089 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 1090 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1091 1092 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 1093 case TargetLowering::Promote: 1094 default: assert(0 && "This action is not supported yet!"); 1095 case TargetLowering::Expand: { 1096 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1097 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1098 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 1099 1100 if (MMI && (useDEBUG_LOC || useLABEL)) { 1101 const std::string &FName = 1102 cast<StringSDNode>(Node->getOperand(3))->getValue(); 1103 const std::string &DirName = 1104 cast<StringSDNode>(Node->getOperand(4))->getValue(); 1105 unsigned SrcFile = MMI->RecordSource(DirName, FName); 1106 1107 SmallVector<SDOperand, 8> Ops; 1108 Ops.push_back(Tmp1); // chain 1109 SDOperand LineOp = Node->getOperand(1); 1110 SDOperand ColOp = Node->getOperand(2); 1111 1112 if (useDEBUG_LOC) { 1113 Ops.push_back(LineOp); // line # 1114 Ops.push_back(ColOp); // col # 1115 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 1116 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 1117 } else { 1118 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 1119 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 1120 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); 1121 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 1122 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label 1123 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size()); 1124 } 1125 } else { 1126 Result = Tmp1; // chain 1127 } 1128 break; 1129 } 1130 case TargetLowering::Legal: 1131 if (Tmp1 != Node->getOperand(0) || 1132 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 1133 SmallVector<SDOperand, 8> Ops; 1134 Ops.push_back(Tmp1); 1135 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 1136 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1137 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1138 } else { 1139 // Otherwise promote them. 1140 Ops.push_back(PromoteOp(Node->getOperand(1))); 1141 Ops.push_back(PromoteOp(Node->getOperand(2))); 1142 } 1143 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1144 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1145 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1146 } 1147 break; 1148 } 1149 break; 1150 1151 case ISD::DECLARE: 1152 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1153 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1154 default: assert(0 && "This action is not supported yet!"); 1155 case TargetLowering::Legal: 1156 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1157 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1158 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1159 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1160 break; 1161 case TargetLowering::Expand: 1162 Result = LegalizeOp(Node->getOperand(0)); 1163 break; 1164 } 1165 break; 1166 1167 case ISD::DEBUG_LOC: 1168 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1169 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1170 default: assert(0 && "This action is not supported yet!"); 1171 case TargetLowering::Legal: 1172 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1173 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1174 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1175 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1176 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1177 break; 1178 } 1179 break; 1180 1181 case ISD::LABEL: 1182 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!"); 1183 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 1184 default: assert(0 && "This action is not supported yet!"); 1185 case TargetLowering::Legal: 1186 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1187 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 1188 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand. 1189 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1190 break; 1191 case TargetLowering::Expand: 1192 Result = LegalizeOp(Node->getOperand(0)); 1193 break; 1194 } 1195 break; 1196 1197 case ISD::PREFETCH: 1198 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1199 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1200 default: assert(0 && "This action is not supported yet!"); 1201 case TargetLowering::Legal: 1202 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1203 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1204 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1205 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1206 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1207 break; 1208 case TargetLowering::Expand: 1209 // It's a noop. 1210 Result = LegalizeOp(Node->getOperand(0)); 1211 break; 1212 } 1213 break; 1214 1215 case ISD::MEMBARRIER: { 1216 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1217 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1218 default: assert(0 && "This action is not supported yet!"); 1219 case TargetLowering::Legal: { 1220 SDOperand Ops[6]; 1221 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1222 for (int x = 1; x < 6; ++x) { 1223 Ops[x] = Node->getOperand(x); 1224 if (!isTypeLegal(Ops[x].getValueType())) 1225 Ops[x] = PromoteOp(Ops[x]); 1226 } 1227 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1228 break; 1229 } 1230 case TargetLowering::Expand: 1231 //There is no libgcc call for this op 1232 Result = Node->getOperand(0); // Noop 1233 break; 1234 } 1235 break; 1236 } 1237 1238 case ISD::ATOMIC_LCS: { 1239 unsigned int num_operands = 4; 1240 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1241 SDOperand Ops[4]; 1242 for (unsigned int x = 0; x < num_operands; ++x) 1243 Ops[x] = LegalizeOp(Node->getOperand(x)); 1244 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1245 1246 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1247 default: assert(0 && "This action is not supported yet!"); 1248 case TargetLowering::Custom: 1249 Result = TLI.LowerOperation(Result, DAG); 1250 break; 1251 case TargetLowering::Legal: 1252 break; 1253 } 1254 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1255 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1256 return Result.getValue(Op.ResNo); 1257 } 1258 case ISD::ATOMIC_LAS: 1259 case ISD::ATOMIC_LSS: 1260 case ISD::ATOMIC_LOAD_AND: 1261 case ISD::ATOMIC_LOAD_OR: 1262 case ISD::ATOMIC_LOAD_XOR: 1263 case ISD::ATOMIC_LOAD_MIN: 1264 case ISD::ATOMIC_LOAD_MAX: 1265 case ISD::ATOMIC_LOAD_UMIN: 1266 case ISD::ATOMIC_LOAD_UMAX: 1267 case ISD::ATOMIC_SWAP: { 1268 unsigned int num_operands = 3; 1269 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1270 SDOperand Ops[3]; 1271 for (unsigned int x = 0; x < num_operands; ++x) 1272 Ops[x] = LegalizeOp(Node->getOperand(x)); 1273 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1274 1275 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1276 default: assert(0 && "This action is not supported yet!"); 1277 case TargetLowering::Custom: 1278 Result = TLI.LowerOperation(Result, DAG); 1279 break; 1280 case TargetLowering::Expand: 1281 Result = SDOperand(TLI.ExpandOperationResult(Op.Val, DAG),0); 1282 break; 1283 case TargetLowering::Legal: 1284 break; 1285 } 1286 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1287 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1288 return Result.getValue(Op.ResNo); 1289 } 1290 case ISD::Constant: { 1291 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1292 unsigned opAction = 1293 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1294 1295 // We know we don't need to expand constants here, constants only have one 1296 // value and we check that it is fine above. 1297 1298 if (opAction == TargetLowering::Custom) { 1299 Tmp1 = TLI.LowerOperation(Result, DAG); 1300 if (Tmp1.Val) 1301 Result = Tmp1; 1302 } 1303 break; 1304 } 1305 case ISD::ConstantFP: { 1306 // Spill FP immediates to the constant pool if the target cannot directly 1307 // codegen them. Targets often have some immediate values that can be 1308 // efficiently generated into an FP register without a load. We explicitly 1309 // leave these constants as ConstantFP nodes for the target to deal with. 1310 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1311 1312 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1313 default: assert(0 && "This action is not supported yet!"); 1314 case TargetLowering::Legal: 1315 break; 1316 case TargetLowering::Custom: 1317 Tmp3 = TLI.LowerOperation(Result, DAG); 1318 if (Tmp3.Val) { 1319 Result = Tmp3; 1320 break; 1321 } 1322 // FALLTHROUGH 1323 case TargetLowering::Expand: { 1324 // Check to see if this FP immediate is already legal. 1325 bool isLegal = false; 1326 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1327 E = TLI.legal_fpimm_end(); I != E; ++I) { 1328 if (CFP->isExactlyValue(*I)) { 1329 isLegal = true; 1330 break; 1331 } 1332 } 1333 // If this is a legal constant, turn it into a TargetConstantFP node. 1334 if (isLegal) 1335 break; 1336 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1337 } 1338 } 1339 break; 1340 } 1341 case ISD::TokenFactor: 1342 if (Node->getNumOperands() == 2) { 1343 Tmp1 = LegalizeOp(Node->getOperand(0)); 1344 Tmp2 = LegalizeOp(Node->getOperand(1)); 1345 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1346 } else if (Node->getNumOperands() == 3) { 1347 Tmp1 = LegalizeOp(Node->getOperand(0)); 1348 Tmp2 = LegalizeOp(Node->getOperand(1)); 1349 Tmp3 = LegalizeOp(Node->getOperand(2)); 1350 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1351 } else { 1352 SmallVector<SDOperand, 8> Ops; 1353 // Legalize the operands. 1354 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1355 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1356 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1357 } 1358 break; 1359 1360 case ISD::FORMAL_ARGUMENTS: 1361 case ISD::CALL: 1362 // The only option for this is to custom lower it. 1363 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1364 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1365 // A call within a calling sequence must be legalized to something 1366 // other than the normal CALLSEQ_END. Violating this gets Legalize 1367 // into an infinite loop. 1368 assert ((!IsLegalizingCall || 1369 Node->getOpcode() != ISD::CALL || 1370 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) && 1371 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1372 1373 // The number of incoming and outgoing values should match; unless the final 1374 // outgoing value is a flag. 1375 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || 1376 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && 1377 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == 1378 MVT::Flag)) && 1379 "Lowering call/formal_arguments produced unexpected # results!"); 1380 1381 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1382 // remember that we legalized all of them, so it doesn't get relegalized. 1383 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1384 if (Tmp3.Val->getValueType(i) == MVT::Flag) 1385 continue; 1386 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1387 if (Op.ResNo == i) 1388 Tmp2 = Tmp1; 1389 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1390 } 1391 return Tmp2; 1392 case ISD::EXTRACT_SUBREG: { 1393 Tmp1 = LegalizeOp(Node->getOperand(0)); 1394 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1395 assert(idx && "Operand must be a constant"); 1396 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1397 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1398 } 1399 break; 1400 case ISD::INSERT_SUBREG: { 1401 Tmp1 = LegalizeOp(Node->getOperand(0)); 1402 Tmp2 = LegalizeOp(Node->getOperand(1)); 1403 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1404 assert(idx && "Operand must be a constant"); 1405 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1406 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1407 } 1408 break; 1409 case ISD::BUILD_VECTOR: 1410 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1411 default: assert(0 && "This action is not supported yet!"); 1412 case TargetLowering::Custom: 1413 Tmp3 = TLI.LowerOperation(Result, DAG); 1414 if (Tmp3.Val) { 1415 Result = Tmp3; 1416 break; 1417 } 1418 // FALLTHROUGH 1419 case TargetLowering::Expand: 1420 Result = ExpandBUILD_VECTOR(Result.Val); 1421 break; 1422 } 1423 break; 1424 case ISD::INSERT_VECTOR_ELT: 1425 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1426 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1427 1428 // The type of the value to insert may not be legal, even though the vector 1429 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1430 // here. 1431 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1432 default: assert(0 && "Cannot expand insert element operand"); 1433 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1434 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1435 } 1436 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1437 1438 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1439 Node->getValueType(0))) { 1440 default: assert(0 && "This action is not supported yet!"); 1441 case TargetLowering::Legal: 1442 break; 1443 case TargetLowering::Custom: 1444 Tmp4 = TLI.LowerOperation(Result, DAG); 1445 if (Tmp4.Val) { 1446 Result = Tmp4; 1447 break; 1448 } 1449 // FALLTHROUGH 1450 case TargetLowering::Expand: { 1451 // If the insert index is a constant, codegen this as a scalar_to_vector, 1452 // then a shuffle that inserts it into the right position in the vector. 1453 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1454 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1455 // match the element type of the vector being created. 1456 if (Tmp2.getValueType() == 1457 MVT::getVectorElementType(Op.getValueType())) { 1458 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1459 Tmp1.getValueType(), Tmp2); 1460 1461 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1462 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1463 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); 1464 1465 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1466 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1467 // elt 0 of the RHS. 1468 SmallVector<SDOperand, 8> ShufOps; 1469 for (unsigned i = 0; i != NumElts; ++i) { 1470 if (i != InsertPos->getValue()) 1471 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1472 else 1473 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1474 } 1475 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1476 &ShufOps[0], ShufOps.size()); 1477 1478 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1479 Tmp1, ScVec, ShufMask); 1480 Result = LegalizeOp(Result); 1481 break; 1482 } 1483 } 1484 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3); 1485 break; 1486 } 1487 } 1488 break; 1489 case ISD::SCALAR_TO_VECTOR: 1490 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1491 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1492 break; 1493 } 1494 1495 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1496 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1497 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1498 Node->getValueType(0))) { 1499 default: assert(0 && "This action is not supported yet!"); 1500 case TargetLowering::Legal: 1501 break; 1502 case TargetLowering::Custom: 1503 Tmp3 = TLI.LowerOperation(Result, DAG); 1504 if (Tmp3.Val) { 1505 Result = Tmp3; 1506 break; 1507 } 1508 // FALLTHROUGH 1509 case TargetLowering::Expand: 1510 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1511 break; 1512 } 1513 break; 1514 case ISD::VECTOR_SHUFFLE: 1515 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1516 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1517 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1518 1519 // Allow targets to custom lower the SHUFFLEs they support. 1520 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1521 default: assert(0 && "Unknown operation action!"); 1522 case TargetLowering::Legal: 1523 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1524 "vector shuffle should not be created if not legal!"); 1525 break; 1526 case TargetLowering::Custom: 1527 Tmp3 = TLI.LowerOperation(Result, DAG); 1528 if (Tmp3.Val) { 1529 Result = Tmp3; 1530 break; 1531 } 1532 // FALLTHROUGH 1533 case TargetLowering::Expand: { 1534 MVT::ValueType VT = Node->getValueType(0); 1535 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1536 MVT::ValueType PtrVT = TLI.getPointerTy(); 1537 SDOperand Mask = Node->getOperand(2); 1538 unsigned NumElems = Mask.getNumOperands(); 1539 SmallVector<SDOperand,8> Ops; 1540 for (unsigned i = 0; i != NumElems; ++i) { 1541 SDOperand Arg = Mask.getOperand(i); 1542 if (Arg.getOpcode() == ISD::UNDEF) { 1543 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1544 } else { 1545 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1546 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1547 if (Idx < NumElems) 1548 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1549 DAG.getConstant(Idx, PtrVT))); 1550 else 1551 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1552 DAG.getConstant(Idx - NumElems, PtrVT))); 1553 } 1554 } 1555 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1556 break; 1557 } 1558 case TargetLowering::Promote: { 1559 // Change base type to a different vector type. 1560 MVT::ValueType OVT = Node->getValueType(0); 1561 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1562 1563 // Cast the two input vectors. 1564 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1565 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1566 1567 // Convert the shuffle mask to the right # elements. 1568 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1569 assert(Tmp3.Val && "Shuffle not legal?"); 1570 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1571 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1572 break; 1573 } 1574 } 1575 break; 1576 1577 case ISD::EXTRACT_VECTOR_ELT: 1578 Tmp1 = Node->getOperand(0); 1579 Tmp2 = LegalizeOp(Node->getOperand(1)); 1580 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1581 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1582 break; 1583 1584 case ISD::EXTRACT_SUBVECTOR: 1585 Tmp1 = Node->getOperand(0); 1586 Tmp2 = LegalizeOp(Node->getOperand(1)); 1587 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1588 Result = ExpandEXTRACT_SUBVECTOR(Result); 1589 break; 1590 1591 case ISD::CALLSEQ_START: { 1592 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1593 1594 // Recursively Legalize all of the inputs of the call end that do not lead 1595 // to this call start. This ensures that any libcalls that need be inserted 1596 // are inserted *before* the CALLSEQ_START. 1597 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1598 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1599 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1600 NodesLeadingTo); 1601 } 1602 1603 // Now that we legalized all of the inputs (which may have inserted 1604 // libcalls) create the new CALLSEQ_START node. 1605 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1606 1607 // Merge in the last call, to ensure that this call start after the last 1608 // call ended. 1609 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1610 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1611 Tmp1 = LegalizeOp(Tmp1); 1612 } 1613 1614 // Do not try to legalize the target-specific arguments (#1+). 1615 if (Tmp1 != Node->getOperand(0)) { 1616 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1617 Ops[0] = Tmp1; 1618 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1619 } 1620 1621 // Remember that the CALLSEQ_START is legalized. 1622 AddLegalizedOperand(Op.getValue(0), Result); 1623 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1624 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1625 1626 // Now that the callseq_start and all of the non-call nodes above this call 1627 // sequence have been legalized, legalize the call itself. During this 1628 // process, no libcalls can/will be inserted, guaranteeing that no calls 1629 // can overlap. 1630 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1631 SDOperand InCallSEQ = LastCALLSEQ_END; 1632 // Note that we are selecting this call! 1633 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1634 IsLegalizingCall = true; 1635 1636 // Legalize the call, starting from the CALLSEQ_END. 1637 LegalizeOp(LastCALLSEQ_END); 1638 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1639 return Result; 1640 } 1641 case ISD::CALLSEQ_END: 1642 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1643 // will cause this node to be legalized as well as handling libcalls right. 1644 if (LastCALLSEQ_END.Val != Node) { 1645 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1646 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1647 assert(I != LegalizedNodes.end() && 1648 "Legalizing the call start should have legalized this node!"); 1649 return I->second; 1650 } 1651 1652 // Otherwise, the call start has been legalized and everything is going 1653 // according to plan. Just legalize ourselves normally here. 1654 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1655 // Do not try to legalize the target-specific arguments (#1+), except for 1656 // an optional flag input. 1657 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1658 if (Tmp1 != Node->getOperand(0)) { 1659 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1660 Ops[0] = Tmp1; 1661 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1662 } 1663 } else { 1664 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1665 if (Tmp1 != Node->getOperand(0) || 1666 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1667 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1668 Ops[0] = Tmp1; 1669 Ops.back() = Tmp2; 1670 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1671 } 1672 } 1673 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1674 // This finishes up call legalization. 1675 IsLegalizingCall = false; 1676 1677 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1678 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1679 if (Node->getNumValues() == 2) 1680 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1681 return Result.getValue(Op.ResNo); 1682 case ISD::DYNAMIC_STACKALLOC: { 1683 MVT::ValueType VT = Node->getValueType(0); 1684 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1685 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1686 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1687 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1688 1689 Tmp1 = Result.getValue(0); 1690 Tmp2 = Result.getValue(1); 1691 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1692 default: assert(0 && "This action is not supported yet!"); 1693 case TargetLowering::Expand: { 1694 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1695 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1696 " not tell us which reg is the stack pointer!"); 1697 SDOperand Chain = Tmp1.getOperand(0); 1698 1699 // Chain the dynamic stack allocation so that it doesn't modify the stack 1700 // pointer when other instructions are using the stack. 1701 Chain = DAG.getCALLSEQ_START(Chain, 1702 DAG.getConstant(0, TLI.getPointerTy())); 1703 1704 SDOperand Size = Tmp2.getOperand(1); 1705 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1706 Chain = SP.getValue(1); 1707 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1708 unsigned StackAlign = 1709 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1710 if (Align > StackAlign) 1711 SP = DAG.getNode(ISD::AND, VT, SP, 1712 DAG.getConstant(-(uint64_t)Align, VT)); 1713 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1714 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1715 1716 Tmp2 = 1717 DAG.getCALLSEQ_END(Chain, 1718 DAG.getConstant(0, TLI.getPointerTy()), 1719 DAG.getConstant(0, TLI.getPointerTy()), 1720 SDOperand()); 1721 1722 Tmp1 = LegalizeOp(Tmp1); 1723 Tmp2 = LegalizeOp(Tmp2); 1724 break; 1725 } 1726 case TargetLowering::Custom: 1727 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1728 if (Tmp3.Val) { 1729 Tmp1 = LegalizeOp(Tmp3); 1730 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1731 } 1732 break; 1733 case TargetLowering::Legal: 1734 break; 1735 } 1736 // Since this op produce two values, make sure to remember that we 1737 // legalized both of them. 1738 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1739 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1740 return Op.ResNo ? Tmp2 : Tmp1; 1741 } 1742 case ISD::INLINEASM: { 1743 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1744 bool Changed = false; 1745 // Legalize all of the operands of the inline asm, in case they are nodes 1746 // that need to be expanded or something. Note we skip the asm string and 1747 // all of the TargetConstant flags. 1748 SDOperand Op = LegalizeOp(Ops[0]); 1749 Changed = Op != Ops[0]; 1750 Ops[0] = Op; 1751 1752 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1753 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1754 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1755 for (++i; NumVals; ++i, --NumVals) { 1756 SDOperand Op = LegalizeOp(Ops[i]); 1757 if (Op != Ops[i]) { 1758 Changed = true; 1759 Ops[i] = Op; 1760 } 1761 } 1762 } 1763 1764 if (HasInFlag) { 1765 Op = LegalizeOp(Ops.back()); 1766 Changed |= Op != Ops.back(); 1767 Ops.back() = Op; 1768 } 1769 1770 if (Changed) 1771 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1772 1773 // INLINE asm returns a chain and flag, make sure to add both to the map. 1774 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1775 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1776 return Result.getValue(Op.ResNo); 1777 } 1778 case ISD::BR: 1779 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1780 // Ensure that libcalls are emitted before a branch. 1781 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1782 Tmp1 = LegalizeOp(Tmp1); 1783 LastCALLSEQ_END = DAG.getEntryNode(); 1784 1785 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1786 break; 1787 case ISD::BRIND: 1788 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1789 // Ensure that libcalls are emitted before a branch. 1790 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1791 Tmp1 = LegalizeOp(Tmp1); 1792 LastCALLSEQ_END = DAG.getEntryNode(); 1793 1794 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1795 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1796 case Legal: 1797 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1798 break; 1799 } 1800 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1801 break; 1802 case ISD::BR_JT: 1803 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1804 // Ensure that libcalls are emitted before a branch. 1805 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1806 Tmp1 = LegalizeOp(Tmp1); 1807 LastCALLSEQ_END = DAG.getEntryNode(); 1808 1809 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1810 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1811 1812 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1813 default: assert(0 && "This action is not supported yet!"); 1814 case TargetLowering::Legal: break; 1815 case TargetLowering::Custom: 1816 Tmp1 = TLI.LowerOperation(Result, DAG); 1817 if (Tmp1.Val) Result = Tmp1; 1818 break; 1819 case TargetLowering::Expand: { 1820 SDOperand Chain = Result.getOperand(0); 1821 SDOperand Table = Result.getOperand(1); 1822 SDOperand Index = Result.getOperand(2); 1823 1824 MVT::ValueType PTy = TLI.getPointerTy(); 1825 MachineFunction &MF = DAG.getMachineFunction(); 1826 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1827 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1828 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1829 1830 SDOperand LD; 1831 switch (EntrySize) { 1832 default: assert(0 && "Size of jump table not supported yet."); break; 1833 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, 1834 PseudoSourceValue::getJumpTable(), 0); break; 1835 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, 1836 PseudoSourceValue::getJumpTable(), 0); break; 1837 } 1838 1839 Addr = LD; 1840 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1841 // For PIC, the sequence is: 1842 // BRIND(load(Jumptable + index) + RelocBase) 1843 // RelocBase can be JumpTable, GOT or some sort of global base. 1844 if (PTy != MVT::i32) 1845 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1846 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1847 TLI.getPICJumpTableRelocBase(Table, DAG)); 1848 } 1849 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1850 } 1851 } 1852 break; 1853 case ISD::BRCOND: 1854 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1855 // Ensure that libcalls are emitted before a return. 1856 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1857 Tmp1 = LegalizeOp(Tmp1); 1858 LastCALLSEQ_END = DAG.getEntryNode(); 1859 1860 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1861 case Expand: assert(0 && "It's impossible to expand bools"); 1862 case Legal: 1863 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1864 break; 1865 case Promote: { 1866 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1867 1868 // The top bits of the promoted condition are not necessarily zero, ensure 1869 // that the value is properly zero extended. 1870 unsigned BitWidth = Tmp2.getValueSizeInBits(); 1871 if (!DAG.MaskedValueIsZero(Tmp2, 1872 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 1873 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1874 break; 1875 } 1876 } 1877 1878 // Basic block destination (Op#2) is always legal. 1879 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1880 1881 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1882 default: assert(0 && "This action is not supported yet!"); 1883 case TargetLowering::Legal: break; 1884 case TargetLowering::Custom: 1885 Tmp1 = TLI.LowerOperation(Result, DAG); 1886 if (Tmp1.Val) Result = Tmp1; 1887 break; 1888 case TargetLowering::Expand: 1889 // Expand brcond's setcc into its constituent parts and create a BR_CC 1890 // Node. 1891 if (Tmp2.getOpcode() == ISD::SETCC) { 1892 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1893 Tmp2.getOperand(0), Tmp2.getOperand(1), 1894 Node->getOperand(2)); 1895 } else { 1896 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1897 DAG.getCondCode(ISD::SETNE), Tmp2, 1898 DAG.getConstant(0, Tmp2.getValueType()), 1899 Node->getOperand(2)); 1900 } 1901 break; 1902 } 1903 break; 1904 case ISD::BR_CC: 1905 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1906 // Ensure that libcalls are emitted before a branch. 1907 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1908 Tmp1 = LegalizeOp(Tmp1); 1909 Tmp2 = Node->getOperand(2); // LHS 1910 Tmp3 = Node->getOperand(3); // RHS 1911 Tmp4 = Node->getOperand(1); // CC 1912 1913 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1914 LastCALLSEQ_END = DAG.getEntryNode(); 1915 1916 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1917 // the LHS is a legal SETCC itself. In this case, we need to compare 1918 // the result against zero to select between true and false values. 1919 if (Tmp3.Val == 0) { 1920 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1921 Tmp4 = DAG.getCondCode(ISD::SETNE); 1922 } 1923 1924 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1925 Node->getOperand(4)); 1926 1927 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1928 default: assert(0 && "Unexpected action for BR_CC!"); 1929 case TargetLowering::Legal: break; 1930 case TargetLowering::Custom: 1931 Tmp4 = TLI.LowerOperation(Result, DAG); 1932 if (Tmp4.Val) Result = Tmp4; 1933 break; 1934 } 1935 break; 1936 case ISD::LOAD: { 1937 LoadSDNode *LD = cast<LoadSDNode>(Node); 1938 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1939 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1940 1941 ISD::LoadExtType ExtType = LD->getExtensionType(); 1942 if (ExtType == ISD::NON_EXTLOAD) { 1943 MVT::ValueType VT = Node->getValueType(0); 1944 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1945 Tmp3 = Result.getValue(0); 1946 Tmp4 = Result.getValue(1); 1947 1948 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1949 default: assert(0 && "This action is not supported yet!"); 1950 case TargetLowering::Legal: 1951 // If this is an unaligned load and the target doesn't support it, 1952 // expand it. 1953 if (!TLI.allowsUnalignedMemoryAccesses()) { 1954 unsigned ABIAlignment = TLI.getTargetData()-> 1955 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT())); 1956 if (LD->getAlignment() < ABIAlignment){ 1957 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1958 TLI); 1959 Tmp3 = Result.getOperand(0); 1960 Tmp4 = Result.getOperand(1); 1961 Tmp3 = LegalizeOp(Tmp3); 1962 Tmp4 = LegalizeOp(Tmp4); 1963 } 1964 } 1965 break; 1966 case TargetLowering::Custom: 1967 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1968 if (Tmp1.Val) { 1969 Tmp3 = LegalizeOp(Tmp1); 1970 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1971 } 1972 break; 1973 case TargetLowering::Promote: { 1974 // Only promote a load of vector type to another. 1975 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1976 // Change base type to a different vector type. 1977 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1978 1979 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1980 LD->getSrcValueOffset(), 1981 LD->isVolatile(), LD->getAlignment()); 1982 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1983 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1984 break; 1985 } 1986 } 1987 // Since loads produce two values, make sure to remember that we 1988 // legalized both of them. 1989 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1990 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1991 return Op.ResNo ? Tmp4 : Tmp3; 1992 } else { 1993 MVT::ValueType SrcVT = LD->getMemoryVT(); 1994 unsigned SrcWidth = MVT::getSizeInBits(SrcVT); 1995 int SVOffset = LD->getSrcValueOffset(); 1996 unsigned Alignment = LD->getAlignment(); 1997 bool isVolatile = LD->isVolatile(); 1998 1999 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) && 2000 // Some targets pretend to have an i1 loading operation, and actually 2001 // load an i8. This trick is correct for ZEXTLOAD because the top 7 2002 // bits are guaranteed to be zero; it helps the optimizers understand 2003 // that these bits are zero. It is also useful for EXTLOAD, since it 2004 // tells the optimizers that those bits are undefined. It would be 2005 // nice to have an effective generic way of getting these benefits... 2006 // Until such a way is found, don't insist on promoting i1 here. 2007 (SrcVT != MVT::i1 || 2008 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 2009 // Promote to a byte-sized load if not loading an integral number of 2010 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 2011 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT); 2012 MVT::ValueType NVT = MVT::getIntegerType(NewWidth); 2013 SDOperand Ch; 2014 2015 // The extra bits are guaranteed to be zero, since we stored them that 2016 // way. A zext load from NVT thus automatically gives zext from SrcVT. 2017 2018 ISD::LoadExtType NewExtType = 2019 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 2020 2021 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), 2022 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 2023 NVT, isVolatile, Alignment); 2024 2025 Ch = Result.getValue(1); // The chain. 2026 2027 if (ExtType == ISD::SEXTLOAD) 2028 // Having the top bits zero doesn't help when sign extending. 2029 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2030 Result, DAG.getValueType(SrcVT)); 2031 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 2032 // All the top bits are guaranteed to be zero - inform the optimizers. 2033 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, 2034 DAG.getValueType(SrcVT)); 2035 2036 Tmp1 = LegalizeOp(Result); 2037 Tmp2 = LegalizeOp(Ch); 2038 } else if (SrcWidth & (SrcWidth - 1)) { 2039 // If not loading a power-of-2 number of bits, expand as two loads. 2040 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) && 2041 "Unsupported extload!"); 2042 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 2043 assert(RoundWidth < SrcWidth); 2044 unsigned ExtraWidth = SrcWidth - RoundWidth; 2045 assert(ExtraWidth < RoundWidth); 2046 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2047 "Load size not an integral number of bytes!"); 2048 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth); 2049 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth); 2050 SDOperand Lo, Hi, Ch; 2051 unsigned IncrementSize; 2052 2053 if (TLI.isLittleEndian()) { 2054 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2055 // Load the bottom RoundWidth bits. 2056 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2057 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2058 Alignment); 2059 2060 // Load the remaining ExtraWidth bits. 2061 IncrementSize = RoundWidth / 8; 2062 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2063 DAG.getIntPtrConstant(IncrementSize)); 2064 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2065 LD->getSrcValue(), SVOffset + IncrementSize, 2066 ExtraVT, isVolatile, 2067 MinAlign(Alignment, IncrementSize)); 2068 2069 // Build a factor node to remember that this load is independent of the 2070 // other one. 2071 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2072 Hi.getValue(1)); 2073 2074 // Move the top bits to the right place. 2075 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2076 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2077 2078 // Join the hi and lo parts. 2079 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2080 } else { 2081 // Big endian - avoid unaligned loads. 2082 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2083 // Load the top RoundWidth bits. 2084 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2085 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2086 Alignment); 2087 2088 // Load the remaining ExtraWidth bits. 2089 IncrementSize = RoundWidth / 8; 2090 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2091 DAG.getIntPtrConstant(IncrementSize)); 2092 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2093 LD->getSrcValue(), SVOffset + IncrementSize, 2094 ExtraVT, isVolatile, 2095 MinAlign(Alignment, IncrementSize)); 2096 2097 // Build a factor node to remember that this load is independent of the 2098 // other one. 2099 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2100 Hi.getValue(1)); 2101 2102 // Move the top bits to the right place. 2103 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2104 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2105 2106 // Join the hi and lo parts. 2107 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2108 } 2109 2110 Tmp1 = LegalizeOp(Result); 2111 Tmp2 = LegalizeOp(Ch); 2112 } else { 2113 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 2114 default: assert(0 && "This action is not supported yet!"); 2115 case TargetLowering::Custom: 2116 isCustom = true; 2117 // FALLTHROUGH 2118 case TargetLowering::Legal: 2119 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2120 Tmp1 = Result.getValue(0); 2121 Tmp2 = Result.getValue(1); 2122 2123 if (isCustom) { 2124 Tmp3 = TLI.LowerOperation(Result, DAG); 2125 if (Tmp3.Val) { 2126 Tmp1 = LegalizeOp(Tmp3); 2127 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2128 } 2129 } else { 2130 // If this is an unaligned load and the target doesn't support it, 2131 // expand it. 2132 if (!TLI.allowsUnalignedMemoryAccesses()) { 2133 unsigned ABIAlignment = TLI.getTargetData()-> 2134 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT())); 2135 if (LD->getAlignment() < ABIAlignment){ 2136 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 2137 TLI); 2138 Tmp1 = Result.getOperand(0); 2139 Tmp2 = Result.getOperand(1); 2140 Tmp1 = LegalizeOp(Tmp1); 2141 Tmp2 = LegalizeOp(Tmp2); 2142 } 2143 } 2144 } 2145 break; 2146 case TargetLowering::Expand: 2147 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2148 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2149 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 2150 LD->getSrcValueOffset(), 2151 LD->isVolatile(), LD->getAlignment()); 2152 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 2153 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2154 Tmp2 = LegalizeOp(Load.getValue(1)); 2155 break; 2156 } 2157 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2158 // Turn the unsupported load into an EXTLOAD followed by an explicit 2159 // zero/sign extend inreg. 2160 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2161 Tmp1, Tmp2, LD->getSrcValue(), 2162 LD->getSrcValueOffset(), SrcVT, 2163 LD->isVolatile(), LD->getAlignment()); 2164 SDOperand ValRes; 2165 if (ExtType == ISD::SEXTLOAD) 2166 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2167 Result, DAG.getValueType(SrcVT)); 2168 else 2169 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 2170 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2171 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2172 break; 2173 } 2174 } 2175 2176 // Since loads produce two values, make sure to remember that we legalized 2177 // both of them. 2178 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2179 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2180 return Op.ResNo ? Tmp2 : Tmp1; 2181 } 2182 } 2183 case ISD::EXTRACT_ELEMENT: { 2184 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 2185 switch (getTypeAction(OpTy)) { 2186 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2187 case Legal: 2188 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 2189 // 1 -> Hi 2190 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 2191 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 2192 TLI.getShiftAmountTy())); 2193 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 2194 } else { 2195 // 0 -> Lo 2196 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 2197 Node->getOperand(0)); 2198 } 2199 break; 2200 case Expand: 2201 // Get both the low and high parts. 2202 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2203 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 2204 Result = Tmp2; // 1 -> Hi 2205 else 2206 Result = Tmp1; // 0 -> Lo 2207 break; 2208 } 2209 break; 2210 } 2211 2212 case ISD::CopyToReg: 2213 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2214 2215 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2216 "Register type must be legal!"); 2217 // Legalize the incoming value (must be a legal type). 2218 Tmp2 = LegalizeOp(Node->getOperand(2)); 2219 if (Node->getNumValues() == 1) { 2220 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2221 } else { 2222 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2223 if (Node->getNumOperands() == 4) { 2224 Tmp3 = LegalizeOp(Node->getOperand(3)); 2225 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2226 Tmp3); 2227 } else { 2228 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2229 } 2230 2231 // Since this produces two values, make sure to remember that we legalized 2232 // both of them. 2233 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2234 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2235 return Result; 2236 } 2237 break; 2238 2239 case ISD::RET: 2240 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2241 2242 // Ensure that libcalls are emitted before a return. 2243 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2244 Tmp1 = LegalizeOp(Tmp1); 2245 LastCALLSEQ_END = DAG.getEntryNode(); 2246 2247 switch (Node->getNumOperands()) { 2248 case 3: // ret val 2249 Tmp2 = Node->getOperand(1); 2250 Tmp3 = Node->getOperand(2); // Signness 2251 switch (getTypeAction(Tmp2.getValueType())) { 2252 case Legal: 2253 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2254 break; 2255 case Expand: 2256 if (!MVT::isVector(Tmp2.getValueType())) { 2257 SDOperand Lo, Hi; 2258 ExpandOp(Tmp2, Lo, Hi); 2259 2260 // Big endian systems want the hi reg first. 2261 if (TLI.isBigEndian()) 2262 std::swap(Lo, Hi); 2263 2264 if (Hi.Val) 2265 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2266 else 2267 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 2268 Result = LegalizeOp(Result); 2269 } else { 2270 SDNode *InVal = Tmp2.Val; 2271 int InIx = Tmp2.ResNo; 2272 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 2273 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 2274 2275 // Figure out if there is a simple type corresponding to this Vector 2276 // type. If so, convert to the vector type. 2277 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2278 if (TLI.isTypeLegal(TVT)) { 2279 // Turn this into a return of the vector type. 2280 Tmp2 = LegalizeOp(Tmp2); 2281 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2282 } else if (NumElems == 1) { 2283 // Turn this into a return of the scalar type. 2284 Tmp2 = ScalarizeVectorOp(Tmp2); 2285 Tmp2 = LegalizeOp(Tmp2); 2286 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2287 2288 // FIXME: Returns of gcc generic vectors smaller than a legal type 2289 // should be returned in integer registers! 2290 2291 // The scalarized value type may not be legal, e.g. it might require 2292 // promotion or expansion. Relegalize the return. 2293 Result = LegalizeOp(Result); 2294 } else { 2295 // FIXME: Returns of gcc generic vectors larger than a legal vector 2296 // type should be returned by reference! 2297 SDOperand Lo, Hi; 2298 SplitVectorOp(Tmp2, Lo, Hi); 2299 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2300 Result = LegalizeOp(Result); 2301 } 2302 } 2303 break; 2304 case Promote: 2305 Tmp2 = PromoteOp(Node->getOperand(1)); 2306 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2307 Result = LegalizeOp(Result); 2308 break; 2309 } 2310 break; 2311 case 1: // ret void 2312 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2313 break; 2314 default: { // ret <values> 2315 SmallVector<SDOperand, 8> NewValues; 2316 NewValues.push_back(Tmp1); 2317 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2318 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2319 case Legal: 2320 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2321 NewValues.push_back(Node->getOperand(i+1)); 2322 break; 2323 case Expand: { 2324 SDOperand Lo, Hi; 2325 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && 2326 "FIXME: TODO: implement returning non-legal vector types!"); 2327 ExpandOp(Node->getOperand(i), Lo, Hi); 2328 NewValues.push_back(Lo); 2329 NewValues.push_back(Node->getOperand(i+1)); 2330 if (Hi.Val) { 2331 NewValues.push_back(Hi); 2332 NewValues.push_back(Node->getOperand(i+1)); 2333 } 2334 break; 2335 } 2336 case Promote: 2337 assert(0 && "Can't promote multiple return value yet!"); 2338 } 2339 2340 if (NewValues.size() == Node->getNumOperands()) 2341 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2342 else 2343 Result = DAG.getNode(ISD::RET, MVT::Other, 2344 &NewValues[0], NewValues.size()); 2345 break; 2346 } 2347 } 2348 2349 if (Result.getOpcode() == ISD::RET) { 2350 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2351 default: assert(0 && "This action is not supported yet!"); 2352 case TargetLowering::Legal: break; 2353 case TargetLowering::Custom: 2354 Tmp1 = TLI.LowerOperation(Result, DAG); 2355 if (Tmp1.Val) Result = Tmp1; 2356 break; 2357 } 2358 } 2359 break; 2360 case ISD::STORE: { 2361 StoreSDNode *ST = cast<StoreSDNode>(Node); 2362 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2363 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2364 int SVOffset = ST->getSrcValueOffset(); 2365 unsigned Alignment = ST->getAlignment(); 2366 bool isVolatile = ST->isVolatile(); 2367 2368 if (!ST->isTruncatingStore()) { 2369 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2370 // FIXME: We shouldn't do this for TargetConstantFP's. 2371 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2372 // to phase ordering between legalized code and the dag combiner. This 2373 // probably means that we need to integrate dag combiner and legalizer 2374 // together. 2375 // We generally can't do this one for long doubles. 2376 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2377 if (CFP->getValueType(0) == MVT::f32 && 2378 getTypeAction(MVT::i32) == Legal) { 2379 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2380 convertToAPInt().zextOrTrunc(32), 2381 MVT::i32); 2382 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2383 SVOffset, isVolatile, Alignment); 2384 break; 2385 } else if (CFP->getValueType(0) == MVT::f64) { 2386 // If this target supports 64-bit registers, do a single 64-bit store. 2387 if (getTypeAction(MVT::i64) == Legal) { 2388 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2389 zextOrTrunc(64), MVT::i64); 2390 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2391 SVOffset, isVolatile, Alignment); 2392 break; 2393 } else if (getTypeAction(MVT::i32) == Legal) { 2394 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2395 // stores. If the target supports neither 32- nor 64-bits, this 2396 // xform is certainly not worth it. 2397 const APInt &IntVal =CFP->getValueAPF().convertToAPInt(); 2398 SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2399 SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2400 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2401 2402 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2403 SVOffset, isVolatile, Alignment); 2404 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2405 DAG.getIntPtrConstant(4)); 2406 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2407 isVolatile, MinAlign(Alignment, 4U)); 2408 2409 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2410 break; 2411 } 2412 } 2413 } 2414 2415 switch (getTypeAction(ST->getMemoryVT())) { 2416 case Legal: { 2417 Tmp3 = LegalizeOp(ST->getValue()); 2418 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2419 ST->getOffset()); 2420 2421 MVT::ValueType VT = Tmp3.getValueType(); 2422 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2423 default: assert(0 && "This action is not supported yet!"); 2424 case TargetLowering::Legal: 2425 // If this is an unaligned store and the target doesn't support it, 2426 // expand it. 2427 if (!TLI.allowsUnalignedMemoryAccesses()) { 2428 unsigned ABIAlignment = TLI.getTargetData()-> 2429 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT())); 2430 if (ST->getAlignment() < ABIAlignment) 2431 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2432 TLI); 2433 } 2434 break; 2435 case TargetLowering::Custom: 2436 Tmp1 = TLI.LowerOperation(Result, DAG); 2437 if (Tmp1.Val) Result = Tmp1; 2438 break; 2439 case TargetLowering::Promote: 2440 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 2441 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2442 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2443 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2444 ST->getSrcValue(), SVOffset, isVolatile, 2445 Alignment); 2446 break; 2447 } 2448 break; 2449 } 2450 case Promote: 2451 // Truncate the value and store the result. 2452 Tmp3 = PromoteOp(ST->getValue()); 2453 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2454 SVOffset, ST->getMemoryVT(), 2455 isVolatile, Alignment); 2456 break; 2457 2458 case Expand: 2459 unsigned IncrementSize = 0; 2460 SDOperand Lo, Hi; 2461 2462 // If this is a vector type, then we have to calculate the increment as 2463 // the product of the element size in bytes, and the number of elements 2464 // in the high half of the vector. 2465 if (MVT::isVector(ST->getValue().getValueType())) { 2466 SDNode *InVal = ST->getValue().Val; 2467 int InIx = ST->getValue().ResNo; 2468 MVT::ValueType InVT = InVal->getValueType(InIx); 2469 unsigned NumElems = MVT::getVectorNumElements(InVT); 2470 MVT::ValueType EVT = MVT::getVectorElementType(InVT); 2471 2472 // Figure out if there is a simple type corresponding to this Vector 2473 // type. If so, convert to the vector type. 2474 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2475 if (TLI.isTypeLegal(TVT)) { 2476 // Turn this into a normal store of the vector type. 2477 Tmp3 = LegalizeOp(ST->getValue()); 2478 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2479 SVOffset, isVolatile, Alignment); 2480 Result = LegalizeOp(Result); 2481 break; 2482 } else if (NumElems == 1) { 2483 // Turn this into a normal store of the scalar type. 2484 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2485 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2486 SVOffset, isVolatile, Alignment); 2487 // The scalarized value type may not be legal, e.g. it might require 2488 // promotion or expansion. Relegalize the scalar store. 2489 Result = LegalizeOp(Result); 2490 break; 2491 } else { 2492 SplitVectorOp(ST->getValue(), Lo, Hi); 2493 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) * 2494 MVT::getSizeInBits(EVT)/8; 2495 } 2496 } else { 2497 ExpandOp(ST->getValue(), Lo, Hi); 2498 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 2499 2500 if (TLI.isBigEndian()) 2501 std::swap(Lo, Hi); 2502 } 2503 2504 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2505 SVOffset, isVolatile, Alignment); 2506 2507 if (Hi.Val == NULL) { 2508 // Must be int <-> float one-to-one expansion. 2509 Result = Lo; 2510 break; 2511 } 2512 2513 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2514 DAG.getIntPtrConstant(IncrementSize)); 2515 assert(isTypeLegal(Tmp2.getValueType()) && 2516 "Pointers must be legal!"); 2517 SVOffset += IncrementSize; 2518 Alignment = MinAlign(Alignment, IncrementSize); 2519 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2520 SVOffset, isVolatile, Alignment); 2521 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2522 break; 2523 } 2524 } else { 2525 switch (getTypeAction(ST->getValue().getValueType())) { 2526 case Legal: 2527 Tmp3 = LegalizeOp(ST->getValue()); 2528 break; 2529 case Promote: 2530 // We can promote the value, the truncstore will still take care of it. 2531 Tmp3 = PromoteOp(ST->getValue()); 2532 break; 2533 case Expand: 2534 // Just store the low part. This may become a non-trunc store, so make 2535 // sure to use getTruncStore, not UpdateNodeOperands below. 2536 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2537 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2538 SVOffset, MVT::i8, isVolatile, Alignment); 2539 } 2540 2541 MVT::ValueType StVT = ST->getMemoryVT(); 2542 unsigned StWidth = MVT::getSizeInBits(StVT); 2543 2544 if (StWidth != MVT::getStoreSizeInBits(StVT)) { 2545 // Promote to a byte-sized store with upper bits zero if not 2546 // storing an integral number of bytes. For example, promote 2547 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2548 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT)); 2549 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); 2550 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2551 SVOffset, NVT, isVolatile, Alignment); 2552 } else if (StWidth & (StWidth - 1)) { 2553 // If not storing a power-of-2 number of bits, expand as two stores. 2554 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) && 2555 "Unsupported truncstore!"); 2556 unsigned RoundWidth = 1 << Log2_32(StWidth); 2557 assert(RoundWidth < StWidth); 2558 unsigned ExtraWidth = StWidth - RoundWidth; 2559 assert(ExtraWidth < RoundWidth); 2560 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2561 "Store size not an integral number of bytes!"); 2562 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth); 2563 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth); 2564 SDOperand Lo, Hi; 2565 unsigned IncrementSize; 2566 2567 if (TLI.isLittleEndian()) { 2568 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2569 // Store the bottom RoundWidth bits. 2570 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2571 SVOffset, RoundVT, 2572 isVolatile, Alignment); 2573 2574 // Store the remaining ExtraWidth bits. 2575 IncrementSize = RoundWidth / 8; 2576 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2577 DAG.getIntPtrConstant(IncrementSize)); 2578 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2579 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2580 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2581 SVOffset + IncrementSize, ExtraVT, isVolatile, 2582 MinAlign(Alignment, IncrementSize)); 2583 } else { 2584 // Big endian - avoid unaligned stores. 2585 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2586 // Store the top RoundWidth bits. 2587 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2588 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2589 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, 2590 RoundVT, isVolatile, Alignment); 2591 2592 // Store the remaining ExtraWidth bits. 2593 IncrementSize = RoundWidth / 8; 2594 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2595 DAG.getIntPtrConstant(IncrementSize)); 2596 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2597 SVOffset + IncrementSize, ExtraVT, isVolatile, 2598 MinAlign(Alignment, IncrementSize)); 2599 } 2600 2601 // The order of the stores doesn't matter. 2602 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2603 } else { 2604 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2605 Tmp2 != ST->getBasePtr()) 2606 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2607 ST->getOffset()); 2608 2609 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2610 default: assert(0 && "This action is not supported yet!"); 2611 case TargetLowering::Legal: 2612 // If this is an unaligned store and the target doesn't support it, 2613 // expand it. 2614 if (!TLI.allowsUnalignedMemoryAccesses()) { 2615 unsigned ABIAlignment = TLI.getTargetData()-> 2616 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT())); 2617 if (ST->getAlignment() < ABIAlignment) 2618 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2619 TLI); 2620 } 2621 break; 2622 case TargetLowering::Custom: 2623 Result = TLI.LowerOperation(Result, DAG); 2624 break; 2625 case Expand: 2626 // TRUNCSTORE:i16 i32 -> STORE i16 2627 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2628 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); 2629 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, 2630 isVolatile, Alignment); 2631 break; 2632 } 2633 } 2634 } 2635 break; 2636 } 2637 case ISD::PCMARKER: 2638 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2639 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2640 break; 2641 case ISD::STACKSAVE: 2642 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2643 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2644 Tmp1 = Result.getValue(0); 2645 Tmp2 = Result.getValue(1); 2646 2647 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2648 default: assert(0 && "This action is not supported yet!"); 2649 case TargetLowering::Legal: break; 2650 case TargetLowering::Custom: 2651 Tmp3 = TLI.LowerOperation(Result, DAG); 2652 if (Tmp3.Val) { 2653 Tmp1 = LegalizeOp(Tmp3); 2654 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2655 } 2656 break; 2657 case TargetLowering::Expand: 2658 // Expand to CopyFromReg if the target set 2659 // StackPointerRegisterToSaveRestore. 2660 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2661 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2662 Node->getValueType(0)); 2663 Tmp2 = Tmp1.getValue(1); 2664 } else { 2665 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2666 Tmp2 = Node->getOperand(0); 2667 } 2668 break; 2669 } 2670 2671 // Since stacksave produce two values, make sure to remember that we 2672 // legalized both of them. 2673 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2674 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2675 return Op.ResNo ? Tmp2 : Tmp1; 2676 2677 case ISD::STACKRESTORE: 2678 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2679 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2680 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2681 2682 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2683 default: assert(0 && "This action is not supported yet!"); 2684 case TargetLowering::Legal: break; 2685 case TargetLowering::Custom: 2686 Tmp1 = TLI.LowerOperation(Result, DAG); 2687 if (Tmp1.Val) Result = Tmp1; 2688 break; 2689 case TargetLowering::Expand: 2690 // Expand to CopyToReg if the target set 2691 // StackPointerRegisterToSaveRestore. 2692 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2693 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2694 } else { 2695 Result = Tmp1; 2696 } 2697 break; 2698 } 2699 break; 2700 2701 case ISD::READCYCLECOUNTER: 2702 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2703 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2704 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2705 Node->getValueType(0))) { 2706 default: assert(0 && "This action is not supported yet!"); 2707 case TargetLowering::Legal: 2708 Tmp1 = Result.getValue(0); 2709 Tmp2 = Result.getValue(1); 2710 break; 2711 case TargetLowering::Custom: 2712 Result = TLI.LowerOperation(Result, DAG); 2713 Tmp1 = LegalizeOp(Result.getValue(0)); 2714 Tmp2 = LegalizeOp(Result.getValue(1)); 2715 break; 2716 } 2717 2718 // Since rdcc produce two values, make sure to remember that we legalized 2719 // both of them. 2720 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2721 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2722 return Result; 2723 2724 case ISD::SELECT: 2725 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2726 case Expand: assert(0 && "It's impossible to expand bools"); 2727 case Legal: 2728 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2729 break; 2730 case Promote: { 2731 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2732 // Make sure the condition is either zero or one. 2733 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2734 if (!DAG.MaskedValueIsZero(Tmp1, 2735 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2736 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2737 break; 2738 } 2739 } 2740 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2741 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2742 2743 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2744 2745 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2746 default: assert(0 && "This action is not supported yet!"); 2747 case TargetLowering::Legal: break; 2748 case TargetLowering::Custom: { 2749 Tmp1 = TLI.LowerOperation(Result, DAG); 2750 if (Tmp1.Val) Result = Tmp1; 2751 break; 2752 } 2753 case TargetLowering::Expand: 2754 if (Tmp1.getOpcode() == ISD::SETCC) { 2755 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2756 Tmp2, Tmp3, 2757 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2758 } else { 2759 Result = DAG.getSelectCC(Tmp1, 2760 DAG.getConstant(0, Tmp1.getValueType()), 2761 Tmp2, Tmp3, ISD::SETNE); 2762 } 2763 break; 2764 case TargetLowering::Promote: { 2765 MVT::ValueType NVT = 2766 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2767 unsigned ExtOp, TruncOp; 2768 if (MVT::isVector(Tmp2.getValueType())) { 2769 ExtOp = ISD::BIT_CONVERT; 2770 TruncOp = ISD::BIT_CONVERT; 2771 } else if (MVT::isInteger(Tmp2.getValueType())) { 2772 ExtOp = ISD::ANY_EXTEND; 2773 TruncOp = ISD::TRUNCATE; 2774 } else { 2775 ExtOp = ISD::FP_EXTEND; 2776 TruncOp = ISD::FP_ROUND; 2777 } 2778 // Promote each of the values to the new type. 2779 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2780 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2781 // Perform the larger operation, then round down. 2782 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2783 if (TruncOp != ISD::FP_ROUND) 2784 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2785 else 2786 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2787 DAG.getIntPtrConstant(0)); 2788 break; 2789 } 2790 } 2791 break; 2792 case ISD::SELECT_CC: { 2793 Tmp1 = Node->getOperand(0); // LHS 2794 Tmp2 = Node->getOperand(1); // RHS 2795 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2796 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2797 SDOperand CC = Node->getOperand(4); 2798 2799 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2800 2801 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2802 // the LHS is a legal SETCC itself. In this case, we need to compare 2803 // the result against zero to select between true and false values. 2804 if (Tmp2.Val == 0) { 2805 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2806 CC = DAG.getCondCode(ISD::SETNE); 2807 } 2808 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2809 2810 // Everything is legal, see if we should expand this op or something. 2811 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2812 default: assert(0 && "This action is not supported yet!"); 2813 case TargetLowering::Legal: break; 2814 case TargetLowering::Custom: 2815 Tmp1 = TLI.LowerOperation(Result, DAG); 2816 if (Tmp1.Val) Result = Tmp1; 2817 break; 2818 } 2819 break; 2820 } 2821 case ISD::SETCC: 2822 Tmp1 = Node->getOperand(0); 2823 Tmp2 = Node->getOperand(1); 2824 Tmp3 = Node->getOperand(2); 2825 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2826 2827 // If we had to Expand the SetCC operands into a SELECT node, then it may 2828 // not always be possible to return a true LHS & RHS. In this case, just 2829 // return the value we legalized, returned in the LHS 2830 if (Tmp2.Val == 0) { 2831 Result = Tmp1; 2832 break; 2833 } 2834 2835 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2836 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2837 case TargetLowering::Custom: 2838 isCustom = true; 2839 // FALLTHROUGH. 2840 case TargetLowering::Legal: 2841 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2842 if (isCustom) { 2843 Tmp4 = TLI.LowerOperation(Result, DAG); 2844 if (Tmp4.Val) Result = Tmp4; 2845 } 2846 break; 2847 case TargetLowering::Promote: { 2848 // First step, figure out the appropriate operation to use. 2849 // Allow SETCC to not be supported for all legal data types 2850 // Mostly this targets FP 2851 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2852 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2853 2854 // Scan for the appropriate larger type to use. 2855 while (1) { 2856 NewInTy = (MVT::ValueType)(NewInTy+1); 2857 2858 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2859 "Fell off of the edge of the integer world"); 2860 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2861 "Fell off of the edge of the floating point world"); 2862 2863 // If the target supports SETCC of this type, use it. 2864 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2865 break; 2866 } 2867 if (MVT::isInteger(NewInTy)) 2868 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2869 else { 2870 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2871 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2872 } 2873 Tmp1 = LegalizeOp(Tmp1); 2874 Tmp2 = LegalizeOp(Tmp2); 2875 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2876 Result = LegalizeOp(Result); 2877 break; 2878 } 2879 case TargetLowering::Expand: 2880 // Expand a setcc node into a select_cc of the same condition, lhs, and 2881 // rhs that selects between const 1 (true) and const 0 (false). 2882 MVT::ValueType VT = Node->getValueType(0); 2883 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2884 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2885 Tmp3); 2886 break; 2887 } 2888 break; 2889 case ISD::VSETCC: { 2890 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2891 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2892 SDOperand CC = Node->getOperand(2); 2893 2894 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC); 2895 2896 // Everything is legal, see if we should expand this op or something. 2897 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) { 2898 default: assert(0 && "This action is not supported yet!"); 2899 case TargetLowering::Legal: break; 2900 case TargetLowering::Custom: 2901 Tmp1 = TLI.LowerOperation(Result, DAG); 2902 if (Tmp1.Val) Result = Tmp1; 2903 break; 2904 } 2905 break; 2906 } 2907 2908 case ISD::SHL_PARTS: 2909 case ISD::SRA_PARTS: 2910 case ISD::SRL_PARTS: { 2911 SmallVector<SDOperand, 8> Ops; 2912 bool Changed = false; 2913 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2914 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2915 Changed |= Ops.back() != Node->getOperand(i); 2916 } 2917 if (Changed) 2918 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2919 2920 switch (TLI.getOperationAction(Node->getOpcode(), 2921 Node->getValueType(0))) { 2922 default: assert(0 && "This action is not supported yet!"); 2923 case TargetLowering::Legal: break; 2924 case TargetLowering::Custom: 2925 Tmp1 = TLI.LowerOperation(Result, DAG); 2926 if (Tmp1.Val) { 2927 SDOperand Tmp2, RetVal(0, 0); 2928 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2929 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2930 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2931 if (i == Op.ResNo) 2932 RetVal = Tmp2; 2933 } 2934 assert(RetVal.Val && "Illegal result number"); 2935 return RetVal; 2936 } 2937 break; 2938 } 2939 2940 // Since these produce multiple values, make sure to remember that we 2941 // legalized all of them. 2942 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2943 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2944 return Result.getValue(Op.ResNo); 2945 } 2946 2947 // Binary operators 2948 case ISD::ADD: 2949 case ISD::SUB: 2950 case ISD::MUL: 2951 case ISD::MULHS: 2952 case ISD::MULHU: 2953 case ISD::UDIV: 2954 case ISD::SDIV: 2955 case ISD::AND: 2956 case ISD::OR: 2957 case ISD::XOR: 2958 case ISD::SHL: 2959 case ISD::SRL: 2960 case ISD::SRA: 2961 case ISD::FADD: 2962 case ISD::FSUB: 2963 case ISD::FMUL: 2964 case ISD::FDIV: 2965 case ISD::FPOW: 2966 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2967 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2968 case Expand: assert(0 && "Not possible"); 2969 case Legal: 2970 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2971 break; 2972 case Promote: 2973 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2974 break; 2975 } 2976 2977 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2978 2979 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2980 default: assert(0 && "BinOp legalize operation not supported"); 2981 case TargetLowering::Legal: break; 2982 case TargetLowering::Custom: 2983 Tmp1 = TLI.LowerOperation(Result, DAG); 2984 if (Tmp1.Val) Result = Tmp1; 2985 break; 2986 case TargetLowering::Expand: { 2987 MVT::ValueType VT = Op.getValueType(); 2988 2989 // See if multiply or divide can be lowered using two-result operations. 2990 SDVTList VTs = DAG.getVTList(VT, VT); 2991 if (Node->getOpcode() == ISD::MUL) { 2992 // We just need the low half of the multiply; try both the signed 2993 // and unsigned forms. If the target supports both SMUL_LOHI and 2994 // UMUL_LOHI, form a preference by checking which forms of plain 2995 // MULH it supports. 2996 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2997 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2998 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2999 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 3000 unsigned OpToUse = 0; 3001 if (HasSMUL_LOHI && !HasMULHS) { 3002 OpToUse = ISD::SMUL_LOHI; 3003 } else if (HasUMUL_LOHI && !HasMULHU) { 3004 OpToUse = ISD::UMUL_LOHI; 3005 } else if (HasSMUL_LOHI) { 3006 OpToUse = ISD::SMUL_LOHI; 3007 } else if (HasUMUL_LOHI) { 3008 OpToUse = ISD::UMUL_LOHI; 3009 } 3010 if (OpToUse) { 3011 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 3012 break; 3013 } 3014 } 3015 if (Node->getOpcode() == ISD::MULHS && 3016 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 3017 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3018 break; 3019 } 3020 if (Node->getOpcode() == ISD::MULHU && 3021 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 3022 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3023 break; 3024 } 3025 if (Node->getOpcode() == ISD::SDIV && 3026 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3027 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3028 break; 3029 } 3030 if (Node->getOpcode() == ISD::UDIV && 3031 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3032 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3033 break; 3034 } 3035 3036 // Check to see if we have a libcall for this operator. 3037 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3038 bool isSigned = false; 3039 switch (Node->getOpcode()) { 3040 case ISD::UDIV: 3041 case ISD::SDIV: 3042 if (VT == MVT::i32) { 3043 LC = Node->getOpcode() == ISD::UDIV 3044 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3045 isSigned = Node->getOpcode() == ISD::SDIV; 3046 } 3047 break; 3048 case ISD::FPOW: 3049 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3050 RTLIB::POW_PPCF128); 3051 break; 3052 default: break; 3053 } 3054 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3055 SDOperand Dummy; 3056 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3057 break; 3058 } 3059 3060 assert(MVT::isVector(Node->getValueType(0)) && 3061 "Cannot expand this binary operator!"); 3062 // Expand the operation into a bunch of nasty scalar code. 3063 Result = LegalizeOp(UnrollVectorOp(Op)); 3064 break; 3065 } 3066 case TargetLowering::Promote: { 3067 switch (Node->getOpcode()) { 3068 default: assert(0 && "Do not know how to promote this BinOp!"); 3069 case ISD::AND: 3070 case ISD::OR: 3071 case ISD::XOR: { 3072 MVT::ValueType OVT = Node->getValueType(0); 3073 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3074 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 3075 // Bit convert each of the values to the new type. 3076 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 3077 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 3078 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3079 // Bit convert the result back the original type. 3080 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 3081 break; 3082 } 3083 } 3084 } 3085 } 3086 break; 3087 3088 case ISD::SMUL_LOHI: 3089 case ISD::UMUL_LOHI: 3090 case ISD::SDIVREM: 3091 case ISD::UDIVREM: 3092 // These nodes will only be produced by target-specific lowering, so 3093 // they shouldn't be here if they aren't legal. 3094 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3095 "This must be legal!"); 3096 3097 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3098 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3099 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3100 break; 3101 3102 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3103 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3104 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3105 case Expand: assert(0 && "Not possible"); 3106 case Legal: 3107 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3108 break; 3109 case Promote: 3110 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3111 break; 3112 } 3113 3114 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3115 3116 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3117 default: assert(0 && "Operation not supported"); 3118 case TargetLowering::Custom: 3119 Tmp1 = TLI.LowerOperation(Result, DAG); 3120 if (Tmp1.Val) Result = Tmp1; 3121 break; 3122 case TargetLowering::Legal: break; 3123 case TargetLowering::Expand: { 3124 // If this target supports fabs/fneg natively and select is cheap, 3125 // do this efficiently. 3126 if (!TLI.isSelectExpensive() && 3127 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3128 TargetLowering::Legal && 3129 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3130 TargetLowering::Legal) { 3131 // Get the sign bit of the RHS. 3132 MVT::ValueType IVT = 3133 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3134 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 3135 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), 3136 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3137 // Get the absolute value of the result. 3138 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 3139 // Select between the nabs and abs value based on the sign bit of 3140 // the input. 3141 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 3142 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3143 AbsVal), 3144 AbsVal); 3145 Result = LegalizeOp(Result); 3146 break; 3147 } 3148 3149 // Otherwise, do bitwise ops! 3150 MVT::ValueType NVT = 3151 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3152 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3153 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 3154 Result = LegalizeOp(Result); 3155 break; 3156 } 3157 } 3158 break; 3159 3160 case ISD::ADDC: 3161 case ISD::SUBC: 3162 Tmp1 = LegalizeOp(Node->getOperand(0)); 3163 Tmp2 = LegalizeOp(Node->getOperand(1)); 3164 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3165 // Since this produces two values, make sure to remember that we legalized 3166 // both of them. 3167 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3168 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3169 return Result; 3170 3171 case ISD::ADDE: 3172 case ISD::SUBE: 3173 Tmp1 = LegalizeOp(Node->getOperand(0)); 3174 Tmp2 = LegalizeOp(Node->getOperand(1)); 3175 Tmp3 = LegalizeOp(Node->getOperand(2)); 3176 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3177 // Since this produces two values, make sure to remember that we legalized 3178 // both of them. 3179 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3180 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3181 return Result; 3182 3183 case ISD::BUILD_PAIR: { 3184 MVT::ValueType PairTy = Node->getValueType(0); 3185 // TODO: handle the case where the Lo and Hi operands are not of legal type 3186 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3187 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3188 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3189 case TargetLowering::Promote: 3190 case TargetLowering::Custom: 3191 assert(0 && "Cannot promote/custom this yet!"); 3192 case TargetLowering::Legal: 3193 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3194 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 3195 break; 3196 case TargetLowering::Expand: 3197 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 3198 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 3199 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 3200 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 3201 TLI.getShiftAmountTy())); 3202 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 3203 break; 3204 } 3205 break; 3206 } 3207 3208 case ISD::UREM: 3209 case ISD::SREM: 3210 case ISD::FREM: 3211 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3212 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3213 3214 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3215 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3216 case TargetLowering::Custom: 3217 isCustom = true; 3218 // FALLTHROUGH 3219 case TargetLowering::Legal: 3220 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3221 if (isCustom) { 3222 Tmp1 = TLI.LowerOperation(Result, DAG); 3223 if (Tmp1.Val) Result = Tmp1; 3224 } 3225 break; 3226 case TargetLowering::Expand: { 3227 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3228 bool isSigned = DivOpc == ISD::SDIV; 3229 MVT::ValueType VT = Node->getValueType(0); 3230 3231 // See if remainder can be lowered using two-result operations. 3232 SDVTList VTs = DAG.getVTList(VT, VT); 3233 if (Node->getOpcode() == ISD::SREM && 3234 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3235 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3236 break; 3237 } 3238 if (Node->getOpcode() == ISD::UREM && 3239 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3240 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3241 break; 3242 } 3243 3244 if (MVT::isInteger(VT)) { 3245 if (TLI.getOperationAction(DivOpc, VT) == 3246 TargetLowering::Legal) { 3247 // X % Y -> X-X/Y*Y 3248 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3249 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3250 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3251 } else if (MVT::isVector(VT)) { 3252 Result = LegalizeOp(UnrollVectorOp(Op)); 3253 } else { 3254 assert(VT == MVT::i32 && 3255 "Cannot expand this binary operator!"); 3256 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3257 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3258 SDOperand Dummy; 3259 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3260 } 3261 } else { 3262 assert(MVT::isFloatingPoint(VT) && 3263 "remainder op must have integer or floating-point type"); 3264 if (MVT::isVector(VT)) { 3265 Result = LegalizeOp(UnrollVectorOp(Op)); 3266 } else { 3267 // Floating point mod -> fmod libcall. 3268 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3269 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3270 SDOperand Dummy; 3271 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3272 } 3273 } 3274 break; 3275 } 3276 } 3277 break; 3278 case ISD::VAARG: { 3279 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3280 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3281 3282 MVT::ValueType VT = Node->getValueType(0); 3283 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3284 default: assert(0 && "This action is not supported yet!"); 3285 case TargetLowering::Custom: 3286 isCustom = true; 3287 // FALLTHROUGH 3288 case TargetLowering::Legal: 3289 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3290 Result = Result.getValue(0); 3291 Tmp1 = Result.getValue(1); 3292 3293 if (isCustom) { 3294 Tmp2 = TLI.LowerOperation(Result, DAG); 3295 if (Tmp2.Val) { 3296 Result = LegalizeOp(Tmp2); 3297 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3298 } 3299 } 3300 break; 3301 case TargetLowering::Expand: { 3302 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3303 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 3304 // Increment the pointer, VAList, to the next vaarg 3305 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3306 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3307 TLI.getPointerTy())); 3308 // Store the incremented VAList to the legalized pointer 3309 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 3310 // Load the actual argument out of the pointer VAList 3311 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3312 Tmp1 = LegalizeOp(Result.getValue(1)); 3313 Result = LegalizeOp(Result); 3314 break; 3315 } 3316 } 3317 // Since VAARG produces two values, make sure to remember that we 3318 // legalized both of them. 3319 AddLegalizedOperand(SDOperand(Node, 0), Result); 3320 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3321 return Op.ResNo ? Tmp1 : Result; 3322 } 3323 3324 case ISD::VACOPY: 3325 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3326 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3327 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3328 3329 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3330 default: assert(0 && "This action is not supported yet!"); 3331 case TargetLowering::Custom: 3332 isCustom = true; 3333 // FALLTHROUGH 3334 case TargetLowering::Legal: 3335 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3336 Node->getOperand(3), Node->getOperand(4)); 3337 if (isCustom) { 3338 Tmp1 = TLI.LowerOperation(Result, DAG); 3339 if (Tmp1.Val) Result = Tmp1; 3340 } 3341 break; 3342 case TargetLowering::Expand: 3343 // This defaults to loading a pointer from the input and storing it to the 3344 // output, returning the chain. 3345 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3346 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3347 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0); 3348 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0); 3349 break; 3350 } 3351 break; 3352 3353 case ISD::VAEND: 3354 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3355 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3356 3357 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3358 default: assert(0 && "This action is not supported yet!"); 3359 case TargetLowering::Custom: 3360 isCustom = true; 3361 // FALLTHROUGH 3362 case TargetLowering::Legal: 3363 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3364 if (isCustom) { 3365 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3366 if (Tmp1.Val) Result = Tmp1; 3367 } 3368 break; 3369 case TargetLowering::Expand: 3370 Result = Tmp1; // Default to a no-op, return the chain 3371 break; 3372 } 3373 break; 3374 3375 case ISD::VASTART: 3376 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3377 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3378 3379 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3380 3381 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3382 default: assert(0 && "This action is not supported yet!"); 3383 case TargetLowering::Legal: break; 3384 case TargetLowering::Custom: 3385 Tmp1 = TLI.LowerOperation(Result, DAG); 3386 if (Tmp1.Val) Result = Tmp1; 3387 break; 3388 } 3389 break; 3390 3391 case ISD::ROTL: 3392 case ISD::ROTR: 3393 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3394 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3395 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3396 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3397 default: 3398 assert(0 && "ROTL/ROTR legalize operation not supported"); 3399 break; 3400 case TargetLowering::Legal: 3401 break; 3402 case TargetLowering::Custom: 3403 Tmp1 = TLI.LowerOperation(Result, DAG); 3404 if (Tmp1.Val) Result = Tmp1; 3405 break; 3406 case TargetLowering::Promote: 3407 assert(0 && "Do not know how to promote ROTL/ROTR"); 3408 break; 3409 case TargetLowering::Expand: 3410 assert(0 && "Do not know how to expand ROTL/ROTR"); 3411 break; 3412 } 3413 break; 3414 3415 case ISD::BSWAP: 3416 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3417 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3418 case TargetLowering::Custom: 3419 assert(0 && "Cannot custom legalize this yet!"); 3420 case TargetLowering::Legal: 3421 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3422 break; 3423 case TargetLowering::Promote: { 3424 MVT::ValueType OVT = Tmp1.getValueType(); 3425 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3426 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); 3427 3428 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3429 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3430 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3431 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3432 break; 3433 } 3434 case TargetLowering::Expand: 3435 Result = ExpandBSWAP(Tmp1); 3436 break; 3437 } 3438 break; 3439 3440 case ISD::CTPOP: 3441 case ISD::CTTZ: 3442 case ISD::CTLZ: 3443 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3444 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3445 case TargetLowering::Custom: 3446 case TargetLowering::Legal: 3447 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3448 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3449 TargetLowering::Custom) { 3450 Tmp1 = TLI.LowerOperation(Result, DAG); 3451 if (Tmp1.Val) { 3452 Result = Tmp1; 3453 } 3454 } 3455 break; 3456 case TargetLowering::Promote: { 3457 MVT::ValueType OVT = Tmp1.getValueType(); 3458 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3459 3460 // Zero extend the argument. 3461 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3462 // Perform the larger operation, then subtract if needed. 3463 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3464 switch (Node->getOpcode()) { 3465 case ISD::CTPOP: 3466 Result = Tmp1; 3467 break; 3468 case ISD::CTTZ: 3469 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3470 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 3471 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 3472 ISD::SETEQ); 3473 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3474 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); 3475 break; 3476 case ISD::CTLZ: 3477 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3478 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3479 DAG.getConstant(MVT::getSizeInBits(NVT) - 3480 MVT::getSizeInBits(OVT), NVT)); 3481 break; 3482 } 3483 break; 3484 } 3485 case TargetLowering::Expand: 3486 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3487 break; 3488 } 3489 break; 3490 3491 // Unary operators 3492 case ISD::FABS: 3493 case ISD::FNEG: 3494 case ISD::FSQRT: 3495 case ISD::FSIN: 3496 case ISD::FCOS: 3497 Tmp1 = LegalizeOp(Node->getOperand(0)); 3498 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3499 case TargetLowering::Promote: 3500 case TargetLowering::Custom: 3501 isCustom = true; 3502 // FALLTHROUGH 3503 case TargetLowering::Legal: 3504 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3505 if (isCustom) { 3506 Tmp1 = TLI.LowerOperation(Result, DAG); 3507 if (Tmp1.Val) Result = Tmp1; 3508 } 3509 break; 3510 case TargetLowering::Expand: 3511 switch (Node->getOpcode()) { 3512 default: assert(0 && "Unreachable!"); 3513 case ISD::FNEG: 3514 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3515 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3516 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3517 break; 3518 case ISD::FABS: { 3519 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3520 MVT::ValueType VT = Node->getValueType(0); 3521 Tmp2 = DAG.getConstantFP(0.0, VT); 3522 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 3523 ISD::SETUGT); 3524 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3525 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3526 break; 3527 } 3528 case ISD::FSQRT: 3529 case ISD::FSIN: 3530 case ISD::FCOS: { 3531 MVT::ValueType VT = Node->getValueType(0); 3532 3533 // Expand unsupported unary vector operators by unrolling them. 3534 if (MVT::isVector(VT)) { 3535 Result = LegalizeOp(UnrollVectorOp(Op)); 3536 break; 3537 } 3538 3539 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3540 switch(Node->getOpcode()) { 3541 case ISD::FSQRT: 3542 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3543 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3544 break; 3545 case ISD::FSIN: 3546 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3547 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3548 break; 3549 case ISD::FCOS: 3550 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3551 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3552 break; 3553 default: assert(0 && "Unreachable!"); 3554 } 3555 SDOperand Dummy; 3556 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3557 break; 3558 } 3559 } 3560 break; 3561 } 3562 break; 3563 case ISD::FPOWI: { 3564 MVT::ValueType VT = Node->getValueType(0); 3565 3566 // Expand unsupported unary vector operators by unrolling them. 3567 if (MVT::isVector(VT)) { 3568 Result = LegalizeOp(UnrollVectorOp(Op)); 3569 break; 3570 } 3571 3572 // We always lower FPOWI into a libcall. No target support for it yet. 3573 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3574 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3575 SDOperand Dummy; 3576 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3577 break; 3578 } 3579 case ISD::BIT_CONVERT: 3580 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3581 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3582 Node->getValueType(0)); 3583 } else if (MVT::isVector(Op.getOperand(0).getValueType())) { 3584 // The input has to be a vector type, we have to either scalarize it, pack 3585 // it, or convert it based on whether the input vector type is legal. 3586 SDNode *InVal = Node->getOperand(0).Val; 3587 int InIx = Node->getOperand(0).ResNo; 3588 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 3589 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 3590 3591 // Figure out if there is a simple type corresponding to this Vector 3592 // type. If so, convert to the vector type. 3593 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3594 if (TLI.isTypeLegal(TVT)) { 3595 // Turn this into a bit convert of the vector input. 3596 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3597 LegalizeOp(Node->getOperand(0))); 3598 break; 3599 } else if (NumElems == 1) { 3600 // Turn this into a bit convert of the scalar input. 3601 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3602 ScalarizeVectorOp(Node->getOperand(0))); 3603 break; 3604 } else { 3605 // FIXME: UNIMP! Store then reload 3606 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3607 } 3608 } else { 3609 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3610 Node->getOperand(0).getValueType())) { 3611 default: assert(0 && "Unknown operation action!"); 3612 case TargetLowering::Expand: 3613 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3614 Node->getValueType(0)); 3615 break; 3616 case TargetLowering::Legal: 3617 Tmp1 = LegalizeOp(Node->getOperand(0)); 3618 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3619 break; 3620 } 3621 } 3622 break; 3623 3624 // Conversion operators. The source and destination have different types. 3625 case ISD::SINT_TO_FP: 3626 case ISD::UINT_TO_FP: { 3627 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3628 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3629 case Legal: 3630 switch (TLI.getOperationAction(Node->getOpcode(), 3631 Node->getOperand(0).getValueType())) { 3632 default: assert(0 && "Unknown operation action!"); 3633 case TargetLowering::Custom: 3634 isCustom = true; 3635 // FALLTHROUGH 3636 case TargetLowering::Legal: 3637 Tmp1 = LegalizeOp(Node->getOperand(0)); 3638 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3639 if (isCustom) { 3640 Tmp1 = TLI.LowerOperation(Result, DAG); 3641 if (Tmp1.Val) Result = Tmp1; 3642 } 3643 break; 3644 case TargetLowering::Expand: 3645 Result = ExpandLegalINT_TO_FP(isSigned, 3646 LegalizeOp(Node->getOperand(0)), 3647 Node->getValueType(0)); 3648 break; 3649 case TargetLowering::Promote: 3650 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3651 Node->getValueType(0), 3652 isSigned); 3653 break; 3654 } 3655 break; 3656 case Expand: 3657 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3658 Node->getValueType(0), Node->getOperand(0)); 3659 break; 3660 case Promote: 3661 Tmp1 = PromoteOp(Node->getOperand(0)); 3662 if (isSigned) { 3663 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3664 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3665 } else { 3666 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3667 Node->getOperand(0).getValueType()); 3668 } 3669 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3670 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3671 break; 3672 } 3673 break; 3674 } 3675 case ISD::TRUNCATE: 3676 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3677 case Legal: 3678 Tmp1 = LegalizeOp(Node->getOperand(0)); 3679 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3680 break; 3681 case Expand: 3682 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3683 3684 // Since the result is legal, we should just be able to truncate the low 3685 // part of the source. 3686 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3687 break; 3688 case Promote: 3689 Result = PromoteOp(Node->getOperand(0)); 3690 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3691 break; 3692 } 3693 break; 3694 3695 case ISD::FP_TO_SINT: 3696 case ISD::FP_TO_UINT: 3697 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3698 case Legal: 3699 Tmp1 = LegalizeOp(Node->getOperand(0)); 3700 3701 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3702 default: assert(0 && "Unknown operation action!"); 3703 case TargetLowering::Custom: 3704 isCustom = true; 3705 // FALLTHROUGH 3706 case TargetLowering::Legal: 3707 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3708 if (isCustom) { 3709 Tmp1 = TLI.LowerOperation(Result, DAG); 3710 if (Tmp1.Val) Result = Tmp1; 3711 } 3712 break; 3713 case TargetLowering::Promote: 3714 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3715 Node->getOpcode() == ISD::FP_TO_SINT); 3716 break; 3717 case TargetLowering::Expand: 3718 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3719 SDOperand True, False; 3720 MVT::ValueType VT = Node->getOperand(0).getValueType(); 3721 MVT::ValueType NVT = Node->getValueType(0); 3722 const uint64_t zero[] = {0, 0}; 3723 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero)); 3724 APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT)); 3725 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 3726 Tmp2 = DAG.getConstantFP(apf, VT); 3727 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)), 3728 Node->getOperand(0), Tmp2, ISD::SETLT); 3729 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3730 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3731 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3732 Tmp2)); 3733 False = DAG.getNode(ISD::XOR, NVT, False, 3734 DAG.getConstant(x, NVT)); 3735 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3736 break; 3737 } else { 3738 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3739 } 3740 break; 3741 } 3742 break; 3743 case Expand: { 3744 MVT::ValueType VT = Op.getValueType(); 3745 MVT::ValueType OVT = Node->getOperand(0).getValueType(); 3746 // Convert ppcf128 to i32 3747 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3748 if (Node->getOpcode() == ISD::FP_TO_SINT) { 3749 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 3750 Node->getOperand(0), DAG.getValueType(MVT::f64)); 3751 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 3752 DAG.getIntPtrConstant(1)); 3753 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 3754 } else { 3755 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3756 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3757 Tmp2 = DAG.getConstantFP(apf, OVT); 3758 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3759 // FIXME: generated code sucks. 3760 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3761 DAG.getNode(ISD::ADD, MVT::i32, 3762 DAG.getNode(ISD::FP_TO_SINT, VT, 3763 DAG.getNode(ISD::FSUB, OVT, 3764 Node->getOperand(0), Tmp2)), 3765 DAG.getConstant(0x80000000, MVT::i32)), 3766 DAG.getNode(ISD::FP_TO_SINT, VT, 3767 Node->getOperand(0)), 3768 DAG.getCondCode(ISD::SETGE)); 3769 } 3770 break; 3771 } 3772 // Convert f32 / f64 to i32 / i64 / i128. 3773 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3774 switch (Node->getOpcode()) { 3775 case ISD::FP_TO_SINT: { 3776 if (VT == MVT::i32) { 3777 if (OVT == MVT::f32) 3778 LC = RTLIB::FPTOSINT_F32_I32; 3779 else if (OVT == MVT::f64) 3780 LC = RTLIB::FPTOSINT_F64_I32; 3781 else 3782 assert(0 && "Unexpected i32-to-fp conversion!"); 3783 } else if (VT == MVT::i64) { 3784 if (OVT == MVT::f32) 3785 LC = RTLIB::FPTOSINT_F32_I64; 3786 else if (OVT == MVT::f64) 3787 LC = RTLIB::FPTOSINT_F64_I64; 3788 else if (OVT == MVT::f80) 3789 LC = RTLIB::FPTOSINT_F80_I64; 3790 else if (OVT == MVT::ppcf128) 3791 LC = RTLIB::FPTOSINT_PPCF128_I64; 3792 else 3793 assert(0 && "Unexpected i64-to-fp conversion!"); 3794 } else if (VT == MVT::i128) { 3795 if (OVT == MVT::f32) 3796 LC = RTLIB::FPTOSINT_F32_I128; 3797 else if (OVT == MVT::f64) 3798 LC = RTLIB::FPTOSINT_F64_I128; 3799 else if (OVT == MVT::f80) 3800 LC = RTLIB::FPTOSINT_F80_I128; 3801 else if (OVT == MVT::ppcf128) 3802 LC = RTLIB::FPTOSINT_PPCF128_I128; 3803 else 3804 assert(0 && "Unexpected i128-to-fp conversion!"); 3805 } else { 3806 assert(0 && "Unexpectd int-to-fp conversion!"); 3807 } 3808 break; 3809 } 3810 case ISD::FP_TO_UINT: { 3811 if (VT == MVT::i32) { 3812 if (OVT == MVT::f32) 3813 LC = RTLIB::FPTOUINT_F32_I32; 3814 else if (OVT == MVT::f64) 3815 LC = RTLIB::FPTOUINT_F64_I32; 3816 else if (OVT == MVT::f80) 3817 LC = RTLIB::FPTOUINT_F80_I32; 3818 else 3819 assert(0 && "Unexpected i32-to-fp conversion!"); 3820 } else if (VT == MVT::i64) { 3821 if (OVT == MVT::f32) 3822 LC = RTLIB::FPTOUINT_F32_I64; 3823 else if (OVT == MVT::f64) 3824 LC = RTLIB::FPTOUINT_F64_I64; 3825 else if (OVT == MVT::f80) 3826 LC = RTLIB::FPTOUINT_F80_I64; 3827 else if (OVT == MVT::ppcf128) 3828 LC = RTLIB::FPTOUINT_PPCF128_I64; 3829 else 3830 assert(0 && "Unexpected i64-to-fp conversion!"); 3831 } else if (VT == MVT::i128) { 3832 if (OVT == MVT::f32) 3833 LC = RTLIB::FPTOUINT_F32_I128; 3834 else if (OVT == MVT::f64) 3835 LC = RTLIB::FPTOUINT_F64_I128; 3836 else if (OVT == MVT::f80) 3837 LC = RTLIB::FPTOUINT_F80_I128; 3838 else if (OVT == MVT::ppcf128) 3839 LC = RTLIB::FPTOUINT_PPCF128_I128; 3840 else 3841 assert(0 && "Unexpected i128-to-fp conversion!"); 3842 } else { 3843 assert(0 && "Unexpectd int-to-fp conversion!"); 3844 } 3845 break; 3846 } 3847 default: assert(0 && "Unreachable!"); 3848 } 3849 SDOperand Dummy; 3850 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3851 break; 3852 } 3853 case Promote: 3854 Tmp1 = PromoteOp(Node->getOperand(0)); 3855 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3856 Result = LegalizeOp(Result); 3857 break; 3858 } 3859 break; 3860 3861 case ISD::FP_EXTEND: { 3862 MVT::ValueType DstVT = Op.getValueType(); 3863 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 3864 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3865 // The only other way we can lower this is to turn it into a STORE, 3866 // LOAD pair, targetting a temporary location (a stack slot). 3867 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 3868 break; 3869 } 3870 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3871 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3872 case Legal: 3873 Tmp1 = LegalizeOp(Node->getOperand(0)); 3874 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3875 break; 3876 case Promote: 3877 Tmp1 = PromoteOp(Node->getOperand(0)); 3878 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 3879 break; 3880 } 3881 break; 3882 } 3883 case ISD::FP_ROUND: { 3884 MVT::ValueType DstVT = Op.getValueType(); 3885 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 3886 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3887 if (SrcVT == MVT::ppcf128) { 3888 SDOperand Lo; 3889 ExpandOp(Node->getOperand(0), Lo, Result); 3890 // Round it the rest of the way (e.g. to f32) if needed. 3891 if (DstVT!=MVT::f64) 3892 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 3893 break; 3894 } 3895 // The only other way we can lower this is to turn it into a STORE, 3896 // LOAD pair, targetting a temporary location (a stack slot). 3897 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 3898 break; 3899 } 3900 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3901 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3902 case Legal: 3903 Tmp1 = LegalizeOp(Node->getOperand(0)); 3904 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3905 break; 3906 case Promote: 3907 Tmp1 = PromoteOp(Node->getOperand(0)); 3908 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 3909 Node->getOperand(1)); 3910 break; 3911 } 3912 break; 3913 } 3914 case ISD::ANY_EXTEND: 3915 case ISD::ZERO_EXTEND: 3916 case ISD::SIGN_EXTEND: 3917 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3918 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3919 case Legal: 3920 Tmp1 = LegalizeOp(Node->getOperand(0)); 3921 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3922 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3923 TargetLowering::Custom) { 3924 Tmp1 = TLI.LowerOperation(Result, DAG); 3925 if (Tmp1.Val) Result = Tmp1; 3926 } 3927 break; 3928 case Promote: 3929 switch (Node->getOpcode()) { 3930 case ISD::ANY_EXTEND: 3931 Tmp1 = PromoteOp(Node->getOperand(0)); 3932 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3933 break; 3934 case ISD::ZERO_EXTEND: 3935 Result = PromoteOp(Node->getOperand(0)); 3936 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3937 Result = DAG.getZeroExtendInReg(Result, 3938 Node->getOperand(0).getValueType()); 3939 break; 3940 case ISD::SIGN_EXTEND: 3941 Result = PromoteOp(Node->getOperand(0)); 3942 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3943 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3944 Result, 3945 DAG.getValueType(Node->getOperand(0).getValueType())); 3946 break; 3947 } 3948 } 3949 break; 3950 case ISD::FP_ROUND_INREG: 3951 case ISD::SIGN_EXTEND_INREG: { 3952 Tmp1 = LegalizeOp(Node->getOperand(0)); 3953 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3954 3955 // If this operation is not supported, convert it to a shl/shr or load/store 3956 // pair. 3957 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3958 default: assert(0 && "This action not supported for this op yet!"); 3959 case TargetLowering::Legal: 3960 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3961 break; 3962 case TargetLowering::Expand: 3963 // If this is an integer extend and shifts are supported, do that. 3964 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3965 // NOTE: we could fall back on load/store here too for targets without 3966 // SAR. However, it is doubtful that any exist. 3967 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3968 MVT::getSizeInBits(ExtraVT); 3969 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3970 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3971 Node->getOperand(0), ShiftCst); 3972 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3973 Result, ShiftCst); 3974 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3975 // The only way we can lower this is to turn it into a TRUNCSTORE, 3976 // EXTLOAD pair, targetting a temporary location (a stack slot). 3977 3978 // NOTE: there is a choice here between constantly creating new stack 3979 // slots and always reusing the same one. We currently always create 3980 // new ones, as reuse may inhibit scheduling. 3981 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 3982 Node->getValueType(0)); 3983 } else { 3984 assert(0 && "Unknown op"); 3985 } 3986 break; 3987 } 3988 break; 3989 } 3990 case ISD::TRAMPOLINE: { 3991 SDOperand Ops[6]; 3992 for (unsigned i = 0; i != 6; ++i) 3993 Ops[i] = LegalizeOp(Node->getOperand(i)); 3994 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3995 // The only option for this node is to custom lower it. 3996 Result = TLI.LowerOperation(Result, DAG); 3997 assert(Result.Val && "Should always custom lower!"); 3998 3999 // Since trampoline produces two values, make sure to remember that we 4000 // legalized both of them. 4001 Tmp1 = LegalizeOp(Result.getValue(1)); 4002 Result = LegalizeOp(Result); 4003 AddLegalizedOperand(SDOperand(Node, 0), Result); 4004 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 4005 return Op.ResNo ? Tmp1 : Result; 4006 } 4007 case ISD::FLT_ROUNDS_: { 4008 MVT::ValueType VT = Node->getValueType(0); 4009 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4010 default: assert(0 && "This action not supported for this op yet!"); 4011 case TargetLowering::Custom: 4012 Result = TLI.LowerOperation(Op, DAG); 4013 if (Result.Val) break; 4014 // Fall Thru 4015 case TargetLowering::Legal: 4016 // If this operation is not supported, lower it to constant 1 4017 Result = DAG.getConstant(1, VT); 4018 break; 4019 } 4020 break; 4021 } 4022 case ISD::TRAP: { 4023 MVT::ValueType VT = Node->getValueType(0); 4024 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4025 default: assert(0 && "This action not supported for this op yet!"); 4026 case TargetLowering::Legal: 4027 Tmp1 = LegalizeOp(Node->getOperand(0)); 4028 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4029 break; 4030 case TargetLowering::Custom: 4031 Result = TLI.LowerOperation(Op, DAG); 4032 if (Result.Val) break; 4033 // Fall Thru 4034 case TargetLowering::Expand: 4035 // If this operation is not supported, lower it to 'abort()' call 4036 Tmp1 = LegalizeOp(Node->getOperand(0)); 4037 TargetLowering::ArgListTy Args; 4038 std::pair<SDOperand,SDOperand> CallResult = 4039 TLI.LowerCallTo(Tmp1, Type::VoidTy, 4040 false, false, false, CallingConv::C, false, 4041 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 4042 Args, DAG); 4043 Result = CallResult.second; 4044 break; 4045 } 4046 break; 4047 } 4048 } 4049 4050 assert(Result.getValueType() == Op.getValueType() && 4051 "Bad legalization!"); 4052 4053 // Make sure that the generated code is itself legal. 4054 if (Result != Op) 4055 Result = LegalizeOp(Result); 4056 4057 // Note that LegalizeOp may be reentered even from single-use nodes, which 4058 // means that we always must cache transformed nodes. 4059 AddLegalizedOperand(Op, Result); 4060 return Result; 4061} 4062 4063/// PromoteOp - Given an operation that produces a value in an invalid type, 4064/// promote it to compute the value into a larger type. The produced value will 4065/// have the correct bits for the low portion of the register, but no guarantee 4066/// is made about the top bits: it may be zero, sign-extended, or garbage. 4067SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 4068 MVT::ValueType VT = Op.getValueType(); 4069 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4070 assert(getTypeAction(VT) == Promote && 4071 "Caller should expand or legalize operands that are not promotable!"); 4072 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 4073 "Cannot promote to smaller type!"); 4074 4075 SDOperand Tmp1, Tmp2, Tmp3; 4076 SDOperand Result; 4077 SDNode *Node = Op.Val; 4078 4079 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 4080 if (I != PromotedNodes.end()) return I->second; 4081 4082 switch (Node->getOpcode()) { 4083 case ISD::CopyFromReg: 4084 assert(0 && "CopyFromReg must be legal!"); 4085 default: 4086#ifndef NDEBUG 4087 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4088#endif 4089 assert(0 && "Do not know how to promote this operator!"); 4090 abort(); 4091 case ISD::UNDEF: 4092 Result = DAG.getNode(ISD::UNDEF, NVT); 4093 break; 4094 case ISD::Constant: 4095 if (VT != MVT::i1) 4096 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 4097 else 4098 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 4099 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4100 break; 4101 case ISD::ConstantFP: 4102 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 4103 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4104 break; 4105 4106 case ISD::SETCC: 4107 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0))) 4108 && "SetCC type is not legal??"); 4109 Result = DAG.getNode(ISD::SETCC, 4110 TLI.getSetCCResultType(Node->getOperand(0)), 4111 Node->getOperand(0), Node->getOperand(1), 4112 Node->getOperand(2)); 4113 break; 4114 4115 case ISD::TRUNCATE: 4116 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4117 case Legal: 4118 Result = LegalizeOp(Node->getOperand(0)); 4119 assert(Result.getValueType() >= NVT && 4120 "This truncation doesn't make sense!"); 4121 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 4122 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 4123 break; 4124 case Promote: 4125 // The truncation is not required, because we don't guarantee anything 4126 // about high bits anyway. 4127 Result = PromoteOp(Node->getOperand(0)); 4128 break; 4129 case Expand: 4130 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4131 // Truncate the low part of the expanded value to the result type 4132 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 4133 } 4134 break; 4135 case ISD::SIGN_EXTEND: 4136 case ISD::ZERO_EXTEND: 4137 case ISD::ANY_EXTEND: 4138 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4139 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4140 case Legal: 4141 // Input is legal? Just do extend all the way to the larger type. 4142 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4143 break; 4144 case Promote: 4145 // Promote the reg if it's smaller. 4146 Result = PromoteOp(Node->getOperand(0)); 4147 // The high bits are not guaranteed to be anything. Insert an extend. 4148 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4149 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4150 DAG.getValueType(Node->getOperand(0).getValueType())); 4151 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4152 Result = DAG.getZeroExtendInReg(Result, 4153 Node->getOperand(0).getValueType()); 4154 break; 4155 } 4156 break; 4157 case ISD::BIT_CONVERT: 4158 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4159 Node->getValueType(0)); 4160 Result = PromoteOp(Result); 4161 break; 4162 4163 case ISD::FP_EXTEND: 4164 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4165 case ISD::FP_ROUND: 4166 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4167 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4168 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4169 case Legal: 4170 if (Node->getConstantOperandVal(1) == 0) { 4171 // Input is legal? Do an FP_ROUND_INREG. 4172 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 4173 DAG.getValueType(VT)); 4174 } else { 4175 // Just remove the truncate, it isn't affecting the value. 4176 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 4177 Node->getOperand(1)); 4178 } 4179 break; 4180 } 4181 break; 4182 case ISD::SINT_TO_FP: 4183 case ISD::UINT_TO_FP: 4184 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4185 case Legal: 4186 // No extra round required here. 4187 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4188 break; 4189 4190 case Promote: 4191 Result = PromoteOp(Node->getOperand(0)); 4192 if (Node->getOpcode() == ISD::SINT_TO_FP) 4193 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4194 Result, 4195 DAG.getValueType(Node->getOperand(0).getValueType())); 4196 else 4197 Result = DAG.getZeroExtendInReg(Result, 4198 Node->getOperand(0).getValueType()); 4199 // No extra round required here. 4200 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 4201 break; 4202 case Expand: 4203 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4204 Node->getOperand(0)); 4205 // Round if we cannot tolerate excess precision. 4206 if (NoExcessFPPrecision) 4207 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4208 DAG.getValueType(VT)); 4209 break; 4210 } 4211 break; 4212 4213 case ISD::SIGN_EXTEND_INREG: 4214 Result = PromoteOp(Node->getOperand(0)); 4215 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4216 Node->getOperand(1)); 4217 break; 4218 case ISD::FP_TO_SINT: 4219 case ISD::FP_TO_UINT: 4220 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4221 case Legal: 4222 case Expand: 4223 Tmp1 = Node->getOperand(0); 4224 break; 4225 case Promote: 4226 // The input result is prerounded, so we don't have to do anything 4227 // special. 4228 Tmp1 = PromoteOp(Node->getOperand(0)); 4229 break; 4230 } 4231 // If we're promoting a UINT to a larger size, check to see if the new node 4232 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4233 // we can use that instead. This allows us to generate better code for 4234 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4235 // legal, such as PowerPC. 4236 if (Node->getOpcode() == ISD::FP_TO_UINT && 4237 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 4238 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 4239 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4240 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 4241 } else { 4242 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4243 } 4244 break; 4245 4246 case ISD::FABS: 4247 case ISD::FNEG: 4248 Tmp1 = PromoteOp(Node->getOperand(0)); 4249 assert(Tmp1.getValueType() == NVT); 4250 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4251 // NOTE: we do not have to do any extra rounding here for 4252 // NoExcessFPPrecision, because we know the input will have the appropriate 4253 // precision, and these operations don't modify precision at all. 4254 break; 4255 4256 case ISD::FSQRT: 4257 case ISD::FSIN: 4258 case ISD::FCOS: 4259 Tmp1 = PromoteOp(Node->getOperand(0)); 4260 assert(Tmp1.getValueType() == NVT); 4261 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4262 if (NoExcessFPPrecision) 4263 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4264 DAG.getValueType(VT)); 4265 break; 4266 4267 case ISD::FPOWI: { 4268 // Promote f32 powi to f64 powi. Note that this could insert a libcall 4269 // directly as well, which may be better. 4270 Tmp1 = PromoteOp(Node->getOperand(0)); 4271 assert(Tmp1.getValueType() == NVT); 4272 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 4273 if (NoExcessFPPrecision) 4274 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4275 DAG.getValueType(VT)); 4276 break; 4277 } 4278 4279 case ISD::ATOMIC_LCS: { 4280 Tmp2 = PromoteOp(Node->getOperand(2)); 4281 Tmp3 = PromoteOp(Node->getOperand(3)); 4282 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0), 4283 Node->getOperand(1), Tmp2, Tmp3, 4284 cast<AtomicSDNode>(Node)->getVT()); 4285 // Remember that we legalized the chain. 4286 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4287 break; 4288 } 4289 case ISD::ATOMIC_LAS: 4290 case ISD::ATOMIC_LSS: 4291 case ISD::ATOMIC_LOAD_AND: 4292 case ISD::ATOMIC_LOAD_OR: 4293 case ISD::ATOMIC_LOAD_XOR: 4294 case ISD::ATOMIC_LOAD_MIN: 4295 case ISD::ATOMIC_LOAD_MAX: 4296 case ISD::ATOMIC_LOAD_UMIN: 4297 case ISD::ATOMIC_LOAD_UMAX: 4298 case ISD::ATOMIC_SWAP: { 4299 Tmp2 = PromoteOp(Node->getOperand(2)); 4300 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0), 4301 Node->getOperand(1), Tmp2, 4302 cast<AtomicSDNode>(Node)->getVT()); 4303 // Remember that we legalized the chain. 4304 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4305 break; 4306 } 4307 4308 case ISD::AND: 4309 case ISD::OR: 4310 case ISD::XOR: 4311 case ISD::ADD: 4312 case ISD::SUB: 4313 case ISD::MUL: 4314 // The input may have strange things in the top bits of the registers, but 4315 // these operations don't care. They may have weird bits going out, but 4316 // that too is okay if they are integer operations. 4317 Tmp1 = PromoteOp(Node->getOperand(0)); 4318 Tmp2 = PromoteOp(Node->getOperand(1)); 4319 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4320 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4321 break; 4322 case ISD::FADD: 4323 case ISD::FSUB: 4324 case ISD::FMUL: 4325 Tmp1 = PromoteOp(Node->getOperand(0)); 4326 Tmp2 = PromoteOp(Node->getOperand(1)); 4327 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4328 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4329 4330 // Floating point operations will give excess precision that we may not be 4331 // able to tolerate. If we DO allow excess precision, just leave it, 4332 // otherwise excise it. 4333 // FIXME: Why would we need to round FP ops more than integer ones? 4334 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4335 if (NoExcessFPPrecision) 4336 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4337 DAG.getValueType(VT)); 4338 break; 4339 4340 case ISD::SDIV: 4341 case ISD::SREM: 4342 // These operators require that their input be sign extended. 4343 Tmp1 = PromoteOp(Node->getOperand(0)); 4344 Tmp2 = PromoteOp(Node->getOperand(1)); 4345 if (MVT::isInteger(NVT)) { 4346 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4347 DAG.getValueType(VT)); 4348 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4349 DAG.getValueType(VT)); 4350 } 4351 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4352 4353 // Perform FP_ROUND: this is probably overly pessimistic. 4354 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 4355 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4356 DAG.getValueType(VT)); 4357 break; 4358 case ISD::FDIV: 4359 case ISD::FREM: 4360 case ISD::FCOPYSIGN: 4361 // These operators require that their input be fp extended. 4362 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4363 case Expand: assert(0 && "not implemented"); 4364 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4365 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4366 } 4367 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4368 case Expand: assert(0 && "not implemented"); 4369 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4370 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4371 } 4372 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4373 4374 // Perform FP_ROUND: this is probably overly pessimistic. 4375 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4376 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4377 DAG.getValueType(VT)); 4378 break; 4379 4380 case ISD::UDIV: 4381 case ISD::UREM: 4382 // These operators require that their input be zero extended. 4383 Tmp1 = PromoteOp(Node->getOperand(0)); 4384 Tmp2 = PromoteOp(Node->getOperand(1)); 4385 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 4386 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4387 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4388 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4389 break; 4390 4391 case ISD::SHL: 4392 Tmp1 = PromoteOp(Node->getOperand(0)); 4393 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4394 break; 4395 case ISD::SRA: 4396 // The input value must be properly sign extended. 4397 Tmp1 = PromoteOp(Node->getOperand(0)); 4398 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4399 DAG.getValueType(VT)); 4400 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4401 break; 4402 case ISD::SRL: 4403 // The input value must be properly zero extended. 4404 Tmp1 = PromoteOp(Node->getOperand(0)); 4405 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4406 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4407 break; 4408 4409 case ISD::VAARG: 4410 Tmp1 = Node->getOperand(0); // Get the chain. 4411 Tmp2 = Node->getOperand(1); // Get the pointer. 4412 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4413 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4414 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 4415 } else { 4416 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4417 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 4418 // Increment the pointer, VAList, to the next vaarg 4419 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4420 DAG.getConstant(MVT::getSizeInBits(VT)/8, 4421 TLI.getPointerTy())); 4422 // Store the incremented VAList to the legalized pointer 4423 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 4424 // Load the actual argument out of the pointer VAList 4425 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4426 } 4427 // Remember that we legalized the chain. 4428 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4429 break; 4430 4431 case ISD::LOAD: { 4432 LoadSDNode *LD = cast<LoadSDNode>(Node); 4433 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4434 ? ISD::EXTLOAD : LD->getExtensionType(); 4435 Result = DAG.getExtLoad(ExtType, NVT, 4436 LD->getChain(), LD->getBasePtr(), 4437 LD->getSrcValue(), LD->getSrcValueOffset(), 4438 LD->getMemoryVT(), 4439 LD->isVolatile(), 4440 LD->getAlignment()); 4441 // Remember that we legalized the chain. 4442 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4443 break; 4444 } 4445 case ISD::SELECT: 4446 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4447 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4448 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 4449 break; 4450 case ISD::SELECT_CC: 4451 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4452 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4453 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4454 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4455 break; 4456 case ISD::BSWAP: 4457 Tmp1 = Node->getOperand(0); 4458 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4459 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4460 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4461 DAG.getConstant(MVT::getSizeInBits(NVT) - 4462 MVT::getSizeInBits(VT), 4463 TLI.getShiftAmountTy())); 4464 break; 4465 case ISD::CTPOP: 4466 case ISD::CTTZ: 4467 case ISD::CTLZ: 4468 // Zero extend the argument 4469 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4470 // Perform the larger operation, then subtract if needed. 4471 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4472 switch(Node->getOpcode()) { 4473 case ISD::CTPOP: 4474 Result = Tmp1; 4475 break; 4476 case ISD::CTTZ: 4477 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4478 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 4479 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 4480 ISD::SETEQ); 4481 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4482 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); 4483 break; 4484 case ISD::CTLZ: 4485 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4486 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4487 DAG.getConstant(MVT::getSizeInBits(NVT) - 4488 MVT::getSizeInBits(VT), NVT)); 4489 break; 4490 } 4491 break; 4492 case ISD::EXTRACT_SUBVECTOR: 4493 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4494 break; 4495 case ISD::EXTRACT_VECTOR_ELT: 4496 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4497 break; 4498 } 4499 4500 assert(Result.Val && "Didn't set a result!"); 4501 4502 // Make sure the result is itself legal. 4503 Result = LegalizeOp(Result); 4504 4505 // Remember that we promoted this! 4506 AddPromotedOperand(Op, Result); 4507 return Result; 4508} 4509 4510/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4511/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4512/// based on the vector type. The return type of this matches the element type 4513/// of the vector, which may not be legal for the target. 4514SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 4515 // We know that operand #0 is the Vec vector. If the index is a constant 4516 // or if the invec is a supported hardware type, we can use it. Otherwise, 4517 // lower to a store then an indexed load. 4518 SDOperand Vec = Op.getOperand(0); 4519 SDOperand Idx = Op.getOperand(1); 4520 4521 MVT::ValueType TVT = Vec.getValueType(); 4522 unsigned NumElems = MVT::getVectorNumElements(TVT); 4523 4524 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4525 default: assert(0 && "This action is not supported yet!"); 4526 case TargetLowering::Custom: { 4527 Vec = LegalizeOp(Vec); 4528 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4529 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 4530 if (Tmp3.Val) 4531 return Tmp3; 4532 break; 4533 } 4534 case TargetLowering::Legal: 4535 if (isTypeLegal(TVT)) { 4536 Vec = LegalizeOp(Vec); 4537 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4538 return Op; 4539 } 4540 break; 4541 case TargetLowering::Expand: 4542 break; 4543 } 4544 4545 if (NumElems == 1) { 4546 // This must be an access of the only element. Return it. 4547 Op = ScalarizeVectorOp(Vec); 4548 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4549 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 4550 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4551 SDOperand Lo, Hi; 4552 SplitVectorOp(Vec, Lo, Hi); 4553 if (CIdx->getValue() < NumLoElts) { 4554 Vec = Lo; 4555 } else { 4556 Vec = Hi; 4557 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts, 4558 Idx.getValueType()); 4559 } 4560 4561 // It's now an extract from the appropriate high or low part. Recurse. 4562 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4563 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4564 } else { 4565 // Store the value to a temporary stack slot, then LOAD the scalar 4566 // element back out. 4567 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4568 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4569 4570 // Add the offset to the index. 4571 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 4572 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4573 DAG.getConstant(EltSize, Idx.getValueType())); 4574 4575 if (MVT::getSizeInBits(Idx.getValueType()) > 4576 MVT::getSizeInBits(TLI.getPointerTy())) 4577 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4578 else 4579 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4580 4581 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4582 4583 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4584 } 4585 return Op; 4586} 4587 4588/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4589/// we assume the operation can be split if it is not already legal. 4590SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 4591 // We know that operand #0 is the Vec vector. For now we assume the index 4592 // is a constant and that the extracted result is a supported hardware type. 4593 SDOperand Vec = Op.getOperand(0); 4594 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 4595 4596 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); 4597 4598 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { 4599 // This must be an access of the desired vector length. Return it. 4600 return Vec; 4601 } 4602 4603 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4604 SDOperand Lo, Hi; 4605 SplitVectorOp(Vec, Lo, Hi); 4606 if (CIdx->getValue() < NumElems/2) { 4607 Vec = Lo; 4608 } else { 4609 Vec = Hi; 4610 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4611 } 4612 4613 // It's now an extract from the appropriate high or low part. Recurse. 4614 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4615 return ExpandEXTRACT_SUBVECTOR(Op); 4616} 4617 4618/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4619/// with condition CC on the current target. This usually involves legalizing 4620/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4621/// there may be no choice but to create a new SetCC node to represent the 4622/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4623/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 4624void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 4625 SDOperand &RHS, 4626 SDOperand &CC) { 4627 SDOperand Tmp1, Tmp2, Tmp3, Result; 4628 4629 switch (getTypeAction(LHS.getValueType())) { 4630 case Legal: 4631 Tmp1 = LegalizeOp(LHS); // LHS 4632 Tmp2 = LegalizeOp(RHS); // RHS 4633 break; 4634 case Promote: 4635 Tmp1 = PromoteOp(LHS); // LHS 4636 Tmp2 = PromoteOp(RHS); // RHS 4637 4638 // If this is an FP compare, the operands have already been extended. 4639 if (MVT::isInteger(LHS.getValueType())) { 4640 MVT::ValueType VT = LHS.getValueType(); 4641 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4642 4643 // Otherwise, we have to insert explicit sign or zero extends. Note 4644 // that we could insert sign extends for ALL conditions, but zero extend 4645 // is cheaper on many machines (an AND instead of two shifts), so prefer 4646 // it. 4647 switch (cast<CondCodeSDNode>(CC)->get()) { 4648 default: assert(0 && "Unknown integer comparison!"); 4649 case ISD::SETEQ: 4650 case ISD::SETNE: 4651 case ISD::SETUGE: 4652 case ISD::SETUGT: 4653 case ISD::SETULE: 4654 case ISD::SETULT: 4655 // ALL of these operations will work if we either sign or zero extend 4656 // the operands (including the unsigned comparisons!). Zero extend is 4657 // usually a simpler/cheaper operation, so prefer it. 4658 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4659 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4660 break; 4661 case ISD::SETGE: 4662 case ISD::SETGT: 4663 case ISD::SETLT: 4664 case ISD::SETLE: 4665 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4666 DAG.getValueType(VT)); 4667 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4668 DAG.getValueType(VT)); 4669 break; 4670 } 4671 } 4672 break; 4673 case Expand: { 4674 MVT::ValueType VT = LHS.getValueType(); 4675 if (VT == MVT::f32 || VT == MVT::f64) { 4676 // Expand into one or more soft-fp libcall(s). 4677 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 4678 switch (cast<CondCodeSDNode>(CC)->get()) { 4679 case ISD::SETEQ: 4680 case ISD::SETOEQ: 4681 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4682 break; 4683 case ISD::SETNE: 4684 case ISD::SETUNE: 4685 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4686 break; 4687 case ISD::SETGE: 4688 case ISD::SETOGE: 4689 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4690 break; 4691 case ISD::SETLT: 4692 case ISD::SETOLT: 4693 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4694 break; 4695 case ISD::SETLE: 4696 case ISD::SETOLE: 4697 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4698 break; 4699 case ISD::SETGT: 4700 case ISD::SETOGT: 4701 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4702 break; 4703 case ISD::SETUO: 4704 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4705 break; 4706 case ISD::SETO: 4707 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4708 break; 4709 default: 4710 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4711 switch (cast<CondCodeSDNode>(CC)->get()) { 4712 case ISD::SETONE: 4713 // SETONE = SETOLT | SETOGT 4714 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4715 // Fallthrough 4716 case ISD::SETUGT: 4717 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4718 break; 4719 case ISD::SETUGE: 4720 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4721 break; 4722 case ISD::SETULT: 4723 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4724 break; 4725 case ISD::SETULE: 4726 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4727 break; 4728 case ISD::SETUEQ: 4729 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4730 break; 4731 default: assert(0 && "Unsupported FP setcc!"); 4732 } 4733 } 4734 4735 SDOperand Dummy; 4736 Tmp1 = ExpandLibCall(LC1, 4737 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4738 false /*sign irrelevant*/, Dummy); 4739 Tmp2 = DAG.getConstant(0, MVT::i32); 4740 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4741 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4742 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 4743 CC); 4744 LHS = ExpandLibCall(LC2, 4745 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4746 false /*sign irrelevant*/, Dummy); 4747 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2, 4748 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4749 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4750 Tmp2 = SDOperand(); 4751 } 4752 LHS = Tmp1; 4753 RHS = Tmp2; 4754 return; 4755 } 4756 4757 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4758 ExpandOp(LHS, LHSLo, LHSHi); 4759 ExpandOp(RHS, RHSLo, RHSHi); 4760 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4761 4762 if (VT==MVT::ppcf128) { 4763 // FIXME: This generated code sucks. We want to generate 4764 // FCMP crN, hi1, hi2 4765 // BNE crN, L: 4766 // FCMP crN, lo1, lo2 4767 // The following can be improved, but not that much. 4768 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ); 4769 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode); 4770 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4771 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE); 4772 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode); 4773 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4774 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4775 Tmp2 = SDOperand(); 4776 break; 4777 } 4778 4779 switch (CCCode) { 4780 case ISD::SETEQ: 4781 case ISD::SETNE: 4782 if (RHSLo == RHSHi) 4783 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4784 if (RHSCST->isAllOnesValue()) { 4785 // Comparison to -1. 4786 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4787 Tmp2 = RHSLo; 4788 break; 4789 } 4790 4791 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4792 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4793 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4794 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4795 break; 4796 default: 4797 // If this is a comparison of the sign bit, just look at the top part. 4798 // X > -1, x < 0 4799 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4800 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4801 CST->isNullValue()) || // X < 0 4802 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4803 CST->isAllOnesValue())) { // X > -1 4804 Tmp1 = LHSHi; 4805 Tmp2 = RHSHi; 4806 break; 4807 } 4808 4809 // FIXME: This generated code sucks. 4810 ISD::CondCode LowCC; 4811 switch (CCCode) { 4812 default: assert(0 && "Unknown integer setcc!"); 4813 case ISD::SETLT: 4814 case ISD::SETULT: LowCC = ISD::SETULT; break; 4815 case ISD::SETGT: 4816 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4817 case ISD::SETLE: 4818 case ISD::SETULE: LowCC = ISD::SETULE; break; 4819 case ISD::SETGE: 4820 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4821 } 4822 4823 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4824 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4825 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4826 4827 // NOTE: on targets without efficient SELECT of bools, we can always use 4828 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4829 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4830 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, 4831 LowCC, false, DagCombineInfo); 4832 if (!Tmp1.Val) 4833 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 4834 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4835 CCCode, false, DagCombineInfo); 4836 if (!Tmp2.Val) 4837 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, 4838 RHSHi,CC); 4839 4840 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4841 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4842 if ((Tmp1C && Tmp1C->isNullValue()) || 4843 (Tmp2C && Tmp2C->isNullValue() && 4844 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4845 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4846 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 4847 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4848 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4849 // low part is known false, returns high part. 4850 // For LE / GE, if high part is known false, ignore the low part. 4851 // For LT / GT, if high part is known true, ignore the low part. 4852 Tmp1 = Tmp2; 4853 Tmp2 = SDOperand(); 4854 } else { 4855 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4856 ISD::SETEQ, false, DagCombineInfo); 4857 if (!Result.Val) 4858 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4859 ISD::SETEQ); 4860 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4861 Result, Tmp1, Tmp2)); 4862 Tmp1 = Result; 4863 Tmp2 = SDOperand(); 4864 } 4865 } 4866 } 4867 } 4868 LHS = Tmp1; 4869 RHS = Tmp2; 4870} 4871 4872/// EmitStackConvert - Emit a store/load combination to the stack. This stores 4873/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 4874/// a load from the stack slot to DestVT, extending it if needed. 4875/// The resultant code need not be legal. 4876SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, 4877 MVT::ValueType SlotVT, 4878 MVT::ValueType DestVT) { 4879 // Create the stack frame object. 4880 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); 4881 4882 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 4883 int SPFI = StackPtrFI->getIndex(); 4884 4885 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType()); 4886 unsigned SlotSize = MVT::getSizeInBits(SlotVT); 4887 unsigned DestSize = MVT::getSizeInBits(DestVT); 4888 4889 // Emit a store to the stack slot. Use a truncstore if the input value is 4890 // later than DestVT. 4891 SDOperand Store; 4892 if (SrcSize > SlotSize) 4893 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, 4894 PseudoSourceValue::getFixedStack(), 4895 SPFI, SlotVT); 4896 else { 4897 assert(SrcSize == SlotSize && "Invalid store"); 4898 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, 4899 PseudoSourceValue::getFixedStack(), 4900 SPFI, SlotVT); 4901 } 4902 4903 // Result is a load from the stack slot. 4904 if (SlotSize == DestSize) 4905 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4906 4907 assert(SlotSize < DestSize && "Unknown extension!"); 4908 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT); 4909} 4910 4911SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4912 // Create a vector sized/aligned stack slot, store the value to element #0, 4913 // then load the whole vector back out. 4914 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4915 4916 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 4917 int SPFI = StackPtrFI->getIndex(); 4918 4919 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4920 PseudoSourceValue::getFixedStack(), SPFI); 4921 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, 4922 PseudoSourceValue::getFixedStack(), SPFI); 4923} 4924 4925 4926/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4927/// support the operation, but do support the resultant vector type. 4928SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4929 4930 // If the only non-undef value is the low element, turn this into a 4931 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4932 unsigned NumElems = Node->getNumOperands(); 4933 bool isOnlyLowElement = true; 4934 SDOperand SplatValue = Node->getOperand(0); 4935 4936 // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t> 4937 // and use a bitmask instead of a list of elements. 4938 std::map<SDOperand, std::vector<unsigned> > Values; 4939 Values[SplatValue].push_back(0); 4940 bool isConstant = true; 4941 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4942 SplatValue.getOpcode() != ISD::UNDEF) 4943 isConstant = false; 4944 4945 for (unsigned i = 1; i < NumElems; ++i) { 4946 SDOperand V = Node->getOperand(i); 4947 Values[V].push_back(i); 4948 if (V.getOpcode() != ISD::UNDEF) 4949 isOnlyLowElement = false; 4950 if (SplatValue != V) 4951 SplatValue = SDOperand(0,0); 4952 4953 // If this isn't a constant element or an undef, we can't use a constant 4954 // pool load. 4955 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4956 V.getOpcode() != ISD::UNDEF) 4957 isConstant = false; 4958 } 4959 4960 if (isOnlyLowElement) { 4961 // If the low element is an undef too, then this whole things is an undef. 4962 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4963 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4964 // Otherwise, turn this into a scalar_to_vector node. 4965 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4966 Node->getOperand(0)); 4967 } 4968 4969 // If all elements are constants, create a load from the constant pool. 4970 if (isConstant) { 4971 MVT::ValueType VT = Node->getValueType(0); 4972 std::vector<Constant*> CV; 4973 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4974 if (ConstantFPSDNode *V = 4975 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4976 CV.push_back(ConstantFP::get(V->getValueAPF())); 4977 } else if (ConstantSDNode *V = 4978 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4979 CV.push_back(ConstantInt::get(V->getAPIntValue())); 4980 } else { 4981 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4982 const Type *OpNTy = 4983 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 4984 CV.push_back(UndefValue::get(OpNTy)); 4985 } 4986 } 4987 Constant *CP = ConstantVector::get(CV); 4988 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4989 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4990 PseudoSourceValue::getConstantPool(), 0); 4991 } 4992 4993 if (SplatValue.Val) { // Splat of one value? 4994 // Build the shuffle constant vector: <0, 0, 0, 0> 4995 MVT::ValueType MaskVT = 4996 MVT::getIntVectorWithNumElements(NumElems); 4997 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); 4998 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4999 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5000 &ZeroVec[0], ZeroVec.size()); 5001 5002 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 5003 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 5004 // Get the splatted value into the low element of a vector register. 5005 SDOperand LowValVec = 5006 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 5007 5008 // Return shuffle(LowValVec, undef, <0,0,0,0>) 5009 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 5010 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 5011 SplatMask); 5012 } 5013 } 5014 5015 // If there are only two unique elements, we may be able to turn this into a 5016 // vector shuffle. 5017 if (Values.size() == 2) { 5018 // Get the two values in deterministic order. 5019 SDOperand Val1 = Node->getOperand(1); 5020 SDOperand Val2; 5021 std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin(); 5022 if (MI->first != Val1) 5023 Val2 = MI->first; 5024 else 5025 Val2 = (++MI)->first; 5026 5027 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our 5028 // vector shuffle has the undef vector on the RHS. 5029 if (Val1.getOpcode() == ISD::UNDEF) 5030 std::swap(Val1, Val2); 5031 5032 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 5033 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5034 MVT::ValueType MaskEltVT = MVT::getVectorElementType(MaskVT); 5035 std::vector<SDOperand> MaskVec(NumElems); 5036 5037 // Set elements of the shuffle mask for Val1. 5038 std::vector<unsigned> &Val1Elts = Values[Val1]; 5039 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 5040 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT); 5041 5042 // Set elements of the shuffle mask for Val2. 5043 std::vector<unsigned> &Val2Elts = Values[Val2]; 5044 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 5045 if (Val2.getOpcode() != ISD::UNDEF) 5046 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); 5047 else 5048 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); 5049 5050 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5051 &MaskVec[0], MaskVec.size()); 5052 5053 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 5054 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 5055 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 5056 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); 5057 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); 5058 SDOperand Ops[] = { Val1, Val2, ShuffleMask }; 5059 5060 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 5061 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); 5062 } 5063 } 5064 5065 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5066 // aligned object on the stack, store each element into it, then load 5067 // the result as a vector. 5068 MVT::ValueType VT = Node->getValueType(0); 5069 // Create the stack frame object. 5070 SDOperand FIPtr = DAG.CreateStackTemporary(VT); 5071 5072 // Emit a store of each element to the stack slot. 5073 SmallVector<SDOperand, 8> Stores; 5074 unsigned TypeByteSize = 5075 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 5076 // Store (in the right endianness) the elements to memory. 5077 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5078 // Ignore undef elements. 5079 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5080 5081 unsigned Offset = TypeByteSize*i; 5082 5083 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5084 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 5085 5086 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 5087 NULL, 0)); 5088 } 5089 5090 SDOperand StoreChain; 5091 if (!Stores.empty()) // Not all undef elements? 5092 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5093 &Stores[0], Stores.size()); 5094 else 5095 StoreChain = DAG.getEntryNode(); 5096 5097 // Result is a load from the stack slot. 5098 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 5099} 5100 5101void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5102 SDOperand Op, SDOperand Amt, 5103 SDOperand &Lo, SDOperand &Hi) { 5104 // Expand the subcomponents. 5105 SDOperand LHSL, LHSH; 5106 ExpandOp(Op, LHSL, LHSH); 5107 5108 SDOperand Ops[] = { LHSL, LHSH, Amt }; 5109 MVT::ValueType VT = LHSL.getValueType(); 5110 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5111 Hi = Lo.getValue(1); 5112} 5113 5114 5115/// ExpandShift - Try to find a clever way to expand this shift operation out to 5116/// smaller elements. If we can't find a way that is more efficient than a 5117/// libcall on this target, return false. Otherwise, return true with the 5118/// low-parts expanded into Lo and Hi. 5119bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 5120 SDOperand &Lo, SDOperand &Hi) { 5121 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5122 "This is not a shift!"); 5123 5124 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5125 SDOperand ShAmt = LegalizeOp(Amt); 5126 MVT::ValueType ShTy = ShAmt.getValueType(); 5127 unsigned ShBits = MVT::getSizeInBits(ShTy); 5128 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 5129 unsigned NVTBits = MVT::getSizeInBits(NVT); 5130 5131 // Handle the case when Amt is an immediate. 5132 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 5133 unsigned Cst = CN->getValue(); 5134 // Expand the incoming operand to be shifted, so that we have its parts 5135 SDOperand InL, InH; 5136 ExpandOp(Op, InL, InH); 5137 switch(Opc) { 5138 case ISD::SHL: 5139 if (Cst > VTBits) { 5140 Lo = DAG.getConstant(0, NVT); 5141 Hi = DAG.getConstant(0, NVT); 5142 } else if (Cst > NVTBits) { 5143 Lo = DAG.getConstant(0, NVT); 5144 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5145 } else if (Cst == NVTBits) { 5146 Lo = DAG.getConstant(0, NVT); 5147 Hi = InL; 5148 } else { 5149 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 5150 Hi = DAG.getNode(ISD::OR, NVT, 5151 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 5152 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 5153 } 5154 return true; 5155 case ISD::SRL: 5156 if (Cst > VTBits) { 5157 Lo = DAG.getConstant(0, NVT); 5158 Hi = DAG.getConstant(0, NVT); 5159 } else if (Cst > NVTBits) { 5160 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5161 Hi = DAG.getConstant(0, NVT); 5162 } else if (Cst == NVTBits) { 5163 Lo = InH; 5164 Hi = DAG.getConstant(0, NVT); 5165 } else { 5166 Lo = DAG.getNode(ISD::OR, NVT, 5167 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5168 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5169 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 5170 } 5171 return true; 5172 case ISD::SRA: 5173 if (Cst > VTBits) { 5174 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 5175 DAG.getConstant(NVTBits-1, ShTy)); 5176 } else if (Cst > NVTBits) { 5177 Lo = DAG.getNode(ISD::SRA, NVT, InH, 5178 DAG.getConstant(Cst-NVTBits, ShTy)); 5179 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5180 DAG.getConstant(NVTBits-1, ShTy)); 5181 } else if (Cst == NVTBits) { 5182 Lo = InH; 5183 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5184 DAG.getConstant(NVTBits-1, ShTy)); 5185 } else { 5186 Lo = DAG.getNode(ISD::OR, NVT, 5187 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5188 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5189 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 5190 } 5191 return true; 5192 } 5193 } 5194 5195 // Okay, the shift amount isn't constant. However, if we can tell that it is 5196 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5197 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5198 APInt KnownZero, KnownOne; 5199 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5200 5201 // If we know that if any of the high bits of the shift amount are one, then 5202 // we can do this as a couple of simple shifts. 5203 if (KnownOne.intersects(Mask)) { 5204 // Mask out the high bit, which we know is set. 5205 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 5206 DAG.getConstant(~Mask, Amt.getValueType())); 5207 5208 // Expand the incoming operand to be shifted, so that we have its parts 5209 SDOperand InL, InH; 5210 ExpandOp(Op, InL, InH); 5211 switch(Opc) { 5212 case ISD::SHL: 5213 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5214 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 5215 return true; 5216 case ISD::SRL: 5217 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5218 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 5219 return true; 5220 case ISD::SRA: 5221 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 5222 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5223 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 5224 return true; 5225 } 5226 } 5227 5228 // If we know that the high bits of the shift amount are all zero, then we can 5229 // do this as a couple of simple shifts. 5230 if ((KnownZero & Mask) == Mask) { 5231 // Compute 32-amt. 5232 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 5233 DAG.getConstant(NVTBits, Amt.getValueType()), 5234 Amt); 5235 5236 // Expand the incoming operand to be shifted, so that we have its parts 5237 SDOperand InL, InH; 5238 ExpandOp(Op, InL, InH); 5239 switch(Opc) { 5240 case ISD::SHL: 5241 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 5242 Hi = DAG.getNode(ISD::OR, NVT, 5243 DAG.getNode(ISD::SHL, NVT, InH, Amt), 5244 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 5245 return true; 5246 case ISD::SRL: 5247 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 5248 Lo = DAG.getNode(ISD::OR, NVT, 5249 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5250 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5251 return true; 5252 case ISD::SRA: 5253 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 5254 Lo = DAG.getNode(ISD::OR, NVT, 5255 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5256 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5257 return true; 5258 } 5259 } 5260 5261 return false; 5262} 5263 5264 5265// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5266// does not fit into a register, return the lo part and set the hi part to the 5267// by-reg argument. If it does fit into a single register, return the result 5268// and leave the Hi part unset. 5269SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 5270 bool isSigned, SDOperand &Hi) { 5271 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5272 // The input chain to this libcall is the entry node of the function. 5273 // Legalizing the call will automatically add the previous call to the 5274 // dependence. 5275 SDOperand InChain = DAG.getEntryNode(); 5276 5277 TargetLowering::ArgListTy Args; 5278 TargetLowering::ArgListEntry Entry; 5279 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5280 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 5281 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 5282 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5283 Entry.isSExt = isSigned; 5284 Entry.isZExt = !isSigned; 5285 Args.push_back(Entry); 5286 } 5287 SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 5288 TLI.getPointerTy()); 5289 5290 // Splice the libcall in wherever FindInputOutputChains tells us to. 5291 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 5292 std::pair<SDOperand,SDOperand> CallInfo = 5293 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C, 5294 false, Callee, Args, DAG); 5295 5296 // Legalize the call sequence, starting with the chain. This will advance 5297 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5298 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5299 LegalizeOp(CallInfo.second); 5300 SDOperand Result; 5301 switch (getTypeAction(CallInfo.first.getValueType())) { 5302 default: assert(0 && "Unknown thing"); 5303 case Legal: 5304 Result = CallInfo.first; 5305 break; 5306 case Expand: 5307 ExpandOp(CallInfo.first, Result, Hi); 5308 break; 5309 } 5310 return Result; 5311} 5312 5313 5314/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5315/// 5316SDOperand SelectionDAGLegalize:: 5317ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 5318 MVT::ValueType SourceVT = Source.getValueType(); 5319 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5320 5321 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. 5322 if (!isSigned && SourceVT != MVT::i32) { 5323 // The integer value loaded will be incorrectly if the 'sign bit' of the 5324 // incoming integer is set. To handle this, we dynamically test to see if 5325 // it is set, and, if so, add a fudge factor. 5326 SDOperand Hi; 5327 if (ExpandSource) { 5328 SDOperand Lo; 5329 ExpandOp(Source, Lo, Hi); 5330 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi); 5331 } else { 5332 // The comparison for the sign bit will use the entire operand. 5333 Hi = Source; 5334 } 5335 5336 // If this is unsigned, and not supported, first perform the conversion to 5337 // signed, then adjust the result if the sign bit is set. 5338 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source); 5339 5340 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 5341 DAG.getConstant(0, Hi.getValueType()), 5342 ISD::SETLT); 5343 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5344 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5345 SignSet, Four, Zero); 5346 uint64_t FF = 0x5f800000ULL; 5347 if (TLI.isLittleEndian()) FF <<= 32; 5348 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5349 5350 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5351 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5352 SDOperand FudgeInReg; 5353 if (DestTy == MVT::f32) 5354 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5355 PseudoSourceValue::getConstantPool(), 0); 5356 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) 5357 // FIXME: Avoid the extend by construction the right constantpool? 5358 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5359 CPIdx, 5360 PseudoSourceValue::getConstantPool(), 0, 5361 MVT::f32); 5362 else 5363 assert(0 && "Unexpected conversion"); 5364 5365 MVT::ValueType SCVT = SignedConv.getValueType(); 5366 if (SCVT != DestTy) { 5367 // Destination type needs to be expanded as well. The FADD now we are 5368 // constructing will be expanded into a libcall. 5369 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { 5370 assert(MVT::getSizeInBits(SCVT) * 2 == MVT::getSizeInBits(DestTy)); 5371 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, 5372 SignedConv, SignedConv.getValue(1)); 5373 } 5374 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5375 } 5376 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5377 } 5378 5379 // Check to see if the target has a custom way to lower this. If so, use it. 5380 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 5381 default: assert(0 && "This action not implemented for this operation!"); 5382 case TargetLowering::Legal: 5383 case TargetLowering::Expand: 5384 break; // This case is handled below. 5385 case TargetLowering::Custom: { 5386 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5387 Source), DAG); 5388 if (NV.Val) 5389 return LegalizeOp(NV); 5390 break; // The target decided this was legal after all 5391 } 5392 } 5393 5394 // Expand the source, then glue it back together for the call. We must expand 5395 // the source in case it is shared (this pass of legalize must traverse it). 5396 if (ExpandSource) { 5397 SDOperand SrcLo, SrcHi; 5398 ExpandOp(Source, SrcLo, SrcHi); 5399 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); 5400 } 5401 5402 RTLIB::Libcall LC; 5403 if (SourceVT == MVT::i32) { 5404 if (DestTy == MVT::f32) 5405 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 5406 else { 5407 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 5408 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 5409 } 5410 } else if (SourceVT == MVT::i64) { 5411 if (DestTy == MVT::f32) 5412 LC = RTLIB::SINTTOFP_I64_F32; 5413 else if (DestTy == MVT::f64) 5414 LC = RTLIB::SINTTOFP_I64_F64; 5415 else if (DestTy == MVT::f80) 5416 LC = RTLIB::SINTTOFP_I64_F80; 5417 else { 5418 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 5419 LC = RTLIB::SINTTOFP_I64_PPCF128; 5420 } 5421 } else if (SourceVT == MVT::i128) { 5422 if (DestTy == MVT::f32) 5423 LC = RTLIB::SINTTOFP_I128_F32; 5424 else if (DestTy == MVT::f64) 5425 LC = RTLIB::SINTTOFP_I128_F64; 5426 else if (DestTy == MVT::f80) 5427 LC = RTLIB::SINTTOFP_I128_F80; 5428 else { 5429 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 5430 LC = RTLIB::SINTTOFP_I128_PPCF128; 5431 } 5432 } else { 5433 assert(0 && "Unknown int value type"); 5434 } 5435 5436 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 5437 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5438 SDOperand HiPart; 5439 SDOperand Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart); 5440 if (Result.getValueType() != DestTy && HiPart.Val) 5441 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart); 5442 return Result; 5443} 5444 5445/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5446/// INT_TO_FP operation of the specified operand when the target requests that 5447/// we expand it. At this point, we know that the result and operand types are 5448/// legal for the target. 5449SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5450 SDOperand Op0, 5451 MVT::ValueType DestVT) { 5452 if (Op0.getValueType() == MVT::i32) { 5453 // simple 32-bit [signed|unsigned] integer to float/double expansion 5454 5455 // Get the stack frame index of a 8 byte buffer. 5456 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64); 5457 5458 // word offset constant for Hi/Lo address computation 5459 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5460 // set up Hi and Lo (into buffer) address based on endian 5461 SDOperand Hi = StackSlot; 5462 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5463 if (TLI.isLittleEndian()) 5464 std::swap(Hi, Lo); 5465 5466 // if signed map to unsigned space 5467 SDOperand Op0Mapped; 5468 if (isSigned) { 5469 // constant used to invert sign bit (signed to unsigned mapping) 5470 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5471 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5472 } else { 5473 Op0Mapped = Op0; 5474 } 5475 // store the lo of the constructed double - based on integer input 5476 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 5477 Op0Mapped, Lo, NULL, 0); 5478 // initial hi portion of constructed double 5479 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5480 // store the hi of the constructed double - biased exponent 5481 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5482 // load the constructed double 5483 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5484 // FP constant to bias correct the final result 5485 SDOperand Bias = DAG.getConstantFP(isSigned ? 5486 BitsToDouble(0x4330000080000000ULL) 5487 : BitsToDouble(0x4330000000000000ULL), 5488 MVT::f64); 5489 // subtract the bias 5490 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5491 // final result 5492 SDOperand Result; 5493 // handle final rounding 5494 if (DestVT == MVT::f64) { 5495 // do nothing 5496 Result = Sub; 5497 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) { 5498 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 5499 DAG.getIntPtrConstant(0)); 5500 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) { 5501 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5502 } 5503 return Result; 5504 } 5505 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5506 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5507 5508 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0, 5509 DAG.getConstant(0, Op0.getValueType()), 5510 ISD::SETLT); 5511 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5512 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5513 SignSet, Four, Zero); 5514 5515 // If the sign bit of the integer is set, the large number will be treated 5516 // as a negative number. To counteract this, the dynamic code adds an 5517 // offset depending on the data type. 5518 uint64_t FF; 5519 switch (Op0.getValueType()) { 5520 default: assert(0 && "Unsupported integer type!"); 5521 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5522 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5523 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5524 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5525 } 5526 if (TLI.isLittleEndian()) FF <<= 32; 5527 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5528 5529 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5530 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5531 SDOperand FudgeInReg; 5532 if (DestVT == MVT::f32) 5533 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5534 PseudoSourceValue::getConstantPool(), 0); 5535 else { 5536 FudgeInReg = 5537 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5538 DAG.getEntryNode(), CPIdx, 5539 PseudoSourceValue::getConstantPool(), 0, 5540 MVT::f32)); 5541 } 5542 5543 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5544} 5545 5546/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5547/// *INT_TO_FP operation of the specified operand when the target requests that 5548/// we promote it. At this point, we know that the result and operand types are 5549/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5550/// operation that takes a larger input. 5551SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 5552 MVT::ValueType DestVT, 5553 bool isSigned) { 5554 // First step, figure out the appropriate *INT_TO_FP operation to use. 5555 MVT::ValueType NewInTy = LegalOp.getValueType(); 5556 5557 unsigned OpToUse = 0; 5558 5559 // Scan for the appropriate larger type to use. 5560 while (1) { 5561 NewInTy = (MVT::ValueType)(NewInTy+1); 5562 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 5563 5564 // If the target supports SINT_TO_FP of this type, use it. 5565 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5566 default: break; 5567 case TargetLowering::Legal: 5568 if (!TLI.isTypeLegal(NewInTy)) 5569 break; // Can't use this datatype. 5570 // FALL THROUGH. 5571 case TargetLowering::Custom: 5572 OpToUse = ISD::SINT_TO_FP; 5573 break; 5574 } 5575 if (OpToUse) break; 5576 if (isSigned) continue; 5577 5578 // If the target supports UINT_TO_FP of this type, use it. 5579 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5580 default: break; 5581 case TargetLowering::Legal: 5582 if (!TLI.isTypeLegal(NewInTy)) 5583 break; // Can't use this datatype. 5584 // FALL THROUGH. 5585 case TargetLowering::Custom: 5586 OpToUse = ISD::UINT_TO_FP; 5587 break; 5588 } 5589 if (OpToUse) break; 5590 5591 // Otherwise, try a larger type. 5592 } 5593 5594 // Okay, we found the operation and type to use. Zero extend our input to the 5595 // desired type then run the operation on it. 5596 return DAG.getNode(OpToUse, DestVT, 5597 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5598 NewInTy, LegalOp)); 5599} 5600 5601/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5602/// FP_TO_*INT operation of the specified operand when the target requests that 5603/// we promote it. At this point, we know that the result and operand types are 5604/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5605/// operation that returns a larger result. 5606SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 5607 MVT::ValueType DestVT, 5608 bool isSigned) { 5609 // First step, figure out the appropriate FP_TO*INT operation to use. 5610 MVT::ValueType NewOutTy = DestVT; 5611 5612 unsigned OpToUse = 0; 5613 5614 // Scan for the appropriate larger type to use. 5615 while (1) { 5616 NewOutTy = (MVT::ValueType)(NewOutTy+1); 5617 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 5618 5619 // If the target supports FP_TO_SINT returning this type, use it. 5620 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5621 default: break; 5622 case TargetLowering::Legal: 5623 if (!TLI.isTypeLegal(NewOutTy)) 5624 break; // Can't use this datatype. 5625 // FALL THROUGH. 5626 case TargetLowering::Custom: 5627 OpToUse = ISD::FP_TO_SINT; 5628 break; 5629 } 5630 if (OpToUse) break; 5631 5632 // If the target supports FP_TO_UINT of this type, use it. 5633 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5634 default: break; 5635 case TargetLowering::Legal: 5636 if (!TLI.isTypeLegal(NewOutTy)) 5637 break; // Can't use this datatype. 5638 // FALL THROUGH. 5639 case TargetLowering::Custom: 5640 OpToUse = ISD::FP_TO_UINT; 5641 break; 5642 } 5643 if (OpToUse) break; 5644 5645 // Otherwise, try a larger type. 5646 } 5647 5648 5649 // Okay, we found the operation and type to use. 5650 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5651 5652 // If the operation produces an invalid type, it must be custom lowered. Use 5653 // the target lowering hooks to expand it. Just keep the low part of the 5654 // expanded operation, we know that we're truncating anyway. 5655 if (getTypeAction(NewOutTy) == Expand) { 5656 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0); 5657 assert(Operation.Val && "Didn't return anything"); 5658 } 5659 5660 // Truncate the result of the extended FP_TO_*INT operation to the desired 5661 // size. 5662 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5663} 5664 5665/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5666/// 5667SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 5668 MVT::ValueType VT = Op.getValueType(); 5669 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 5670 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5671 switch (VT) { 5672 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5673 case MVT::i16: 5674 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5675 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5676 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5677 case MVT::i32: 5678 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5679 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5680 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5681 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5682 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5683 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5684 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5685 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5686 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5687 case MVT::i64: 5688 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5689 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5690 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5691 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5692 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5693 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5694 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5695 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5696 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5697 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5698 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5699 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5700 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5701 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5702 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5703 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5704 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5705 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5706 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5707 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5708 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5709 } 5710} 5711 5712/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5713/// 5714SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 5715 switch (Opc) { 5716 default: assert(0 && "Cannot expand this yet!"); 5717 case ISD::CTPOP: { 5718 static const uint64_t mask[6] = { 5719 0x5555555555555555ULL, 0x3333333333333333ULL, 5720 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5721 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5722 }; 5723 MVT::ValueType VT = Op.getValueType(); 5724 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5725 unsigned len = MVT::getSizeInBits(VT); 5726 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5727 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5728 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 5729 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5730 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5731 DAG.getNode(ISD::AND, VT, 5732 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5733 } 5734 return Op; 5735 } 5736 case ISD::CTLZ: { 5737 // for now, we do this: 5738 // x = x | (x >> 1); 5739 // x = x | (x >> 2); 5740 // ... 5741 // x = x | (x >>16); 5742 // x = x | (x >>32); // for 64-bit input 5743 // return popcount(~x); 5744 // 5745 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5746 MVT::ValueType VT = Op.getValueType(); 5747 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5748 unsigned len = MVT::getSizeInBits(VT); 5749 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5750 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5751 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5752 } 5753 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5754 return DAG.getNode(ISD::CTPOP, VT, Op); 5755 } 5756 case ISD::CTTZ: { 5757 // for now, we use: { return popcount(~x & (x - 1)); } 5758 // unless the target has ctlz but not ctpop, in which case we use: 5759 // { return 32 - nlz(~x & (x-1)); } 5760 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5761 MVT::ValueType VT = Op.getValueType(); 5762 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 5763 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 5764 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5765 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5766 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5767 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5768 TLI.isOperationLegal(ISD::CTLZ, VT)) 5769 return DAG.getNode(ISD::SUB, VT, 5770 DAG.getConstant(MVT::getSizeInBits(VT), VT), 5771 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5772 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5773 } 5774 } 5775} 5776 5777/// ExpandOp - Expand the specified SDOperand into its two component pieces 5778/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5779/// LegalizeNodes map is filled in for any results that are not expanded, the 5780/// ExpandedNodes map is filled in for any results that are expanded, and the 5781/// Lo/Hi values are returned. 5782void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 5783 MVT::ValueType VT = Op.getValueType(); 5784 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 5785 SDNode *Node = Op.Val; 5786 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5787 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 5788 MVT::isVector(VT)) && 5789 "Cannot expand to FP value or to larger int value!"); 5790 5791 // See if we already expanded it. 5792 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5793 = ExpandedNodes.find(Op); 5794 if (I != ExpandedNodes.end()) { 5795 Lo = I->second.first; 5796 Hi = I->second.second; 5797 return; 5798 } 5799 5800 switch (Node->getOpcode()) { 5801 case ISD::CopyFromReg: 5802 assert(0 && "CopyFromReg must be legal!"); 5803 case ISD::FP_ROUND_INREG: 5804 if (VT == MVT::ppcf128 && 5805 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5806 TargetLowering::Custom) { 5807 SDOperand SrcLo, SrcHi, Src; 5808 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5809 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5810 SDOperand Result = TLI.LowerOperation( 5811 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5812 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5813 Lo = Result.Val->getOperand(0); 5814 Hi = Result.Val->getOperand(1); 5815 break; 5816 } 5817 // fall through 5818 default: 5819#ifndef NDEBUG 5820 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5821#endif 5822 assert(0 && "Do not know how to expand this operator!"); 5823 abort(); 5824 case ISD::EXTRACT_ELEMENT: 5825 ExpandOp(Node->getOperand(0), Lo, Hi); 5826 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 5827 return ExpandOp(Hi, Lo, Hi); 5828 return ExpandOp(Lo, Lo, Hi); 5829 case ISD::EXTRACT_VECTOR_ELT: 5830 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5831 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5832 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5833 return ExpandOp(Lo, Lo, Hi); 5834 case ISD::UNDEF: 5835 NVT = TLI.getTypeToExpandTo(VT); 5836 Lo = DAG.getNode(ISD::UNDEF, NVT); 5837 Hi = DAG.getNode(ISD::UNDEF, NVT); 5838 break; 5839 case ISD::Constant: { 5840 unsigned NVTBits = MVT::getSizeInBits(NVT); 5841 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 5842 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 5843 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 5844 break; 5845 } 5846 case ISD::ConstantFP: { 5847 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5848 if (CFP->getValueType(0) == MVT::ppcf128) { 5849 APInt api = CFP->getValueAPF().convertToAPInt(); 5850 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5851 MVT::f64); 5852 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5853 MVT::f64); 5854 break; 5855 } 5856 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5857 if (getTypeAction(Lo.getValueType()) == Expand) 5858 ExpandOp(Lo, Lo, Hi); 5859 break; 5860 } 5861 case ISD::BUILD_PAIR: 5862 // Return the operands. 5863 Lo = Node->getOperand(0); 5864 Hi = Node->getOperand(1); 5865 break; 5866 5867 case ISD::MERGE_VALUES: 5868 if (Node->getNumValues() == 1) { 5869 ExpandOp(Op.getOperand(0), Lo, Hi); 5870 break; 5871 } 5872 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5873 assert(Op.ResNo == 0 && Node->getNumValues() == 2 && 5874 Op.getValue(1).getValueType() == MVT::Other && 5875 "unhandled MERGE_VALUES"); 5876 ExpandOp(Op.getOperand(0), Lo, Hi); 5877 // Remember that we legalized the chain. 5878 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5879 break; 5880 5881 case ISD::SIGN_EXTEND_INREG: 5882 ExpandOp(Node->getOperand(0), Lo, Hi); 5883 // sext_inreg the low part if needed. 5884 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5885 5886 // The high part gets the sign extension from the lo-part. This handles 5887 // things like sextinreg V:i64 from i8. 5888 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5889 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 5890 TLI.getShiftAmountTy())); 5891 break; 5892 5893 case ISD::BSWAP: { 5894 ExpandOp(Node->getOperand(0), Lo, Hi); 5895 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5896 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5897 Lo = TempLo; 5898 break; 5899 } 5900 5901 case ISD::CTPOP: 5902 ExpandOp(Node->getOperand(0), Lo, Hi); 5903 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5904 DAG.getNode(ISD::CTPOP, NVT, Lo), 5905 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5906 Hi = DAG.getConstant(0, NVT); 5907 break; 5908 5909 case ISD::CTLZ: { 5910 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5911 ExpandOp(Node->getOperand(0), Lo, Hi); 5912 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5913 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5914 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC, 5915 ISD::SETNE); 5916 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5917 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5918 5919 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5920 Hi = DAG.getConstant(0, NVT); 5921 break; 5922 } 5923 5924 case ISD::CTTZ: { 5925 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5926 ExpandOp(Node->getOperand(0), Lo, Hi); 5927 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5928 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5929 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC, 5930 ISD::SETNE); 5931 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5932 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5933 5934 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5935 Hi = DAG.getConstant(0, NVT); 5936 break; 5937 } 5938 5939 case ISD::VAARG: { 5940 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5941 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5942 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5943 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5944 5945 // Remember that we legalized the chain. 5946 Hi = LegalizeOp(Hi); 5947 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5948 if (TLI.isBigEndian()) 5949 std::swap(Lo, Hi); 5950 break; 5951 } 5952 5953 case ISD::LOAD: { 5954 LoadSDNode *LD = cast<LoadSDNode>(Node); 5955 SDOperand Ch = LD->getChain(); // Legalize the chain. 5956 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5957 ISD::LoadExtType ExtType = LD->getExtensionType(); 5958 int SVOffset = LD->getSrcValueOffset(); 5959 unsigned Alignment = LD->getAlignment(); 5960 bool isVolatile = LD->isVolatile(); 5961 5962 if (ExtType == ISD::NON_EXTLOAD) { 5963 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5964 isVolatile, Alignment); 5965 if (VT == MVT::f32 || VT == MVT::f64) { 5966 // f32->i32 or f64->i64 one to one expansion. 5967 // Remember that we legalized the chain. 5968 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5969 // Recursively expand the new load. 5970 if (getTypeAction(NVT) == Expand) 5971 ExpandOp(Lo, Lo, Hi); 5972 break; 5973 } 5974 5975 // Increment the pointer to the other half. 5976 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 5977 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5978 DAG.getIntPtrConstant(IncrementSize)); 5979 SVOffset += IncrementSize; 5980 Alignment = MinAlign(Alignment, IncrementSize); 5981 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5982 isVolatile, Alignment); 5983 5984 // Build a factor node to remember that this load is independent of the 5985 // other one. 5986 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5987 Hi.getValue(1)); 5988 5989 // Remember that we legalized the chain. 5990 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5991 if (TLI.isBigEndian()) 5992 std::swap(Lo, Hi); 5993 } else { 5994 MVT::ValueType EVT = LD->getMemoryVT(); 5995 5996 if ((VT == MVT::f64 && EVT == MVT::f32) || 5997 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 5998 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5999 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 6000 SVOffset, isVolatile, Alignment); 6001 // Remember that we legalized the chain. 6002 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 6003 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 6004 break; 6005 } 6006 6007 if (EVT == NVT) 6008 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 6009 SVOffset, isVolatile, Alignment); 6010 else 6011 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 6012 SVOffset, EVT, isVolatile, 6013 Alignment); 6014 6015 // Remember that we legalized the chain. 6016 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 6017 6018 if (ExtType == ISD::SEXTLOAD) { 6019 // The high part is obtained by SRA'ing all but one of the bits of the 6020 // lo part. 6021 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 6022 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6023 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6024 } else if (ExtType == ISD::ZEXTLOAD) { 6025 // The high part is just a zero. 6026 Hi = DAG.getConstant(0, NVT); 6027 } else /* if (ExtType == ISD::EXTLOAD) */ { 6028 // The high part is undefined. 6029 Hi = DAG.getNode(ISD::UNDEF, NVT); 6030 } 6031 } 6032 break; 6033 } 6034 case ISD::AND: 6035 case ISD::OR: 6036 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 6037 SDOperand LL, LH, RL, RH; 6038 ExpandOp(Node->getOperand(0), LL, LH); 6039 ExpandOp(Node->getOperand(1), RL, RH); 6040 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 6041 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 6042 break; 6043 } 6044 case ISD::SELECT: { 6045 SDOperand LL, LH, RL, RH; 6046 ExpandOp(Node->getOperand(1), LL, LH); 6047 ExpandOp(Node->getOperand(2), RL, RH); 6048 if (getTypeAction(NVT) == Expand) 6049 NVT = TLI.getTypeToExpandTo(NVT); 6050 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 6051 if (VT != MVT::f32) 6052 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 6053 break; 6054 } 6055 case ISD::SELECT_CC: { 6056 SDOperand TL, TH, FL, FH; 6057 ExpandOp(Node->getOperand(2), TL, TH); 6058 ExpandOp(Node->getOperand(3), FL, FH); 6059 if (getTypeAction(NVT) == Expand) 6060 NVT = TLI.getTypeToExpandTo(NVT); 6061 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6062 Node->getOperand(1), TL, FL, Node->getOperand(4)); 6063 if (VT != MVT::f32) 6064 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6065 Node->getOperand(1), TH, FH, Node->getOperand(4)); 6066 break; 6067 } 6068 case ISD::ANY_EXTEND: 6069 // The low part is any extension of the input (which degenerates to a copy). 6070 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 6071 // The high part is undefined. 6072 Hi = DAG.getNode(ISD::UNDEF, NVT); 6073 break; 6074 case ISD::SIGN_EXTEND: { 6075 // The low part is just a sign extension of the input (which degenerates to 6076 // a copy). 6077 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 6078 6079 // The high part is obtained by SRA'ing all but one of the bits of the lo 6080 // part. 6081 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 6082 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6083 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6084 break; 6085 } 6086 case ISD::ZERO_EXTEND: 6087 // The low part is just a zero extension of the input (which degenerates to 6088 // a copy). 6089 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 6090 6091 // The high part is just a zero. 6092 Hi = DAG.getConstant(0, NVT); 6093 break; 6094 6095 case ISD::TRUNCATE: { 6096 // The input value must be larger than this value. Expand *it*. 6097 SDOperand NewLo; 6098 ExpandOp(Node->getOperand(0), NewLo, Hi); 6099 6100 // The low part is now either the right size, or it is closer. If not the 6101 // right size, make an illegal truncate so we recursively expand it. 6102 if (NewLo.getValueType() != Node->getValueType(0)) 6103 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 6104 ExpandOp(NewLo, Lo, Hi); 6105 break; 6106 } 6107 6108 case ISD::BIT_CONVERT: { 6109 SDOperand Tmp; 6110 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6111 // If the target wants to, allow it to lower this itself. 6112 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6113 case Expand: assert(0 && "cannot expand FP!"); 6114 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6115 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6116 } 6117 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 6118 } 6119 6120 // f32 / f64 must be expanded to i32 / i64. 6121 if (VT == MVT::f32 || VT == MVT::f64) { 6122 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6123 if (getTypeAction(NVT) == Expand) 6124 ExpandOp(Lo, Lo, Hi); 6125 break; 6126 } 6127 6128 // If source operand will be expanded to the same type as VT, i.e. 6129 // i64 <- f64, i32 <- f32, expand the source operand instead. 6130 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 6131 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6132 ExpandOp(Node->getOperand(0), Lo, Hi); 6133 break; 6134 } 6135 6136 // Turn this into a load/store pair by default. 6137 if (Tmp.Val == 0) 6138 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 6139 6140 ExpandOp(Tmp, Lo, Hi); 6141 break; 6142 } 6143 6144 case ISD::READCYCLECOUNTER: { 6145 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6146 TargetLowering::Custom && 6147 "Must custom expand ReadCycleCounter"); 6148 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 6149 assert(Tmp.Val && "Node must be custom expanded!"); 6150 ExpandOp(Tmp.getValue(0), Lo, Hi); 6151 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 6152 LegalizeOp(Tmp.getValue(1))); 6153 break; 6154 } 6155 6156 case ISD::ATOMIC_LCS: { 6157 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 6158 assert(Tmp.Val && "Node must be custom expanded!"); 6159 ExpandOp(Tmp.getValue(0), Lo, Hi); 6160 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 6161 LegalizeOp(Tmp.getValue(1))); 6162 break; 6163 } 6164 6165 6166 6167 // These operators cannot be expanded directly, emit them as calls to 6168 // library functions. 6169 case ISD::FP_TO_SINT: { 6170 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6171 SDOperand Op; 6172 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6173 case Expand: assert(0 && "cannot expand FP!"); 6174 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6175 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6176 } 6177 6178 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 6179 6180 // Now that the custom expander is done, expand the result, which is still 6181 // VT. 6182 if (Op.Val) { 6183 ExpandOp(Op, Lo, Hi); 6184 break; 6185 } 6186 } 6187 6188 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6189 if (VT == MVT::i64) { 6190 if (Node->getOperand(0).getValueType() == MVT::f32) 6191 LC = RTLIB::FPTOSINT_F32_I64; 6192 else if (Node->getOperand(0).getValueType() == MVT::f64) 6193 LC = RTLIB::FPTOSINT_F64_I64; 6194 else if (Node->getOperand(0).getValueType() == MVT::f80) 6195 LC = RTLIB::FPTOSINT_F80_I64; 6196 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6197 LC = RTLIB::FPTOSINT_PPCF128_I64; 6198 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6199 } else if (VT == MVT::i128) { 6200 if (Node->getOperand(0).getValueType() == MVT::f32) 6201 LC = RTLIB::FPTOSINT_F32_I128; 6202 else if (Node->getOperand(0).getValueType() == MVT::f64) 6203 LC = RTLIB::FPTOSINT_F64_I128; 6204 else if (Node->getOperand(0).getValueType() == MVT::f80) 6205 LC = RTLIB::FPTOSINT_F80_I128; 6206 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6207 LC = RTLIB::FPTOSINT_PPCF128_I128; 6208 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6209 } else { 6210 assert(0 && "Unexpected uint-to-fp conversion!"); 6211 } 6212 break; 6213 } 6214 6215 case ISD::FP_TO_UINT: { 6216 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6217 SDOperand Op; 6218 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6219 case Expand: assert(0 && "cannot expand FP!"); 6220 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6221 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6222 } 6223 6224 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 6225 6226 // Now that the custom expander is done, expand the result. 6227 if (Op.Val) { 6228 ExpandOp(Op, Lo, Hi); 6229 break; 6230 } 6231 } 6232 6233 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6234 if (VT == MVT::i64) { 6235 if (Node->getOperand(0).getValueType() == MVT::f32) 6236 LC = RTLIB::FPTOUINT_F32_I64; 6237 else if (Node->getOperand(0).getValueType() == MVT::f64) 6238 LC = RTLIB::FPTOUINT_F64_I64; 6239 else if (Node->getOperand(0).getValueType() == MVT::f80) 6240 LC = RTLIB::FPTOUINT_F80_I64; 6241 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6242 LC = RTLIB::FPTOUINT_PPCF128_I64; 6243 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6244 } else if (VT == MVT::i128) { 6245 if (Node->getOperand(0).getValueType() == MVT::f32) 6246 LC = RTLIB::FPTOUINT_F32_I128; 6247 else if (Node->getOperand(0).getValueType() == MVT::f64) 6248 LC = RTLIB::FPTOUINT_F64_I128; 6249 else if (Node->getOperand(0).getValueType() == MVT::f80) 6250 LC = RTLIB::FPTOUINT_F80_I128; 6251 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6252 LC = RTLIB::FPTOUINT_PPCF128_I128; 6253 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6254 } else { 6255 assert(0 && "Unexpected uint-to-fp conversion!"); 6256 } 6257 break; 6258 } 6259 6260 case ISD::SHL: { 6261 // If the target wants custom lowering, do so. 6262 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6263 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6264 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 6265 Op = TLI.LowerOperation(Op, DAG); 6266 if (Op.Val) { 6267 // Now that the custom expander is done, expand the result, which is 6268 // still VT. 6269 ExpandOp(Op, Lo, Hi); 6270 break; 6271 } 6272 } 6273 6274 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6275 // this X << 1 as X+X. 6276 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6277 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 6278 TLI.isOperationLegal(ISD::ADDE, NVT)) { 6279 SDOperand LoOps[2], HiOps[3]; 6280 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6281 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6282 LoOps[1] = LoOps[0]; 6283 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6284 6285 HiOps[1] = HiOps[0]; 6286 HiOps[2] = Lo.getValue(1); 6287 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6288 break; 6289 } 6290 } 6291 6292 // If we can emit an efficient shift operation, do so now. 6293 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6294 break; 6295 6296 // If this target supports SHL_PARTS, use it. 6297 TargetLowering::LegalizeAction Action = 6298 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6299 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6300 Action == TargetLowering::Custom) { 6301 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6302 break; 6303 } 6304 6305 // Otherwise, emit a libcall. 6306 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi); 6307 break; 6308 } 6309 6310 case ISD::SRA: { 6311 // If the target wants custom lowering, do so. 6312 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6313 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6314 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6315 Op = TLI.LowerOperation(Op, DAG); 6316 if (Op.Val) { 6317 // Now that the custom expander is done, expand the result, which is 6318 // still VT. 6319 ExpandOp(Op, Lo, Hi); 6320 break; 6321 } 6322 } 6323 6324 // If we can emit an efficient shift operation, do so now. 6325 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6326 break; 6327 6328 // If this target supports SRA_PARTS, use it. 6329 TargetLowering::LegalizeAction Action = 6330 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6331 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6332 Action == TargetLowering::Custom) { 6333 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6334 break; 6335 } 6336 6337 // Otherwise, emit a libcall. 6338 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi); 6339 break; 6340 } 6341 6342 case ISD::SRL: { 6343 // If the target wants custom lowering, do so. 6344 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6345 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6346 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 6347 Op = TLI.LowerOperation(Op, DAG); 6348 if (Op.Val) { 6349 // Now that the custom expander is done, expand the result, which is 6350 // still VT. 6351 ExpandOp(Op, Lo, Hi); 6352 break; 6353 } 6354 } 6355 6356 // If we can emit an efficient shift operation, do so now. 6357 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6358 break; 6359 6360 // If this target supports SRL_PARTS, use it. 6361 TargetLowering::LegalizeAction Action = 6362 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6363 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6364 Action == TargetLowering::Custom) { 6365 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6366 break; 6367 } 6368 6369 // Otherwise, emit a libcall. 6370 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi); 6371 break; 6372 } 6373 6374 case ISD::ADD: 6375 case ISD::SUB: { 6376 // If the target wants to custom expand this, let them. 6377 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6378 TargetLowering::Custom) { 6379 Op = TLI.LowerOperation(Op, DAG); 6380 if (Op.Val) { 6381 ExpandOp(Op, Lo, Hi); 6382 break; 6383 } 6384 } 6385 6386 // Expand the subcomponents. 6387 SDOperand LHSL, LHSH, RHSL, RHSH; 6388 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6389 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6390 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6391 SDOperand LoOps[2], HiOps[3]; 6392 LoOps[0] = LHSL; 6393 LoOps[1] = RHSL; 6394 HiOps[0] = LHSH; 6395 HiOps[1] = RHSH; 6396 if (Node->getOpcode() == ISD::ADD) { 6397 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6398 HiOps[2] = Lo.getValue(1); 6399 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6400 } else { 6401 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6402 HiOps[2] = Lo.getValue(1); 6403 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6404 } 6405 break; 6406 } 6407 6408 case ISD::ADDC: 6409 case ISD::SUBC: { 6410 // Expand the subcomponents. 6411 SDOperand LHSL, LHSH, RHSL, RHSH; 6412 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6413 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6414 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6415 SDOperand LoOps[2] = { LHSL, RHSL }; 6416 SDOperand HiOps[3] = { LHSH, RHSH }; 6417 6418 if (Node->getOpcode() == ISD::ADDC) { 6419 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6420 HiOps[2] = Lo.getValue(1); 6421 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6422 } else { 6423 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6424 HiOps[2] = Lo.getValue(1); 6425 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6426 } 6427 // Remember that we legalized the flag. 6428 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6429 break; 6430 } 6431 case ISD::ADDE: 6432 case ISD::SUBE: { 6433 // Expand the subcomponents. 6434 SDOperand LHSL, LHSH, RHSL, RHSH; 6435 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6436 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6437 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6438 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 6439 SDOperand HiOps[3] = { LHSH, RHSH }; 6440 6441 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 6442 HiOps[2] = Lo.getValue(1); 6443 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 6444 6445 // Remember that we legalized the flag. 6446 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6447 break; 6448 } 6449 case ISD::MUL: { 6450 // If the target wants to custom expand this, let them. 6451 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 6452 SDOperand New = TLI.LowerOperation(Op, DAG); 6453 if (New.Val) { 6454 ExpandOp(New, Lo, Hi); 6455 break; 6456 } 6457 } 6458 6459 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 6460 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 6461 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 6462 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 6463 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 6464 SDOperand LL, LH, RL, RH; 6465 ExpandOp(Node->getOperand(0), LL, LH); 6466 ExpandOp(Node->getOperand(1), RL, RH); 6467 unsigned OuterBitSize = Op.getValueSizeInBits(); 6468 unsigned InnerBitSize = RH.getValueSizeInBits(); 6469 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 6470 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 6471 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 6472 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 6473 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 6474 // The inputs are both zero-extended. 6475 if (HasUMUL_LOHI) { 6476 // We can emit a umul_lohi. 6477 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6478 Hi = SDOperand(Lo.Val, 1); 6479 break; 6480 } 6481 if (HasMULHU) { 6482 // We can emit a mulhu+mul. 6483 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6484 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6485 break; 6486 } 6487 } 6488 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 6489 // The input values are both sign-extended. 6490 if (HasSMUL_LOHI) { 6491 // We can emit a smul_lohi. 6492 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6493 Hi = SDOperand(Lo.Val, 1); 6494 break; 6495 } 6496 if (HasMULHS) { 6497 // We can emit a mulhs+mul. 6498 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6499 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6500 break; 6501 } 6502 } 6503 if (HasUMUL_LOHI) { 6504 // Lo,Hi = umul LHS, RHS. 6505 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6506 DAG.getVTList(NVT, NVT), LL, RL); 6507 Lo = UMulLOHI; 6508 Hi = UMulLOHI.getValue(1); 6509 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6510 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6511 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6512 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6513 break; 6514 } 6515 if (HasMULHU) { 6516 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6517 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6518 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6519 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6520 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6521 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6522 break; 6523 } 6524 } 6525 6526 // If nothing else, we can make a libcall. 6527 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi); 6528 break; 6529 } 6530 case ISD::SDIV: 6531 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi); 6532 break; 6533 case ISD::UDIV: 6534 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi); 6535 break; 6536 case ISD::SREM: 6537 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi); 6538 break; 6539 case ISD::UREM: 6540 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi); 6541 break; 6542 6543 case ISD::FADD: 6544 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32, 6545 RTLIB::ADD_F64, 6546 RTLIB::ADD_F80, 6547 RTLIB::ADD_PPCF128), 6548 Node, false, Hi); 6549 break; 6550 case ISD::FSUB: 6551 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32, 6552 RTLIB::SUB_F64, 6553 RTLIB::SUB_F80, 6554 RTLIB::SUB_PPCF128), 6555 Node, false, Hi); 6556 break; 6557 case ISD::FMUL: 6558 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32, 6559 RTLIB::MUL_F64, 6560 RTLIB::MUL_F80, 6561 RTLIB::MUL_PPCF128), 6562 Node, false, Hi); 6563 break; 6564 case ISD::FDIV: 6565 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32, 6566 RTLIB::DIV_F64, 6567 RTLIB::DIV_F80, 6568 RTLIB::DIV_PPCF128), 6569 Node, false, Hi); 6570 break; 6571 case ISD::FP_EXTEND: 6572 if (VT == MVT::ppcf128) { 6573 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6574 Node->getOperand(0).getValueType()==MVT::f64); 6575 const uint64_t zero = 0; 6576 if (Node->getOperand(0).getValueType()==MVT::f32) 6577 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6578 else 6579 Hi = Node->getOperand(0); 6580 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6581 break; 6582 } 6583 Lo = ExpandLibCall(RTLIB::FPEXT_F32_F64, Node, true, Hi); 6584 break; 6585 case ISD::FP_ROUND: 6586 Lo = ExpandLibCall(RTLIB::FPROUND_F64_F32, Node, true, Hi); 6587 break; 6588 case ISD::FPOWI: 6589 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32, 6590 RTLIB::POWI_F64, 6591 RTLIB::POWI_F80, 6592 RTLIB::POWI_PPCF128), 6593 Node, false, Hi); 6594 break; 6595 case ISD::FSQRT: 6596 case ISD::FSIN: 6597 case ISD::FCOS: { 6598 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6599 switch(Node->getOpcode()) { 6600 case ISD::FSQRT: 6601 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 6602 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 6603 break; 6604 case ISD::FSIN: 6605 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 6606 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 6607 break; 6608 case ISD::FCOS: 6609 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 6610 RTLIB::COS_F80, RTLIB::COS_PPCF128); 6611 break; 6612 default: assert(0 && "Unreachable!"); 6613 } 6614 Lo = ExpandLibCall(LC, Node, false, Hi); 6615 break; 6616 } 6617 case ISD::FABS: { 6618 if (VT == MVT::ppcf128) { 6619 SDOperand Tmp; 6620 ExpandOp(Node->getOperand(0), Lo, Tmp); 6621 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6622 // lo = hi==fabs(hi) ? lo : -lo; 6623 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6624 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6625 DAG.getCondCode(ISD::SETEQ)); 6626 break; 6627 } 6628 SDOperand Mask = (VT == MVT::f64) 6629 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6630 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6631 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6632 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6633 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6634 if (getTypeAction(NVT) == Expand) 6635 ExpandOp(Lo, Lo, Hi); 6636 break; 6637 } 6638 case ISD::FNEG: { 6639 if (VT == MVT::ppcf128) { 6640 ExpandOp(Node->getOperand(0), Lo, Hi); 6641 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6642 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6643 break; 6644 } 6645 SDOperand Mask = (VT == MVT::f64) 6646 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6647 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6648 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6649 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6650 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6651 if (getTypeAction(NVT) == Expand) 6652 ExpandOp(Lo, Lo, Hi); 6653 break; 6654 } 6655 case ISD::FCOPYSIGN: { 6656 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6657 if (getTypeAction(NVT) == Expand) 6658 ExpandOp(Lo, Lo, Hi); 6659 break; 6660 } 6661 case ISD::SINT_TO_FP: 6662 case ISD::UINT_TO_FP: { 6663 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6664 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 6665 6666 // Promote the operand if needed. Do this before checking for 6667 // ppcf128 so conversions of i16 and i8 work. 6668 if (getTypeAction(SrcVT) == Promote) { 6669 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 6670 Tmp = isSigned 6671 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6672 DAG.getValueType(SrcVT)) 6673 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6674 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6675 SrcVT = Node->getOperand(0).getValueType(); 6676 } 6677 6678 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 6679 static const uint64_t zero = 0; 6680 if (isSigned) { 6681 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6682 Node->getOperand(0))); 6683 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6684 } else { 6685 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6686 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6687 Node->getOperand(0))); 6688 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6689 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6690 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6691 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6692 DAG.getConstant(0, MVT::i32), 6693 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6694 DAG.getConstantFP( 6695 APFloat(APInt(128, 2, TwoE32)), 6696 MVT::ppcf128)), 6697 Hi, 6698 DAG.getCondCode(ISD::SETLT)), 6699 Lo, Hi); 6700 } 6701 break; 6702 } 6703 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6704 // si64->ppcf128 done by libcall, below 6705 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6706 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6707 Lo, Hi); 6708 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6709 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6710 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6711 DAG.getConstant(0, MVT::i64), 6712 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6713 DAG.getConstantFP( 6714 APFloat(APInt(128, 2, TwoE64)), 6715 MVT::ppcf128)), 6716 Hi, 6717 DAG.getCondCode(ISD::SETLT)), 6718 Lo, Hi); 6719 break; 6720 } 6721 6722 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6723 Node->getOperand(0)); 6724 if (getTypeAction(Lo.getValueType()) == Expand) 6725 // float to i32 etc. can be 'expanded' to a single node. 6726 ExpandOp(Lo, Lo, Hi); 6727 break; 6728 } 6729 } 6730 6731 // Make sure the resultant values have been legalized themselves, unless this 6732 // is a type that requires multi-step expansion. 6733 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6734 Lo = LegalizeOp(Lo); 6735 if (Hi.Val) 6736 // Don't legalize the high part if it is expanded to a single node. 6737 Hi = LegalizeOp(Hi); 6738 } 6739 6740 // Remember in a map if the values will be reused later. 6741 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 6742 assert(isNew && "Value already expanded?!?"); 6743} 6744 6745/// SplitVectorOp - Given an operand of vector type, break it down into 6746/// two smaller values, still of vector type. 6747void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 6748 SDOperand &Hi) { 6749 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); 6750 SDNode *Node = Op.Val; 6751 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType()); 6752 assert(NumElements > 1 && "Cannot split a single element vector!"); 6753 6754 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType()); 6755 6756 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6757 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6758 6759 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo); 6760 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi); 6761 6762 // See if we already split it. 6763 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 6764 = SplitNodes.find(Op); 6765 if (I != SplitNodes.end()) { 6766 Lo = I->second.first; 6767 Hi = I->second.second; 6768 return; 6769 } 6770 6771 switch (Node->getOpcode()) { 6772 default: 6773#ifndef NDEBUG 6774 Node->dump(&DAG); 6775#endif 6776 assert(0 && "Unhandled operation in SplitVectorOp!"); 6777 case ISD::UNDEF: 6778 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6779 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6780 break; 6781 case ISD::BUILD_PAIR: 6782 Lo = Node->getOperand(0); 6783 Hi = Node->getOperand(1); 6784 break; 6785 case ISD::INSERT_VECTOR_ELT: { 6786 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 6787 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6788 unsigned Index = Idx->getValue(); 6789 SDOperand ScalarOp = Node->getOperand(1); 6790 if (Index < NewNumElts_Lo) 6791 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6792 DAG.getIntPtrConstant(Index)); 6793 else 6794 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6795 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 6796 break; 6797 } 6798 SDOperand Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), 6799 Node->getOperand(1), 6800 Node->getOperand(2)); 6801 SplitVectorOp(Tmp, Lo, Hi); 6802 break; 6803 } 6804 case ISD::VECTOR_SHUFFLE: { 6805 // Build the low part. 6806 SDOperand Mask = Node->getOperand(2); 6807 SmallVector<SDOperand, 8> Ops; 6808 MVT::ValueType PtrVT = TLI.getPointerTy(); 6809 6810 // Insert all of the elements from the input that are needed. We use 6811 // buildvector of extractelement here because the input vectors will have 6812 // to be legalized, so this makes the code simpler. 6813 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 6814 SDOperand IdxNode = Mask.getOperand(i); 6815 if (IdxNode.getOpcode() == ISD::UNDEF) { 6816 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6817 continue; 6818 } 6819 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6820 SDOperand InVec = Node->getOperand(0); 6821 if (Idx >= NumElements) { 6822 InVec = Node->getOperand(1); 6823 Idx -= NumElements; 6824 } 6825 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6826 DAG.getConstant(Idx, PtrVT))); 6827 } 6828 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6829 Ops.clear(); 6830 6831 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 6832 SDOperand IdxNode = Mask.getOperand(i); 6833 if (IdxNode.getOpcode() == ISD::UNDEF) { 6834 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6835 continue; 6836 } 6837 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6838 SDOperand InVec = Node->getOperand(0); 6839 if (Idx >= NumElements) { 6840 InVec = Node->getOperand(1); 6841 Idx -= NumElements; 6842 } 6843 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6844 DAG.getConstant(Idx, PtrVT))); 6845 } 6846 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6847 break; 6848 } 6849 case ISD::BUILD_VECTOR: { 6850 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6851 Node->op_begin()+NewNumElts_Lo); 6852 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 6853 6854 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 6855 Node->op_end()); 6856 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 6857 break; 6858 } 6859 case ISD::CONCAT_VECTORS: { 6860 // FIXME: Handle non-power-of-two vectors? 6861 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6862 if (NewNumSubvectors == 1) { 6863 Lo = Node->getOperand(0); 6864 Hi = Node->getOperand(1); 6865 } else { 6866 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6867 Node->op_begin()+NewNumSubvectors); 6868 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 6869 6870 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6871 Node->op_end()); 6872 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 6873 } 6874 break; 6875 } 6876 case ISD::SELECT: { 6877 SDOperand Cond = Node->getOperand(0); 6878 6879 SDOperand LL, LH, RL, RH; 6880 SplitVectorOp(Node->getOperand(1), LL, LH); 6881 SplitVectorOp(Node->getOperand(2), RL, RH); 6882 6883 if (MVT::isVector(Cond.getValueType())) { 6884 // Handle a vector merge. 6885 SDOperand CL, CH; 6886 SplitVectorOp(Cond, CL, CH); 6887 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 6888 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 6889 } else { 6890 // Handle a simple select with vector operands. 6891 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 6892 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 6893 } 6894 break; 6895 } 6896 case ISD::VSETCC: { 6897 SDOperand LL, LH, RL, RH; 6898 SplitVectorOp(Node->getOperand(0), LL, LH); 6899 SplitVectorOp(Node->getOperand(1), RL, RH); 6900 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2)); 6901 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2)); 6902 break; 6903 } 6904 case ISD::ADD: 6905 case ISD::SUB: 6906 case ISD::MUL: 6907 case ISD::FADD: 6908 case ISD::FSUB: 6909 case ISD::FMUL: 6910 case ISD::SDIV: 6911 case ISD::UDIV: 6912 case ISD::FDIV: 6913 case ISD::FPOW: 6914 case ISD::AND: 6915 case ISD::OR: 6916 case ISD::XOR: 6917 case ISD::UREM: 6918 case ISD::SREM: 6919 case ISD::FREM: { 6920 SDOperand LL, LH, RL, RH; 6921 SplitVectorOp(Node->getOperand(0), LL, LH); 6922 SplitVectorOp(Node->getOperand(1), RL, RH); 6923 6924 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 6925 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 6926 break; 6927 } 6928 case ISD::FPOWI: { 6929 SDOperand L, H; 6930 SplitVectorOp(Node->getOperand(0), L, H); 6931 6932 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 6933 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 6934 break; 6935 } 6936 case ISD::CTTZ: 6937 case ISD::CTLZ: 6938 case ISD::CTPOP: 6939 case ISD::FNEG: 6940 case ISD::FABS: 6941 case ISD::FSQRT: 6942 case ISD::FSIN: 6943 case ISD::FCOS: 6944 case ISD::FP_TO_SINT: 6945 case ISD::FP_TO_UINT: 6946 case ISD::SINT_TO_FP: 6947 case ISD::UINT_TO_FP: { 6948 SDOperand L, H; 6949 SplitVectorOp(Node->getOperand(0), L, H); 6950 6951 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 6952 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 6953 break; 6954 } 6955 case ISD::LOAD: { 6956 LoadSDNode *LD = cast<LoadSDNode>(Node); 6957 SDOperand Ch = LD->getChain(); 6958 SDOperand Ptr = LD->getBasePtr(); 6959 const Value *SV = LD->getSrcValue(); 6960 int SVOffset = LD->getSrcValueOffset(); 6961 unsigned Alignment = LD->getAlignment(); 6962 bool isVolatile = LD->isVolatile(); 6963 6964 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6965 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8; 6966 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6967 DAG.getIntPtrConstant(IncrementSize)); 6968 SVOffset += IncrementSize; 6969 Alignment = MinAlign(Alignment, IncrementSize); 6970 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6971 6972 // Build a factor node to remember that this load is independent of the 6973 // other one. 6974 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6975 Hi.getValue(1)); 6976 6977 // Remember that we legalized the chain. 6978 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6979 break; 6980 } 6981 case ISD::BIT_CONVERT: { 6982 // We know the result is a vector. The input may be either a vector or a 6983 // scalar value. 6984 SDOperand InOp = Node->getOperand(0); 6985 if (!MVT::isVector(InOp.getValueType()) || 6986 MVT::getVectorNumElements(InOp.getValueType()) == 1) { 6987 // The input is a scalar or single-element vector. 6988 // Lower to a store/load so that it can be split. 6989 // FIXME: this could be improved probably. 6990 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); 6991 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val); 6992 6993 SDOperand St = DAG.getStore(DAG.getEntryNode(), 6994 InOp, Ptr, 6995 PseudoSourceValue::getFixedStack(), 6996 FI->getIndex()); 6997 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, 6998 PseudoSourceValue::getFixedStack(), 6999 FI->getIndex()); 7000 } 7001 // Split the vector and convert each of the pieces now. 7002 SplitVectorOp(InOp, Lo, Hi); 7003 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 7004 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 7005 break; 7006 } 7007 } 7008 7009 // Remember in a map if the values will be reused later. 7010 bool isNew = 7011 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7012 assert(isNew && "Value already split?!?"); 7013} 7014 7015 7016/// ScalarizeVectorOp - Given an operand of single-element vector type 7017/// (e.g. v1f32), convert it into the equivalent operation that returns a 7018/// scalar (e.g. f32) value. 7019SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 7020 assert(MVT::isVector(Op.getValueType()) && 7021 "Bad ScalarizeVectorOp invocation!"); 7022 SDNode *Node = Op.Val; 7023 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); 7024 assert(MVT::getVectorNumElements(Op.getValueType()) == 1); 7025 7026 // See if we already scalarized it. 7027 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 7028 if (I != ScalarizedNodes.end()) return I->second; 7029 7030 SDOperand Result; 7031 switch (Node->getOpcode()) { 7032 default: 7033#ifndef NDEBUG 7034 Node->dump(&DAG); cerr << "\n"; 7035#endif 7036 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 7037 case ISD::ADD: 7038 case ISD::FADD: 7039 case ISD::SUB: 7040 case ISD::FSUB: 7041 case ISD::MUL: 7042 case ISD::FMUL: 7043 case ISD::SDIV: 7044 case ISD::UDIV: 7045 case ISD::FDIV: 7046 case ISD::SREM: 7047 case ISD::UREM: 7048 case ISD::FREM: 7049 case ISD::FPOW: 7050 case ISD::AND: 7051 case ISD::OR: 7052 case ISD::XOR: 7053 Result = DAG.getNode(Node->getOpcode(), 7054 NewVT, 7055 ScalarizeVectorOp(Node->getOperand(0)), 7056 ScalarizeVectorOp(Node->getOperand(1))); 7057 break; 7058 case ISD::FNEG: 7059 case ISD::FABS: 7060 case ISD::FSQRT: 7061 case ISD::FSIN: 7062 case ISD::FCOS: 7063 Result = DAG.getNode(Node->getOpcode(), 7064 NewVT, 7065 ScalarizeVectorOp(Node->getOperand(0))); 7066 break; 7067 case ISD::FPOWI: 7068 Result = DAG.getNode(Node->getOpcode(), 7069 NewVT, 7070 ScalarizeVectorOp(Node->getOperand(0)), 7071 Node->getOperand(1)); 7072 break; 7073 case ISD::LOAD: { 7074 LoadSDNode *LD = cast<LoadSDNode>(Node); 7075 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 7076 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 7077 7078 const Value *SV = LD->getSrcValue(); 7079 int SVOffset = LD->getSrcValueOffset(); 7080 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 7081 LD->isVolatile(), LD->getAlignment()); 7082 7083 // Remember that we legalized the chain. 7084 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 7085 break; 7086 } 7087 case ISD::BUILD_VECTOR: 7088 Result = Node->getOperand(0); 7089 break; 7090 case ISD::INSERT_VECTOR_ELT: 7091 // Returning the inserted scalar element. 7092 Result = Node->getOperand(1); 7093 break; 7094 case ISD::CONCAT_VECTORS: 7095 assert(Node->getOperand(0).getValueType() == NewVT && 7096 "Concat of non-legal vectors not yet supported!"); 7097 Result = Node->getOperand(0); 7098 break; 7099 case ISD::VECTOR_SHUFFLE: { 7100 // Figure out if the scalar is the LHS or RHS and return it. 7101 SDOperand EltNum = Node->getOperand(2).getOperand(0); 7102 if (cast<ConstantSDNode>(EltNum)->getValue()) 7103 Result = ScalarizeVectorOp(Node->getOperand(1)); 7104 else 7105 Result = ScalarizeVectorOp(Node->getOperand(0)); 7106 break; 7107 } 7108 case ISD::EXTRACT_SUBVECTOR: 7109 Result = Node->getOperand(0); 7110 assert(Result.getValueType() == NewVT); 7111 break; 7112 case ISD::BIT_CONVERT: { 7113 SDOperand Op0 = Op.getOperand(0); 7114 if (MVT::getVectorNumElements(Op0.getValueType()) == 1) 7115 Op0 = ScalarizeVectorOp(Op0); 7116 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0); 7117 break; 7118 } 7119 case ISD::SELECT: 7120 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 7121 ScalarizeVectorOp(Op.getOperand(1)), 7122 ScalarizeVectorOp(Op.getOperand(2))); 7123 break; 7124 case ISD::VSETCC: { 7125 SDOperand Op0 = ScalarizeVectorOp(Op.getOperand(0)); 7126 SDOperand Op1 = ScalarizeVectorOp(Op.getOperand(1)); 7127 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1, 7128 Op.getOperand(2)); 7129 Result = DAG.getNode(ISD::SELECT, NewVT, Result, 7130 DAG.getConstant(-1ULL, NewVT), 7131 DAG.getConstant(0ULL, NewVT)); 7132 break; 7133 } 7134 } 7135 7136 if (TLI.isTypeLegal(NewVT)) 7137 Result = LegalizeOp(Result); 7138 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7139 assert(isNew && "Value already scalarized?"); 7140 return Result; 7141} 7142 7143 7144// SelectionDAG::Legalize - This is the entry point for the file. 7145// 7146void SelectionDAG::Legalize() { 7147 if (ViewLegalizeDAGs) viewGraph(); 7148 7149 /// run - This is the main entry point to this class. 7150 /// 7151 SelectionDAGLegalize(*this).LegalizeDAG(); 7152} 7153 7154