LegalizeDAG.cpp revision 2e49f090f9656af7d5ed4d5c4e9fa26af59c7233
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Target/TargetLowering.h" 18#include "llvm/Target/TargetData.h" 19#include "llvm/Target/TargetOptions.h" 20#include "llvm/CallingConv.h" 21#include "llvm/Constants.h" 22#include "llvm/Support/MathExtras.h" 23#include "llvm/Support/CommandLine.h" 24#include "llvm/Support/Compiler.h" 25#include "llvm/ADT/SmallVector.h" 26#include <iostream> 27#include <map> 28using namespace llvm; 29 30#ifndef NDEBUG 31static cl::opt<bool> 32ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 33 cl::desc("Pop up a window to show dags before legalize")); 34#else 35static const bool ViewLegalizeDAGs = 0; 36#endif 37 38//===----------------------------------------------------------------------===// 39/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 40/// hacks on it until the target machine can handle it. This involves 41/// eliminating value sizes the machine cannot handle (promoting small sizes to 42/// large sizes or splitting up large values into small values) as well as 43/// eliminating operations the machine cannot handle. 44/// 45/// This code also does a small amount of optimization and recognition of idioms 46/// as part of its processing. For example, if a target does not support a 47/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 48/// will attempt merge setcc and brc instructions into brcc's. 49/// 50namespace { 51class VISIBILITY_HIDDEN SelectionDAGLegalize { 52 TargetLowering &TLI; 53 SelectionDAG &DAG; 54 55 // Libcall insertion helpers. 56 57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 58 /// legalized. We use this to ensure that calls are properly serialized 59 /// against each other, including inserted libcalls. 60 SDOperand LastCALLSEQ_END; 61 62 /// IsLegalizingCall - This member is used *only* for purposes of providing 63 /// helpful assertions that a libcall isn't created while another call is 64 /// being legalized (which could lead to non-serialized call sequences). 65 bool IsLegalizingCall; 66 67 enum LegalizeAction { 68 Legal, // The target natively supports this operation. 69 Promote, // This operation should be executed in a larger type. 70 Expand // Try to expand this to other ops, otherwise use a libcall. 71 }; 72 73 /// ValueTypeActions - This is a bitvector that contains two bits for each 74 /// value type, where the two bits correspond to the LegalizeAction enum. 75 /// This can be queried with "getTypeAction(VT)". 76 TargetLowering::ValueTypeActionImpl ValueTypeActions; 77 78 /// LegalizedNodes - For nodes that are of legal width, and that have more 79 /// than one use, this map indicates what regularized operand to use. This 80 /// allows us to avoid legalizing the same thing more than once. 81 std::map<SDOperand, SDOperand> LegalizedNodes; 82 83 /// PromotedNodes - For nodes that are below legal width, and that have more 84 /// than one use, this map indicates what promoted value to use. This allows 85 /// us to avoid promoting the same thing more than once. 86 std::map<SDOperand, SDOperand> PromotedNodes; 87 88 /// ExpandedNodes - For nodes that need to be expanded this map indicates 89 /// which which operands are the expanded version of the input. This allows 90 /// us to avoid expanding the same node more than once. 91 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 92 93 /// SplitNodes - For vector nodes that need to be split, this map indicates 94 /// which which operands are the split version of the input. This allows us 95 /// to avoid splitting the same node more than once. 96 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 97 98 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to 99 /// concrete packed types, this contains the mapping of ones we have already 100 /// processed to the result. 101 std::map<SDOperand, SDOperand> PackedNodes; 102 103 void AddLegalizedOperand(SDOperand From, SDOperand To) { 104 LegalizedNodes.insert(std::make_pair(From, To)); 105 // If someone requests legalization of the new node, return itself. 106 if (From != To) 107 LegalizedNodes.insert(std::make_pair(To, To)); 108 } 109 void AddPromotedOperand(SDOperand From, SDOperand To) { 110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 111 assert(isNew && "Got into the map somehow?"); 112 // If someone requests legalization of the new node, return itself. 113 LegalizedNodes.insert(std::make_pair(To, To)); 114 } 115 116public: 117 118 SelectionDAGLegalize(SelectionDAG &DAG); 119 120 /// getTypeAction - Return how we should legalize values of this type, either 121 /// it is already legal or we need to expand it into multiple registers of 122 /// smaller integer type, or we need to promote it to a larger type. 123 LegalizeAction getTypeAction(MVT::ValueType VT) const { 124 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 125 } 126 127 /// isTypeLegal - Return true if this type is legal on this target. 128 /// 129 bool isTypeLegal(MVT::ValueType VT) const { 130 return getTypeAction(VT) == Legal; 131 } 132 133 void LegalizeDAG(); 134 135private: 136 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 137 /// appropriate for its type. 138 void HandleOp(SDOperand Op); 139 140 /// LegalizeOp - We know that the specified value has a legal type. 141 /// Recursively ensure that the operands have legal types, then return the 142 /// result. 143 SDOperand LegalizeOp(SDOperand O); 144 145 /// PromoteOp - Given an operation that produces a value in an invalid type, 146 /// promote it to compute the value into a larger type. The produced value 147 /// will have the correct bits for the low portion of the register, but no 148 /// guarantee is made about the top bits: it may be zero, sign-extended, or 149 /// garbage. 150 SDOperand PromoteOp(SDOperand O); 151 152 /// ExpandOp - Expand the specified SDOperand into its two component pieces 153 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 154 /// the LegalizeNodes map is filled in for any results that are not expanded, 155 /// the ExpandedNodes map is filled in for any results that are expanded, and 156 /// the Lo/Hi values are returned. This applies to integer types and Vector 157 /// types. 158 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 159 160 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 161 /// two smaller values of MVT::Vector type. 162 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 163 164 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 165 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When 166 /// this is called, we know that PackedVT is the right type for the result and 167 /// we know that this type is legal for the target. 168 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT); 169 170 /// isShuffleLegal - Return true if a vector shuffle is legal with the 171 /// specified mask and type. Targets can specify exactly which masks they 172 /// support and the code generator is tasked with not creating illegal masks. 173 /// 174 /// Note that this will also return true for shuffles that are promoted to a 175 /// different type. 176 /// 177 /// If this is a legal shuffle, this method returns the (possibly promoted) 178 /// build_vector Mask. If it's not a legal shuffle, it returns null. 179 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 180 181 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 182 std::set<SDNode*> &NodesLeadingTo); 183 184 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 185 186 SDOperand CreateStackTemporary(MVT::ValueType VT); 187 188 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 189 SDOperand &Hi); 190 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 191 SDOperand Source); 192 193 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 194 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 195 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 196 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 197 SDOperand LegalOp, 198 MVT::ValueType DestVT); 199 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 200 bool isSigned); 201 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 202 bool isSigned); 203 204 SDOperand ExpandBSWAP(SDOperand Op); 205 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 206 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 207 SDOperand &Lo, SDOperand &Hi); 208 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 209 SDOperand &Lo, SDOperand &Hi); 210 211 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op); 212 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 213 214 SDOperand getIntPtrConstant(uint64_t Val) { 215 return DAG.getConstant(Val, TLI.getPointerTy()); 216 } 217}; 218} 219 220/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 221/// specified mask and type. Targets can specify exactly which masks they 222/// support and the code generator is tasked with not creating illegal masks. 223/// 224/// Note that this will also return true for shuffles that are promoted to a 225/// different type. 226SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 227 SDOperand Mask) const { 228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 229 default: return 0; 230 case TargetLowering::Legal: 231 case TargetLowering::Custom: 232 break; 233 case TargetLowering::Promote: { 234 // If this is promoted to a different type, convert the shuffle mask and 235 // ask if it is legal in the promoted type! 236 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 237 238 // If we changed # elements, change the shuffle mask. 239 unsigned NumEltsGrowth = 240 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 241 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 242 if (NumEltsGrowth > 1) { 243 // Renumber the elements. 244 SmallVector<SDOperand, 8> Ops; 245 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 246 SDOperand InOp = Mask.getOperand(i); 247 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 248 if (InOp.getOpcode() == ISD::UNDEF) 249 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 250 else { 251 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 252 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 253 } 254 } 255 } 256 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 257 } 258 VT = NVT; 259 break; 260 } 261 } 262 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 263} 264 265/// getScalarizedOpcode - Return the scalar opcode that corresponds to the 266/// specified vector opcode. 267static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 268 switch (VecOp) { 269 default: assert(0 && "Don't know how to scalarize this opcode!"); 270 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 271 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 272 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 273 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV; 274 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV; 275 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0; 276 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0; 277 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0; 278 } 279} 280 281SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 282 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 283 ValueTypeActions(TLI.getValueTypeActions()) { 284 assert(MVT::LAST_VALUETYPE <= 32 && 285 "Too many value types for ValueTypeActions to hold!"); 286} 287 288/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 289/// not been visited yet and if all of its operands have already been visited. 290static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 291 std::map<SDNode*, unsigned> &Visited) { 292 if (++Visited[N] != N->getNumOperands()) 293 return; // Haven't visited all operands yet 294 295 Order.push_back(N); 296 297 if (N->hasOneUse()) { // Tail recurse in common case. 298 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 299 return; 300 } 301 302 // Now that we have N in, add anything that uses it if all of their operands 303 // are now done. 304 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 305 ComputeTopDownOrdering(*UI, Order, Visited); 306} 307 308 309void SelectionDAGLegalize::LegalizeDAG() { 310 LastCALLSEQ_END = DAG.getEntryNode(); 311 IsLegalizingCall = false; 312 313 // The legalize process is inherently a bottom-up recursive process (users 314 // legalize their uses before themselves). Given infinite stack space, we 315 // could just start legalizing on the root and traverse the whole graph. In 316 // practice however, this causes us to run out of stack space on large basic 317 // blocks. To avoid this problem, compute an ordering of the nodes where each 318 // node is only legalized after all of its operands are legalized. 319 std::map<SDNode*, unsigned> Visited; 320 std::vector<SDNode*> Order; 321 322 // Compute ordering from all of the leaves in the graphs, those (like the 323 // entry node) that have no operands. 324 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 325 E = DAG.allnodes_end(); I != E; ++I) { 326 if (I->getNumOperands() == 0) { 327 Visited[I] = 0 - 1U; 328 ComputeTopDownOrdering(I, Order, Visited); 329 } 330 } 331 332 assert(Order.size() == Visited.size() && 333 Order.size() == 334 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 335 "Error: DAG is cyclic!"); 336 Visited.clear(); 337 338 for (unsigned i = 0, e = Order.size(); i != e; ++i) 339 HandleOp(SDOperand(Order[i], 0)); 340 341 // Finally, it's possible the root changed. Get the new root. 342 SDOperand OldRoot = DAG.getRoot(); 343 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 344 DAG.setRoot(LegalizedNodes[OldRoot]); 345 346 ExpandedNodes.clear(); 347 LegalizedNodes.clear(); 348 PromotedNodes.clear(); 349 SplitNodes.clear(); 350 PackedNodes.clear(); 351 352 // Remove dead nodes now. 353 DAG.RemoveDeadNodes(); 354} 355 356 357/// FindCallEndFromCallStart - Given a chained node that is part of a call 358/// sequence, find the CALLSEQ_END node that terminates the call sequence. 359static SDNode *FindCallEndFromCallStart(SDNode *Node) { 360 if (Node->getOpcode() == ISD::CALLSEQ_END) 361 return Node; 362 if (Node->use_empty()) 363 return 0; // No CallSeqEnd 364 365 // The chain is usually at the end. 366 SDOperand TheChain(Node, Node->getNumValues()-1); 367 if (TheChain.getValueType() != MVT::Other) { 368 // Sometimes it's at the beginning. 369 TheChain = SDOperand(Node, 0); 370 if (TheChain.getValueType() != MVT::Other) { 371 // Otherwise, hunt for it. 372 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 373 if (Node->getValueType(i) == MVT::Other) { 374 TheChain = SDOperand(Node, i); 375 break; 376 } 377 378 // Otherwise, we walked into a node without a chain. 379 if (TheChain.getValueType() != MVT::Other) 380 return 0; 381 } 382 } 383 384 for (SDNode::use_iterator UI = Node->use_begin(), 385 E = Node->use_end(); UI != E; ++UI) { 386 387 // Make sure to only follow users of our token chain. 388 SDNode *User = *UI; 389 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 390 if (User->getOperand(i) == TheChain) 391 if (SDNode *Result = FindCallEndFromCallStart(User)) 392 return Result; 393 } 394 return 0; 395} 396 397/// FindCallStartFromCallEnd - Given a chained node that is part of a call 398/// sequence, find the CALLSEQ_START node that initiates the call sequence. 399static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 400 assert(Node && "Didn't find callseq_start for a call??"); 401 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 402 403 assert(Node->getOperand(0).getValueType() == MVT::Other && 404 "Node doesn't have a token chain argument!"); 405 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 406} 407 408/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 409/// see if any uses can reach Dest. If no dest operands can get to dest, 410/// legalize them, legalize ourself, and return false, otherwise, return true. 411/// 412/// Keep track of the nodes we fine that actually do lead to Dest in 413/// NodesLeadingTo. This avoids retraversing them exponential number of times. 414/// 415bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 416 std::set<SDNode*> &NodesLeadingTo) { 417 if (N == Dest) return true; // N certainly leads to Dest :) 418 419 // If we've already processed this node and it does lead to Dest, there is no 420 // need to reprocess it. 421 if (NodesLeadingTo.count(N)) return true; 422 423 // If the first result of this node has been already legalized, then it cannot 424 // reach N. 425 switch (getTypeAction(N->getValueType(0))) { 426 case Legal: 427 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 428 break; 429 case Promote: 430 if (PromotedNodes.count(SDOperand(N, 0))) return false; 431 break; 432 case Expand: 433 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 434 break; 435 } 436 437 // Okay, this node has not already been legalized. Check and legalize all 438 // operands. If none lead to Dest, then we can legalize this node. 439 bool OperandsLeadToDest = false; 440 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 441 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 442 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 443 444 if (OperandsLeadToDest) { 445 NodesLeadingTo.insert(N); 446 return true; 447 } 448 449 // Okay, this node looks safe, legalize it and return false. 450 HandleOp(SDOperand(N, 0)); 451 return false; 452} 453 454/// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 455/// appropriate for its type. 456void SelectionDAGLegalize::HandleOp(SDOperand Op) { 457 switch (getTypeAction(Op.getValueType())) { 458 default: assert(0 && "Bad type action!"); 459 case Legal: LegalizeOp(Op); break; 460 case Promote: PromoteOp(Op); break; 461 case Expand: 462 if (Op.getValueType() != MVT::Vector) { 463 SDOperand X, Y; 464 ExpandOp(Op, X, Y); 465 } else { 466 SDNode *N = Op.Val; 467 unsigned NumOps = N->getNumOperands(); 468 unsigned NumElements = 469 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue(); 470 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT(); 471 MVT::ValueType PackedVT = getVectorType(EVT, NumElements); 472 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) { 473 // In the common case, this is a legal vector type, convert it to the 474 // packed operation and type now. 475 PackVectorOp(Op, PackedVT); 476 } else if (NumElements == 1) { 477 // Otherwise, if this is a single element vector, convert it to a 478 // scalar operation. 479 PackVectorOp(Op, EVT); 480 } else { 481 // Otherwise, this is a multiple element vector that isn't supported. 482 // Split it in half and legalize both parts. 483 SDOperand X, Y; 484 SplitVectorOp(Op, X, Y); 485 } 486 } 487 break; 488 } 489} 490 491 492/// LegalizeOp - We know that the specified value has a legal type. 493/// Recursively ensure that the operands have legal types, then return the 494/// result. 495SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 496 assert(isTypeLegal(Op.getValueType()) && 497 "Caller should expand or promote operands that are not legal!"); 498 SDNode *Node = Op.Val; 499 500 // If this operation defines any values that cannot be represented in a 501 // register on this target, make sure to expand or promote them. 502 if (Node->getNumValues() > 1) { 503 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 504 if (getTypeAction(Node->getValueType(i)) != Legal) { 505 HandleOp(Op.getValue(i)); 506 assert(LegalizedNodes.count(Op) && 507 "Handling didn't add legal operands!"); 508 return LegalizedNodes[Op]; 509 } 510 } 511 512 // Note that LegalizeOp may be reentered even from single-use nodes, which 513 // means that we always must cache transformed nodes. 514 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 515 if (I != LegalizedNodes.end()) return I->second; 516 517 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 518 SDOperand Result = Op; 519 bool isCustom = false; 520 521 switch (Node->getOpcode()) { 522 case ISD::FrameIndex: 523 case ISD::EntryToken: 524 case ISD::Register: 525 case ISD::BasicBlock: 526 case ISD::TargetFrameIndex: 527 case ISD::TargetJumpTable: 528 case ISD::TargetConstant: 529 case ISD::TargetConstantFP: 530 case ISD::TargetConstantPool: 531 case ISD::TargetGlobalAddress: 532 case ISD::TargetExternalSymbol: 533 case ISD::VALUETYPE: 534 case ISD::SRCVALUE: 535 case ISD::STRING: 536 case ISD::CONDCODE: 537 case ISD::GLOBAL_OFFSET_TABLE: 538 // Primitives must all be legal. 539 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 540 "This must be legal!"); 541 break; 542 default: 543 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 544 // If this is a target node, legalize it by legalizing the operands then 545 // passing it through. 546 SmallVector<SDOperand, 8> Ops; 547 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 548 Ops.push_back(LegalizeOp(Node->getOperand(i))); 549 550 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 551 552 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 553 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 554 return Result.getValue(Op.ResNo); 555 } 556 // Otherwise this is an unhandled builtin node. splat. 557#ifndef NDEBUG 558 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 559#endif 560 assert(0 && "Do not know how to legalize this operator!"); 561 abort(); 562 case ISD::GlobalAddress: 563 case ISD::ExternalSymbol: 564 case ISD::ConstantPool: 565 case ISD::JumpTable: // Nothing to do. 566 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 567 default: assert(0 && "This action is not supported yet!"); 568 case TargetLowering::Custom: 569 Tmp1 = TLI.LowerOperation(Op, DAG); 570 if (Tmp1.Val) Result = Tmp1; 571 // FALLTHROUGH if the target doesn't want to lower this op after all. 572 case TargetLowering::Legal: 573 break; 574 } 575 break; 576 case ISD::AssertSext: 577 case ISD::AssertZext: 578 Tmp1 = LegalizeOp(Node->getOperand(0)); 579 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 580 break; 581 case ISD::MERGE_VALUES: 582 // Legalize eliminates MERGE_VALUES nodes. 583 Result = Node->getOperand(Op.ResNo); 584 break; 585 case ISD::CopyFromReg: 586 Tmp1 = LegalizeOp(Node->getOperand(0)); 587 Result = Op.getValue(0); 588 if (Node->getNumValues() == 2) { 589 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 590 } else { 591 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 592 if (Node->getNumOperands() == 3) { 593 Tmp2 = LegalizeOp(Node->getOperand(2)); 594 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 595 } else { 596 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 597 } 598 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 599 } 600 // Since CopyFromReg produces two values, make sure to remember that we 601 // legalized both of them. 602 AddLegalizedOperand(Op.getValue(0), Result); 603 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 604 return Result.getValue(Op.ResNo); 605 case ISD::UNDEF: { 606 MVT::ValueType VT = Op.getValueType(); 607 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 608 default: assert(0 && "This action is not supported yet!"); 609 case TargetLowering::Expand: 610 if (MVT::isInteger(VT)) 611 Result = DAG.getConstant(0, VT); 612 else if (MVT::isFloatingPoint(VT)) 613 Result = DAG.getConstantFP(0, VT); 614 else 615 assert(0 && "Unknown value type!"); 616 break; 617 case TargetLowering::Legal: 618 break; 619 } 620 break; 621 } 622 623 case ISD::INTRINSIC_W_CHAIN: 624 case ISD::INTRINSIC_WO_CHAIN: 625 case ISD::INTRINSIC_VOID: { 626 SmallVector<SDOperand, 8> Ops; 627 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 628 Ops.push_back(LegalizeOp(Node->getOperand(i))); 629 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 630 631 // Allow the target to custom lower its intrinsics if it wants to. 632 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 633 TargetLowering::Custom) { 634 Tmp3 = TLI.LowerOperation(Result, DAG); 635 if (Tmp3.Val) Result = Tmp3; 636 } 637 638 if (Result.Val->getNumValues() == 1) break; 639 640 // Must have return value and chain result. 641 assert(Result.Val->getNumValues() == 2 && 642 "Cannot return more than two values!"); 643 644 // Since loads produce two values, make sure to remember that we 645 // legalized both of them. 646 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 647 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 648 return Result.getValue(Op.ResNo); 649 } 650 651 case ISD::LOCATION: 652 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 653 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 654 655 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 656 case TargetLowering::Promote: 657 default: assert(0 && "This action is not supported yet!"); 658 case TargetLowering::Expand: { 659 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 660 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 661 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other); 662 663 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) { 664 const std::string &FName = 665 cast<StringSDNode>(Node->getOperand(3))->getValue(); 666 const std::string &DirName = 667 cast<StringSDNode>(Node->getOperand(4))->getValue(); 668 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName); 669 670 SmallVector<SDOperand, 8> Ops; 671 Ops.push_back(Tmp1); // chain 672 SDOperand LineOp = Node->getOperand(1); 673 SDOperand ColOp = Node->getOperand(2); 674 675 if (useDEBUG_LOC) { 676 Ops.push_back(LineOp); // line # 677 Ops.push_back(ColOp); // col # 678 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 679 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 680 } else { 681 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 682 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 683 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile); 684 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 685 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size()); 686 } 687 } else { 688 Result = Tmp1; // chain 689 } 690 break; 691 } 692 case TargetLowering::Legal: 693 if (Tmp1 != Node->getOperand(0) || 694 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 695 SmallVector<SDOperand, 8> Ops; 696 Ops.push_back(Tmp1); 697 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 698 Ops.push_back(Node->getOperand(1)); // line # must be legal. 699 Ops.push_back(Node->getOperand(2)); // col # must be legal. 700 } else { 701 // Otherwise promote them. 702 Ops.push_back(PromoteOp(Node->getOperand(1))); 703 Ops.push_back(PromoteOp(Node->getOperand(2))); 704 } 705 Ops.push_back(Node->getOperand(3)); // filename must be legal. 706 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 707 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 708 } 709 break; 710 } 711 break; 712 713 case ISD::DEBUG_LOC: 714 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 715 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 716 default: assert(0 && "This action is not supported yet!"); 717 case TargetLowering::Legal: 718 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 719 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 720 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 721 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 722 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 723 break; 724 } 725 break; 726 727 case ISD::DEBUG_LABEL: 728 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!"); 729 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) { 730 default: assert(0 && "This action is not supported yet!"); 731 case TargetLowering::Legal: 732 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 733 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 734 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 735 break; 736 } 737 break; 738 739 case ISD::Constant: 740 // We know we don't need to expand constants here, constants only have one 741 // value and we check that it is fine above. 742 743 // FIXME: Maybe we should handle things like targets that don't support full 744 // 32-bit immediates? 745 break; 746 case ISD::ConstantFP: { 747 // Spill FP immediates to the constant pool if the target cannot directly 748 // codegen them. Targets often have some immediate values that can be 749 // efficiently generated into an FP register without a load. We explicitly 750 // leave these constants as ConstantFP nodes for the target to deal with. 751 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 752 753 // Check to see if this FP immediate is already legal. 754 bool isLegal = false; 755 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 756 E = TLI.legal_fpimm_end(); I != E; ++I) 757 if (CFP->isExactlyValue(*I)) { 758 isLegal = true; 759 break; 760 } 761 762 // If this is a legal constant, turn it into a TargetConstantFP node. 763 if (isLegal) { 764 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0)); 765 break; 766 } 767 768 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 769 default: assert(0 && "This action is not supported yet!"); 770 case TargetLowering::Custom: 771 Tmp3 = TLI.LowerOperation(Result, DAG); 772 if (Tmp3.Val) { 773 Result = Tmp3; 774 break; 775 } 776 // FALLTHROUGH 777 case TargetLowering::Expand: 778 // Otherwise we need to spill the constant to memory. 779 bool Extend = false; 780 781 // If a FP immediate is precise when represented as a float and if the 782 // target can do an extending load from float to double, we put it into 783 // the constant pool as a float, even if it's is statically typed as a 784 // double. 785 MVT::ValueType VT = CFP->getValueType(0); 786 bool isDouble = VT == MVT::f64; 787 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 788 Type::FloatTy, CFP->getValue()); 789 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 790 // Only do this if the target has a native EXTLOAD instruction from 791 // f32. 792 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 793 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 794 VT = MVT::f32; 795 Extend = true; 796 } 797 798 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 799 if (Extend) { 800 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 801 CPIdx, NULL, 0, MVT::f32); 802 } else { 803 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 804 } 805 } 806 break; 807 } 808 case ISD::TokenFactor: 809 if (Node->getNumOperands() == 2) { 810 Tmp1 = LegalizeOp(Node->getOperand(0)); 811 Tmp2 = LegalizeOp(Node->getOperand(1)); 812 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 813 } else if (Node->getNumOperands() == 3) { 814 Tmp1 = LegalizeOp(Node->getOperand(0)); 815 Tmp2 = LegalizeOp(Node->getOperand(1)); 816 Tmp3 = LegalizeOp(Node->getOperand(2)); 817 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 818 } else { 819 SmallVector<SDOperand, 8> Ops; 820 // Legalize the operands. 821 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 822 Ops.push_back(LegalizeOp(Node->getOperand(i))); 823 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 824 } 825 break; 826 827 case ISD::FORMAL_ARGUMENTS: 828 case ISD::CALL: 829 // The only option for this is to custom lower it. 830 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 831 assert(Tmp3.Val && "Target didn't custom lower this node!"); 832 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() && 833 "Lowering call/formal_arguments produced unexpected # results!"); 834 835 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 836 // remember that we legalized all of them, so it doesn't get relegalized. 837 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 838 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 839 if (Op.ResNo == i) 840 Tmp2 = Tmp1; 841 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 842 } 843 return Tmp2; 844 845 case ISD::BUILD_VECTOR: 846 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 847 default: assert(0 && "This action is not supported yet!"); 848 case TargetLowering::Custom: 849 Tmp3 = TLI.LowerOperation(Result, DAG); 850 if (Tmp3.Val) { 851 Result = Tmp3; 852 break; 853 } 854 // FALLTHROUGH 855 case TargetLowering::Expand: 856 Result = ExpandBUILD_VECTOR(Result.Val); 857 break; 858 } 859 break; 860 case ISD::INSERT_VECTOR_ELT: 861 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 862 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 863 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 864 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 865 866 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 867 Node->getValueType(0))) { 868 default: assert(0 && "This action is not supported yet!"); 869 case TargetLowering::Legal: 870 break; 871 case TargetLowering::Custom: 872 Tmp3 = TLI.LowerOperation(Result, DAG); 873 if (Tmp3.Val) { 874 Result = Tmp3; 875 break; 876 } 877 // FALLTHROUGH 878 case TargetLowering::Expand: { 879 // If the insert index is a constant, codegen this as a scalar_to_vector, 880 // then a shuffle that inserts it into the right position in the vector. 881 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 882 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 883 Tmp1.getValueType(), Tmp2); 884 885 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 886 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 887 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT); 888 889 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 890 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 891 // the RHS. 892 SmallVector<SDOperand, 8> ShufOps; 893 for (unsigned i = 0; i != NumElts; ++i) { 894 if (i != InsertPos->getValue()) 895 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 896 else 897 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 898 } 899 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 900 &ShufOps[0], ShufOps.size()); 901 902 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 903 Tmp1, ScVec, ShufMask); 904 Result = LegalizeOp(Result); 905 break; 906 } 907 908 // If the target doesn't support this, we have to spill the input vector 909 // to a temporary stack slot, update the element, then reload it. This is 910 // badness. We could also load the value into a vector register (either 911 // with a "move to register" or "extload into register" instruction, then 912 // permute it into place, if the idx is a constant and if the idx is 913 // supported by the target. 914 MVT::ValueType VT = Tmp1.getValueType(); 915 MVT::ValueType EltVT = Tmp2.getValueType(); 916 MVT::ValueType IdxVT = Tmp3.getValueType(); 917 MVT::ValueType PtrVT = TLI.getPointerTy(); 918 SDOperand StackPtr = CreateStackTemporary(VT); 919 // Store the vector. 920 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), 921 Tmp1, StackPtr, DAG.getSrcValue(NULL)); 922 923 // Truncate or zero extend offset to target pointer type. 924 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 925 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 926 // Add the offset to the index. 927 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 928 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 929 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 930 // Store the scalar value. 931 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, DAG.getSrcValue(NULL)); 932 // Load the updated vector. 933 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); 934 break; 935 } 936 } 937 break; 938 case ISD::SCALAR_TO_VECTOR: 939 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 940 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 941 break; 942 } 943 944 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 945 Result = DAG.UpdateNodeOperands(Result, Tmp1); 946 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 947 Node->getValueType(0))) { 948 default: assert(0 && "This action is not supported yet!"); 949 case TargetLowering::Legal: 950 break; 951 case TargetLowering::Custom: 952 Tmp3 = TLI.LowerOperation(Result, DAG); 953 if (Tmp3.Val) { 954 Result = Tmp3; 955 break; 956 } 957 // FALLTHROUGH 958 case TargetLowering::Expand: 959 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 960 break; 961 } 962 break; 963 case ISD::VECTOR_SHUFFLE: 964 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 965 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 966 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 967 968 // Allow targets to custom lower the SHUFFLEs they support. 969 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 970 default: assert(0 && "Unknown operation action!"); 971 case TargetLowering::Legal: 972 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 973 "vector shuffle should not be created if not legal!"); 974 break; 975 case TargetLowering::Custom: 976 Tmp3 = TLI.LowerOperation(Result, DAG); 977 if (Tmp3.Val) { 978 Result = Tmp3; 979 break; 980 } 981 // FALLTHROUGH 982 case TargetLowering::Expand: { 983 MVT::ValueType VT = Node->getValueType(0); 984 MVT::ValueType EltVT = MVT::getVectorBaseType(VT); 985 MVT::ValueType PtrVT = TLI.getPointerTy(); 986 SDOperand Mask = Node->getOperand(2); 987 unsigned NumElems = Mask.getNumOperands(); 988 SmallVector<SDOperand,8> Ops; 989 for (unsigned i = 0; i != NumElems; ++i) { 990 SDOperand Arg = Mask.getOperand(i); 991 if (Arg.getOpcode() == ISD::UNDEF) { 992 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 993 } else { 994 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 995 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 996 if (Idx < NumElems) 997 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 998 DAG.getConstant(Idx, PtrVT))); 999 else 1000 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1001 DAG.getConstant(Idx - NumElems, PtrVT))); 1002 } 1003 } 1004 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1005 break; 1006 } 1007 case TargetLowering::Promote: { 1008 // Change base type to a different vector type. 1009 MVT::ValueType OVT = Node->getValueType(0); 1010 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1011 1012 // Cast the two input vectors. 1013 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1014 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1015 1016 // Convert the shuffle mask to the right # elements. 1017 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1018 assert(Tmp3.Val && "Shuffle not legal?"); 1019 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1020 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1021 break; 1022 } 1023 } 1024 break; 1025 1026 case ISD::EXTRACT_VECTOR_ELT: 1027 Tmp1 = LegalizeOp(Node->getOperand(0)); 1028 Tmp2 = LegalizeOp(Node->getOperand(1)); 1029 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1030 1031 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, 1032 Tmp1.getValueType())) { 1033 default: assert(0 && "This action is not supported yet!"); 1034 case TargetLowering::Legal: 1035 break; 1036 case TargetLowering::Custom: 1037 Tmp3 = TLI.LowerOperation(Result, DAG); 1038 if (Tmp3.Val) { 1039 Result = Tmp3; 1040 break; 1041 } 1042 // FALLTHROUGH 1043 case TargetLowering::Expand: 1044 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1045 break; 1046 } 1047 break; 1048 1049 case ISD::VEXTRACT_VECTOR_ELT: 1050 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op)); 1051 break; 1052 1053 case ISD::CALLSEQ_START: { 1054 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1055 1056 // Recursively Legalize all of the inputs of the call end that do not lead 1057 // to this call start. This ensures that any libcalls that need be inserted 1058 // are inserted *before* the CALLSEQ_START. 1059 {std::set<SDNode*> NodesLeadingTo; 1060 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1061 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1062 NodesLeadingTo); 1063 } 1064 1065 // Now that we legalized all of the inputs (which may have inserted 1066 // libcalls) create the new CALLSEQ_START node. 1067 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1068 1069 // Merge in the last call, to ensure that this call start after the last 1070 // call ended. 1071 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1072 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1073 Tmp1 = LegalizeOp(Tmp1); 1074 } 1075 1076 // Do not try to legalize the target-specific arguments (#1+). 1077 if (Tmp1 != Node->getOperand(0)) { 1078 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1079 Ops[0] = Tmp1; 1080 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1081 } 1082 1083 // Remember that the CALLSEQ_START is legalized. 1084 AddLegalizedOperand(Op.getValue(0), Result); 1085 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1086 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1087 1088 // Now that the callseq_start and all of the non-call nodes above this call 1089 // sequence have been legalized, legalize the call itself. During this 1090 // process, no libcalls can/will be inserted, guaranteeing that no calls 1091 // can overlap. 1092 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1093 SDOperand InCallSEQ = LastCALLSEQ_END; 1094 // Note that we are selecting this call! 1095 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1096 IsLegalizingCall = true; 1097 1098 // Legalize the call, starting from the CALLSEQ_END. 1099 LegalizeOp(LastCALLSEQ_END); 1100 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1101 return Result; 1102 } 1103 case ISD::CALLSEQ_END: 1104 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1105 // will cause this node to be legalized as well as handling libcalls right. 1106 if (LastCALLSEQ_END.Val != Node) { 1107 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1108 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1109 assert(I != LegalizedNodes.end() && 1110 "Legalizing the call start should have legalized this node!"); 1111 return I->second; 1112 } 1113 1114 // Otherwise, the call start has been legalized and everything is going 1115 // according to plan. Just legalize ourselves normally here. 1116 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1117 // Do not try to legalize the target-specific arguments (#1+), except for 1118 // an optional flag input. 1119 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1120 if (Tmp1 != Node->getOperand(0)) { 1121 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1122 Ops[0] = Tmp1; 1123 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1124 } 1125 } else { 1126 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1127 if (Tmp1 != Node->getOperand(0) || 1128 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1129 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1130 Ops[0] = Tmp1; 1131 Ops.back() = Tmp2; 1132 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1133 } 1134 } 1135 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1136 // This finishes up call legalization. 1137 IsLegalizingCall = false; 1138 1139 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1140 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1141 if (Node->getNumValues() == 2) 1142 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1143 return Result.getValue(Op.ResNo); 1144 case ISD::DYNAMIC_STACKALLOC: { 1145 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1146 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1147 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1148 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1149 1150 Tmp1 = Result.getValue(0); 1151 Tmp2 = Result.getValue(1); 1152 switch (TLI.getOperationAction(Node->getOpcode(), 1153 Node->getValueType(0))) { 1154 default: assert(0 && "This action is not supported yet!"); 1155 case TargetLowering::Expand: { 1156 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1157 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1158 " not tell us which reg is the stack pointer!"); 1159 SDOperand Chain = Tmp1.getOperand(0); 1160 SDOperand Size = Tmp2.getOperand(1); 1161 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0)); 1162 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value 1163 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain 1164 Tmp1 = LegalizeOp(Tmp1); 1165 Tmp2 = LegalizeOp(Tmp2); 1166 break; 1167 } 1168 case TargetLowering::Custom: 1169 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1170 if (Tmp3.Val) { 1171 Tmp1 = LegalizeOp(Tmp3); 1172 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1173 } 1174 break; 1175 case TargetLowering::Legal: 1176 break; 1177 } 1178 // Since this op produce two values, make sure to remember that we 1179 // legalized both of them. 1180 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1181 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1182 return Op.ResNo ? Tmp2 : Tmp1; 1183 } 1184 case ISD::INLINEASM: { 1185 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1186 bool Changed = false; 1187 // Legalize all of the operands of the inline asm, in case they are nodes 1188 // that need to be expanded or something. Note we skip the asm string and 1189 // all of the TargetConstant flags. 1190 SDOperand Op = LegalizeOp(Ops[0]); 1191 Changed = Op != Ops[0]; 1192 Ops[0] = Op; 1193 1194 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1195 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1196 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1197 for (++i; NumVals; ++i, --NumVals) { 1198 SDOperand Op = LegalizeOp(Ops[i]); 1199 if (Op != Ops[i]) { 1200 Changed = true; 1201 Ops[i] = Op; 1202 } 1203 } 1204 } 1205 1206 if (HasInFlag) { 1207 Op = LegalizeOp(Ops.back()); 1208 Changed |= Op != Ops.back(); 1209 Ops.back() = Op; 1210 } 1211 1212 if (Changed) 1213 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1214 1215 // INLINE asm returns a chain and flag, make sure to add both to the map. 1216 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1217 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1218 return Result.getValue(Op.ResNo); 1219 } 1220 case ISD::BR: 1221 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1222 // Ensure that libcalls are emitted before a branch. 1223 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1224 Tmp1 = LegalizeOp(Tmp1); 1225 LastCALLSEQ_END = DAG.getEntryNode(); 1226 1227 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1228 break; 1229 case ISD::BRIND: 1230 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1231 // Ensure that libcalls are emitted before a branch. 1232 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1233 Tmp1 = LegalizeOp(Tmp1); 1234 LastCALLSEQ_END = DAG.getEntryNode(); 1235 1236 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1237 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1238 case Legal: 1239 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1240 break; 1241 } 1242 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1243 break; 1244 case ISD::BRCOND: 1245 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1246 // Ensure that libcalls are emitted before a return. 1247 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1248 Tmp1 = LegalizeOp(Tmp1); 1249 LastCALLSEQ_END = DAG.getEntryNode(); 1250 1251 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1252 case Expand: assert(0 && "It's impossible to expand bools"); 1253 case Legal: 1254 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1255 break; 1256 case Promote: 1257 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1258 break; 1259 } 1260 1261 // Basic block destination (Op#2) is always legal. 1262 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1263 1264 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1265 default: assert(0 && "This action is not supported yet!"); 1266 case TargetLowering::Legal: break; 1267 case TargetLowering::Custom: 1268 Tmp1 = TLI.LowerOperation(Result, DAG); 1269 if (Tmp1.Val) Result = Tmp1; 1270 break; 1271 case TargetLowering::Expand: 1272 // Expand brcond's setcc into its constituent parts and create a BR_CC 1273 // Node. 1274 if (Tmp2.getOpcode() == ISD::SETCC) { 1275 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1276 Tmp2.getOperand(0), Tmp2.getOperand(1), 1277 Node->getOperand(2)); 1278 } else { 1279 // Make sure the condition is either zero or one. It may have been 1280 // promoted from something else. 1281 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType()); 1282 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1)) 1283 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1284 1285 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1286 DAG.getCondCode(ISD::SETNE), Tmp2, 1287 DAG.getConstant(0, Tmp2.getValueType()), 1288 Node->getOperand(2)); 1289 } 1290 break; 1291 } 1292 break; 1293 case ISD::BR_CC: 1294 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1295 // Ensure that libcalls are emitted before a branch. 1296 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1297 Tmp1 = LegalizeOp(Tmp1); 1298 LastCALLSEQ_END = DAG.getEntryNode(); 1299 1300 Tmp2 = Node->getOperand(2); // LHS 1301 Tmp3 = Node->getOperand(3); // RHS 1302 Tmp4 = Node->getOperand(1); // CC 1303 1304 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1305 1306 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1307 // the LHS is a legal SETCC itself. In this case, we need to compare 1308 // the result against zero to select between true and false values. 1309 if (Tmp3.Val == 0) { 1310 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1311 Tmp4 = DAG.getCondCode(ISD::SETNE); 1312 } 1313 1314 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1315 Node->getOperand(4)); 1316 1317 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1318 default: assert(0 && "Unexpected action for BR_CC!"); 1319 case TargetLowering::Legal: break; 1320 case TargetLowering::Custom: 1321 Tmp4 = TLI.LowerOperation(Result, DAG); 1322 if (Tmp4.Val) Result = Tmp4; 1323 break; 1324 } 1325 break; 1326 case ISD::LOAD: { 1327 LoadSDNode *LD = cast<LoadSDNode>(Node); 1328 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1329 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1330 1331 ISD::LoadExtType ExtType = LD->getExtensionType(); 1332 if (ExtType == ISD::NON_EXTLOAD) { 1333 MVT::ValueType VT = Node->getValueType(0); 1334 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1335 Tmp3 = Result.getValue(0); 1336 Tmp4 = Result.getValue(1); 1337 1338 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1339 default: assert(0 && "This action is not supported yet!"); 1340 case TargetLowering::Legal: break; 1341 case TargetLowering::Custom: 1342 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1343 if (Tmp1.Val) { 1344 Tmp3 = LegalizeOp(Tmp1); 1345 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1346 } 1347 break; 1348 case TargetLowering::Promote: { 1349 // Only promote a load of vector type to another. 1350 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1351 // Change base type to a different vector type. 1352 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1353 1354 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1355 LD->getSrcValueOffset()); 1356 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1357 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1358 break; 1359 } 1360 } 1361 // Since loads produce two values, make sure to remember that we 1362 // legalized both of them. 1363 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1364 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1365 return Op.ResNo ? Tmp4 : Tmp3; 1366 } else { 1367 MVT::ValueType SrcVT = LD->getLoadedVT(); 1368 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1369 default: assert(0 && "This action is not supported yet!"); 1370 case TargetLowering::Promote: 1371 assert(SrcVT == MVT::i1 && 1372 "Can only promote extending LOAD from i1 -> i8!"); 1373 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1374 LD->getSrcValue(), LD->getSrcValueOffset(), 1375 MVT::i8); 1376 Tmp1 = Result.getValue(0); 1377 Tmp2 = Result.getValue(1); 1378 break; 1379 case TargetLowering::Custom: 1380 isCustom = true; 1381 // FALLTHROUGH 1382 case TargetLowering::Legal: 1383 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1384 Tmp1 = Result.getValue(0); 1385 Tmp2 = Result.getValue(1); 1386 1387 if (isCustom) { 1388 Tmp3 = TLI.LowerOperation(Result, DAG); 1389 if (Tmp3.Val) { 1390 Tmp1 = LegalizeOp(Tmp3); 1391 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1392 } 1393 } 1394 break; 1395 case TargetLowering::Expand: 1396 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1397 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1398 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 1399 LD->getSrcValueOffset()); 1400 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1401 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1402 Tmp2 = LegalizeOp(Load.getValue(1)); 1403 break; 1404 } 1405 assert(ExtType != ISD::EXTLOAD && "EXTLOAD should always be supported!"); 1406 // Turn the unsupported load into an EXTLOAD followed by an explicit 1407 // zero/sign extend inreg. 1408 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1409 Tmp1, Tmp2, LD->getSrcValue(), 1410 LD->getSrcValueOffset(), SrcVT); 1411 SDOperand ValRes; 1412 if (ExtType == ISD::SEXTLOAD) 1413 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1414 Result, DAG.getValueType(SrcVT)); 1415 else 1416 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1417 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1418 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1419 break; 1420 } 1421 // Since loads produce two values, make sure to remember that we legalized 1422 // both of them. 1423 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1424 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1425 return Op.ResNo ? Tmp2 : Tmp1; 1426 } 1427 } 1428 case ISD::EXTRACT_ELEMENT: { 1429 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1430 switch (getTypeAction(OpTy)) { 1431 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1432 case Legal: 1433 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1434 // 1 -> Hi 1435 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1436 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1437 TLI.getShiftAmountTy())); 1438 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1439 } else { 1440 // 0 -> Lo 1441 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1442 Node->getOperand(0)); 1443 } 1444 break; 1445 case Expand: 1446 // Get both the low and high parts. 1447 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1448 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1449 Result = Tmp2; // 1 -> Hi 1450 else 1451 Result = Tmp1; // 0 -> Lo 1452 break; 1453 } 1454 break; 1455 } 1456 1457 case ISD::CopyToReg: 1458 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1459 1460 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1461 "Register type must be legal!"); 1462 // Legalize the incoming value (must be a legal type). 1463 Tmp2 = LegalizeOp(Node->getOperand(2)); 1464 if (Node->getNumValues() == 1) { 1465 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1466 } else { 1467 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1468 if (Node->getNumOperands() == 4) { 1469 Tmp3 = LegalizeOp(Node->getOperand(3)); 1470 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1471 Tmp3); 1472 } else { 1473 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1474 } 1475 1476 // Since this produces two values, make sure to remember that we legalized 1477 // both of them. 1478 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1479 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1480 return Result; 1481 } 1482 break; 1483 1484 case ISD::RET: 1485 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1486 1487 // Ensure that libcalls are emitted before a return. 1488 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1489 Tmp1 = LegalizeOp(Tmp1); 1490 LastCALLSEQ_END = DAG.getEntryNode(); 1491 1492 switch (Node->getNumOperands()) { 1493 case 3: // ret val 1494 Tmp2 = Node->getOperand(1); 1495 Tmp3 = Node->getOperand(2); // Signness 1496 switch (getTypeAction(Tmp2.getValueType())) { 1497 case Legal: 1498 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1499 break; 1500 case Expand: 1501 if (Tmp2.getValueType() != MVT::Vector) { 1502 SDOperand Lo, Hi; 1503 ExpandOp(Tmp2, Lo, Hi); 1504 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3); 1505 Result = LegalizeOp(Result); 1506 } else { 1507 SDNode *InVal = Tmp2.Val; 1508 unsigned NumElems = 1509 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 1510 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 1511 1512 // Figure out if there is a Packed type corresponding to this Vector 1513 // type. If so, convert to the packed type. 1514 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1515 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 1516 // Turn this into a return of the packed type. 1517 Tmp2 = PackVectorOp(Tmp2, TVT); 1518 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1519 } else if (NumElems == 1) { 1520 // Turn this into a return of the scalar type. 1521 Tmp2 = PackVectorOp(Tmp2, EVT); 1522 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1523 1524 // FIXME: Returns of gcc generic vectors smaller than a legal type 1525 // should be returned in integer registers! 1526 1527 // The scalarized value type may not be legal, e.g. it might require 1528 // promotion or expansion. Relegalize the return. 1529 Result = LegalizeOp(Result); 1530 } else { 1531 // FIXME: Returns of gcc generic vectors larger than a legal vector 1532 // type should be returned by reference! 1533 SDOperand Lo, Hi; 1534 SplitVectorOp(Tmp2, Lo, Hi); 1535 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3); 1536 Result = LegalizeOp(Result); 1537 } 1538 } 1539 break; 1540 case Promote: 1541 Tmp2 = PromoteOp(Node->getOperand(1)); 1542 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1543 Result = LegalizeOp(Result); 1544 break; 1545 } 1546 break; 1547 case 1: // ret void 1548 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1549 break; 1550 default: { // ret <values> 1551 SmallVector<SDOperand, 8> NewValues; 1552 NewValues.push_back(Tmp1); 1553 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 1554 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1555 case Legal: 1556 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1557 NewValues.push_back(Node->getOperand(i+1)); 1558 break; 1559 case Expand: { 1560 SDOperand Lo, Hi; 1561 assert(Node->getOperand(i).getValueType() != MVT::Vector && 1562 "FIXME: TODO: implement returning non-legal vector types!"); 1563 ExpandOp(Node->getOperand(i), Lo, Hi); 1564 NewValues.push_back(Lo); 1565 NewValues.push_back(Node->getOperand(i+1)); 1566 NewValues.push_back(Hi); 1567 NewValues.push_back(Node->getOperand(i+1)); 1568 break; 1569 } 1570 case Promote: 1571 assert(0 && "Can't promote multiple return value yet!"); 1572 } 1573 1574 if (NewValues.size() == Node->getNumOperands()) 1575 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 1576 else 1577 Result = DAG.getNode(ISD::RET, MVT::Other, 1578 &NewValues[0], NewValues.size()); 1579 break; 1580 } 1581 } 1582 1583 if (Result.getOpcode() == ISD::RET) { 1584 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 1585 default: assert(0 && "This action is not supported yet!"); 1586 case TargetLowering::Legal: break; 1587 case TargetLowering::Custom: 1588 Tmp1 = TLI.LowerOperation(Result, DAG); 1589 if (Tmp1.Val) Result = Tmp1; 1590 break; 1591 } 1592 } 1593 break; 1594 case ISD::STORE: { 1595 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1596 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1597 1598 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1599 // FIXME: We shouldn't do this for TargetConstantFP's. 1600 // FIXME: move this to the DAG Combiner! 1601 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1602 if (CFP->getValueType(0) == MVT::f32) { 1603 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 1604 } else { 1605 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1606 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 1607 } 1608 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, Node->getOperand(3)); 1609 break; 1610 } 1611 1612 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1613 case Legal: { 1614 Tmp3 = LegalizeOp(Node->getOperand(1)); 1615 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1616 Node->getOperand(3)); 1617 1618 MVT::ValueType VT = Tmp3.getValueType(); 1619 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1620 default: assert(0 && "This action is not supported yet!"); 1621 case TargetLowering::Legal: break; 1622 case TargetLowering::Custom: 1623 Tmp1 = TLI.LowerOperation(Result, DAG); 1624 if (Tmp1.Val) Result = Tmp1; 1625 break; 1626 case TargetLowering::Promote: 1627 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 1628 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 1629 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1630 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1631 Node->getOperand(3)); 1632 break; 1633 } 1634 break; 1635 } 1636 case Promote: 1637 // Truncate the value and store the result. 1638 Tmp3 = PromoteOp(Node->getOperand(1)); 1639 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1640 Node->getOperand(3), 1641 DAG.getValueType(Node->getOperand(1).getValueType())); 1642 break; 1643 1644 case Expand: 1645 unsigned IncrementSize = 0; 1646 SDOperand Lo, Hi; 1647 1648 // If this is a vector type, then we have to calculate the increment as 1649 // the product of the element size in bytes, and the number of elements 1650 // in the high half of the vector. 1651 if (Node->getOperand(1).getValueType() == MVT::Vector) { 1652 SDNode *InVal = Node->getOperand(1).Val; 1653 unsigned NumElems = 1654 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 1655 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 1656 1657 // Figure out if there is a Packed type corresponding to this Vector 1658 // type. If so, convert to the packed type. 1659 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1660 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 1661 // Turn this into a normal store of the packed type. 1662 Tmp3 = PackVectorOp(Node->getOperand(1), TVT); 1663 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1664 Node->getOperand(3)); 1665 Result = LegalizeOp(Result); 1666 break; 1667 } else if (NumElems == 1) { 1668 // Turn this into a normal store of the scalar type. 1669 Tmp3 = PackVectorOp(Node->getOperand(1), EVT); 1670 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1671 Node->getOperand(3)); 1672 // The scalarized value type may not be legal, e.g. it might require 1673 // promotion or expansion. Relegalize the scalar store. 1674 Result = LegalizeOp(Result); 1675 break; 1676 } else { 1677 SplitVectorOp(Node->getOperand(1), Lo, Hi); 1678 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; 1679 } 1680 } else { 1681 ExpandOp(Node->getOperand(1), Lo, Hi); 1682 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1683 1684 if (!TLI.isLittleEndian()) 1685 std::swap(Lo, Hi); 1686 } 1687 1688 Lo = DAG.getStore(Tmp1, Lo, Tmp2, Node->getOperand(3)); 1689 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1690 getIntPtrConstant(IncrementSize)); 1691 assert(isTypeLegal(Tmp2.getValueType()) && 1692 "Pointers must be legal!"); 1693 // FIXME: This sets the srcvalue of both halves to be the same, which is 1694 // wrong. 1695 Hi = DAG.getStore(Tmp1, Hi, Tmp2, Node->getOperand(3)); 1696 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1697 break; 1698 } 1699 break; 1700 } 1701 case ISD::PCMARKER: 1702 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1703 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1704 break; 1705 case ISD::STACKSAVE: 1706 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1707 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1708 Tmp1 = Result.getValue(0); 1709 Tmp2 = Result.getValue(1); 1710 1711 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 1712 default: assert(0 && "This action is not supported yet!"); 1713 case TargetLowering::Legal: break; 1714 case TargetLowering::Custom: 1715 Tmp3 = TLI.LowerOperation(Result, DAG); 1716 if (Tmp3.Val) { 1717 Tmp1 = LegalizeOp(Tmp3); 1718 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1719 } 1720 break; 1721 case TargetLowering::Expand: 1722 // Expand to CopyFromReg if the target set 1723 // StackPointerRegisterToSaveRestore. 1724 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1725 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 1726 Node->getValueType(0)); 1727 Tmp2 = Tmp1.getValue(1); 1728 } else { 1729 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 1730 Tmp2 = Node->getOperand(0); 1731 } 1732 break; 1733 } 1734 1735 // Since stacksave produce two values, make sure to remember that we 1736 // legalized both of them. 1737 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1738 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1739 return Op.ResNo ? Tmp2 : Tmp1; 1740 1741 case ISD::STACKRESTORE: 1742 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1743 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1744 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1745 1746 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 1747 default: assert(0 && "This action is not supported yet!"); 1748 case TargetLowering::Legal: break; 1749 case TargetLowering::Custom: 1750 Tmp1 = TLI.LowerOperation(Result, DAG); 1751 if (Tmp1.Val) Result = Tmp1; 1752 break; 1753 case TargetLowering::Expand: 1754 // Expand to CopyToReg if the target set 1755 // StackPointerRegisterToSaveRestore. 1756 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1757 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 1758 } else { 1759 Result = Tmp1; 1760 } 1761 break; 1762 } 1763 break; 1764 1765 case ISD::READCYCLECOUNTER: 1766 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1767 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1768 1769 // Since rdcc produce two values, make sure to remember that we legalized 1770 // both of them. 1771 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1772 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1773 return Result; 1774 1775 case ISD::TRUNCSTORE: { 1776 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1777 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1778 1779 assert(isTypeLegal(Node->getOperand(1).getValueType()) && 1780 "Cannot handle illegal TRUNCSTORE yet!"); 1781 Tmp2 = LegalizeOp(Node->getOperand(1)); 1782 1783 // The only promote case we handle is TRUNCSTORE:i1 X into 1784 // -> TRUNCSTORE:i8 (and X, 1) 1785 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1786 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1787 TargetLowering::Promote) { 1788 // Promote the bool to a mask then store. 1789 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1790 DAG.getConstant(1, Tmp2.getValueType())); 1791 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1792 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1793 1794 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1795 Tmp3 != Node->getOperand(2)) { 1796 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 1797 Node->getOperand(3), Node->getOperand(4)); 1798 } 1799 1800 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT(); 1801 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) { 1802 default: assert(0 && "This action is not supported yet!"); 1803 case TargetLowering::Legal: break; 1804 case TargetLowering::Custom: 1805 Tmp1 = TLI.LowerOperation(Result, DAG); 1806 if (Tmp1.Val) Result = Tmp1; 1807 break; 1808 } 1809 break; 1810 } 1811 case ISD::SELECT: 1812 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1813 case Expand: assert(0 && "It's impossible to expand bools"); 1814 case Legal: 1815 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1816 break; 1817 case Promote: 1818 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1819 break; 1820 } 1821 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1822 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1823 1824 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1825 1826 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1827 default: assert(0 && "This action is not supported yet!"); 1828 case TargetLowering::Legal: break; 1829 case TargetLowering::Custom: { 1830 Tmp1 = TLI.LowerOperation(Result, DAG); 1831 if (Tmp1.Val) Result = Tmp1; 1832 break; 1833 } 1834 case TargetLowering::Expand: 1835 if (Tmp1.getOpcode() == ISD::SETCC) { 1836 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1837 Tmp2, Tmp3, 1838 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1839 } else { 1840 // Make sure the condition is either zero or one. It may have been 1841 // promoted from something else. 1842 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType()); 1843 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1)) 1844 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1845 Result = DAG.getSelectCC(Tmp1, 1846 DAG.getConstant(0, Tmp1.getValueType()), 1847 Tmp2, Tmp3, ISD::SETNE); 1848 } 1849 break; 1850 case TargetLowering::Promote: { 1851 MVT::ValueType NVT = 1852 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1853 unsigned ExtOp, TruncOp; 1854 if (MVT::isVector(Tmp2.getValueType())) { 1855 ExtOp = ISD::BIT_CONVERT; 1856 TruncOp = ISD::BIT_CONVERT; 1857 } else if (MVT::isInteger(Tmp2.getValueType())) { 1858 ExtOp = ISD::ANY_EXTEND; 1859 TruncOp = ISD::TRUNCATE; 1860 } else { 1861 ExtOp = ISD::FP_EXTEND; 1862 TruncOp = ISD::FP_ROUND; 1863 } 1864 // Promote each of the values to the new type. 1865 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1866 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1867 // Perform the larger operation, then round down. 1868 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1869 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1870 break; 1871 } 1872 } 1873 break; 1874 case ISD::SELECT_CC: { 1875 Tmp1 = Node->getOperand(0); // LHS 1876 Tmp2 = Node->getOperand(1); // RHS 1877 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1878 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1879 SDOperand CC = Node->getOperand(4); 1880 1881 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 1882 1883 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1884 // the LHS is a legal SETCC itself. In this case, we need to compare 1885 // the result against zero to select between true and false values. 1886 if (Tmp2.Val == 0) { 1887 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1888 CC = DAG.getCondCode(ISD::SETNE); 1889 } 1890 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 1891 1892 // Everything is legal, see if we should expand this op or something. 1893 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 1894 default: assert(0 && "This action is not supported yet!"); 1895 case TargetLowering::Legal: break; 1896 case TargetLowering::Custom: 1897 Tmp1 = TLI.LowerOperation(Result, DAG); 1898 if (Tmp1.Val) Result = Tmp1; 1899 break; 1900 } 1901 break; 1902 } 1903 case ISD::SETCC: 1904 Tmp1 = Node->getOperand(0); 1905 Tmp2 = Node->getOperand(1); 1906 Tmp3 = Node->getOperand(2); 1907 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 1908 1909 // If we had to Expand the SetCC operands into a SELECT node, then it may 1910 // not always be possible to return a true LHS & RHS. In this case, just 1911 // return the value we legalized, returned in the LHS 1912 if (Tmp2.Val == 0) { 1913 Result = Tmp1; 1914 break; 1915 } 1916 1917 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 1918 default: assert(0 && "Cannot handle this action for SETCC yet!"); 1919 case TargetLowering::Custom: 1920 isCustom = true; 1921 // FALLTHROUGH. 1922 case TargetLowering::Legal: 1923 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1924 if (isCustom) { 1925 Tmp3 = TLI.LowerOperation(Result, DAG); 1926 if (Tmp3.Val) Result = Tmp3; 1927 } 1928 break; 1929 case TargetLowering::Promote: { 1930 // First step, figure out the appropriate operation to use. 1931 // Allow SETCC to not be supported for all legal data types 1932 // Mostly this targets FP 1933 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 1934 MVT::ValueType OldVT = NewInTy; 1935 1936 // Scan for the appropriate larger type to use. 1937 while (1) { 1938 NewInTy = (MVT::ValueType)(NewInTy+1); 1939 1940 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 1941 "Fell off of the edge of the integer world"); 1942 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 1943 "Fell off of the edge of the floating point world"); 1944 1945 // If the target supports SETCC of this type, use it. 1946 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 1947 break; 1948 } 1949 if (MVT::isInteger(NewInTy)) 1950 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1951 else { 1952 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 1953 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 1954 } 1955 Tmp1 = LegalizeOp(Tmp1); 1956 Tmp2 = LegalizeOp(Tmp2); 1957 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1958 Result = LegalizeOp(Result); 1959 break; 1960 } 1961 case TargetLowering::Expand: 1962 // Expand a setcc node into a select_cc of the same condition, lhs, and 1963 // rhs that selects between const 1 (true) and const 0 (false). 1964 MVT::ValueType VT = Node->getValueType(0); 1965 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1966 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1967 Node->getOperand(2)); 1968 break; 1969 } 1970 break; 1971 case ISD::MEMSET: 1972 case ISD::MEMCPY: 1973 case ISD::MEMMOVE: { 1974 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1975 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1976 1977 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1978 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1979 case Expand: assert(0 && "Cannot expand a byte!"); 1980 case Legal: 1981 Tmp3 = LegalizeOp(Node->getOperand(2)); 1982 break; 1983 case Promote: 1984 Tmp3 = PromoteOp(Node->getOperand(2)); 1985 break; 1986 } 1987 } else { 1988 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1989 } 1990 1991 SDOperand Tmp4; 1992 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1993 case Expand: { 1994 // Length is too big, just take the lo-part of the length. 1995 SDOperand HiPart; 1996 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1997 break; 1998 } 1999 case Legal: 2000 Tmp4 = LegalizeOp(Node->getOperand(3)); 2001 break; 2002 case Promote: 2003 Tmp4 = PromoteOp(Node->getOperand(3)); 2004 break; 2005 } 2006 2007 SDOperand Tmp5; 2008 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2009 case Expand: assert(0 && "Cannot expand this yet!"); 2010 case Legal: 2011 Tmp5 = LegalizeOp(Node->getOperand(4)); 2012 break; 2013 case Promote: 2014 Tmp5 = PromoteOp(Node->getOperand(4)); 2015 break; 2016 } 2017 2018 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2019 default: assert(0 && "This action not implemented for this operation!"); 2020 case TargetLowering::Custom: 2021 isCustom = true; 2022 // FALLTHROUGH 2023 case TargetLowering::Legal: 2024 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 2025 if (isCustom) { 2026 Tmp1 = TLI.LowerOperation(Result, DAG); 2027 if (Tmp1.Val) Result = Tmp1; 2028 } 2029 break; 2030 case TargetLowering::Expand: { 2031 // Otherwise, the target does not support this operation. Lower the 2032 // operation to an explicit libcall as appropriate. 2033 MVT::ValueType IntPtr = TLI.getPointerTy(); 2034 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2035 std::vector<std::pair<SDOperand, const Type*> > Args; 2036 2037 const char *FnName = 0; 2038 if (Node->getOpcode() == ISD::MEMSET) { 2039 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 2040 // Extend the (previously legalized) ubyte argument to be an int value 2041 // for the call. 2042 if (Tmp3.getValueType() > MVT::i32) 2043 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2044 else 2045 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2046 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 2047 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 2048 2049 FnName = "memset"; 2050 } else if (Node->getOpcode() == ISD::MEMCPY || 2051 Node->getOpcode() == ISD::MEMMOVE) { 2052 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 2053 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 2054 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 2055 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2056 } else { 2057 assert(0 && "Unknown op!"); 2058 } 2059 2060 std::pair<SDOperand,SDOperand> CallResult = 2061 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 2062 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2063 Result = CallResult.second; 2064 break; 2065 } 2066 } 2067 break; 2068 } 2069 2070 case ISD::SHL_PARTS: 2071 case ISD::SRA_PARTS: 2072 case ISD::SRL_PARTS: { 2073 SmallVector<SDOperand, 8> Ops; 2074 bool Changed = false; 2075 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2076 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2077 Changed |= Ops.back() != Node->getOperand(i); 2078 } 2079 if (Changed) 2080 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2081 2082 switch (TLI.getOperationAction(Node->getOpcode(), 2083 Node->getValueType(0))) { 2084 default: assert(0 && "This action is not supported yet!"); 2085 case TargetLowering::Legal: break; 2086 case TargetLowering::Custom: 2087 Tmp1 = TLI.LowerOperation(Result, DAG); 2088 if (Tmp1.Val) { 2089 SDOperand Tmp2, RetVal(0, 0); 2090 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2091 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2092 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2093 if (i == Op.ResNo) 2094 RetVal = Tmp2; 2095 } 2096 assert(RetVal.Val && "Illegal result number"); 2097 return RetVal; 2098 } 2099 break; 2100 } 2101 2102 // Since these produce multiple values, make sure to remember that we 2103 // legalized all of them. 2104 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2105 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2106 return Result.getValue(Op.ResNo); 2107 } 2108 2109 // Binary operators 2110 case ISD::ADD: 2111 case ISD::SUB: 2112 case ISD::MUL: 2113 case ISD::MULHS: 2114 case ISD::MULHU: 2115 case ISD::UDIV: 2116 case ISD::SDIV: 2117 case ISD::AND: 2118 case ISD::OR: 2119 case ISD::XOR: 2120 case ISD::SHL: 2121 case ISD::SRL: 2122 case ISD::SRA: 2123 case ISD::FADD: 2124 case ISD::FSUB: 2125 case ISD::FMUL: 2126 case ISD::FDIV: 2127 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2128 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2129 case Expand: assert(0 && "Not possible"); 2130 case Legal: 2131 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2132 break; 2133 case Promote: 2134 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2135 break; 2136 } 2137 2138 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2139 2140 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2141 default: assert(0 && "BinOp legalize operation not supported"); 2142 case TargetLowering::Legal: break; 2143 case TargetLowering::Custom: 2144 Tmp1 = TLI.LowerOperation(Result, DAG); 2145 if (Tmp1.Val) Result = Tmp1; 2146 break; 2147 case TargetLowering::Expand: { 2148 if (Node->getValueType(0) == MVT::i32) { 2149 switch (Node->getOpcode()) { 2150 default: assert(0 && "Do not know how to expand this integer BinOp!"); 2151 case ISD::UDIV: 2152 case ISD::SDIV: 2153 const char *FnName = Node->getOpcode() == ISD::UDIV 2154 ? "__udivsi3" : "__divsi3"; 2155 SDOperand Dummy; 2156 Result = ExpandLibCall(FnName, Node, Dummy); 2157 }; 2158 break; 2159 } 2160 2161 assert(MVT::isVector(Node->getValueType(0)) && 2162 "Cannot expand this binary operator!"); 2163 // Expand the operation into a bunch of nasty scalar code. 2164 SmallVector<SDOperand, 8> Ops; 2165 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0)); 2166 MVT::ValueType PtrVT = TLI.getPointerTy(); 2167 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0)); 2168 i != e; ++i) { 2169 SDOperand Idx = DAG.getConstant(i, PtrVT); 2170 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx); 2171 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx); 2172 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS)); 2173 } 2174 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), 2175 &Ops[0], Ops.size()); 2176 break; 2177 } 2178 case TargetLowering::Promote: { 2179 switch (Node->getOpcode()) { 2180 default: assert(0 && "Do not know how to promote this BinOp!"); 2181 case ISD::AND: 2182 case ISD::OR: 2183 case ISD::XOR: { 2184 MVT::ValueType OVT = Node->getValueType(0); 2185 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2186 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2187 // Bit convert each of the values to the new type. 2188 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2189 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2190 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2191 // Bit convert the result back the original type. 2192 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2193 break; 2194 } 2195 } 2196 } 2197 } 2198 break; 2199 2200 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2201 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2202 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2203 case Expand: assert(0 && "Not possible"); 2204 case Legal: 2205 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2206 break; 2207 case Promote: 2208 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2209 break; 2210 } 2211 2212 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2213 2214 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2215 default: assert(0 && "Operation not supported"); 2216 case TargetLowering::Custom: 2217 Tmp1 = TLI.LowerOperation(Result, DAG); 2218 if (Tmp1.Val) Result = Tmp1; 2219 break; 2220 case TargetLowering::Legal: break; 2221 case TargetLowering::Expand: 2222 // If this target supports fabs/fneg natively, do this efficiently. 2223 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) && 2224 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) { 2225 // Get the sign bit of the RHS. 2226 MVT::ValueType IVT = 2227 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2228 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2229 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2230 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2231 // Get the absolute value of the result. 2232 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2233 // Select between the nabs and abs value based on the sign bit of 2234 // the input. 2235 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2236 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2237 AbsVal), 2238 AbsVal); 2239 Result = LegalizeOp(Result); 2240 break; 2241 } 2242 2243 // Otherwise, do bitwise ops! 2244 2245 // copysign -> copysignf/copysign libcall. 2246 const char *FnName; 2247 if (Node->getValueType(0) == MVT::f32) { 2248 FnName = "copysignf"; 2249 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type. 2250 Result = DAG.UpdateNodeOperands(Result, Tmp1, 2251 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2)); 2252 } else { 2253 FnName = "copysign"; 2254 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type. 2255 Result = DAG.UpdateNodeOperands(Result, Tmp1, 2256 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2)); 2257 } 2258 SDOperand Dummy; 2259 Result = ExpandLibCall(FnName, Node, Dummy); 2260 break; 2261 } 2262 break; 2263 2264 case ISD::ADDC: 2265 case ISD::SUBC: 2266 Tmp1 = LegalizeOp(Node->getOperand(0)); 2267 Tmp2 = LegalizeOp(Node->getOperand(1)); 2268 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2269 // Since this produces two values, make sure to remember that we legalized 2270 // both of them. 2271 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2272 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2273 return Result; 2274 2275 case ISD::ADDE: 2276 case ISD::SUBE: 2277 Tmp1 = LegalizeOp(Node->getOperand(0)); 2278 Tmp2 = LegalizeOp(Node->getOperand(1)); 2279 Tmp3 = LegalizeOp(Node->getOperand(2)); 2280 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2281 // Since this produces two values, make sure to remember that we legalized 2282 // both of them. 2283 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2284 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2285 return Result; 2286 2287 case ISD::BUILD_PAIR: { 2288 MVT::ValueType PairTy = Node->getValueType(0); 2289 // TODO: handle the case where the Lo and Hi operands are not of legal type 2290 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2291 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2292 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2293 case TargetLowering::Promote: 2294 case TargetLowering::Custom: 2295 assert(0 && "Cannot promote/custom this yet!"); 2296 case TargetLowering::Legal: 2297 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2298 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2299 break; 2300 case TargetLowering::Expand: 2301 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2302 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2303 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2304 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2305 TLI.getShiftAmountTy())); 2306 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2307 break; 2308 } 2309 break; 2310 } 2311 2312 case ISD::UREM: 2313 case ISD::SREM: 2314 case ISD::FREM: 2315 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2316 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2317 2318 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2319 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2320 case TargetLowering::Custom: 2321 isCustom = true; 2322 // FALLTHROUGH 2323 case TargetLowering::Legal: 2324 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2325 if (isCustom) { 2326 Tmp1 = TLI.LowerOperation(Result, DAG); 2327 if (Tmp1.Val) Result = Tmp1; 2328 } 2329 break; 2330 case TargetLowering::Expand: 2331 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2332 if (MVT::isInteger(Node->getValueType(0))) { 2333 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) == 2334 TargetLowering::Legal) { 2335 // X % Y -> X-X/Y*Y 2336 MVT::ValueType VT = Node->getValueType(0); 2337 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 2338 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2339 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2340 } else { 2341 assert(Node->getValueType(0) == MVT::i32 && 2342 "Cannot expand this binary operator!"); 2343 const char *FnName = Node->getOpcode() == ISD::UREM 2344 ? "__umodsi3" : "__modsi3"; 2345 SDOperand Dummy; 2346 Result = ExpandLibCall(FnName, Node, Dummy); 2347 } 2348 } else { 2349 // Floating point mod -> fmod libcall. 2350 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 2351 SDOperand Dummy; 2352 Result = ExpandLibCall(FnName, Node, Dummy); 2353 } 2354 break; 2355 } 2356 break; 2357 case ISD::VAARG: { 2358 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2359 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2360 2361 MVT::ValueType VT = Node->getValueType(0); 2362 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2363 default: assert(0 && "This action is not supported yet!"); 2364 case TargetLowering::Custom: 2365 isCustom = true; 2366 // FALLTHROUGH 2367 case TargetLowering::Legal: 2368 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2369 Result = Result.getValue(0); 2370 Tmp1 = Result.getValue(1); 2371 2372 if (isCustom) { 2373 Tmp2 = TLI.LowerOperation(Result, DAG); 2374 if (Tmp2.Val) { 2375 Result = LegalizeOp(Tmp2); 2376 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 2377 } 2378 } 2379 break; 2380 case TargetLowering::Expand: { 2381 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 2382 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2383 SV->getValue(), SV->getOffset()); 2384 // Increment the pointer, VAList, to the next vaarg 2385 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2386 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2387 TLI.getPointerTy())); 2388 // Store the incremented VAList to the legalized pointer 2389 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, Node->getOperand(2)); 2390 // Load the actual argument out of the pointer VAList 2391 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 2392 Tmp1 = LegalizeOp(Result.getValue(1)); 2393 Result = LegalizeOp(Result); 2394 break; 2395 } 2396 } 2397 // Since VAARG produces two values, make sure to remember that we 2398 // legalized both of them. 2399 AddLegalizedOperand(SDOperand(Node, 0), Result); 2400 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 2401 return Op.ResNo ? Tmp1 : Result; 2402 } 2403 2404 case ISD::VACOPY: 2405 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2406 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 2407 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 2408 2409 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 2410 default: assert(0 && "This action is not supported yet!"); 2411 case TargetLowering::Custom: 2412 isCustom = true; 2413 // FALLTHROUGH 2414 case TargetLowering::Legal: 2415 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 2416 Node->getOperand(3), Node->getOperand(4)); 2417 if (isCustom) { 2418 Tmp1 = TLI.LowerOperation(Result, DAG); 2419 if (Tmp1.Val) Result = Tmp1; 2420 } 2421 break; 2422 case TargetLowering::Expand: 2423 // This defaults to loading a pointer from the input and storing it to the 2424 // output, returning the chain. 2425 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); 2426 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), 2427 SVD->getOffset()); 2428 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, Node->getOperand(4)); 2429 break; 2430 } 2431 break; 2432 2433 case ISD::VAEND: 2434 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2435 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2436 2437 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 2438 default: assert(0 && "This action is not supported yet!"); 2439 case TargetLowering::Custom: 2440 isCustom = true; 2441 // FALLTHROUGH 2442 case TargetLowering::Legal: 2443 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2444 if (isCustom) { 2445 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 2446 if (Tmp1.Val) Result = Tmp1; 2447 } 2448 break; 2449 case TargetLowering::Expand: 2450 Result = Tmp1; // Default to a no-op, return the chain 2451 break; 2452 } 2453 break; 2454 2455 case ISD::VASTART: 2456 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2457 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2458 2459 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2460 2461 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 2462 default: assert(0 && "This action is not supported yet!"); 2463 case TargetLowering::Legal: break; 2464 case TargetLowering::Custom: 2465 Tmp1 = TLI.LowerOperation(Result, DAG); 2466 if (Tmp1.Val) Result = Tmp1; 2467 break; 2468 } 2469 break; 2470 2471 case ISD::ROTL: 2472 case ISD::ROTR: 2473 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2474 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2475 2476 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 2477 "Cannot handle this yet!"); 2478 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2479 break; 2480 2481 case ISD::BSWAP: 2482 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2483 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2484 case TargetLowering::Custom: 2485 assert(0 && "Cannot custom legalize this yet!"); 2486 case TargetLowering::Legal: 2487 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2488 break; 2489 case TargetLowering::Promote: { 2490 MVT::ValueType OVT = Tmp1.getValueType(); 2491 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2492 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT); 2493 2494 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2495 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 2496 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 2497 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 2498 break; 2499 } 2500 case TargetLowering::Expand: 2501 Result = ExpandBSWAP(Tmp1); 2502 break; 2503 } 2504 break; 2505 2506 case ISD::CTPOP: 2507 case ISD::CTTZ: 2508 case ISD::CTLZ: 2509 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2510 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2511 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!"); 2512 case TargetLowering::Legal: 2513 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2514 break; 2515 case TargetLowering::Promote: { 2516 MVT::ValueType OVT = Tmp1.getValueType(); 2517 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2518 2519 // Zero extend the argument. 2520 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2521 // Perform the larger operation, then subtract if needed. 2522 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2523 switch (Node->getOpcode()) { 2524 case ISD::CTPOP: 2525 Result = Tmp1; 2526 break; 2527 case ISD::CTTZ: 2528 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2529 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2530 DAG.getConstant(getSizeInBits(NVT), NVT), 2531 ISD::SETEQ); 2532 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2533 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 2534 break; 2535 case ISD::CTLZ: 2536 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2537 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2538 DAG.getConstant(getSizeInBits(NVT) - 2539 getSizeInBits(OVT), NVT)); 2540 break; 2541 } 2542 break; 2543 } 2544 case TargetLowering::Expand: 2545 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 2546 break; 2547 } 2548 break; 2549 2550 // Unary operators 2551 case ISD::FABS: 2552 case ISD::FNEG: 2553 case ISD::FSQRT: 2554 case ISD::FSIN: 2555 case ISD::FCOS: 2556 Tmp1 = LegalizeOp(Node->getOperand(0)); 2557 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2558 case TargetLowering::Promote: 2559 case TargetLowering::Custom: 2560 isCustom = true; 2561 // FALLTHROUGH 2562 case TargetLowering::Legal: 2563 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2564 if (isCustom) { 2565 Tmp1 = TLI.LowerOperation(Result, DAG); 2566 if (Tmp1.Val) Result = Tmp1; 2567 } 2568 break; 2569 case TargetLowering::Expand: 2570 switch (Node->getOpcode()) { 2571 default: assert(0 && "Unreachable!"); 2572 case ISD::FNEG: 2573 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2574 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2575 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 2576 break; 2577 case ISD::FABS: { 2578 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2579 MVT::ValueType VT = Node->getValueType(0); 2580 Tmp2 = DAG.getConstantFP(0.0, VT); 2581 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2582 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2583 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2584 break; 2585 } 2586 case ISD::FSQRT: 2587 case ISD::FSIN: 2588 case ISD::FCOS: { 2589 MVT::ValueType VT = Node->getValueType(0); 2590 const char *FnName = 0; 2591 switch(Node->getOpcode()) { 2592 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 2593 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 2594 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 2595 default: assert(0 && "Unreachable!"); 2596 } 2597 SDOperand Dummy; 2598 Result = ExpandLibCall(FnName, Node, Dummy); 2599 break; 2600 } 2601 } 2602 break; 2603 } 2604 break; 2605 case ISD::FPOWI: { 2606 // We always lower FPOWI into a libcall. No target support it yet. 2607 const char *FnName = Node->getValueType(0) == MVT::f32 2608 ? "__powisf2" : "__powidf2"; 2609 SDOperand Dummy; 2610 Result = ExpandLibCall(FnName, Node, Dummy); 2611 break; 2612 } 2613 case ISD::BIT_CONVERT: 2614 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 2615 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2616 } else { 2617 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 2618 Node->getOperand(0).getValueType())) { 2619 default: assert(0 && "Unknown operation action!"); 2620 case TargetLowering::Expand: 2621 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2622 break; 2623 case TargetLowering::Legal: 2624 Tmp1 = LegalizeOp(Node->getOperand(0)); 2625 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2626 break; 2627 } 2628 } 2629 break; 2630 case ISD::VBIT_CONVERT: { 2631 assert(Op.getOperand(0).getValueType() == MVT::Vector && 2632 "Can only have VBIT_CONVERT where input or output is MVT::Vector!"); 2633 2634 // The input has to be a vector type, we have to either scalarize it, pack 2635 // it, or convert it based on whether the input vector type is legal. 2636 SDNode *InVal = Node->getOperand(0).Val; 2637 unsigned NumElems = 2638 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 2639 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 2640 2641 // Figure out if there is a Packed type corresponding to this Vector 2642 // type. If so, convert to the packed type. 2643 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2644 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 2645 // Turn this into a bit convert of the packed input. 2646 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2647 PackVectorOp(Node->getOperand(0), TVT)); 2648 break; 2649 } else if (NumElems == 1) { 2650 // Turn this into a bit convert of the scalar input. 2651 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2652 PackVectorOp(Node->getOperand(0), EVT)); 2653 break; 2654 } else { 2655 // FIXME: UNIMP! Store then reload 2656 assert(0 && "Cast from unsupported vector type not implemented yet!"); 2657 } 2658 } 2659 2660 // Conversion operators. The source and destination have different types. 2661 case ISD::SINT_TO_FP: 2662 case ISD::UINT_TO_FP: { 2663 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2664 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2665 case Legal: 2666 switch (TLI.getOperationAction(Node->getOpcode(), 2667 Node->getOperand(0).getValueType())) { 2668 default: assert(0 && "Unknown operation action!"); 2669 case TargetLowering::Custom: 2670 isCustom = true; 2671 // FALLTHROUGH 2672 case TargetLowering::Legal: 2673 Tmp1 = LegalizeOp(Node->getOperand(0)); 2674 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2675 if (isCustom) { 2676 Tmp1 = TLI.LowerOperation(Result, DAG); 2677 if (Tmp1.Val) Result = Tmp1; 2678 } 2679 break; 2680 case TargetLowering::Expand: 2681 Result = ExpandLegalINT_TO_FP(isSigned, 2682 LegalizeOp(Node->getOperand(0)), 2683 Node->getValueType(0)); 2684 break; 2685 case TargetLowering::Promote: 2686 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2687 Node->getValueType(0), 2688 isSigned); 2689 break; 2690 } 2691 break; 2692 case Expand: 2693 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2694 Node->getValueType(0), Node->getOperand(0)); 2695 break; 2696 case Promote: 2697 Tmp1 = PromoteOp(Node->getOperand(0)); 2698 if (isSigned) { 2699 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 2700 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 2701 } else { 2702 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 2703 Node->getOperand(0).getValueType()); 2704 } 2705 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2706 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 2707 break; 2708 } 2709 break; 2710 } 2711 case ISD::TRUNCATE: 2712 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2713 case Legal: 2714 Tmp1 = LegalizeOp(Node->getOperand(0)); 2715 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2716 break; 2717 case Expand: 2718 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2719 2720 // Since the result is legal, we should just be able to truncate the low 2721 // part of the source. 2722 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2723 break; 2724 case Promote: 2725 Result = PromoteOp(Node->getOperand(0)); 2726 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2727 break; 2728 } 2729 break; 2730 2731 case ISD::FP_TO_SINT: 2732 case ISD::FP_TO_UINT: 2733 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2734 case Legal: 2735 Tmp1 = LegalizeOp(Node->getOperand(0)); 2736 2737 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2738 default: assert(0 && "Unknown operation action!"); 2739 case TargetLowering::Custom: 2740 isCustom = true; 2741 // FALLTHROUGH 2742 case TargetLowering::Legal: 2743 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2744 if (isCustom) { 2745 Tmp1 = TLI.LowerOperation(Result, DAG); 2746 if (Tmp1.Val) Result = Tmp1; 2747 } 2748 break; 2749 case TargetLowering::Promote: 2750 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2751 Node->getOpcode() == ISD::FP_TO_SINT); 2752 break; 2753 case TargetLowering::Expand: 2754 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2755 SDOperand True, False; 2756 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2757 MVT::ValueType NVT = Node->getValueType(0); 2758 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2759 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2760 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2761 Node->getOperand(0), Tmp2, ISD::SETLT); 2762 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2763 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2764 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2765 Tmp2)); 2766 False = DAG.getNode(ISD::XOR, NVT, False, 2767 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2768 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 2769 break; 2770 } else { 2771 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2772 } 2773 break; 2774 } 2775 break; 2776 case Expand: 2777 assert(0 && "Shouldn't need to expand other operators here!"); 2778 case Promote: 2779 Tmp1 = PromoteOp(Node->getOperand(0)); 2780 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 2781 Result = LegalizeOp(Result); 2782 break; 2783 } 2784 break; 2785 2786 case ISD::ANY_EXTEND: 2787 case ISD::ZERO_EXTEND: 2788 case ISD::SIGN_EXTEND: 2789 case ISD::FP_EXTEND: 2790 case ISD::FP_ROUND: 2791 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2792 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 2793 case Legal: 2794 Tmp1 = LegalizeOp(Node->getOperand(0)); 2795 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2796 break; 2797 case Promote: 2798 switch (Node->getOpcode()) { 2799 case ISD::ANY_EXTEND: 2800 Tmp1 = PromoteOp(Node->getOperand(0)); 2801 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 2802 break; 2803 case ISD::ZERO_EXTEND: 2804 Result = PromoteOp(Node->getOperand(0)); 2805 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2806 Result = DAG.getZeroExtendInReg(Result, 2807 Node->getOperand(0).getValueType()); 2808 break; 2809 case ISD::SIGN_EXTEND: 2810 Result = PromoteOp(Node->getOperand(0)); 2811 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2812 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2813 Result, 2814 DAG.getValueType(Node->getOperand(0).getValueType())); 2815 break; 2816 case ISD::FP_EXTEND: 2817 Result = PromoteOp(Node->getOperand(0)); 2818 if (Result.getValueType() != Op.getValueType()) 2819 // Dynamically dead while we have only 2 FP types. 2820 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2821 break; 2822 case ISD::FP_ROUND: 2823 Result = PromoteOp(Node->getOperand(0)); 2824 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2825 break; 2826 } 2827 } 2828 break; 2829 case ISD::FP_ROUND_INREG: 2830 case ISD::SIGN_EXTEND_INREG: { 2831 Tmp1 = LegalizeOp(Node->getOperand(0)); 2832 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2833 2834 // If this operation is not supported, convert it to a shl/shr or load/store 2835 // pair. 2836 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2837 default: assert(0 && "This action not supported for this op yet!"); 2838 case TargetLowering::Legal: 2839 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2840 break; 2841 case TargetLowering::Expand: 2842 // If this is an integer extend and shifts are supported, do that. 2843 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2844 // NOTE: we could fall back on load/store here too for targets without 2845 // SAR. However, it is doubtful that any exist. 2846 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2847 MVT::getSizeInBits(ExtraVT); 2848 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2849 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2850 Node->getOperand(0), ShiftCst); 2851 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2852 Result, ShiftCst); 2853 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2854 // The only way we can lower this is to turn it into a STORETRUNC, 2855 // EXTLOAD pair, targetting a temporary location (a stack slot). 2856 2857 // NOTE: there is a choice here between constantly creating new stack 2858 // slots and always reusing the same one. We currently always create 2859 // new ones, as reuse may inhibit scheduling. 2860 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2861 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty); 2862 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty); 2863 MachineFunction &MF = DAG.getMachineFunction(); 2864 int SSFI = 2865 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2866 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2867 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2868 Node->getOperand(0), StackSlot, 2869 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2870 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2871 Result, StackSlot, NULL, 0, ExtraVT); 2872 } else { 2873 assert(0 && "Unknown op"); 2874 } 2875 break; 2876 } 2877 break; 2878 } 2879 } 2880 2881 assert(Result.getValueType() == Op.getValueType() && 2882 "Bad legalization!"); 2883 2884 // Make sure that the generated code is itself legal. 2885 if (Result != Op) 2886 Result = LegalizeOp(Result); 2887 2888 // Note that LegalizeOp may be reentered even from single-use nodes, which 2889 // means that we always must cache transformed nodes. 2890 AddLegalizedOperand(Op, Result); 2891 return Result; 2892} 2893 2894/// PromoteOp - Given an operation that produces a value in an invalid type, 2895/// promote it to compute the value into a larger type. The produced value will 2896/// have the correct bits for the low portion of the register, but no guarantee 2897/// is made about the top bits: it may be zero, sign-extended, or garbage. 2898SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2899 MVT::ValueType VT = Op.getValueType(); 2900 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2901 assert(getTypeAction(VT) == Promote && 2902 "Caller should expand or legalize operands that are not promotable!"); 2903 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2904 "Cannot promote to smaller type!"); 2905 2906 SDOperand Tmp1, Tmp2, Tmp3; 2907 SDOperand Result; 2908 SDNode *Node = Op.Val; 2909 2910 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2911 if (I != PromotedNodes.end()) return I->second; 2912 2913 switch (Node->getOpcode()) { 2914 case ISD::CopyFromReg: 2915 assert(0 && "CopyFromReg must be legal!"); 2916 default: 2917#ifndef NDEBUG 2918 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2919#endif 2920 assert(0 && "Do not know how to promote this operator!"); 2921 abort(); 2922 case ISD::UNDEF: 2923 Result = DAG.getNode(ISD::UNDEF, NVT); 2924 break; 2925 case ISD::Constant: 2926 if (VT != MVT::i1) 2927 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2928 else 2929 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2930 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2931 break; 2932 case ISD::ConstantFP: 2933 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2934 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2935 break; 2936 2937 case ISD::SETCC: 2938 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2939 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2940 Node->getOperand(1), Node->getOperand(2)); 2941 break; 2942 2943 case ISD::TRUNCATE: 2944 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2945 case Legal: 2946 Result = LegalizeOp(Node->getOperand(0)); 2947 assert(Result.getValueType() >= NVT && 2948 "This truncation doesn't make sense!"); 2949 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2950 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2951 break; 2952 case Promote: 2953 // The truncation is not required, because we don't guarantee anything 2954 // about high bits anyway. 2955 Result = PromoteOp(Node->getOperand(0)); 2956 break; 2957 case Expand: 2958 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2959 // Truncate the low part of the expanded value to the result type 2960 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2961 } 2962 break; 2963 case ISD::SIGN_EXTEND: 2964 case ISD::ZERO_EXTEND: 2965 case ISD::ANY_EXTEND: 2966 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2967 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2968 case Legal: 2969 // Input is legal? Just do extend all the way to the larger type. 2970 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 2971 break; 2972 case Promote: 2973 // Promote the reg if it's smaller. 2974 Result = PromoteOp(Node->getOperand(0)); 2975 // The high bits are not guaranteed to be anything. Insert an extend. 2976 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2977 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2978 DAG.getValueType(Node->getOperand(0).getValueType())); 2979 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2980 Result = DAG.getZeroExtendInReg(Result, 2981 Node->getOperand(0).getValueType()); 2982 break; 2983 } 2984 break; 2985 case ISD::BIT_CONVERT: 2986 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2987 Result = PromoteOp(Result); 2988 break; 2989 2990 case ISD::FP_EXTEND: 2991 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2992 case ISD::FP_ROUND: 2993 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2994 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2995 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2996 case Legal: 2997 // Input is legal? Do an FP_ROUND_INREG. 2998 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 2999 DAG.getValueType(VT)); 3000 break; 3001 } 3002 break; 3003 3004 case ISD::SINT_TO_FP: 3005 case ISD::UINT_TO_FP: 3006 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3007 case Legal: 3008 // No extra round required here. 3009 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3010 break; 3011 3012 case Promote: 3013 Result = PromoteOp(Node->getOperand(0)); 3014 if (Node->getOpcode() == ISD::SINT_TO_FP) 3015 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3016 Result, 3017 DAG.getValueType(Node->getOperand(0).getValueType())); 3018 else 3019 Result = DAG.getZeroExtendInReg(Result, 3020 Node->getOperand(0).getValueType()); 3021 // No extra round required here. 3022 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3023 break; 3024 case Expand: 3025 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3026 Node->getOperand(0)); 3027 // Round if we cannot tolerate excess precision. 3028 if (NoExcessFPPrecision) 3029 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3030 DAG.getValueType(VT)); 3031 break; 3032 } 3033 break; 3034 3035 case ISD::SIGN_EXTEND_INREG: 3036 Result = PromoteOp(Node->getOperand(0)); 3037 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3038 Node->getOperand(1)); 3039 break; 3040 case ISD::FP_TO_SINT: 3041 case ISD::FP_TO_UINT: 3042 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3043 case Legal: 3044 Tmp1 = Node->getOperand(0); 3045 break; 3046 case Promote: 3047 // The input result is prerounded, so we don't have to do anything 3048 // special. 3049 Tmp1 = PromoteOp(Node->getOperand(0)); 3050 break; 3051 case Expand: 3052 assert(0 && "not implemented"); 3053 } 3054 // If we're promoting a UINT to a larger size, check to see if the new node 3055 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3056 // we can use that instead. This allows us to generate better code for 3057 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3058 // legal, such as PowerPC. 3059 if (Node->getOpcode() == ISD::FP_TO_UINT && 3060 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3061 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3062 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3063 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3064 } else { 3065 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3066 } 3067 break; 3068 3069 case ISD::FABS: 3070 case ISD::FNEG: 3071 Tmp1 = PromoteOp(Node->getOperand(0)); 3072 assert(Tmp1.getValueType() == NVT); 3073 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3074 // NOTE: we do not have to do any extra rounding here for 3075 // NoExcessFPPrecision, because we know the input will have the appropriate 3076 // precision, and these operations don't modify precision at all. 3077 break; 3078 3079 case ISD::FSQRT: 3080 case ISD::FSIN: 3081 case ISD::FCOS: 3082 Tmp1 = PromoteOp(Node->getOperand(0)); 3083 assert(Tmp1.getValueType() == NVT); 3084 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3085 if (NoExcessFPPrecision) 3086 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3087 DAG.getValueType(VT)); 3088 break; 3089 3090 case ISD::AND: 3091 case ISD::OR: 3092 case ISD::XOR: 3093 case ISD::ADD: 3094 case ISD::SUB: 3095 case ISD::MUL: 3096 // The input may have strange things in the top bits of the registers, but 3097 // these operations don't care. They may have weird bits going out, but 3098 // that too is okay if they are integer operations. 3099 Tmp1 = PromoteOp(Node->getOperand(0)); 3100 Tmp2 = PromoteOp(Node->getOperand(1)); 3101 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3102 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3103 break; 3104 case ISD::FADD: 3105 case ISD::FSUB: 3106 case ISD::FMUL: 3107 Tmp1 = PromoteOp(Node->getOperand(0)); 3108 Tmp2 = PromoteOp(Node->getOperand(1)); 3109 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3110 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3111 3112 // Floating point operations will give excess precision that we may not be 3113 // able to tolerate. If we DO allow excess precision, just leave it, 3114 // otherwise excise it. 3115 // FIXME: Why would we need to round FP ops more than integer ones? 3116 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3117 if (NoExcessFPPrecision) 3118 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3119 DAG.getValueType(VT)); 3120 break; 3121 3122 case ISD::SDIV: 3123 case ISD::SREM: 3124 // These operators require that their input be sign extended. 3125 Tmp1 = PromoteOp(Node->getOperand(0)); 3126 Tmp2 = PromoteOp(Node->getOperand(1)); 3127 if (MVT::isInteger(NVT)) { 3128 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3129 DAG.getValueType(VT)); 3130 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3131 DAG.getValueType(VT)); 3132 } 3133 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3134 3135 // Perform FP_ROUND: this is probably overly pessimistic. 3136 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 3137 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3138 DAG.getValueType(VT)); 3139 break; 3140 case ISD::FDIV: 3141 case ISD::FREM: 3142 case ISD::FCOPYSIGN: 3143 // These operators require that their input be fp extended. 3144 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3145 case Legal: 3146 Tmp1 = LegalizeOp(Node->getOperand(0)); 3147 break; 3148 case Promote: 3149 Tmp1 = PromoteOp(Node->getOperand(0)); 3150 break; 3151 case Expand: 3152 assert(0 && "not implemented"); 3153 } 3154 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3155 case Legal: 3156 Tmp2 = LegalizeOp(Node->getOperand(1)); 3157 break; 3158 case Promote: 3159 Tmp2 = PromoteOp(Node->getOperand(1)); 3160 break; 3161 case Expand: 3162 assert(0 && "not implemented"); 3163 } 3164 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3165 3166 // Perform FP_ROUND: this is probably overly pessimistic. 3167 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 3168 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3169 DAG.getValueType(VT)); 3170 break; 3171 3172 case ISD::UDIV: 3173 case ISD::UREM: 3174 // These operators require that their input be zero extended. 3175 Tmp1 = PromoteOp(Node->getOperand(0)); 3176 Tmp2 = PromoteOp(Node->getOperand(1)); 3177 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 3178 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3179 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3180 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3181 break; 3182 3183 case ISD::SHL: 3184 Tmp1 = PromoteOp(Node->getOperand(0)); 3185 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 3186 break; 3187 case ISD::SRA: 3188 // The input value must be properly sign extended. 3189 Tmp1 = PromoteOp(Node->getOperand(0)); 3190 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3191 DAG.getValueType(VT)); 3192 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 3193 break; 3194 case ISD::SRL: 3195 // The input value must be properly zero extended. 3196 Tmp1 = PromoteOp(Node->getOperand(0)); 3197 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3198 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 3199 break; 3200 3201 case ISD::VAARG: 3202 Tmp1 = Node->getOperand(0); // Get the chain. 3203 Tmp2 = Node->getOperand(1); // Get the pointer. 3204 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 3205 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 3206 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 3207 } else { 3208 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 3209 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3210 SV->getValue(), SV->getOffset()); 3211 // Increment the pointer, VAList, to the next vaarg 3212 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3213 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3214 TLI.getPointerTy())); 3215 // Store the incremented VAList to the legalized pointer 3216 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, Node->getOperand(2)); 3217 // Load the actual argument out of the pointer VAList 3218 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 3219 } 3220 // Remember that we legalized the chain. 3221 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3222 break; 3223 3224 case ISD::LOAD: { 3225 LoadSDNode *LD = cast<LoadSDNode>(Node); 3226 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 3227 ? ISD::EXTLOAD : LD->getExtensionType(); 3228 Result = DAG.getExtLoad(ExtType, NVT, 3229 LD->getChain(), LD->getBasePtr(), 3230 LD->getSrcValue(), LD->getSrcValueOffset(), 3231 LD->getLoadedVT()); 3232 // Remember that we legalized the chain. 3233 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3234 break; 3235 } 3236 case ISD::SELECT: 3237 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 3238 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 3239 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 3240 break; 3241 case ISD::SELECT_CC: 3242 Tmp2 = PromoteOp(Node->getOperand(2)); // True 3243 Tmp3 = PromoteOp(Node->getOperand(3)); // False 3244 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3245 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 3246 break; 3247 case ISD::BSWAP: 3248 Tmp1 = Node->getOperand(0); 3249 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3250 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3251 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3252 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT), 3253 TLI.getShiftAmountTy())); 3254 break; 3255 case ISD::CTPOP: 3256 case ISD::CTTZ: 3257 case ISD::CTLZ: 3258 // Zero extend the argument 3259 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 3260 // Perform the larger operation, then subtract if needed. 3261 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3262 switch(Node->getOpcode()) { 3263 case ISD::CTPOP: 3264 Result = Tmp1; 3265 break; 3266 case ISD::CTTZ: 3267 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3268 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3269 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 3270 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3271 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1); 3272 break; 3273 case ISD::CTLZ: 3274 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3275 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3276 DAG.getConstant(getSizeInBits(NVT) - 3277 getSizeInBits(VT), NVT)); 3278 break; 3279 } 3280 break; 3281 case ISD::VEXTRACT_VECTOR_ELT: 3282 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op)); 3283 break; 3284 case ISD::EXTRACT_VECTOR_ELT: 3285 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 3286 break; 3287 } 3288 3289 assert(Result.Val && "Didn't set a result!"); 3290 3291 // Make sure the result is itself legal. 3292 Result = LegalizeOp(Result); 3293 3294 // Remember that we promoted this! 3295 AddPromotedOperand(Op, Result); 3296 return Result; 3297} 3298 3299/// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a 3300/// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based 3301/// on the vector type. The return type of this matches the element type of the 3302/// vector, which may not be legal for the target. 3303SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) { 3304 // We know that operand #0 is the Vec vector. If the index is a constant 3305 // or if the invec is a supported hardware type, we can use it. Otherwise, 3306 // lower to a store then an indexed load. 3307 SDOperand Vec = Op.getOperand(0); 3308 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 3309 3310 SDNode *InVal = Vec.Val; 3311 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 3312 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 3313 3314 // Figure out if there is a Packed type corresponding to this Vector 3315 // type. If so, convert to the packed type. 3316 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3317 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 3318 // Turn this into a packed extract_vector_elt operation. 3319 Vec = PackVectorOp(Vec, TVT); 3320 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx); 3321 } else if (NumElems == 1) { 3322 // This must be an access of the only element. Return it. 3323 return PackVectorOp(Vec, EVT); 3324 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 3325 SDOperand Lo, Hi; 3326 SplitVectorOp(Vec, Lo, Hi); 3327 if (CIdx->getValue() < NumElems/2) { 3328 Vec = Lo; 3329 } else { 3330 Vec = Hi; 3331 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 3332 } 3333 3334 // It's now an extract from the appropriate high or low part. Recurse. 3335 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3336 return LowerVEXTRACT_VECTOR_ELT(Op); 3337 } else { 3338 // Variable index case for extract element. 3339 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!! 3340 assert(0 && "unimp!"); 3341 return SDOperand(); 3342 } 3343} 3344 3345/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 3346/// memory traffic. 3347SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 3348 SDOperand Vector = Op.getOperand(0); 3349 SDOperand Idx = Op.getOperand(1); 3350 3351 // If the target doesn't support this, store the value to a temporary 3352 // stack slot, then LOAD the scalar element back out. 3353 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType()); 3354 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), 3355 Vector, StackPtr, DAG.getSrcValue(NULL)); 3356 3357 // Add the offset to the index. 3358 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 3359 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 3360 DAG.getConstant(EltSize, Idx.getValueType())); 3361 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 3362 3363 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 3364} 3365 3366 3367/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 3368/// with condition CC on the current target. This usually involves legalizing 3369/// or promoting the arguments. In the case where LHS and RHS must be expanded, 3370/// there may be no choice but to create a new SetCC node to represent the 3371/// legalized value of setcc lhs, rhs. In this case, the value is returned in 3372/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 3373void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 3374 SDOperand &RHS, 3375 SDOperand &CC) { 3376 SDOperand Tmp1, Tmp2, Result; 3377 3378 switch (getTypeAction(LHS.getValueType())) { 3379 case Legal: 3380 Tmp1 = LegalizeOp(LHS); // LHS 3381 Tmp2 = LegalizeOp(RHS); // RHS 3382 break; 3383 case Promote: 3384 Tmp1 = PromoteOp(LHS); // LHS 3385 Tmp2 = PromoteOp(RHS); // RHS 3386 3387 // If this is an FP compare, the operands have already been extended. 3388 if (MVT::isInteger(LHS.getValueType())) { 3389 MVT::ValueType VT = LHS.getValueType(); 3390 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3391 3392 // Otherwise, we have to insert explicit sign or zero extends. Note 3393 // that we could insert sign extends for ALL conditions, but zero extend 3394 // is cheaper on many machines (an AND instead of two shifts), so prefer 3395 // it. 3396 switch (cast<CondCodeSDNode>(CC)->get()) { 3397 default: assert(0 && "Unknown integer comparison!"); 3398 case ISD::SETEQ: 3399 case ISD::SETNE: 3400 case ISD::SETUGE: 3401 case ISD::SETUGT: 3402 case ISD::SETULE: 3403 case ISD::SETULT: 3404 // ALL of these operations will work if we either sign or zero extend 3405 // the operands (including the unsigned comparisons!). Zero extend is 3406 // usually a simpler/cheaper operation, so prefer it. 3407 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3408 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3409 break; 3410 case ISD::SETGE: 3411 case ISD::SETGT: 3412 case ISD::SETLT: 3413 case ISD::SETLE: 3414 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3415 DAG.getValueType(VT)); 3416 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3417 DAG.getValueType(VT)); 3418 break; 3419 } 3420 } 3421 break; 3422 case Expand: 3423 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 3424 ExpandOp(LHS, LHSLo, LHSHi); 3425 ExpandOp(RHS, RHSLo, RHSHi); 3426 switch (cast<CondCodeSDNode>(CC)->get()) { 3427 case ISD::SETEQ: 3428 case ISD::SETNE: 3429 if (RHSLo == RHSHi) 3430 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 3431 if (RHSCST->isAllOnesValue()) { 3432 // Comparison to -1. 3433 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 3434 Tmp2 = RHSLo; 3435 break; 3436 } 3437 3438 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 3439 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 3440 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 3441 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3442 break; 3443 default: 3444 // If this is a comparison of the sign bit, just look at the top part. 3445 // X > -1, x < 0 3446 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 3447 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 3448 CST->getValue() == 0) || // X < 0 3449 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 3450 CST->isAllOnesValue())) { // X > -1 3451 Tmp1 = LHSHi; 3452 Tmp2 = RHSHi; 3453 break; 3454 } 3455 3456 // FIXME: This generated code sucks. 3457 ISD::CondCode LowCC; 3458 switch (cast<CondCodeSDNode>(CC)->get()) { 3459 default: assert(0 && "Unknown integer setcc!"); 3460 case ISD::SETLT: 3461 case ISD::SETULT: LowCC = ISD::SETULT; break; 3462 case ISD::SETGT: 3463 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 3464 case ISD::SETLE: 3465 case ISD::SETULE: LowCC = ISD::SETULE; break; 3466 case ISD::SETGE: 3467 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 3468 } 3469 3470 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 3471 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 3472 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 3473 3474 // NOTE: on targets without efficient SELECT of bools, we can always use 3475 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 3476 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 3477 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC); 3478 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 3479 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 3480 Result, Tmp1, Tmp2)); 3481 Tmp1 = Result; 3482 Tmp2 = SDOperand(); 3483 } 3484 } 3485 LHS = Tmp1; 3486 RHS = Tmp2; 3487} 3488 3489/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 3490/// The resultant code need not be legal. Note that SrcOp is the input operand 3491/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 3492SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 3493 SDOperand SrcOp) { 3494 // Create the stack frame object. 3495 SDOperand FIPtr = CreateStackTemporary(DestVT); 3496 3497 // Emit a store to the stack slot. 3498 SDOperand Store = DAG.getStore(DAG.getEntryNode(), 3499 SrcOp, FIPtr, DAG.getSrcValue(NULL)); 3500 // Result is a load from the stack slot. 3501 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 3502} 3503 3504SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 3505 // Create a vector sized/aligned stack slot, store the value to element #0, 3506 // then load the whole vector back out. 3507 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); 3508 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 3509 DAG.getSrcValue(NULL)); 3510 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); 3511} 3512 3513 3514/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 3515/// support the operation, but do support the resultant packed vector type. 3516SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 3517 3518 // If the only non-undef value is the low element, turn this into a 3519 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 3520 unsigned NumElems = Node->getNumOperands(); 3521 bool isOnlyLowElement = true; 3522 SDOperand SplatValue = Node->getOperand(0); 3523 std::map<SDOperand, std::vector<unsigned> > Values; 3524 Values[SplatValue].push_back(0); 3525 bool isConstant = true; 3526 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 3527 SplatValue.getOpcode() != ISD::UNDEF) 3528 isConstant = false; 3529 3530 for (unsigned i = 1; i < NumElems; ++i) { 3531 SDOperand V = Node->getOperand(i); 3532 Values[V].push_back(i); 3533 if (V.getOpcode() != ISD::UNDEF) 3534 isOnlyLowElement = false; 3535 if (SplatValue != V) 3536 SplatValue = SDOperand(0,0); 3537 3538 // If this isn't a constant element or an undef, we can't use a constant 3539 // pool load. 3540 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 3541 V.getOpcode() != ISD::UNDEF) 3542 isConstant = false; 3543 } 3544 3545 if (isOnlyLowElement) { 3546 // If the low element is an undef too, then this whole things is an undef. 3547 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 3548 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 3549 // Otherwise, turn this into a scalar_to_vector node. 3550 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 3551 Node->getOperand(0)); 3552 } 3553 3554 // If all elements are constants, create a load from the constant pool. 3555 if (isConstant) { 3556 MVT::ValueType VT = Node->getValueType(0); 3557 const Type *OpNTy = 3558 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 3559 std::vector<Constant*> CV; 3560 for (unsigned i = 0, e = NumElems; i != e; ++i) { 3561 if (ConstantFPSDNode *V = 3562 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 3563 CV.push_back(ConstantFP::get(OpNTy, V->getValue())); 3564 } else if (ConstantSDNode *V = 3565 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 3566 CV.push_back(ConstantUInt::get(OpNTy, V->getValue())); 3567 } else { 3568 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 3569 CV.push_back(UndefValue::get(OpNTy)); 3570 } 3571 } 3572 Constant *CP = ConstantPacked::get(CV); 3573 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 3574 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 3575 } 3576 3577 if (SplatValue.Val) { // Splat of one value? 3578 // Build the shuffle constant vector: <0, 0, 0, 0> 3579 MVT::ValueType MaskVT = 3580 MVT::getIntVectorWithNumElements(NumElems); 3581 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT)); 3582 std::vector<SDOperand> ZeroVec(NumElems, Zero); 3583 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3584 &ZeroVec[0], ZeroVec.size()); 3585 3586 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 3587 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 3588 // Get the splatted value into the low element of a vector register. 3589 SDOperand LowValVec = 3590 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 3591 3592 // Return shuffle(LowValVec, undef, <0,0,0,0>) 3593 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 3594 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 3595 SplatMask); 3596 } 3597 } 3598 3599 // If there are only two unique elements, we may be able to turn this into a 3600 // vector shuffle. 3601 if (Values.size() == 2) { 3602 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 3603 MVT::ValueType MaskVT = 3604 MVT::getIntVectorWithNumElements(NumElems); 3605 std::vector<SDOperand> MaskVec(NumElems); 3606 unsigned i = 0; 3607 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 3608 E = Values.end(); I != E; ++I) { 3609 for (std::vector<unsigned>::iterator II = I->second.begin(), 3610 EE = I->second.end(); II != EE; ++II) 3611 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT)); 3612 i += NumElems; 3613 } 3614 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3615 &MaskVec[0], MaskVec.size()); 3616 3617 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 3618 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 3619 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 3620 SmallVector<SDOperand, 8> Ops; 3621 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 3622 E = Values.end(); I != E; ++I) { 3623 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 3624 I->first); 3625 Ops.push_back(Op); 3626 } 3627 Ops.push_back(ShuffleMask); 3628 3629 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 3630 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 3631 &Ops[0], Ops.size()); 3632 } 3633 } 3634 3635 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 3636 // aligned object on the stack, store each element into it, then load 3637 // the result as a vector. 3638 MVT::ValueType VT = Node->getValueType(0); 3639 // Create the stack frame object. 3640 SDOperand FIPtr = CreateStackTemporary(VT); 3641 3642 // Emit a store of each element to the stack slot. 3643 SmallVector<SDOperand, 8> Stores; 3644 unsigned TypeByteSize = 3645 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 3646 unsigned VectorSize = MVT::getSizeInBits(VT)/8; 3647 // Store (in the right endianness) the elements to memory. 3648 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3649 // Ignore undef elements. 3650 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3651 3652 unsigned Offset = TypeByteSize*i; 3653 3654 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 3655 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 3656 3657 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 3658 DAG.getSrcValue(NULL))); 3659 } 3660 3661 SDOperand StoreChain; 3662 if (!Stores.empty()) // Not all undef elements? 3663 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3664 &Stores[0], Stores.size()); 3665 else 3666 StoreChain = DAG.getEntryNode(); 3667 3668 // Result is a load from the stack slot. 3669 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 3670} 3671 3672/// CreateStackTemporary - Create a stack temporary, suitable for holding the 3673/// specified value type. 3674SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) { 3675 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 3676 unsigned ByteSize = MVT::getSizeInBits(VT)/8; 3677 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize); 3678 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 3679} 3680 3681void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 3682 SDOperand Op, SDOperand Amt, 3683 SDOperand &Lo, SDOperand &Hi) { 3684 // Expand the subcomponents. 3685 SDOperand LHSL, LHSH; 3686 ExpandOp(Op, LHSL, LHSH); 3687 3688 SDOperand Ops[] = { LHSL, LHSH, Amt }; 3689 MVT::ValueType VT = LHSL.getValueType(); 3690 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 3691 Hi = Lo.getValue(1); 3692} 3693 3694 3695/// ExpandShift - Try to find a clever way to expand this shift operation out to 3696/// smaller elements. If we can't find a way that is more efficient than a 3697/// libcall on this target, return false. Otherwise, return true with the 3698/// low-parts expanded into Lo and Hi. 3699bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 3700 SDOperand &Lo, SDOperand &Hi) { 3701 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 3702 "This is not a shift!"); 3703 3704 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 3705 SDOperand ShAmt = LegalizeOp(Amt); 3706 MVT::ValueType ShTy = ShAmt.getValueType(); 3707 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 3708 unsigned NVTBits = MVT::getSizeInBits(NVT); 3709 3710 // Handle the case when Amt is an immediate. Other cases are currently broken 3711 // and are disabled. 3712 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 3713 unsigned Cst = CN->getValue(); 3714 // Expand the incoming operand to be shifted, so that we have its parts 3715 SDOperand InL, InH; 3716 ExpandOp(Op, InL, InH); 3717 switch(Opc) { 3718 case ISD::SHL: 3719 if (Cst > VTBits) { 3720 Lo = DAG.getConstant(0, NVT); 3721 Hi = DAG.getConstant(0, NVT); 3722 } else if (Cst > NVTBits) { 3723 Lo = DAG.getConstant(0, NVT); 3724 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 3725 } else if (Cst == NVTBits) { 3726 Lo = DAG.getConstant(0, NVT); 3727 Hi = InL; 3728 } else { 3729 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 3730 Hi = DAG.getNode(ISD::OR, NVT, 3731 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 3732 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 3733 } 3734 return true; 3735 case ISD::SRL: 3736 if (Cst > VTBits) { 3737 Lo = DAG.getConstant(0, NVT); 3738 Hi = DAG.getConstant(0, NVT); 3739 } else if (Cst > NVTBits) { 3740 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 3741 Hi = DAG.getConstant(0, NVT); 3742 } else if (Cst == NVTBits) { 3743 Lo = InH; 3744 Hi = DAG.getConstant(0, NVT); 3745 } else { 3746 Lo = DAG.getNode(ISD::OR, NVT, 3747 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3748 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3749 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 3750 } 3751 return true; 3752 case ISD::SRA: 3753 if (Cst > VTBits) { 3754 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 3755 DAG.getConstant(NVTBits-1, ShTy)); 3756 } else if (Cst > NVTBits) { 3757 Lo = DAG.getNode(ISD::SRA, NVT, InH, 3758 DAG.getConstant(Cst-NVTBits, ShTy)); 3759 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3760 DAG.getConstant(NVTBits-1, ShTy)); 3761 } else if (Cst == NVTBits) { 3762 Lo = InH; 3763 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3764 DAG.getConstant(NVTBits-1, ShTy)); 3765 } else { 3766 Lo = DAG.getNode(ISD::OR, NVT, 3767 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3768 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3769 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 3770 } 3771 return true; 3772 } 3773 } 3774 3775 // Okay, the shift amount isn't constant. However, if we can tell that it is 3776 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 3777 uint64_t Mask = NVTBits, KnownZero, KnownOne; 3778 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 3779 3780 // If we know that the high bit of the shift amount is one, then we can do 3781 // this as a couple of simple shifts. 3782 if (KnownOne & Mask) { 3783 // Mask out the high bit, which we know is set. 3784 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 3785 DAG.getConstant(NVTBits-1, Amt.getValueType())); 3786 3787 // Expand the incoming operand to be shifted, so that we have its parts 3788 SDOperand InL, InH; 3789 ExpandOp(Op, InL, InH); 3790 switch(Opc) { 3791 case ISD::SHL: 3792 Lo = DAG.getConstant(0, NVT); // Low part is zero. 3793 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 3794 return true; 3795 case ISD::SRL: 3796 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 3797 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 3798 return true; 3799 case ISD::SRA: 3800 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 3801 DAG.getConstant(NVTBits-1, Amt.getValueType())); 3802 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 3803 return true; 3804 } 3805 } 3806 3807 // If we know that the high bit of the shift amount is zero, then we can do 3808 // this as a couple of simple shifts. 3809 if (KnownZero & Mask) { 3810 // Compute 32-amt. 3811 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 3812 DAG.getConstant(NVTBits, Amt.getValueType()), 3813 Amt); 3814 3815 // Expand the incoming operand to be shifted, so that we have its parts 3816 SDOperand InL, InH; 3817 ExpandOp(Op, InL, InH); 3818 switch(Opc) { 3819 case ISD::SHL: 3820 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 3821 Hi = DAG.getNode(ISD::OR, NVT, 3822 DAG.getNode(ISD::SHL, NVT, InH, Amt), 3823 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 3824 return true; 3825 case ISD::SRL: 3826 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 3827 Lo = DAG.getNode(ISD::OR, NVT, 3828 DAG.getNode(ISD::SRL, NVT, InL, Amt), 3829 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 3830 return true; 3831 case ISD::SRA: 3832 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 3833 Lo = DAG.getNode(ISD::OR, NVT, 3834 DAG.getNode(ISD::SRL, NVT, InL, Amt), 3835 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 3836 return true; 3837 } 3838 } 3839 3840 return false; 3841} 3842 3843 3844// ExpandLibCall - Expand a node into a call to a libcall. If the result value 3845// does not fit into a register, return the lo part and set the hi part to the 3846// by-reg argument. If it does fit into a single register, return the result 3847// and leave the Hi part unset. 3848SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 3849 SDOperand &Hi) { 3850 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 3851 // The input chain to this libcall is the entry node of the function. 3852 // Legalizing the call will automatically add the previous call to the 3853 // dependence. 3854 SDOperand InChain = DAG.getEntryNode(); 3855 3856 TargetLowering::ArgListTy Args; 3857 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3858 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 3859 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 3860 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 3861 } 3862 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 3863 3864 // Splice the libcall in wherever FindInputOutputChains tells us to. 3865 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 3866 std::pair<SDOperand,SDOperand> CallInfo = 3867 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 3868 Callee, Args, DAG); 3869 3870 // Legalize the call sequence, starting with the chain. This will advance 3871 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 3872 // was added by LowerCallTo (guaranteeing proper serialization of calls). 3873 LegalizeOp(CallInfo.second); 3874 SDOperand Result; 3875 switch (getTypeAction(CallInfo.first.getValueType())) { 3876 default: assert(0 && "Unknown thing"); 3877 case Legal: 3878 Result = CallInfo.first; 3879 break; 3880 case Expand: 3881 ExpandOp(CallInfo.first, Result, Hi); 3882 break; 3883 } 3884 return Result; 3885} 3886 3887 3888/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 3889/// destination type is legal. 3890SDOperand SelectionDAGLegalize:: 3891ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 3892 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 3893 assert(getTypeAction(Source.getValueType()) == Expand && 3894 "This is not an expansion!"); 3895 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 3896 3897 if (!isSigned) { 3898 assert(Source.getValueType() == MVT::i64 && 3899 "This only works for 64-bit -> FP"); 3900 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 3901 // incoming integer is set. To handle this, we dynamically test to see if 3902 // it is set, and, if so, add a fudge factor. 3903 SDOperand Lo, Hi; 3904 ExpandOp(Source, Lo, Hi); 3905 3906 // If this is unsigned, and not supported, first perform the conversion to 3907 // signed, then adjust the result if the sign bit is set. 3908 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 3909 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 3910 3911 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 3912 DAG.getConstant(0, Hi.getValueType()), 3913 ISD::SETLT); 3914 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3915 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3916 SignSet, Four, Zero); 3917 uint64_t FF = 0x5f800000ULL; 3918 if (TLI.isLittleEndian()) FF <<= 32; 3919 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3920 3921 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3922 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3923 SDOperand FudgeInReg; 3924 if (DestTy == MVT::f32) 3925 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 3926 else { 3927 assert(DestTy == MVT::f64 && "Unexpected conversion"); 3928 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 3929 CPIdx, NULL, 0, MVT::f32); 3930 } 3931 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 3932 } 3933 3934 // Check to see if the target has a custom way to lower this. If so, use it. 3935 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 3936 default: assert(0 && "This action not implemented for this operation!"); 3937 case TargetLowering::Legal: 3938 case TargetLowering::Expand: 3939 break; // This case is handled below. 3940 case TargetLowering::Custom: { 3941 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 3942 Source), DAG); 3943 if (NV.Val) 3944 return LegalizeOp(NV); 3945 break; // The target decided this was legal after all 3946 } 3947 } 3948 3949 // Expand the source, then glue it back together for the call. We must expand 3950 // the source in case it is shared (this pass of legalize must traverse it). 3951 SDOperand SrcLo, SrcHi; 3952 ExpandOp(Source, SrcLo, SrcHi); 3953 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3954 3955 const char *FnName = 0; 3956 if (DestTy == MVT::f32) 3957 FnName = "__floatdisf"; 3958 else { 3959 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3960 FnName = "__floatdidf"; 3961 } 3962 3963 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 3964 SDOperand UnusedHiPart; 3965 return ExpandLibCall(FnName, Source.Val, UnusedHiPart); 3966} 3967 3968/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 3969/// INT_TO_FP operation of the specified operand when the target requests that 3970/// we expand it. At this point, we know that the result and operand types are 3971/// legal for the target. 3972SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 3973 SDOperand Op0, 3974 MVT::ValueType DestVT) { 3975 if (Op0.getValueType() == MVT::i32) { 3976 // simple 32-bit [signed|unsigned] integer to float/double expansion 3977 3978 // get the stack frame index of a 8 byte buffer 3979 MachineFunction &MF = DAG.getMachineFunction(); 3980 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 3981 // get address of 8 byte buffer 3982 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3983 // word offset constant for Hi/Lo address computation 3984 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 3985 // set up Hi and Lo (into buffer) address based on endian 3986 SDOperand Hi = StackSlot; 3987 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 3988 if (TLI.isLittleEndian()) 3989 std::swap(Hi, Lo); 3990 3991 // if signed map to unsigned space 3992 SDOperand Op0Mapped; 3993 if (isSigned) { 3994 // constant used to invert sign bit (signed to unsigned mapping) 3995 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 3996 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 3997 } else { 3998 Op0Mapped = Op0; 3999 } 4000 // store the lo of the constructed double - based on integer input 4001 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 4002 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 4003 // initial hi portion of constructed double 4004 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 4005 // store the hi of the constructed double - biased exponent 4006 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, DAG.getSrcValue(NULL)); 4007 // load the constructed double 4008 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 4009 // FP constant to bias correct the final result 4010 SDOperand Bias = DAG.getConstantFP(isSigned ? 4011 BitsToDouble(0x4330000080000000ULL) 4012 : BitsToDouble(0x4330000000000000ULL), 4013 MVT::f64); 4014 // subtract the bias 4015 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 4016 // final result 4017 SDOperand Result; 4018 // handle final rounding 4019 if (DestVT == MVT::f64) { 4020 // do nothing 4021 Result = Sub; 4022 } else { 4023 // if f32 then cast to f32 4024 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 4025 } 4026 return Result; 4027 } 4028 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 4029 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 4030 4031 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 4032 DAG.getConstant(0, Op0.getValueType()), 4033 ISD::SETLT); 4034 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4035 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4036 SignSet, Four, Zero); 4037 4038 // If the sign bit of the integer is set, the large number will be treated 4039 // as a negative number. To counteract this, the dynamic code adds an 4040 // offset depending on the data type. 4041 uint64_t FF; 4042 switch (Op0.getValueType()) { 4043 default: assert(0 && "Unsupported integer type!"); 4044 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 4045 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 4046 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 4047 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 4048 } 4049 if (TLI.isLittleEndian()) FF <<= 32; 4050 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 4051 4052 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4053 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4054 SDOperand FudgeInReg; 4055 if (DestVT == MVT::f32) 4056 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4057 else { 4058 assert(DestVT == MVT::f64 && "Unexpected conversion"); 4059 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 4060 DAG.getEntryNode(), CPIdx, 4061 NULL, 0, MVT::f32)); 4062 } 4063 4064 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 4065} 4066 4067/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 4068/// *INT_TO_FP operation of the specified operand when the target requests that 4069/// we promote it. At this point, we know that the result and operand types are 4070/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 4071/// operation that takes a larger input. 4072SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 4073 MVT::ValueType DestVT, 4074 bool isSigned) { 4075 // First step, figure out the appropriate *INT_TO_FP operation to use. 4076 MVT::ValueType NewInTy = LegalOp.getValueType(); 4077 4078 unsigned OpToUse = 0; 4079 4080 // Scan for the appropriate larger type to use. 4081 while (1) { 4082 NewInTy = (MVT::ValueType)(NewInTy+1); 4083 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 4084 4085 // If the target supports SINT_TO_FP of this type, use it. 4086 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 4087 default: break; 4088 case TargetLowering::Legal: 4089 if (!TLI.isTypeLegal(NewInTy)) 4090 break; // Can't use this datatype. 4091 // FALL THROUGH. 4092 case TargetLowering::Custom: 4093 OpToUse = ISD::SINT_TO_FP; 4094 break; 4095 } 4096 if (OpToUse) break; 4097 if (isSigned) continue; 4098 4099 // If the target supports UINT_TO_FP of this type, use it. 4100 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 4101 default: break; 4102 case TargetLowering::Legal: 4103 if (!TLI.isTypeLegal(NewInTy)) 4104 break; // Can't use this datatype. 4105 // FALL THROUGH. 4106 case TargetLowering::Custom: 4107 OpToUse = ISD::UINT_TO_FP; 4108 break; 4109 } 4110 if (OpToUse) break; 4111 4112 // Otherwise, try a larger type. 4113 } 4114 4115 // Okay, we found the operation and type to use. Zero extend our input to the 4116 // desired type then run the operation on it. 4117 return DAG.getNode(OpToUse, DestVT, 4118 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 4119 NewInTy, LegalOp)); 4120} 4121 4122/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 4123/// FP_TO_*INT operation of the specified operand when the target requests that 4124/// we promote it. At this point, we know that the result and operand types are 4125/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 4126/// operation that returns a larger result. 4127SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 4128 MVT::ValueType DestVT, 4129 bool isSigned) { 4130 // First step, figure out the appropriate FP_TO*INT operation to use. 4131 MVT::ValueType NewOutTy = DestVT; 4132 4133 unsigned OpToUse = 0; 4134 4135 // Scan for the appropriate larger type to use. 4136 while (1) { 4137 NewOutTy = (MVT::ValueType)(NewOutTy+1); 4138 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 4139 4140 // If the target supports FP_TO_SINT returning this type, use it. 4141 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 4142 default: break; 4143 case TargetLowering::Legal: 4144 if (!TLI.isTypeLegal(NewOutTy)) 4145 break; // Can't use this datatype. 4146 // FALL THROUGH. 4147 case TargetLowering::Custom: 4148 OpToUse = ISD::FP_TO_SINT; 4149 break; 4150 } 4151 if (OpToUse) break; 4152 4153 // If the target supports FP_TO_UINT of this type, use it. 4154 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 4155 default: break; 4156 case TargetLowering::Legal: 4157 if (!TLI.isTypeLegal(NewOutTy)) 4158 break; // Can't use this datatype. 4159 // FALL THROUGH. 4160 case TargetLowering::Custom: 4161 OpToUse = ISD::FP_TO_UINT; 4162 break; 4163 } 4164 if (OpToUse) break; 4165 4166 // Otherwise, try a larger type. 4167 } 4168 4169 // Okay, we found the operation and type to use. Truncate the result of the 4170 // extended FP_TO_*INT operation to the desired size. 4171 return DAG.getNode(ISD::TRUNCATE, DestVT, 4172 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 4173} 4174 4175/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 4176/// 4177SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 4178 MVT::ValueType VT = Op.getValueType(); 4179 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 4180 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 4181 switch (VT) { 4182 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 4183 case MVT::i16: 4184 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4185 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4186 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 4187 case MVT::i32: 4188 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4189 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4190 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4191 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4192 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 4193 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 4194 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4195 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4196 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4197 case MVT::i64: 4198 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 4199 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 4200 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4201 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4202 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4203 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4204 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 4205 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 4206 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 4207 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 4208 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 4209 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 4210 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 4211 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 4212 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 4213 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 4214 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4215 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4216 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 4217 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4218 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 4219 } 4220} 4221 4222/// ExpandBitCount - Expand the specified bitcount instruction into operations. 4223/// 4224SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 4225 switch (Opc) { 4226 default: assert(0 && "Cannot expand this yet!"); 4227 case ISD::CTPOP: { 4228 static const uint64_t mask[6] = { 4229 0x5555555555555555ULL, 0x3333333333333333ULL, 4230 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 4231 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 4232 }; 4233 MVT::ValueType VT = Op.getValueType(); 4234 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4235 unsigned len = getSizeInBits(VT); 4236 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4237 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 4238 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 4239 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4240 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 4241 DAG.getNode(ISD::AND, VT, 4242 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 4243 } 4244 return Op; 4245 } 4246 case ISD::CTLZ: { 4247 // for now, we do this: 4248 // x = x | (x >> 1); 4249 // x = x | (x >> 2); 4250 // ... 4251 // x = x | (x >>16); 4252 // x = x | (x >>32); // for 64-bit input 4253 // return popcount(~x); 4254 // 4255 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 4256 MVT::ValueType VT = Op.getValueType(); 4257 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4258 unsigned len = getSizeInBits(VT); 4259 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4260 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4261 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 4262 } 4263 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 4264 return DAG.getNode(ISD::CTPOP, VT, Op); 4265 } 4266 case ISD::CTTZ: { 4267 // for now, we use: { return popcount(~x & (x - 1)); } 4268 // unless the target has ctlz but not ctpop, in which case we use: 4269 // { return 32 - nlz(~x & (x-1)); } 4270 // see also http://www.hackersdelight.org/HDcode/ntz.cc 4271 MVT::ValueType VT = Op.getValueType(); 4272 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 4273 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 4274 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 4275 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 4276 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 4277 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 4278 TLI.isOperationLegal(ISD::CTLZ, VT)) 4279 return DAG.getNode(ISD::SUB, VT, 4280 DAG.getConstant(getSizeInBits(VT), VT), 4281 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 4282 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 4283 } 4284 } 4285} 4286 4287/// ExpandOp - Expand the specified SDOperand into its two component pieces 4288/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 4289/// LegalizeNodes map is filled in for any results that are not expanded, the 4290/// ExpandedNodes map is filled in for any results that are expanded, and the 4291/// Lo/Hi values are returned. 4292void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 4293 MVT::ValueType VT = Op.getValueType(); 4294 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4295 SDNode *Node = Op.Val; 4296 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 4297 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 4298 "Cannot expand FP values!"); 4299 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 4300 "Cannot expand to FP value or to larger int value!"); 4301 4302 // See if we already expanded it. 4303 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 4304 = ExpandedNodes.find(Op); 4305 if (I != ExpandedNodes.end()) { 4306 Lo = I->second.first; 4307 Hi = I->second.second; 4308 return; 4309 } 4310 4311 switch (Node->getOpcode()) { 4312 case ISD::CopyFromReg: 4313 assert(0 && "CopyFromReg must be legal!"); 4314 default: 4315#ifndef NDEBUG 4316 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 4317#endif 4318 assert(0 && "Do not know how to expand this operator!"); 4319 abort(); 4320 case ISD::UNDEF: 4321 Lo = DAG.getNode(ISD::UNDEF, NVT); 4322 Hi = DAG.getNode(ISD::UNDEF, NVT); 4323 break; 4324 case ISD::Constant: { 4325 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 4326 Lo = DAG.getConstant(Cst, NVT); 4327 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 4328 break; 4329 } 4330 case ISD::BUILD_PAIR: 4331 // Return the operands. 4332 Lo = Node->getOperand(0); 4333 Hi = Node->getOperand(1); 4334 break; 4335 4336 case ISD::SIGN_EXTEND_INREG: 4337 ExpandOp(Node->getOperand(0), Lo, Hi); 4338 // sext_inreg the low part if needed. 4339 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 4340 4341 // The high part gets the sign extension from the lo-part. This handles 4342 // things like sextinreg V:i64 from i8. 4343 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4344 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 4345 TLI.getShiftAmountTy())); 4346 break; 4347 4348 case ISD::BSWAP: { 4349 ExpandOp(Node->getOperand(0), Lo, Hi); 4350 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 4351 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 4352 Lo = TempLo; 4353 break; 4354 } 4355 4356 case ISD::CTPOP: 4357 ExpandOp(Node->getOperand(0), Lo, Hi); 4358 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 4359 DAG.getNode(ISD::CTPOP, NVT, Lo), 4360 DAG.getNode(ISD::CTPOP, NVT, Hi)); 4361 Hi = DAG.getConstant(0, NVT); 4362 break; 4363 4364 case ISD::CTLZ: { 4365 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 4366 ExpandOp(Node->getOperand(0), Lo, Hi); 4367 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4368 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 4369 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 4370 ISD::SETNE); 4371 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 4372 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 4373 4374 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 4375 Hi = DAG.getConstant(0, NVT); 4376 break; 4377 } 4378 4379 case ISD::CTTZ: { 4380 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 4381 ExpandOp(Node->getOperand(0), Lo, Hi); 4382 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4383 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 4384 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 4385 ISD::SETNE); 4386 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 4387 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 4388 4389 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 4390 Hi = DAG.getConstant(0, NVT); 4391 break; 4392 } 4393 4394 case ISD::VAARG: { 4395 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 4396 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 4397 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 4398 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 4399 4400 // Remember that we legalized the chain. 4401 Hi = LegalizeOp(Hi); 4402 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 4403 if (!TLI.isLittleEndian()) 4404 std::swap(Lo, Hi); 4405 break; 4406 } 4407 4408 case ISD::LOAD: { 4409 LoadSDNode *LD = cast<LoadSDNode>(Node); 4410 SDOperand Ch = LD->getChain(); // Legalize the chain. 4411 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 4412 ISD::LoadExtType ExtType = LD->getExtensionType(); 4413 4414 if (ExtType == ISD::NON_EXTLOAD) { 4415 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset()); 4416 4417 // Increment the pointer to the other half. 4418 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 4419 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4420 getIntPtrConstant(IncrementSize)); 4421 // FIXME: This creates a bogus srcvalue! 4422 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset()); 4423 4424 // Build a factor node to remember that this load is independent of the 4425 // other one. 4426 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 4427 Hi.getValue(1)); 4428 4429 // Remember that we legalized the chain. 4430 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 4431 if (!TLI.isLittleEndian()) 4432 std::swap(Lo, Hi); 4433 } else { 4434 MVT::ValueType EVT = LD->getLoadedVT(); 4435 4436 if (EVT == NVT) 4437 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 4438 LD->getSrcValueOffset()); 4439 else 4440 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 4441 LD->getSrcValueOffset(), EVT); 4442 4443 // Remember that we legalized the chain. 4444 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4445 4446 if (ExtType == ISD::SEXTLOAD) { 4447 // The high part is obtained by SRA'ing all but one of the bits of the 4448 // lo part. 4449 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4450 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4451 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 4452 } else if (ExtType == ISD::ZEXTLOAD) { 4453 // The high part is just a zero. 4454 Hi = DAG.getConstant(0, NVT); 4455 } else /* if (ExtType == ISD::EXTLOAD) */ { 4456 // The high part is undefined. 4457 Hi = DAG.getNode(ISD::UNDEF, NVT); 4458 } 4459 } 4460 break; 4461 } 4462 case ISD::AND: 4463 case ISD::OR: 4464 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 4465 SDOperand LL, LH, RL, RH; 4466 ExpandOp(Node->getOperand(0), LL, LH); 4467 ExpandOp(Node->getOperand(1), RL, RH); 4468 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 4469 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 4470 break; 4471 } 4472 case ISD::SELECT: { 4473 SDOperand LL, LH, RL, RH; 4474 ExpandOp(Node->getOperand(1), LL, LH); 4475 ExpandOp(Node->getOperand(2), RL, RH); 4476 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 4477 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 4478 break; 4479 } 4480 case ISD::SELECT_CC: { 4481 SDOperand TL, TH, FL, FH; 4482 ExpandOp(Node->getOperand(2), TL, TH); 4483 ExpandOp(Node->getOperand(3), FL, FH); 4484 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4485 Node->getOperand(1), TL, FL, Node->getOperand(4)); 4486 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4487 Node->getOperand(1), TH, FH, Node->getOperand(4)); 4488 break; 4489 } 4490 case ISD::ANY_EXTEND: 4491 // The low part is any extension of the input (which degenerates to a copy). 4492 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 4493 // The high part is undefined. 4494 Hi = DAG.getNode(ISD::UNDEF, NVT); 4495 break; 4496 case ISD::SIGN_EXTEND: { 4497 // The low part is just a sign extension of the input (which degenerates to 4498 // a copy). 4499 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 4500 4501 // The high part is obtained by SRA'ing all but one of the bits of the lo 4502 // part. 4503 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4504 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4505 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 4506 break; 4507 } 4508 case ISD::ZERO_EXTEND: 4509 // The low part is just a zero extension of the input (which degenerates to 4510 // a copy). 4511 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4512 4513 // The high part is just a zero. 4514 Hi = DAG.getConstant(0, NVT); 4515 break; 4516 4517 case ISD::BIT_CONVERT: { 4518 SDOperand Tmp; 4519 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 4520 // If the target wants to, allow it to lower this itself. 4521 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4522 case Expand: assert(0 && "cannot expand FP!"); 4523 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 4524 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 4525 } 4526 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 4527 } 4528 4529 // Turn this into a load/store pair by default. 4530 if (Tmp.Val == 0) 4531 Tmp = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 4532 4533 ExpandOp(Tmp, Lo, Hi); 4534 break; 4535 } 4536 4537 case ISD::READCYCLECOUNTER: 4538 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 4539 TargetLowering::Custom && 4540 "Must custom expand ReadCycleCounter"); 4541 Lo = TLI.LowerOperation(Op, DAG); 4542 assert(Lo.Val && "Node must be custom expanded!"); 4543 Hi = Lo.getValue(1); 4544 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 4545 LegalizeOp(Lo.getValue(2))); 4546 break; 4547 4548 // These operators cannot be expanded directly, emit them as calls to 4549 // library functions. 4550 case ISD::FP_TO_SINT: 4551 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 4552 SDOperand Op; 4553 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4554 case Expand: assert(0 && "cannot expand FP!"); 4555 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 4556 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 4557 } 4558 4559 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 4560 4561 // Now that the custom expander is done, expand the result, which is still 4562 // VT. 4563 if (Op.Val) { 4564 ExpandOp(Op, Lo, Hi); 4565 break; 4566 } 4567 } 4568 4569 if (Node->getOperand(0).getValueType() == MVT::f32) 4570 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 4571 else 4572 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 4573 break; 4574 4575 case ISD::FP_TO_UINT: 4576 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 4577 SDOperand Op; 4578 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4579 case Expand: assert(0 && "cannot expand FP!"); 4580 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 4581 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 4582 } 4583 4584 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 4585 4586 // Now that the custom expander is done, expand the result. 4587 if (Op.Val) { 4588 ExpandOp(Op, Lo, Hi); 4589 break; 4590 } 4591 } 4592 4593 if (Node->getOperand(0).getValueType() == MVT::f32) 4594 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 4595 else 4596 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 4597 break; 4598 4599 case ISD::SHL: { 4600 // If the target wants custom lowering, do so. 4601 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4602 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 4603 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 4604 Op = TLI.LowerOperation(Op, DAG); 4605 if (Op.Val) { 4606 // Now that the custom expander is done, expand the result, which is 4607 // still VT. 4608 ExpandOp(Op, Lo, Hi); 4609 break; 4610 } 4611 } 4612 4613 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 4614 // this X << 1 as X+X. 4615 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 4616 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 4617 TLI.isOperationLegal(ISD::ADDE, NVT)) { 4618 SDOperand LoOps[2], HiOps[3]; 4619 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 4620 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 4621 LoOps[1] = LoOps[0]; 4622 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 4623 4624 HiOps[1] = HiOps[0]; 4625 HiOps[2] = Lo.getValue(1); 4626 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 4627 break; 4628 } 4629 } 4630 4631 // If we can emit an efficient shift operation, do so now. 4632 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4633 break; 4634 4635 // If this target supports SHL_PARTS, use it. 4636 TargetLowering::LegalizeAction Action = 4637 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 4638 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4639 Action == TargetLowering::Custom) { 4640 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4641 break; 4642 } 4643 4644 // Otherwise, emit a libcall. 4645 Lo = ExpandLibCall("__ashldi3", Node, Hi); 4646 break; 4647 } 4648 4649 case ISD::SRA: { 4650 // If the target wants custom lowering, do so. 4651 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4652 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 4653 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 4654 Op = TLI.LowerOperation(Op, DAG); 4655 if (Op.Val) { 4656 // Now that the custom expander is done, expand the result, which is 4657 // still VT. 4658 ExpandOp(Op, Lo, Hi); 4659 break; 4660 } 4661 } 4662 4663 // If we can emit an efficient shift operation, do so now. 4664 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4665 break; 4666 4667 // If this target supports SRA_PARTS, use it. 4668 TargetLowering::LegalizeAction Action = 4669 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 4670 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4671 Action == TargetLowering::Custom) { 4672 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4673 break; 4674 } 4675 4676 // Otherwise, emit a libcall. 4677 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 4678 break; 4679 } 4680 4681 case ISD::SRL: { 4682 // If the target wants custom lowering, do so. 4683 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4684 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 4685 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 4686 Op = TLI.LowerOperation(Op, DAG); 4687 if (Op.Val) { 4688 // Now that the custom expander is done, expand the result, which is 4689 // still VT. 4690 ExpandOp(Op, Lo, Hi); 4691 break; 4692 } 4693 } 4694 4695 // If we can emit an efficient shift operation, do so now. 4696 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4697 break; 4698 4699 // If this target supports SRL_PARTS, use it. 4700 TargetLowering::LegalizeAction Action = 4701 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 4702 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4703 Action == TargetLowering::Custom) { 4704 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4705 break; 4706 } 4707 4708 // Otherwise, emit a libcall. 4709 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 4710 break; 4711 } 4712 4713 case ISD::ADD: 4714 case ISD::SUB: { 4715 // If the target wants to custom expand this, let them. 4716 if (TLI.getOperationAction(Node->getOpcode(), VT) == 4717 TargetLowering::Custom) { 4718 Op = TLI.LowerOperation(Op, DAG); 4719 if (Op.Val) { 4720 ExpandOp(Op, Lo, Hi); 4721 break; 4722 } 4723 } 4724 4725 // Expand the subcomponents. 4726 SDOperand LHSL, LHSH, RHSL, RHSH; 4727 ExpandOp(Node->getOperand(0), LHSL, LHSH); 4728 ExpandOp(Node->getOperand(1), RHSL, RHSH); 4729 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 4730 SDOperand LoOps[2], HiOps[3]; 4731 LoOps[0] = LHSL; 4732 LoOps[1] = RHSL; 4733 HiOps[0] = LHSH; 4734 HiOps[1] = RHSH; 4735 if (Node->getOpcode() == ISD::ADD) { 4736 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 4737 HiOps[2] = Lo.getValue(1); 4738 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 4739 } else { 4740 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 4741 HiOps[2] = Lo.getValue(1); 4742 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 4743 } 4744 break; 4745 } 4746 case ISD::MUL: { 4747 // If the target wants to custom expand this, let them. 4748 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 4749 SDOperand New = TLI.LowerOperation(Op, DAG); 4750 if (New.Val) { 4751 ExpandOp(New, Lo, Hi); 4752 break; 4753 } 4754 } 4755 4756 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 4757 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 4758 bool UseLibCall = true; 4759 if (HasMULHS || HasMULHU) { 4760 SDOperand LL, LH, RL, RH; 4761 ExpandOp(Node->getOperand(0), LL, LH); 4762 ExpandOp(Node->getOperand(1), RL, RH); 4763 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 4764 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 4765 // extended the sign bit of the low half through the upper half, and if so 4766 // emit a MULHS instead of the alternate sequence that is valid for any 4767 // i64 x i64 multiply. 4768 if (HasMULHS && 4769 // is RH an extension of the sign bit of RL? 4770 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 4771 RH.getOperand(1).getOpcode() == ISD::Constant && 4772 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 4773 // is LH an extension of the sign bit of LL? 4774 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 4775 LH.getOperand(1).getOpcode() == ISD::Constant && 4776 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 4777 // FIXME: Move this to the dag combiner. 4778 4779 // Low part: 4780 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 4781 // High part: 4782 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 4783 break; 4784 } else if (HasMULHU) { 4785 // Low part: 4786 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 4787 4788 // High part: 4789 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 4790 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 4791 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 4792 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 4793 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 4794 break; 4795 } 4796 } 4797 4798 Lo = ExpandLibCall("__muldi3" , Node, Hi); 4799 break; 4800 } 4801 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 4802 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 4803 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 4804 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 4805 } 4806 4807 // Make sure the resultant values have been legalized themselves, unless this 4808 // is a type that requires multi-step expansion. 4809 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 4810 Lo = LegalizeOp(Lo); 4811 Hi = LegalizeOp(Hi); 4812 } 4813 4814 // Remember in a map if the values will be reused later. 4815 bool isNew = 4816 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 4817 assert(isNew && "Value already expanded?!?"); 4818} 4819 4820/// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 4821/// two smaller values of MVT::Vector type. 4822void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 4823 SDOperand &Hi) { 4824 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!"); 4825 SDNode *Node = Op.Val; 4826 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue(); 4827 assert(NumElements > 1 && "Cannot split a single element vector!"); 4828 unsigned NewNumElts = NumElements/2; 4829 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32); 4830 SDOperand TypeNode = *(Node->op_end()-1); 4831 4832 // See if we already split it. 4833 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 4834 = SplitNodes.find(Op); 4835 if (I != SplitNodes.end()) { 4836 Lo = I->second.first; 4837 Hi = I->second.second; 4838 return; 4839 } 4840 4841 switch (Node->getOpcode()) { 4842 default: 4843#ifndef NDEBUG 4844 Node->dump(); 4845#endif 4846 assert(0 && "Unhandled operation in SplitVectorOp!"); 4847 case ISD::VBUILD_VECTOR: { 4848 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 4849 Node->op_begin()+NewNumElts); 4850 LoOps.push_back(NewNumEltsNode); 4851 LoOps.push_back(TypeNode); 4852 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size()); 4853 4854 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts, 4855 Node->op_end()-2); 4856 HiOps.push_back(NewNumEltsNode); 4857 HiOps.push_back(TypeNode); 4858 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size()); 4859 break; 4860 } 4861 case ISD::VADD: 4862 case ISD::VSUB: 4863 case ISD::VMUL: 4864 case ISD::VSDIV: 4865 case ISD::VUDIV: 4866 case ISD::VAND: 4867 case ISD::VOR: 4868 case ISD::VXOR: { 4869 SDOperand LL, LH, RL, RH; 4870 SplitVectorOp(Node->getOperand(0), LL, LH); 4871 SplitVectorOp(Node->getOperand(1), RL, RH); 4872 4873 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, 4874 NewNumEltsNode, TypeNode); 4875 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, 4876 NewNumEltsNode, TypeNode); 4877 break; 4878 } 4879 case ISD::VLOAD: { 4880 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 4881 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 4882 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 4883 4884 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 4885 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8; 4886 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4887 getIntPtrConstant(IncrementSize)); 4888 // FIXME: This creates a bogus srcvalue! 4889 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 4890 4891 // Build a factor node to remember that this load is independent of the 4892 // other one. 4893 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 4894 Hi.getValue(1)); 4895 4896 // Remember that we legalized the chain. 4897 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 4898 break; 4899 } 4900 case ISD::VBIT_CONVERT: { 4901 // We know the result is a vector. The input may be either a vector or a 4902 // scalar value. 4903 if (Op.getOperand(0).getValueType() != MVT::Vector) { 4904 // Lower to a store/load. FIXME: this could be improved probably. 4905 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType()); 4906 4907 SDOperand St = DAG.getStore(DAG.getEntryNode(), 4908 Op.getOperand(0), Ptr, DAG.getSrcValue(0)); 4909 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 4910 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0)); 4911 SplitVectorOp(St, Lo, Hi); 4912 } else { 4913 // If the input is a vector type, we have to either scalarize it, pack it 4914 // or convert it based on whether the input vector type is legal. 4915 SDNode *InVal = Node->getOperand(0).Val; 4916 unsigned NumElems = 4917 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 4918 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 4919 4920 // If the input is from a single element vector, scalarize the vector, 4921 // then treat like a scalar. 4922 if (NumElems == 1) { 4923 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT); 4924 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar, 4925 Op.getOperand(1), Op.getOperand(2)); 4926 SplitVectorOp(Scalar, Lo, Hi); 4927 } else { 4928 // Split the input vector. 4929 SplitVectorOp(Op.getOperand(0), Lo, Hi); 4930 4931 // Convert each of the pieces now. 4932 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo, 4933 NewNumEltsNode, TypeNode); 4934 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi, 4935 NewNumEltsNode, TypeNode); 4936 } 4937 break; 4938 } 4939 } 4940 } 4941 4942 // Remember in a map if the values will be reused later. 4943 bool isNew = 4944 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 4945 assert(isNew && "Value already expanded?!?"); 4946} 4947 4948 4949/// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 4950/// equivalent operation that returns a scalar (e.g. F32) or packed value 4951/// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right 4952/// type for the result. 4953SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, 4954 MVT::ValueType NewVT) { 4955 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!"); 4956 SDNode *Node = Op.Val; 4957 4958 // See if we already packed it. 4959 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op); 4960 if (I != PackedNodes.end()) return I->second; 4961 4962 SDOperand Result; 4963 switch (Node->getOpcode()) { 4964 default: 4965#ifndef NDEBUG 4966 Node->dump(); std::cerr << "\n"; 4967#endif 4968 assert(0 && "Unknown vector operation in PackVectorOp!"); 4969 case ISD::VADD: 4970 case ISD::VSUB: 4971 case ISD::VMUL: 4972 case ISD::VSDIV: 4973 case ISD::VUDIV: 4974 case ISD::VAND: 4975 case ISD::VOR: 4976 case ISD::VXOR: 4977 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT), 4978 NewVT, 4979 PackVectorOp(Node->getOperand(0), NewVT), 4980 PackVectorOp(Node->getOperand(1), NewVT)); 4981 break; 4982 case ISD::VLOAD: { 4983 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 4984 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 4985 4986 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 4987 Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset()); 4988 4989 // Remember that we legalized the chain. 4990 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4991 break; 4992 } 4993 case ISD::VBUILD_VECTOR: 4994 if (Node->getOperand(0).getValueType() == NewVT) { 4995 // Returning a scalar? 4996 Result = Node->getOperand(0); 4997 } else { 4998 // Returning a BUILD_VECTOR? 4999 5000 // If all elements of the build_vector are undefs, return an undef. 5001 bool AllUndef = true; 5002 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i) 5003 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) { 5004 AllUndef = false; 5005 break; 5006 } 5007 if (AllUndef) { 5008 Result = DAG.getNode(ISD::UNDEF, NewVT); 5009 } else { 5010 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(), 5011 Node->getNumOperands()-2); 5012 } 5013 } 5014 break; 5015 case ISD::VINSERT_VECTOR_ELT: 5016 if (!MVT::isVector(NewVT)) { 5017 // Returning a scalar? Must be the inserted element. 5018 Result = Node->getOperand(1); 5019 } else { 5020 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, 5021 PackVectorOp(Node->getOperand(0), NewVT), 5022 Node->getOperand(1), Node->getOperand(2)); 5023 } 5024 break; 5025 case ISD::VVECTOR_SHUFFLE: 5026 if (!MVT::isVector(NewVT)) { 5027 // Returning a scalar? Figure out if it is the LHS or RHS and return it. 5028 SDOperand EltNum = Node->getOperand(2).getOperand(0); 5029 if (cast<ConstantSDNode>(EltNum)->getValue()) 5030 Result = PackVectorOp(Node->getOperand(1), NewVT); 5031 else 5032 Result = PackVectorOp(Node->getOperand(0), NewVT); 5033 } else { 5034 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index 5035 // vector from a VBUILD_VECTOR to a BUILD_VECTOR. 5036 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(), 5037 Node->getOperand(2).Val->op_end()-2); 5038 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size()); 5039 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, 5040 Node->getOperand(2).Val->op_begin(), 5041 Node->getOperand(2).Val->getNumOperands()-2); 5042 5043 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, 5044 PackVectorOp(Node->getOperand(0), NewVT), 5045 PackVectorOp(Node->getOperand(1), NewVT), BV); 5046 } 5047 break; 5048 case ISD::VBIT_CONVERT: 5049 if (Op.getOperand(0).getValueType() != MVT::Vector) 5050 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 5051 else { 5052 // If the input is a vector type, we have to either scalarize it, pack it 5053 // or convert it based on whether the input vector type is legal. 5054 SDNode *InVal = Node->getOperand(0).Val; 5055 unsigned NumElems = 5056 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 5057 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 5058 5059 // Figure out if there is a Packed type corresponding to this Vector 5060 // type. If so, convert to the packed type. 5061 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 5062 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 5063 // Turn this into a bit convert of the packed input. 5064 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 5065 PackVectorOp(Node->getOperand(0), TVT)); 5066 break; 5067 } else if (NumElems == 1) { 5068 // Turn this into a bit convert of the scalar input. 5069 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 5070 PackVectorOp(Node->getOperand(0), EVT)); 5071 break; 5072 } else { 5073 // FIXME: UNIMP! 5074 assert(0 && "Cast from unsupported vector type not implemented yet!"); 5075 } 5076 } 5077 break; 5078 case ISD::VSELECT: 5079 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 5080 PackVectorOp(Op.getOperand(1), NewVT), 5081 PackVectorOp(Op.getOperand(2), NewVT)); 5082 break; 5083 } 5084 5085 if (TLI.isTypeLegal(NewVT)) 5086 Result = LegalizeOp(Result); 5087 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second; 5088 assert(isNew && "Value already packed?"); 5089 return Result; 5090} 5091 5092 5093// SelectionDAG::Legalize - This is the entry point for the file. 5094// 5095void SelectionDAG::Legalize() { 5096 if (ViewLegalizeDAGs) viewGraph(); 5097 5098 /// run - This is the main entry point to this class. 5099 /// 5100 SelectionDAGLegalize(*this).LegalizeDAG(); 5101} 5102 5103