LegalizeDAG.cpp revision 39355f9fea790c5a1b12ef0fdcfeac3f533232ea
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/DwarfWriter.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/CodeGen/PseudoSourceValue.h" 22#include "llvm/Target/TargetFrameInfo.h" 23#include "llvm/Target/TargetLowering.h" 24#include "llvm/Target/TargetData.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Target/TargetSubtarget.h" 28#include "llvm/CallingConv.h" 29#include "llvm/Constants.h" 30#include "llvm/DerivedTypes.h" 31#include "llvm/GlobalVariable.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Compiler.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/ADT/DenseMap.h" 36#include "llvm/ADT/SmallVector.h" 37#include "llvm/ADT/SmallPtrSet.h" 38#include <map> 39using namespace llvm; 40 41//===----------------------------------------------------------------------===// 42/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 43/// hacks on it until the target machine can handle it. This involves 44/// eliminating value sizes the machine cannot handle (promoting small sizes to 45/// large sizes or splitting up large values into small values) as well as 46/// eliminating operations the machine cannot handle. 47/// 48/// This code also does a small amount of optimization and recognition of idioms 49/// as part of its processing. For example, if a target does not support a 50/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 51/// will attempt merge setcc and brc instructions into brcc's. 52/// 53namespace { 54class VISIBILITY_HIDDEN SelectionDAGLegalize { 55 TargetLowering &TLI; 56 SelectionDAG &DAG; 57 bool TypesNeedLegalizing; 58 59 // Libcall insertion helpers. 60 61 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 62 /// legalized. We use this to ensure that calls are properly serialized 63 /// against each other, including inserted libcalls. 64 SDValue LastCALLSEQ_END; 65 66 /// IsLegalizingCall - This member is used *only* for purposes of providing 67 /// helpful assertions that a libcall isn't created while another call is 68 /// being legalized (which could lead to non-serialized call sequences). 69 bool IsLegalizingCall; 70 71 enum LegalizeAction { 72 Legal, // The target natively supports this operation. 73 Promote, // This operation should be executed in a larger type. 74 Expand // Try to expand this to other ops, otherwise use a libcall. 75 }; 76 77 /// ValueTypeActions - This is a bitvector that contains two bits for each 78 /// value type, where the two bits correspond to the LegalizeAction enum. 79 /// This can be queried with "getTypeAction(VT)". 80 TargetLowering::ValueTypeActionImpl ValueTypeActions; 81 82 /// LegalizedNodes - For nodes that are of legal width, and that have more 83 /// than one use, this map indicates what regularized operand to use. This 84 /// allows us to avoid legalizing the same thing more than once. 85 DenseMap<SDValue, SDValue> LegalizedNodes; 86 87 /// PromotedNodes - For nodes that are below legal width, and that have more 88 /// than one use, this map indicates what promoted value to use. This allows 89 /// us to avoid promoting the same thing more than once. 90 DenseMap<SDValue, SDValue> PromotedNodes; 91 92 /// ExpandedNodes - For nodes that need to be expanded this map indicates 93 /// which operands are the expanded version of the input. This allows 94 /// us to avoid expanding the same node more than once. 95 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes; 96 97 /// SplitNodes - For vector nodes that need to be split, this map indicates 98 /// which operands are the split version of the input. This allows us 99 /// to avoid splitting the same node more than once. 100 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes; 101 102 /// ScalarizedNodes - For nodes that need to be converted from vector types to 103 /// scalar types, this contains the mapping of ones we have already 104 /// processed to the result. 105 std::map<SDValue, SDValue> ScalarizedNodes; 106 107 /// WidenNodes - For nodes that need to be widened from one vector type to 108 /// another, this contains the mapping of those that we have already widen. 109 /// This allows us to avoid widening more than once. 110 std::map<SDValue, SDValue> WidenNodes; 111 112 void AddLegalizedOperand(SDValue From, SDValue To) { 113 LegalizedNodes.insert(std::make_pair(From, To)); 114 // If someone requests legalization of the new node, return itself. 115 if (From != To) 116 LegalizedNodes.insert(std::make_pair(To, To)); 117 } 118 void AddPromotedOperand(SDValue From, SDValue To) { 119 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 120 assert(isNew && "Got into the map somehow?"); 121 isNew = isNew; 122 // If someone requests legalization of the new node, return itself. 123 LegalizedNodes.insert(std::make_pair(To, To)); 124 } 125 void AddWidenedOperand(SDValue From, SDValue To) { 126 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second; 127 assert(isNew && "Got into the map somehow?"); 128 isNew = isNew; 129 // If someone requests legalization of the new node, return itself. 130 LegalizedNodes.insert(std::make_pair(To, To)); 131 } 132 133public: 134 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing); 135 136 /// getTypeAction - Return how we should legalize values of this type, either 137 /// it is already legal or we need to expand it into multiple registers of 138 /// smaller integer type, or we need to promote it to a larger type. 139 LegalizeAction getTypeAction(MVT VT) const { 140 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 141 } 142 143 /// isTypeLegal - Return true if this type is legal on this target. 144 /// 145 bool isTypeLegal(MVT VT) const { 146 return getTypeAction(VT) == Legal; 147 } 148 149 void LegalizeDAG(); 150 151private: 152 /// HandleOp - Legalize, Promote, or Expand the specified operand as 153 /// appropriate for its type. 154 void HandleOp(SDValue Op); 155 156 /// LegalizeOp - We know that the specified value has a legal type. 157 /// Recursively ensure that the operands have legal types, then return the 158 /// result. 159 SDValue LegalizeOp(SDValue O); 160 161 /// UnrollVectorOp - We know that the given vector has a legal type, however 162 /// the operation it performs is not legal and is an operation that we have 163 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 164 /// operating on each element individually. 165 SDValue UnrollVectorOp(SDValue O); 166 167 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 168 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 169 /// is necessary to spill the vector being inserted into to memory, perform 170 /// the insert there, and then read the result back. 171 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 172 SDValue Idx, DebugLoc dl); 173 174 /// PromoteOp - Given an operation that produces a value in an invalid type, 175 /// promote it to compute the value into a larger type. The produced value 176 /// will have the correct bits for the low portion of the register, but no 177 /// guarantee is made about the top bits: it may be zero, sign-extended, or 178 /// garbage. 179 SDValue PromoteOp(SDValue O); 180 181 /// ExpandOp - Expand the specified SDValue into its two component pieces 182 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 183 /// the LegalizedNodes map is filled in for any results that are not expanded, 184 /// the ExpandedNodes map is filled in for any results that are expanded, and 185 /// the Lo/Hi values are returned. This applies to integer types and Vector 186 /// types. 187 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi); 188 189 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT 190 /// (e.g., v3i32 to v4i32). The produced value will have the correct value 191 /// for the existing elements but no guarantee is made about the new elements 192 /// at the end of the vector: it may be zero, ones, or garbage. This is useful 193 /// when we have an instruction operating on an illegal vector type and we 194 /// want to widen it to do the computation on a legal wider vector type. 195 SDValue WidenVectorOp(SDValue Op, MVT WidenVT); 196 197 /// SplitVectorOp - Given an operand of vector type, break it down into 198 /// two smaller values. 199 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi); 200 201 /// ScalarizeVectorOp - Given an operand of single-element vector type 202 /// (e.g. v1f32), convert it into the equivalent operation that returns a 203 /// scalar (e.g. f32) value. 204 SDValue ScalarizeVectorOp(SDValue O); 205 206 /// Useful 16 element vector type that is used to pass operands for widening. 207 typedef SmallVector<SDValue, 16> SDValueVector; 208 209 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if 210 /// the LdChain contains a single load and false if it contains a token 211 /// factor for multiple loads. It takes 212 /// Result: location to return the result 213 /// LdChain: location to return the load chain 214 /// Op: load operation to widen 215 /// NVT: widen vector result type we want for the load 216 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain, 217 SDValue Op, MVT NVT); 218 219 /// Helper genWidenVectorLoads - Helper function to generate a set of 220 /// loads to load a vector with a resulting wider type. It takes 221 /// LdChain: list of chains for the load we have generated 222 /// Chain: incoming chain for the ld vector 223 /// BasePtr: base pointer to load from 224 /// SV: memory disambiguation source value 225 /// SVOffset: memory disambiugation offset 226 /// Alignment: alignment of the memory 227 /// isVolatile: volatile load 228 /// LdWidth: width of memory that we want to load 229 /// ResType: the wider result result type for the resulting loaded vector 230 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain, 231 SDValue BasePtr, const Value *SV, 232 int SVOffset, unsigned Alignment, 233 bool isVolatile, unsigned LdWidth, 234 MVT ResType, DebugLoc dl); 235 236 /// StoreWidenVectorOp - Stores a widen vector into non widen memory 237 /// location. It takes 238 /// ST: store node that we want to replace 239 /// Chain: incoming store chain 240 /// BasePtr: base address of where we want to store into 241 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain, 242 SDValue BasePtr); 243 244 /// Helper genWidenVectorStores - Helper function to generate a set of 245 /// stores to store a widen vector into non widen memory 246 // It takes 247 // StChain: list of chains for the stores we have generated 248 // Chain: incoming chain for the ld vector 249 // BasePtr: base pointer to load from 250 // SV: memory disambiguation source value 251 // SVOffset: memory disambiugation offset 252 // Alignment: alignment of the memory 253 // isVolatile: volatile lod 254 // ValOp: value to store 255 // StWidth: width of memory that we want to store 256 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain, 257 SDValue BasePtr, const Value *SV, 258 int SVOffset, unsigned Alignment, 259 bool isVolatile, SDValue ValOp, 260 unsigned StWidth, DebugLoc dl); 261 262 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the 263 /// specified mask and type. Targets can specify exactly which masks they 264 /// support and the code generator is tasked with not creating illegal masks. 265 /// 266 /// Note that this will also return true for shuffles that are promoted to a 267 /// different type. 268 /// 269 /// If this is a legal shuffle, this method returns the (possibly promoted) 270 /// build_vector Mask. If it's not a legal shuffle, it returns null. 271 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const; 272 273 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 274 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 275 276 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC, 277 DebugLoc dl); 278 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 279 DebugLoc dl); 280 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 281 DebugLoc dl) { 282 LegalizeSetCCOperands(LHS, RHS, CC, dl); 283 LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl); 284 } 285 286 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, 287 SDValue &Hi); 288 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl); 289 290 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl); 291 SDValue ExpandBUILD_VECTOR(SDNode *Node); 292 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 293 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, 294 SDValue Op, DebugLoc dl); 295 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT, 296 DebugLoc dl); 297 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned, 298 DebugLoc dl); 299 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned, 300 DebugLoc dl); 301 302 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 303 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 304 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt, 305 SDValue &Lo, SDValue &Hi, DebugLoc dl); 306 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt, 307 SDValue &Lo, SDValue &Hi, DebugLoc dl); 308 309 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op); 310 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op); 311}; 312} 313 314/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 315/// specified mask and type. Targets can specify exactly which masks they 316/// support and the code generator is tasked with not creating illegal masks. 317/// 318/// Note that this will also return true for shuffles that are promoted to a 319/// different type. 320SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const { 321 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 322 default: return 0; 323 case TargetLowering::Legal: 324 case TargetLowering::Custom: 325 break; 326 case TargetLowering::Promote: { 327 // If this is promoted to a different type, convert the shuffle mask and 328 // ask if it is legal in the promoted type! 329 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 330 MVT EltVT = NVT.getVectorElementType(); 331 332 // If we changed # elements, change the shuffle mask. 333 unsigned NumEltsGrowth = 334 NVT.getVectorNumElements() / VT.getVectorNumElements(); 335 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 336 if (NumEltsGrowth > 1) { 337 // Renumber the elements. 338 SmallVector<SDValue, 8> Ops; 339 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 340 SDValue InOp = Mask.getOperand(i); 341 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 342 if (InOp.getOpcode() == ISD::UNDEF) 343 Ops.push_back(DAG.getNode(ISD::UNDEF, 344 InOp.getNode()->getDebugLoc(), EltVT)); 345 else { 346 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue(); 347 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT)); 348 } 349 } 350 } 351 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getNode()->getDebugLoc(), 352 NVT, &Ops[0], Ops.size()); 353 } 354 VT = NVT; 355 break; 356 } 357 } 358 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0; 359} 360 361SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, bool types) 362 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types), 363 ValueTypeActions(TLI.getValueTypeActions()) { 364 assert(MVT::LAST_VALUETYPE <= 32 && 365 "Too many value types for ValueTypeActions to hold!"); 366} 367 368void SelectionDAGLegalize::LegalizeDAG() { 369 LastCALLSEQ_END = DAG.getEntryNode(); 370 IsLegalizingCall = false; 371 372 // The legalize process is inherently a bottom-up recursive process (users 373 // legalize their uses before themselves). Given infinite stack space, we 374 // could just start legalizing on the root and traverse the whole graph. In 375 // practice however, this causes us to run out of stack space on large basic 376 // blocks. To avoid this problem, compute an ordering of the nodes where each 377 // node is only legalized after all of its operands are legalized. 378 DAG.AssignTopologicalOrder(); 379 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 380 E = prior(DAG.allnodes_end()); I != next(E); ++I) 381 HandleOp(SDValue(I, 0)); 382 383 // Finally, it's possible the root changed. Get the new root. 384 SDValue OldRoot = DAG.getRoot(); 385 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 386 DAG.setRoot(LegalizedNodes[OldRoot]); 387 388 ExpandedNodes.clear(); 389 LegalizedNodes.clear(); 390 PromotedNodes.clear(); 391 SplitNodes.clear(); 392 ScalarizedNodes.clear(); 393 WidenNodes.clear(); 394 395 // Remove dead nodes now. 396 DAG.RemoveDeadNodes(); 397} 398 399 400/// FindCallEndFromCallStart - Given a chained node that is part of a call 401/// sequence, find the CALLSEQ_END node that terminates the call sequence. 402static SDNode *FindCallEndFromCallStart(SDNode *Node) { 403 if (Node->getOpcode() == ISD::CALLSEQ_END) 404 return Node; 405 if (Node->use_empty()) 406 return 0; // No CallSeqEnd 407 408 // The chain is usually at the end. 409 SDValue TheChain(Node, Node->getNumValues()-1); 410 if (TheChain.getValueType() != MVT::Other) { 411 // Sometimes it's at the beginning. 412 TheChain = SDValue(Node, 0); 413 if (TheChain.getValueType() != MVT::Other) { 414 // Otherwise, hunt for it. 415 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 416 if (Node->getValueType(i) == MVT::Other) { 417 TheChain = SDValue(Node, i); 418 break; 419 } 420 421 // Otherwise, we walked into a node without a chain. 422 if (TheChain.getValueType() != MVT::Other) 423 return 0; 424 } 425 } 426 427 for (SDNode::use_iterator UI = Node->use_begin(), 428 E = Node->use_end(); UI != E; ++UI) { 429 430 // Make sure to only follow users of our token chain. 431 SDNode *User = *UI; 432 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 433 if (User->getOperand(i) == TheChain) 434 if (SDNode *Result = FindCallEndFromCallStart(User)) 435 return Result; 436 } 437 return 0; 438} 439 440/// FindCallStartFromCallEnd - Given a chained node that is part of a call 441/// sequence, find the CALLSEQ_START node that initiates the call sequence. 442static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 443 assert(Node && "Didn't find callseq_start for a call??"); 444 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 445 446 assert(Node->getOperand(0).getValueType() == MVT::Other && 447 "Node doesn't have a token chain argument!"); 448 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 449} 450 451/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 452/// see if any uses can reach Dest. If no dest operands can get to dest, 453/// legalize them, legalize ourself, and return false, otherwise, return true. 454/// 455/// Keep track of the nodes we fine that actually do lead to Dest in 456/// NodesLeadingTo. This avoids retraversing them exponential number of times. 457/// 458bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 459 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 460 if (N == Dest) return true; // N certainly leads to Dest :) 461 462 // If we've already processed this node and it does lead to Dest, there is no 463 // need to reprocess it. 464 if (NodesLeadingTo.count(N)) return true; 465 466 // If the first result of this node has been already legalized, then it cannot 467 // reach N. 468 switch (getTypeAction(N->getValueType(0))) { 469 case Legal: 470 if (LegalizedNodes.count(SDValue(N, 0))) return false; 471 break; 472 case Promote: 473 if (PromotedNodes.count(SDValue(N, 0))) return false; 474 break; 475 case Expand: 476 if (ExpandedNodes.count(SDValue(N, 0))) return false; 477 break; 478 } 479 480 // Okay, this node has not already been legalized. Check and legalize all 481 // operands. If none lead to Dest, then we can legalize this node. 482 bool OperandsLeadToDest = false; 483 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 484 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 485 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 486 487 if (OperandsLeadToDest) { 488 NodesLeadingTo.insert(N); 489 return true; 490 } 491 492 // Okay, this node looks safe, legalize it and return false. 493 HandleOp(SDValue(N, 0)); 494 return false; 495} 496 497/// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as 498/// appropriate for its type. 499void SelectionDAGLegalize::HandleOp(SDValue Op) { 500 MVT VT = Op.getValueType(); 501 // If the type legalizer was run then we should never see any illegal result 502 // types here except for target constants (the type legalizer does not touch 503 // those) or for build vector used as a mask for a vector shuffle. 504 // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957. 505 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal || 506 Op.getOpcode() == ISD::TargetConstant || 507 Op.getOpcode() == ISD::BUILD_VECTOR) && 508 "Illegal type introduced after type legalization?"); 509 switch (getTypeAction(VT)) { 510 default: assert(0 && "Bad type action!"); 511 case Legal: (void)LegalizeOp(Op); break; 512 case Promote: 513 if (!VT.isVector()) { 514 (void)PromoteOp(Op); 515 break; 516 } 517 else { 518 // See if we can widen otherwise use Expand to either scalarize or split 519 MVT WidenVT = TLI.getWidenVectorType(VT); 520 if (WidenVT != MVT::Other) { 521 (void) WidenVectorOp(Op, WidenVT); 522 break; 523 } 524 // else fall thru to expand since we can't widen the vector 525 } 526 case Expand: 527 if (!VT.isVector()) { 528 // If this is an illegal scalar, expand it into its two component 529 // pieces. 530 SDValue X, Y; 531 if (Op.getOpcode() == ISD::TargetConstant) 532 break; // Allow illegal target nodes. 533 ExpandOp(Op, X, Y); 534 } else if (VT.getVectorNumElements() == 1) { 535 // If this is an illegal single element vector, convert it to a 536 // scalar operation. 537 (void)ScalarizeVectorOp(Op); 538 } else { 539 // This is an illegal multiple element vector. 540 // Split it in half and legalize both parts. 541 SDValue X, Y; 542 SplitVectorOp(Op, X, Y); 543 } 544 break; 545 } 546} 547 548/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 549/// a load from the constant pool. 550static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 551 SelectionDAG &DAG, const TargetLowering &TLI) { 552 bool Extend = false; 553 554 // If a FP immediate is precise when represented as a float and if the 555 // target can do an extending load from float to double, we put it into 556 // the constant pool as a float, even if it's is statically typed as a 557 // double. This shrinks FP constants and canonicalizes them for targets where 558 // an FP extending load is the same cost as a normal load (such as on the x87 559 // fp stack or PPC FP unit). 560 MVT VT = CFP->getValueType(0); 561 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 562 if (!UseCP) { 563 if (VT!=MVT::f64 && VT!=MVT::f32) 564 assert(0 && "Invalid type expansion"); 565 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 566 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 567 } 568 569 MVT OrigVT = VT; 570 MVT SVT = VT; 571 while (SVT != MVT::f32) { 572 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 573 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 574 // Only do this if the target has a native EXTLOAD instruction from 575 // smaller type. 576 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 577 TLI.ShouldShrinkFPConstant(OrigVT)) { 578 const Type *SType = SVT.getTypeForMVT(); 579 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 580 VT = SVT; 581 Extend = true; 582 } 583 } 584 585 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 586 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 587 if (Extend) 588 return DAG.getExtLoad(ISD::EXTLOAD, CFP->getDebugLoc(), 589 OrigVT, DAG.getEntryNode(), 590 CPIdx, PseudoSourceValue::getConstantPool(), 591 0, VT, false, Alignment); 592 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, 593 PseudoSourceValue::getConstantPool(), 0, false, Alignment); 594} 595 596 597/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 598/// operations. 599static 600SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, 601 SelectionDAG &DAG, 602 const TargetLowering &TLI) { 603 DebugLoc dl = Node->getDebugLoc(); 604 MVT VT = Node->getValueType(0); 605 MVT SrcVT = Node->getOperand(1).getValueType(); 606 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 607 "fcopysign expansion only supported for f32 and f64"); 608 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 609 610 // First get the sign bit of second operand. 611 SDValue Mask1 = (SrcVT == MVT::f64) 612 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 613 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 614 Mask1 = DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, Mask1); 615 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, 616 Node->getOperand(1)); 617 SignBit = DAG.getNode(ISD::AND, dl, SrcNVT, SignBit, Mask1); 618 // Shift right or sign-extend it if the two operands have different types. 619 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); 620 if (SizeDiff > 0) { 621 SignBit = DAG.getNode(ISD::SRL, dl, SrcNVT, SignBit, 622 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 623 SignBit = DAG.getNode(ISD::TRUNCATE, dl, NVT, SignBit); 624 } else if (SizeDiff < 0) { 625 SignBit = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, SignBit); 626 SignBit = DAG.getNode(ISD::SHL, dl, NVT, SignBit, 627 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy())); 628 } 629 630 // Clear the sign bit of first operand. 631 SDValue Mask2 = (VT == MVT::f64) 632 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 633 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 634 Mask2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask2); 635 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 636 Result = DAG.getNode(ISD::AND, dl, NVT, Result, Mask2); 637 638 // Or the value with the sign bit. 639 Result = DAG.getNode(ISD::OR, dl, NVT, Result, SignBit); 640 return Result; 641} 642 643/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 644static 645SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 646 const TargetLowering &TLI) { 647 SDValue Chain = ST->getChain(); 648 SDValue Ptr = ST->getBasePtr(); 649 SDValue Val = ST->getValue(); 650 MVT VT = Val.getValueType(); 651 int Alignment = ST->getAlignment(); 652 int SVOffset = ST->getSrcValueOffset(); 653 DebugLoc dl = ST->getDebugLoc(); 654 if (ST->getMemoryVT().isFloatingPoint() || 655 ST->getMemoryVT().isVector()) { 656 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits()); 657 if (TLI.isTypeLegal(intVT)) { 658 // Expand to a bitconvert of the value to the integer type of the 659 // same size, then a (misaligned) int store. 660 // FIXME: Does not handle truncating floating point stores! 661 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 662 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 663 SVOffset, ST->isVolatile(), Alignment); 664 } else { 665 // Do a (aligned) store to a stack slot, then copy from the stack slot 666 // to the final destination using (unaligned) integer loads and stores. 667 MVT StoredVT = ST->getMemoryVT(); 668 MVT RegVT = 669 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits())); 670 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 671 unsigned RegBytes = RegVT.getSizeInBits() / 8; 672 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 673 674 // Make sure the stack slot is also aligned for the register type. 675 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 676 677 // Perform the original store, only redirected to the stack slot. 678 SDValue Store = DAG.getTruncStore(Chain, dl, 679 Val, StackPtr, NULL, 0,StoredVT); 680 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 681 SmallVector<SDValue, 8> Stores; 682 unsigned Offset = 0; 683 684 // Do all but one copies using the full register width. 685 for (unsigned i = 1; i < NumRegs; i++) { 686 // Load one integer register's worth from the stack slot. 687 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0); 688 // Store it to the final location. Remember the store. 689 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 690 ST->getSrcValue(), SVOffset + Offset, 691 ST->isVolatile(), 692 MinAlign(ST->getAlignment(), Offset))); 693 // Increment the pointers. 694 Offset += RegBytes; 695 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 696 Increment); 697 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 698 } 699 700 // The last store may be partial. Do a truncating store. On big-endian 701 // machines this requires an extending load from the stack slot to ensure 702 // that the bits are in the right place. 703 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset)); 704 705 // Load from the stack slot. 706 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 707 NULL, 0, MemVT); 708 709 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 710 ST->getSrcValue(), SVOffset + Offset, 711 MemVT, ST->isVolatile(), 712 MinAlign(ST->getAlignment(), Offset))); 713 // The order of the stores doesn't matter - say it with a TokenFactor. 714 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 715 Stores.size()); 716 } 717 } 718 assert(ST->getMemoryVT().isInteger() && 719 !ST->getMemoryVT().isVector() && 720 "Unaligned store of unknown type."); 721 // Get the half-size VT 722 MVT NewStoredVT = 723 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 724 int NumBits = NewStoredVT.getSizeInBits(); 725 int IncrementSize = NumBits / 8; 726 727 // Divide the stored value in two parts. 728 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 729 SDValue Lo = Val; 730 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 731 732 // Store the two parts 733 SDValue Store1, Store2; 734 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 735 ST->getSrcValue(), SVOffset, NewStoredVT, 736 ST->isVolatile(), Alignment); 737 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 738 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 739 Alignment = MinAlign(Alignment, IncrementSize); 740 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 741 ST->getSrcValue(), SVOffset + IncrementSize, 742 NewStoredVT, ST->isVolatile(), Alignment); 743 744 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 745} 746 747/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 748static 749SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 750 const TargetLowering &TLI) { 751 int SVOffset = LD->getSrcValueOffset(); 752 SDValue Chain = LD->getChain(); 753 SDValue Ptr = LD->getBasePtr(); 754 MVT VT = LD->getValueType(0); 755 MVT LoadedVT = LD->getMemoryVT(); 756 DebugLoc dl = LD->getDebugLoc(); 757 if (VT.isFloatingPoint() || VT.isVector()) { 758 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits()); 759 if (TLI.isTypeLegal(intVT)) { 760 // Expand to a (misaligned) integer load of the same size, 761 // then bitconvert to floating point or vector. 762 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 763 SVOffset, LD->isVolatile(), 764 LD->getAlignment()); 765 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 766 if (VT.isFloatingPoint() && LoadedVT != VT) 767 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 768 769 SDValue Ops[] = { Result, Chain }; 770 return DAG.getMergeValues(Ops, 2, dl); 771 } else { 772 // Copy the value to a (aligned) stack slot using (unaligned) integer 773 // loads and stores, then do a (aligned) load from the stack slot. 774 MVT RegVT = TLI.getRegisterType(intVT); 775 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 776 unsigned RegBytes = RegVT.getSizeInBits() / 8; 777 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 778 779 // Make sure the stack slot is also aligned for the register type. 780 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 781 782 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 783 SmallVector<SDValue, 8> Stores; 784 SDValue StackPtr = StackBase; 785 unsigned Offset = 0; 786 787 // Do all but one copies using the full register width. 788 for (unsigned i = 1; i < NumRegs; i++) { 789 // Load one integer register's worth from the original location. 790 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 791 SVOffset + Offset, LD->isVolatile(), 792 MinAlign(LD->getAlignment(), Offset)); 793 // Follow the load with a store to the stack slot. Remember the store. 794 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 795 NULL, 0)); 796 // Increment the pointers. 797 Offset += RegBytes; 798 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 799 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 800 Increment); 801 } 802 803 // The last copy may be partial. Do an extending load. 804 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset)); 805 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 806 LD->getSrcValue(), SVOffset + Offset, 807 MemVT, LD->isVolatile(), 808 MinAlign(LD->getAlignment(), Offset)); 809 // Follow the load with a store to the stack slot. Remember the store. 810 // On big-endian machines this requires a truncating store to ensure 811 // that the bits end up in the right place. 812 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 813 NULL, 0, MemVT)); 814 815 // The order of the stores doesn't matter - say it with a TokenFactor. 816 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 817 Stores.size()); 818 819 // Finally, perform the original load only redirected to the stack slot. 820 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 821 NULL, 0, LoadedVT); 822 823 // Callers expect a MERGE_VALUES node. 824 SDValue Ops[] = { Load, TF }; 825 return DAG.getMergeValues(Ops, 2, dl); 826 } 827 } 828 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 829 "Unaligned load of unsupported type."); 830 831 // Compute the new VT that is half the size of the old one. This is an 832 // integer MVT. 833 unsigned NumBits = LoadedVT.getSizeInBits(); 834 MVT NewLoadedVT; 835 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 836 NumBits >>= 1; 837 838 unsigned Alignment = LD->getAlignment(); 839 unsigned IncrementSize = NumBits / 8; 840 ISD::LoadExtType HiExtType = LD->getExtensionType(); 841 842 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 843 if (HiExtType == ISD::NON_EXTLOAD) 844 HiExtType = ISD::ZEXTLOAD; 845 846 // Load the value in two parts 847 SDValue Lo, Hi; 848 if (TLI.isLittleEndian()) { 849 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 850 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 851 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 852 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 853 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 854 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 855 MinAlign(Alignment, IncrementSize)); 856 } else { 857 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 858 SVOffset, NewLoadedVT,LD->isVolatile(), Alignment); 859 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 860 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 861 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 862 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 863 MinAlign(Alignment, IncrementSize)); 864 } 865 866 // aggregate the two parts 867 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 868 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 869 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 870 871 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 872 Hi.getValue(1)); 873 874 SDValue Ops[] = { Result, TF }; 875 return DAG.getMergeValues(Ops, 2, dl); 876} 877 878/// UnrollVectorOp - We know that the given vector has a legal type, however 879/// the operation it performs is not legal and is an operation that we have 880/// no way of lowering. "Unroll" the vector, splitting out the scalars and 881/// operating on each element individually. 882SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) { 883 MVT VT = Op.getValueType(); 884 assert(isTypeLegal(VT) && 885 "Caller should expand or promote operands that are not legal!"); 886 assert(Op.getNode()->getNumValues() == 1 && 887 "Can't unroll a vector with multiple results!"); 888 unsigned NE = VT.getVectorNumElements(); 889 MVT EltVT = VT.getVectorElementType(); 890 DebugLoc dl = Op.getNode()->getDebugLoc(); 891 892 SmallVector<SDValue, 8> Scalars; 893 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 894 for (unsigned i = 0; i != NE; ++i) { 895 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 896 SDValue Operand = Op.getOperand(j); 897 MVT OperandVT = Operand.getValueType(); 898 if (OperandVT.isVector()) { 899 // A vector operand; extract a single element. 900 MVT OperandEltVT = OperandVT.getVectorElementType(); 901 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 902 OperandEltVT, 903 Operand, 904 DAG.getConstant(i, MVT::i32)); 905 } else { 906 // A scalar operand; just use it as is. 907 Operands[j] = Operand; 908 } 909 } 910 911 switch (Op.getOpcode()) { 912 default: 913 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, 914 &Operands[0], Operands.size())); 915 break; 916 case ISD::SHL: 917 case ISD::SRA: 918 case ISD::SRL: 919 case ISD::ROTL: 920 case ISD::ROTR: 921 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0], 922 DAG.getShiftAmountOperand(Operands[1]))); 923 break; 924 } 925 } 926 927 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Scalars[0], Scalars.size()); 928} 929 930/// GetFPLibCall - Return the right libcall for the given floating point type. 931static RTLIB::Libcall GetFPLibCall(MVT VT, 932 RTLIB::Libcall Call_F32, 933 RTLIB::Libcall Call_F64, 934 RTLIB::Libcall Call_F80, 935 RTLIB::Libcall Call_PPCF128) { 936 return 937 VT == MVT::f32 ? Call_F32 : 938 VT == MVT::f64 ? Call_F64 : 939 VT == MVT::f80 ? Call_F80 : 940 VT == MVT::ppcf128 ? Call_PPCF128 : 941 RTLIB::UNKNOWN_LIBCALL; 942} 943 944/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 945/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 946/// is necessary to spill the vector being inserted into to memory, perform 947/// the insert there, and then read the result back. 948SDValue SelectionDAGLegalize:: 949PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 950 DebugLoc dl) { 951 SDValue Tmp1 = Vec; 952 SDValue Tmp2 = Val; 953 SDValue Tmp3 = Idx; 954 955 // If the target doesn't support this, we have to spill the input vector 956 // to a temporary stack slot, update the element, then reload it. This is 957 // badness. We could also load the value into a vector register (either 958 // with a "move to register" or "extload into register" instruction, then 959 // permute it into place, if the idx is a constant and if the idx is 960 // supported by the target. 961 MVT VT = Tmp1.getValueType(); 962 MVT EltVT = VT.getVectorElementType(); 963 MVT IdxVT = Tmp3.getValueType(); 964 MVT PtrVT = TLI.getPointerTy(); 965 SDValue StackPtr = DAG.CreateStackTemporary(VT); 966 967 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 968 969 // Store the vector. 970 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 971 PseudoSourceValue::getFixedStack(SPFI), 0); 972 973 // Truncate or zero extend offset to target pointer type. 974 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 975 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 976 // Add the offset to the index. 977 unsigned EltSize = EltVT.getSizeInBits()/8; 978 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 979 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 980 // Store the scalar value. 981 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 982 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); 983 // Load the updated vector. 984 return DAG.getLoad(VT, dl, Ch, StackPtr, 985 PseudoSourceValue::getFixedStack(SPFI), 0); 986} 987 988 989/// LegalizeOp - We know that the specified value has a legal type, and 990/// that its operands are legal. Now ensure that the operation itself 991/// is legal, recursively ensuring that the operands' operations remain 992/// legal. 993SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 994 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 995 return Op; 996 997 assert(isTypeLegal(Op.getValueType()) && 998 "Caller should expand or promote operands that are not legal!"); 999 SDNode *Node = Op.getNode(); 1000 DebugLoc dl = Node->getDebugLoc(); 1001 1002 // If this operation defines any values that cannot be represented in a 1003 // register on this target, make sure to expand or promote them. 1004 if (Node->getNumValues() > 1) { 1005 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1006 if (getTypeAction(Node->getValueType(i)) != Legal) { 1007 HandleOp(Op.getValue(i)); 1008 assert(LegalizedNodes.count(Op) && 1009 "Handling didn't add legal operands!"); 1010 return LegalizedNodes[Op]; 1011 } 1012 } 1013 1014 // Note that LegalizeOp may be reentered even from single-use nodes, which 1015 // means that we always must cache transformed nodes. 1016 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1017 if (I != LegalizedNodes.end()) return I->second; 1018 1019 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 1020 SDValue Result = Op; 1021 bool isCustom = false; 1022 1023 switch (Node->getOpcode()) { 1024 case ISD::FrameIndex: 1025 case ISD::EntryToken: 1026 case ISD::Register: 1027 case ISD::BasicBlock: 1028 case ISD::TargetFrameIndex: 1029 case ISD::TargetJumpTable: 1030 case ISD::TargetConstant: 1031 case ISD::TargetConstantFP: 1032 case ISD::TargetConstantPool: 1033 case ISD::TargetGlobalAddress: 1034 case ISD::TargetGlobalTLSAddress: 1035 case ISD::TargetExternalSymbol: 1036 case ISD::VALUETYPE: 1037 case ISD::SRCVALUE: 1038 case ISD::MEMOPERAND: 1039 case ISD::CONDCODE: 1040 case ISD::ARG_FLAGS: 1041 // Primitives must all be legal. 1042 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 1043 "This must be legal!"); 1044 break; 1045 default: 1046 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 1047 // If this is a target node, legalize it by legalizing the operands then 1048 // passing it through. 1049 SmallVector<SDValue, 8> Ops; 1050 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1051 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1052 1053 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 1054 1055 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1056 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 1057 return Result.getValue(Op.getResNo()); 1058 } 1059 // Otherwise this is an unhandled builtin node. splat. 1060#ifndef NDEBUG 1061 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 1062#endif 1063 assert(0 && "Do not know how to legalize this operator!"); 1064 abort(); 1065 case ISD::GLOBAL_OFFSET_TABLE: 1066 case ISD::GlobalAddress: 1067 case ISD::GlobalTLSAddress: 1068 case ISD::ExternalSymbol: 1069 case ISD::ConstantPool: 1070 case ISD::JumpTable: // Nothing to do. 1071 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1072 default: assert(0 && "This action is not supported yet!"); 1073 case TargetLowering::Custom: 1074 Tmp1 = TLI.LowerOperation(Op, DAG); 1075 if (Tmp1.getNode()) Result = Tmp1; 1076 // FALLTHROUGH if the target doesn't want to lower this op after all. 1077 case TargetLowering::Legal: 1078 break; 1079 } 1080 break; 1081 case ISD::FRAMEADDR: 1082 case ISD::RETURNADDR: 1083 // The only option for these nodes is to custom lower them. If the target 1084 // does not custom lower them, then return zero. 1085 Tmp1 = TLI.LowerOperation(Op, DAG); 1086 if (Tmp1.getNode()) 1087 Result = Tmp1; 1088 else 1089 Result = DAG.getConstant(0, TLI.getPointerTy()); 1090 break; 1091 case ISD::FRAME_TO_ARGS_OFFSET: { 1092 MVT VT = Node->getValueType(0); 1093 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1094 default: assert(0 && "This action is not supported yet!"); 1095 case TargetLowering::Custom: 1096 Result = TLI.LowerOperation(Op, DAG); 1097 if (Result.getNode()) break; 1098 // Fall Thru 1099 case TargetLowering::Legal: 1100 Result = DAG.getConstant(0, VT); 1101 break; 1102 } 1103 } 1104 break; 1105 case ISD::EXCEPTIONADDR: { 1106 Tmp1 = LegalizeOp(Node->getOperand(0)); 1107 MVT VT = Node->getValueType(0); 1108 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1109 default: assert(0 && "This action is not supported yet!"); 1110 case TargetLowering::Expand: { 1111 unsigned Reg = TLI.getExceptionAddressRegister(); 1112 Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT); 1113 } 1114 break; 1115 case TargetLowering::Custom: 1116 Result = TLI.LowerOperation(Op, DAG); 1117 if (Result.getNode()) break; 1118 // Fall Thru 1119 case TargetLowering::Legal: { 1120 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 1121 Result = DAG.getMergeValues(Ops, 2, dl); 1122 break; 1123 } 1124 } 1125 } 1126 if (Result.getNode()->getNumValues() == 1) break; 1127 1128 assert(Result.getNode()->getNumValues() == 2 && 1129 "Cannot return more than two values!"); 1130 1131 // Since we produced two values, make sure to remember that we 1132 // legalized both of them. 1133 Tmp1 = LegalizeOp(Result); 1134 Tmp2 = LegalizeOp(Result.getValue(1)); 1135 AddLegalizedOperand(Op.getValue(0), Tmp1); 1136 AddLegalizedOperand(Op.getValue(1), Tmp2); 1137 return Op.getResNo() ? Tmp2 : Tmp1; 1138 case ISD::EHSELECTION: { 1139 Tmp1 = LegalizeOp(Node->getOperand(0)); 1140 Tmp2 = LegalizeOp(Node->getOperand(1)); 1141 MVT VT = Node->getValueType(0); 1142 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1143 default: assert(0 && "This action is not supported yet!"); 1144 case TargetLowering::Expand: { 1145 unsigned Reg = TLI.getExceptionSelectorRegister(); 1146 Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT); 1147 } 1148 break; 1149 case TargetLowering::Custom: 1150 Result = TLI.LowerOperation(Op, DAG); 1151 if (Result.getNode()) break; 1152 // Fall Thru 1153 case TargetLowering::Legal: { 1154 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 1155 Result = DAG.getMergeValues(Ops, 2, dl); 1156 break; 1157 } 1158 } 1159 } 1160 if (Result.getNode()->getNumValues() == 1) break; 1161 1162 assert(Result.getNode()->getNumValues() == 2 && 1163 "Cannot return more than two values!"); 1164 1165 // Since we produced two values, make sure to remember that we 1166 // legalized both of them. 1167 Tmp1 = LegalizeOp(Result); 1168 Tmp2 = LegalizeOp(Result.getValue(1)); 1169 AddLegalizedOperand(Op.getValue(0), Tmp1); 1170 AddLegalizedOperand(Op.getValue(1), Tmp2); 1171 return Op.getResNo() ? Tmp2 : Tmp1; 1172 case ISD::EH_RETURN: { 1173 MVT VT = Node->getValueType(0); 1174 // The only "good" option for this node is to custom lower it. 1175 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1176 default: assert(0 && "This action is not supported at all!"); 1177 case TargetLowering::Custom: 1178 Result = TLI.LowerOperation(Op, DAG); 1179 if (Result.getNode()) break; 1180 // Fall Thru 1181 case TargetLowering::Legal: 1182 // Target does not know, how to lower this, lower to noop 1183 Result = LegalizeOp(Node->getOperand(0)); 1184 break; 1185 } 1186 } 1187 break; 1188 case ISD::AssertSext: 1189 case ISD::AssertZext: 1190 Tmp1 = LegalizeOp(Node->getOperand(0)); 1191 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1192 break; 1193 case ISD::MERGE_VALUES: 1194 // Legalize eliminates MERGE_VALUES nodes. 1195 Result = Node->getOperand(Op.getResNo()); 1196 break; 1197 case ISD::CopyFromReg: 1198 Tmp1 = LegalizeOp(Node->getOperand(0)); 1199 Result = Op.getValue(0); 1200 if (Node->getNumValues() == 2) { 1201 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1202 } else { 1203 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 1204 if (Node->getNumOperands() == 3) { 1205 Tmp2 = LegalizeOp(Node->getOperand(2)); 1206 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1207 } else { 1208 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1209 } 1210 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 1211 } 1212 // Since CopyFromReg produces two values, make sure to remember that we 1213 // legalized both of them. 1214 AddLegalizedOperand(Op.getValue(0), Result); 1215 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1216 return Result.getValue(Op.getResNo()); 1217 case ISD::UNDEF: { 1218 MVT VT = Op.getValueType(); 1219 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 1220 default: assert(0 && "This action is not supported yet!"); 1221 case TargetLowering::Expand: 1222 if (VT.isInteger()) 1223 Result = DAG.getConstant(0, VT); 1224 else if (VT.isFloatingPoint()) 1225 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), 1226 VT); 1227 else 1228 assert(0 && "Unknown value type!"); 1229 break; 1230 case TargetLowering::Legal: 1231 break; 1232 } 1233 break; 1234 } 1235 1236 case ISD::INTRINSIC_W_CHAIN: 1237 case ISD::INTRINSIC_WO_CHAIN: 1238 case ISD::INTRINSIC_VOID: { 1239 SmallVector<SDValue, 8> Ops; 1240 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1241 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1242 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1243 1244 // Allow the target to custom lower its intrinsics if it wants to. 1245 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1246 TargetLowering::Custom) { 1247 Tmp3 = TLI.LowerOperation(Result, DAG); 1248 if (Tmp3.getNode()) Result = Tmp3; 1249 } 1250 1251 if (Result.getNode()->getNumValues() == 1) break; 1252 1253 // Must have return value and chain result. 1254 assert(Result.getNode()->getNumValues() == 2 && 1255 "Cannot return more than two values!"); 1256 1257 // Since loads produce two values, make sure to remember that we 1258 // legalized both of them. 1259 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1260 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1261 return Result.getValue(Op.getResNo()); 1262 } 1263 1264 case ISD::DBG_STOPPOINT: 1265 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!"); 1266 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1267 1268 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) { 1269 case TargetLowering::Promote: 1270 default: assert(0 && "This action is not supported yet!"); 1271 case TargetLowering::Expand: { 1272 DwarfWriter *DW = DAG.getDwarfWriter(); 1273 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC, 1274 MVT::Other); 1275 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other); 1276 1277 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 1278 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit()); 1279 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) { 1280 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit())); 1281 unsigned SrcFile = DW->RecordSource(CU.getDirectory(), 1282 CU.getFilename()); 1283 1284 unsigned Line = DSP->getLine(); 1285 unsigned Col = DSP->getColumn(); 1286 1287 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but 1288 // it won't hurt anything. 1289 if (useDEBUG_LOC) { 1290 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32), 1291 DAG.getConstant(Col, MVT::i32), 1292 DAG.getConstant(SrcFile, MVT::i32) }; 1293 Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4); 1294 } else { 1295 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); 1296 Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID); 1297 } 1298 } else { 1299 Result = Tmp1; // chain 1300 } 1301 break; 1302 } 1303 case TargetLowering::Legal: { 1304 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1305 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1306 break; 1307 1308 SmallVector<SDValue, 8> Ops; 1309 Ops.push_back(Tmp1); 1310 if (Action == Legal) { 1311 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1312 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1313 } else { 1314 // Otherwise promote them. 1315 Ops.push_back(PromoteOp(Node->getOperand(1))); 1316 Ops.push_back(PromoteOp(Node->getOperand(2))); 1317 } 1318 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1319 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1320 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1321 break; 1322 } 1323 } 1324 break; 1325 1326 case ISD::DECLARE: 1327 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1328 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1329 default: assert(0 && "This action is not supported yet!"); 1330 case TargetLowering::Legal: 1331 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1332 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1333 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1334 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1335 break; 1336 case TargetLowering::Expand: 1337 Result = LegalizeOp(Node->getOperand(0)); 1338 break; 1339 } 1340 break; 1341 1342 case ISD::DEBUG_LOC: 1343 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1344 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1345 default: assert(0 && "This action is not supported yet!"); 1346 case TargetLowering::Legal: { 1347 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1348 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1349 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1350 break; 1351 if (Action == Legal) { 1352 Tmp2 = Node->getOperand(1); 1353 Tmp3 = Node->getOperand(2); 1354 Tmp4 = Node->getOperand(3); 1355 } else { 1356 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1357 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1358 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1359 } 1360 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1361 break; 1362 } 1363 } 1364 break; 1365 1366 case ISD::DBG_LABEL: 1367 case ISD::EH_LABEL: 1368 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!"); 1369 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1370 default: assert(0 && "This action is not supported yet!"); 1371 case TargetLowering::Legal: 1372 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1373 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1374 break; 1375 case TargetLowering::Expand: 1376 Result = LegalizeOp(Node->getOperand(0)); 1377 break; 1378 } 1379 break; 1380 1381 case ISD::PREFETCH: 1382 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1383 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1384 default: assert(0 && "This action is not supported yet!"); 1385 case TargetLowering::Legal: 1386 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1387 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1388 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1389 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1390 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1391 break; 1392 case TargetLowering::Expand: 1393 // It's a noop. 1394 Result = LegalizeOp(Node->getOperand(0)); 1395 break; 1396 } 1397 break; 1398 1399 case ISD::MEMBARRIER: { 1400 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1401 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1402 default: assert(0 && "This action is not supported yet!"); 1403 case TargetLowering::Legal: { 1404 SDValue Ops[6]; 1405 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1406 for (int x = 1; x < 6; ++x) { 1407 Ops[x] = Node->getOperand(x); 1408 if (!isTypeLegal(Ops[x].getValueType())) 1409 Ops[x] = PromoteOp(Ops[x]); 1410 } 1411 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1412 break; 1413 } 1414 case TargetLowering::Expand: 1415 //There is no libgcc call for this op 1416 Result = Node->getOperand(0); // Noop 1417 break; 1418 } 1419 break; 1420 } 1421 1422 case ISD::ATOMIC_CMP_SWAP: { 1423 unsigned int num_operands = 4; 1424 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1425 SDValue Ops[4]; 1426 for (unsigned int x = 0; x < num_operands; ++x) 1427 Ops[x] = LegalizeOp(Node->getOperand(x)); 1428 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1429 1430 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1431 default: assert(0 && "This action is not supported yet!"); 1432 case TargetLowering::Custom: 1433 Result = TLI.LowerOperation(Result, DAG); 1434 break; 1435 case TargetLowering::Legal: 1436 break; 1437 } 1438 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1439 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1440 return Result.getValue(Op.getResNo()); 1441 } 1442 case ISD::ATOMIC_LOAD_ADD: 1443 case ISD::ATOMIC_LOAD_SUB: 1444 case ISD::ATOMIC_LOAD_AND: 1445 case ISD::ATOMIC_LOAD_OR: 1446 case ISD::ATOMIC_LOAD_XOR: 1447 case ISD::ATOMIC_LOAD_NAND: 1448 case ISD::ATOMIC_LOAD_MIN: 1449 case ISD::ATOMIC_LOAD_MAX: 1450 case ISD::ATOMIC_LOAD_UMIN: 1451 case ISD::ATOMIC_LOAD_UMAX: 1452 case ISD::ATOMIC_SWAP: { 1453 unsigned int num_operands = 3; 1454 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1455 SDValue Ops[3]; 1456 for (unsigned int x = 0; x < num_operands; ++x) 1457 Ops[x] = LegalizeOp(Node->getOperand(x)); 1458 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1459 1460 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1461 default: assert(0 && "This action is not supported yet!"); 1462 case TargetLowering::Custom: 1463 Result = TLI.LowerOperation(Result, DAG); 1464 break; 1465 case TargetLowering::Legal: 1466 break; 1467 } 1468 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1469 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1470 return Result.getValue(Op.getResNo()); 1471 } 1472 case ISD::Constant: { 1473 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1474 unsigned opAction = 1475 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1476 1477 // We know we don't need to expand constants here, constants only have one 1478 // value and we check that it is fine above. 1479 1480 if (opAction == TargetLowering::Custom) { 1481 Tmp1 = TLI.LowerOperation(Result, DAG); 1482 if (Tmp1.getNode()) 1483 Result = Tmp1; 1484 } 1485 break; 1486 } 1487 case ISD::ConstantFP: { 1488 // Spill FP immediates to the constant pool if the target cannot directly 1489 // codegen them. Targets often have some immediate values that can be 1490 // efficiently generated into an FP register without a load. We explicitly 1491 // leave these constants as ConstantFP nodes for the target to deal with. 1492 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1493 1494 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1495 default: assert(0 && "This action is not supported yet!"); 1496 case TargetLowering::Legal: 1497 break; 1498 case TargetLowering::Custom: 1499 Tmp3 = TLI.LowerOperation(Result, DAG); 1500 if (Tmp3.getNode()) { 1501 Result = Tmp3; 1502 break; 1503 } 1504 // FALLTHROUGH 1505 case TargetLowering::Expand: { 1506 // Check to see if this FP immediate is already legal. 1507 bool isLegal = false; 1508 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1509 E = TLI.legal_fpimm_end(); I != E; ++I) { 1510 if (CFP->isExactlyValue(*I)) { 1511 isLegal = true; 1512 break; 1513 } 1514 } 1515 // If this is a legal constant, turn it into a TargetConstantFP node. 1516 if (isLegal) 1517 break; 1518 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1519 } 1520 } 1521 break; 1522 } 1523 case ISD::TokenFactor: 1524 if (Node->getNumOperands() == 2) { 1525 Tmp1 = LegalizeOp(Node->getOperand(0)); 1526 Tmp2 = LegalizeOp(Node->getOperand(1)); 1527 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1528 } else if (Node->getNumOperands() == 3) { 1529 Tmp1 = LegalizeOp(Node->getOperand(0)); 1530 Tmp2 = LegalizeOp(Node->getOperand(1)); 1531 Tmp3 = LegalizeOp(Node->getOperand(2)); 1532 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1533 } else { 1534 SmallVector<SDValue, 8> Ops; 1535 // Legalize the operands. 1536 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1537 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1538 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1539 } 1540 break; 1541 1542 case ISD::FORMAL_ARGUMENTS: 1543 case ISD::CALL: 1544 // The only option for this is to custom lower it. 1545 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1546 assert(Tmp3.getNode() && "Target didn't custom lower this node!"); 1547 // A call within a calling sequence must be legalized to something 1548 // other than the normal CALLSEQ_END. Violating this gets Legalize 1549 // into an infinite loop. 1550 assert ((!IsLegalizingCall || 1551 Node->getOpcode() != ISD::CALL || 1552 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) && 1553 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1554 1555 // The number of incoming and outgoing values should match; unless the final 1556 // outgoing value is a flag. 1557 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() || 1558 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 && 1559 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) == 1560 MVT::Flag)) && 1561 "Lowering call/formal_arguments produced unexpected # results!"); 1562 1563 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1564 // remember that we legalized all of them, so it doesn't get relegalized. 1565 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) { 1566 if (Tmp3.getNode()->getValueType(i) == MVT::Flag) 1567 continue; 1568 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1569 if (Op.getResNo() == i) 1570 Tmp2 = Tmp1; 1571 AddLegalizedOperand(SDValue(Node, i), Tmp1); 1572 } 1573 return Tmp2; 1574 case ISD::EXTRACT_SUBREG: { 1575 Tmp1 = LegalizeOp(Node->getOperand(0)); 1576 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1577 assert(idx && "Operand must be a constant"); 1578 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); 1579 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1580 } 1581 break; 1582 case ISD::INSERT_SUBREG: { 1583 Tmp1 = LegalizeOp(Node->getOperand(0)); 1584 Tmp2 = LegalizeOp(Node->getOperand(1)); 1585 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1586 assert(idx && "Operand must be a constant"); 1587 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); 1588 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1589 } 1590 break; 1591 case ISD::BUILD_VECTOR: 1592 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1593 default: assert(0 && "This action is not supported yet!"); 1594 case TargetLowering::Custom: 1595 Tmp3 = TLI.LowerOperation(Result, DAG); 1596 if (Tmp3.getNode()) { 1597 Result = Tmp3; 1598 break; 1599 } 1600 // FALLTHROUGH 1601 case TargetLowering::Expand: 1602 Result = ExpandBUILD_VECTOR(Result.getNode()); 1603 break; 1604 } 1605 break; 1606 case ISD::INSERT_VECTOR_ELT: 1607 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1608 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1609 1610 // The type of the value to insert may not be legal, even though the vector 1611 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1612 // here. 1613 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1614 default: assert(0 && "Cannot expand insert element operand"); 1615 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1616 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1617 case Expand: 1618 // FIXME: An alternative would be to check to see if the target is not 1619 // going to custom lower this operation, we could bitcast to half elt 1620 // width and perform two inserts at that width, if that is legal. 1621 Tmp2 = Node->getOperand(1); 1622 break; 1623 } 1624 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1625 1626 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1627 Node->getValueType(0))) { 1628 default: assert(0 && "This action is not supported yet!"); 1629 case TargetLowering::Legal: 1630 break; 1631 case TargetLowering::Custom: 1632 Tmp4 = TLI.LowerOperation(Result, DAG); 1633 if (Tmp4.getNode()) { 1634 Result = Tmp4; 1635 break; 1636 } 1637 // FALLTHROUGH 1638 case TargetLowering::Promote: 1639 // Fall thru for vector case 1640 case TargetLowering::Expand: { 1641 // If the insert index is a constant, codegen this as a scalar_to_vector, 1642 // then a shuffle that inserts it into the right position in the vector. 1643 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1644 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1645 // match the element type of the vector being created. 1646 if (Tmp2.getValueType() == 1647 Op.getValueType().getVectorElementType()) { 1648 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 1649 Tmp1.getValueType(), Tmp2); 1650 1651 unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); 1652 MVT ShufMaskVT = 1653 MVT::getIntVectorWithNumElements(NumElts); 1654 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType(); 1655 1656 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1657 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1658 // elt 0 of the RHS. 1659 SmallVector<SDValue, 8> ShufOps; 1660 for (unsigned i = 0; i != NumElts; ++i) { 1661 if (i != InsertPos->getZExtValue()) 1662 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1663 else 1664 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1665 } 1666 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, ShufMaskVT, 1667 &ShufOps[0], ShufOps.size()); 1668 1669 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Tmp1.getValueType(), 1670 Tmp1, ScVec, ShufMask); 1671 Result = LegalizeOp(Result); 1672 break; 1673 } 1674 } 1675 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3, dl); 1676 break; 1677 } 1678 } 1679 break; 1680 case ISD::SCALAR_TO_VECTOR: 1681 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1682 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1683 break; 1684 } 1685 1686 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1687 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1688 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1689 Node->getValueType(0))) { 1690 default: assert(0 && "This action is not supported yet!"); 1691 case TargetLowering::Legal: 1692 break; 1693 case TargetLowering::Custom: 1694 Tmp3 = TLI.LowerOperation(Result, DAG); 1695 if (Tmp3.getNode()) { 1696 Result = Tmp3; 1697 break; 1698 } 1699 // FALLTHROUGH 1700 case TargetLowering::Expand: 1701 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1702 break; 1703 } 1704 break; 1705 case ISD::VECTOR_SHUFFLE: 1706 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1707 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1708 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1709 1710 // Allow targets to custom lower the SHUFFLEs they support. 1711 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1712 default: assert(0 && "Unknown operation action!"); 1713 case TargetLowering::Legal: 1714 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1715 "vector shuffle should not be created if not legal!"); 1716 break; 1717 case TargetLowering::Custom: 1718 Tmp3 = TLI.LowerOperation(Result, DAG); 1719 if (Tmp3.getNode()) { 1720 Result = Tmp3; 1721 break; 1722 } 1723 // FALLTHROUGH 1724 case TargetLowering::Expand: { 1725 MVT VT = Node->getValueType(0); 1726 MVT EltVT = VT.getVectorElementType(); 1727 MVT PtrVT = TLI.getPointerTy(); 1728 SDValue Mask = Node->getOperand(2); 1729 unsigned NumElems = Mask.getNumOperands(); 1730 SmallVector<SDValue,8> Ops; 1731 for (unsigned i = 0; i != NumElems; ++i) { 1732 SDValue Arg = Mask.getOperand(i); 1733 if (Arg.getOpcode() == ISD::UNDEF) { 1734 Ops.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT)); 1735 } else { 1736 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1737 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue(); 1738 if (Idx < NumElems) 1739 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1, 1740 DAG.getConstant(Idx, PtrVT))); 1741 else 1742 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2, 1743 DAG.getConstant(Idx - NumElems, PtrVT))); 1744 } 1745 } 1746 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 1747 break; 1748 } 1749 case TargetLowering::Promote: { 1750 // Change base type to a different vector type. 1751 MVT OVT = Node->getValueType(0); 1752 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1753 1754 // Cast the two input vectors. 1755 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1); 1756 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2); 1757 1758 // Convert the shuffle mask to the right # elements. 1759 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1760 assert(Tmp3.getNode() && "Shuffle not legal?"); 1761 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NVT, Tmp1, Tmp2, Tmp3); 1762 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result); 1763 break; 1764 } 1765 } 1766 break; 1767 1768 case ISD::EXTRACT_VECTOR_ELT: 1769 Tmp1 = Node->getOperand(0); 1770 Tmp2 = LegalizeOp(Node->getOperand(1)); 1771 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1772 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1773 break; 1774 1775 case ISD::EXTRACT_SUBVECTOR: 1776 Tmp1 = Node->getOperand(0); 1777 Tmp2 = LegalizeOp(Node->getOperand(1)); 1778 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1779 Result = ExpandEXTRACT_SUBVECTOR(Result); 1780 break; 1781 1782 case ISD::CONCAT_VECTORS: { 1783 // Use extract/insert/build vector for now. We might try to be 1784 // more clever later. 1785 MVT PtrVT = TLI.getPointerTy(); 1786 SmallVector<SDValue, 8> Ops; 1787 unsigned NumOperands = Node->getNumOperands(); 1788 for (unsigned i=0; i < NumOperands; ++i) { 1789 SDValue SubOp = Node->getOperand(i); 1790 MVT VVT = SubOp.getNode()->getValueType(0); 1791 MVT EltVT = VVT.getVectorElementType(); 1792 unsigned NumSubElem = VVT.getVectorNumElements(); 1793 for (unsigned j=0; j < NumSubElem; ++j) { 1794 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, 1795 DAG.getConstant(j, PtrVT))); 1796 } 1797 } 1798 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), 1799 &Ops[0], Ops.size())); 1800 } 1801 1802 case ISD::CALLSEQ_START: { 1803 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1804 1805 // Recursively Legalize all of the inputs of the call end that do not lead 1806 // to this call start. This ensures that any libcalls that need be inserted 1807 // are inserted *before* the CALLSEQ_START. 1808 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1809 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1810 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1811 NodesLeadingTo); 1812 } 1813 1814 // Now that we legalized all of the inputs (which may have inserted 1815 // libcalls) create the new CALLSEQ_START node. 1816 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1817 1818 // Merge in the last call, to ensure that this call start after the last 1819 // call ended. 1820 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1821 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1822 Tmp1, LastCALLSEQ_END); 1823 Tmp1 = LegalizeOp(Tmp1); 1824 } 1825 1826 // Do not try to legalize the target-specific arguments (#1+). 1827 if (Tmp1 != Node->getOperand(0)) { 1828 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1829 Ops[0] = Tmp1; 1830 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1831 } 1832 1833 // Remember that the CALLSEQ_START is legalized. 1834 AddLegalizedOperand(Op.getValue(0), Result); 1835 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1836 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1837 1838 // Now that the callseq_start and all of the non-call nodes above this call 1839 // sequence have been legalized, legalize the call itself. During this 1840 // process, no libcalls can/will be inserted, guaranteeing that no calls 1841 // can overlap. 1842 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1843 // Note that we are selecting this call! 1844 LastCALLSEQ_END = SDValue(CallEnd, 0); 1845 IsLegalizingCall = true; 1846 1847 // Legalize the call, starting from the CALLSEQ_END. 1848 LegalizeOp(LastCALLSEQ_END); 1849 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1850 return Result; 1851 } 1852 case ISD::CALLSEQ_END: 1853 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1854 // will cause this node to be legalized as well as handling libcalls right. 1855 if (LastCALLSEQ_END.getNode() != Node) { 1856 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1857 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1858 assert(I != LegalizedNodes.end() && 1859 "Legalizing the call start should have legalized this node!"); 1860 return I->second; 1861 } 1862 1863 // Otherwise, the call start has been legalized and everything is going 1864 // according to plan. Just legalize ourselves normally here. 1865 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1866 // Do not try to legalize the target-specific arguments (#1+), except for 1867 // an optional flag input. 1868 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1869 if (Tmp1 != Node->getOperand(0)) { 1870 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1871 Ops[0] = Tmp1; 1872 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1873 } 1874 } else { 1875 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1876 if (Tmp1 != Node->getOperand(0) || 1877 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1878 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1879 Ops[0] = Tmp1; 1880 Ops.back() = Tmp2; 1881 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1882 } 1883 } 1884 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1885 // This finishes up call legalization. 1886 IsLegalizingCall = false; 1887 1888 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1889 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1890 if (Node->getNumValues() == 2) 1891 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1892 return Result.getValue(Op.getResNo()); 1893 case ISD::DYNAMIC_STACKALLOC: { 1894 MVT VT = Node->getValueType(0); 1895 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1896 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1897 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1898 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1899 1900 Tmp1 = Result.getValue(0); 1901 Tmp2 = Result.getValue(1); 1902 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1903 default: assert(0 && "This action is not supported yet!"); 1904 case TargetLowering::Expand: { 1905 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1906 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1907 " not tell us which reg is the stack pointer!"); 1908 SDValue Chain = Tmp1.getOperand(0); 1909 1910 // Chain the dynamic stack allocation so that it doesn't modify the stack 1911 // pointer when other instructions are using the stack. 1912 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1913 1914 SDValue Size = Tmp2.getOperand(1); 1915 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1916 Chain = SP.getValue(1); 1917 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1918 unsigned StackAlign = 1919 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1920 if (Align > StackAlign) 1921 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1922 DAG.getConstant(-(uint64_t)Align, VT)); 1923 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1924 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1925 1926 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1927 DAG.getIntPtrConstant(0, true), SDValue()); 1928 1929 Tmp1 = LegalizeOp(Tmp1); 1930 Tmp2 = LegalizeOp(Tmp2); 1931 break; 1932 } 1933 case TargetLowering::Custom: 1934 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1935 if (Tmp3.getNode()) { 1936 Tmp1 = LegalizeOp(Tmp3); 1937 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1938 } 1939 break; 1940 case TargetLowering::Legal: 1941 break; 1942 } 1943 // Since this op produce two values, make sure to remember that we 1944 // legalized both of them. 1945 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1946 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1947 return Op.getResNo() ? Tmp2 : Tmp1; 1948 } 1949 case ISD::INLINEASM: { 1950 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1951 bool Changed = false; 1952 // Legalize all of the operands of the inline asm, in case they are nodes 1953 // that need to be expanded or something. Note we skip the asm string and 1954 // all of the TargetConstant flags. 1955 SDValue Op = LegalizeOp(Ops[0]); 1956 Changed = Op != Ops[0]; 1957 Ops[0] = Op; 1958 1959 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1960 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1961 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3; 1962 for (++i; NumVals; ++i, --NumVals) { 1963 SDValue Op = LegalizeOp(Ops[i]); 1964 if (Op != Ops[i]) { 1965 Changed = true; 1966 Ops[i] = Op; 1967 } 1968 } 1969 } 1970 1971 if (HasInFlag) { 1972 Op = LegalizeOp(Ops.back()); 1973 Changed |= Op != Ops.back(); 1974 Ops.back() = Op; 1975 } 1976 1977 if (Changed) 1978 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1979 1980 // INLINE asm returns a chain and flag, make sure to add both to the map. 1981 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1982 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1983 return Result.getValue(Op.getResNo()); 1984 } 1985 case ISD::BR: 1986 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1987 // Ensure that libcalls are emitted before a branch. 1988 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 1989 Tmp1 = LegalizeOp(Tmp1); 1990 LastCALLSEQ_END = DAG.getEntryNode(); 1991 1992 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1993 break; 1994 case ISD::BRIND: 1995 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1996 // Ensure that libcalls are emitted before a branch. 1997 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 1998 Tmp1 = LegalizeOp(Tmp1); 1999 LastCALLSEQ_END = DAG.getEntryNode(); 2000 2001 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2002 default: assert(0 && "Indirect target must be legal type (pointer)!"); 2003 case Legal: 2004 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 2005 break; 2006 } 2007 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2008 break; 2009 case ISD::BR_JT: 2010 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2011 // Ensure that libcalls are emitted before a branch. 2012 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 2013 Tmp1 = LegalizeOp(Tmp1); 2014 LastCALLSEQ_END = DAG.getEntryNode(); 2015 2016 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 2017 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2018 2019 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 2020 default: assert(0 && "This action is not supported yet!"); 2021 case TargetLowering::Legal: break; 2022 case TargetLowering::Custom: 2023 Tmp1 = TLI.LowerOperation(Result, DAG); 2024 if (Tmp1.getNode()) Result = Tmp1; 2025 break; 2026 case TargetLowering::Expand: { 2027 SDValue Chain = Result.getOperand(0); 2028 SDValue Table = Result.getOperand(1); 2029 SDValue Index = Result.getOperand(2); 2030 2031 MVT PTy = TLI.getPointerTy(); 2032 MachineFunction &MF = DAG.getMachineFunction(); 2033 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 2034 Index= DAG.getNode(ISD::MUL, dl, PTy, 2035 Index, DAG.getConstant(EntrySize, PTy)); 2036 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2037 2038 MVT MemVT = MVT::getIntegerVT(EntrySize * 8); 2039 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 2040 PseudoSourceValue::getJumpTable(), 0, MemVT); 2041 Addr = LD; 2042 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2043 // For PIC, the sequence is: 2044 // BRIND(load(Jumptable + index) + RelocBase) 2045 // RelocBase can be JumpTable, GOT or some sort of global base. 2046 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 2047 TLI.getPICJumpTableRelocBase(Table, DAG)); 2048 } 2049 Result = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 2050 } 2051 } 2052 break; 2053 case ISD::BRCOND: 2054 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2055 // Ensure that libcalls are emitted before a return. 2056 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 2057 Tmp1 = LegalizeOp(Tmp1); 2058 LastCALLSEQ_END = DAG.getEntryNode(); 2059 2060 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2061 case Expand: assert(0 && "It's impossible to expand bools"); 2062 case Legal: 2063 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 2064 break; 2065 case Promote: { 2066 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 2067 2068 // The top bits of the promoted condition are not necessarily zero, ensure 2069 // that the value is properly zero extended. 2070 unsigned BitWidth = Tmp2.getValueSizeInBits(); 2071 if (!DAG.MaskedValueIsZero(Tmp2, 2072 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2073 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, MVT::i1); 2074 break; 2075 } 2076 } 2077 2078 // Basic block destination (Op#2) is always legal. 2079 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2080 2081 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 2082 default: assert(0 && "This action is not supported yet!"); 2083 case TargetLowering::Legal: break; 2084 case TargetLowering::Custom: 2085 Tmp1 = TLI.LowerOperation(Result, DAG); 2086 if (Tmp1.getNode()) Result = Tmp1; 2087 break; 2088 case TargetLowering::Expand: 2089 // Expand brcond's setcc into its constituent parts and create a BR_CC 2090 // Node. 2091 if (Tmp2.getOpcode() == ISD::SETCC) { 2092 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 2093 Tmp1, Tmp2.getOperand(2), 2094 Tmp2.getOperand(0), Tmp2.getOperand(1), 2095 Node->getOperand(2)); 2096 } else { 2097 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 2098 DAG.getCondCode(ISD::SETNE), Tmp2, 2099 DAG.getConstant(0, Tmp2.getValueType()), 2100 Node->getOperand(2)); 2101 } 2102 break; 2103 } 2104 break; 2105 case ISD::BR_CC: 2106 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2107 // Ensure that libcalls are emitted before a branch. 2108 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 2109 Tmp1 = LegalizeOp(Tmp1); 2110 Tmp2 = Node->getOperand(2); // LHS 2111 Tmp3 = Node->getOperand(3); // RHS 2112 Tmp4 = Node->getOperand(1); // CC 2113 2114 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()), 2115 Tmp2, Tmp3, Tmp4, dl); 2116 LastCALLSEQ_END = DAG.getEntryNode(); 2117 2118 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 2119 // the LHS is a legal SETCC itself. In this case, we need to compare 2120 // the result against zero to select between true and false values. 2121 if (Tmp3.getNode() == 0) { 2122 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 2123 Tmp4 = DAG.getCondCode(ISD::SETNE); 2124 } 2125 2126 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 2127 Node->getOperand(4)); 2128 2129 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 2130 default: assert(0 && "Unexpected action for BR_CC!"); 2131 case TargetLowering::Legal: break; 2132 case TargetLowering::Custom: 2133 Tmp4 = TLI.LowerOperation(Result, DAG); 2134 if (Tmp4.getNode()) Result = Tmp4; 2135 break; 2136 } 2137 break; 2138 case ISD::LOAD: { 2139 LoadSDNode *LD = cast<LoadSDNode>(Node); 2140 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 2141 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 2142 2143 ISD::LoadExtType ExtType = LD->getExtensionType(); 2144 if (ExtType == ISD::NON_EXTLOAD) { 2145 MVT VT = Node->getValueType(0); 2146 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2147 Tmp3 = Result.getValue(0); 2148 Tmp4 = Result.getValue(1); 2149 2150 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 2151 default: assert(0 && "This action is not supported yet!"); 2152 case TargetLowering::Legal: 2153 // If this is an unaligned load and the target doesn't support it, 2154 // expand it. 2155 if (!TLI.allowsUnalignedMemoryAccesses()) { 2156 unsigned ABIAlignment = TLI.getTargetData()-> 2157 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2158 if (LD->getAlignment() < ABIAlignment){ 2159 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 2160 TLI); 2161 Tmp3 = Result.getOperand(0); 2162 Tmp4 = Result.getOperand(1); 2163 Tmp3 = LegalizeOp(Tmp3); 2164 Tmp4 = LegalizeOp(Tmp4); 2165 } 2166 } 2167 break; 2168 case TargetLowering::Custom: 2169 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 2170 if (Tmp1.getNode()) { 2171 Tmp3 = LegalizeOp(Tmp1); 2172 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 2173 } 2174 break; 2175 case TargetLowering::Promote: { 2176 // Only promote a load of vector type to another. 2177 assert(VT.isVector() && "Cannot promote this load!"); 2178 // Change base type to a different vector type. 2179 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 2180 2181 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 2182 LD->getSrcValueOffset(), 2183 LD->isVolatile(), LD->getAlignment()); 2184 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 2185 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 2186 break; 2187 } 2188 } 2189 // Since loads produce two values, make sure to remember that we 2190 // legalized both of them. 2191 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 2192 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 2193 return Op.getResNo() ? Tmp4 : Tmp3; 2194 } else { 2195 MVT SrcVT = LD->getMemoryVT(); 2196 unsigned SrcWidth = SrcVT.getSizeInBits(); 2197 int SVOffset = LD->getSrcValueOffset(); 2198 unsigned Alignment = LD->getAlignment(); 2199 bool isVolatile = LD->isVolatile(); 2200 2201 if (SrcWidth != SrcVT.getStoreSizeInBits() && 2202 // Some targets pretend to have an i1 loading operation, and actually 2203 // load an i8. This trick is correct for ZEXTLOAD because the top 7 2204 // bits are guaranteed to be zero; it helps the optimizers understand 2205 // that these bits are zero. It is also useful for EXTLOAD, since it 2206 // tells the optimizers that those bits are undefined. It would be 2207 // nice to have an effective generic way of getting these benefits... 2208 // Until such a way is found, don't insist on promoting i1 here. 2209 (SrcVT != MVT::i1 || 2210 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 2211 // Promote to a byte-sized load if not loading an integral number of 2212 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 2213 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 2214 MVT NVT = MVT::getIntegerVT(NewWidth); 2215 SDValue Ch; 2216 2217 // The extra bits are guaranteed to be zero, since we stored them that 2218 // way. A zext load from NVT thus automatically gives zext from SrcVT. 2219 2220 ISD::LoadExtType NewExtType = 2221 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 2222 2223 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 2224 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 2225 NVT, isVolatile, Alignment); 2226 2227 Ch = Result.getValue(1); // The chain. 2228 2229 if (ExtType == ISD::SEXTLOAD) 2230 // Having the top bits zero doesn't help when sign extending. 2231 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 2232 Result.getValueType(), 2233 Result, DAG.getValueType(SrcVT)); 2234 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 2235 // All the top bits are guaranteed to be zero - inform the optimizers. 2236 Result = DAG.getNode(ISD::AssertZext, dl, 2237 Result.getValueType(), Result, 2238 DAG.getValueType(SrcVT)); 2239 2240 Tmp1 = LegalizeOp(Result); 2241 Tmp2 = LegalizeOp(Ch); 2242 } else if (SrcWidth & (SrcWidth - 1)) { 2243 // If not loading a power-of-2 number of bits, expand as two loads. 2244 assert(SrcVT.isExtended() && !SrcVT.isVector() && 2245 "Unsupported extload!"); 2246 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 2247 assert(RoundWidth < SrcWidth); 2248 unsigned ExtraWidth = SrcWidth - RoundWidth; 2249 assert(ExtraWidth < RoundWidth); 2250 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2251 "Load size not an integral number of bytes!"); 2252 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2253 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2254 SDValue Lo, Hi, Ch; 2255 unsigned IncrementSize; 2256 2257 if (TLI.isLittleEndian()) { 2258 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2259 // Load the bottom RoundWidth bits. 2260 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 2261 Node->getValueType(0), Tmp1, Tmp2, 2262 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2263 Alignment); 2264 2265 // Load the remaining ExtraWidth bits. 2266 IncrementSize = RoundWidth / 8; 2267 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 2268 DAG.getIntPtrConstant(IncrementSize)); 2269 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 2270 LD->getSrcValue(), SVOffset + IncrementSize, 2271 ExtraVT, isVolatile, 2272 MinAlign(Alignment, IncrementSize)); 2273 2274 // Build a factor node to remember that this load is independent of the 2275 // other one. 2276 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 2277 Hi.getValue(1)); 2278 2279 // Move the top bits to the right place. 2280 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 2281 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2282 2283 // Join the hi and lo parts. 2284 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 2285 } else { 2286 // Big endian - avoid unaligned loads. 2287 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2288 // Load the top RoundWidth bits. 2289 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 2290 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2291 Alignment); 2292 2293 // Load the remaining ExtraWidth bits. 2294 IncrementSize = RoundWidth / 8; 2295 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 2296 DAG.getIntPtrConstant(IncrementSize)); 2297 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 2298 Node->getValueType(0), Tmp1, Tmp2, 2299 LD->getSrcValue(), SVOffset + IncrementSize, 2300 ExtraVT, isVolatile, 2301 MinAlign(Alignment, IncrementSize)); 2302 2303 // Build a factor node to remember that this load is independent of the 2304 // other one. 2305 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 2306 Hi.getValue(1)); 2307 2308 // Move the top bits to the right place. 2309 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 2310 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2311 2312 // Join the hi and lo parts. 2313 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 2314 } 2315 2316 Tmp1 = LegalizeOp(Result); 2317 Tmp2 = LegalizeOp(Ch); 2318 } else { 2319 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 2320 default: assert(0 && "This action is not supported yet!"); 2321 case TargetLowering::Custom: 2322 isCustom = true; 2323 // FALLTHROUGH 2324 case TargetLowering::Legal: 2325 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2326 Tmp1 = Result.getValue(0); 2327 Tmp2 = Result.getValue(1); 2328 2329 if (isCustom) { 2330 Tmp3 = TLI.LowerOperation(Result, DAG); 2331 if (Tmp3.getNode()) { 2332 Tmp1 = LegalizeOp(Tmp3); 2333 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2334 } 2335 } else { 2336 // If this is an unaligned load and the target doesn't support it, 2337 // expand it. 2338 if (!TLI.allowsUnalignedMemoryAccesses()) { 2339 unsigned ABIAlignment = TLI.getTargetData()-> 2340 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2341 if (LD->getAlignment() < ABIAlignment){ 2342 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 2343 TLI); 2344 Tmp1 = Result.getOperand(0); 2345 Tmp2 = Result.getOperand(1); 2346 Tmp1 = LegalizeOp(Tmp1); 2347 Tmp2 = LegalizeOp(Tmp2); 2348 } 2349 } 2350 } 2351 break; 2352 case TargetLowering::Expand: 2353 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2354 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2355 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 2356 LD->getSrcValueOffset(), 2357 LD->isVolatile(), LD->getAlignment()); 2358 Result = DAG.getNode(ISD::FP_EXTEND, dl, 2359 Node->getValueType(0), Load); 2360 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2361 Tmp2 = LegalizeOp(Load.getValue(1)); 2362 break; 2363 } 2364 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2365 // Turn the unsupported load into an EXTLOAD followed by an explicit 2366 // zero/sign extend inreg. 2367 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 2368 Tmp1, Tmp2, LD->getSrcValue(), 2369 LD->getSrcValueOffset(), SrcVT, 2370 LD->isVolatile(), LD->getAlignment()); 2371 SDValue ValRes; 2372 if (ExtType == ISD::SEXTLOAD) 2373 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 2374 Result.getValueType(), 2375 Result, DAG.getValueType(SrcVT)); 2376 else 2377 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 2378 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2379 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2380 break; 2381 } 2382 } 2383 2384 // Since loads produce two values, make sure to remember that we legalized 2385 // both of them. 2386 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2387 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2388 return Op.getResNo() ? Tmp2 : Tmp1; 2389 } 2390 } 2391 case ISD::EXTRACT_ELEMENT: { 2392 MVT OpTy = Node->getOperand(0).getValueType(); 2393 switch (getTypeAction(OpTy)) { 2394 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2395 case Legal: 2396 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2397 // 1 -> Hi 2398 Result = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2399 DAG.getConstant(OpTy.getSizeInBits()/2, 2400 TLI.getShiftAmountTy())); 2401 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Result); 2402 } else { 2403 // 0 -> Lo 2404 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2405 Node->getOperand(0)); 2406 } 2407 break; 2408 case Expand: 2409 // Get both the low and high parts. 2410 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2411 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) 2412 Result = Tmp2; // 1 -> Hi 2413 else 2414 Result = Tmp1; // 0 -> Lo 2415 break; 2416 } 2417 break; 2418 } 2419 2420 case ISD::CopyToReg: 2421 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2422 2423 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2424 "Register type must be legal!"); 2425 // Legalize the incoming value (must be a legal type). 2426 Tmp2 = LegalizeOp(Node->getOperand(2)); 2427 if (Node->getNumValues() == 1) { 2428 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2429 } else { 2430 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2431 if (Node->getNumOperands() == 4) { 2432 Tmp3 = LegalizeOp(Node->getOperand(3)); 2433 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2434 Tmp3); 2435 } else { 2436 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2437 } 2438 2439 // Since this produces two values, make sure to remember that we legalized 2440 // both of them. 2441 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 2442 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 2443 return Result; 2444 } 2445 break; 2446 2447 case ISD::RET: 2448 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2449 2450 // Ensure that libcalls are emitted before a return. 2451 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 2452 Tmp1 = LegalizeOp(Tmp1); 2453 LastCALLSEQ_END = DAG.getEntryNode(); 2454 2455 switch (Node->getNumOperands()) { 2456 case 3: // ret val 2457 Tmp2 = Node->getOperand(1); 2458 Tmp3 = Node->getOperand(2); // Signness 2459 switch (getTypeAction(Tmp2.getValueType())) { 2460 case Legal: 2461 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2462 break; 2463 case Expand: 2464 if (!Tmp2.getValueType().isVector()) { 2465 SDValue Lo, Hi; 2466 ExpandOp(Tmp2, Lo, Hi); 2467 2468 // Big endian systems want the hi reg first. 2469 if (TLI.isBigEndian()) 2470 std::swap(Lo, Hi); 2471 2472 if (Hi.getNode()) 2473 Result = DAG.getNode(ISD::RET, dl, MVT::Other, 2474 Tmp1, Lo, Tmp3, Hi,Tmp3); 2475 else 2476 Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3); 2477 Result = LegalizeOp(Result); 2478 } else { 2479 SDNode *InVal = Tmp2.getNode(); 2480 int InIx = Tmp2.getResNo(); 2481 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 2482 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 2483 2484 // Figure out if there is a simple type corresponding to this Vector 2485 // type. If so, convert to the vector type. 2486 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2487 if (TLI.isTypeLegal(TVT)) { 2488 // Turn this into a return of the vector type. 2489 Tmp2 = LegalizeOp(Tmp2); 2490 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2491 } else if (NumElems == 1) { 2492 // Turn this into a return of the scalar type. 2493 Tmp2 = ScalarizeVectorOp(Tmp2); 2494 Tmp2 = LegalizeOp(Tmp2); 2495 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2496 2497 // FIXME: Returns of gcc generic vectors smaller than a legal type 2498 // should be returned in integer registers! 2499 2500 // The scalarized value type may not be legal, e.g. it might require 2501 // promotion or expansion. Relegalize the return. 2502 Result = LegalizeOp(Result); 2503 } else { 2504 // FIXME: Returns of gcc generic vectors larger than a legal vector 2505 // type should be returned by reference! 2506 SDValue Lo, Hi; 2507 SplitVectorOp(Tmp2, Lo, Hi); 2508 Result = DAG.getNode(ISD::RET, dl, MVT::Other, 2509 Tmp1, Lo, Tmp3, Hi,Tmp3); 2510 Result = LegalizeOp(Result); 2511 } 2512 } 2513 break; 2514 case Promote: 2515 Tmp2 = PromoteOp(Node->getOperand(1)); 2516 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2517 Result = LegalizeOp(Result); 2518 break; 2519 } 2520 break; 2521 case 1: // ret void 2522 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2523 break; 2524 default: { // ret <values> 2525 SmallVector<SDValue, 8> NewValues; 2526 NewValues.push_back(Tmp1); 2527 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2528 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2529 case Legal: 2530 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2531 NewValues.push_back(Node->getOperand(i+1)); 2532 break; 2533 case Expand: { 2534 SDValue Lo, Hi; 2535 assert(!Node->getOperand(i).getValueType().isExtended() && 2536 "FIXME: TODO: implement returning non-legal vector types!"); 2537 ExpandOp(Node->getOperand(i), Lo, Hi); 2538 NewValues.push_back(Lo); 2539 NewValues.push_back(Node->getOperand(i+1)); 2540 if (Hi.getNode()) { 2541 NewValues.push_back(Hi); 2542 NewValues.push_back(Node->getOperand(i+1)); 2543 } 2544 break; 2545 } 2546 case Promote: 2547 assert(0 && "Can't promote multiple return value yet!"); 2548 } 2549 2550 if (NewValues.size() == Node->getNumOperands()) 2551 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2552 else 2553 Result = DAG.getNode(ISD::RET, dl, MVT::Other, 2554 &NewValues[0], NewValues.size()); 2555 break; 2556 } 2557 } 2558 2559 if (Result.getOpcode() == ISD::RET) { 2560 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2561 default: assert(0 && "This action is not supported yet!"); 2562 case TargetLowering::Legal: break; 2563 case TargetLowering::Custom: 2564 Tmp1 = TLI.LowerOperation(Result, DAG); 2565 if (Tmp1.getNode()) Result = Tmp1; 2566 break; 2567 } 2568 } 2569 break; 2570 case ISD::STORE: { 2571 StoreSDNode *ST = cast<StoreSDNode>(Node); 2572 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2573 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2574 int SVOffset = ST->getSrcValueOffset(); 2575 unsigned Alignment = ST->getAlignment(); 2576 bool isVolatile = ST->isVolatile(); 2577 2578 if (!ST->isTruncatingStore()) { 2579 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2580 // FIXME: We shouldn't do this for TargetConstantFP's. 2581 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2582 // to phase ordering between legalized code and the dag combiner. This 2583 // probably means that we need to integrate dag combiner and legalizer 2584 // together. 2585 // We generally can't do this one for long doubles. 2586 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2587 if (CFP->getValueType(0) == MVT::f32 && 2588 getTypeAction(MVT::i32) == Legal) { 2589 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2590 bitcastToAPInt().zextOrTrunc(32), 2591 MVT::i32); 2592 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2593 SVOffset, isVolatile, Alignment); 2594 break; 2595 } else if (CFP->getValueType(0) == MVT::f64) { 2596 // If this target supports 64-bit registers, do a single 64-bit store. 2597 if (getTypeAction(MVT::i64) == Legal) { 2598 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 2599 zextOrTrunc(64), MVT::i64); 2600 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2601 SVOffset, isVolatile, Alignment); 2602 break; 2603 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 2604 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2605 // stores. If the target supports neither 32- nor 64-bits, this 2606 // xform is certainly not worth it. 2607 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 2608 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2609 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2610 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2611 2612 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 2613 SVOffset, isVolatile, Alignment); 2614 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 2615 DAG.getIntPtrConstant(4)); 2616 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2617 isVolatile, MinAlign(Alignment, 4U)); 2618 2619 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2620 break; 2621 } 2622 } 2623 } 2624 2625 switch (getTypeAction(ST->getMemoryVT())) { 2626 case Legal: { 2627 Tmp3 = LegalizeOp(ST->getValue()); 2628 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2629 ST->getOffset()); 2630 2631 MVT VT = Tmp3.getValueType(); 2632 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2633 default: assert(0 && "This action is not supported yet!"); 2634 case TargetLowering::Legal: 2635 // If this is an unaligned store and the target doesn't support it, 2636 // expand it. 2637 if (!TLI.allowsUnalignedMemoryAccesses()) { 2638 unsigned ABIAlignment = TLI.getTargetData()-> 2639 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2640 if (ST->getAlignment() < ABIAlignment) 2641 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 2642 TLI); 2643 } 2644 break; 2645 case TargetLowering::Custom: 2646 Tmp1 = TLI.LowerOperation(Result, DAG); 2647 if (Tmp1.getNode()) Result = Tmp1; 2648 break; 2649 case TargetLowering::Promote: 2650 assert(VT.isVector() && "Unknown legal promote case!"); 2651 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 2652 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2653 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 2654 ST->getSrcValue(), SVOffset, isVolatile, 2655 Alignment); 2656 break; 2657 } 2658 break; 2659 } 2660 case Promote: 2661 if (!ST->getMemoryVT().isVector()) { 2662 // Truncate the value and store the result. 2663 Tmp3 = PromoteOp(ST->getValue()); 2664 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2665 SVOffset, ST->getMemoryVT(), 2666 isVolatile, Alignment); 2667 break; 2668 } 2669 // Fall thru to expand for vector 2670 case Expand: { 2671 unsigned IncrementSize = 0; 2672 SDValue Lo, Hi; 2673 2674 // If this is a vector type, then we have to calculate the increment as 2675 // the product of the element size in bytes, and the number of elements 2676 // in the high half of the vector. 2677 if (ST->getValue().getValueType().isVector()) { 2678 SDNode *InVal = ST->getValue().getNode(); 2679 int InIx = ST->getValue().getResNo(); 2680 MVT InVT = InVal->getValueType(InIx); 2681 unsigned NumElems = InVT.getVectorNumElements(); 2682 MVT EVT = InVT.getVectorElementType(); 2683 2684 // Figure out if there is a simple type corresponding to this Vector 2685 // type. If so, convert to the vector type. 2686 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2687 if (TLI.isTypeLegal(TVT)) { 2688 // Turn this into a normal store of the vector type. 2689 Tmp3 = LegalizeOp(ST->getValue()); 2690 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2691 SVOffset, isVolatile, Alignment); 2692 Result = LegalizeOp(Result); 2693 break; 2694 } else if (NumElems == 1) { 2695 // Turn this into a normal store of the scalar type. 2696 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2697 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2698 SVOffset, isVolatile, Alignment); 2699 // The scalarized value type may not be legal, e.g. it might require 2700 // promotion or expansion. Relegalize the scalar store. 2701 Result = LegalizeOp(Result); 2702 break; 2703 } else { 2704 // Check if we have widen this node with another value 2705 std::map<SDValue, SDValue>::iterator I = 2706 WidenNodes.find(ST->getValue()); 2707 if (I != WidenNodes.end()) { 2708 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2); 2709 break; 2710 } 2711 else { 2712 SplitVectorOp(ST->getValue(), Lo, Hi); 2713 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() * 2714 EVT.getSizeInBits()/8; 2715 } 2716 } 2717 } else { 2718 ExpandOp(ST->getValue(), Lo, Hi); 2719 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0; 2720 2721 if (Hi.getNode() && TLI.isBigEndian()) 2722 std::swap(Lo, Hi); 2723 } 2724 2725 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 2726 SVOffset, isVolatile, Alignment); 2727 2728 if (Hi.getNode() == NULL) { 2729 // Must be int <-> float one-to-one expansion. 2730 Result = Lo; 2731 break; 2732 } 2733 2734 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 2735 DAG.getIntPtrConstant(IncrementSize)); 2736 assert(isTypeLegal(Tmp2.getValueType()) && 2737 "Pointers must be legal!"); 2738 SVOffset += IncrementSize; 2739 Alignment = MinAlign(Alignment, IncrementSize); 2740 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 2741 SVOffset, isVolatile, Alignment); 2742 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2743 break; 2744 } // case Expand 2745 } 2746 } else { 2747 switch (getTypeAction(ST->getValue().getValueType())) { 2748 case Legal: 2749 Tmp3 = LegalizeOp(ST->getValue()); 2750 break; 2751 case Promote: 2752 if (!ST->getValue().getValueType().isVector()) { 2753 // We can promote the value, the truncstore will still take care of it. 2754 Tmp3 = PromoteOp(ST->getValue()); 2755 break; 2756 } 2757 // Vector case falls through to expand 2758 case Expand: 2759 // Just store the low part. This may become a non-trunc store, so make 2760 // sure to use getTruncStore, not UpdateNodeOperands below. 2761 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2762 return DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2763 SVOffset, MVT::i8, isVolatile, Alignment); 2764 } 2765 2766 MVT StVT = ST->getMemoryVT(); 2767 unsigned StWidth = StVT.getSizeInBits(); 2768 2769 if (StWidth != StVT.getStoreSizeInBits()) { 2770 // Promote to a byte-sized store with upper bits zero if not 2771 // storing an integral number of bytes. For example, promote 2772 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2773 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 2774 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 2775 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2776 SVOffset, NVT, isVolatile, Alignment); 2777 } else if (StWidth & (StWidth - 1)) { 2778 // If not storing a power-of-2 number of bits, expand as two stores. 2779 assert(StVT.isExtended() && !StVT.isVector() && 2780 "Unsupported truncstore!"); 2781 unsigned RoundWidth = 1 << Log2_32(StWidth); 2782 assert(RoundWidth < StWidth); 2783 unsigned ExtraWidth = StWidth - RoundWidth; 2784 assert(ExtraWidth < RoundWidth); 2785 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2786 "Store size not an integral number of bytes!"); 2787 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2788 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2789 SDValue Lo, Hi; 2790 unsigned IncrementSize; 2791 2792 if (TLI.isLittleEndian()) { 2793 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2794 // Store the bottom RoundWidth bits. 2795 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2796 SVOffset, RoundVT, 2797 isVolatile, Alignment); 2798 2799 // Store the remaining ExtraWidth bits. 2800 IncrementSize = RoundWidth / 8; 2801 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 2802 DAG.getIntPtrConstant(IncrementSize)); 2803 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 2804 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2805 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 2806 SVOffset + IncrementSize, ExtraVT, isVolatile, 2807 MinAlign(Alignment, IncrementSize)); 2808 } else { 2809 // Big endian - avoid unaligned stores. 2810 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2811 // Store the top RoundWidth bits. 2812 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 2813 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2814 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 2815 SVOffset, RoundVT, isVolatile, Alignment); 2816 2817 // Store the remaining ExtraWidth bits. 2818 IncrementSize = RoundWidth / 8; 2819 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 2820 DAG.getIntPtrConstant(IncrementSize)); 2821 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2822 SVOffset + IncrementSize, ExtraVT, isVolatile, 2823 MinAlign(Alignment, IncrementSize)); 2824 } 2825 2826 // The order of the stores doesn't matter. 2827 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2828 } else { 2829 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2830 Tmp2 != ST->getBasePtr()) 2831 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2832 ST->getOffset()); 2833 2834 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2835 default: assert(0 && "This action is not supported yet!"); 2836 case TargetLowering::Legal: 2837 // If this is an unaligned store and the target doesn't support it, 2838 // expand it. 2839 if (!TLI.allowsUnalignedMemoryAccesses()) { 2840 unsigned ABIAlignment = TLI.getTargetData()-> 2841 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2842 if (ST->getAlignment() < ABIAlignment) 2843 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 2844 TLI); 2845 } 2846 break; 2847 case TargetLowering::Custom: 2848 Result = TLI.LowerOperation(Result, DAG); 2849 break; 2850 case Expand: 2851 // TRUNCSTORE:i16 i32 -> STORE i16 2852 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2853 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 2854 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2855 SVOffset, isVolatile, Alignment); 2856 break; 2857 } 2858 } 2859 } 2860 break; 2861 } 2862 case ISD::PCMARKER: 2863 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2864 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2865 break; 2866 case ISD::STACKSAVE: 2867 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2868 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2869 Tmp1 = Result.getValue(0); 2870 Tmp2 = Result.getValue(1); 2871 2872 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2873 default: assert(0 && "This action is not supported yet!"); 2874 case TargetLowering::Legal: break; 2875 case TargetLowering::Custom: 2876 Tmp3 = TLI.LowerOperation(Result, DAG); 2877 if (Tmp3.getNode()) { 2878 Tmp1 = LegalizeOp(Tmp3); 2879 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2880 } 2881 break; 2882 case TargetLowering::Expand: 2883 // Expand to CopyFromReg if the target set 2884 // StackPointerRegisterToSaveRestore. 2885 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2886 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP, 2887 Node->getValueType(0)); 2888 Tmp2 = Tmp1.getValue(1); 2889 } else { 2890 Tmp1 = DAG.getNode(ISD::UNDEF, dl, Node->getValueType(0)); 2891 Tmp2 = Node->getOperand(0); 2892 } 2893 break; 2894 } 2895 2896 // Since stacksave produce two values, make sure to remember that we 2897 // legalized both of them. 2898 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2899 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2900 return Op.getResNo() ? Tmp2 : Tmp1; 2901 2902 case ISD::STACKRESTORE: 2903 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2904 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2905 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2906 2907 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2908 default: assert(0 && "This action is not supported yet!"); 2909 case TargetLowering::Legal: break; 2910 case TargetLowering::Custom: 2911 Tmp1 = TLI.LowerOperation(Result, DAG); 2912 if (Tmp1.getNode()) Result = Tmp1; 2913 break; 2914 case TargetLowering::Expand: 2915 // Expand to CopyToReg if the target set 2916 // StackPointerRegisterToSaveRestore. 2917 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2918 Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2); 2919 } else { 2920 Result = Tmp1; 2921 } 2922 break; 2923 } 2924 break; 2925 2926 case ISD::READCYCLECOUNTER: 2927 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2928 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2929 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2930 Node->getValueType(0))) { 2931 default: assert(0 && "This action is not supported yet!"); 2932 case TargetLowering::Legal: 2933 Tmp1 = Result.getValue(0); 2934 Tmp2 = Result.getValue(1); 2935 break; 2936 case TargetLowering::Custom: 2937 Result = TLI.LowerOperation(Result, DAG); 2938 Tmp1 = LegalizeOp(Result.getValue(0)); 2939 Tmp2 = LegalizeOp(Result.getValue(1)); 2940 break; 2941 } 2942 2943 // Since rdcc produce two values, make sure to remember that we legalized 2944 // both of them. 2945 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2946 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2947 return Result; 2948 2949 case ISD::SELECT: 2950 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2951 case Expand: assert(0 && "It's impossible to expand bools"); 2952 case Legal: 2953 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2954 break; 2955 case Promote: { 2956 assert(!Node->getOperand(0).getValueType().isVector() && "not possible"); 2957 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2958 // Make sure the condition is either zero or one. 2959 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2960 if (!DAG.MaskedValueIsZero(Tmp1, 2961 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2962 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, MVT::i1); 2963 break; 2964 } 2965 } 2966 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2967 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2968 2969 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2970 2971 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2972 default: assert(0 && "This action is not supported yet!"); 2973 case TargetLowering::Legal: break; 2974 case TargetLowering::Custom: { 2975 Tmp1 = TLI.LowerOperation(Result, DAG); 2976 if (Tmp1.getNode()) Result = Tmp1; 2977 break; 2978 } 2979 case TargetLowering::Expand: 2980 if (Tmp1.getOpcode() == ISD::SETCC) { 2981 Result = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 2982 Tmp2, Tmp3, 2983 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2984 } else { 2985 Result = DAG.getSelectCC(dl, Tmp1, 2986 DAG.getConstant(0, Tmp1.getValueType()), 2987 Tmp2, Tmp3, ISD::SETNE); 2988 } 2989 break; 2990 case TargetLowering::Promote: { 2991 MVT NVT = 2992 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2993 unsigned ExtOp, TruncOp; 2994 if (Tmp2.getValueType().isVector()) { 2995 ExtOp = ISD::BIT_CONVERT; 2996 TruncOp = ISD::BIT_CONVERT; 2997 } else if (Tmp2.getValueType().isInteger()) { 2998 ExtOp = ISD::ANY_EXTEND; 2999 TruncOp = ISD::TRUNCATE; 3000 } else { 3001 ExtOp = ISD::FP_EXTEND; 3002 TruncOp = ISD::FP_ROUND; 3003 } 3004 // Promote each of the values to the new type. 3005 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2); 3006 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3); 3007 // Perform the larger operation, then round down. 3008 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2,Tmp3); 3009 if (TruncOp != ISD::FP_ROUND) 3010 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result); 3011 else 3012 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result, 3013 DAG.getIntPtrConstant(0)); 3014 break; 3015 } 3016 } 3017 break; 3018 case ISD::SELECT_CC: { 3019 Tmp1 = Node->getOperand(0); // LHS 3020 Tmp2 = Node->getOperand(1); // RHS 3021 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 3022 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 3023 SDValue CC = Node->getOperand(4); 3024 3025 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), 3026 Tmp1, Tmp2, CC, dl); 3027 3028 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 3029 // the LHS is a legal SETCC itself. In this case, we need to compare 3030 // the result against zero to select between true and false values. 3031 if (Tmp2.getNode() == 0) { 3032 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3033 CC = DAG.getCondCode(ISD::SETNE); 3034 } 3035 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 3036 3037 // Everything is legal, see if we should expand this op or something. 3038 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 3039 default: assert(0 && "This action is not supported yet!"); 3040 case TargetLowering::Legal: break; 3041 case TargetLowering::Custom: 3042 Tmp1 = TLI.LowerOperation(Result, DAG); 3043 if (Tmp1.getNode()) Result = Tmp1; 3044 break; 3045 } 3046 break; 3047 } 3048 case ISD::SETCC: 3049 Tmp1 = Node->getOperand(0); 3050 Tmp2 = Node->getOperand(1); 3051 Tmp3 = Node->getOperand(2); 3052 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 3053 3054 // If we had to Expand the SetCC operands into a SELECT node, then it may 3055 // not always be possible to return a true LHS & RHS. In this case, just 3056 // return the value we legalized, returned in the LHS 3057 if (Tmp2.getNode() == 0) { 3058 Result = Tmp1; 3059 break; 3060 } 3061 3062 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 3063 default: assert(0 && "Cannot handle this action for SETCC yet!"); 3064 case TargetLowering::Custom: 3065 isCustom = true; 3066 // FALLTHROUGH. 3067 case TargetLowering::Legal: 3068 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3069 if (isCustom) { 3070 Tmp4 = TLI.LowerOperation(Result, DAG); 3071 if (Tmp4.getNode()) Result = Tmp4; 3072 } 3073 break; 3074 case TargetLowering::Promote: { 3075 // First step, figure out the appropriate operation to use. 3076 // Allow SETCC to not be supported for all legal data types 3077 // Mostly this targets FP 3078 MVT NewInTy = Node->getOperand(0).getValueType(); 3079 MVT OldVT = NewInTy; OldVT = OldVT; 3080 3081 // Scan for the appropriate larger type to use. 3082 while (1) { 3083 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 3084 3085 assert(NewInTy.isInteger() == OldVT.isInteger() && 3086 "Fell off of the edge of the integer world"); 3087 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 3088 "Fell off of the edge of the floating point world"); 3089 3090 // If the target supports SETCC of this type, use it. 3091 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy)) 3092 break; 3093 } 3094 if (NewInTy.isInteger()) 3095 assert(0 && "Cannot promote Legal Integer SETCC yet"); 3096 else { 3097 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1); 3098 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2); 3099 } 3100 Tmp1 = LegalizeOp(Tmp1); 3101 Tmp2 = LegalizeOp(Tmp2); 3102 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3103 Result = LegalizeOp(Result); 3104 break; 3105 } 3106 case TargetLowering::Expand: 3107 // Expand a setcc node into a select_cc of the same condition, lhs, and 3108 // rhs that selects between const 1 (true) and const 0 (false). 3109 MVT VT = Node->getValueType(0); 3110 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3111 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3112 Tmp3); 3113 break; 3114 } 3115 break; 3116 case ISD::VSETCC: { 3117 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3118 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3119 SDValue CC = Node->getOperand(2); 3120 3121 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC); 3122 3123 // Everything is legal, see if we should expand this op or something. 3124 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) { 3125 default: assert(0 && "This action is not supported yet!"); 3126 case TargetLowering::Legal: break; 3127 case TargetLowering::Custom: 3128 Tmp1 = TLI.LowerOperation(Result, DAG); 3129 if (Tmp1.getNode()) Result = Tmp1; 3130 break; 3131 case TargetLowering::Expand: { 3132 // Unroll into a nasty set of scalar code for now. 3133 MVT VT = Node->getValueType(0); 3134 unsigned NumElems = VT.getVectorNumElements(); 3135 MVT EltVT = VT.getVectorElementType(); 3136 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType(); 3137 SmallVector<SDValue, 8> Ops(NumElems); 3138 for (unsigned i = 0; i < NumElems; ++i) { 3139 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, 3140 Tmp1, DAG.getIntPtrConstant(i)); 3141 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT), 3142 In1, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 3143 TmpEltVT, Tmp2, 3144 DAG.getIntPtrConstant(i)), 3145 CC); 3146 Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], DAG.getConstant( 3147 APInt::getAllOnesValue(EltVT.getSizeInBits()), 3148 EltVT), DAG.getConstant(0, EltVT)); 3149 } 3150 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems); 3151 break; 3152 } 3153 } 3154 break; 3155 } 3156 3157 case ISD::SHL_PARTS: 3158 case ISD::SRA_PARTS: 3159 case ISD::SRL_PARTS: { 3160 SmallVector<SDValue, 8> Ops; 3161 bool Changed = false; 3162 unsigned N = Node->getNumOperands(); 3163 for (unsigned i = 0; i + 1 < N; ++i) { 3164 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3165 Changed |= Ops.back() != Node->getOperand(i); 3166 } 3167 Ops.push_back(LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(N-1)))); 3168 Changed |= Ops.back() != Node->getOperand(N-1); 3169 if (Changed) 3170 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 3171 3172 switch (TLI.getOperationAction(Node->getOpcode(), 3173 Node->getValueType(0))) { 3174 default: assert(0 && "This action is not supported yet!"); 3175 case TargetLowering::Legal: break; 3176 case TargetLowering::Custom: 3177 Tmp1 = TLI.LowerOperation(Result, DAG); 3178 if (Tmp1.getNode()) { 3179 SDValue Tmp2, RetVal(0, 0); 3180 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 3181 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 3182 AddLegalizedOperand(SDValue(Node, i), Tmp2); 3183 if (i == Op.getResNo()) 3184 RetVal = Tmp2; 3185 } 3186 assert(RetVal.getNode() && "Illegal result number"); 3187 return RetVal; 3188 } 3189 break; 3190 } 3191 3192 // Since these produce multiple values, make sure to remember that we 3193 // legalized all of them. 3194 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3195 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i)); 3196 return Result.getValue(Op.getResNo()); 3197 } 3198 3199 // Binary operators 3200 case ISD::ADD: 3201 case ISD::SUB: 3202 case ISD::MUL: 3203 case ISD::MULHS: 3204 case ISD::MULHU: 3205 case ISD::UDIV: 3206 case ISD::SDIV: 3207 case ISD::AND: 3208 case ISD::OR: 3209 case ISD::XOR: 3210 case ISD::SHL: 3211 case ISD::SRL: 3212 case ISD::SRA: 3213 case ISD::FADD: 3214 case ISD::FSUB: 3215 case ISD::FMUL: 3216 case ISD::FDIV: 3217 case ISD::FPOW: 3218 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3219 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3220 3221 if ((Node->getOpcode() == ISD::SHL || 3222 Node->getOpcode() == ISD::SRL || 3223 Node->getOpcode() == ISD::SRA) && 3224 !Node->getValueType(0).isVector()) 3225 Tmp2 = DAG.getShiftAmountOperand(Tmp2); 3226 3227 switch (getTypeAction(Tmp2.getValueType())) { 3228 case Expand: assert(0 && "Not possible"); 3229 case Legal: 3230 Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS. 3231 break; 3232 case Promote: 3233 Tmp2 = PromoteOp(Tmp2); // Promote the RHS. 3234 break; 3235 } 3236 3237 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3238 3239 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3240 default: assert(0 && "BinOp legalize operation not supported"); 3241 case TargetLowering::Legal: break; 3242 case TargetLowering::Custom: 3243 Tmp1 = TLI.LowerOperation(Result, DAG); 3244 if (Tmp1.getNode()) { 3245 Result = Tmp1; 3246 break; 3247 } 3248 // Fall through if the custom lower can't deal with the operation 3249 case TargetLowering::Expand: { 3250 MVT VT = Op.getValueType(); 3251 3252 // See if multiply or divide can be lowered using two-result operations. 3253 SDVTList VTs = DAG.getVTList(VT, VT); 3254 if (Node->getOpcode() == ISD::MUL) { 3255 // We just need the low half of the multiply; try both the signed 3256 // and unsigned forms. If the target supports both SMUL_LOHI and 3257 // UMUL_LOHI, form a preference by checking which forms of plain 3258 // MULH it supports. 3259 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 3260 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 3261 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 3262 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 3263 unsigned OpToUse = 0; 3264 if (HasSMUL_LOHI && !HasMULHS) { 3265 OpToUse = ISD::SMUL_LOHI; 3266 } else if (HasUMUL_LOHI && !HasMULHU) { 3267 OpToUse = ISD::UMUL_LOHI; 3268 } else if (HasSMUL_LOHI) { 3269 OpToUse = ISD::SMUL_LOHI; 3270 } else if (HasUMUL_LOHI) { 3271 OpToUse = ISD::UMUL_LOHI; 3272 } 3273 if (OpToUse) { 3274 Result = SDValue(DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2).getNode(), 3275 0); 3276 break; 3277 } 3278 } 3279 if (Node->getOpcode() == ISD::MULHS && 3280 TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) { 3281 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, 3282 VTs, Tmp1, Tmp2).getNode(), 3283 1); 3284 break; 3285 } 3286 if (Node->getOpcode() == ISD::MULHU && 3287 TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) { 3288 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, 3289 VTs, Tmp1, Tmp2).getNode(), 3290 1); 3291 break; 3292 } 3293 if (Node->getOpcode() == ISD::SDIV && 3294 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) { 3295 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl, 3296 VTs, Tmp1, Tmp2).getNode(), 3297 0); 3298 break; 3299 } 3300 if (Node->getOpcode() == ISD::UDIV && 3301 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) { 3302 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl, 3303 VTs, Tmp1, Tmp2).getNode(), 3304 0); 3305 break; 3306 } 3307 3308 // Check to see if we have a libcall for this operator. 3309 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3310 bool isSigned = false; 3311 switch (Node->getOpcode()) { 3312 case ISD::UDIV: 3313 case ISD::SDIV: 3314 if (VT == MVT::i32) { 3315 LC = Node->getOpcode() == ISD::UDIV 3316 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3317 isSigned = Node->getOpcode() == ISD::SDIV; 3318 } 3319 break; 3320 case ISD::MUL: 3321 if (VT == MVT::i32) 3322 LC = RTLIB::MUL_I32; 3323 else if (VT == MVT::i64) 3324 LC = RTLIB::MUL_I64; 3325 break; 3326 case ISD::FPOW: 3327 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3328 RTLIB::POW_PPCF128); 3329 break; 3330 case ISD::FDIV: 3331 LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80, 3332 RTLIB::DIV_PPCF128); 3333 break; 3334 default: break; 3335 } 3336 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3337 SDValue Dummy; 3338 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3339 break; 3340 } 3341 3342 assert(Node->getValueType(0).isVector() && 3343 "Cannot expand this binary operator!"); 3344 // Expand the operation into a bunch of nasty scalar code. 3345 Result = LegalizeOp(UnrollVectorOp(Op)); 3346 break; 3347 } 3348 case TargetLowering::Promote: { 3349 switch (Node->getOpcode()) { 3350 default: assert(0 && "Do not know how to promote this BinOp!"); 3351 case ISD::AND: 3352 case ISD::OR: 3353 case ISD::XOR: { 3354 MVT OVT = Node->getValueType(0); 3355 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3356 assert(OVT.isVector() && "Cannot promote this BinOp!"); 3357 // Bit convert each of the values to the new type. 3358 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1); 3359 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2); 3360 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3361 // Bit convert the result back the original type. 3362 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result); 3363 break; 3364 } 3365 } 3366 } 3367 } 3368 break; 3369 3370 case ISD::SMUL_LOHI: 3371 case ISD::UMUL_LOHI: 3372 case ISD::SDIVREM: 3373 case ISD::UDIVREM: 3374 // These nodes will only be produced by target-specific lowering, so 3375 // they shouldn't be here if they aren't legal. 3376 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3377 "This must be legal!"); 3378 3379 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3380 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3381 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3382 break; 3383 3384 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3385 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3386 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3387 case Expand: assert(0 && "Not possible"); 3388 case Legal: 3389 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3390 break; 3391 case Promote: 3392 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3393 break; 3394 } 3395 3396 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3397 3398 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3399 default: assert(0 && "Operation not supported"); 3400 case TargetLowering::Custom: 3401 Tmp1 = TLI.LowerOperation(Result, DAG); 3402 if (Tmp1.getNode()) Result = Tmp1; 3403 break; 3404 case TargetLowering::Legal: break; 3405 case TargetLowering::Expand: { 3406 // If this target supports fabs/fneg natively and select is cheap, 3407 // do this efficiently. 3408 if (!TLI.isSelectExpensive() && 3409 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3410 TargetLowering::Legal && 3411 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3412 TargetLowering::Legal) { 3413 // Get the sign bit of the RHS. 3414 MVT IVT = 3415 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3416 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 3417 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(IVT), 3418 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3419 // Get the absolute value of the result. 3420 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 3421 // Select between the nabs and abs value based on the sign bit of 3422 // the input. 3423 Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 3424 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3425 AbsVal), 3426 AbsVal); 3427 Result = LegalizeOp(Result); 3428 break; 3429 } 3430 3431 // Otherwise, do bitwise ops! 3432 MVT NVT = 3433 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3434 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3435 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Result); 3436 Result = LegalizeOp(Result); 3437 break; 3438 } 3439 } 3440 break; 3441 3442 case ISD::ADDC: 3443 case ISD::SUBC: 3444 Tmp1 = LegalizeOp(Node->getOperand(0)); 3445 Tmp2 = LegalizeOp(Node->getOperand(1)); 3446 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3447 Tmp3 = Result.getValue(0); 3448 Tmp4 = Result.getValue(1); 3449 3450 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3451 default: assert(0 && "This action is not supported yet!"); 3452 case TargetLowering::Legal: 3453 break; 3454 case TargetLowering::Custom: 3455 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 3456 if (Tmp1.getNode() != NULL) { 3457 Tmp3 = LegalizeOp(Tmp1); 3458 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 3459 } 3460 break; 3461 } 3462 // Since this produces two values, make sure to remember that we legalized 3463 // both of them. 3464 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 3465 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 3466 return Op.getResNo() ? Tmp4 : Tmp3; 3467 3468 case ISD::ADDE: 3469 case ISD::SUBE: 3470 Tmp1 = LegalizeOp(Node->getOperand(0)); 3471 Tmp2 = LegalizeOp(Node->getOperand(1)); 3472 Tmp3 = LegalizeOp(Node->getOperand(2)); 3473 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3474 Tmp3 = Result.getValue(0); 3475 Tmp4 = Result.getValue(1); 3476 3477 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3478 default: assert(0 && "This action is not supported yet!"); 3479 case TargetLowering::Legal: 3480 break; 3481 case TargetLowering::Custom: 3482 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 3483 if (Tmp1.getNode() != NULL) { 3484 Tmp3 = LegalizeOp(Tmp1); 3485 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 3486 } 3487 break; 3488 } 3489 // Since this produces two values, make sure to remember that we legalized 3490 // both of them. 3491 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 3492 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 3493 return Op.getResNo() ? Tmp4 : Tmp3; 3494 3495 case ISD::BUILD_PAIR: { 3496 MVT PairTy = Node->getValueType(0); 3497 // TODO: handle the case where the Lo and Hi operands are not of legal type 3498 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3499 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3500 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3501 case TargetLowering::Promote: 3502 case TargetLowering::Custom: 3503 assert(0 && "Cannot promote/custom this yet!"); 3504 case TargetLowering::Legal: 3505 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3506 Result = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Tmp1, Tmp2); 3507 break; 3508 case TargetLowering::Expand: 3509 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Tmp1); 3510 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Tmp2); 3511 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 3512 DAG.getConstant(PairTy.getSizeInBits()/2, 3513 TLI.getShiftAmountTy())); 3514 Result = DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2); 3515 break; 3516 } 3517 break; 3518 } 3519 3520 case ISD::UREM: 3521 case ISD::SREM: 3522 case ISD::FREM: 3523 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3524 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3525 3526 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3527 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3528 case TargetLowering::Custom: 3529 isCustom = true; 3530 // FALLTHROUGH 3531 case TargetLowering::Legal: 3532 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3533 if (isCustom) { 3534 Tmp1 = TLI.LowerOperation(Result, DAG); 3535 if (Tmp1.getNode()) Result = Tmp1; 3536 } 3537 break; 3538 case TargetLowering::Expand: { 3539 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3540 bool isSigned = DivOpc == ISD::SDIV; 3541 MVT VT = Node->getValueType(0); 3542 3543 // See if remainder can be lowered using two-result operations. 3544 SDVTList VTs = DAG.getVTList(VT, VT); 3545 if (Node->getOpcode() == ISD::SREM && 3546 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) { 3547 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl, 3548 VTs, Tmp1, Tmp2).getNode(), 1); 3549 break; 3550 } 3551 if (Node->getOpcode() == ISD::UREM && 3552 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) { 3553 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl, 3554 VTs, Tmp1, Tmp2).getNode(), 1); 3555 break; 3556 } 3557 3558 if (VT.isInteger()) { 3559 if (TLI.getOperationAction(DivOpc, VT) == 3560 TargetLowering::Legal) { 3561 // X % Y -> X-X/Y*Y 3562 Result = DAG.getNode(DivOpc, dl, VT, Tmp1, Tmp2); 3563 Result = DAG.getNode(ISD::MUL, dl, VT, Result, Tmp2); 3564 Result = DAG.getNode(ISD::SUB, dl, VT, Tmp1, Result); 3565 } else if (VT.isVector()) { 3566 Result = LegalizeOp(UnrollVectorOp(Op)); 3567 } else { 3568 assert(VT == MVT::i32 && 3569 "Cannot expand this binary operator!"); 3570 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3571 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3572 SDValue Dummy; 3573 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3574 } 3575 } else { 3576 assert(VT.isFloatingPoint() && 3577 "remainder op must have integer or floating-point type"); 3578 if (VT.isVector()) { 3579 Result = LegalizeOp(UnrollVectorOp(Op)); 3580 } else { 3581 // Floating point mod -> fmod libcall. 3582 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3583 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3584 SDValue Dummy; 3585 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3586 } 3587 } 3588 break; 3589 } 3590 } 3591 break; 3592 case ISD::VAARG: { 3593 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3594 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3595 3596 MVT VT = Node->getValueType(0); 3597 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3598 default: assert(0 && "This action is not supported yet!"); 3599 case TargetLowering::Custom: 3600 isCustom = true; 3601 // FALLTHROUGH 3602 case TargetLowering::Legal: 3603 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3604 Result = Result.getValue(0); 3605 Tmp1 = Result.getValue(1); 3606 3607 if (isCustom) { 3608 Tmp2 = TLI.LowerOperation(Result, DAG); 3609 if (Tmp2.getNode()) { 3610 Result = LegalizeOp(Tmp2); 3611 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3612 } 3613 } 3614 break; 3615 case TargetLowering::Expand: { 3616 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3617 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0); 3618 // Increment the pointer, VAList, to the next vaarg 3619 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 3620 DAG.getConstant(TLI.getTargetData()-> 3621 getTypePaddedSize(VT.getTypeForMVT()), 3622 TLI.getPointerTy())); 3623 // Store the incremented VAList to the legalized pointer 3624 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0); 3625 // Load the actual argument out of the pointer VAList 3626 Result = DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0); 3627 Tmp1 = LegalizeOp(Result.getValue(1)); 3628 Result = LegalizeOp(Result); 3629 break; 3630 } 3631 } 3632 // Since VAARG produces two values, make sure to remember that we 3633 // legalized both of them. 3634 AddLegalizedOperand(SDValue(Node, 0), Result); 3635 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 3636 return Op.getResNo() ? Tmp1 : Result; 3637 } 3638 3639 case ISD::VACOPY: 3640 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3641 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3642 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3643 3644 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3645 default: assert(0 && "This action is not supported yet!"); 3646 case TargetLowering::Custom: 3647 isCustom = true; 3648 // FALLTHROUGH 3649 case TargetLowering::Legal: 3650 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3651 Node->getOperand(3), Node->getOperand(4)); 3652 if (isCustom) { 3653 Tmp1 = TLI.LowerOperation(Result, DAG); 3654 if (Tmp1.getNode()) Result = Tmp1; 3655 } 3656 break; 3657 case TargetLowering::Expand: 3658 // This defaults to loading a pointer from the input and storing it to the 3659 // output, returning the chain. 3660 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3661 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3662 Tmp4 = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp3, VS, 0); 3663 Result = DAG.getStore(Tmp4.getValue(1), dl, Tmp4, Tmp2, VD, 0); 3664 break; 3665 } 3666 break; 3667 3668 case ISD::VAEND: 3669 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3670 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3671 3672 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3673 default: assert(0 && "This action is not supported yet!"); 3674 case TargetLowering::Custom: 3675 isCustom = true; 3676 // FALLTHROUGH 3677 case TargetLowering::Legal: 3678 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3679 if (isCustom) { 3680 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3681 if (Tmp1.getNode()) Result = Tmp1; 3682 } 3683 break; 3684 case TargetLowering::Expand: 3685 Result = Tmp1; // Default to a no-op, return the chain 3686 break; 3687 } 3688 break; 3689 3690 case ISD::VASTART: 3691 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3692 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3693 3694 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3695 3696 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3697 default: assert(0 && "This action is not supported yet!"); 3698 case TargetLowering::Legal: break; 3699 case TargetLowering::Custom: 3700 Tmp1 = TLI.LowerOperation(Result, DAG); 3701 if (Tmp1.getNode()) Result = Tmp1; 3702 break; 3703 } 3704 break; 3705 3706 case ISD::ROTL: 3707 case ISD::ROTR: 3708 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3709 Tmp2 = LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(1))); // RHS 3710 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3711 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3712 default: 3713 assert(0 && "ROTL/ROTR legalize operation not supported"); 3714 break; 3715 case TargetLowering::Legal: 3716 break; 3717 case TargetLowering::Custom: 3718 Tmp1 = TLI.LowerOperation(Result, DAG); 3719 if (Tmp1.getNode()) Result = Tmp1; 3720 break; 3721 case TargetLowering::Promote: 3722 assert(0 && "Do not know how to promote ROTL/ROTR"); 3723 break; 3724 case TargetLowering::Expand: 3725 assert(0 && "Do not know how to expand ROTL/ROTR"); 3726 break; 3727 } 3728 break; 3729 3730 case ISD::BSWAP: 3731 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3732 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3733 case TargetLowering::Custom: 3734 assert(0 && "Cannot custom legalize this yet!"); 3735 case TargetLowering::Legal: 3736 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3737 break; 3738 case TargetLowering::Promote: { 3739 MVT OVT = Tmp1.getValueType(); 3740 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3741 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3742 3743 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); 3744 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3745 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3746 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3747 break; 3748 } 3749 case TargetLowering::Expand: 3750 Result = ExpandBSWAP(Tmp1, dl); 3751 break; 3752 } 3753 break; 3754 3755 case ISD::CTPOP: 3756 case ISD::CTTZ: 3757 case ISD::CTLZ: 3758 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3759 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3760 case TargetLowering::Custom: 3761 case TargetLowering::Legal: 3762 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3763 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3764 TargetLowering::Custom) { 3765 Tmp1 = TLI.LowerOperation(Result, DAG); 3766 if (Tmp1.getNode()) { 3767 Result = Tmp1; 3768 } 3769 } 3770 break; 3771 case TargetLowering::Promote: { 3772 MVT OVT = Tmp1.getValueType(); 3773 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3774 3775 // Zero extend the argument. 3776 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); 3777 // Perform the larger operation, then subtract if needed. 3778 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1); 3779 switch (Node->getOpcode()) { 3780 case ISD::CTPOP: 3781 Result = Tmp1; 3782 break; 3783 case ISD::CTTZ: 3784 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3785 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 3786 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3787 ISD::SETEQ); 3788 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3789 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3790 break; 3791 case ISD::CTLZ: 3792 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3793 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3794 DAG.getConstant(NVT.getSizeInBits() - 3795 OVT.getSizeInBits(), NVT)); 3796 break; 3797 } 3798 break; 3799 } 3800 case TargetLowering::Expand: 3801 Result = ExpandBitCount(Node->getOpcode(), Tmp1, dl); 3802 break; 3803 } 3804 break; 3805 3806 // Unary operators 3807 case ISD::FABS: 3808 case ISD::FNEG: 3809 case ISD::FSQRT: 3810 case ISD::FSIN: 3811 case ISD::FCOS: 3812 case ISD::FLOG: 3813 case ISD::FLOG2: 3814 case ISD::FLOG10: 3815 case ISD::FEXP: 3816 case ISD::FEXP2: 3817 case ISD::FTRUNC: 3818 case ISD::FFLOOR: 3819 case ISD::FCEIL: 3820 case ISD::FRINT: 3821 case ISD::FNEARBYINT: 3822 Tmp1 = LegalizeOp(Node->getOperand(0)); 3823 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3824 case TargetLowering::Promote: 3825 case TargetLowering::Custom: 3826 isCustom = true; 3827 // FALLTHROUGH 3828 case TargetLowering::Legal: 3829 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3830 if (isCustom) { 3831 Tmp1 = TLI.LowerOperation(Result, DAG); 3832 if (Tmp1.getNode()) Result = Tmp1; 3833 } 3834 break; 3835 case TargetLowering::Expand: 3836 switch (Node->getOpcode()) { 3837 default: assert(0 && "Unreachable!"); 3838 case ISD::FNEG: 3839 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3840 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3841 Result = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp2, Tmp1); 3842 break; 3843 case ISD::FABS: { 3844 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3845 MVT VT = Node->getValueType(0); 3846 Tmp2 = DAG.getConstantFP(0.0, VT); 3847 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 3848 Tmp1, Tmp2, ISD::SETUGT); 3849 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 3850 Result = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 3851 break; 3852 } 3853 case ISD::FSQRT: 3854 case ISD::FSIN: 3855 case ISD::FCOS: 3856 case ISD::FLOG: 3857 case ISD::FLOG2: 3858 case ISD::FLOG10: 3859 case ISD::FEXP: 3860 case ISD::FEXP2: 3861 case ISD::FTRUNC: 3862 case ISD::FFLOOR: 3863 case ISD::FCEIL: 3864 case ISD::FRINT: 3865 case ISD::FNEARBYINT: { 3866 MVT VT = Node->getValueType(0); 3867 3868 // Expand unsupported unary vector operators by unrolling them. 3869 if (VT.isVector()) { 3870 Result = LegalizeOp(UnrollVectorOp(Op)); 3871 break; 3872 } 3873 3874 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3875 switch(Node->getOpcode()) { 3876 case ISD::FSQRT: 3877 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3878 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3879 break; 3880 case ISD::FSIN: 3881 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3882 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3883 break; 3884 case ISD::FCOS: 3885 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3886 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3887 break; 3888 case ISD::FLOG: 3889 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64, 3890 RTLIB::LOG_F80, RTLIB::LOG_PPCF128); 3891 break; 3892 case ISD::FLOG2: 3893 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 3894 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128); 3895 break; 3896 case ISD::FLOG10: 3897 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 3898 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128); 3899 break; 3900 case ISD::FEXP: 3901 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64, 3902 RTLIB::EXP_F80, RTLIB::EXP_PPCF128); 3903 break; 3904 case ISD::FEXP2: 3905 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 3906 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128); 3907 break; 3908 case ISD::FTRUNC: 3909 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 3910 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 3911 break; 3912 case ISD::FFLOOR: 3913 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 3914 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 3915 break; 3916 case ISD::FCEIL: 3917 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 3918 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 3919 break; 3920 case ISD::FRINT: 3921 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 3922 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 3923 break; 3924 case ISD::FNEARBYINT: 3925 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 3926 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 3927 break; 3928 break; 3929 default: assert(0 && "Unreachable!"); 3930 } 3931 SDValue Dummy; 3932 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3933 break; 3934 } 3935 } 3936 break; 3937 } 3938 break; 3939 case ISD::FPOWI: { 3940 MVT VT = Node->getValueType(0); 3941 3942 // Expand unsupported unary vector operators by unrolling them. 3943 if (VT.isVector()) { 3944 Result = LegalizeOp(UnrollVectorOp(Op)); 3945 break; 3946 } 3947 3948 // We always lower FPOWI into a libcall. No target support for it yet. 3949 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3950 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3951 SDValue Dummy; 3952 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3953 break; 3954 } 3955 case ISD::BIT_CONVERT: 3956 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3957 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3958 Node->getValueType(0), dl); 3959 } else if (Op.getOperand(0).getValueType().isVector()) { 3960 // The input has to be a vector type, we have to either scalarize it, pack 3961 // it, or convert it based on whether the input vector type is legal. 3962 SDNode *InVal = Node->getOperand(0).getNode(); 3963 int InIx = Node->getOperand(0).getResNo(); 3964 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 3965 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 3966 3967 // Figure out if there is a simple type corresponding to this Vector 3968 // type. If so, convert to the vector type. 3969 MVT TVT = MVT::getVectorVT(EVT, NumElems); 3970 if (TLI.isTypeLegal(TVT)) { 3971 // Turn this into a bit convert of the vector input. 3972 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 3973 LegalizeOp(Node->getOperand(0))); 3974 break; 3975 } else if (NumElems == 1) { 3976 // Turn this into a bit convert of the scalar input. 3977 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 3978 ScalarizeVectorOp(Node->getOperand(0))); 3979 break; 3980 } else { 3981 // FIXME: UNIMP! Store then reload 3982 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3983 } 3984 } else { 3985 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3986 Node->getOperand(0).getValueType())) { 3987 default: assert(0 && "Unknown operation action!"); 3988 case TargetLowering::Expand: 3989 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3990 Node->getValueType(0), dl); 3991 break; 3992 case TargetLowering::Legal: 3993 Tmp1 = LegalizeOp(Node->getOperand(0)); 3994 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3995 break; 3996 } 3997 } 3998 break; 3999 case ISD::CONVERT_RNDSAT: { 4000 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 4001 switch (CvtCode) { 4002 default: assert(0 && "Unknown cvt code!"); 4003 case ISD::CVT_SF: 4004 case ISD::CVT_UF: 4005 case ISD::CVT_FF: 4006 break; 4007 case ISD::CVT_FS: 4008 case ISD::CVT_FU: 4009 case ISD::CVT_SS: 4010 case ISD::CVT_SU: 4011 case ISD::CVT_US: 4012 case ISD::CVT_UU: { 4013 SDValue DTyOp = Node->getOperand(1); 4014 SDValue STyOp = Node->getOperand(2); 4015 SDValue RndOp = Node->getOperand(3); 4016 SDValue SatOp = Node->getOperand(4); 4017 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4018 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4019 case Legal: 4020 Tmp1 = LegalizeOp(Node->getOperand(0)); 4021 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp, 4022 RndOp, SatOp); 4023 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 4024 TargetLowering::Custom) { 4025 Tmp1 = TLI.LowerOperation(Result, DAG); 4026 if (Tmp1.getNode()) Result = Tmp1; 4027 } 4028 break; 4029 case Promote: 4030 Result = PromoteOp(Node->getOperand(0)); 4031 // For FP, make Op1 a i32 4032 4033 Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result, 4034 DTyOp, STyOp, RndOp, SatOp, CvtCode); 4035 break; 4036 } 4037 break; 4038 } 4039 } // end switch CvtCode 4040 break; 4041 } 4042 // Conversion operators. The source and destination have different types. 4043 case ISD::SINT_TO_FP: 4044 case ISD::UINT_TO_FP: { 4045 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 4046 Result = LegalizeINT_TO_FP(Result, isSigned, 4047 Node->getValueType(0), Node->getOperand(0), dl); 4048 break; 4049 } 4050 case ISD::TRUNCATE: 4051 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4052 case Legal: 4053 Tmp1 = LegalizeOp(Node->getOperand(0)); 4054 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 4055 default: assert(0 && "Unknown TRUNCATE legalization operation action!"); 4056 case TargetLowering::Custom: 4057 isCustom = true; 4058 // FALLTHROUGH 4059 case TargetLowering::Legal: 4060 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4061 if (isCustom) { 4062 Tmp1 = TLI.LowerOperation(Result, DAG); 4063 if (Tmp1.getNode()) Result = Tmp1; 4064 } 4065 break; 4066 case TargetLowering::Expand: 4067 assert(Result.getValueType().isVector() && "must be vector type"); 4068 // Unroll the truncate. We should do better. 4069 Result = LegalizeOp(UnrollVectorOp(Result)); 4070 } 4071 break; 4072 case Expand: 4073 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4074 4075 // Since the result is legal, we should just be able to truncate the low 4076 // part of the source. 4077 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 4078 break; 4079 case Promote: 4080 Result = PromoteOp(Node->getOperand(0)); 4081 Result = DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Result); 4082 break; 4083 } 4084 break; 4085 4086 case ISD::FP_TO_SINT: 4087 case ISD::FP_TO_UINT: 4088 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4089 case Legal: 4090 Tmp1 = LegalizeOp(Node->getOperand(0)); 4091 4092 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 4093 default: assert(0 && "Unknown operation action!"); 4094 case TargetLowering::Custom: 4095 isCustom = true; 4096 // FALLTHROUGH 4097 case TargetLowering::Legal: 4098 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4099 if (isCustom) { 4100 Tmp1 = TLI.LowerOperation(Result, DAG); 4101 if (Tmp1.getNode()) Result = Tmp1; 4102 } 4103 break; 4104 case TargetLowering::Promote: 4105 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 4106 Node->getOpcode() == ISD::FP_TO_SINT, 4107 dl); 4108 break; 4109 case TargetLowering::Expand: 4110 if (Node->getOpcode() == ISD::FP_TO_UINT) { 4111 SDValue True, False; 4112 MVT VT = Node->getOperand(0).getValueType(); 4113 MVT NVT = Node->getValueType(0); 4114 const uint64_t zero[] = {0, 0}; 4115 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 4116 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 4117 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 4118 Tmp2 = DAG.getConstantFP(apf, VT); 4119 Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 4120 Node->getOperand(0), 4121 Tmp2, ISD::SETLT); 4122 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 4123 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 4124 DAG.getNode(ISD::FSUB, dl, VT, 4125 Node->getOperand(0), Tmp2)); 4126 False = DAG.getNode(ISD::XOR, dl, NVT, False, 4127 DAG.getConstant(x, NVT)); 4128 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp3, True, False); 4129 break; 4130 } else { 4131 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 4132 } 4133 break; 4134 } 4135 break; 4136 case Expand: { 4137 MVT VT = Op.getValueType(); 4138 MVT OVT = Node->getOperand(0).getValueType(); 4139 // Convert ppcf128 to i32 4140 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 4141 if (Node->getOpcode() == ISD::FP_TO_SINT) { 4142 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128, 4143 Node->getOperand(0), DAG.getValueType(MVT::f64)); 4144 Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result, 4145 DAG.getIntPtrConstant(1)); 4146 Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result); 4147 } else { 4148 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 4149 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 4150 Tmp2 = DAG.getConstantFP(apf, OVT); 4151 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 4152 // FIXME: generated code sucks. 4153 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0), 4154 Tmp2, 4155 DAG.getNode(ISD::ADD, dl, MVT::i32, 4156 DAG.getNode(ISD::FP_TO_SINT, dl, VT, 4157 DAG.getNode(ISD::FSUB, dl, OVT, 4158 Node->getOperand(0), Tmp2)), 4159 DAG.getConstant(0x80000000, MVT::i32)), 4160 DAG.getNode(ISD::FP_TO_SINT, dl, VT, 4161 Node->getOperand(0)), 4162 DAG.getCondCode(ISD::SETGE)); 4163 } 4164 break; 4165 } 4166 // Convert f32 / f64 to i32 / i64 / i128. 4167 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ? 4168 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT); 4169 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!"); 4170 SDValue Dummy; 4171 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 4172 break; 4173 } 4174 case Promote: 4175 Tmp1 = PromoteOp(Node->getOperand(0)); 4176 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 4177 Result = LegalizeOp(Result); 4178 break; 4179 } 4180 break; 4181 4182 case ISD::FP_EXTEND: { 4183 MVT DstVT = Op.getValueType(); 4184 MVT SrcVT = Op.getOperand(0).getValueType(); 4185 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 4186 // The only other way we can lower this is to turn it into a STORE, 4187 // LOAD pair, targetting a temporary location (a stack slot). 4188 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT, dl); 4189 break; 4190 } 4191 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4192 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4193 case Legal: 4194 Tmp1 = LegalizeOp(Node->getOperand(0)); 4195 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4196 break; 4197 case Promote: 4198 Tmp1 = PromoteOp(Node->getOperand(0)); 4199 Result = DAG.getNode(ISD::FP_EXTEND, dl, Op.getValueType(), Tmp1); 4200 break; 4201 } 4202 break; 4203 } 4204 case ISD::FP_ROUND: { 4205 MVT DstVT = Op.getValueType(); 4206 MVT SrcVT = Op.getOperand(0).getValueType(); 4207 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 4208 if (SrcVT == MVT::ppcf128) { 4209 SDValue Lo; 4210 ExpandOp(Node->getOperand(0), Lo, Result); 4211 // Round it the rest of the way (e.g. to f32) if needed. 4212 if (DstVT!=MVT::f64) 4213 Result = DAG.getNode(ISD::FP_ROUND, dl, 4214 DstVT, Result, Op.getOperand(1)); 4215 break; 4216 } 4217 // The only other way we can lower this is to turn it into a STORE, 4218 // LOAD pair, targetting a temporary location (a stack slot). 4219 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT, dl); 4220 break; 4221 } 4222 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4223 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4224 case Legal: 4225 Tmp1 = LegalizeOp(Node->getOperand(0)); 4226 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 4227 break; 4228 case Promote: 4229 Tmp1 = PromoteOp(Node->getOperand(0)); 4230 Result = DAG.getNode(ISD::FP_ROUND, dl, Op.getValueType(), Tmp1, 4231 Node->getOperand(1)); 4232 break; 4233 } 4234 break; 4235 } 4236 case ISD::ANY_EXTEND: 4237 case ISD::ZERO_EXTEND: 4238 case ISD::SIGN_EXTEND: 4239 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4240 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4241 case Legal: 4242 Tmp1 = LegalizeOp(Node->getOperand(0)); 4243 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4244 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 4245 TargetLowering::Custom) { 4246 Tmp1 = TLI.LowerOperation(Result, DAG); 4247 if (Tmp1.getNode()) Result = Tmp1; 4248 } 4249 break; 4250 case Promote: 4251 switch (Node->getOpcode()) { 4252 case ISD::ANY_EXTEND: 4253 Tmp1 = PromoteOp(Node->getOperand(0)); 4254 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Tmp1); 4255 break; 4256 case ISD::ZERO_EXTEND: 4257 Result = PromoteOp(Node->getOperand(0)); 4258 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result); 4259 Result = DAG.getZeroExtendInReg(Result, dl, 4260 Node->getOperand(0).getValueType()); 4261 break; 4262 case ISD::SIGN_EXTEND: 4263 Result = PromoteOp(Node->getOperand(0)); 4264 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result); 4265 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(), 4266 Result, 4267 DAG.getValueType(Node->getOperand(0).getValueType())); 4268 break; 4269 } 4270 } 4271 break; 4272 case ISD::FP_ROUND_INREG: 4273 case ISD::SIGN_EXTEND_INREG: { 4274 Tmp1 = LegalizeOp(Node->getOperand(0)); 4275 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 4276 4277 // If this operation is not supported, convert it to a shl/shr or load/store 4278 // pair. 4279 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 4280 default: assert(0 && "This action not supported for this op yet!"); 4281 case TargetLowering::Legal: 4282 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 4283 break; 4284 case TargetLowering::Expand: 4285 // If this is an integer extend and shifts are supported, do that. 4286 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 4287 // NOTE: we could fall back on load/store here too for targets without 4288 // SAR. However, it is doubtful that any exist. 4289 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 4290 ExtraVT.getSizeInBits(); 4291 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 4292 Result = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 4293 Node->getOperand(0), ShiftCst); 4294 Result = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), 4295 Result, ShiftCst); 4296 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 4297 // The only way we can lower this is to turn it into a TRUNCSTORE, 4298 // EXTLOAD pair, targetting a temporary location (a stack slot). 4299 4300 // NOTE: there is a choice here between constantly creating new stack 4301 // slots and always reusing the same one. We currently always create 4302 // new ones, as reuse may inhibit scheduling. 4303 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 4304 Node->getValueType(0), dl); 4305 } else { 4306 assert(0 && "Unknown op"); 4307 } 4308 break; 4309 } 4310 break; 4311 } 4312 case ISD::TRAMPOLINE: { 4313 SDValue Ops[6]; 4314 for (unsigned i = 0; i != 6; ++i) 4315 Ops[i] = LegalizeOp(Node->getOperand(i)); 4316 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 4317 // The only option for this node is to custom lower it. 4318 Result = TLI.LowerOperation(Result, DAG); 4319 assert(Result.getNode() && "Should always custom lower!"); 4320 4321 // Since trampoline produces two values, make sure to remember that we 4322 // legalized both of them. 4323 Tmp1 = LegalizeOp(Result.getValue(1)); 4324 Result = LegalizeOp(Result); 4325 AddLegalizedOperand(SDValue(Node, 0), Result); 4326 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 4327 return Op.getResNo() ? Tmp1 : Result; 4328 } 4329 case ISD::FLT_ROUNDS_: { 4330 MVT VT = Node->getValueType(0); 4331 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4332 default: assert(0 && "This action not supported for this op yet!"); 4333 case TargetLowering::Custom: 4334 Result = TLI.LowerOperation(Op, DAG); 4335 if (Result.getNode()) break; 4336 // Fall Thru 4337 case TargetLowering::Legal: 4338 // If this operation is not supported, lower it to constant 1 4339 Result = DAG.getConstant(1, VT); 4340 break; 4341 } 4342 break; 4343 } 4344 case ISD::TRAP: { 4345 MVT VT = Node->getValueType(0); 4346 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4347 default: assert(0 && "This action not supported for this op yet!"); 4348 case TargetLowering::Legal: 4349 Tmp1 = LegalizeOp(Node->getOperand(0)); 4350 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4351 break; 4352 case TargetLowering::Custom: 4353 Result = TLI.LowerOperation(Op, DAG); 4354 if (Result.getNode()) break; 4355 // Fall Thru 4356 case TargetLowering::Expand: 4357 // If this operation is not supported, lower it to 'abort()' call 4358 Tmp1 = LegalizeOp(Node->getOperand(0)); 4359 TargetLowering::ArgListTy Args; 4360 std::pair<SDValue,SDValue> CallResult = 4361 TLI.LowerCallTo(Tmp1, Type::VoidTy, 4362 false, false, false, false, CallingConv::C, false, 4363 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 4364 Args, DAG, dl); 4365 Result = CallResult.second; 4366 break; 4367 } 4368 break; 4369 } 4370 4371 case ISD::SADDO: 4372 case ISD::SSUBO: { 4373 MVT VT = Node->getValueType(0); 4374 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4375 default: assert(0 && "This action not supported for this op yet!"); 4376 case TargetLowering::Custom: 4377 Result = TLI.LowerOperation(Op, DAG); 4378 if (Result.getNode()) break; 4379 // FALLTHROUGH 4380 case TargetLowering::Legal: { 4381 SDValue LHS = LegalizeOp(Node->getOperand(0)); 4382 SDValue RHS = LegalizeOp(Node->getOperand(1)); 4383 4384 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 4385 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 4386 LHS, RHS); 4387 MVT OType = Node->getValueType(1); 4388 4389 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 4390 4391 // LHSSign -> LHS >= 0 4392 // RHSSign -> RHS >= 0 4393 // SumSign -> Sum >= 0 4394 // 4395 // Add: 4396 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 4397 // Sub: 4398 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 4399 // 4400 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 4401 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 4402 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 4403 Node->getOpcode() == ISD::SADDO ? 4404 ISD::SETEQ : ISD::SETNE); 4405 4406 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 4407 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 4408 4409 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 4410 4411 MVT ValueVTs[] = { LHS.getValueType(), OType }; 4412 SDValue Ops[] = { Sum, Cmp }; 4413 4414 Result = DAG.getNode(ISD::MERGE_VALUES, dl, 4415 DAG.getVTList(&ValueVTs[0], 2), 4416 &Ops[0], 2); 4417 SDNode *RNode = Result.getNode(); 4418 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0)); 4419 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1)); 4420 break; 4421 } 4422 } 4423 4424 break; 4425 } 4426 case ISD::UADDO: 4427 case ISD::USUBO: { 4428 MVT VT = Node->getValueType(0); 4429 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4430 default: assert(0 && "This action not supported for this op yet!"); 4431 case TargetLowering::Custom: 4432 Result = TLI.LowerOperation(Op, DAG); 4433 if (Result.getNode()) break; 4434 // FALLTHROUGH 4435 case TargetLowering::Legal: { 4436 SDValue LHS = LegalizeOp(Node->getOperand(0)); 4437 SDValue RHS = LegalizeOp(Node->getOperand(1)); 4438 4439 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 4440 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 4441 LHS, RHS); 4442 MVT OType = Node->getValueType(1); 4443 SDValue Cmp = DAG.getSetCC(dl, OType, Sum, LHS, 4444 Node->getOpcode () == ISD::UADDO ? 4445 ISD::SETULT : ISD::SETUGT); 4446 4447 MVT ValueVTs[] = { LHS.getValueType(), OType }; 4448 SDValue Ops[] = { Sum, Cmp }; 4449 4450 Result = DAG.getNode(ISD::MERGE_VALUES, dl, 4451 DAG.getVTList(&ValueVTs[0], 2), 4452 &Ops[0], 2); 4453 SDNode *RNode = Result.getNode(); 4454 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0)); 4455 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1)); 4456 break; 4457 } 4458 } 4459 4460 break; 4461 } 4462 case ISD::SMULO: 4463 case ISD::UMULO: { 4464 MVT VT = Node->getValueType(0); 4465 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4466 default: assert(0 && "This action is not supported at all!"); 4467 case TargetLowering::Custom: 4468 Result = TLI.LowerOperation(Op, DAG); 4469 if (Result.getNode()) break; 4470 // Fall Thru 4471 case TargetLowering::Legal: 4472 // FIXME: According to Hacker's Delight, this can be implemented in 4473 // target independent lowering, but it would be inefficient, since it 4474 // requires a division + a branch. 4475 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!"); 4476 break; 4477 } 4478 break; 4479 } 4480 4481 } 4482 4483 assert(Result.getValueType() == Op.getValueType() && 4484 "Bad legalization!"); 4485 4486 // Make sure that the generated code is itself legal. 4487 if (Result != Op) 4488 Result = LegalizeOp(Result); 4489 4490 // Note that LegalizeOp may be reentered even from single-use nodes, which 4491 // means that we always must cache transformed nodes. 4492 AddLegalizedOperand(Op, Result); 4493 return Result; 4494} 4495 4496/// PromoteOp - Given an operation that produces a value in an invalid type, 4497/// promote it to compute the value into a larger type. The produced value will 4498/// have the correct bits for the low portion of the register, but no guarantee 4499/// is made about the top bits: it may be zero, sign-extended, or garbage. 4500SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { 4501 MVT VT = Op.getValueType(); 4502 MVT NVT = TLI.getTypeToTransformTo(VT); 4503 assert(getTypeAction(VT) == Promote && 4504 "Caller should expand or legalize operands that are not promotable!"); 4505 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() && 4506 "Cannot promote to smaller type!"); 4507 4508 SDValue Tmp1, Tmp2, Tmp3; 4509 SDValue Result; 4510 SDNode *Node = Op.getNode(); 4511 DebugLoc dl = Node->getDebugLoc(); 4512 4513 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op); 4514 if (I != PromotedNodes.end()) return I->second; 4515 4516 switch (Node->getOpcode()) { 4517 case ISD::CopyFromReg: 4518 assert(0 && "CopyFromReg must be legal!"); 4519 default: 4520#ifndef NDEBUG 4521 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4522#endif 4523 assert(0 && "Do not know how to promote this operator!"); 4524 abort(); 4525 case ISD::UNDEF: 4526 Result = DAG.getNode(ISD::UNDEF, dl, NVT); 4527 break; 4528 case ISD::Constant: 4529 if (VT != MVT::i1) 4530 Result = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Op); 4531 else 4532 Result = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Op); 4533 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4534 break; 4535 case ISD::ConstantFP: 4536 Result = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op); 4537 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4538 break; 4539 4540 case ISD::SETCC: { 4541 MVT VT0 = Node->getOperand(0).getValueType(); 4542 assert(isTypeLegal(TLI.getSetCCResultType(VT0)) 4543 && "SetCC type is not legal??"); 4544 Result = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(VT0), 4545 Node->getOperand(0), Node->getOperand(1), 4546 Node->getOperand(2)); 4547 break; 4548 } 4549 case ISD::TRUNCATE: 4550 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4551 case Legal: 4552 Result = LegalizeOp(Node->getOperand(0)); 4553 assert(Result.getValueType().bitsGE(NVT) && 4554 "This truncation doesn't make sense!"); 4555 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT 4556 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Result); 4557 break; 4558 case Promote: 4559 // The truncation is not required, because we don't guarantee anything 4560 // about high bits anyway. 4561 Result = PromoteOp(Node->getOperand(0)); 4562 break; 4563 case Expand: 4564 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4565 // Truncate the low part of the expanded value to the result type 4566 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Tmp1); 4567 } 4568 break; 4569 case ISD::SIGN_EXTEND: 4570 case ISD::ZERO_EXTEND: 4571 case ISD::ANY_EXTEND: 4572 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4573 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4574 case Legal: 4575 // Input is legal? Just do extend all the way to the larger type. 4576 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0)); 4577 break; 4578 case Promote: 4579 // Promote the reg if it's smaller. 4580 Result = PromoteOp(Node->getOperand(0)); 4581 // The high bits are not guaranteed to be anything. Insert an extend. 4582 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4583 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result, 4584 DAG.getValueType(Node->getOperand(0).getValueType())); 4585 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4586 Result = DAG.getZeroExtendInReg(Result, dl, 4587 Node->getOperand(0).getValueType()); 4588 break; 4589 } 4590 break; 4591 case ISD::CONVERT_RNDSAT: { 4592 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 4593 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 4594 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 4595 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 4596 "can only promote integers"); 4597 Result = DAG.getConvertRndSat(NVT, dl, Node->getOperand(0), 4598 Node->getOperand(1), Node->getOperand(2), 4599 Node->getOperand(3), Node->getOperand(4), 4600 CvtCode); 4601 break; 4602 4603 } 4604 case ISD::BIT_CONVERT: 4605 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4606 Node->getValueType(0), dl); 4607 Result = PromoteOp(Result); 4608 break; 4609 4610 case ISD::FP_EXTEND: 4611 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4612 case ISD::FP_ROUND: 4613 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4614 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4615 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4616 case Legal: 4617 if (Node->getConstantOperandVal(1) == 0) { 4618 // Input is legal? Do an FP_ROUND_INREG. 4619 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Node->getOperand(0), 4620 DAG.getValueType(VT)); 4621 } else { 4622 // Just remove the truncate, it isn't affecting the value. 4623 Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0), 4624 Node->getOperand(1)); 4625 } 4626 break; 4627 } 4628 break; 4629 case ISD::SINT_TO_FP: 4630 case ISD::UINT_TO_FP: 4631 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4632 case Legal: 4633 // No extra round required here. 4634 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0)); 4635 break; 4636 4637 case Promote: 4638 Result = PromoteOp(Node->getOperand(0)); 4639 if (Node->getOpcode() == ISD::SINT_TO_FP) 4640 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(), 4641 Result, 4642 DAG.getValueType(Node->getOperand(0).getValueType())); 4643 else 4644 Result = DAG.getZeroExtendInReg(Result, dl, 4645 Node->getOperand(0).getValueType()); 4646 // No extra round required here. 4647 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Result); 4648 break; 4649 case Expand: 4650 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4651 Node->getOperand(0), dl); 4652 // Round if we cannot tolerate excess precision. 4653 if (NoExcessFPPrecision) 4654 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, 4655 DAG.getValueType(VT)); 4656 break; 4657 } 4658 break; 4659 4660 case ISD::SIGN_EXTEND_INREG: 4661 Result = PromoteOp(Node->getOperand(0)); 4662 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result, 4663 Node->getOperand(1)); 4664 break; 4665 case ISD::FP_TO_SINT: 4666 case ISD::FP_TO_UINT: 4667 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4668 case Legal: 4669 case Expand: 4670 Tmp1 = Node->getOperand(0); 4671 break; 4672 case Promote: 4673 // The input result is prerounded, so we don't have to do anything 4674 // special. 4675 Tmp1 = PromoteOp(Node->getOperand(0)); 4676 break; 4677 } 4678 // If we're promoting a UINT to a larger size, check to see if the new node 4679 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4680 // we can use that instead. This allows us to generate better code for 4681 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4682 // legal, such as PowerPC. 4683 if (Node->getOpcode() == ISD::FP_TO_UINT && 4684 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) && 4685 (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) || 4686 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4687 Result = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Tmp1); 4688 } else { 4689 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 4690 } 4691 break; 4692 4693 case ISD::FABS: 4694 case ISD::FNEG: 4695 Tmp1 = PromoteOp(Node->getOperand(0)); 4696 assert(Tmp1.getValueType() == NVT); 4697 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 4698 // NOTE: we do not have to do any extra rounding here for 4699 // NoExcessFPPrecision, because we know the input will have the appropriate 4700 // precision, and these operations don't modify precision at all. 4701 break; 4702 4703 case ISD::FLOG: 4704 case ISD::FLOG2: 4705 case ISD::FLOG10: 4706 case ISD::FEXP: 4707 case ISD::FEXP2: 4708 case ISD::FSQRT: 4709 case ISD::FSIN: 4710 case ISD::FCOS: 4711 case ISD::FTRUNC: 4712 case ISD::FFLOOR: 4713 case ISD::FCEIL: 4714 case ISD::FRINT: 4715 case ISD::FNEARBYINT: 4716 Tmp1 = PromoteOp(Node->getOperand(0)); 4717 assert(Tmp1.getValueType() == NVT); 4718 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 4719 if (NoExcessFPPrecision) 4720 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, 4721 DAG.getValueType(VT)); 4722 break; 4723 4724 case ISD::FPOW: 4725 case ISD::FPOWI: { 4726 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall 4727 // directly as well, which may be better. 4728 Tmp1 = PromoteOp(Node->getOperand(0)); 4729 Tmp2 = Node->getOperand(1); 4730 if (Node->getOpcode() == ISD::FPOW) 4731 Tmp2 = PromoteOp(Tmp2); 4732 assert(Tmp1.getValueType() == NVT); 4733 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 4734 if (NoExcessFPPrecision) 4735 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, 4736 DAG.getValueType(VT)); 4737 break; 4738 } 4739 4740 case ISD::ATOMIC_CMP_SWAP: { 4741 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4742 Tmp2 = PromoteOp(Node->getOperand(2)); 4743 Tmp3 = PromoteOp(Node->getOperand(3)); 4744 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(), 4745 AtomNode->getChain(), 4746 AtomNode->getBasePtr(), Tmp2, Tmp3, 4747 AtomNode->getSrcValue(), 4748 AtomNode->getAlignment()); 4749 // Remember that we legalized the chain. 4750 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4751 break; 4752 } 4753 case ISD::ATOMIC_LOAD_ADD: 4754 case ISD::ATOMIC_LOAD_SUB: 4755 case ISD::ATOMIC_LOAD_AND: 4756 case ISD::ATOMIC_LOAD_OR: 4757 case ISD::ATOMIC_LOAD_XOR: 4758 case ISD::ATOMIC_LOAD_NAND: 4759 case ISD::ATOMIC_LOAD_MIN: 4760 case ISD::ATOMIC_LOAD_MAX: 4761 case ISD::ATOMIC_LOAD_UMIN: 4762 case ISD::ATOMIC_LOAD_UMAX: 4763 case ISD::ATOMIC_SWAP: { 4764 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4765 Tmp2 = PromoteOp(Node->getOperand(2)); 4766 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(), 4767 AtomNode->getChain(), 4768 AtomNode->getBasePtr(), Tmp2, 4769 AtomNode->getSrcValue(), 4770 AtomNode->getAlignment()); 4771 // Remember that we legalized the chain. 4772 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4773 break; 4774 } 4775 4776 case ISD::AND: 4777 case ISD::OR: 4778 case ISD::XOR: 4779 case ISD::ADD: 4780 case ISD::SUB: 4781 case ISD::MUL: 4782 // The input may have strange things in the top bits of the registers, but 4783 // these operations don't care. They may have weird bits going out, but 4784 // that too is okay if they are integer operations. 4785 Tmp1 = PromoteOp(Node->getOperand(0)); 4786 Tmp2 = PromoteOp(Node->getOperand(1)); 4787 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4788 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 4789 break; 4790 case ISD::FADD: 4791 case ISD::FSUB: 4792 case ISD::FMUL: 4793 Tmp1 = PromoteOp(Node->getOperand(0)); 4794 Tmp2 = PromoteOp(Node->getOperand(1)); 4795 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4796 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 4797 4798 // Floating point operations will give excess precision that we may not be 4799 // able to tolerate. If we DO allow excess precision, just leave it, 4800 // otherwise excise it. 4801 // FIXME: Why would we need to round FP ops more than integer ones? 4802 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4803 if (NoExcessFPPrecision) 4804 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, 4805 DAG.getValueType(VT)); 4806 break; 4807 4808 case ISD::SDIV: 4809 case ISD::SREM: 4810 // These operators require that their input be sign extended. 4811 Tmp1 = PromoteOp(Node->getOperand(0)); 4812 Tmp2 = PromoteOp(Node->getOperand(1)); 4813 if (NVT.isInteger()) { 4814 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1, 4815 DAG.getValueType(VT)); 4816 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2, 4817 DAG.getValueType(VT)); 4818 } 4819 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 4820 4821 // Perform FP_ROUND: this is probably overly pessimistic. 4822 if (NVT.isFloatingPoint() && NoExcessFPPrecision) 4823 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, 4824 DAG.getValueType(VT)); 4825 break; 4826 case ISD::FDIV: 4827 case ISD::FREM: 4828 case ISD::FCOPYSIGN: 4829 // These operators require that their input be fp extended. 4830 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4831 case Expand: assert(0 && "not implemented"); 4832 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4833 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4834 } 4835 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4836 case Expand: assert(0 && "not implemented"); 4837 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4838 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4839 } 4840 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 4841 4842 // Perform FP_ROUND: this is probably overly pessimistic. 4843 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4844 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, 4845 DAG.getValueType(VT)); 4846 break; 4847 4848 case ISD::UDIV: 4849 case ISD::UREM: 4850 // These operators require that their input be zero extended. 4851 Tmp1 = PromoteOp(Node->getOperand(0)); 4852 Tmp2 = PromoteOp(Node->getOperand(1)); 4853 assert(NVT.isInteger() && "Operators don't apply to FP!"); 4854 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT); 4855 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT); 4856 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 4857 break; 4858 4859 case ISD::SHL: 4860 Tmp1 = PromoteOp(Node->getOperand(0)); 4861 Result = DAG.getNode(ISD::SHL, dl, NVT, Tmp1, Node->getOperand(1)); 4862 break; 4863 case ISD::SRA: 4864 // The input value must be properly sign extended. 4865 Tmp1 = PromoteOp(Node->getOperand(0)); 4866 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1, 4867 DAG.getValueType(VT)); 4868 Result = DAG.getNode(ISD::SRA, dl, NVT, Tmp1, Node->getOperand(1)); 4869 break; 4870 case ISD::SRL: 4871 // The input value must be properly zero extended. 4872 Tmp1 = PromoteOp(Node->getOperand(0)); 4873 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT); 4874 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, Node->getOperand(1)); 4875 break; 4876 4877 case ISD::VAARG: 4878 Tmp1 = Node->getOperand(0); // Get the chain. 4879 Tmp2 = Node->getOperand(1); // Get the pointer. 4880 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4881 Tmp3 = DAG.getVAArg(VT, dl, Tmp1, Tmp2, Node->getOperand(2)); 4882 Result = TLI.LowerOperation(Tmp3, DAG); 4883 } else { 4884 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4885 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0); 4886 // Increment the pointer, VAList, to the next vaarg 4887 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 4888 DAG.getConstant(VT.getSizeInBits()/8, 4889 TLI.getPointerTy())); 4890 // Store the incremented VAList to the legalized pointer 4891 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0); 4892 // Load the actual argument out of the pointer VAList 4893 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT); 4894 } 4895 // Remember that we legalized the chain. 4896 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4897 break; 4898 4899 case ISD::LOAD: { 4900 LoadSDNode *LD = cast<LoadSDNode>(Node); 4901 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4902 ? ISD::EXTLOAD : LD->getExtensionType(); 4903 Result = DAG.getExtLoad(ExtType, dl, NVT, 4904 LD->getChain(), LD->getBasePtr(), 4905 LD->getSrcValue(), LD->getSrcValueOffset(), 4906 LD->getMemoryVT(), 4907 LD->isVolatile(), 4908 LD->getAlignment()); 4909 // Remember that we legalized the chain. 4910 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4911 break; 4912 } 4913 case ISD::SELECT: { 4914 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4915 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4916 4917 MVT VT2 = Tmp2.getValueType(); 4918 assert(VT2 == Tmp3.getValueType() 4919 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); 4920 // Ensure that the resulting node is at least the same size as the operands' 4921 // value types, because we cannot assume that TLI.getSetCCValueType() is 4922 // constant. 4923 Result = DAG.getNode(ISD::SELECT, dl, VT2, Node->getOperand(0), Tmp2, Tmp3); 4924 break; 4925 } 4926 case ISD::SELECT_CC: 4927 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4928 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4929 Result = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0), 4930 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4931 break; 4932 case ISD::BSWAP: 4933 Tmp1 = Node->getOperand(0); 4934 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); 4935 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 4936 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 4937 DAG.getConstant(NVT.getSizeInBits() - 4938 VT.getSizeInBits(), 4939 TLI.getShiftAmountTy())); 4940 break; 4941 case ISD::CTPOP: 4942 case ISD::CTTZ: 4943 case ISD::CTLZ: 4944 // Zero extend the argument 4945 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 4946 // Perform the larger operation, then subtract if needed. 4947 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 4948 switch(Node->getOpcode()) { 4949 case ISD::CTPOP: 4950 Result = Tmp1; 4951 break; 4952 case ISD::CTTZ: 4953 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4954 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, 4955 DAG.getConstant(NVT.getSizeInBits(), NVT), 4956 ISD::SETEQ); 4957 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 4958 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); 4959 break; 4960 case ISD::CTLZ: 4961 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4962 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 4963 DAG.getConstant(NVT.getSizeInBits() - 4964 VT.getSizeInBits(), NVT)); 4965 break; 4966 } 4967 break; 4968 case ISD::EXTRACT_SUBVECTOR: 4969 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4970 break; 4971 case ISD::EXTRACT_VECTOR_ELT: 4972 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4973 break; 4974 } 4975 4976 assert(Result.getNode() && "Didn't set a result!"); 4977 4978 // Make sure the result is itself legal. 4979 Result = LegalizeOp(Result); 4980 4981 // Remember that we promoted this! 4982 AddPromotedOperand(Op, Result); 4983 return Result; 4984} 4985 4986/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4987/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4988/// based on the vector type. The return type of this matches the element type 4989/// of the vector, which may not be legal for the target. 4990SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) { 4991 // We know that operand #0 is the Vec vector. If the index is a constant 4992 // or if the invec is a supported hardware type, we can use it. Otherwise, 4993 // lower to a store then an indexed load. 4994 SDValue Vec = Op.getOperand(0); 4995 SDValue Idx = Op.getOperand(1); 4996 DebugLoc dl = Op.getNode()->getDebugLoc(); 4997 4998 MVT TVT = Vec.getValueType(); 4999 unsigned NumElems = TVT.getVectorNumElements(); 5000 5001 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 5002 default: assert(0 && "This action is not supported yet!"); 5003 case TargetLowering::Custom: { 5004 Vec = LegalizeOp(Vec); 5005 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 5006 SDValue Tmp3 = TLI.LowerOperation(Op, DAG); 5007 if (Tmp3.getNode()) 5008 return Tmp3; 5009 break; 5010 } 5011 case TargetLowering::Legal: 5012 if (isTypeLegal(TVT)) { 5013 Vec = LegalizeOp(Vec); 5014 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 5015 return Op; 5016 } 5017 break; 5018 case TargetLowering::Promote: 5019 assert(TVT.isVector() && "not vector type"); 5020 // fall thru to expand since vectors are by default are promote 5021 case TargetLowering::Expand: 5022 break; 5023 } 5024 5025 if (NumElems == 1) { 5026 // This must be an access of the only element. Return it. 5027 Op = ScalarizeVectorOp(Vec); 5028 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 5029 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 5030 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 5031 SDValue Lo, Hi; 5032 SplitVectorOp(Vec, Lo, Hi); 5033 if (CIdx->getZExtValue() < NumLoElts) { 5034 Vec = Lo; 5035 } else { 5036 Vec = Hi; 5037 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts, 5038 Idx.getValueType()); 5039 } 5040 5041 // It's now an extract from the appropriate high or low part. Recurse. 5042 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 5043 Op = ExpandEXTRACT_VECTOR_ELT(Op); 5044 } else { 5045 // Store the value to a temporary stack slot, then LOAD the scalar 5046 // element back out. 5047 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 5048 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0); 5049 5050 // Add the offset to the index. 5051 unsigned EltSize = Op.getValueType().getSizeInBits()/8; 5052 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 5053 DAG.getConstant(EltSize, Idx.getValueType())); 5054 5055 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 5056 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 5057 else 5058 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 5059 5060 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 5061 5062 Op = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0); 5063 } 5064 return Op; 5065} 5066 5067/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 5068/// we assume the operation can be split if it is not already legal. 5069SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) { 5070 // We know that operand #0 is the Vec vector. For now we assume the index 5071 // is a constant and that the extracted result is a supported hardware type. 5072 SDValue Vec = Op.getOperand(0); 5073 SDValue Idx = LegalizeOp(Op.getOperand(1)); 5074 5075 unsigned NumElems = Vec.getValueType().getVectorNumElements(); 5076 5077 if (NumElems == Op.getValueType().getVectorNumElements()) { 5078 // This must be an access of the desired vector length. Return it. 5079 return Vec; 5080 } 5081 5082 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 5083 SDValue Lo, Hi; 5084 SplitVectorOp(Vec, Lo, Hi); 5085 if (CIdx->getZExtValue() < NumElems/2) { 5086 Vec = Lo; 5087 } else { 5088 Vec = Hi; 5089 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2, 5090 Idx.getValueType()); 5091 } 5092 5093 // It's now an extract from the appropriate high or low part. Recurse. 5094 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 5095 return ExpandEXTRACT_SUBVECTOR(Op); 5096} 5097 5098/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 5099/// with condition CC on the current target. This usually involves legalizing 5100/// or promoting the arguments. In the case where LHS and RHS must be expanded, 5101/// there may be no choice but to create a new SetCC node to represent the 5102/// legalized value of setcc lhs, rhs. In this case, the value is returned in 5103/// LHS, and the SDValue returned in RHS has a nil SDNode value. 5104void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS, 5105 SDValue &RHS, 5106 SDValue &CC, 5107 DebugLoc dl) { 5108 SDValue Tmp1, Tmp2, Tmp3, Result; 5109 5110 switch (getTypeAction(LHS.getValueType())) { 5111 case Legal: 5112 Tmp1 = LegalizeOp(LHS); // LHS 5113 Tmp2 = LegalizeOp(RHS); // RHS 5114 break; 5115 case Promote: 5116 Tmp1 = PromoteOp(LHS); // LHS 5117 Tmp2 = PromoteOp(RHS); // RHS 5118 5119 // If this is an FP compare, the operands have already been extended. 5120 if (LHS.getValueType().isInteger()) { 5121 MVT VT = LHS.getValueType(); 5122 MVT NVT = TLI.getTypeToTransformTo(VT); 5123 5124 // Otherwise, we have to insert explicit sign or zero extends. Note 5125 // that we could insert sign extends for ALL conditions, but zero extend 5126 // is cheaper on many machines (an AND instead of two shifts), so prefer 5127 // it. 5128 switch (cast<CondCodeSDNode>(CC)->get()) { 5129 default: assert(0 && "Unknown integer comparison!"); 5130 case ISD::SETEQ: 5131 case ISD::SETNE: 5132 case ISD::SETUGE: 5133 case ISD::SETUGT: 5134 case ISD::SETULE: 5135 case ISD::SETULT: 5136 // ALL of these operations will work if we either sign or zero extend 5137 // the operands (including the unsigned comparisons!). Zero extend is 5138 // usually a simpler/cheaper operation, so prefer it. 5139 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT); 5140 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT); 5141 break; 5142 case ISD::SETGE: 5143 case ISD::SETGT: 5144 case ISD::SETLT: 5145 case ISD::SETLE: 5146 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1, 5147 DAG.getValueType(VT)); 5148 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2, 5149 DAG.getValueType(VT)); 5150 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes. 5151 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes. 5152 break; 5153 } 5154 } 5155 break; 5156 case Expand: { 5157 MVT VT = LHS.getValueType(); 5158 if (VT == MVT::f32 || VT == MVT::f64) { 5159 // Expand into one or more soft-fp libcall(s). 5160 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; 5161 switch (cast<CondCodeSDNode>(CC)->get()) { 5162 case ISD::SETEQ: 5163 case ISD::SETOEQ: 5164 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 5165 break; 5166 case ISD::SETNE: 5167 case ISD::SETUNE: 5168 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 5169 break; 5170 case ISD::SETGE: 5171 case ISD::SETOGE: 5172 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 5173 break; 5174 case ISD::SETLT: 5175 case ISD::SETOLT: 5176 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 5177 break; 5178 case ISD::SETLE: 5179 case ISD::SETOLE: 5180 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 5181 break; 5182 case ISD::SETGT: 5183 case ISD::SETOGT: 5184 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 5185 break; 5186 case ISD::SETUO: 5187 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 5188 break; 5189 case ISD::SETO: 5190 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 5191 break; 5192 default: 5193 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 5194 switch (cast<CondCodeSDNode>(CC)->get()) { 5195 case ISD::SETONE: 5196 // SETONE = SETOLT | SETOGT 5197 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 5198 // Fallthrough 5199 case ISD::SETUGT: 5200 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 5201 break; 5202 case ISD::SETUGE: 5203 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 5204 break; 5205 case ISD::SETULT: 5206 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 5207 break; 5208 case ISD::SETULE: 5209 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 5210 break; 5211 case ISD::SETUEQ: 5212 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 5213 break; 5214 default: assert(0 && "Unsupported FP setcc!"); 5215 } 5216 } 5217 5218 SDValue Dummy; 5219 SDValue Ops[2] = { LHS, RHS }; 5220 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2, dl).getNode(), 5221 false /*sign irrelevant*/, Dummy); 5222 Tmp2 = DAG.getConstant(0, MVT::i32); 5223 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 5224 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 5225 Tmp1 = DAG.getNode(ISD::SETCC, dl, 5226 TLI.getSetCCResultType(Tmp1.getValueType()), 5227 Tmp1, Tmp2, CC); 5228 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2, dl).getNode(), 5229 false /*sign irrelevant*/, Dummy); 5230 Tmp2 = DAG.getNode(ISD::SETCC, dl, 5231 TLI.getSetCCResultType(LHS.getValueType()), LHS, 5232 Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 5233 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2); 5234 Tmp2 = SDValue(); 5235 } 5236 LHS = LegalizeOp(Tmp1); 5237 RHS = Tmp2; 5238 return; 5239 } 5240 5241 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 5242 ExpandOp(LHS, LHSLo, LHSHi); 5243 ExpandOp(RHS, RHSLo, RHSHi); 5244 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 5245 5246 if (VT==MVT::ppcf128) { 5247 // FIXME: This generated code sucks. We want to generate 5248 // FCMPU crN, hi1, hi2 5249 // BNE crN, L: 5250 // FCMPU crN, lo1, lo2 5251 // The following can be improved, but not that much. 5252 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 5253 LHSHi, RHSHi, ISD::SETOEQ); 5254 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 5255 LHSLo, RHSLo, CCCode); 5256 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); 5257 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 5258 LHSHi, RHSHi, ISD::SETUNE); 5259 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 5260 LHSHi, RHSHi, CCCode); 5261 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); 5262 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); 5263 Tmp2 = SDValue(); 5264 break; 5265 } 5266 5267 switch (CCCode) { 5268 case ISD::SETEQ: 5269 case ISD::SETNE: 5270 if (RHSLo == RHSHi) 5271 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 5272 if (RHSCST->isAllOnesValue()) { 5273 // Comparison to -1. 5274 Tmp1 = DAG.getNode(ISD::AND, dl,LHSLo.getValueType(), LHSLo, LHSHi); 5275 Tmp2 = RHSLo; 5276 break; 5277 } 5278 5279 Tmp1 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); 5280 Tmp2 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); 5281 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2); 5282 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 5283 break; 5284 default: 5285 // If this is a comparison of the sign bit, just look at the top part. 5286 // X > -1, x < 0 5287 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 5288 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 5289 CST->isNullValue()) || // X < 0 5290 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 5291 CST->isAllOnesValue())) { // X > -1 5292 Tmp1 = LHSHi; 5293 Tmp2 = RHSHi; 5294 break; 5295 } 5296 5297 // FIXME: This generated code sucks. 5298 ISD::CondCode LowCC; 5299 switch (CCCode) { 5300 default: assert(0 && "Unknown integer setcc!"); 5301 case ISD::SETLT: 5302 case ISD::SETULT: LowCC = ISD::SETULT; break; 5303 case ISD::SETGT: 5304 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 5305 case ISD::SETLE: 5306 case ISD::SETULE: LowCC = ISD::SETULE; break; 5307 case ISD::SETGE: 5308 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 5309 } 5310 5311 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 5312 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 5313 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 5314 5315 // NOTE: on targets without efficient SELECT of bools, we can always use 5316 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 5317 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 5318 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), 5319 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl); 5320 if (!Tmp1.getNode()) 5321 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 5322 LHSLo, RHSLo, LowCC); 5323 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 5324 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl); 5325 if (!Tmp2.getNode()) 5326 Tmp2 = DAG.getNode(ISD::SETCC, dl, 5327 TLI.getSetCCResultType(LHSHi.getValueType()), 5328 LHSHi, RHSHi,CC); 5329 5330 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 5331 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 5332 if ((Tmp1C && Tmp1C->isNullValue()) || 5333 (Tmp2C && Tmp2C->isNullValue() && 5334 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 5335 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 5336 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 5337 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 5338 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 5339 // low part is known false, returns high part. 5340 // For LE / GE, if high part is known false, ignore the low part. 5341 // For LT / GT, if high part is known true, ignore the low part. 5342 Tmp1 = Tmp2; 5343 Tmp2 = SDValue(); 5344 } else { 5345 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 5346 LHSHi, RHSHi, ISD::SETEQ, false, 5347 DagCombineInfo, dl); 5348 if (!Result.getNode()) 5349 Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 5350 LHSHi, RHSHi, ISD::SETEQ); 5351 Result = LegalizeOp(DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), 5352 Result, Tmp1, Tmp2)); 5353 Tmp1 = Result; 5354 Tmp2 = SDValue(); 5355 } 5356 } 5357 } 5358 } 5359 LHS = Tmp1; 5360 RHS = Tmp2; 5361} 5362 5363/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 5364/// condition code CC on the current target. This routine assumes LHS and rHS 5365/// have already been legalized by LegalizeSetCCOperands. It expands SETCC with 5366/// illegal condition code into AND / OR of multiple SETCC values. 5367void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, 5368 SDValue &LHS, SDValue &RHS, 5369 SDValue &CC, 5370 DebugLoc dl) { 5371 MVT OpVT = LHS.getValueType(); 5372 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 5373 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 5374 default: assert(0 && "Unknown condition code action!"); 5375 case TargetLowering::Legal: 5376 // Nothing to do. 5377 break; 5378 case TargetLowering::Expand: { 5379 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 5380 unsigned Opc = 0; 5381 switch (CCCode) { 5382 default: assert(0 && "Don't know how to expand this condition!"); abort(); 5383 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 5384 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 5385 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 5386 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 5387 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 5388 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 5389 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5390 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5391 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5392 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5393 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5394 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5395 // FIXME: Implement more expansions. 5396 } 5397 5398 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 5399 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 5400 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 5401 RHS = SDValue(); 5402 CC = SDValue(); 5403 break; 5404 } 5405 } 5406} 5407 5408/// EmitStackConvert - Emit a store/load combination to the stack. This stores 5409/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 5410/// a load from the stack slot to DestVT, extending it if needed. 5411/// The resultant code need not be legal. 5412SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 5413 MVT SlotVT, 5414 MVT DestVT, 5415 DebugLoc dl) { 5416 // Create the stack frame object. 5417 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment( 5418 SrcOp.getValueType().getTypeForMVT()); 5419 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 5420 5421 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 5422 int SPFI = StackPtrFI->getIndex(); 5423 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 5424 5425 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 5426 unsigned SlotSize = SlotVT.getSizeInBits(); 5427 unsigned DestSize = DestVT.getSizeInBits(); 5428 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment( 5429 DestVT.getTypeForMVT()); 5430 5431 // Emit a store to the stack slot. Use a truncstore if the input value is 5432 // later than DestVT. 5433 SDValue Store; 5434 5435 if (SrcSize > SlotSize) 5436 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 5437 SV, 0, SlotVT, false, SrcAlign); 5438 else { 5439 assert(SrcSize == SlotSize && "Invalid store"); 5440 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 5441 SV, 0, false, SrcAlign); 5442 } 5443 5444 // Result is a load from the stack slot. 5445 if (SlotSize == DestSize) 5446 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign); 5447 5448 assert(SlotSize < DestSize && "Unknown extension!"); 5449 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, 5450 false, DestAlign); 5451} 5452 5453SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 5454 DebugLoc dl = Node->getDebugLoc(); 5455 // Create a vector sized/aligned stack slot, store the value to element #0, 5456 // then load the whole vector back out. 5457 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 5458 5459 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 5460 int SPFI = StackPtrFI->getIndex(); 5461 5462 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(0), 5463 StackPtr, 5464 PseudoSourceValue::getFixedStack(SPFI), 0); 5465 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 5466 PseudoSourceValue::getFixedStack(SPFI), 0); 5467} 5468 5469 5470/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 5471/// support the operation, but do support the resultant vector type. 5472SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 5473 5474 // If the only non-undef value is the low element, turn this into a 5475 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 5476 unsigned NumElems = Node->getNumOperands(); 5477 bool isOnlyLowElement = true; 5478 SDValue SplatValue = Node->getOperand(0); 5479 DebugLoc dl = Node->getDebugLoc(); 5480 5481 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t> 5482 // and use a bitmask instead of a list of elements. 5483 std::map<SDValue, std::vector<unsigned> > Values; 5484 Values[SplatValue].push_back(0); 5485 bool isConstant = true; 5486 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 5487 SplatValue.getOpcode() != ISD::UNDEF) 5488 isConstant = false; 5489 5490 for (unsigned i = 1; i < NumElems; ++i) { 5491 SDValue V = Node->getOperand(i); 5492 Values[V].push_back(i); 5493 if (V.getOpcode() != ISD::UNDEF) 5494 isOnlyLowElement = false; 5495 if (SplatValue != V) 5496 SplatValue = SDValue(0,0); 5497 5498 // If this isn't a constant element or an undef, we can't use a constant 5499 // pool load. 5500 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 5501 V.getOpcode() != ISD::UNDEF) 5502 isConstant = false; 5503 } 5504 5505 if (isOnlyLowElement) { 5506 // If the low element is an undef too, then this whole things is an undef. 5507 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 5508 return DAG.getNode(ISD::UNDEF, dl, Node->getValueType(0)); 5509 // Otherwise, turn this into a scalar_to_vector node. 5510 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Node->getValueType(0), 5511 Node->getOperand(0)); 5512 } 5513 5514 // If all elements are constants, create a load from the constant pool. 5515 if (isConstant) { 5516 MVT VT = Node->getValueType(0); 5517 std::vector<Constant*> CV; 5518 for (unsigned i = 0, e = NumElems; i != e; ++i) { 5519 if (ConstantFPSDNode *V = 5520 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 5521 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 5522 } else if (ConstantSDNode *V = 5523 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 5524 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 5525 } else { 5526 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 5527 const Type *OpNTy = 5528 Node->getOperand(0).getValueType().getTypeForMVT(); 5529 CV.push_back(UndefValue::get(OpNTy)); 5530 } 5531 } 5532 Constant *CP = ConstantVector::get(CV); 5533 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 5534 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5535 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5536 PseudoSourceValue::getConstantPool(), 0, 5537 false, Alignment); 5538 } 5539 5540 if (SplatValue.getNode()) { // Splat of one value? 5541 // Build the shuffle constant vector: <0, 0, 0, 0> 5542 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5543 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); 5544 std::vector<SDValue> ZeroVec(NumElems, Zero); 5545 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 5546 &ZeroVec[0], ZeroVec.size()); 5547 5548 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 5549 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 5550 // Get the splatted value into the low element of a vector register. 5551 SDValue LowValVec = 5552 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5553 Node->getValueType(0), SplatValue); 5554 5555 // Return shuffle(LowValVec, undef, <0,0,0,0>) 5556 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, 5557 Node->getValueType(0), LowValVec, 5558 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 5559 SplatMask); 5560 } 5561 } 5562 5563 // If there are only two unique elements, we may be able to turn this into a 5564 // vector shuffle. 5565 if (Values.size() == 2) { 5566 // Get the two values in deterministic order. 5567 SDValue Val1 = Node->getOperand(1); 5568 SDValue Val2; 5569 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin(); 5570 if (MI->first != Val1) 5571 Val2 = MI->first; 5572 else 5573 Val2 = (++MI)->first; 5574 5575 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our 5576 // vector shuffle has the undef vector on the RHS. 5577 if (Val1.getOpcode() == ISD::UNDEF) 5578 std::swap(Val1, Val2); 5579 5580 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 5581 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5582 MVT MaskEltVT = MaskVT.getVectorElementType(); 5583 std::vector<SDValue> MaskVec(NumElems); 5584 5585 // Set elements of the shuffle mask for Val1. 5586 std::vector<unsigned> &Val1Elts = Values[Val1]; 5587 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 5588 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT); 5589 5590 // Set elements of the shuffle mask for Val2. 5591 std::vector<unsigned> &Val2Elts = Values[Val2]; 5592 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 5593 if (Val2.getOpcode() != ISD::UNDEF) 5594 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); 5595 else 5596 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, dl, MaskEltVT); 5597 5598 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 5599 &MaskVec[0], MaskVec.size()); 5600 5601 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 5602 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, 5603 Node->getValueType(0)) && 5604 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 5605 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val1); 5606 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val2); 5607 SDValue Ops[] = { Val1, Val2, ShuffleMask }; 5608 5609 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 5610 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,Node->getValueType(0), Ops, 3); 5611 } 5612 } 5613 5614 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5615 // aligned object on the stack, store each element into it, then load 5616 // the result as a vector. 5617 MVT VT = Node->getValueType(0); 5618 // Create the stack frame object. 5619 SDValue FIPtr = DAG.CreateStackTemporary(VT); 5620 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 5621 const Value *SV = PseudoSourceValue::getFixedStack(FI); 5622 5623 // Emit a store of each element to the stack slot. 5624 SmallVector<SDValue, 8> Stores; 5625 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8; 5626 // Store (in the right endianness) the elements to memory. 5627 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5628 // Ignore undef elements. 5629 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5630 5631 unsigned Offset = TypeByteSize*i; 5632 5633 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5634 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 5635 5636 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i), 5637 Idx, SV, Offset)); 5638 } 5639 5640 SDValue StoreChain; 5641 if (!Stores.empty()) // Not all undef elements? 5642 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 5643 &Stores[0], Stores.size()); 5644 else 5645 StoreChain = DAG.getEntryNode(); 5646 5647 // Result is a load from the stack slot. 5648 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0); 5649} 5650 5651void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5652 SDValue Op, SDValue Amt, 5653 SDValue &Lo, SDValue &Hi, 5654 DebugLoc dl) { 5655 // Expand the subcomponents. 5656 SDValue LHSL, LHSH; 5657 ExpandOp(Op, LHSL, LHSH); 5658 5659 SDValue Ops[] = { LHSL, LHSH, Amt }; 5660 MVT VT = LHSL.getValueType(); 5661 Lo = DAG.getNode(NodeOp, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5662 Hi = Lo.getValue(1); 5663} 5664 5665 5666/// ExpandShift - Try to find a clever way to expand this shift operation out to 5667/// smaller elements. If we can't find a way that is more efficient than a 5668/// libcall on this target, return false. Otherwise, return true with the 5669/// low-parts expanded into Lo and Hi. 5670bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, 5671 SDValue &Lo, SDValue &Hi, 5672 DebugLoc dl) { 5673 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5674 "This is not a shift!"); 5675 5676 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5677 SDValue ShAmt = LegalizeOp(Amt); 5678 MVT ShTy = ShAmt.getValueType(); 5679 unsigned ShBits = ShTy.getSizeInBits(); 5680 unsigned VTBits = Op.getValueType().getSizeInBits(); 5681 unsigned NVTBits = NVT.getSizeInBits(); 5682 5683 // Handle the case when Amt is an immediate. 5684 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) { 5685 unsigned Cst = CN->getZExtValue(); 5686 // Expand the incoming operand to be shifted, so that we have its parts 5687 SDValue InL, InH; 5688 ExpandOp(Op, InL, InH); 5689 switch(Opc) { 5690 case ISD::SHL: 5691 if (Cst > VTBits) { 5692 Lo = DAG.getConstant(0, NVT); 5693 Hi = DAG.getConstant(0, NVT); 5694 } else if (Cst > NVTBits) { 5695 Lo = DAG.getConstant(0, NVT); 5696 Hi = DAG.getNode(ISD::SHL, dl, 5697 NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5698 } else if (Cst == NVTBits) { 5699 Lo = DAG.getConstant(0, NVT); 5700 Hi = InL; 5701 } else { 5702 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)); 5703 Hi = DAG.getNode(ISD::OR, dl, NVT, 5704 DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)), 5705 DAG.getNode(ISD::SRL, dl, NVT, InL, 5706 DAG.getConstant(NVTBits-Cst, ShTy))); 5707 } 5708 return true; 5709 case ISD::SRL: 5710 if (Cst > VTBits) { 5711 Lo = DAG.getConstant(0, NVT); 5712 Hi = DAG.getConstant(0, NVT); 5713 } else if (Cst > NVTBits) { 5714 Lo = DAG.getNode(ISD::SRL, dl, NVT, 5715 InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5716 Hi = DAG.getConstant(0, NVT); 5717 } else if (Cst == NVTBits) { 5718 Lo = InH; 5719 Hi = DAG.getConstant(0, NVT); 5720 } else { 5721 Lo = DAG.getNode(ISD::OR, dl, NVT, 5722 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)), 5723 DAG.getNode(ISD::SHL, dl, NVT, InH, 5724 DAG.getConstant(NVTBits-Cst, ShTy))); 5725 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)); 5726 } 5727 return true; 5728 case ISD::SRA: 5729 if (Cst > VTBits) { 5730 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 5731 DAG.getConstant(NVTBits-1, ShTy)); 5732 } else if (Cst > NVTBits) { 5733 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 5734 DAG.getConstant(Cst-NVTBits, ShTy)); 5735 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 5736 DAG.getConstant(NVTBits-1, ShTy)); 5737 } else if (Cst == NVTBits) { 5738 Lo = InH; 5739 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 5740 DAG.getConstant(NVTBits-1, ShTy)); 5741 } else { 5742 Lo = DAG.getNode(ISD::OR, dl, NVT, 5743 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)), 5744 DAG.getNode(ISD::SHL, dl, 5745 NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5746 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst, ShTy)); 5747 } 5748 return true; 5749 } 5750 } 5751 5752 // Okay, the shift amount isn't constant. However, if we can tell that it is 5753 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5754 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5755 APInt KnownZero, KnownOne; 5756 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5757 5758 // If we know that if any of the high bits of the shift amount are one, then 5759 // we can do this as a couple of simple shifts. 5760 if (KnownOne.intersects(Mask)) { 5761 // Mask out the high bit, which we know is set. 5762 Amt = DAG.getNode(ISD::AND, dl, Amt.getValueType(), Amt, 5763 DAG.getConstant(~Mask, Amt.getValueType())); 5764 5765 // Expand the incoming operand to be shifted, so that we have its parts 5766 SDValue InL, InH; 5767 ExpandOp(Op, InL, InH); 5768 switch(Opc) { 5769 case ISD::SHL: 5770 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5771 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 5772 return true; 5773 case ISD::SRL: 5774 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5775 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 5776 return true; 5777 case ISD::SRA: 5778 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 5779 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5780 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 5781 return true; 5782 } 5783 } 5784 5785 // If we know that the high bits of the shift amount are all zero, then we can 5786 // do this as a couple of simple shifts. 5787 if ((KnownZero & Mask) == Mask) { 5788 // Compute 32-amt. 5789 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(), 5790 DAG.getConstant(NVTBits, Amt.getValueType()), 5791 Amt); 5792 5793 // Expand the incoming operand to be shifted, so that we have its parts 5794 SDValue InL, InH; 5795 ExpandOp(Op, InL, InH); 5796 switch(Opc) { 5797 case ISD::SHL: 5798 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); 5799 Hi = DAG.getNode(ISD::OR, dl, NVT, 5800 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt), 5801 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2)); 5802 return true; 5803 case ISD::SRL: 5804 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); 5805 Lo = DAG.getNode(ISD::OR, dl, NVT, 5806 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 5807 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2)); 5808 return true; 5809 case ISD::SRA: 5810 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); 5811 Lo = DAG.getNode(ISD::OR, dl, NVT, 5812 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 5813 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2)); 5814 return true; 5815 } 5816 } 5817 5818 return false; 5819} 5820 5821 5822// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5823// does not fit into a register, return the lo part and set the hi part to the 5824// by-reg argument. If it does fit into a single register, return the result 5825// and leave the Hi part unset. 5826SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 5827 bool isSigned, SDValue &Hi) { 5828 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5829 // The input chain to this libcall is the entry node of the function. 5830 // Legalizing the call will automatically add the previous call to the 5831 // dependence. 5832 SDValue InChain = DAG.getEntryNode(); 5833 5834 TargetLowering::ArgListTy Args; 5835 TargetLowering::ArgListEntry Entry; 5836 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5837 MVT ArgVT = Node->getOperand(i).getValueType(); 5838 const Type *ArgTy = ArgVT.getTypeForMVT(); 5839 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5840 Entry.isSExt = isSigned; 5841 Entry.isZExt = !isSigned; 5842 Args.push_back(Entry); 5843 } 5844 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 5845 TLI.getPointerTy()); 5846 5847 // Splice the libcall in wherever FindInputOutputChains tells us to. 5848 const Type *RetTy = Node->getValueType(0).getTypeForMVT(); 5849 std::pair<SDValue,SDValue> CallInfo = 5850 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 5851 CallingConv::C, false, Callee, Args, DAG, 5852 Node->getDebugLoc()); 5853 5854 // Legalize the call sequence, starting with the chain. This will advance 5855 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5856 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5857 LegalizeOp(CallInfo.second); 5858 SDValue Result; 5859 switch (getTypeAction(CallInfo.first.getValueType())) { 5860 default: assert(0 && "Unknown thing"); 5861 case Legal: 5862 Result = CallInfo.first; 5863 break; 5864 case Expand: 5865 ExpandOp(CallInfo.first, Result, Hi); 5866 break; 5867 } 5868 return Result; 5869} 5870 5871/// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation. 5872/// 5873SDValue SelectionDAGLegalize:: 5874LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op, 5875 DebugLoc dl) { 5876 bool isCustom = false; 5877 SDValue Tmp1; 5878 switch (getTypeAction(Op.getValueType())) { 5879 case Legal: 5880 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5881 Op.getValueType())) { 5882 default: assert(0 && "Unknown operation action!"); 5883 case TargetLowering::Custom: 5884 isCustom = true; 5885 // FALLTHROUGH 5886 case TargetLowering::Legal: 5887 Tmp1 = LegalizeOp(Op); 5888 if (Result.getNode()) 5889 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5890 else 5891 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl, 5892 DestTy, Tmp1); 5893 if (isCustom) { 5894 Tmp1 = TLI.LowerOperation(Result, DAG); 5895 if (Tmp1.getNode()) Result = Tmp1; 5896 } 5897 break; 5898 case TargetLowering::Expand: 5899 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy, dl); 5900 break; 5901 case TargetLowering::Promote: 5902 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned, dl); 5903 break; 5904 } 5905 break; 5906 case Expand: 5907 Result = ExpandIntToFP(isSigned, DestTy, Op, dl) ; 5908 break; 5909 case Promote: 5910 Tmp1 = PromoteOp(Op); 5911 if (isSigned) { 5912 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(), 5913 Tmp1, DAG.getValueType(Op.getValueType())); 5914 } else { 5915 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, 5916 Op.getValueType()); 5917 } 5918 if (Result.getNode()) 5919 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5920 else 5921 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl, 5922 DestTy, Tmp1); 5923 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 5924 break; 5925 } 5926 return Result; 5927} 5928 5929/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5930/// 5931SDValue SelectionDAGLegalize:: 5932ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) { 5933 MVT SourceVT = Source.getValueType(); 5934 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5935 5936 // Expand unsupported int-to-fp vector casts by unrolling them. 5937 if (DestTy.isVector()) { 5938 if (!ExpandSource) 5939 return LegalizeOp(UnrollVectorOp(Source)); 5940 MVT DestEltTy = DestTy.getVectorElementType(); 5941 if (DestTy.getVectorNumElements() == 1) { 5942 SDValue Scalar = ScalarizeVectorOp(Source); 5943 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned, 5944 DestEltTy, Scalar, dl); 5945 return DAG.getNode(ISD::BUILD_VECTOR, dl, DestTy, Result); 5946 } 5947 SDValue Lo, Hi; 5948 SplitVectorOp(Source, Lo, Hi); 5949 MVT SplitDestTy = MVT::getVectorVT(DestEltTy, 5950 DestTy.getVectorNumElements() / 2); 5951 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, 5952 Lo, dl); 5953 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, 5954 Hi, dl); 5955 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, DestTy, LoResult, 5956 HiResult)); 5957 } 5958 5959 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. 5960 if (!isSigned && SourceVT != MVT::i32) { 5961 // The integer value loaded will be incorrectly if the 'sign bit' of the 5962 // incoming integer is set. To handle this, we dynamically test to see if 5963 // it is set, and, if so, add a fudge factor. 5964 SDValue Hi; 5965 if (ExpandSource) { 5966 SDValue Lo; 5967 ExpandOp(Source, Lo, Hi); 5968 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, Lo, Hi); 5969 } else { 5970 // The comparison for the sign bit will use the entire operand. 5971 Hi = Source; 5972 } 5973 5974 // Check to see if the target has a custom way to lower this. If so, use 5975 // it. (Note we've already expanded the operand in this case.) 5976 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) { 5977 default: assert(0 && "This action not implemented for this operation!"); 5978 case TargetLowering::Legal: 5979 case TargetLowering::Expand: 5980 break; // This case is handled below. 5981 case TargetLowering::Custom: { 5982 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy, 5983 Source), DAG); 5984 if (NV.getNode()) 5985 return LegalizeOp(NV); 5986 break; // The target decided this was legal after all 5987 } 5988 } 5989 5990 // If this is unsigned, and not supported, first perform the conversion to 5991 // signed, then adjust the result if the sign bit is set. 5992 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source, dl); 5993 5994 SDValue SignSet = DAG.getSetCC(dl, 5995 TLI.getSetCCResultType(Hi.getValueType()), 5996 Hi, DAG.getConstant(0, Hi.getValueType()), 5997 ISD::SETLT); 5998 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5999 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 6000 SignSet, Four, Zero); 6001 uint64_t FF = 0x5f800000ULL; 6002 if (TLI.isLittleEndian()) FF <<= 32; 6003 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 6004 6005 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 6006 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6007 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 6008 Alignment = std::min(Alignment, 4u); 6009 SDValue FudgeInReg; 6010 if (DestTy == MVT::f32) 6011 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 6012 PseudoSourceValue::getConstantPool(), 0, 6013 false, Alignment); 6014 else if (DestTy.bitsGT(MVT::f32)) 6015 // FIXME: Avoid the extend by construction the right constantpool? 6016 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, dl, DestTy, DAG.getEntryNode(), 6017 CPIdx, 6018 PseudoSourceValue::getConstantPool(), 0, 6019 MVT::f32, false, Alignment); 6020 else 6021 assert(0 && "Unexpected conversion"); 6022 6023 MVT SCVT = SignedConv.getValueType(); 6024 if (SCVT != DestTy) { 6025 // Destination type needs to be expanded as well. The FADD now we are 6026 // constructing will be expanded into a libcall. 6027 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { 6028 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); 6029 SignedConv = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, 6030 SignedConv, SignedConv.getValue(1)); 6031 } 6032 SignedConv = DAG.getNode(ISD::BIT_CONVERT, dl, DestTy, SignedConv); 6033 } 6034 return DAG.getNode(ISD::FADD, dl, DestTy, SignedConv, FudgeInReg); 6035 } 6036 6037 // Check to see if the target has a custom way to lower this. If so, use it. 6038 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 6039 default: assert(0 && "This action not implemented for this operation!"); 6040 case TargetLowering::Legal: 6041 case TargetLowering::Expand: 6042 break; // This case is handled below. 6043 case TargetLowering::Custom: { 6044 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, 6045 Source), DAG); 6046 if (NV.getNode()) 6047 return LegalizeOp(NV); 6048 break; // The target decided this was legal after all 6049 } 6050 } 6051 6052 // Expand the source, then glue it back together for the call. We must expand 6053 // the source in case it is shared (this pass of legalize must traverse it). 6054 if (ExpandSource) { 6055 SDValue SrcLo, SrcHi; 6056 ExpandOp(Source, SrcLo, SrcHi); 6057 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, SrcLo, SrcHi); 6058 } 6059 6060 RTLIB::Libcall LC = isSigned ? 6061 RTLIB::getSINTTOFP(SourceVT, DestTy) : 6062 RTLIB::getUINTTOFP(SourceVT, DestTy); 6063 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type"); 6064 6065 Source = DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, Source); 6066 SDValue HiPart; 6067 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart); 6068 if (Result.getValueType() != DestTy && HiPart.getNode()) 6069 Result = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, Result, HiPart); 6070 return Result; 6071} 6072 6073/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 6074/// INT_TO_FP operation of the specified operand when the target requests that 6075/// we expand it. At this point, we know that the result and operand types are 6076/// legal for the target. 6077SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 6078 SDValue Op0, 6079 MVT DestVT, 6080 DebugLoc dl) { 6081 if (Op0.getValueType() == MVT::i32) { 6082 // simple 32-bit [signed|unsigned] integer to float/double expansion 6083 6084 // Get the stack frame index of a 8 byte buffer. 6085 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 6086 6087 // word offset constant for Hi/Lo address computation 6088 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 6089 // set up Hi and Lo (into buffer) address based on endian 6090 SDValue Hi = StackSlot; 6091 SDValue Lo = DAG.getNode(ISD::ADD, dl, 6092 TLI.getPointerTy(), StackSlot,WordOff); 6093 if (TLI.isLittleEndian()) 6094 std::swap(Hi, Lo); 6095 6096 // if signed map to unsigned space 6097 SDValue Op0Mapped; 6098 if (isSigned) { 6099 // constant used to invert sign bit (signed to unsigned mapping) 6100 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 6101 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 6102 } else { 6103 Op0Mapped = Op0; 6104 } 6105 // store the lo of the constructed double - based on integer input 6106 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 6107 Op0Mapped, Lo, NULL, 0); 6108 // initial hi portion of constructed double 6109 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 6110 // store the hi of the constructed double - biased exponent 6111 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0); 6112 // load the constructed double 6113 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0); 6114 // FP constant to bias correct the final result 6115 SDValue Bias = DAG.getConstantFP(isSigned ? 6116 BitsToDouble(0x4330000080000000ULL) 6117 : BitsToDouble(0x4330000000000000ULL), 6118 MVT::f64); 6119 // subtract the bias 6120 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 6121 // final result 6122 SDValue Result; 6123 // handle final rounding 6124 if (DestVT == MVT::f64) { 6125 // do nothing 6126 Result = Sub; 6127 } else if (DestVT.bitsLT(MVT::f64)) { 6128 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 6129 DAG.getIntPtrConstant(0)); 6130 } else if (DestVT.bitsGT(MVT::f64)) { 6131 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 6132 } 6133 return Result; 6134 } 6135 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 6136 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 6137 6138 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 6139 Op0, DAG.getConstant(0, Op0.getValueType()), 6140 ISD::SETLT); 6141 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 6142 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 6143 SignSet, Four, Zero); 6144 6145 // If the sign bit of the integer is set, the large number will be treated 6146 // as a negative number. To counteract this, the dynamic code adds an 6147 // offset depending on the data type. 6148 uint64_t FF; 6149 switch (Op0.getValueType().getSimpleVT()) { 6150 default: assert(0 && "Unsupported integer type!"); 6151 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 6152 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 6153 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 6154 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 6155 } 6156 if (TLI.isLittleEndian()) FF <<= 32; 6157 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 6158 6159 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 6160 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6161 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 6162 Alignment = std::min(Alignment, 4u); 6163 SDValue FudgeInReg; 6164 if (DestVT == MVT::f32) 6165 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 6166 PseudoSourceValue::getConstantPool(), 0, 6167 false, Alignment); 6168 else { 6169 FudgeInReg = 6170 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 6171 DAG.getEntryNode(), CPIdx, 6172 PseudoSourceValue::getConstantPool(), 0, 6173 MVT::f32, false, Alignment)); 6174 } 6175 6176 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 6177} 6178 6179/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 6180/// *INT_TO_FP operation of the specified operand when the target requests that 6181/// we promote it. At this point, we know that the result and operand types are 6182/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 6183/// operation that takes a larger input. 6184SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 6185 MVT DestVT, 6186 bool isSigned, 6187 DebugLoc dl) { 6188 // First step, figure out the appropriate *INT_TO_FP operation to use. 6189 MVT NewInTy = LegalOp.getValueType(); 6190 6191 unsigned OpToUse = 0; 6192 6193 // Scan for the appropriate larger type to use. 6194 while (1) { 6195 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 6196 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 6197 6198 // If the target supports SINT_TO_FP of this type, use it. 6199 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 6200 default: break; 6201 case TargetLowering::Legal: 6202 if (!TLI.isTypeLegal(NewInTy)) 6203 break; // Can't use this datatype. 6204 // FALL THROUGH. 6205 case TargetLowering::Custom: 6206 OpToUse = ISD::SINT_TO_FP; 6207 break; 6208 } 6209 if (OpToUse) break; 6210 if (isSigned) continue; 6211 6212 // If the target supports UINT_TO_FP of this type, use it. 6213 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 6214 default: break; 6215 case TargetLowering::Legal: 6216 if (!TLI.isTypeLegal(NewInTy)) 6217 break; // Can't use this datatype. 6218 // FALL THROUGH. 6219 case TargetLowering::Custom: 6220 OpToUse = ISD::UINT_TO_FP; 6221 break; 6222 } 6223 if (OpToUse) break; 6224 6225 // Otherwise, try a larger type. 6226 } 6227 6228 // Okay, we found the operation and type to use. Zero extend our input to the 6229 // desired type then run the operation on it. 6230 return DAG.getNode(OpToUse, dl, DestVT, 6231 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 6232 dl, NewInTy, LegalOp)); 6233} 6234 6235/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 6236/// FP_TO_*INT operation of the specified operand when the target requests that 6237/// we promote it. At this point, we know that the result and operand types are 6238/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 6239/// operation that returns a larger result. 6240SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 6241 MVT DestVT, 6242 bool isSigned, 6243 DebugLoc dl) { 6244 // First step, figure out the appropriate FP_TO*INT operation to use. 6245 MVT NewOutTy = DestVT; 6246 6247 unsigned OpToUse = 0; 6248 6249 // Scan for the appropriate larger type to use. 6250 while (1) { 6251 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 6252 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 6253 6254 // If the target supports FP_TO_SINT returning this type, use it. 6255 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 6256 default: break; 6257 case TargetLowering::Legal: 6258 if (!TLI.isTypeLegal(NewOutTy)) 6259 break; // Can't use this datatype. 6260 // FALL THROUGH. 6261 case TargetLowering::Custom: 6262 OpToUse = ISD::FP_TO_SINT; 6263 break; 6264 } 6265 if (OpToUse) break; 6266 6267 // If the target supports FP_TO_UINT of this type, use it. 6268 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 6269 default: break; 6270 case TargetLowering::Legal: 6271 if (!TLI.isTypeLegal(NewOutTy)) 6272 break; // Can't use this datatype. 6273 // FALL THROUGH. 6274 case TargetLowering::Custom: 6275 OpToUse = ISD::FP_TO_UINT; 6276 break; 6277 } 6278 if (OpToUse) break; 6279 6280 // Otherwise, try a larger type. 6281 } 6282 6283 6284 // Okay, we found the operation and type to use. 6285 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 6286 6287 // If the operation produces an invalid type, it must be custom lowered. Use 6288 // the target lowering hooks to expand it. Just keep the low part of the 6289 // expanded operation, we know that we're truncating anyway. 6290 if (getTypeAction(NewOutTy) == Expand) { 6291 SmallVector<SDValue, 2> Results; 6292 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG); 6293 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!"); 6294 Operation = Results[0]; 6295 } 6296 6297 // Truncate the result of the extended FP_TO_*INT operation to the desired 6298 // size. 6299 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 6300} 6301 6302/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 6303/// 6304SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 6305 MVT VT = Op.getValueType(); 6306 MVT SHVT = TLI.getShiftAmountTy(); 6307 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 6308 switch (VT.getSimpleVT()) { 6309 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 6310 case MVT::i16: 6311 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 6312 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 6313 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 6314 case MVT::i32: 6315 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 6316 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 6317 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 6318 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 6319 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 6320 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 6321 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 6322 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 6323 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 6324 case MVT::i64: 6325 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 6326 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 6327 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 6328 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 6329 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 6330 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 6331 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 6332 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 6333 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 6334 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 6335 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 6336 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 6337 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 6338 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 6339 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 6340 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 6341 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 6342 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 6343 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 6344 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 6345 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 6346 } 6347} 6348 6349/// ExpandBitCount - Expand the specified bitcount instruction into operations. 6350/// 6351SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 6352 DebugLoc dl) { 6353 switch (Opc) { 6354 default: assert(0 && "Cannot expand this yet!"); 6355 case ISD::CTPOP: { 6356 static const uint64_t mask[6] = { 6357 0x5555555555555555ULL, 0x3333333333333333ULL, 6358 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 6359 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 6360 }; 6361 MVT VT = Op.getValueType(); 6362 MVT ShVT = TLI.getShiftAmountTy(); 6363 unsigned len = VT.getSizeInBits(); 6364 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 6365 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 6366 unsigned EltSize = VT.isVector() ? 6367 VT.getVectorElementType().getSizeInBits() : len; 6368 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 6369 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 6370 Op = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 6371 DAG.getNode(ISD::AND, dl, VT, 6372 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 6373 Tmp2)); 6374 } 6375 return Op; 6376 } 6377 case ISD::CTLZ: { 6378 // for now, we do this: 6379 // x = x | (x >> 1); 6380 // x = x | (x >> 2); 6381 // ... 6382 // x = x | (x >>16); 6383 // x = x | (x >>32); // for 64-bit input 6384 // return popcount(~x); 6385 // 6386 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 6387 MVT VT = Op.getValueType(); 6388 MVT ShVT = TLI.getShiftAmountTy(); 6389 unsigned len = VT.getSizeInBits(); 6390 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 6391 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 6392 Op = DAG.getNode(ISD::OR, dl, VT, Op, 6393 DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 6394 } 6395 Op = DAG.getNOT(dl, Op, VT); 6396 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 6397 } 6398 case ISD::CTTZ: { 6399 // for now, we use: { return popcount(~x & (x - 1)); } 6400 // unless the target has ctlz but not ctpop, in which case we use: 6401 // { return 32 - nlz(~x & (x-1)); } 6402 // see also http://www.hackersdelight.org/HDcode/ntz.cc 6403 MVT VT = Op.getValueType(); 6404 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 6405 DAG.getNOT(dl, Op, VT), 6406 DAG.getNode(ISD::SUB, dl, VT, Op, 6407 DAG.getConstant(1, VT))); 6408 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 6409 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 6410 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 6411 return DAG.getNode(ISD::SUB, dl, VT, 6412 DAG.getConstant(VT.getSizeInBits(), VT), 6413 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 6414 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 6415 } 6416 } 6417} 6418 6419/// ExpandOp - Expand the specified SDValue into its two component pieces 6420/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 6421/// LegalizedNodes map is filled in for any results that are not expanded, the 6422/// ExpandedNodes map is filled in for any results that are expanded, and the 6423/// Lo/Hi values are returned. 6424void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){ 6425 MVT VT = Op.getValueType(); 6426 MVT NVT = TLI.getTypeToTransformTo(VT); 6427 SDNode *Node = Op.getNode(); 6428 DebugLoc dl = Node->getDebugLoc(); 6429 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 6430 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() || 6431 VT.isVector()) && "Cannot expand to FP value or to larger int value!"); 6432 6433 // See if we already expanded it. 6434 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I 6435 = ExpandedNodes.find(Op); 6436 if (I != ExpandedNodes.end()) { 6437 Lo = I->second.first; 6438 Hi = I->second.second; 6439 return; 6440 } 6441 6442 switch (Node->getOpcode()) { 6443 case ISD::CopyFromReg: 6444 assert(0 && "CopyFromReg must be legal!"); 6445 case ISD::FP_ROUND_INREG: 6446 if (VT == MVT::ppcf128 && 6447 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 6448 TargetLowering::Custom) { 6449 SDValue SrcLo, SrcHi, Src; 6450 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 6451 Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi); 6452 SDValue Result = TLI.LowerOperation( 6453 DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src, Op.getOperand(1)), DAG); 6454 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR); 6455 Lo = Result.getNode()->getOperand(0); 6456 Hi = Result.getNode()->getOperand(1); 6457 break; 6458 } 6459 // fall through 6460 default: 6461#ifndef NDEBUG 6462 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 6463#endif 6464 assert(0 && "Do not know how to expand this operator!"); 6465 abort(); 6466 case ISD::EXTRACT_ELEMENT: 6467 ExpandOp(Node->getOperand(0), Lo, Hi); 6468 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) 6469 return ExpandOp(Hi, Lo, Hi); 6470 return ExpandOp(Lo, Lo, Hi); 6471 case ISD::EXTRACT_VECTOR_ELT: 6472 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 6473 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 6474 return ExpandOp(Lo, Lo, Hi); 6475 case ISD::UNDEF: 6476 Lo = DAG.getNode(ISD::UNDEF, dl, NVT); 6477 Hi = DAG.getNode(ISD::UNDEF, dl, NVT); 6478 break; 6479 case ISD::Constant: { 6480 unsigned NVTBits = NVT.getSizeInBits(); 6481 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 6482 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 6483 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 6484 break; 6485 } 6486 case ISD::ConstantFP: { 6487 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 6488 if (CFP->getValueType(0) == MVT::ppcf128) { 6489 APInt api = CFP->getValueAPF().bitcastToAPInt(); 6490 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 6491 MVT::f64); 6492 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 6493 MVT::f64); 6494 break; 6495 } 6496 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 6497 if (getTypeAction(Lo.getValueType()) == Expand) 6498 ExpandOp(Lo, Lo, Hi); 6499 break; 6500 } 6501 case ISD::BUILD_PAIR: 6502 // Return the operands. 6503 Lo = Node->getOperand(0); 6504 Hi = Node->getOperand(1); 6505 break; 6506 6507 case ISD::MERGE_VALUES: 6508 if (Node->getNumValues() == 1) { 6509 ExpandOp(Op.getOperand(0), Lo, Hi); 6510 break; 6511 } 6512 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 6513 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 && 6514 Op.getValue(1).getValueType() == MVT::Other && 6515 "unhandled MERGE_VALUES"); 6516 ExpandOp(Op.getOperand(0), Lo, Hi); 6517 // Remember that we legalized the chain. 6518 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 6519 break; 6520 6521 case ISD::SIGN_EXTEND_INREG: 6522 ExpandOp(Node->getOperand(0), Lo, Hi); 6523 // sext_inreg the low part if needed. 6524 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Lo, Node->getOperand(1)); 6525 6526 // The high part gets the sign extension from the lo-part. This handles 6527 // things like sextinreg V:i64 from i8. 6528 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 6529 DAG.getConstant(NVT.getSizeInBits()-1, 6530 TLI.getShiftAmountTy())); 6531 break; 6532 6533 case ISD::BSWAP: { 6534 ExpandOp(Node->getOperand(0), Lo, Hi); 6535 SDValue TempLo = DAG.getNode(ISD::BSWAP, dl, NVT, Hi); 6536 Hi = DAG.getNode(ISD::BSWAP, dl, NVT, Lo); 6537 Lo = TempLo; 6538 break; 6539 } 6540 6541 case ISD::CTPOP: 6542 ExpandOp(Node->getOperand(0), Lo, Hi); 6543 Lo = DAG.getNode(ISD::ADD, dl, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 6544 DAG.getNode(ISD::CTPOP, dl, NVT, Lo), 6545 DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); 6546 Hi = DAG.getConstant(0, NVT); 6547 break; 6548 6549 case ISD::CTLZ: { 6550 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 6551 ExpandOp(Node->getOperand(0), Lo, Hi); 6552 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 6553 SDValue HLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi); 6554 SDValue TopNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), HLZ, 6555 BitsC, ISD::SETNE); 6556 SDValue LowPart = DAG.getNode(ISD::CTLZ, dl, NVT, Lo); 6557 LowPart = DAG.getNode(ISD::ADD, dl, NVT, LowPart, BitsC); 6558 6559 Lo = DAG.getNode(ISD::SELECT, dl, NVT, TopNotZero, HLZ, LowPart); 6560 Hi = DAG.getConstant(0, NVT); 6561 break; 6562 } 6563 6564 case ISD::CTTZ: { 6565 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 6566 ExpandOp(Node->getOperand(0), Lo, Hi); 6567 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 6568 SDValue LTZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo); 6569 SDValue BotNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), LTZ, 6570 BitsC, ISD::SETNE); 6571 SDValue HiPart = DAG.getNode(ISD::CTTZ, dl, NVT, Hi); 6572 HiPart = DAG.getNode(ISD::ADD, dl, NVT, HiPart, BitsC); 6573 6574 Lo = DAG.getNode(ISD::SELECT, dl, NVT, BotNotZero, LTZ, HiPart); 6575 Hi = DAG.getConstant(0, NVT); 6576 break; 6577 } 6578 6579 case ISD::VAARG: { 6580 SDValue Ch = Node->getOperand(0); // Legalize the chain. 6581 SDValue Ptr = Node->getOperand(1); // Legalize the pointer. 6582 Lo = DAG.getVAArg(NVT, dl, Ch, Ptr, Node->getOperand(2)); 6583 Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, Node->getOperand(2)); 6584 6585 // Remember that we legalized the chain. 6586 Hi = LegalizeOp(Hi); 6587 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 6588 if (TLI.isBigEndian()) 6589 std::swap(Lo, Hi); 6590 break; 6591 } 6592 6593 case ISD::LOAD: { 6594 LoadSDNode *LD = cast<LoadSDNode>(Node); 6595 SDValue Ch = LD->getChain(); // Legalize the chain. 6596 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer. 6597 ISD::LoadExtType ExtType = LD->getExtensionType(); 6598 const Value *SV = LD->getSrcValue(); 6599 int SVOffset = LD->getSrcValueOffset(); 6600 unsigned Alignment = LD->getAlignment(); 6601 bool isVolatile = LD->isVolatile(); 6602 6603 if (ExtType == ISD::NON_EXTLOAD) { 6604 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset, 6605 isVolatile, Alignment); 6606 if (VT == MVT::f32 || VT == MVT::f64) { 6607 // f32->i32 or f64->i64 one to one expansion. 6608 // Remember that we legalized the chain. 6609 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 6610 // Recursively expand the new load. 6611 if (getTypeAction(NVT) == Expand) 6612 ExpandOp(Lo, Lo, Hi); 6613 break; 6614 } 6615 6616 // Increment the pointer to the other half. 6617 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; 6618 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 6619 DAG.getIntPtrConstant(IncrementSize)); 6620 SVOffset += IncrementSize; 6621 Alignment = MinAlign(Alignment, IncrementSize); 6622 Hi = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset, 6623 isVolatile, Alignment); 6624 6625 // Build a factor node to remember that this load is independent of the 6626 // other one. 6627 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 6628 Hi.getValue(1)); 6629 6630 // Remember that we legalized the chain. 6631 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6632 if (TLI.isBigEndian()) 6633 std::swap(Lo, Hi); 6634 } else { 6635 MVT EVT = LD->getMemoryVT(); 6636 6637 if ((VT == MVT::f64 && EVT == MVT::f32) || 6638 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 6639 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 6640 SDValue Load = DAG.getLoad(EVT, dl, Ch, Ptr, SV, 6641 SVOffset, isVolatile, Alignment); 6642 // Remember that we legalized the chain. 6643 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1))); 6644 ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi); 6645 break; 6646 } 6647 6648 if (EVT == NVT) 6649 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, 6650 SVOffset, isVolatile, Alignment); 6651 else 6652 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, SV, 6653 SVOffset, EVT, isVolatile, 6654 Alignment); 6655 6656 // Remember that we legalized the chain. 6657 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 6658 6659 if (ExtType == ISD::SEXTLOAD) { 6660 // The high part is obtained by SRA'ing all but one of the bits of the 6661 // lo part. 6662 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6663 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 6664 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6665 } else if (ExtType == ISD::ZEXTLOAD) { 6666 // The high part is just a zero. 6667 Hi = DAG.getConstant(0, NVT); 6668 } else /* if (ExtType == ISD::EXTLOAD) */ { 6669 // The high part is undefined. 6670 Hi = DAG.getNode(ISD::UNDEF, dl, NVT); 6671 } 6672 } 6673 break; 6674 } 6675 case ISD::AND: 6676 case ISD::OR: 6677 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 6678 SDValue LL, LH, RL, RH; 6679 ExpandOp(Node->getOperand(0), LL, LH); 6680 ExpandOp(Node->getOperand(1), RL, RH); 6681 Lo = DAG.getNode(Node->getOpcode(), dl, NVT, LL, RL); 6682 Hi = DAG.getNode(Node->getOpcode(), dl, NVT, LH, RH); 6683 break; 6684 } 6685 case ISD::SELECT: { 6686 SDValue LL, LH, RL, RH; 6687 ExpandOp(Node->getOperand(1), LL, LH); 6688 ExpandOp(Node->getOperand(2), RL, RH); 6689 if (getTypeAction(NVT) == Expand) 6690 NVT = TLI.getTypeToExpandTo(NVT); 6691 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LL, RL); 6692 if (VT != MVT::f32) 6693 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LH, RH); 6694 break; 6695 } 6696 case ISD::SELECT_CC: { 6697 SDValue TL, TH, FL, FH; 6698 ExpandOp(Node->getOperand(2), TL, TH); 6699 ExpandOp(Node->getOperand(3), FL, FH); 6700 if (getTypeAction(NVT) == Expand) 6701 NVT = TLI.getTypeToExpandTo(NVT); 6702 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0), 6703 Node->getOperand(1), TL, FL, Node->getOperand(4)); 6704 if (VT != MVT::f32) 6705 Hi = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0), 6706 Node->getOperand(1), TH, FH, Node->getOperand(4)); 6707 break; 6708 } 6709 case ISD::ANY_EXTEND: 6710 // The low part is any extension of the input (which degenerates to a copy). 6711 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0)); 6712 // The high part is undefined. 6713 Hi = DAG.getNode(ISD::UNDEF, dl, NVT); 6714 break; 6715 case ISD::SIGN_EXTEND: { 6716 // The low part is just a sign extension of the input (which degenerates to 6717 // a copy). 6718 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Node->getOperand(0)); 6719 6720 // The high part is obtained by SRA'ing all but one of the bits of the lo 6721 // part. 6722 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6723 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 6724 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6725 break; 6726 } 6727 case ISD::ZERO_EXTEND: 6728 // The low part is just a zero extension of the input (which degenerates to 6729 // a copy). 6730 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 6731 6732 // The high part is just a zero. 6733 Hi = DAG.getConstant(0, NVT); 6734 break; 6735 6736 case ISD::TRUNCATE: { 6737 // The input value must be larger than this value. Expand *it*. 6738 SDValue NewLo; 6739 ExpandOp(Node->getOperand(0), NewLo, Hi); 6740 6741 // The low part is now either the right size, or it is closer. If not the 6742 // right size, make an illegal truncate so we recursively expand it. 6743 if (NewLo.getValueType() != Node->getValueType(0)) 6744 NewLo = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), NewLo); 6745 ExpandOp(NewLo, Lo, Hi); 6746 break; 6747 } 6748 6749 case ISD::BIT_CONVERT: { 6750 SDValue Tmp; 6751 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6752 // If the target wants to, allow it to lower this itself. 6753 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6754 case Expand: assert(0 && "cannot expand FP!"); 6755 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6756 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6757 } 6758 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp), DAG); 6759 } 6760 6761 // f32 / f64 must be expanded to i32 / i64. 6762 if (VT == MVT::f32 || VT == MVT::f64) { 6763 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 6764 if (getTypeAction(NVT) == Expand) 6765 ExpandOp(Lo, Lo, Hi); 6766 break; 6767 } 6768 6769 // If source operand will be expanded to the same type as VT, i.e. 6770 // i64 <- f64, i32 <- f32, expand the source operand instead. 6771 MVT VT0 = Node->getOperand(0).getValueType(); 6772 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6773 ExpandOp(Node->getOperand(0), Lo, Hi); 6774 break; 6775 } 6776 6777 // Turn this into a load/store pair by default. 6778 if (Tmp.getNode() == 0) 6779 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT, dl); 6780 6781 ExpandOp(Tmp, Lo, Hi); 6782 break; 6783 } 6784 6785 case ISD::READCYCLECOUNTER: { 6786 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6787 TargetLowering::Custom && 6788 "Must custom expand ReadCycleCounter"); 6789 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6790 assert(Tmp.getNode() && "Node must be custom expanded!"); 6791 ExpandOp(Tmp.getValue(0), Lo, Hi); 6792 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6793 LegalizeOp(Tmp.getValue(1))); 6794 break; 6795 } 6796 6797 case ISD::ATOMIC_CMP_SWAP: { 6798 // This operation does not need a loop. 6799 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6800 assert(Tmp.getNode() && "Node must be custom expanded!"); 6801 ExpandOp(Tmp.getValue(0), Lo, Hi); 6802 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6803 LegalizeOp(Tmp.getValue(1))); 6804 break; 6805 } 6806 6807 case ISD::ATOMIC_LOAD_ADD: 6808 case ISD::ATOMIC_LOAD_SUB: 6809 case ISD::ATOMIC_LOAD_AND: 6810 case ISD::ATOMIC_LOAD_OR: 6811 case ISD::ATOMIC_LOAD_XOR: 6812 case ISD::ATOMIC_LOAD_NAND: 6813 case ISD::ATOMIC_SWAP: { 6814 // These operations require a loop to be generated. We can't do that yet, 6815 // so substitute a target-dependent pseudo and expand that later. 6816 SDValue In2Lo, In2Hi, In2; 6817 ExpandOp(Op.getOperand(2), In2Lo, In2Hi); 6818 In2 = DAG.getNode(ISD::BUILD_PAIR, dl, VT, In2Lo, In2Hi); 6819 AtomicSDNode* Anode = cast<AtomicSDNode>(Node); 6820 SDValue Replace = 6821 DAG.getAtomic(Op.getOpcode(), dl, Anode->getMemoryVT(), 6822 Op.getOperand(0), Op.getOperand(1), In2, 6823 Anode->getSrcValue(), Anode->getAlignment()); 6824 SDValue Result = TLI.LowerOperation(Replace, DAG); 6825 ExpandOp(Result.getValue(0), Lo, Hi); 6826 // Remember that we legalized the chain. 6827 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1))); 6828 break; 6829 } 6830 6831 // These operators cannot be expanded directly, emit them as calls to 6832 // library functions. 6833 case ISD::FP_TO_SINT: { 6834 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6835 SDValue Op; 6836 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6837 case Expand: assert(0 && "cannot expand FP!"); 6838 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6839 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6840 } 6841 6842 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op), DAG); 6843 6844 // Now that the custom expander is done, expand the result, which is still 6845 // VT. 6846 if (Op.getNode()) { 6847 ExpandOp(Op, Lo, Hi); 6848 break; 6849 } 6850 } 6851 6852 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(), 6853 VT); 6854 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!"); 6855 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6856 break; 6857 } 6858 6859 case ISD::FP_TO_UINT: { 6860 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6861 SDValue Op; 6862 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6863 case Expand: assert(0 && "cannot expand FP!"); 6864 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6865 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6866 } 6867 6868 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op), DAG); 6869 6870 // Now that the custom expander is done, expand the result. 6871 if (Op.getNode()) { 6872 ExpandOp(Op, Lo, Hi); 6873 break; 6874 } 6875 } 6876 6877 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(), 6878 VT); 6879 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 6880 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6881 break; 6882 } 6883 6884 case ISD::SHL: { 6885 // If the target wants custom lowering, do so. 6886 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6887 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6888 SDValue Op = DAG.getNode(ISD::SHL, dl, VT, Node->getOperand(0), ShiftAmt); 6889 Op = TLI.LowerOperation(Op, DAG); 6890 if (Op.getNode()) { 6891 // Now that the custom expander is done, expand the result, which is 6892 // still VT. 6893 ExpandOp(Op, Lo, Hi); 6894 break; 6895 } 6896 } 6897 6898 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6899 // this X << 1 as X+X. 6900 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6901 if (ShAmt->getAPIntValue() == 1 && 6902 TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) && 6903 TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) { 6904 SDValue LoOps[2], HiOps[3]; 6905 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6906 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6907 LoOps[1] = LoOps[0]; 6908 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 6909 6910 HiOps[1] = HiOps[0]; 6911 HiOps[2] = Lo.getValue(1); 6912 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 6913 break; 6914 } 6915 } 6916 6917 // If we can emit an efficient shift operation, do so now. 6918 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl)) 6919 break; 6920 6921 // If this target supports SHL_PARTS, use it. 6922 TargetLowering::LegalizeAction Action = 6923 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6924 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6925 Action == TargetLowering::Custom) { 6926 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), 6927 ShiftAmt, Lo, Hi, dl); 6928 break; 6929 } 6930 6931 // Otherwise, emit a libcall. 6932 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi); 6933 break; 6934 } 6935 6936 case ISD::SRA: { 6937 // If the target wants custom lowering, do so. 6938 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6939 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6940 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6941 Op = TLI.LowerOperation(Op, DAG); 6942 if (Op.getNode()) { 6943 // Now that the custom expander is done, expand the result, which is 6944 // still VT. 6945 ExpandOp(Op, Lo, Hi); 6946 break; 6947 } 6948 } 6949 6950 // If we can emit an efficient shift operation, do so now. 6951 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi, dl)) 6952 break; 6953 6954 // If this target supports SRA_PARTS, use it. 6955 TargetLowering::LegalizeAction Action = 6956 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6957 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6958 Action == TargetLowering::Custom) { 6959 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), 6960 ShiftAmt, Lo, Hi, dl); 6961 break; 6962 } 6963 6964 // Otherwise, emit a libcall. 6965 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi); 6966 break; 6967 } 6968 6969 case ISD::SRL: { 6970 // If the target wants custom lowering, do so. 6971 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6972 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6973 SDValue Op = DAG.getNode(ISD::SRL, dl, VT, Node->getOperand(0), ShiftAmt); 6974 Op = TLI.LowerOperation(Op, DAG); 6975 if (Op.getNode()) { 6976 // Now that the custom expander is done, expand the result, which is 6977 // still VT. 6978 ExpandOp(Op, Lo, Hi); 6979 break; 6980 } 6981 } 6982 6983 // If we can emit an efficient shift operation, do so now. 6984 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl)) 6985 break; 6986 6987 // If this target supports SRL_PARTS, use it. 6988 TargetLowering::LegalizeAction Action = 6989 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6990 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6991 Action == TargetLowering::Custom) { 6992 ExpandShiftParts(ISD::SRL_PARTS, 6993 Node->getOperand(0), ShiftAmt, Lo, Hi, dl); 6994 break; 6995 } 6996 6997 // Otherwise, emit a libcall. 6998 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi); 6999 break; 7000 } 7001 7002 case ISD::ADD: 7003 case ISD::SUB: { 7004 // If the target wants to custom expand this, let them. 7005 if (TLI.getOperationAction(Node->getOpcode(), VT) == 7006 TargetLowering::Custom) { 7007 SDValue Result = TLI.LowerOperation(Op, DAG); 7008 if (Result.getNode()) { 7009 ExpandOp(Result, Lo, Hi); 7010 break; 7011 } 7012 } 7013 // Expand the subcomponents. 7014 SDValue LHSL, LHSH, RHSL, RHSH; 7015 ExpandOp(Node->getOperand(0), LHSL, LHSH); 7016 ExpandOp(Node->getOperand(1), RHSL, RHSH); 7017 SDValue LoOps[2], HiOps[3]; 7018 LoOps[0] = LHSL; 7019 LoOps[1] = RHSL; 7020 HiOps[0] = LHSH; 7021 HiOps[1] = RHSH; 7022 7023 //cascaded check to see if any smaller size has a a carry flag. 7024 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC; 7025 bool hasCarry = false; 7026 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) { 7027 MVT AVT = MVT::getIntegerVT(BitSize); 7028 if (TLI.isOperationLegalOrCustom(OpV, AVT)) { 7029 hasCarry = true; 7030 break; 7031 } 7032 } 7033 7034 if(hasCarry) { 7035 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 7036 if (Node->getOpcode() == ISD::ADD) { 7037 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 7038 HiOps[2] = Lo.getValue(1); 7039 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 7040 } else { 7041 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 7042 HiOps[2] = Lo.getValue(1); 7043 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 7044 } 7045 break; 7046 } else { 7047 if (Node->getOpcode() == ISD::ADD) { 7048 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); 7049 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); 7050 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 7051 Lo, LoOps[0], ISD::SETULT); 7052 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1, 7053 DAG.getConstant(1, NVT), 7054 DAG.getConstant(0, NVT)); 7055 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 7056 Lo, LoOps[1], ISD::SETULT); 7057 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2, 7058 DAG.getConstant(1, NVT), 7059 Carry1); 7060 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); 7061 } else { 7062 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); 7063 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); 7064 SDValue Cmp = DAG.getSetCC(dl, NVT, LoOps[0], LoOps[1], ISD::SETULT); 7065 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, 7066 DAG.getConstant(1, NVT), 7067 DAG.getConstant(0, NVT)); 7068 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); 7069 } 7070 break; 7071 } 7072 } 7073 7074 case ISD::ADDC: 7075 case ISD::SUBC: { 7076 // Expand the subcomponents. 7077 SDValue LHSL, LHSH, RHSL, RHSH; 7078 ExpandOp(Node->getOperand(0), LHSL, LHSH); 7079 ExpandOp(Node->getOperand(1), RHSL, RHSH); 7080 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 7081 SDValue LoOps[2] = { LHSL, RHSL }; 7082 SDValue HiOps[3] = { LHSH, RHSH }; 7083 7084 if (Node->getOpcode() == ISD::ADDC) { 7085 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 7086 HiOps[2] = Lo.getValue(1); 7087 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 7088 } else { 7089 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 7090 HiOps[2] = Lo.getValue(1); 7091 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 7092 } 7093 // Remember that we legalized the flag. 7094 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 7095 break; 7096 } 7097 case ISD::ADDE: 7098 case ISD::SUBE: { 7099 // Expand the subcomponents. 7100 SDValue LHSL, LHSH, RHSL, RHSH; 7101 ExpandOp(Node->getOperand(0), LHSL, LHSH); 7102 ExpandOp(Node->getOperand(1), RHSL, RHSH); 7103 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 7104 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 7105 SDValue HiOps[3] = { LHSH, RHSH }; 7106 7107 Lo = DAG.getNode(Node->getOpcode(), dl, VTList, LoOps, 3); 7108 HiOps[2] = Lo.getValue(1); 7109 Hi = DAG.getNode(Node->getOpcode(), dl, VTList, HiOps, 3); 7110 7111 // Remember that we legalized the flag. 7112 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 7113 break; 7114 } 7115 case ISD::MUL: { 7116 // If the target wants to custom expand this, let them. 7117 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 7118 SDValue New = TLI.LowerOperation(Op, DAG); 7119 if (New.getNode()) { 7120 ExpandOp(New, Lo, Hi); 7121 break; 7122 } 7123 } 7124 7125 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); 7126 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); 7127 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); 7128 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); 7129 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 7130 SDValue LL, LH, RL, RH; 7131 ExpandOp(Node->getOperand(0), LL, LH); 7132 ExpandOp(Node->getOperand(1), RL, RH); 7133 unsigned OuterBitSize = Op.getValueSizeInBits(); 7134 unsigned InnerBitSize = RH.getValueSizeInBits(); 7135 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 7136 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 7137 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 7138 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 7139 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 7140 // The inputs are both zero-extended. 7141 if (HasUMUL_LOHI) { 7142 // We can emit a umul_lohi. 7143 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 7144 Hi = SDValue(Lo.getNode(), 1); 7145 break; 7146 } 7147 if (HasMULHU) { 7148 // We can emit a mulhu+mul. 7149 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 7150 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 7151 break; 7152 } 7153 } 7154 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 7155 // The input values are both sign-extended. 7156 if (HasSMUL_LOHI) { 7157 // We can emit a smul_lohi. 7158 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 7159 Hi = SDValue(Lo.getNode(), 1); 7160 break; 7161 } 7162 if (HasMULHS) { 7163 // We can emit a mulhs+mul. 7164 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 7165 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); 7166 break; 7167 } 7168 } 7169 if (HasUMUL_LOHI) { 7170 // Lo,Hi = umul LHS, RHS. 7171 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, 7172 DAG.getVTList(NVT, NVT), LL, RL); 7173 Lo = UMulLOHI; 7174 Hi = UMulLOHI.getValue(1); 7175 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 7176 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 7177 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 7178 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 7179 break; 7180 } 7181 if (HasMULHU) { 7182 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 7183 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 7184 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 7185 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 7186 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 7187 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 7188 break; 7189 } 7190 } 7191 7192 // If nothing else, we can make a libcall. 7193 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi); 7194 break; 7195 } 7196 case ISD::SDIV: 7197 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi); 7198 break; 7199 case ISD::UDIV: 7200 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi); 7201 break; 7202 case ISD::SREM: 7203 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi); 7204 break; 7205 case ISD::UREM: 7206 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi); 7207 break; 7208 7209 case ISD::FADD: 7210 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32, 7211 RTLIB::ADD_F64, 7212 RTLIB::ADD_F80, 7213 RTLIB::ADD_PPCF128), 7214 Node, false, Hi); 7215 break; 7216 case ISD::FSUB: 7217 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32, 7218 RTLIB::SUB_F64, 7219 RTLIB::SUB_F80, 7220 RTLIB::SUB_PPCF128), 7221 Node, false, Hi); 7222 break; 7223 case ISD::FMUL: 7224 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32, 7225 RTLIB::MUL_F64, 7226 RTLIB::MUL_F80, 7227 RTLIB::MUL_PPCF128), 7228 Node, false, Hi); 7229 break; 7230 case ISD::FDIV: 7231 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32, 7232 RTLIB::DIV_F64, 7233 RTLIB::DIV_F80, 7234 RTLIB::DIV_PPCF128), 7235 Node, false, Hi); 7236 break; 7237 case ISD::FP_EXTEND: { 7238 if (VT == MVT::ppcf128) { 7239 assert(Node->getOperand(0).getValueType()==MVT::f32 || 7240 Node->getOperand(0).getValueType()==MVT::f64); 7241 const uint64_t zero = 0; 7242 if (Node->getOperand(0).getValueType()==MVT::f32) 7243 Hi = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Node->getOperand(0)); 7244 else 7245 Hi = Node->getOperand(0); 7246 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 7247 break; 7248 } 7249 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT); 7250 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!"); 7251 Lo = ExpandLibCall(LC, Node, true, Hi); 7252 break; 7253 } 7254 case ISD::FP_ROUND: { 7255 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(), 7256 VT); 7257 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!"); 7258 Lo = ExpandLibCall(LC, Node, true, Hi); 7259 break; 7260 } 7261 case ISD::FSQRT: 7262 case ISD::FSIN: 7263 case ISD::FCOS: 7264 case ISD::FLOG: 7265 case ISD::FLOG2: 7266 case ISD::FLOG10: 7267 case ISD::FEXP: 7268 case ISD::FEXP2: 7269 case ISD::FTRUNC: 7270 case ISD::FFLOOR: 7271 case ISD::FCEIL: 7272 case ISD::FRINT: 7273 case ISD::FNEARBYINT: 7274 case ISD::FPOW: 7275 case ISD::FPOWI: { 7276 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 7277 switch(Node->getOpcode()) { 7278 case ISD::FSQRT: 7279 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 7280 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 7281 break; 7282 case ISD::FSIN: 7283 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 7284 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 7285 break; 7286 case ISD::FCOS: 7287 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 7288 RTLIB::COS_F80, RTLIB::COS_PPCF128); 7289 break; 7290 case ISD::FLOG: 7291 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64, 7292 RTLIB::LOG_F80, RTLIB::LOG_PPCF128); 7293 break; 7294 case ISD::FLOG2: 7295 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 7296 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128); 7297 break; 7298 case ISD::FLOG10: 7299 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 7300 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128); 7301 break; 7302 case ISD::FEXP: 7303 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64, 7304 RTLIB::EXP_F80, RTLIB::EXP_PPCF128); 7305 break; 7306 case ISD::FEXP2: 7307 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 7308 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128); 7309 break; 7310 case ISD::FTRUNC: 7311 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 7312 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 7313 break; 7314 case ISD::FFLOOR: 7315 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 7316 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 7317 break; 7318 case ISD::FCEIL: 7319 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 7320 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 7321 break; 7322 case ISD::FRINT: 7323 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 7324 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 7325 break; 7326 case ISD::FNEARBYINT: 7327 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 7328 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 7329 break; 7330 case ISD::FPOW: 7331 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 7332 RTLIB::POW_PPCF128); 7333 break; 7334 case ISD::FPOWI: 7335 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80, 7336 RTLIB::POWI_PPCF128); 7337 break; 7338 default: assert(0 && "Unreachable!"); 7339 } 7340 Lo = ExpandLibCall(LC, Node, false, Hi); 7341 break; 7342 } 7343 case ISD::FABS: { 7344 if (VT == MVT::ppcf128) { 7345 SDValue Tmp; 7346 ExpandOp(Node->getOperand(0), Lo, Tmp); 7347 Hi = DAG.getNode(ISD::FABS, dl, NVT, Tmp); 7348 // lo = hi==fabs(hi) ? lo : -lo; 7349 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Hi, Tmp, 7350 Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo), 7351 DAG.getCondCode(ISD::SETEQ)); 7352 break; 7353 } 7354 SDValue Mask = (VT == MVT::f64) 7355 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 7356 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 7357 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask); 7358 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 7359 Lo = DAG.getNode(ISD::AND, dl, NVT, Lo, Mask); 7360 if (getTypeAction(NVT) == Expand) 7361 ExpandOp(Lo, Lo, Hi); 7362 break; 7363 } 7364 case ISD::FNEG: { 7365 if (VT == MVT::ppcf128) { 7366 ExpandOp(Node->getOperand(0), Lo, Hi); 7367 Lo = DAG.getNode(ISD::FNEG, dl, MVT::f64, Lo); 7368 Hi = DAG.getNode(ISD::FNEG, dl, MVT::f64, Hi); 7369 break; 7370 } 7371 SDValue Mask = (VT == MVT::f64) 7372 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 7373 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 7374 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask); 7375 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 7376 Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Mask); 7377 if (getTypeAction(NVT) == Expand) 7378 ExpandOp(Lo, Lo, Hi); 7379 break; 7380 } 7381 case ISD::FCOPYSIGN: { 7382 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 7383 if (getTypeAction(NVT) == Expand) 7384 ExpandOp(Lo, Lo, Hi); 7385 break; 7386 } 7387 case ISD::SINT_TO_FP: 7388 case ISD::UINT_TO_FP: { 7389 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 7390 MVT SrcVT = Node->getOperand(0).getValueType(); 7391 7392 // Promote the operand if needed. Do this before checking for 7393 // ppcf128 so conversions of i16 and i8 work. 7394 if (getTypeAction(SrcVT) == Promote) { 7395 SDValue Tmp = PromoteOp(Node->getOperand(0)); 7396 Tmp = isSigned 7397 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp.getValueType(), Tmp, 7398 DAG.getValueType(SrcVT)) 7399 : DAG.getZeroExtendInReg(Tmp, dl, SrcVT); 7400 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode(); 7401 SrcVT = Node->getOperand(0).getValueType(); 7402 } 7403 7404 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 7405 static const uint64_t zero = 0; 7406 if (isSigned) { 7407 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64, 7408 Node->getOperand(0))); 7409 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 7410 } else { 7411 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 7412 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64, 7413 Node->getOperand(0))); 7414 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 7415 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi); 7416 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 7417 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, 7418 MVT::ppcf128, Node->getOperand(0), 7419 DAG.getConstant(0, MVT::i32), 7420 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi, 7421 DAG.getConstantFP( 7422 APFloat(APInt(128, 2, TwoE32)), 7423 MVT::ppcf128)), 7424 Hi, 7425 DAG.getCondCode(ISD::SETLT)), 7426 Lo, Hi); 7427 } 7428 break; 7429 } 7430 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 7431 // si64->ppcf128 done by libcall, below 7432 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 7433 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::ppcf128, 7434 Node->getOperand(0)), Lo, Hi); 7435 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi); 7436 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 7437 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, MVT::ppcf128, 7438 Node->getOperand(0), 7439 DAG.getConstant(0, MVT::i64), 7440 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi, 7441 DAG.getConstantFP( 7442 APFloat(APInt(128, 2, TwoE64)), 7443 MVT::ppcf128)), 7444 Hi, 7445 DAG.getCondCode(ISD::SETLT)), 7446 Lo, Hi); 7447 break; 7448 } 7449 7450 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 7451 Node->getOperand(0), dl); 7452 if (getTypeAction(Lo.getValueType()) == Expand) 7453 // float to i32 etc. can be 'expanded' to a single node. 7454 ExpandOp(Lo, Lo, Hi); 7455 break; 7456 } 7457 } 7458 7459 // Make sure the resultant values have been legalized themselves, unless this 7460 // is a type that requires multi-step expansion. 7461 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 7462 Lo = LegalizeOp(Lo); 7463 if (Hi.getNode()) 7464 // Don't legalize the high part if it is expanded to a single node. 7465 Hi = LegalizeOp(Hi); 7466 } 7467 7468 // Remember in a map if the values will be reused later. 7469 bool isNew = 7470 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7471 assert(isNew && "Value already expanded?!?"); 7472 isNew = isNew; 7473} 7474 7475/// SplitVectorOp - Given an operand of vector type, break it down into 7476/// two smaller values, still of vector type. 7477void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo, 7478 SDValue &Hi) { 7479 assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); 7480 SDNode *Node = Op.getNode(); 7481 DebugLoc dl = Node->getDebugLoc(); 7482 unsigned NumElements = Op.getValueType().getVectorNumElements(); 7483 assert(NumElements > 1 && "Cannot split a single element vector!"); 7484 7485 MVT NewEltVT = Op.getValueType().getVectorElementType(); 7486 7487 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 7488 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 7489 7490 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); 7491 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); 7492 7493 // See if we already split it. 7494 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I 7495 = SplitNodes.find(Op); 7496 if (I != SplitNodes.end()) { 7497 Lo = I->second.first; 7498 Hi = I->second.second; 7499 return; 7500 } 7501 7502 switch (Node->getOpcode()) { 7503 default: 7504#ifndef NDEBUG 7505 Node->dump(&DAG); 7506#endif 7507 assert(0 && "Unhandled operation in SplitVectorOp!"); 7508 case ISD::UNDEF: 7509 Lo = DAG.getNode(ISD::UNDEF, dl, NewVT_Lo); 7510 Hi = DAG.getNode(ISD::UNDEF, dl, NewVT_Hi); 7511 break; 7512 case ISD::BUILD_PAIR: 7513 Lo = Node->getOperand(0); 7514 Hi = Node->getOperand(1); 7515 break; 7516 case ISD::INSERT_VECTOR_ELT: { 7517 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 7518 SplitVectorOp(Node->getOperand(0), Lo, Hi); 7519 unsigned Index = Idx->getZExtValue(); 7520 SDValue ScalarOp = Node->getOperand(1); 7521 if (Index < NewNumElts_Lo) 7522 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Lo, Lo, ScalarOp, 7523 DAG.getIntPtrConstant(Index)); 7524 else 7525 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Hi, Hi, ScalarOp, 7526 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 7527 break; 7528 } 7529 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), 7530 Node->getOperand(1), 7531 Node->getOperand(2), dl); 7532 SplitVectorOp(Tmp, Lo, Hi); 7533 break; 7534 } 7535 case ISD::VECTOR_SHUFFLE: { 7536 // Build the low part. 7537 SDValue Mask = Node->getOperand(2); 7538 SmallVector<SDValue, 8> Ops; 7539 MVT PtrVT = TLI.getPointerTy(); 7540 7541 // Insert all of the elements from the input that are needed. We use 7542 // buildvector of extractelement here because the input vectors will have 7543 // to be legalized, so this makes the code simpler. 7544 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 7545 SDValue IdxNode = Mask.getOperand(i); 7546 if (IdxNode.getOpcode() == ISD::UNDEF) { 7547 Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT)); 7548 continue; 7549 } 7550 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue(); 7551 SDValue InVec = Node->getOperand(0); 7552 if (Idx >= NumElements) { 7553 InVec = Node->getOperand(1); 7554 Idx -= NumElements; 7555 } 7556 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec, 7557 DAG.getConstant(Idx, PtrVT))); 7558 } 7559 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &Ops[0], Ops.size()); 7560 Ops.clear(); 7561 7562 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 7563 SDValue IdxNode = Mask.getOperand(i); 7564 if (IdxNode.getOpcode() == ISD::UNDEF) { 7565 Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT)); 7566 continue; 7567 } 7568 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue(); 7569 SDValue InVec = Node->getOperand(0); 7570 if (Idx >= NumElements) { 7571 InVec = Node->getOperand(1); 7572 Idx -= NumElements; 7573 } 7574 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec, 7575 DAG.getConstant(Idx, PtrVT))); 7576 } 7577 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &Ops[0], Ops.size()); 7578 break; 7579 } 7580 case ISD::BUILD_VECTOR: { 7581 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 7582 Node->op_begin()+NewNumElts_Lo); 7583 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &LoOps[0], LoOps.size()); 7584 7585 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 7586 Node->op_end()); 7587 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &HiOps[0], HiOps.size()); 7588 break; 7589 } 7590 case ISD::CONCAT_VECTORS: { 7591 // FIXME: Handle non-power-of-two vectors? 7592 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 7593 if (NewNumSubvectors == 1) { 7594 Lo = Node->getOperand(0); 7595 Hi = Node->getOperand(1); 7596 } else { 7597 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 7598 Node->op_begin()+NewNumSubvectors); 7599 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo, 7600 &LoOps[0], LoOps.size()); 7601 7602 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors, 7603 Node->op_end()); 7604 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi, 7605 &HiOps[0], HiOps.size()); 7606 } 7607 break; 7608 } 7609 case ISD::EXTRACT_SUBVECTOR: { 7610 SDValue Vec = Op.getOperand(0); 7611 SDValue Idx = Op.getOperand(1); 7612 MVT IdxVT = Idx.getValueType(); 7613 7614 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Lo, Vec, Idx); 7615 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx); 7616 if (CIdx) { 7617 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, 7618 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo, 7619 IdxVT)); 7620 } else { 7621 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx, 7622 DAG.getConstant(NewNumElts_Lo, IdxVT)); 7623 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, Idx); 7624 } 7625 break; 7626 } 7627 case ISD::SELECT: { 7628 SDValue Cond = Node->getOperand(0); 7629 7630 SDValue LL, LH, RL, RH; 7631 SplitVectorOp(Node->getOperand(1), LL, LH); 7632 SplitVectorOp(Node->getOperand(2), RL, RH); 7633 7634 if (Cond.getValueType().isVector()) { 7635 // Handle a vector merge. 7636 SDValue CL, CH; 7637 SplitVectorOp(Cond, CL, CH); 7638 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, CL, LL, RL); 7639 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, CH, LH, RH); 7640 } else { 7641 // Handle a simple select with vector operands. 7642 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, Cond, LL, RL); 7643 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, Cond, LH, RH); 7644 } 7645 break; 7646 } 7647 case ISD::SELECT_CC: { 7648 SDValue CondLHS = Node->getOperand(0); 7649 SDValue CondRHS = Node->getOperand(1); 7650 SDValue CondCode = Node->getOperand(4); 7651 7652 SDValue LL, LH, RL, RH; 7653 SplitVectorOp(Node->getOperand(2), LL, LH); 7654 SplitVectorOp(Node->getOperand(3), RL, RH); 7655 7656 // Handle a simple select with vector operands. 7657 Lo = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Lo, CondLHS, CondRHS, 7658 LL, RL, CondCode); 7659 Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS, 7660 LH, RH, CondCode); 7661 break; 7662 } 7663 case ISD::VSETCC: { 7664 SDValue LL, LH, RL, RH; 7665 SplitVectorOp(Node->getOperand(0), LL, LH); 7666 SplitVectorOp(Node->getOperand(1), RL, RH); 7667 Lo = DAG.getNode(ISD::VSETCC, dl, NewVT_Lo, LL, RL, Node->getOperand(2)); 7668 Hi = DAG.getNode(ISD::VSETCC, dl, NewVT_Hi, LH, RH, Node->getOperand(2)); 7669 break; 7670 } 7671 case ISD::ADD: 7672 case ISD::SUB: 7673 case ISD::MUL: 7674 case ISD::FADD: 7675 case ISD::FSUB: 7676 case ISD::FMUL: 7677 case ISD::SDIV: 7678 case ISD::UDIV: 7679 case ISD::FDIV: 7680 case ISD::FPOW: 7681 case ISD::AND: 7682 case ISD::OR: 7683 case ISD::XOR: 7684 case ISD::UREM: 7685 case ISD::SREM: 7686 case ISD::FREM: 7687 case ISD::SHL: 7688 case ISD::SRA: 7689 case ISD::SRL: { 7690 SDValue LL, LH, RL, RH; 7691 SplitVectorOp(Node->getOperand(0), LL, LH); 7692 SplitVectorOp(Node->getOperand(1), RL, RH); 7693 7694 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, LL, RL); 7695 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, LH, RH); 7696 break; 7697 } 7698 case ISD::FP_ROUND: 7699 case ISD::FPOWI: { 7700 SDValue L, H; 7701 SplitVectorOp(Node->getOperand(0), L, H); 7702 7703 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L, Node->getOperand(1)); 7704 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H, Node->getOperand(1)); 7705 break; 7706 } 7707 case ISD::CTTZ: 7708 case ISD::CTLZ: 7709 case ISD::CTPOP: 7710 case ISD::FNEG: 7711 case ISD::FABS: 7712 case ISD::FSQRT: 7713 case ISD::FSIN: 7714 case ISD::FCOS: 7715 case ISD::FLOG: 7716 case ISD::FLOG2: 7717 case ISD::FLOG10: 7718 case ISD::FEXP: 7719 case ISD::FEXP2: 7720 case ISD::FP_TO_SINT: 7721 case ISD::FP_TO_UINT: 7722 case ISD::SINT_TO_FP: 7723 case ISD::UINT_TO_FP: 7724 case ISD::TRUNCATE: 7725 case ISD::ANY_EXTEND: 7726 case ISD::SIGN_EXTEND: 7727 case ISD::ZERO_EXTEND: 7728 case ISD::FP_EXTEND: { 7729 SDValue L, H; 7730 SplitVectorOp(Node->getOperand(0), L, H); 7731 7732 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L); 7733 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H); 7734 break; 7735 } 7736 case ISD::CONVERT_RNDSAT: { 7737 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 7738 SDValue L, H; 7739 SplitVectorOp(Node->getOperand(0), L, H); 7740 SDValue DTyOpL = DAG.getValueType(NewVT_Lo); 7741 SDValue DTyOpH = DAG.getValueType(NewVT_Hi); 7742 SDValue STyOpL = DAG.getValueType(L.getValueType()); 7743 SDValue STyOpH = DAG.getValueType(H.getValueType()); 7744 7745 SDValue RndOp = Node->getOperand(3); 7746 SDValue SatOp = Node->getOperand(4); 7747 7748 Lo = DAG.getConvertRndSat(NewVT_Lo, dl, L, DTyOpL, STyOpL, 7749 RndOp, SatOp, CvtCode); 7750 Hi = DAG.getConvertRndSat(NewVT_Hi, dl, H, DTyOpH, STyOpH, 7751 RndOp, SatOp, CvtCode); 7752 break; 7753 } 7754 case ISD::LOAD: { 7755 LoadSDNode *LD = cast<LoadSDNode>(Node); 7756 SDValue Ch = LD->getChain(); 7757 SDValue Ptr = LD->getBasePtr(); 7758 ISD::LoadExtType ExtType = LD->getExtensionType(); 7759 const Value *SV = LD->getSrcValue(); 7760 int SVOffset = LD->getSrcValueOffset(); 7761 MVT MemoryVT = LD->getMemoryVT(); 7762 unsigned Alignment = LD->getAlignment(); 7763 bool isVolatile = LD->isVolatile(); 7764 7765 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 7766 SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType()); 7767 7768 MVT MemNewEltVT = MemoryVT.getVectorElementType(); 7769 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo); 7770 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi); 7771 7772 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, 7773 NewVT_Lo, Ch, Ptr, Offset, 7774 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment); 7775 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8; 7776 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 7777 DAG.getIntPtrConstant(IncrementSize)); 7778 SVOffset += IncrementSize; 7779 Alignment = MinAlign(Alignment, IncrementSize); 7780 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, 7781 NewVT_Hi, Ch, Ptr, Offset, 7782 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment); 7783 7784 // Build a factor node to remember that this load is independent of the 7785 // other one. 7786 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 7787 Hi.getValue(1)); 7788 7789 // Remember that we legalized the chain. 7790 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 7791 break; 7792 } 7793 case ISD::BIT_CONVERT: { 7794 // We know the result is a vector. The input may be either a vector or a 7795 // scalar value. 7796 SDValue InOp = Node->getOperand(0); 7797 if (!InOp.getValueType().isVector() || 7798 InOp.getValueType().getVectorNumElements() == 1) { 7799 // The input is a scalar or single-element vector. 7800 // Lower to a store/load so that it can be split. 7801 // FIXME: this could be improved probably. 7802 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment( 7803 Op.getValueType().getTypeForMVT()); 7804 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign); 7805 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex(); 7806 7807 SDValue St = DAG.getStore(DAG.getEntryNode(), dl, 7808 InOp, Ptr, 7809 PseudoSourceValue::getFixedStack(FI), 0); 7810 InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr, 7811 PseudoSourceValue::getFixedStack(FI), 0); 7812 } 7813 // Split the vector and convert each of the pieces now. 7814 SplitVectorOp(InOp, Lo, Hi); 7815 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Lo, Lo); 7816 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Hi, Hi); 7817 break; 7818 } 7819 } 7820 7821 // Remember in a map if the values will be reused later. 7822 bool isNew = 7823 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7824 assert(isNew && "Value already split?!?"); 7825 isNew = isNew; 7826} 7827 7828 7829/// ScalarizeVectorOp - Given an operand of single-element vector type 7830/// (e.g. v1f32), convert it into the equivalent operation that returns a 7831/// scalar (e.g. f32) value. 7832SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) { 7833 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); 7834 SDNode *Node = Op.getNode(); 7835 DebugLoc dl = Node->getDebugLoc(); 7836 MVT NewVT = Op.getValueType().getVectorElementType(); 7837 assert(Op.getValueType().getVectorNumElements() == 1); 7838 7839 // See if we already scalarized it. 7840 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op); 7841 if (I != ScalarizedNodes.end()) return I->second; 7842 7843 SDValue Result; 7844 switch (Node->getOpcode()) { 7845 default: 7846#ifndef NDEBUG 7847 Node->dump(&DAG); cerr << "\n"; 7848#endif 7849 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 7850 case ISD::ADD: 7851 case ISD::FADD: 7852 case ISD::SUB: 7853 case ISD::FSUB: 7854 case ISD::MUL: 7855 case ISD::FMUL: 7856 case ISD::SDIV: 7857 case ISD::UDIV: 7858 case ISD::FDIV: 7859 case ISD::SREM: 7860 case ISD::UREM: 7861 case ISD::FREM: 7862 case ISD::FPOW: 7863 case ISD::AND: 7864 case ISD::OR: 7865 case ISD::XOR: 7866 Result = DAG.getNode(Node->getOpcode(), dl, 7867 NewVT, 7868 ScalarizeVectorOp(Node->getOperand(0)), 7869 ScalarizeVectorOp(Node->getOperand(1))); 7870 break; 7871 case ISD::FNEG: 7872 case ISD::FABS: 7873 case ISD::FSQRT: 7874 case ISD::FSIN: 7875 case ISD::FCOS: 7876 case ISD::FLOG: 7877 case ISD::FLOG2: 7878 case ISD::FLOG10: 7879 case ISD::FEXP: 7880 case ISD::FEXP2: 7881 case ISD::FP_TO_SINT: 7882 case ISD::FP_TO_UINT: 7883 case ISD::SINT_TO_FP: 7884 case ISD::UINT_TO_FP: 7885 case ISD::SIGN_EXTEND: 7886 case ISD::ZERO_EXTEND: 7887 case ISD::ANY_EXTEND: 7888 case ISD::TRUNCATE: 7889 case ISD::FP_EXTEND: 7890 Result = DAG.getNode(Node->getOpcode(), dl, 7891 NewVT, 7892 ScalarizeVectorOp(Node->getOperand(0))); 7893 break; 7894 case ISD::CONVERT_RNDSAT: { 7895 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0)); 7896 Result = DAG.getConvertRndSat(NewVT, dl, Op0, 7897 DAG.getValueType(NewVT), 7898 DAG.getValueType(Op0.getValueType()), 7899 Node->getOperand(3), 7900 Node->getOperand(4), 7901 cast<CvtRndSatSDNode>(Node)->getCvtCode()); 7902 break; 7903 } 7904 case ISD::FPOWI: 7905 case ISD::FP_ROUND: 7906 Result = DAG.getNode(Node->getOpcode(), dl, 7907 NewVT, 7908 ScalarizeVectorOp(Node->getOperand(0)), 7909 Node->getOperand(1)); 7910 break; 7911 case ISD::LOAD: { 7912 LoadSDNode *LD = cast<LoadSDNode>(Node); 7913 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 7914 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 7915 ISD::LoadExtType ExtType = LD->getExtensionType(); 7916 const Value *SV = LD->getSrcValue(); 7917 int SVOffset = LD->getSrcValueOffset(); 7918 MVT MemoryVT = LD->getMemoryVT(); 7919 unsigned Alignment = LD->getAlignment(); 7920 bool isVolatile = LD->isVolatile(); 7921 7922 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 7923 SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType()); 7924 7925 Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, 7926 NewVT, Ch, Ptr, Offset, SV, SVOffset, 7927 MemoryVT.getVectorElementType(), 7928 isVolatile, Alignment); 7929 7930 // Remember that we legalized the chain. 7931 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 7932 break; 7933 } 7934 case ISD::BUILD_VECTOR: 7935 Result = Node->getOperand(0); 7936 break; 7937 case ISD::INSERT_VECTOR_ELT: 7938 // Returning the inserted scalar element. 7939 Result = Node->getOperand(1); 7940 break; 7941 case ISD::CONCAT_VECTORS: 7942 assert(Node->getOperand(0).getValueType() == NewVT && 7943 "Concat of non-legal vectors not yet supported!"); 7944 Result = Node->getOperand(0); 7945 break; 7946 case ISD::VECTOR_SHUFFLE: { 7947 // Figure out if the scalar is the LHS or RHS and return it. 7948 SDValue EltNum = Node->getOperand(2).getOperand(0); 7949 if (cast<ConstantSDNode>(EltNum)->getZExtValue()) 7950 Result = ScalarizeVectorOp(Node->getOperand(1)); 7951 else 7952 Result = ScalarizeVectorOp(Node->getOperand(0)); 7953 break; 7954 } 7955 case ISD::EXTRACT_SUBVECTOR: 7956 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, 7957 Node->getOperand(0), Node->getOperand(1)); 7958 break; 7959 case ISD::BIT_CONVERT: { 7960 SDValue Op0 = Op.getOperand(0); 7961 if (Op0.getValueType().getVectorNumElements() == 1) 7962 Op0 = ScalarizeVectorOp(Op0); 7963 Result = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, Op0); 7964 break; 7965 } 7966 case ISD::SELECT: 7967 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Op.getOperand(0), 7968 ScalarizeVectorOp(Op.getOperand(1)), 7969 ScalarizeVectorOp(Op.getOperand(2))); 7970 break; 7971 case ISD::SELECT_CC: 7972 Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0), 7973 Node->getOperand(1), 7974 ScalarizeVectorOp(Op.getOperand(2)), 7975 ScalarizeVectorOp(Op.getOperand(3)), 7976 Node->getOperand(4)); 7977 break; 7978 case ISD::VSETCC: { 7979 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0)); 7980 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1)); 7981 Result = DAG.getNode(ISD::SETCC, dl, 7982 TLI.getSetCCResultType(Op0.getValueType()), 7983 Op0, Op1, Op.getOperand(2)); 7984 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Result, 7985 DAG.getConstant(-1ULL, NewVT), 7986 DAG.getConstant(0ULL, NewVT)); 7987 break; 7988 } 7989 } 7990 7991 if (TLI.isTypeLegal(NewVT)) 7992 Result = LegalizeOp(Result); 7993 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7994 assert(isNew && "Value already scalarized?"); 7995 isNew = isNew; 7996 return Result; 7997} 7998 7999 8000SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) { 8001 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op); 8002 if (I != WidenNodes.end()) return I->second; 8003 8004 MVT VT = Op.getValueType(); 8005 assert(VT.isVector() && "Cannot widen non-vector type!"); 8006 8007 SDValue Result; 8008 SDNode *Node = Op.getNode(); 8009 DebugLoc dl = Node->getDebugLoc(); 8010 MVT EVT = VT.getVectorElementType(); 8011 8012 unsigned NumElts = VT.getVectorNumElements(); 8013 unsigned NewNumElts = WidenVT.getVectorNumElements(); 8014 assert(NewNumElts > NumElts && "Cannot widen to smaller type!"); 8015 assert(NewNumElts < 17); 8016 8017 // When widen is called, it is assumed that it is more efficient to use a 8018 // wide type. The default action is to widen to operation to a wider legal 8019 // vector type and then do the operation if it is legal by calling LegalizeOp 8020 // again. If there is no vector equivalent, we will unroll the operation, do 8021 // it, and rebuild the vector. If most of the operations are vectorizible to 8022 // the legal type, the resulting code will be more efficient. If this is not 8023 // the case, the resulting code will preform badly as we end up generating 8024 // code to pack/unpack the results. It is the function that calls widen 8025 // that is responsible for seeing this doesn't happen. 8026 switch (Node->getOpcode()) { 8027 default: 8028#ifndef NDEBUG 8029 Node->dump(&DAG); 8030#endif 8031 assert(0 && "Unexpected operation in WidenVectorOp!"); 8032 break; 8033 case ISD::CopyFromReg: 8034 assert(0 && "CopyFromReg doesn't need widening!"); 8035 case ISD::Constant: 8036 case ISD::ConstantFP: 8037 // To build a vector of these elements, clients should call BuildVector 8038 // and with each element instead of creating a node with a vector type 8039 assert(0 && "Unexpected operation in WidenVectorOp!"); 8040 case ISD::VAARG: 8041 // Variable Arguments with vector types doesn't make any sense to me 8042 assert(0 && "Unexpected operation in WidenVectorOp!"); 8043 break; 8044 case ISD::UNDEF: 8045 Result = DAG.getNode(ISD::UNDEF, dl, WidenVT); 8046 break; 8047 case ISD::BUILD_VECTOR: { 8048 // Build a vector with undefined for the new nodes 8049 SDValueVector NewOps(Node->op_begin(), Node->op_end()); 8050 for (unsigned i = NumElts; i < NewNumElts; ++i) { 8051 NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, EVT)); 8052 } 8053 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, 8054 &NewOps[0], NewOps.size()); 8055 break; 8056 } 8057 case ISD::INSERT_VECTOR_ELT: { 8058 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8059 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WidenVT, Tmp1, 8060 Node->getOperand(1), Node->getOperand(2)); 8061 break; 8062 } 8063 case ISD::VECTOR_SHUFFLE: { 8064 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8065 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT); 8066 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is 8067 // used as permutation array. We build the vector here instead of widening 8068 // because we don't want to legalize and have it turned to something else. 8069 SDValue PermOp = Node->getOperand(2); 8070 SDValueVector NewOps; 8071 MVT PVT = PermOp.getValueType().getVectorElementType(); 8072 for (unsigned i = 0; i < NumElts; ++i) { 8073 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) { 8074 NewOps.push_back(PermOp.getOperand(i)); 8075 } else { 8076 unsigned Idx = 8077 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue(); 8078 if (Idx < NumElts) { 8079 NewOps.push_back(PermOp.getOperand(i)); 8080 } 8081 else { 8082 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts, 8083 PermOp.getOperand(i).getValueType())); 8084 } 8085 } 8086 } 8087 for (unsigned i = NumElts; i < NewNumElts; ++i) { 8088 NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, PVT)); 8089 } 8090 8091 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, dl, 8092 MVT::getVectorVT(PVT, NewOps.size()), 8093 &NewOps[0], NewOps.size()); 8094 8095 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, Tmp1, Tmp2, Tmp3); 8096 break; 8097 } 8098 case ISD::LOAD: { 8099 // If the load widen returns true, we can use a single load for the 8100 // vector. Otherwise, it is returning a token factor for multiple 8101 // loads. 8102 SDValue TFOp; 8103 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT)) 8104 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1))); 8105 else 8106 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0))); 8107 break; 8108 } 8109 8110 case ISD::BIT_CONVERT: { 8111 SDValue Tmp1 = Node->getOperand(0); 8112 // Converts between two different types so we need to determine 8113 // the correct widen type for the input operand. 8114 MVT InVT = Tmp1.getValueType(); 8115 unsigned WidenSize = WidenVT.getSizeInBits(); 8116 if (InVT.isVector()) { 8117 MVT InEltVT = InVT.getVectorElementType(); 8118 unsigned InEltSize = InEltVT.getSizeInBits(); 8119 assert(WidenSize % InEltSize == 0 && 8120 "can not widen bit convert that are not multiple of element type"); 8121 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize); 8122 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT); 8123 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits()); 8124 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Tmp1); 8125 } else { 8126 // If the result size is a multiple of the input size, widen the input 8127 // and then convert. 8128 unsigned InSize = InVT.getSizeInBits(); 8129 assert(WidenSize % InSize == 0 && 8130 "can not widen bit convert that are not multiple of element type"); 8131 unsigned NewNumElts = WidenSize / InSize; 8132 SmallVector<SDValue, 16> Ops(NewNumElts); 8133 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT); 8134 Ops[0] = Tmp1; 8135 for (unsigned i = 1; i < NewNumElts; ++i) 8136 Ops[i] = UndefVal; 8137 8138 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts); 8139 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, &Ops[0], NewNumElts); 8140 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Result); 8141 } 8142 break; 8143 } 8144 8145 case ISD::SINT_TO_FP: 8146 case ISD::UINT_TO_FP: 8147 case ISD::FP_TO_SINT: 8148 case ISD::FP_TO_UINT: 8149 case ISD::FP_ROUND: { 8150 SDValue Tmp1 = Node->getOperand(0); 8151 // Converts between two different types so we need to determine 8152 // the correct widen type for the input operand. 8153 MVT TVT = Tmp1.getValueType(); 8154 assert(TVT.isVector() && "can not widen non vector type"); 8155 MVT TEVT = TVT.getVectorElementType(); 8156 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts); 8157 Tmp1 = WidenVectorOp(Tmp1, TWidenVT); 8158 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts); 8159 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1); 8160 break; 8161 } 8162 8163 case ISD::FP_EXTEND: 8164 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 8165 case ISD::TRUNCATE: 8166 case ISD::SIGN_EXTEND: 8167 case ISD::ZERO_EXTEND: 8168 case ISD::ANY_EXTEND: 8169 case ISD::SIGN_EXTEND_INREG: 8170 case ISD::FABS: 8171 case ISD::FNEG: 8172 case ISD::FSQRT: 8173 case ISD::FSIN: 8174 case ISD::FCOS: 8175 case ISD::CTPOP: 8176 case ISD::CTTZ: 8177 case ISD::CTLZ: { 8178 // Unary op widening 8179 SDValue Tmp1; 8180 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8181 assert(Tmp1.getValueType() == WidenVT); 8182 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1); 8183 break; 8184 } 8185 case ISD::CONVERT_RNDSAT: { 8186 SDValue RndOp = Node->getOperand(3); 8187 SDValue SatOp = Node->getOperand(4); 8188 SDValue SrcOp = Node->getOperand(0); 8189 8190 // Converts between two different types so we need to determine 8191 // the correct widen type for the input operand. 8192 MVT SVT = SrcOp.getValueType(); 8193 assert(SVT.isVector() && "can not widen non vector type"); 8194 MVT SEVT = SVT.getVectorElementType(); 8195 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts); 8196 8197 SrcOp = WidenVectorOp(SrcOp, SWidenVT); 8198 assert(SrcOp.getValueType() == WidenVT); 8199 SDValue DTyOp = DAG.getValueType(WidenVT); 8200 SDValue STyOp = DAG.getValueType(SrcOp.getValueType()); 8201 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 8202 8203 Result = DAG.getConvertRndSat(WidenVT, dl, SrcOp, DTyOp, STyOp, 8204 RndOp, SatOp, CvtCode); 8205 break; 8206 } 8207 case ISD::FPOW: 8208 case ISD::FPOWI: 8209 case ISD::ADD: 8210 case ISD::SUB: 8211 case ISD::MUL: 8212 case ISD::MULHS: 8213 case ISD::MULHU: 8214 case ISD::AND: 8215 case ISD::OR: 8216 case ISD::XOR: 8217 case ISD::FADD: 8218 case ISD::FSUB: 8219 case ISD::FMUL: 8220 case ISD::SDIV: 8221 case ISD::SREM: 8222 case ISD::FDIV: 8223 case ISD::FREM: 8224 case ISD::FCOPYSIGN: 8225 case ISD::UDIV: 8226 case ISD::UREM: 8227 case ISD::BSWAP: { 8228 // Binary op widening 8229 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8230 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT); 8231 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT); 8232 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2); 8233 break; 8234 } 8235 8236 case ISD::SHL: 8237 case ISD::SRA: 8238 case ISD::SRL: { 8239 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8240 assert(Tmp1.getValueType() == WidenVT); 8241 SDValue ShOp = Node->getOperand(1); 8242 MVT ShVT = ShOp.getValueType(); 8243 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(), 8244 WidenVT.getVectorNumElements()); 8245 ShOp = WidenVectorOp(ShOp, NewShVT); 8246 assert(ShOp.getValueType() == NewShVT); 8247 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, ShOp); 8248 break; 8249 } 8250 8251 case ISD::EXTRACT_VECTOR_ELT: { 8252 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8253 assert(Tmp1.getValueType() == WidenVT); 8254 Result = DAG.getNode(Node->getOpcode(), dl, EVT, Tmp1, Node->getOperand(1)); 8255 break; 8256 } 8257 case ISD::CONCAT_VECTORS: { 8258 // We concurrently support only widen on a multiple of the incoming vector. 8259 // We could widen on a multiple of the incoming operand if necessary. 8260 unsigned NumConcat = NewNumElts / NumElts; 8261 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector"); 8262 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT); 8263 SmallVector<SDValue, 8> MOps; 8264 MOps.push_back(Op); 8265 for (unsigned i = 1; i != NumConcat; ++i) { 8266 MOps.push_back(UndefVal); 8267 } 8268 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, 8269 &MOps[0], MOps.size())); 8270 break; 8271 } 8272 case ISD::EXTRACT_SUBVECTOR: { 8273 SDValue Tmp1 = Node->getOperand(0); 8274 SDValue Idx = Node->getOperand(1); 8275 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx); 8276 if (CIdx && CIdx->getZExtValue() == 0) { 8277 // Since we are access the start of the vector, the incoming 8278 // vector type might be the proper. 8279 MVT Tmp1VT = Tmp1.getValueType(); 8280 if (Tmp1VT == WidenVT) 8281 return Tmp1; 8282 else { 8283 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements(); 8284 if (Tmp1VTNumElts < NewNumElts) 8285 Result = WidenVectorOp(Tmp1, WidenVT); 8286 else 8287 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, Tmp1, Idx); 8288 } 8289 } else if (NewNumElts % NumElts == 0) { 8290 // Widen the extracted subvector. 8291 unsigned NumConcat = NewNumElts / NumElts; 8292 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT); 8293 SmallVector<SDValue, 8> MOps; 8294 MOps.push_back(Op); 8295 for (unsigned i = 1; i != NumConcat; ++i) { 8296 MOps.push_back(UndefVal); 8297 } 8298 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, 8299 &MOps[0], MOps.size())); 8300 } else { 8301 assert(0 && "can not widen extract subvector"); 8302 // This could be implemented using insert and build vector but I would 8303 // like to see when this happens. 8304 } 8305 break; 8306 } 8307 8308 case ISD::SELECT: { 8309 // Determine new condition widen type and widen 8310 SDValue Cond1 = Node->getOperand(0); 8311 MVT CondVT = Cond1.getValueType(); 8312 assert(CondVT.isVector() && "can not widen non vector type"); 8313 MVT CondEVT = CondVT.getVectorElementType(); 8314 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts); 8315 Cond1 = WidenVectorOp(Cond1, CondWidenVT); 8316 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen"); 8317 8318 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT); 8319 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT); 8320 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT); 8321 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Tmp1, Tmp2); 8322 break; 8323 } 8324 8325 case ISD::SELECT_CC: { 8326 // Determine new condition widen type and widen 8327 SDValue Cond1 = Node->getOperand(0); 8328 SDValue Cond2 = Node->getOperand(1); 8329 MVT CondVT = Cond1.getValueType(); 8330 assert(CondVT.isVector() && "can not widen non vector type"); 8331 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs"); 8332 MVT CondEVT = CondVT.getVectorElementType(); 8333 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts); 8334 Cond1 = WidenVectorOp(Cond1, CondWidenVT); 8335 Cond2 = WidenVectorOp(Cond2, CondWidenVT); 8336 assert(Cond1.getValueType() == CondWidenVT && 8337 Cond2.getValueType() == CondWidenVT && "condition not widen"); 8338 8339 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT); 8340 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT); 8341 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT && 8342 "operands not widen"); 8343 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Cond2, Tmp1, 8344 Tmp2, Node->getOperand(4)); 8345 break; 8346 } 8347 case ISD::VSETCC: { 8348 // Determine widen for the operand 8349 SDValue Tmp1 = Node->getOperand(0); 8350 MVT TmpVT = Tmp1.getValueType(); 8351 assert(TmpVT.isVector() && "can not widen non vector type"); 8352 MVT TmpEVT = TmpVT.getVectorElementType(); 8353 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts); 8354 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT); 8355 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT); 8356 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2, 8357 Node->getOperand(2)); 8358 break; 8359 } 8360 case ISD::ATOMIC_CMP_SWAP: 8361 case ISD::ATOMIC_LOAD_ADD: 8362 case ISD::ATOMIC_LOAD_SUB: 8363 case ISD::ATOMIC_LOAD_AND: 8364 case ISD::ATOMIC_LOAD_OR: 8365 case ISD::ATOMIC_LOAD_XOR: 8366 case ISD::ATOMIC_LOAD_NAND: 8367 case ISD::ATOMIC_LOAD_MIN: 8368 case ISD::ATOMIC_LOAD_MAX: 8369 case ISD::ATOMIC_LOAD_UMIN: 8370 case ISD::ATOMIC_LOAD_UMAX: 8371 case ISD::ATOMIC_SWAP: { 8372 // For now, we assume that using vectors for these operations don't make 8373 // much sense so we just split it. We return an empty result 8374 SDValue X, Y; 8375 SplitVectorOp(Op, X, Y); 8376 return Result; 8377 break; 8378 } 8379 8380 } // end switch (Node->getOpcode()) 8381 8382 assert(Result.getNode() && "Didn't set a result!"); 8383 if (Result != Op) 8384 Result = LegalizeOp(Result); 8385 8386 AddWidenedOperand(Op, Result); 8387 return Result; 8388} 8389 8390// Utility function to find a legal vector type and its associated element 8391// type from a preferred width and whose vector type must be the same size 8392// as the VVT. 8393// TLI: Target lowering used to determine legal types 8394// Width: Preferred width of element type 8395// VVT: Vector value type whose size we must match. 8396// Returns VecEVT and EVT - the vector type and its associated element type 8397static void FindWidenVecType(const TargetLowering &TLI, unsigned Width, MVT VVT, 8398 MVT& EVT, MVT& VecEVT) { 8399 // We start with the preferred width, make it a power of 2 and see if 8400 // we can find a vector type of that width. If not, we reduce it by 8401 // another power of 2. If we have widen the type, a vector of bytes should 8402 // always be legal. 8403 assert(TLI.isTypeLegal(VVT)); 8404 unsigned EWidth = Width + 1; 8405 do { 8406 assert(EWidth > 0); 8407 EWidth = (1 << Log2_32(EWidth-1)); 8408 EVT = MVT::getIntegerVT(EWidth); 8409 unsigned NumEVT = VVT.getSizeInBits()/EWidth; 8410 VecEVT = MVT::getVectorVT(EVT, NumEVT); 8411 } while (!TLI.isTypeLegal(VecEVT) || 8412 VVT.getSizeInBits() != VecEVT.getSizeInBits()); 8413} 8414 8415SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain, 8416 SDValue Chain, 8417 SDValue BasePtr, 8418 const Value *SV, 8419 int SVOffset, 8420 unsigned Alignment, 8421 bool isVolatile, 8422 unsigned LdWidth, 8423 MVT ResType, 8424 DebugLoc dl) { 8425 // We assume that we have good rules to handle loading power of two loads so 8426 // we break down the operations to power of 2 loads. The strategy is to 8427 // load the largest power of 2 that we can easily transform to a legal vector 8428 // and then insert into that vector, and the cast the result into the legal 8429 // vector that we want. This avoids unnecessary stack converts. 8430 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and 8431 // the load is nonvolatile, we an use a wider load for the value. 8432 // Find a vector length we can load a large chunk 8433 MVT EVT, VecEVT; 8434 unsigned EVTWidth; 8435 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT); 8436 EVTWidth = EVT.getSizeInBits(); 8437 8438 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset, 8439 isVolatile, Alignment); 8440 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp); 8441 LdChain.push_back(LdOp.getValue(1)); 8442 8443 // Check if we can load the element with one instruction 8444 if (LdWidth == EVTWidth) { 8445 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp); 8446 } 8447 8448 // The vector element order is endianness dependent. 8449 unsigned Idx = 1; 8450 LdWidth -= EVTWidth; 8451 unsigned Offset = 0; 8452 8453 while (LdWidth > 0) { 8454 unsigned Increment = EVTWidth / 8; 8455 Offset += Increment; 8456 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 8457 DAG.getIntPtrConstant(Increment)); 8458 8459 if (LdWidth < EVTWidth) { 8460 // Our current type we are using is too large, use a smaller size by 8461 // using a smaller power of 2 8462 unsigned oEVTWidth = EVTWidth; 8463 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT); 8464 EVTWidth = EVT.getSizeInBits(); 8465 // Readjust position and vector position based on new load type 8466 Idx = Idx * (oEVTWidth/EVTWidth); 8467 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp); 8468 } 8469 8470 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, 8471 SVOffset+Offset, isVolatile, 8472 MinAlign(Alignment, Offset)); 8473 LdChain.push_back(LdOp.getValue(1)); 8474 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp, 8475 DAG.getIntPtrConstant(Idx++)); 8476 8477 LdWidth -= EVTWidth; 8478 } 8479 8480 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp); 8481} 8482 8483bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result, 8484 SDValue& TFOp, 8485 SDValue Op, 8486 MVT NVT) { 8487 // TODO: Add support for ConcatVec and the ability to load many vector 8488 // types (e.g., v4i8). This will not work when a vector register 8489 // to memory mapping is strange (e.g., vector elements are not 8490 // stored in some sequential order). 8491 8492 // It must be true that the widen vector type is bigger than where 8493 // we need to load from. 8494 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); 8495 MVT LdVT = LD->getMemoryVT(); 8496 DebugLoc dl = LD->getDebugLoc(); 8497 assert(LdVT.isVector() && NVT.isVector()); 8498 assert(LdVT.getVectorElementType() == NVT.getVectorElementType()); 8499 8500 // Load information 8501 SDValue Chain = LD->getChain(); 8502 SDValue BasePtr = LD->getBasePtr(); 8503 int SVOffset = LD->getSrcValueOffset(); 8504 unsigned Alignment = LD->getAlignment(); 8505 bool isVolatile = LD->isVolatile(); 8506 const Value *SV = LD->getSrcValue(); 8507 unsigned int LdWidth = LdVT.getSizeInBits(); 8508 8509 // Load value as a large register 8510 SDValueVector LdChain; 8511 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset, 8512 Alignment, isVolatile, LdWidth, NVT, dl); 8513 8514 if (LdChain.size() == 1) { 8515 TFOp = LdChain[0]; 8516 return true; 8517 } 8518 else { 8519 TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 8520 &LdChain[0], LdChain.size()); 8521 return false; 8522 } 8523} 8524 8525 8526void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain, 8527 SDValue Chain, 8528 SDValue BasePtr, 8529 const Value *SV, 8530 int SVOffset, 8531 unsigned Alignment, 8532 bool isVolatile, 8533 SDValue ValOp, 8534 unsigned StWidth, 8535 DebugLoc dl) { 8536 // Breaks the stores into a series of power of 2 width stores. For any 8537 // width, we convert the vector to the vector of element size that we 8538 // want to store. This avoids requiring a stack convert. 8539 8540 // Find a width of the element type we can store with 8541 MVT VVT = ValOp.getValueType(); 8542 MVT EVT, VecEVT; 8543 unsigned EVTWidth; 8544 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT); 8545 EVTWidth = EVT.getSizeInBits(); 8546 8547 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, ValOp); 8548 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp, 8549 DAG.getIntPtrConstant(0)); 8550 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset, 8551 isVolatile, Alignment); 8552 StChain.push_back(StOp); 8553 8554 // Check if we are done 8555 if (StWidth == EVTWidth) { 8556 return; 8557 } 8558 8559 unsigned Idx = 1; 8560 StWidth -= EVTWidth; 8561 unsigned Offset = 0; 8562 8563 while (StWidth > 0) { 8564 unsigned Increment = EVTWidth / 8; 8565 Offset += Increment; 8566 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 8567 DAG.getIntPtrConstant(Increment)); 8568 8569 if (StWidth < EVTWidth) { 8570 // Our current type we are using is too large, use a smaller size by 8571 // using a smaller power of 2 8572 unsigned oEVTWidth = EVTWidth; 8573 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT); 8574 EVTWidth = EVT.getSizeInBits(); 8575 // Readjust position and vector position based on new load type 8576 Idx = Idx * (oEVTWidth/EVTWidth); 8577 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp); 8578 } 8579 8580 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp, 8581 DAG.getIntPtrConstant(Idx++)); 8582 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV, 8583 SVOffset + Offset, isVolatile, 8584 MinAlign(Alignment, Offset))); 8585 StWidth -= EVTWidth; 8586 } 8587} 8588 8589 8590SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST, 8591 SDValue Chain, 8592 SDValue BasePtr) { 8593 // TODO: It might be cleaner if we can use SplitVector and have more legal 8594 // vector types that can be stored into memory (e.g., v4xi8 can 8595 // be stored as a word). This will not work when a vector register 8596 // to memory mapping is strange (e.g., vector elements are not 8597 // stored in some sequential order). 8598 8599 MVT StVT = ST->getMemoryVT(); 8600 SDValue ValOp = ST->getValue(); 8601 DebugLoc dl = ST->getDebugLoc(); 8602 8603 // Check if we have widen this node with another value 8604 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp); 8605 if (I != WidenNodes.end()) 8606 ValOp = I->second; 8607 8608 MVT VVT = ValOp.getValueType(); 8609 8610 // It must be true that we the widen vector type is bigger than where 8611 // we need to store. 8612 assert(StVT.isVector() && VVT.isVector()); 8613 assert(StVT.bitsLT(VVT)); 8614 assert(StVT.getVectorElementType() == VVT.getVectorElementType()); 8615 8616 // Store value 8617 SDValueVector StChain; 8618 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(), 8619 ST->getSrcValueOffset(), ST->getAlignment(), 8620 ST->isVolatile(), ValOp, StVT.getSizeInBits(), dl); 8621 if (StChain.size() == 1) 8622 return StChain[0]; 8623 else 8624 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 8625 &StChain[0], StChain.size()); 8626} 8627 8628 8629// SelectionDAG::Legalize - This is the entry point for the file. 8630// 8631void SelectionDAG::Legalize(bool TypesNeedLegalizing) { 8632 /// run - This is the main entry point to this class. 8633 /// 8634 SelectionDAGLegalize(*this, TypesNeedLegalizing).LegalizeDAG(); 8635} 8636 8637