LegalizeDAG.cpp revision 3be2e514c9e7b20135be5b9df3e9aa1cb08cb374
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/DwarfWriter.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/CodeGen/PseudoSourceValue.h" 22#include "llvm/Target/TargetFrameInfo.h" 23#include "llvm/Target/TargetLowering.h" 24#include "llvm/Target/TargetData.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Target/TargetSubtarget.h" 28#include "llvm/CallingConv.h" 29#include "llvm/Constants.h" 30#include "llvm/DerivedTypes.h" 31#include "llvm/Function.h" 32#include "llvm/GlobalVariable.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Compiler.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/ADT/DenseMap.h" 37#include "llvm/ADT/SmallVector.h" 38#include "llvm/ADT/SmallPtrSet.h" 39#include <map> 40using namespace llvm; 41 42//===----------------------------------------------------------------------===// 43/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 44/// hacks on it until the target machine can handle it. This involves 45/// eliminating value sizes the machine cannot handle (promoting small sizes to 46/// large sizes or splitting up large values into small values) as well as 47/// eliminating operations the machine cannot handle. 48/// 49/// This code also does a small amount of optimization and recognition of idioms 50/// as part of its processing. For example, if a target does not support a 51/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 52/// will attempt merge setcc and brc instructions into brcc's. 53/// 54namespace { 55class VISIBILITY_HIDDEN SelectionDAGLegalize { 56 TargetLowering &TLI; 57 SelectionDAG &DAG; 58 CodeGenOpt::Level OptLevel; 59 60 // Libcall insertion helpers. 61 62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 63 /// legalized. We use this to ensure that calls are properly serialized 64 /// against each other, including inserted libcalls. 65 SDValue LastCALLSEQ_END; 66 67 /// IsLegalizingCall - This member is used *only* for purposes of providing 68 /// helpful assertions that a libcall isn't created while another call is 69 /// being legalized (which could lead to non-serialized call sequences). 70 bool IsLegalizingCall; 71 72 enum LegalizeAction { 73 Legal, // The target natively supports this operation. 74 Promote, // This operation should be executed in a larger type. 75 Expand // Try to expand this to other ops, otherwise use a libcall. 76 }; 77 78 /// ValueTypeActions - This is a bitvector that contains two bits for each 79 /// value type, where the two bits correspond to the LegalizeAction enum. 80 /// This can be queried with "getTypeAction(VT)". 81 TargetLowering::ValueTypeActionImpl ValueTypeActions; 82 83 /// LegalizedNodes - For nodes that are of legal width, and that have more 84 /// than one use, this map indicates what regularized operand to use. This 85 /// allows us to avoid legalizing the same thing more than once. 86 DenseMap<SDValue, SDValue> LegalizedNodes; 87 88 void AddLegalizedOperand(SDValue From, SDValue To) { 89 LegalizedNodes.insert(std::make_pair(From, To)); 90 // If someone requests legalization of the new node, return itself. 91 if (From != To) 92 LegalizedNodes.insert(std::make_pair(To, To)); 93 } 94 95public: 96 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 97 98 /// getTypeAction - Return how we should legalize values of this type, either 99 /// it is already legal or we need to expand it into multiple registers of 100 /// smaller integer type, or we need to promote it to a larger type. 101 LegalizeAction getTypeAction(MVT VT) const { 102 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 103 } 104 105 /// isTypeLegal - Return true if this type is legal on this target. 106 /// 107 bool isTypeLegal(MVT VT) const { 108 return getTypeAction(VT) == Legal; 109 } 110 111 void LegalizeDAG(); 112 113private: 114 /// LegalizeOp - We know that the specified value has a legal type. 115 /// Recursively ensure that the operands have legal types, then return the 116 /// result. 117 SDValue LegalizeOp(SDValue O); 118 119 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 120 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 121 /// is necessary to spill the vector being inserted into to memory, perform 122 /// the insert there, and then read the result back. 123 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 124 SDValue Idx, DebugLoc dl); 125 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 126 SDValue Idx, DebugLoc dl); 127 128 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 129 /// performs the same shuffe in terms of order or result bytes, but on a type 130 /// whose vector element type is narrower than the original shuffle type. 131 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 132 SDValue ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl, 133 SDValue N1, SDValue N2, 134 SmallVectorImpl<int> &Mask) const; 135 136 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 137 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 138 139 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC, 140 DebugLoc dl); 141 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 142 DebugLoc dl); 143 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 144 DebugLoc dl) { 145 LegalizeSetCCOperands(LHS, RHS, CC, dl); 146 LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl); 147 } 148 149 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 150 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 151 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 152 RTLIB::Libcall Call_PPCF128); 153 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, RTLIB::Libcall Call_I16, 154 RTLIB::Libcall Call_I32, RTLIB::Libcall Call_I64, 155 RTLIB::Libcall Call_I128); 156 157 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl); 158 SDValue ExpandBUILD_VECTOR(SDNode *Node); 159 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 160 SDValue ExpandDBG_STOPPOINT(SDNode *Node); 161 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 162 SmallVectorImpl<SDValue> &Results); 163 SDValue ExpandFCOPYSIGN(SDNode *Node); 164 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT, 165 DebugLoc dl); 166 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned, 167 DebugLoc dl); 168 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned, 169 DebugLoc dl); 170 171 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 172 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 173 174 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 175 176 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 177 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 178}; 179} 180 181/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 182/// performs the same shuffe in terms of order or result bytes, but on a type 183/// whose vector element type is narrower than the original shuffle type. 184/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 185SDValue 186SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl, 187 SDValue N1, SDValue N2, 188 SmallVectorImpl<int> &Mask) const { 189 MVT EltVT = NVT.getVectorElementType(); 190 unsigned NumMaskElts = VT.getVectorNumElements(); 191 unsigned NumDestElts = NVT.getVectorNumElements(); 192 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 193 194 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 195 196 if (NumEltsGrowth == 1) 197 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 198 199 SmallVector<int, 8> NewMask; 200 for (unsigned i = 0; i != NumMaskElts; ++i) { 201 int Idx = Mask[i]; 202 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 203 if (Idx < 0) 204 NewMask.push_back(-1); 205 else 206 NewMask.push_back(Idx * NumEltsGrowth + j); 207 } 208 } 209 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 210 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 211 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 212} 213 214SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 215 CodeGenOpt::Level ol) 216 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), 217 ValueTypeActions(TLI.getValueTypeActions()) { 218 assert(MVT::LAST_VALUETYPE <= 32 && 219 "Too many value types for ValueTypeActions to hold!"); 220} 221 222void SelectionDAGLegalize::LegalizeDAG() { 223 LastCALLSEQ_END = DAG.getEntryNode(); 224 IsLegalizingCall = false; 225 226 // The legalize process is inherently a bottom-up recursive process (users 227 // legalize their uses before themselves). Given infinite stack space, we 228 // could just start legalizing on the root and traverse the whole graph. In 229 // practice however, this causes us to run out of stack space on large basic 230 // blocks. To avoid this problem, compute an ordering of the nodes where each 231 // node is only legalized after all of its operands are legalized. 232 DAG.AssignTopologicalOrder(); 233 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 234 E = prior(DAG.allnodes_end()); I != next(E); ++I) 235 LegalizeOp(SDValue(I, 0)); 236 237 // Finally, it's possible the root changed. Get the new root. 238 SDValue OldRoot = DAG.getRoot(); 239 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 240 DAG.setRoot(LegalizedNodes[OldRoot]); 241 242 LegalizedNodes.clear(); 243 244 // Remove dead nodes now. 245 DAG.RemoveDeadNodes(); 246} 247 248 249/// FindCallEndFromCallStart - Given a chained node that is part of a call 250/// sequence, find the CALLSEQ_END node that terminates the call sequence. 251static SDNode *FindCallEndFromCallStart(SDNode *Node) { 252 if (Node->getOpcode() == ISD::CALLSEQ_END) 253 return Node; 254 if (Node->use_empty()) 255 return 0; // No CallSeqEnd 256 257 // The chain is usually at the end. 258 SDValue TheChain(Node, Node->getNumValues()-1); 259 if (TheChain.getValueType() != MVT::Other) { 260 // Sometimes it's at the beginning. 261 TheChain = SDValue(Node, 0); 262 if (TheChain.getValueType() != MVT::Other) { 263 // Otherwise, hunt for it. 264 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 265 if (Node->getValueType(i) == MVT::Other) { 266 TheChain = SDValue(Node, i); 267 break; 268 } 269 270 // Otherwise, we walked into a node without a chain. 271 if (TheChain.getValueType() != MVT::Other) 272 return 0; 273 } 274 } 275 276 for (SDNode::use_iterator UI = Node->use_begin(), 277 E = Node->use_end(); UI != E; ++UI) { 278 279 // Make sure to only follow users of our token chain. 280 SDNode *User = *UI; 281 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 282 if (User->getOperand(i) == TheChain) 283 if (SDNode *Result = FindCallEndFromCallStart(User)) 284 return Result; 285 } 286 return 0; 287} 288 289/// FindCallStartFromCallEnd - Given a chained node that is part of a call 290/// sequence, find the CALLSEQ_START node that initiates the call sequence. 291static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 292 assert(Node && "Didn't find callseq_start for a call??"); 293 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 294 295 assert(Node->getOperand(0).getValueType() == MVT::Other && 296 "Node doesn't have a token chain argument!"); 297 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 298} 299 300/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 301/// see if any uses can reach Dest. If no dest operands can get to dest, 302/// legalize them, legalize ourself, and return false, otherwise, return true. 303/// 304/// Keep track of the nodes we fine that actually do lead to Dest in 305/// NodesLeadingTo. This avoids retraversing them exponential number of times. 306/// 307bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 308 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 309 if (N == Dest) return true; // N certainly leads to Dest :) 310 311 // If we've already processed this node and it does lead to Dest, there is no 312 // need to reprocess it. 313 if (NodesLeadingTo.count(N)) return true; 314 315 // If the first result of this node has been already legalized, then it cannot 316 // reach N. 317 if (LegalizedNodes.count(SDValue(N, 0))) return false; 318 319 // Okay, this node has not already been legalized. Check and legalize all 320 // operands. If none lead to Dest, then we can legalize this node. 321 bool OperandsLeadToDest = false; 322 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 323 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 324 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 325 326 if (OperandsLeadToDest) { 327 NodesLeadingTo.insert(N); 328 return true; 329 } 330 331 // Okay, this node looks safe, legalize it and return false. 332 LegalizeOp(SDValue(N, 0)); 333 return false; 334} 335 336/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 337/// a load from the constant pool. 338static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 339 SelectionDAG &DAG, const TargetLowering &TLI) { 340 bool Extend = false; 341 DebugLoc dl = CFP->getDebugLoc(); 342 343 // If a FP immediate is precise when represented as a float and if the 344 // target can do an extending load from float to double, we put it into 345 // the constant pool as a float, even if it's is statically typed as a 346 // double. This shrinks FP constants and canonicalizes them for targets where 347 // an FP extending load is the same cost as a normal load (such as on the x87 348 // fp stack or PPC FP unit). 349 MVT VT = CFP->getValueType(0); 350 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 351 if (!UseCP) { 352 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 353 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 354 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 355 } 356 357 MVT OrigVT = VT; 358 MVT SVT = VT; 359 while (SVT != MVT::f32) { 360 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 361 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 362 // Only do this if the target has a native EXTLOAD instruction from 363 // smaller type. 364 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 365 TLI.ShouldShrinkFPConstant(OrigVT)) { 366 const Type *SType = SVT.getTypeForMVT(); 367 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 368 VT = SVT; 369 Extend = true; 370 } 371 } 372 373 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 374 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 375 if (Extend) 376 return DAG.getExtLoad(ISD::EXTLOAD, dl, 377 OrigVT, DAG.getEntryNode(), 378 CPIdx, PseudoSourceValue::getConstantPool(), 379 0, VT, false, Alignment); 380 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 381 PseudoSourceValue::getConstantPool(), 0, false, Alignment); 382} 383 384/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 385static 386SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 387 const TargetLowering &TLI) { 388 SDValue Chain = ST->getChain(); 389 SDValue Ptr = ST->getBasePtr(); 390 SDValue Val = ST->getValue(); 391 MVT VT = Val.getValueType(); 392 int Alignment = ST->getAlignment(); 393 int SVOffset = ST->getSrcValueOffset(); 394 DebugLoc dl = ST->getDebugLoc(); 395 if (ST->getMemoryVT().isFloatingPoint() || 396 ST->getMemoryVT().isVector()) { 397 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits()); 398 if (TLI.isTypeLegal(intVT)) { 399 // Expand to a bitconvert of the value to the integer type of the 400 // same size, then a (misaligned) int store. 401 // FIXME: Does not handle truncating floating point stores! 402 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 403 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 404 SVOffset, ST->isVolatile(), Alignment); 405 } else { 406 // Do a (aligned) store to a stack slot, then copy from the stack slot 407 // to the final destination using (unaligned) integer loads and stores. 408 MVT StoredVT = ST->getMemoryVT(); 409 MVT RegVT = 410 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits())); 411 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 412 unsigned RegBytes = RegVT.getSizeInBits() / 8; 413 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 414 415 // Make sure the stack slot is also aligned for the register type. 416 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 417 418 // Perform the original store, only redirected to the stack slot. 419 SDValue Store = DAG.getTruncStore(Chain, dl, 420 Val, StackPtr, NULL, 0, StoredVT); 421 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 422 SmallVector<SDValue, 8> Stores; 423 unsigned Offset = 0; 424 425 // Do all but one copies using the full register width. 426 for (unsigned i = 1; i < NumRegs; i++) { 427 // Load one integer register's worth from the stack slot. 428 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0); 429 // Store it to the final location. Remember the store. 430 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 431 ST->getSrcValue(), SVOffset + Offset, 432 ST->isVolatile(), 433 MinAlign(ST->getAlignment(), Offset))); 434 // Increment the pointers. 435 Offset += RegBytes; 436 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 437 Increment); 438 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 439 } 440 441 // The last store may be partial. Do a truncating store. On big-endian 442 // machines this requires an extending load from the stack slot to ensure 443 // that the bits are in the right place. 444 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset)); 445 446 // Load from the stack slot. 447 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 448 NULL, 0, MemVT); 449 450 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 451 ST->getSrcValue(), SVOffset + Offset, 452 MemVT, ST->isVolatile(), 453 MinAlign(ST->getAlignment(), Offset))); 454 // The order of the stores doesn't matter - say it with a TokenFactor. 455 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 456 Stores.size()); 457 } 458 } 459 assert(ST->getMemoryVT().isInteger() && 460 !ST->getMemoryVT().isVector() && 461 "Unaligned store of unknown type."); 462 // Get the half-size VT 463 MVT NewStoredVT = 464 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 465 int NumBits = NewStoredVT.getSizeInBits(); 466 int IncrementSize = NumBits / 8; 467 468 // Divide the stored value in two parts. 469 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 470 SDValue Lo = Val; 471 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 472 473 // Store the two parts 474 SDValue Store1, Store2; 475 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 476 ST->getSrcValue(), SVOffset, NewStoredVT, 477 ST->isVolatile(), Alignment); 478 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 479 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 480 Alignment = MinAlign(Alignment, IncrementSize); 481 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 482 ST->getSrcValue(), SVOffset + IncrementSize, 483 NewStoredVT, ST->isVolatile(), Alignment); 484 485 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 486} 487 488/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 489static 490SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 491 const TargetLowering &TLI) { 492 int SVOffset = LD->getSrcValueOffset(); 493 SDValue Chain = LD->getChain(); 494 SDValue Ptr = LD->getBasePtr(); 495 MVT VT = LD->getValueType(0); 496 MVT LoadedVT = LD->getMemoryVT(); 497 DebugLoc dl = LD->getDebugLoc(); 498 if (VT.isFloatingPoint() || VT.isVector()) { 499 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits()); 500 if (TLI.isTypeLegal(intVT)) { 501 // Expand to a (misaligned) integer load of the same size, 502 // then bitconvert to floating point or vector. 503 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 504 SVOffset, LD->isVolatile(), 505 LD->getAlignment()); 506 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 507 if (VT.isFloatingPoint() && LoadedVT != VT) 508 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 509 510 SDValue Ops[] = { Result, Chain }; 511 return DAG.getMergeValues(Ops, 2, dl); 512 } else { 513 // Copy the value to a (aligned) stack slot using (unaligned) integer 514 // loads and stores, then do a (aligned) load from the stack slot. 515 MVT RegVT = TLI.getRegisterType(intVT); 516 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 517 unsigned RegBytes = RegVT.getSizeInBits() / 8; 518 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 519 520 // Make sure the stack slot is also aligned for the register type. 521 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 522 523 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 524 SmallVector<SDValue, 8> Stores; 525 SDValue StackPtr = StackBase; 526 unsigned Offset = 0; 527 528 // Do all but one copies using the full register width. 529 for (unsigned i = 1; i < NumRegs; i++) { 530 // Load one integer register's worth from the original location. 531 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 532 SVOffset + Offset, LD->isVolatile(), 533 MinAlign(LD->getAlignment(), Offset)); 534 // Follow the load with a store to the stack slot. Remember the store. 535 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 536 NULL, 0)); 537 // Increment the pointers. 538 Offset += RegBytes; 539 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 540 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 541 Increment); 542 } 543 544 // The last copy may be partial. Do an extending load. 545 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset)); 546 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 547 LD->getSrcValue(), SVOffset + Offset, 548 MemVT, LD->isVolatile(), 549 MinAlign(LD->getAlignment(), Offset)); 550 // Follow the load with a store to the stack slot. Remember the store. 551 // On big-endian machines this requires a truncating store to ensure 552 // that the bits end up in the right place. 553 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 554 NULL, 0, MemVT)); 555 556 // The order of the stores doesn't matter - say it with a TokenFactor. 557 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 558 Stores.size()); 559 560 // Finally, perform the original load only redirected to the stack slot. 561 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 562 NULL, 0, LoadedVT); 563 564 // Callers expect a MERGE_VALUES node. 565 SDValue Ops[] = { Load, TF }; 566 return DAG.getMergeValues(Ops, 2, dl); 567 } 568 } 569 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 570 "Unaligned load of unsupported type."); 571 572 // Compute the new VT that is half the size of the old one. This is an 573 // integer MVT. 574 unsigned NumBits = LoadedVT.getSizeInBits(); 575 MVT NewLoadedVT; 576 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 577 NumBits >>= 1; 578 579 unsigned Alignment = LD->getAlignment(); 580 unsigned IncrementSize = NumBits / 8; 581 ISD::LoadExtType HiExtType = LD->getExtensionType(); 582 583 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 584 if (HiExtType == ISD::NON_EXTLOAD) 585 HiExtType = ISD::ZEXTLOAD; 586 587 // Load the value in two parts 588 SDValue Lo, Hi; 589 if (TLI.isLittleEndian()) { 590 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 591 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 592 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 593 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 594 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 595 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 596 MinAlign(Alignment, IncrementSize)); 597 } else { 598 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 599 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 600 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 601 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 602 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 603 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 604 MinAlign(Alignment, IncrementSize)); 605 } 606 607 // aggregate the two parts 608 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 609 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 610 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 611 612 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 613 Hi.getValue(1)); 614 615 SDValue Ops[] = { Result, TF }; 616 return DAG.getMergeValues(Ops, 2, dl); 617} 618 619/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 620/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 621/// is necessary to spill the vector being inserted into to memory, perform 622/// the insert there, and then read the result back. 623SDValue SelectionDAGLegalize:: 624PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 625 DebugLoc dl) { 626 SDValue Tmp1 = Vec; 627 SDValue Tmp2 = Val; 628 SDValue Tmp3 = Idx; 629 630 // If the target doesn't support this, we have to spill the input vector 631 // to a temporary stack slot, update the element, then reload it. This is 632 // badness. We could also load the value into a vector register (either 633 // with a "move to register" or "extload into register" instruction, then 634 // permute it into place, if the idx is a constant and if the idx is 635 // supported by the target. 636 MVT VT = Tmp1.getValueType(); 637 MVT EltVT = VT.getVectorElementType(); 638 MVT IdxVT = Tmp3.getValueType(); 639 MVT PtrVT = TLI.getPointerTy(); 640 SDValue StackPtr = DAG.CreateStackTemporary(VT); 641 642 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 643 644 // Store the vector. 645 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 646 PseudoSourceValue::getFixedStack(SPFI), 0); 647 648 // Truncate or zero extend offset to target pointer type. 649 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 650 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 651 // Add the offset to the index. 652 unsigned EltSize = EltVT.getSizeInBits()/8; 653 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 654 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 655 // Store the scalar value. 656 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 657 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); 658 // Load the updated vector. 659 return DAG.getLoad(VT, dl, Ch, StackPtr, 660 PseudoSourceValue::getFixedStack(SPFI), 0); 661} 662 663 664SDValue SelectionDAGLegalize:: 665ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 666 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 667 // SCALAR_TO_VECTOR requires that the type of the value being inserted 668 // match the element type of the vector being created, except for 669 // integers in which case the inserted value can be over width. 670 MVT EltVT = Vec.getValueType().getVectorElementType(); 671 if (Val.getValueType() == EltVT || 672 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 673 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 674 Vec.getValueType(), Val); 675 676 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 677 // We generate a shuffle of InVec and ScVec, so the shuffle mask 678 // should be 0,1,2,3,4,5... with the appropriate element replaced with 679 // elt 0 of the RHS. 680 SmallVector<int, 8> ShufOps; 681 for (unsigned i = 0; i != NumElts; ++i) 682 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 683 684 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 685 &ShufOps[0]); 686 } 687 } 688 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 689} 690 691/// LegalizeOp - We know that the specified value has a legal type, and 692/// that its operands are legal. Now ensure that the operation itself 693/// is legal, recursively ensuring that the operands' operations remain 694/// legal. 695SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 696 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 697 return Op; 698 699 SDNode *Node = Op.getNode(); 700 DebugLoc dl = Node->getDebugLoc(); 701 702 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 703 assert(getTypeAction(Node->getValueType(i)) == Legal && 704 "Unexpected illegal type!"); 705 706 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 707 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 708 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 709 "Unexpected illegal type!"); 710 711 // Note that LegalizeOp may be reentered even from single-use nodes, which 712 // means that we always must cache transformed nodes. 713 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 714 if (I != LegalizedNodes.end()) return I->second; 715 716 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 717 SDValue Result = Op; 718 bool isCustom = false; 719 720 // Figure out the correct action; the way to query this varies by opcode 721 TargetLowering::LegalizeAction Action; 722 bool SimpleFinishLegalizing = true; 723 switch (Node->getOpcode()) { 724 case ISD::INTRINSIC_W_CHAIN: 725 case ISD::INTRINSIC_WO_CHAIN: 726 case ISD::INTRINSIC_VOID: 727 case ISD::VAARG: 728 case ISD::STACKSAVE: 729 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 730 break; 731 case ISD::SINT_TO_FP: 732 case ISD::UINT_TO_FP: 733 case ISD::EXTRACT_VECTOR_ELT: 734 Action = TLI.getOperationAction(Node->getOpcode(), 735 Node->getOperand(0).getValueType()); 736 break; 737 case ISD::FP_ROUND_INREG: 738 case ISD::SIGN_EXTEND_INREG: { 739 MVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 740 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 741 break; 742 } 743 case ISD::SELECT_CC: 744 case ISD::SETCC: 745 case ISD::BR_CC: { 746 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 747 Node->getOpcode() == ISD::SETCC ? 2 : 1; 748 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 749 MVT OpVT = Node->getOperand(CompareOperand).getValueType(); 750 ISD::CondCode CCCode = 751 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 752 Action = TLI.getCondCodeAction(CCCode, OpVT); 753 if (Action == TargetLowering::Legal) { 754 if (Node->getOpcode() == ISD::SELECT_CC) 755 Action = TLI.getOperationAction(Node->getOpcode(), 756 Node->getValueType(0)); 757 else 758 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 759 } 760 break; 761 } 762 case ISD::LOAD: 763 case ISD::STORE: 764 case ISD::FORMAL_ARGUMENTS: 765 case ISD::CALL: 766 case ISD::CALLSEQ_START: 767 case ISD::CALLSEQ_END: 768 // These instructions have properties that aren't modeled in the 769 // generic codepath 770 SimpleFinishLegalizing = false; 771 break; 772 case ISD::EXTRACT_ELEMENT: 773 case ISD::FLT_ROUNDS_: 774 case ISD::SADDO: 775 case ISD::SSUBO: 776 case ISD::UADDO: 777 case ISD::USUBO: 778 case ISD::SMULO: 779 case ISD::UMULO: 780 case ISD::FPOWI: 781 case ISD::MERGE_VALUES: 782 case ISD::EH_RETURN: 783 case ISD::FRAME_TO_ARGS_OFFSET: 784 // These operations lie about being legal: when they claim to be legal, 785 // they should actually be expanded. 786 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 787 if (Action == TargetLowering::Legal) 788 Action = TargetLowering::Expand; 789 break; 790 case ISD::TRAMPOLINE: 791 case ISD::FRAMEADDR: 792 case ISD::RETURNADDR: 793 // These operations lie about being legal: when they claim to be legal, 794 // they should actually be custom-lowered. 795 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 796 if (Action == TargetLowering::Legal) 797 Action = TargetLowering::Custom; 798 break; 799 case ISD::BUILD_VECTOR: 800 // A weird case: legalization for BUILD_VECTOR never legalizes the 801 // operands! 802 // FIXME: This really sucks... changing it isn't semantically incorrect, 803 // but it massively pessimizes the code for floating-point BUILD_VECTORs 804 // because ConstantFP operands get legalized into constant pool loads 805 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 806 // though, because BUILD_VECTORS usually get lowered into other nodes 807 // which get legalized properly. 808 SimpleFinishLegalizing = false; 809 break; 810 default: 811 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 812 Action = TargetLowering::Legal; 813 } else { 814 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 815 } 816 break; 817 } 818 819 if (SimpleFinishLegalizing) { 820 SmallVector<SDValue, 8> Ops, ResultVals; 821 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 822 Ops.push_back(LegalizeOp(Node->getOperand(i))); 823 switch (Node->getOpcode()) { 824 default: break; 825 case ISD::BR: 826 case ISD::BRIND: 827 case ISD::BR_JT: 828 case ISD::BR_CC: 829 case ISD::BRCOND: 830 case ISD::RET: 831 // Branches tweak the chain to include LastCALLSEQ_END 832 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 833 LastCALLSEQ_END); 834 Ops[0] = LegalizeOp(Ops[0]); 835 LastCALLSEQ_END = DAG.getEntryNode(); 836 break; 837 case ISD::SHL: 838 case ISD::SRL: 839 case ISD::SRA: 840 case ISD::ROTL: 841 case ISD::ROTR: 842 // Legalizing shifts/rotates requires adjusting the shift amount 843 // to the appropriate width. 844 if (!Ops[1].getValueType().isVector()) 845 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 846 break; 847 } 848 849 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(), 850 Ops.size()); 851 switch (Action) { 852 case TargetLowering::Legal: 853 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 854 ResultVals.push_back(Result.getValue(i)); 855 break; 856 case TargetLowering::Custom: 857 // FIXME: The handling for custom lowering with multiple results is 858 // a complete mess. 859 Tmp1 = TLI.LowerOperation(Result, DAG); 860 if (Tmp1.getNode()) { 861 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 862 if (e == 1) 863 ResultVals.push_back(Tmp1); 864 else 865 ResultVals.push_back(Tmp1.getValue(i)); 866 } 867 break; 868 } 869 870 // FALL THROUGH 871 case TargetLowering::Expand: 872 ExpandNode(Result.getNode(), ResultVals); 873 break; 874 case TargetLowering::Promote: 875 PromoteNode(Result.getNode(), ResultVals); 876 break; 877 } 878 if (!ResultVals.empty()) { 879 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 880 if (ResultVals[i] != SDValue(Node, i)) 881 ResultVals[i] = LegalizeOp(ResultVals[i]); 882 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 883 } 884 return ResultVals[Op.getResNo()]; 885 } 886 } 887 888 switch (Node->getOpcode()) { 889 default: 890#ifndef NDEBUG 891 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 892#endif 893 assert(0 && "Do not know how to legalize this operator!"); 894 abort(); 895 case ISD::FORMAL_ARGUMENTS: 896 case ISD::CALL: 897 // The only option for this is to custom lower it. 898 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 899 assert(Tmp3.getNode() && "Target didn't custom lower this node!"); 900 // A call within a calling sequence must be legalized to something 901 // other than the normal CALLSEQ_END. Violating this gets Legalize 902 // into an infinite loop. 903 assert ((!IsLegalizingCall || 904 Node->getOpcode() != ISD::CALL || 905 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) && 906 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 907 908 // The number of incoming and outgoing values should match; unless the final 909 // outgoing value is a flag. 910 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() || 911 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 && 912 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) == 913 MVT::Flag)) && 914 "Lowering call/formal_arguments produced unexpected # results!"); 915 916 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 917 // remember that we legalized all of them, so it doesn't get relegalized. 918 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) { 919 if (Tmp3.getNode()->getValueType(i) == MVT::Flag) 920 continue; 921 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 922 if (Op.getResNo() == i) 923 Tmp2 = Tmp1; 924 AddLegalizedOperand(SDValue(Node, i), Tmp1); 925 } 926 return Tmp2; 927 case ISD::BUILD_VECTOR: 928 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 929 default: assert(0 && "This action is not supported yet!"); 930 case TargetLowering::Custom: 931 Tmp3 = TLI.LowerOperation(Result, DAG); 932 if (Tmp3.getNode()) { 933 Result = Tmp3; 934 break; 935 } 936 // FALLTHROUGH 937 case TargetLowering::Expand: 938 Result = ExpandBUILD_VECTOR(Result.getNode()); 939 break; 940 } 941 break; 942 case ISD::CALLSEQ_START: { 943 SDNode *CallEnd = FindCallEndFromCallStart(Node); 944 945 // Recursively Legalize all of the inputs of the call end that do not lead 946 // to this call start. This ensures that any libcalls that need be inserted 947 // are inserted *before* the CALLSEQ_START. 948 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 949 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 950 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 951 NodesLeadingTo); 952 } 953 954 // Now that we legalized all of the inputs (which may have inserted 955 // libcalls) create the new CALLSEQ_START node. 956 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 957 958 // Merge in the last call, to ensure that this call start after the last 959 // call ended. 960 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 961 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 962 Tmp1, LastCALLSEQ_END); 963 Tmp1 = LegalizeOp(Tmp1); 964 } 965 966 // Do not try to legalize the target-specific arguments (#1+). 967 if (Tmp1 != Node->getOperand(0)) { 968 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 969 Ops[0] = Tmp1; 970 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 971 } 972 973 // Remember that the CALLSEQ_START is legalized. 974 AddLegalizedOperand(Op.getValue(0), Result); 975 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 976 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 977 978 // Now that the callseq_start and all of the non-call nodes above this call 979 // sequence have been legalized, legalize the call itself. During this 980 // process, no libcalls can/will be inserted, guaranteeing that no calls 981 // can overlap. 982 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 983 // Note that we are selecting this call! 984 LastCALLSEQ_END = SDValue(CallEnd, 0); 985 IsLegalizingCall = true; 986 987 // Legalize the call, starting from the CALLSEQ_END. 988 LegalizeOp(LastCALLSEQ_END); 989 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 990 return Result; 991 } 992 case ISD::CALLSEQ_END: 993 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 994 // will cause this node to be legalized as well as handling libcalls right. 995 if (LastCALLSEQ_END.getNode() != Node) { 996 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 997 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 998 assert(I != LegalizedNodes.end() && 999 "Legalizing the call start should have legalized this node!"); 1000 return I->second; 1001 } 1002 1003 // Otherwise, the call start has been legalized and everything is going 1004 // according to plan. Just legalize ourselves normally here. 1005 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1006 // Do not try to legalize the target-specific arguments (#1+), except for 1007 // an optional flag input. 1008 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1009 if (Tmp1 != Node->getOperand(0)) { 1010 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1011 Ops[0] = Tmp1; 1012 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1013 } 1014 } else { 1015 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1016 if (Tmp1 != Node->getOperand(0) || 1017 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1018 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1019 Ops[0] = Tmp1; 1020 Ops.back() = Tmp2; 1021 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1022 } 1023 } 1024 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1025 // This finishes up call legalization. 1026 IsLegalizingCall = false; 1027 1028 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1029 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1030 if (Node->getNumValues() == 2) 1031 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1032 return Result.getValue(Op.getResNo()); 1033 case ISD::BR_CC: 1034 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1035 // Ensure that libcalls are emitted before a branch. 1036 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 1037 Tmp1 = LegalizeOp(Tmp1); 1038 Tmp2 = Node->getOperand(2); // LHS 1039 Tmp3 = Node->getOperand(3); // RHS 1040 Tmp4 = Node->getOperand(1); // CC 1041 1042 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()), 1043 Tmp2, Tmp3, Tmp4, dl); 1044 LastCALLSEQ_END = DAG.getEntryNode(); 1045 1046 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 1047 // the LHS is a legal SETCC itself. In this case, we need to compare 1048 // the result against zero to select between true and false values. 1049 if (Tmp3.getNode() == 0) { 1050 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1051 Tmp4 = DAG.getCondCode(ISD::SETNE); 1052 } 1053 1054 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1055 Node->getOperand(4)); 1056 1057 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1058 default: assert(0 && "Unexpected action for BR_CC!"); 1059 case TargetLowering::Legal: break; 1060 case TargetLowering::Custom: 1061 Tmp4 = TLI.LowerOperation(Result, DAG); 1062 if (Tmp4.getNode()) Result = Tmp4; 1063 break; 1064 } 1065 break; 1066 case ISD::LOAD: { 1067 LoadSDNode *LD = cast<LoadSDNode>(Node); 1068 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1069 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1070 1071 ISD::LoadExtType ExtType = LD->getExtensionType(); 1072 if (ExtType == ISD::NON_EXTLOAD) { 1073 MVT VT = Node->getValueType(0); 1074 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1075 Tmp3 = Result.getValue(0); 1076 Tmp4 = Result.getValue(1); 1077 1078 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1079 default: assert(0 && "This action is not supported yet!"); 1080 case TargetLowering::Legal: 1081 // If this is an unaligned load and the target doesn't support it, 1082 // expand it. 1083 if (!TLI.allowsUnalignedMemoryAccesses()) { 1084 unsigned ABIAlignment = TLI.getTargetData()-> 1085 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 1086 if (LD->getAlignment() < ABIAlignment){ 1087 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 1088 TLI); 1089 Tmp3 = Result.getOperand(0); 1090 Tmp4 = Result.getOperand(1); 1091 Tmp3 = LegalizeOp(Tmp3); 1092 Tmp4 = LegalizeOp(Tmp4); 1093 } 1094 } 1095 break; 1096 case TargetLowering::Custom: 1097 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1098 if (Tmp1.getNode()) { 1099 Tmp3 = LegalizeOp(Tmp1); 1100 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1101 } 1102 break; 1103 case TargetLowering::Promote: { 1104 // Only promote a load of vector type to another. 1105 assert(VT.isVector() && "Cannot promote this load!"); 1106 // Change base type to a different vector type. 1107 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1108 1109 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1110 LD->getSrcValueOffset(), 1111 LD->isVolatile(), LD->getAlignment()); 1112 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1113 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1114 break; 1115 } 1116 } 1117 // Since loads produce two values, make sure to remember that we 1118 // legalized both of them. 1119 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1120 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1121 return Op.getResNo() ? Tmp4 : Tmp3; 1122 } else { 1123 MVT SrcVT = LD->getMemoryVT(); 1124 unsigned SrcWidth = SrcVT.getSizeInBits(); 1125 int SVOffset = LD->getSrcValueOffset(); 1126 unsigned Alignment = LD->getAlignment(); 1127 bool isVolatile = LD->isVolatile(); 1128 1129 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1130 // Some targets pretend to have an i1 loading operation, and actually 1131 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1132 // bits are guaranteed to be zero; it helps the optimizers understand 1133 // that these bits are zero. It is also useful for EXTLOAD, since it 1134 // tells the optimizers that those bits are undefined. It would be 1135 // nice to have an effective generic way of getting these benefits... 1136 // Until such a way is found, don't insist on promoting i1 here. 1137 (SrcVT != MVT::i1 || 1138 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1139 // Promote to a byte-sized load if not loading an integral number of 1140 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1141 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1142 MVT NVT = MVT::getIntegerVT(NewWidth); 1143 SDValue Ch; 1144 1145 // The extra bits are guaranteed to be zero, since we stored them that 1146 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1147 1148 ISD::LoadExtType NewExtType = 1149 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1150 1151 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 1152 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1153 NVT, isVolatile, Alignment); 1154 1155 Ch = Result.getValue(1); // The chain. 1156 1157 if (ExtType == ISD::SEXTLOAD) 1158 // Having the top bits zero doesn't help when sign extending. 1159 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1160 Result.getValueType(), 1161 Result, DAG.getValueType(SrcVT)); 1162 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1163 // All the top bits are guaranteed to be zero - inform the optimizers. 1164 Result = DAG.getNode(ISD::AssertZext, dl, 1165 Result.getValueType(), Result, 1166 DAG.getValueType(SrcVT)); 1167 1168 Tmp1 = LegalizeOp(Result); 1169 Tmp2 = LegalizeOp(Ch); 1170 } else if (SrcWidth & (SrcWidth - 1)) { 1171 // If not loading a power-of-2 number of bits, expand as two loads. 1172 assert(SrcVT.isExtended() && !SrcVT.isVector() && 1173 "Unsupported extload!"); 1174 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1175 assert(RoundWidth < SrcWidth); 1176 unsigned ExtraWidth = SrcWidth - RoundWidth; 1177 assert(ExtraWidth < RoundWidth); 1178 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1179 "Load size not an integral number of bytes!"); 1180 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 1181 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 1182 SDValue Lo, Hi, Ch; 1183 unsigned IncrementSize; 1184 1185 if (TLI.isLittleEndian()) { 1186 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1187 // Load the bottom RoundWidth bits. 1188 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1189 Node->getValueType(0), Tmp1, Tmp2, 1190 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1191 Alignment); 1192 1193 // Load the remaining ExtraWidth bits. 1194 IncrementSize = RoundWidth / 8; 1195 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1196 DAG.getIntPtrConstant(IncrementSize)); 1197 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1198 LD->getSrcValue(), SVOffset + IncrementSize, 1199 ExtraVT, isVolatile, 1200 MinAlign(Alignment, IncrementSize)); 1201 1202 // Build a factor node to remember that this load is independent of the 1203 // other one. 1204 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1205 Hi.getValue(1)); 1206 1207 // Move the top bits to the right place. 1208 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1209 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1210 1211 // Join the hi and lo parts. 1212 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1213 } else { 1214 // Big endian - avoid unaligned loads. 1215 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1216 // Load the top RoundWidth bits. 1217 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1218 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1219 Alignment); 1220 1221 // Load the remaining ExtraWidth bits. 1222 IncrementSize = RoundWidth / 8; 1223 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1224 DAG.getIntPtrConstant(IncrementSize)); 1225 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1226 Node->getValueType(0), Tmp1, Tmp2, 1227 LD->getSrcValue(), SVOffset + IncrementSize, 1228 ExtraVT, isVolatile, 1229 MinAlign(Alignment, IncrementSize)); 1230 1231 // Build a factor node to remember that this load is independent of the 1232 // other one. 1233 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1234 Hi.getValue(1)); 1235 1236 // Move the top bits to the right place. 1237 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1238 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1239 1240 // Join the hi and lo parts. 1241 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1242 } 1243 1244 Tmp1 = LegalizeOp(Result); 1245 Tmp2 = LegalizeOp(Ch); 1246 } else { 1247 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1248 default: assert(0 && "This action is not supported yet!"); 1249 case TargetLowering::Custom: 1250 isCustom = true; 1251 // FALLTHROUGH 1252 case TargetLowering::Legal: 1253 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1254 Tmp1 = Result.getValue(0); 1255 Tmp2 = Result.getValue(1); 1256 1257 if (isCustom) { 1258 Tmp3 = TLI.LowerOperation(Result, DAG); 1259 if (Tmp3.getNode()) { 1260 Tmp1 = LegalizeOp(Tmp3); 1261 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1262 } 1263 } else { 1264 // If this is an unaligned load and the target doesn't support it, 1265 // expand it. 1266 if (!TLI.allowsUnalignedMemoryAccesses()) { 1267 unsigned ABIAlignment = TLI.getTargetData()-> 1268 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 1269 if (LD->getAlignment() < ABIAlignment){ 1270 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 1271 TLI); 1272 Tmp1 = Result.getOperand(0); 1273 Tmp2 = Result.getOperand(1); 1274 Tmp1 = LegalizeOp(Tmp1); 1275 Tmp2 = LegalizeOp(Tmp2); 1276 } 1277 } 1278 } 1279 break; 1280 case TargetLowering::Expand: 1281 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1282 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1283 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1284 LD->getSrcValueOffset(), 1285 LD->isVolatile(), LD->getAlignment()); 1286 Result = DAG.getNode(ISD::FP_EXTEND, dl, 1287 Node->getValueType(0), Load); 1288 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1289 Tmp2 = LegalizeOp(Load.getValue(1)); 1290 break; 1291 } 1292 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1293 // Turn the unsupported load into an EXTLOAD followed by an explicit 1294 // zero/sign extend inreg. 1295 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1296 Tmp1, Tmp2, LD->getSrcValue(), 1297 LD->getSrcValueOffset(), SrcVT, 1298 LD->isVolatile(), LD->getAlignment()); 1299 SDValue ValRes; 1300 if (ExtType == ISD::SEXTLOAD) 1301 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1302 Result.getValueType(), 1303 Result, DAG.getValueType(SrcVT)); 1304 else 1305 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1306 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1307 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1308 break; 1309 } 1310 } 1311 1312 // Since loads produce two values, make sure to remember that we legalized 1313 // both of them. 1314 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1315 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1316 return Op.getResNo() ? Tmp2 : Tmp1; 1317 } 1318 } 1319 case ISD::STORE: { 1320 StoreSDNode *ST = cast<StoreSDNode>(Node); 1321 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1322 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1323 int SVOffset = ST->getSrcValueOffset(); 1324 unsigned Alignment = ST->getAlignment(); 1325 bool isVolatile = ST->isVolatile(); 1326 1327 if (!ST->isTruncatingStore()) { 1328 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1329 // FIXME: We shouldn't do this for TargetConstantFP's. 1330 // FIXME: move this to the DAG Combiner! Note that we can't regress due 1331 // to phase ordering between legalized code and the dag combiner. This 1332 // probably means that we need to integrate dag combiner and legalizer 1333 // together. 1334 // We generally can't do this one for long doubles. 1335 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 1336 if (CFP->getValueType(0) == MVT::f32 && 1337 getTypeAction(MVT::i32) == Legal) { 1338 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 1339 bitcastToAPInt().zextOrTrunc(32), 1340 MVT::i32); 1341 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1342 SVOffset, isVolatile, Alignment); 1343 break; 1344 } else if (CFP->getValueType(0) == MVT::f64) { 1345 // If this target supports 64-bit registers, do a single 64-bit store. 1346 if (getTypeAction(MVT::i64) == Legal) { 1347 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 1348 zextOrTrunc(64), MVT::i64); 1349 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1350 SVOffset, isVolatile, Alignment); 1351 break; 1352 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 1353 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 1354 // stores. If the target supports neither 32- nor 64-bits, this 1355 // xform is certainly not worth it. 1356 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 1357 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 1358 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 1359 if (TLI.isBigEndian()) std::swap(Lo, Hi); 1360 1361 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 1362 SVOffset, isVolatile, Alignment); 1363 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1364 DAG.getIntPtrConstant(4)); 1365 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 1366 isVolatile, MinAlign(Alignment, 4U)); 1367 1368 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1369 break; 1370 } 1371 } 1372 } 1373 1374 { 1375 Tmp3 = LegalizeOp(ST->getValue()); 1376 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1377 ST->getOffset()); 1378 1379 MVT VT = Tmp3.getValueType(); 1380 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1381 default: assert(0 && "This action is not supported yet!"); 1382 case TargetLowering::Legal: 1383 // If this is an unaligned store and the target doesn't support it, 1384 // expand it. 1385 if (!TLI.allowsUnalignedMemoryAccesses()) { 1386 unsigned ABIAlignment = TLI.getTargetData()-> 1387 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 1388 if (ST->getAlignment() < ABIAlignment) 1389 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 1390 TLI); 1391 } 1392 break; 1393 case TargetLowering::Custom: 1394 Tmp1 = TLI.LowerOperation(Result, DAG); 1395 if (Tmp1.getNode()) Result = Tmp1; 1396 break; 1397 case TargetLowering::Promote: 1398 assert(VT.isVector() && "Unknown legal promote case!"); 1399 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1400 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1401 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1402 ST->getSrcValue(), SVOffset, isVolatile, 1403 Alignment); 1404 break; 1405 } 1406 break; 1407 } 1408 } else { 1409 Tmp3 = LegalizeOp(ST->getValue()); 1410 1411 MVT StVT = ST->getMemoryVT(); 1412 unsigned StWidth = StVT.getSizeInBits(); 1413 1414 if (StWidth != StVT.getStoreSizeInBits()) { 1415 // Promote to a byte-sized store with upper bits zero if not 1416 // storing an integral number of bytes. For example, promote 1417 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1418 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 1419 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1420 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1421 SVOffset, NVT, isVolatile, Alignment); 1422 } else if (StWidth & (StWidth - 1)) { 1423 // If not storing a power-of-2 number of bits, expand as two stores. 1424 assert(StVT.isExtended() && !StVT.isVector() && 1425 "Unsupported truncstore!"); 1426 unsigned RoundWidth = 1 << Log2_32(StWidth); 1427 assert(RoundWidth < StWidth); 1428 unsigned ExtraWidth = StWidth - RoundWidth; 1429 assert(ExtraWidth < RoundWidth); 1430 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1431 "Store size not an integral number of bytes!"); 1432 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 1433 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 1434 SDValue Lo, Hi; 1435 unsigned IncrementSize; 1436 1437 if (TLI.isLittleEndian()) { 1438 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1439 // Store the bottom RoundWidth bits. 1440 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1441 SVOffset, RoundVT, 1442 isVolatile, Alignment); 1443 1444 // Store the remaining ExtraWidth bits. 1445 IncrementSize = RoundWidth / 8; 1446 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1447 DAG.getIntPtrConstant(IncrementSize)); 1448 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1449 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1450 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1451 SVOffset + IncrementSize, ExtraVT, isVolatile, 1452 MinAlign(Alignment, IncrementSize)); 1453 } else { 1454 // Big endian - avoid unaligned stores. 1455 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1456 // Store the top RoundWidth bits. 1457 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1458 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1459 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1460 SVOffset, RoundVT, isVolatile, Alignment); 1461 1462 // Store the remaining ExtraWidth bits. 1463 IncrementSize = RoundWidth / 8; 1464 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1465 DAG.getIntPtrConstant(IncrementSize)); 1466 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1467 SVOffset + IncrementSize, ExtraVT, isVolatile, 1468 MinAlign(Alignment, IncrementSize)); 1469 } 1470 1471 // The order of the stores doesn't matter. 1472 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1473 } else { 1474 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1475 Tmp2 != ST->getBasePtr()) 1476 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1477 ST->getOffset()); 1478 1479 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1480 default: assert(0 && "This action is not supported yet!"); 1481 case TargetLowering::Legal: 1482 // If this is an unaligned store and the target doesn't support it, 1483 // expand it. 1484 if (!TLI.allowsUnalignedMemoryAccesses()) { 1485 unsigned ABIAlignment = TLI.getTargetData()-> 1486 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 1487 if (ST->getAlignment() < ABIAlignment) 1488 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 1489 TLI); 1490 } 1491 break; 1492 case TargetLowering::Custom: 1493 Result = TLI.LowerOperation(Result, DAG); 1494 break; 1495 case Expand: 1496 // TRUNCSTORE:i16 i32 -> STORE i16 1497 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1498 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1499 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1500 SVOffset, isVolatile, Alignment); 1501 break; 1502 } 1503 } 1504 } 1505 break; 1506 } 1507 case ISD::SELECT_CC: { 1508 Tmp1 = Node->getOperand(0); // LHS 1509 Tmp2 = Node->getOperand(1); // RHS 1510 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1511 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1512 SDValue CC = Node->getOperand(4); 1513 1514 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), 1515 Tmp1, Tmp2, CC, dl); 1516 1517 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 1518 // the LHS is a legal SETCC itself. In this case, we need to compare 1519 // the result against zero to select between true and false values. 1520 if (Tmp2.getNode() == 0) { 1521 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1522 CC = DAG.getCondCode(ISD::SETNE); 1523 } 1524 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 1525 1526 // Everything is legal, see if we should expand this op or something. 1527 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 1528 default: assert(0 && "This action is not supported yet!"); 1529 case TargetLowering::Legal: break; 1530 case TargetLowering::Custom: 1531 Tmp1 = TLI.LowerOperation(Result, DAG); 1532 if (Tmp1.getNode()) Result = Tmp1; 1533 break; 1534 } 1535 break; 1536 } 1537 case ISD::SETCC: 1538 Tmp1 = Node->getOperand(0); 1539 Tmp2 = Node->getOperand(1); 1540 Tmp3 = Node->getOperand(2); 1541 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 1542 1543 // If we had to Expand the SetCC operands into a SELECT node, then it may 1544 // not always be possible to return a true LHS & RHS. In this case, just 1545 // return the value we legalized, returned in the LHS 1546 if (Tmp2.getNode() == 0) { 1547 Result = Tmp1; 1548 break; 1549 } 1550 1551 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 1552 default: assert(0 && "Cannot handle this action for SETCC yet!"); 1553 case TargetLowering::Custom: 1554 isCustom = true; 1555 // FALLTHROUGH. 1556 case TargetLowering::Legal: 1557 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1558 if (isCustom) { 1559 Tmp4 = TLI.LowerOperation(Result, DAG); 1560 if (Tmp4.getNode()) Result = Tmp4; 1561 } 1562 break; 1563 case TargetLowering::Promote: { 1564 // First step, figure out the appropriate operation to use. 1565 // Allow SETCC to not be supported for all legal data types 1566 // Mostly this targets FP 1567 MVT NewInTy = Node->getOperand(0).getValueType(); 1568 MVT OldVT = NewInTy; OldVT = OldVT; 1569 1570 // Scan for the appropriate larger type to use. 1571 while (1) { 1572 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 1573 1574 assert(NewInTy.isInteger() == OldVT.isInteger() && 1575 "Fell off of the edge of the integer world"); 1576 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 1577 "Fell off of the edge of the floating point world"); 1578 1579 // If the target supports SETCC of this type, use it. 1580 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy)) 1581 break; 1582 } 1583 if (NewInTy.isInteger()) 1584 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1585 else { 1586 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1); 1587 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2); 1588 } 1589 Tmp1 = LegalizeOp(Tmp1); 1590 Tmp2 = LegalizeOp(Tmp2); 1591 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1592 Result = LegalizeOp(Result); 1593 break; 1594 } 1595 case TargetLowering::Expand: 1596 // Expand a setcc node into a select_cc of the same condition, lhs, and 1597 // rhs that selects between const 1 (true) and const 0 (false). 1598 MVT VT = Node->getValueType(0); 1599 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 1600 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1601 Tmp3); 1602 break; 1603 } 1604 break; 1605 } 1606 1607 assert(Result.getValueType() == Op.getValueType() && 1608 "Bad legalization!"); 1609 1610 // Make sure that the generated code is itself legal. 1611 if (Result != Op) 1612 Result = LegalizeOp(Result); 1613 1614 // Note that LegalizeOp may be reentered even from single-use nodes, which 1615 // means that we always must cache transformed nodes. 1616 AddLegalizedOperand(Op, Result); 1617 return Result; 1618} 1619 1620SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1621 SDValue Vec = Op.getOperand(0); 1622 SDValue Idx = Op.getOperand(1); 1623 DebugLoc dl = Op.getDebugLoc(); 1624 // Store the value to a temporary stack slot, then LOAD the returned part. 1625 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1626 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0); 1627 1628 // Add the offset to the index. 1629 unsigned EltSize = 1630 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1631 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1632 DAG.getConstant(EltSize, Idx.getValueType())); 1633 1634 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1635 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1636 else 1637 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1638 1639 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1640 1641 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0); 1642} 1643 1644SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1645 DebugLoc dl = Node->getDebugLoc(); 1646 SDValue Tmp1 = Node->getOperand(0); 1647 SDValue Tmp2 = Node->getOperand(1); 1648 assert((Tmp2.getValueType() == MVT::f32 || 1649 Tmp2.getValueType() == MVT::f64) && 1650 "Ugly special-cased code!"); 1651 // Get the sign bit of the RHS. 1652 SDValue SignBit; 1653 MVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32; 1654 if (isTypeLegal(IVT)) { 1655 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 1656 } else { 1657 assert(isTypeLegal(TLI.getPointerTy()) && 1658 (TLI.getPointerTy() == MVT::i32 || 1659 TLI.getPointerTy() == MVT::i64) && 1660 "Legal type for load?!"); 1661 SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType()); 1662 SDValue StorePtr = StackPtr, LoadPtr = StackPtr; 1663 SDValue Ch = 1664 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0); 1665 if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian()) 1666 LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), 1667 LoadPtr, DAG.getIntPtrConstant(4)); 1668 SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(), 1669 Ch, LoadPtr, NULL, 0, MVT::i32); 1670 } 1671 SignBit = 1672 DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1673 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1674 ISD::SETLT); 1675 // Get the absolute value of the result. 1676 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1677 // Select between the nabs and abs value based on the sign bit of 1678 // the input. 1679 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1680 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1681 AbsVal); 1682} 1683 1684SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) { 1685 DebugLoc dl = Node->getDebugLoc(); 1686 DwarfWriter *DW = DAG.getDwarfWriter(); 1687 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC, 1688 MVT::Other); 1689 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other); 1690 1691 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 1692 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit()); 1693 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) { 1694 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit())); 1695 1696 unsigned Line = DSP->getLine(); 1697 unsigned Col = DSP->getColumn(); 1698 1699 if (OptLevel == CodeGenOpt::None) { 1700 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it 1701 // won't hurt anything. 1702 if (useDEBUG_LOC) { 1703 return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0), 1704 DAG.getConstant(Line, MVT::i32), 1705 DAG.getConstant(Col, MVT::i32), 1706 DAG.getSrcValue(CU.getGV())); 1707 } else { 1708 unsigned ID = DW->RecordSourceLine(Line, Col, CU); 1709 return DAG.getLabel(ISD::DBG_LABEL, dl, Node->getOperand(0), ID); 1710 } 1711 } 1712 } 1713 return Node->getOperand(0); 1714} 1715 1716void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1717 SmallVectorImpl<SDValue> &Results) { 1718 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1719 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1720 " not tell us which reg is the stack pointer!"); 1721 DebugLoc dl = Node->getDebugLoc(); 1722 MVT VT = Node->getValueType(0); 1723 SDValue Tmp1 = SDValue(Node, 0); 1724 SDValue Tmp2 = SDValue(Node, 1); 1725 SDValue Tmp3 = Node->getOperand(2); 1726 SDValue Chain = Tmp1.getOperand(0); 1727 1728 // Chain the dynamic stack allocation so that it doesn't modify the stack 1729 // pointer when other instructions are using the stack. 1730 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1731 1732 SDValue Size = Tmp2.getOperand(1); 1733 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1734 Chain = SP.getValue(1); 1735 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1736 unsigned StackAlign = 1737 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1738 if (Align > StackAlign) 1739 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1740 DAG.getConstant(-(uint64_t)Align, VT)); 1741 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1742 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1743 1744 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1745 DAG.getIntPtrConstant(0, true), SDValue()); 1746 1747 Results.push_back(Tmp1); 1748 Results.push_back(Tmp2); 1749} 1750 1751/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 1752/// with condition CC on the current target. This usually involves legalizing 1753/// or promoting the arguments. In the case where LHS and RHS must be expanded, 1754/// there may be no choice but to create a new SetCC node to represent the 1755/// legalized value of setcc lhs, rhs. In this case, the value is returned in 1756/// LHS, and the SDValue returned in RHS has a nil SDNode value. 1757void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS, 1758 SDValue &RHS, 1759 SDValue &CC, 1760 DebugLoc dl) { 1761 LHS = LegalizeOp(LHS); 1762 RHS = LegalizeOp(RHS); 1763} 1764 1765/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1766/// condition code CC on the current target. This routine assumes LHS and rHS 1767/// have already been legalized by LegalizeSetCCOperands. It expands SETCC with 1768/// illegal condition code into AND / OR of multiple SETCC values. 1769void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, 1770 SDValue &LHS, SDValue &RHS, 1771 SDValue &CC, 1772 DebugLoc dl) { 1773 MVT OpVT = LHS.getValueType(); 1774 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1775 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1776 default: assert(0 && "Unknown condition code action!"); 1777 case TargetLowering::Legal: 1778 // Nothing to do. 1779 break; 1780 case TargetLowering::Expand: { 1781 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1782 unsigned Opc = 0; 1783 switch (CCCode) { 1784 default: assert(0 && "Don't know how to expand this condition!"); abort(); 1785 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1786 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1787 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1788 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1789 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1790 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1791 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1792 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1793 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1794 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1795 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1796 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1797 // FIXME: Implement more expansions. 1798 } 1799 1800 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1801 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1802 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1803 RHS = SDValue(); 1804 CC = SDValue(); 1805 break; 1806 } 1807 } 1808} 1809 1810/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1811/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1812/// a load from the stack slot to DestVT, extending it if needed. 1813/// The resultant code need not be legal. 1814SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1815 MVT SlotVT, 1816 MVT DestVT, 1817 DebugLoc dl) { 1818 // Create the stack frame object. 1819 unsigned SrcAlign = 1820 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1821 getTypeForMVT()); 1822 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1823 1824 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1825 int SPFI = StackPtrFI->getIndex(); 1826 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1827 1828 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1829 unsigned SlotSize = SlotVT.getSizeInBits(); 1830 unsigned DestSize = DestVT.getSizeInBits(); 1831 unsigned DestAlign = 1832 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT()); 1833 1834 // Emit a store to the stack slot. Use a truncstore if the input value is 1835 // later than DestVT. 1836 SDValue Store; 1837 1838 if (SrcSize > SlotSize) 1839 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1840 SV, 0, SlotVT, false, SrcAlign); 1841 else { 1842 assert(SrcSize == SlotSize && "Invalid store"); 1843 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1844 SV, 0, false, SrcAlign); 1845 } 1846 1847 // Result is a load from the stack slot. 1848 if (SlotSize == DestSize) 1849 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign); 1850 1851 assert(SlotSize < DestSize && "Unknown extension!"); 1852 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, 1853 false, DestAlign); 1854} 1855 1856SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1857 DebugLoc dl = Node->getDebugLoc(); 1858 // Create a vector sized/aligned stack slot, store the value to element #0, 1859 // then load the whole vector back out. 1860 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1861 1862 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1863 int SPFI = StackPtrFI->getIndex(); 1864 1865 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1866 StackPtr, 1867 PseudoSourceValue::getFixedStack(SPFI), 0, 1868 Node->getValueType(0).getVectorElementType()); 1869 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1870 PseudoSourceValue::getFixedStack(SPFI), 0); 1871} 1872 1873 1874/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1875/// support the operation, but do support the resultant vector type. 1876SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1877 unsigned NumElems = Node->getNumOperands(); 1878 SDValue SplatValue = Node->getOperand(0); 1879 DebugLoc dl = Node->getDebugLoc(); 1880 MVT VT = Node->getValueType(0); 1881 MVT OpVT = SplatValue.getValueType(); 1882 MVT EltVT = VT.getVectorElementType(); 1883 1884 // If the only non-undef value is the low element, turn this into a 1885 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1886 bool isOnlyLowElement = true; 1887 1888 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t> 1889 // and use a bitmask instead of a list of elements. 1890 // FIXME: this doesn't treat <0, u, 0, u> for example, as a splat. 1891 std::map<SDValue, std::vector<unsigned> > Values; 1892 Values[SplatValue].push_back(0); 1893 bool isConstant = true; 1894 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 1895 SplatValue.getOpcode() != ISD::UNDEF) 1896 isConstant = false; 1897 1898 for (unsigned i = 1; i < NumElems; ++i) { 1899 SDValue V = Node->getOperand(i); 1900 Values[V].push_back(i); 1901 if (V.getOpcode() != ISD::UNDEF) 1902 isOnlyLowElement = false; 1903 if (SplatValue != V) 1904 SplatValue = SDValue(0, 0); 1905 1906 // If this isn't a constant element or an undef, we can't use a constant 1907 // pool load. 1908 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 1909 V.getOpcode() != ISD::UNDEF) 1910 isConstant = false; 1911 } 1912 1913 if (isOnlyLowElement) { 1914 // If the low element is an undef too, then this whole things is an undef. 1915 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 1916 return DAG.getUNDEF(VT); 1917 // Otherwise, turn this into a scalar_to_vector node. 1918 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1919 } 1920 1921 // If all elements are constants, create a load from the constant pool. 1922 if (isConstant) { 1923 std::vector<Constant*> CV; 1924 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1925 if (ConstantFPSDNode *V = 1926 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1927 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1928 } else if (ConstantSDNode *V = 1929 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1930 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1931 } else { 1932 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1933 const Type *OpNTy = OpVT.getTypeForMVT(); 1934 CV.push_back(UndefValue::get(OpNTy)); 1935 } 1936 } 1937 Constant *CP = ConstantVector::get(CV); 1938 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1939 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1940 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1941 PseudoSourceValue::getConstantPool(), 0, 1942 false, Alignment); 1943 } 1944 1945 if (SplatValue.getNode()) { // Splat of one value? 1946 // Build the shuffle constant vector: <0, 0, 0, 0> 1947 SmallVector<int, 8> ZeroVec(NumElems, 0); 1948 1949 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 1950 if (TLI.isShuffleMaskLegal(ZeroVec, Node->getValueType(0))) { 1951 // Get the splatted value into the low element of a vector register. 1952 SDValue LowValVec = 1953 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, SplatValue); 1954 1955 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1956 return DAG.getVectorShuffle(VT, dl, LowValVec, DAG.getUNDEF(VT), 1957 &ZeroVec[0]); 1958 } 1959 } 1960 1961 // If there are only two unique elements, we may be able to turn this into a 1962 // vector shuffle. 1963 if (Values.size() == 2) { 1964 // Get the two values in deterministic order. 1965 SDValue Val1 = Node->getOperand(1); 1966 SDValue Val2; 1967 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin(); 1968 if (MI->first != Val1) 1969 Val2 = MI->first; 1970 else 1971 Val2 = (++MI)->first; 1972 1973 // If Val1 is an undef, make sure it ends up as Val2, to ensure that our 1974 // vector shuffle has the undef vector on the RHS. 1975 if (Val1.getOpcode() == ISD::UNDEF) 1976 std::swap(Val1, Val2); 1977 1978 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 1979 SmallVector<int, 8> ShuffleMask(NumElems, -1); 1980 1981 // Set elements of the shuffle mask for Val1. 1982 std::vector<unsigned> &Val1Elts = Values[Val1]; 1983 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 1984 ShuffleMask[Val1Elts[i]] = 0; 1985 1986 // Set elements of the shuffle mask for Val2. 1987 std::vector<unsigned> &Val2Elts = Values[Val2]; 1988 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 1989 if (Val2.getOpcode() != ISD::UNDEF) 1990 ShuffleMask[Val2Elts[i]] = NumElems; 1991 1992 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 1993 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, VT) && 1994 TLI.isShuffleMaskLegal(ShuffleMask, VT)) { 1995 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val1); 1996 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val2); 1997 return DAG.getVectorShuffle(VT, dl, Val1, Val2, &ShuffleMask[0]); 1998 } 1999 } 2000 2001 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 2002 // aligned object on the stack, store each element into it, then load 2003 // the result as a vector. 2004 // Create the stack frame object. 2005 SDValue FIPtr = DAG.CreateStackTemporary(VT); 2006 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 2007 const Value *SV = PseudoSourceValue::getFixedStack(FI); 2008 2009 // Emit a store of each element to the stack slot. 2010 SmallVector<SDValue, 8> Stores; 2011 unsigned TypeByteSize = OpVT.getSizeInBits() / 8; 2012 // Store (in the right endianness) the elements to memory. 2013 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2014 // Ignore undef elements. 2015 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 2016 2017 unsigned Offset = TypeByteSize*i; 2018 2019 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 2020 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 2021 2022 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i), 2023 Idx, SV, Offset)); 2024 } 2025 2026 SDValue StoreChain; 2027 if (!Stores.empty()) // Not all undef elements? 2028 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2029 &Stores[0], Stores.size()); 2030 else 2031 StoreChain = DAG.getEntryNode(); 2032 2033 // Result is a load from the stack slot. 2034 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0); 2035} 2036 2037// ExpandLibCall - Expand a node into a call to a libcall. If the result value 2038// does not fit into a register, return the lo part and set the hi part to the 2039// by-reg argument. If it does fit into a single register, return the result 2040// and leave the Hi part unset. 2041SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 2042 bool isSigned) { 2043 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 2044 // The input chain to this libcall is the entry node of the function. 2045 // Legalizing the call will automatically add the previous call to the 2046 // dependence. 2047 SDValue InChain = DAG.getEntryNode(); 2048 2049 TargetLowering::ArgListTy Args; 2050 TargetLowering::ArgListEntry Entry; 2051 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2052 MVT ArgVT = Node->getOperand(i).getValueType(); 2053 const Type *ArgTy = ArgVT.getTypeForMVT(); 2054 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 2055 Entry.isSExt = isSigned; 2056 Entry.isZExt = !isSigned; 2057 Args.push_back(Entry); 2058 } 2059 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 2060 TLI.getPointerTy()); 2061 2062 // Splice the libcall in wherever FindInputOutputChains tells us to. 2063 const Type *RetTy = Node->getValueType(0).getTypeForMVT(); 2064 std::pair<SDValue, SDValue> CallInfo = 2065 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 2066 CallingConv::C, false, Callee, Args, DAG, 2067 Node->getDebugLoc()); 2068 2069 // Legalize the call sequence, starting with the chain. This will advance 2070 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 2071 // was added by LowerCallTo (guaranteeing proper serialization of calls). 2072 LegalizeOp(CallInfo.second); 2073 return CallInfo.first; 2074} 2075 2076SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 2077 RTLIB::Libcall Call_F32, 2078 RTLIB::Libcall Call_F64, 2079 RTLIB::Libcall Call_F80, 2080 RTLIB::Libcall Call_PPCF128) { 2081 RTLIB::Libcall LC; 2082 switch (Node->getValueType(0).getSimpleVT()) { 2083 default: assert(0 && "Unexpected request for libcall!"); 2084 case MVT::f32: LC = Call_F32; break; 2085 case MVT::f64: LC = Call_F64; break; 2086 case MVT::f80: LC = Call_F80; break; 2087 case MVT::ppcf128: LC = Call_PPCF128; break; 2088 } 2089 return ExpandLibCall(LC, Node, false); 2090} 2091 2092SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 2093 RTLIB::Libcall Call_I16, 2094 RTLIB::Libcall Call_I32, 2095 RTLIB::Libcall Call_I64, 2096 RTLIB::Libcall Call_I128) { 2097 RTLIB::Libcall LC; 2098 switch (Node->getValueType(0).getSimpleVT()) { 2099 default: assert(0 && "Unexpected request for libcall!"); 2100 case MVT::i16: LC = Call_I16; break; 2101 case MVT::i32: LC = Call_I32; break; 2102 case MVT::i64: LC = Call_I64; break; 2103 case MVT::i128: LC = Call_I128; break; 2104 } 2105 return ExpandLibCall(LC, Node, isSigned); 2106} 2107 2108/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 2109/// INT_TO_FP operation of the specified operand when the target requests that 2110/// we expand it. At this point, we know that the result and operand types are 2111/// legal for the target. 2112SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 2113 SDValue Op0, 2114 MVT DestVT, 2115 DebugLoc dl) { 2116 if (Op0.getValueType() == MVT::i32) { 2117 // simple 32-bit [signed|unsigned] integer to float/double expansion 2118 2119 // Get the stack frame index of a 8 byte buffer. 2120 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 2121 2122 // word offset constant for Hi/Lo address computation 2123 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 2124 // set up Hi and Lo (into buffer) address based on endian 2125 SDValue Hi = StackSlot; 2126 SDValue Lo = DAG.getNode(ISD::ADD, dl, 2127 TLI.getPointerTy(), StackSlot, WordOff); 2128 if (TLI.isLittleEndian()) 2129 std::swap(Hi, Lo); 2130 2131 // if signed map to unsigned space 2132 SDValue Op0Mapped; 2133 if (isSigned) { 2134 // constant used to invert sign bit (signed to unsigned mapping) 2135 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 2136 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 2137 } else { 2138 Op0Mapped = Op0; 2139 } 2140 // store the lo of the constructed double - based on integer input 2141 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 2142 Op0Mapped, Lo, NULL, 0); 2143 // initial hi portion of constructed double 2144 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 2145 // store the hi of the constructed double - biased exponent 2146 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0); 2147 // load the constructed double 2148 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0); 2149 // FP constant to bias correct the final result 2150 SDValue Bias = DAG.getConstantFP(isSigned ? 2151 BitsToDouble(0x4330000080000000ULL) : 2152 BitsToDouble(0x4330000000000000ULL), 2153 MVT::f64); 2154 // subtract the bias 2155 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2156 // final result 2157 SDValue Result; 2158 // handle final rounding 2159 if (DestVT == MVT::f64) { 2160 // do nothing 2161 Result = Sub; 2162 } else if (DestVT.bitsLT(MVT::f64)) { 2163 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2164 DAG.getIntPtrConstant(0)); 2165 } else if (DestVT.bitsGT(MVT::f64)) { 2166 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2167 } 2168 return Result; 2169 } 2170 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2171 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2172 2173 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2174 Op0, DAG.getConstant(0, Op0.getValueType()), 2175 ISD::SETLT); 2176 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2177 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2178 SignSet, Four, Zero); 2179 2180 // If the sign bit of the integer is set, the large number will be treated 2181 // as a negative number. To counteract this, the dynamic code adds an 2182 // offset depending on the data type. 2183 uint64_t FF; 2184 switch (Op0.getValueType().getSimpleVT()) { 2185 default: assert(0 && "Unsupported integer type!"); 2186 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2187 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2188 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2189 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2190 } 2191 if (TLI.isLittleEndian()) FF <<= 32; 2192 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 2193 2194 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2195 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2196 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2197 Alignment = std::min(Alignment, 4u); 2198 SDValue FudgeInReg; 2199 if (DestVT == MVT::f32) 2200 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2201 PseudoSourceValue::getConstantPool(), 0, 2202 false, Alignment); 2203 else { 2204 FudgeInReg = 2205 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2206 DAG.getEntryNode(), CPIdx, 2207 PseudoSourceValue::getConstantPool(), 0, 2208 MVT::f32, false, Alignment)); 2209 } 2210 2211 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2212} 2213 2214/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2215/// *INT_TO_FP operation of the specified operand when the target requests that 2216/// we promote it. At this point, we know that the result and operand types are 2217/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2218/// operation that takes a larger input. 2219SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2220 MVT DestVT, 2221 bool isSigned, 2222 DebugLoc dl) { 2223 // First step, figure out the appropriate *INT_TO_FP operation to use. 2224 MVT NewInTy = LegalOp.getValueType(); 2225 2226 unsigned OpToUse = 0; 2227 2228 // Scan for the appropriate larger type to use. 2229 while (1) { 2230 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 2231 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2232 2233 // If the target supports SINT_TO_FP of this type, use it. 2234 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2235 OpToUse = ISD::SINT_TO_FP; 2236 break; 2237 } 2238 if (isSigned) continue; 2239 2240 // If the target supports UINT_TO_FP of this type, use it. 2241 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2242 OpToUse = ISD::UINT_TO_FP; 2243 break; 2244 } 2245 2246 // Otherwise, try a larger type. 2247 } 2248 2249 // Okay, we found the operation and type to use. Zero extend our input to the 2250 // desired type then run the operation on it. 2251 return DAG.getNode(OpToUse, dl, DestVT, 2252 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2253 dl, NewInTy, LegalOp)); 2254} 2255 2256/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2257/// FP_TO_*INT operation of the specified operand when the target requests that 2258/// we promote it. At this point, we know that the result and operand types are 2259/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2260/// operation that returns a larger result. 2261SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2262 MVT DestVT, 2263 bool isSigned, 2264 DebugLoc dl) { 2265 // First step, figure out the appropriate FP_TO*INT operation to use. 2266 MVT NewOutTy = DestVT; 2267 2268 unsigned OpToUse = 0; 2269 2270 // Scan for the appropriate larger type to use. 2271 while (1) { 2272 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 2273 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2274 2275 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2276 OpToUse = ISD::FP_TO_SINT; 2277 break; 2278 } 2279 2280 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2281 OpToUse = ISD::FP_TO_UINT; 2282 break; 2283 } 2284 2285 // Otherwise, try a larger type. 2286 } 2287 2288 2289 // Okay, we found the operation and type to use. 2290 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2291 2292 // Truncate the result of the extended FP_TO_*INT operation to the desired 2293 // size. 2294 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2295} 2296 2297/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2298/// 2299SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2300 MVT VT = Op.getValueType(); 2301 MVT SHVT = TLI.getShiftAmountTy(); 2302 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2303 switch (VT.getSimpleVT()) { 2304 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 2305 case MVT::i16: 2306 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2307 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2308 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2309 case MVT::i32: 2310 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2311 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2312 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2313 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2314 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2315 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2316 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2317 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2318 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2319 case MVT::i64: 2320 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2321 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2322 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2323 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2324 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2325 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2326 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2327 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2328 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2329 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2330 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2331 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2332 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2333 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2334 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2335 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2336 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2337 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2338 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2339 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2340 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2341 } 2342} 2343 2344/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2345/// 2346SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2347 DebugLoc dl) { 2348 switch (Opc) { 2349 default: assert(0 && "Cannot expand this yet!"); 2350 case ISD::CTPOP: { 2351 static const uint64_t mask[6] = { 2352 0x5555555555555555ULL, 0x3333333333333333ULL, 2353 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2354 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2355 }; 2356 MVT VT = Op.getValueType(); 2357 MVT ShVT = TLI.getShiftAmountTy(); 2358 unsigned len = VT.getSizeInBits(); 2359 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2360 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2361 unsigned EltSize = VT.isVector() ? 2362 VT.getVectorElementType().getSizeInBits() : len; 2363 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2364 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2365 Op = DAG.getNode(ISD::ADD, dl, VT, 2366 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2367 DAG.getNode(ISD::AND, dl, VT, 2368 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2369 Tmp2)); 2370 } 2371 return Op; 2372 } 2373 case ISD::CTLZ: { 2374 // for now, we do this: 2375 // x = x | (x >> 1); 2376 // x = x | (x >> 2); 2377 // ... 2378 // x = x | (x >>16); 2379 // x = x | (x >>32); // for 64-bit input 2380 // return popcount(~x); 2381 // 2382 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2383 MVT VT = Op.getValueType(); 2384 MVT ShVT = TLI.getShiftAmountTy(); 2385 unsigned len = VT.getSizeInBits(); 2386 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2387 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2388 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2389 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2390 } 2391 Op = DAG.getNOT(dl, Op, VT); 2392 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2393 } 2394 case ISD::CTTZ: { 2395 // for now, we use: { return popcount(~x & (x - 1)); } 2396 // unless the target has ctlz but not ctpop, in which case we use: 2397 // { return 32 - nlz(~x & (x-1)); } 2398 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2399 MVT VT = Op.getValueType(); 2400 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2401 DAG.getNOT(dl, Op, VT), 2402 DAG.getNode(ISD::SUB, dl, VT, Op, 2403 DAG.getConstant(1, VT))); 2404 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2405 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2406 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2407 return DAG.getNode(ISD::SUB, dl, VT, 2408 DAG.getConstant(VT.getSizeInBits(), VT), 2409 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2410 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2411 } 2412 } 2413} 2414 2415void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2416 SmallVectorImpl<SDValue> &Results) { 2417 DebugLoc dl = Node->getDebugLoc(); 2418 SDValue Tmp1, Tmp2, Tmp3; 2419 switch (Node->getOpcode()) { 2420 case ISD::CTPOP: 2421 case ISD::CTLZ: 2422 case ISD::CTTZ: 2423 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2424 Results.push_back(Tmp1); 2425 break; 2426 case ISD::BSWAP: 2427 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2428 break; 2429 case ISD::FRAMEADDR: 2430 case ISD::RETURNADDR: 2431 case ISD::FRAME_TO_ARGS_OFFSET: 2432 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2433 break; 2434 case ISD::FLT_ROUNDS_: 2435 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2436 break; 2437 case ISD::EH_RETURN: 2438 case ISD::DECLARE: 2439 case ISD::DBG_LABEL: 2440 case ISD::EH_LABEL: 2441 case ISD::PREFETCH: 2442 case ISD::MEMBARRIER: 2443 case ISD::VAEND: 2444 Results.push_back(Node->getOperand(0)); 2445 break; 2446 case ISD::DBG_STOPPOINT: 2447 Results.push_back(ExpandDBG_STOPPOINT(Node)); 2448 break; 2449 case ISD::DYNAMIC_STACKALLOC: 2450 ExpandDYNAMIC_STACKALLOC(Node, Results); 2451 break; 2452 case ISD::MERGE_VALUES: 2453 for (unsigned i = 0; i < Node->getNumValues(); i++) 2454 Results.push_back(Node->getOperand(i)); 2455 break; 2456 case ISD::UNDEF: { 2457 MVT VT = Node->getValueType(0); 2458 if (VT.isInteger()) 2459 Results.push_back(DAG.getConstant(0, VT)); 2460 else if (VT.isFloatingPoint()) 2461 Results.push_back(DAG.getConstantFP(0, VT)); 2462 else 2463 assert(0 && "Unknown value type!"); 2464 break; 2465 } 2466 case ISD::TRAP: { 2467 // If this operation is not supported, lower it to 'abort()' call 2468 TargetLowering::ArgListTy Args; 2469 std::pair<SDValue, SDValue> CallResult = 2470 TLI.LowerCallTo(Node->getOperand(0), Type::VoidTy, 2471 false, false, false, false, CallingConv::C, false, 2472 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2473 Args, DAG, dl); 2474 Results.push_back(CallResult.second); 2475 break; 2476 } 2477 case ISD::FP_ROUND: 2478 case ISD::BIT_CONVERT: 2479 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2480 Node->getValueType(0), dl); 2481 Results.push_back(Tmp1); 2482 break; 2483 case ISD::FP_EXTEND: 2484 Tmp1 = EmitStackConvert(Node->getOperand(0), 2485 Node->getOperand(0).getValueType(), 2486 Node->getValueType(0), dl); 2487 Results.push_back(Tmp1); 2488 break; 2489 case ISD::SIGN_EXTEND_INREG: { 2490 // NOTE: we could fall back on load/store here too for targets without 2491 // SAR. However, it is doubtful that any exist. 2492 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2493 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 2494 ExtraVT.getSizeInBits(); 2495 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2496 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2497 Node->getOperand(0), ShiftCst); 2498 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2499 Results.push_back(Tmp1); 2500 break; 2501 } 2502 case ISD::FP_ROUND_INREG: { 2503 // The only way we can lower this is to turn it into a TRUNCSTORE, 2504 // EXTLOAD pair, targetting a temporary location (a stack slot). 2505 2506 // NOTE: there is a choice here between constantly creating new stack 2507 // slots and always reusing the same one. We currently always create 2508 // new ones, as reuse may inhibit scheduling. 2509 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2510 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2511 Node->getValueType(0), dl); 2512 Results.push_back(Tmp1); 2513 break; 2514 } 2515 case ISD::SINT_TO_FP: 2516 case ISD::UINT_TO_FP: 2517 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2518 Node->getOperand(0), Node->getValueType(0), dl); 2519 Results.push_back(Tmp1); 2520 break; 2521 case ISD::FP_TO_UINT: { 2522 SDValue True, False; 2523 MVT VT = Node->getOperand(0).getValueType(); 2524 MVT NVT = Node->getValueType(0); 2525 const uint64_t zero[] = {0, 0}; 2526 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 2527 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2528 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2529 Tmp1 = DAG.getConstantFP(apf, VT); 2530 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2531 Node->getOperand(0), 2532 Tmp1, ISD::SETLT); 2533 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2534 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2535 DAG.getNode(ISD::FSUB, dl, VT, 2536 Node->getOperand(0), Tmp1)); 2537 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2538 DAG.getConstant(x, NVT)); 2539 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2540 Results.push_back(Tmp1); 2541 break; 2542 } 2543 case ISD::VAARG: { 2544 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2545 MVT VT = Node->getValueType(0); 2546 Tmp1 = Node->getOperand(0); 2547 Tmp2 = Node->getOperand(1); 2548 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0); 2549 // Increment the pointer, VAList, to the next vaarg 2550 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2551 DAG.getConstant(TLI.getTargetData()-> 2552 getTypeAllocSize(VT.getTypeForMVT()), 2553 TLI.getPointerTy())); 2554 // Store the incremented VAList to the legalized pointer 2555 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0); 2556 // Load the actual argument out of the pointer VAList 2557 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0)); 2558 Results.push_back(Results[0].getValue(1)); 2559 break; 2560 } 2561 case ISD::VACOPY: { 2562 // This defaults to loading a pointer from the input and storing it to the 2563 // output, returning the chain. 2564 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2565 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2566 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2567 Node->getOperand(2), VS, 0); 2568 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0); 2569 Results.push_back(Tmp1); 2570 break; 2571 } 2572 case ISD::EXTRACT_VECTOR_ELT: 2573 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2574 // This must be an access of the only element. Return it. 2575 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 2576 Node->getOperand(0)); 2577 else 2578 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2579 Results.push_back(Tmp1); 2580 break; 2581 case ISD::EXTRACT_SUBVECTOR: 2582 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2583 break; 2584 case ISD::CONCAT_VECTORS: { 2585 // Use extract/insert/build vector for now. We might try to be 2586 // more clever later. 2587 SmallVector<SDValue, 8> Ops; 2588 unsigned NumOperands = Node->getNumOperands(); 2589 for (unsigned i=0; i < NumOperands; ++i) { 2590 SDValue SubOp = Node->getOperand(i); 2591 MVT VVT = SubOp.getNode()->getValueType(0); 2592 MVT EltVT = VVT.getVectorElementType(); 2593 unsigned NumSubElem = VVT.getVectorNumElements(); 2594 for (unsigned j=0; j < NumSubElem; ++j) { 2595 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, 2596 DAG.getIntPtrConstant(j))); 2597 } 2598 } 2599 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), 2600 &Ops[0], Ops.size()); 2601 Results.push_back(Tmp1); 2602 break; 2603 } 2604 case ISD::SCALAR_TO_VECTOR: 2605 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2606 break; 2607 case ISD::INSERT_VECTOR_ELT: 2608 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2609 Node->getOperand(1), 2610 Node->getOperand(2), dl)); 2611 break; 2612 case ISD::VECTOR_SHUFFLE: { 2613 SmallVector<int, 8> Mask; 2614 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2615 2616 MVT VT = Node->getValueType(0); 2617 MVT EltVT = VT.getVectorElementType(); 2618 unsigned NumElems = VT.getVectorNumElements(); 2619 SmallVector<SDValue, 8> Ops; 2620 for (unsigned i = 0; i != NumElems; ++i) { 2621 if (Mask[i] < 0) { 2622 Ops.push_back(DAG.getUNDEF(EltVT)); 2623 continue; 2624 } 2625 unsigned Idx = Mask[i]; 2626 if (Idx < NumElems) 2627 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2628 Node->getOperand(0), 2629 DAG.getIntPtrConstant(Idx))); 2630 else 2631 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2632 Node->getOperand(1), 2633 DAG.getIntPtrConstant(Idx - NumElems))); 2634 } 2635 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2636 Results.push_back(Tmp1); 2637 break; 2638 } 2639 case ISD::EXTRACT_ELEMENT: { 2640 MVT OpTy = Node->getOperand(0).getValueType(); 2641 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2642 // 1 -> Hi 2643 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2644 DAG.getConstant(OpTy.getSizeInBits()/2, 2645 TLI.getShiftAmountTy())); 2646 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2647 } else { 2648 // 0 -> Lo 2649 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2650 Node->getOperand(0)); 2651 } 2652 Results.push_back(Tmp1); 2653 break; 2654 } 2655 case ISD::STACKSAVE: 2656 // Expand to CopyFromReg if the target set 2657 // StackPointerRegisterToSaveRestore. 2658 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2659 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2660 Node->getValueType(0))); 2661 Results.push_back(Results[0].getValue(1)); 2662 } else { 2663 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2664 Results.push_back(Node->getOperand(0)); 2665 } 2666 break; 2667 case ISD::STACKRESTORE: 2668 // Expand to CopyToReg if the target set 2669 // StackPointerRegisterToSaveRestore. 2670 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2671 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2672 Node->getOperand(1))); 2673 } else { 2674 Results.push_back(Node->getOperand(0)); 2675 } 2676 break; 2677 case ISD::FCOPYSIGN: 2678 Results.push_back(ExpandFCOPYSIGN(Node)); 2679 break; 2680 case ISD::FNEG: 2681 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2682 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2683 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2684 Node->getOperand(0)); 2685 Results.push_back(Tmp1); 2686 break; 2687 case ISD::FABS: { 2688 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2689 MVT VT = Node->getValueType(0); 2690 Tmp1 = Node->getOperand(0); 2691 Tmp2 = DAG.getConstantFP(0.0, VT); 2692 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2693 Tmp1, Tmp2, ISD::SETUGT); 2694 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2695 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2696 Results.push_back(Tmp1); 2697 break; 2698 } 2699 case ISD::FSQRT: 2700 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2701 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2702 break; 2703 case ISD::FSIN: 2704 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2705 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2706 break; 2707 case ISD::FCOS: 2708 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2709 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2710 break; 2711 case ISD::FLOG: 2712 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2713 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2714 break; 2715 case ISD::FLOG2: 2716 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2717 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2718 break; 2719 case ISD::FLOG10: 2720 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2721 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2722 break; 2723 case ISD::FEXP: 2724 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2725 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2726 break; 2727 case ISD::FEXP2: 2728 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2729 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2730 break; 2731 case ISD::FTRUNC: 2732 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2733 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2734 break; 2735 case ISD::FFLOOR: 2736 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2737 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2738 break; 2739 case ISD::FCEIL: 2740 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2741 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2742 break; 2743 case ISD::FRINT: 2744 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2745 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2746 break; 2747 case ISD::FNEARBYINT: 2748 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2749 RTLIB::NEARBYINT_F64, 2750 RTLIB::NEARBYINT_F80, 2751 RTLIB::NEARBYINT_PPCF128)); 2752 break; 2753 case ISD::FPOWI: 2754 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2755 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2756 break; 2757 case ISD::FPOW: 2758 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 2759 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 2760 break; 2761 case ISD::FDIV: 2762 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 2763 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 2764 break; 2765 case ISD::FREM: 2766 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 2767 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 2768 break; 2769 case ISD::ConstantFP: { 2770 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 2771 // Check to see if this FP immediate is already legal. 2772 bool isLegal = false; 2773 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 2774 E = TLI.legal_fpimm_end(); I != E; ++I) { 2775 if (CFP->isExactlyValue(*I)) { 2776 isLegal = true; 2777 break; 2778 } 2779 } 2780 // If this is a legal constant, turn it into a TargetConstantFP node. 2781 if (isLegal) 2782 Results.push_back(SDValue(Node, 0)); 2783 else 2784 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 2785 break; 2786 } 2787 case ISD::EHSELECTION: { 2788 unsigned Reg = TLI.getExceptionSelectorRegister(); 2789 assert(Reg && "Can't expand to unknown register!"); 2790 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 2791 Node->getValueType(0))); 2792 Results.push_back(Results[0].getValue(1)); 2793 break; 2794 } 2795 case ISD::EXCEPTIONADDR: { 2796 unsigned Reg = TLI.getExceptionAddressRegister(); 2797 assert(Reg && "Can't expand to unknown register!"); 2798 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 2799 Node->getValueType(0))); 2800 Results.push_back(Results[0].getValue(1)); 2801 break; 2802 } 2803 case ISD::SUB: { 2804 MVT VT = Node->getValueType(0); 2805 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 2806 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 2807 "Don't know how to expand this subtraction!"); 2808 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 2809 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 2810 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 2811 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 2812 break; 2813 } 2814 case ISD::UREM: 2815 case ISD::SREM: { 2816 MVT VT = Node->getValueType(0); 2817 SDVTList VTs = DAG.getVTList(VT, VT); 2818 bool isSigned = Node->getOpcode() == ISD::SREM; 2819 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 2820 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2821 Tmp2 = Node->getOperand(0); 2822 Tmp3 = Node->getOperand(1); 2823 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 2824 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 2825 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 2826 // X % Y -> X-X/Y*Y 2827 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 2828 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 2829 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 2830 } else if (isSigned) { 2831 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SREM_I16, RTLIB::SREM_I32, 2832 RTLIB::SREM_I64, RTLIB::SREM_I128); 2833 } else { 2834 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UREM_I16, RTLIB::UREM_I32, 2835 RTLIB::UREM_I64, RTLIB::UREM_I128); 2836 } 2837 Results.push_back(Tmp1); 2838 break; 2839 } 2840 case ISD::UDIV: 2841 case ISD::SDIV: { 2842 bool isSigned = Node->getOpcode() == ISD::SDIV; 2843 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2844 MVT VT = Node->getValueType(0); 2845 SDVTList VTs = DAG.getVTList(VT, VT); 2846 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 2847 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 2848 Node->getOperand(1)); 2849 else if (isSigned) 2850 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SDIV_I16, RTLIB::SDIV_I32, 2851 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 2852 else 2853 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UDIV_I16, RTLIB::UDIV_I32, 2854 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 2855 Results.push_back(Tmp1); 2856 break; 2857 } 2858 case ISD::MULHU: 2859 case ISD::MULHS: { 2860 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 2861 ISD::SMUL_LOHI; 2862 MVT VT = Node->getValueType(0); 2863 SDVTList VTs = DAG.getVTList(VT, VT); 2864 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 2865 "If this wasn't legal, it shouldn't have been created!"); 2866 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 2867 Node->getOperand(1)); 2868 Results.push_back(Tmp1.getValue(1)); 2869 break; 2870 } 2871 case ISD::MUL: { 2872 MVT VT = Node->getValueType(0); 2873 SDVTList VTs = DAG.getVTList(VT, VT); 2874 // See if multiply or divide can be lowered using two-result operations. 2875 // We just need the low half of the multiply; try both the signed 2876 // and unsigned forms. If the target supports both SMUL_LOHI and 2877 // UMUL_LOHI, form a preference by checking which forms of plain 2878 // MULH it supports. 2879 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 2880 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 2881 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 2882 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 2883 unsigned OpToUse = 0; 2884 if (HasSMUL_LOHI && !HasMULHS) { 2885 OpToUse = ISD::SMUL_LOHI; 2886 } else if (HasUMUL_LOHI && !HasMULHU) { 2887 OpToUse = ISD::UMUL_LOHI; 2888 } else if (HasSMUL_LOHI) { 2889 OpToUse = ISD::SMUL_LOHI; 2890 } else if (HasUMUL_LOHI) { 2891 OpToUse = ISD::UMUL_LOHI; 2892 } 2893 if (OpToUse) { 2894 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 2895 Node->getOperand(1))); 2896 break; 2897 } 2898 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::MUL_I16, RTLIB::MUL_I32, 2899 RTLIB::MUL_I64, RTLIB::MUL_I128); 2900 Results.push_back(Tmp1); 2901 break; 2902 } 2903 case ISD::SADDO: 2904 case ISD::SSUBO: { 2905 SDValue LHS = Node->getOperand(0); 2906 SDValue RHS = Node->getOperand(1); 2907 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 2908 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2909 LHS, RHS); 2910 Results.push_back(Sum); 2911 MVT OType = Node->getValueType(1); 2912 2913 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 2914 2915 // LHSSign -> LHS >= 0 2916 // RHSSign -> RHS >= 0 2917 // SumSign -> Sum >= 0 2918 // 2919 // Add: 2920 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 2921 // Sub: 2922 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 2923 // 2924 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 2925 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 2926 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 2927 Node->getOpcode() == ISD::SADDO ? 2928 ISD::SETEQ : ISD::SETNE); 2929 2930 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 2931 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 2932 2933 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 2934 Results.push_back(Cmp); 2935 break; 2936 } 2937 case ISD::UADDO: 2938 case ISD::USUBO: { 2939 SDValue LHS = Node->getOperand(0); 2940 SDValue RHS = Node->getOperand(1); 2941 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 2942 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2943 LHS, RHS); 2944 Results.push_back(Sum); 2945 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 2946 Node->getOpcode () == ISD::UADDO ? 2947 ISD::SETULT : ISD::SETUGT)); 2948 break; 2949 } 2950 case ISD::BUILD_PAIR: { 2951 MVT PairTy = Node->getValueType(0); 2952 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 2953 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 2954 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 2955 DAG.getConstant(PairTy.getSizeInBits()/2, 2956 TLI.getShiftAmountTy())); 2957 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 2958 break; 2959 } 2960 case ISD::SELECT: 2961 Tmp1 = Node->getOperand(0); 2962 Tmp2 = Node->getOperand(1); 2963 Tmp3 = Node->getOperand(2); 2964 if (Tmp1.getOpcode() == ISD::SETCC) { 2965 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 2966 Tmp2, Tmp3, 2967 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2968 } else { 2969 Tmp1 = DAG.getSelectCC(dl, Tmp1, 2970 DAG.getConstant(0, Tmp1.getValueType()), 2971 Tmp2, Tmp3, ISD::SETNE); 2972 } 2973 Results.push_back(Tmp1); 2974 break; 2975 case ISD::BR_JT: { 2976 SDValue Chain = Node->getOperand(0); 2977 SDValue Table = Node->getOperand(1); 2978 SDValue Index = Node->getOperand(2); 2979 2980 MVT PTy = TLI.getPointerTy(); 2981 MachineFunction &MF = DAG.getMachineFunction(); 2982 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 2983 Index= DAG.getNode(ISD::MUL, dl, PTy, 2984 Index, DAG.getConstant(EntrySize, PTy)); 2985 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2986 2987 MVT MemVT = MVT::getIntegerVT(EntrySize * 8); 2988 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 2989 PseudoSourceValue::getJumpTable(), 0, MemVT); 2990 Addr = LD; 2991 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2992 // For PIC, the sequence is: 2993 // BRIND(load(Jumptable + index) + RelocBase) 2994 // RelocBase can be JumpTable, GOT or some sort of global base. 2995 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 2996 TLI.getPICJumpTableRelocBase(Table, DAG)); 2997 } 2998 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 2999 Results.push_back(Tmp1); 3000 break; 3001 } 3002 case ISD::BRCOND: 3003 // Expand brcond's setcc into its constituent parts and create a BR_CC 3004 // Node. 3005 Tmp1 = Node->getOperand(0); 3006 Tmp2 = Node->getOperand(1); 3007 if (Tmp2.getOpcode() == ISD::SETCC) { 3008 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 3009 Tmp1, Tmp2.getOperand(2), 3010 Tmp2.getOperand(0), Tmp2.getOperand(1), 3011 Node->getOperand(2)); 3012 } else { 3013 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 3014 DAG.getCondCode(ISD::SETNE), Tmp2, 3015 DAG.getConstant(0, Tmp2.getValueType()), 3016 Node->getOperand(2)); 3017 } 3018 Results.push_back(Tmp1); 3019 break; 3020 case ISD::GLOBAL_OFFSET_TABLE: 3021 case ISD::GlobalAddress: 3022 case ISD::GlobalTLSAddress: 3023 case ISD::ExternalSymbol: 3024 case ISD::ConstantPool: 3025 case ISD::JumpTable: 3026 case ISD::INTRINSIC_W_CHAIN: 3027 case ISD::INTRINSIC_WO_CHAIN: 3028 case ISD::INTRINSIC_VOID: 3029 // FIXME: Custom lowering for these operations shouldn't return null! 3030 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3031 Results.push_back(SDValue(Node, i)); 3032 break; 3033 } 3034} 3035void SelectionDAGLegalize::PromoteNode(SDNode *Node, 3036 SmallVectorImpl<SDValue> &Results) { 3037 MVT OVT = Node->getValueType(0); 3038 if (Node->getOpcode() == ISD::UINT_TO_FP || 3039 Node->getOpcode() == ISD::SINT_TO_FP) { 3040 OVT = Node->getOperand(0).getValueType(); 3041 } 3042 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3043 DebugLoc dl = Node->getDebugLoc(); 3044 SDValue Tmp1, Tmp2, Tmp3; 3045 switch (Node->getOpcode()) { 3046 case ISD::CTTZ: 3047 case ISD::CTLZ: 3048 case ISD::CTPOP: 3049 // Zero extend the argument. 3050 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3051 // Perform the larger operation. 3052 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1); 3053 if (Node->getOpcode() == ISD::CTTZ) { 3054 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3055 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 3056 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3057 ISD::SETEQ); 3058 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3059 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3060 } else if (Node->getOpcode() == ISD::CTLZ) { 3061 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3062 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3063 DAG.getConstant(NVT.getSizeInBits() - 3064 OVT.getSizeInBits(), NVT)); 3065 } 3066 Results.push_back(Tmp1); 3067 break; 3068 case ISD::BSWAP: { 3069 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3070 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); 3071 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3072 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3073 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3074 Results.push_back(Tmp1); 3075 break; 3076 } 3077 case ISD::FP_TO_UINT: 3078 case ISD::FP_TO_SINT: 3079 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3080 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3081 Results.push_back(Tmp1); 3082 break; 3083 case ISD::UINT_TO_FP: 3084 case ISD::SINT_TO_FP: 3085 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3086 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3087 Results.push_back(Tmp1); 3088 break; 3089 case ISD::AND: 3090 case ISD::OR: 3091 case ISD::XOR: 3092 assert(OVT.isVector() && "Don't know how to promote scalar logic ops"); 3093 // Bit convert each of the values to the new type. 3094 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3095 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3096 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3097 // Bit convert the result back the original type. 3098 Results.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1)); 3099 break; 3100 case ISD::SELECT: 3101 unsigned ExtOp, TruncOp; 3102 if (Node->getValueType(0).isVector()) { 3103 ExtOp = ISD::BIT_CONVERT; 3104 TruncOp = ISD::BIT_CONVERT; 3105 } else if (Node->getValueType(0).isInteger()) { 3106 ExtOp = ISD::ANY_EXTEND; 3107 TruncOp = ISD::TRUNCATE; 3108 } else { 3109 ExtOp = ISD::FP_EXTEND; 3110 TruncOp = ISD::FP_ROUND; 3111 } 3112 Tmp1 = Node->getOperand(0); 3113 // Promote each of the values to the new type. 3114 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3115 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3116 // Perform the larger operation, then round down. 3117 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3118 if (TruncOp != ISD::FP_ROUND) 3119 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3120 else 3121 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3122 DAG.getIntPtrConstant(0)); 3123 Results.push_back(Tmp1); 3124 break; 3125 case ISD::VECTOR_SHUFFLE: { 3126 SmallVector<int, 8> Mask; 3127 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3128 3129 // Cast the two input vectors. 3130 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3131 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3132 3133 // Convert the shuffle mask to the right # elements. 3134 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3135 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); 3136 Results.push_back(Tmp1); 3137 break; 3138 } 3139 } 3140} 3141 3142// SelectionDAG::Legalize - This is the entry point for the file. 3143// 3144void SelectionDAG::Legalize(bool TypesNeedLegalizing, 3145 CodeGenOpt::Level OptLevel) { 3146 /// run - This is the main entry point to this class. 3147 /// 3148 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3149} 3150 3151