LegalizeDAG.cpp revision 3d6ccfba314ed38e4506dae2781a060e9a3e07ac
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/Analysis/DebugInfo.h" 20#include "llvm/CodeGen/PseudoSourceValue.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetOptions.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Function.h" 30#include "llvm/GlobalVariable.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/ADT/DenseMap.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/ADT/SmallPtrSet.h" 40using namespace llvm; 41 42//===----------------------------------------------------------------------===// 43/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 44/// hacks on it until the target machine can handle it. This involves 45/// eliminating value sizes the machine cannot handle (promoting small sizes to 46/// large sizes or splitting up large values into small values) as well as 47/// eliminating operations the machine cannot handle. 48/// 49/// This code also does a small amount of optimization and recognition of idioms 50/// as part of its processing. For example, if a target does not support a 51/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 52/// will attempt merge setcc and brc instructions into brcc's. 53/// 54namespace { 55class SelectionDAGLegalize { 56 const TargetMachine &TM; 57 const TargetLowering &TLI; 58 SelectionDAG &DAG; 59 CodeGenOpt::Level OptLevel; 60 61 // Libcall insertion helpers. 62 63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 64 /// legalized. We use this to ensure that calls are properly serialized 65 /// against each other, including inserted libcalls. 66 SDValue LastCALLSEQ_END; 67 68 /// IsLegalizingCall - This member is used *only* for purposes of providing 69 /// helpful assertions that a libcall isn't created while another call is 70 /// being legalized (which could lead to non-serialized call sequences). 71 bool IsLegalizingCall; 72 73 enum LegalizeAction { 74 Legal, // The target natively supports this operation. 75 Promote, // This operation should be executed in a larger type. 76 Expand // Try to expand this to other ops, otherwise use a libcall. 77 }; 78 79 /// ValueTypeActions - This is a bitvector that contains two bits for each 80 /// value type, where the two bits correspond to the LegalizeAction enum. 81 /// This can be queried with "getTypeAction(VT)". 82 TargetLowering::ValueTypeActionImpl ValueTypeActions; 83 84 /// LegalizedNodes - For nodes that are of legal width, and that have more 85 /// than one use, this map indicates what regularized operand to use. This 86 /// allows us to avoid legalizing the same thing more than once. 87 DenseMap<SDValue, SDValue> LegalizedNodes; 88 89 void AddLegalizedOperand(SDValue From, SDValue To) { 90 LegalizedNodes.insert(std::make_pair(From, To)); 91 // If someone requests legalization of the new node, return itself. 92 if (From != To) 93 LegalizedNodes.insert(std::make_pair(To, To)); 94 } 95 96public: 97 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 98 99 /// getTypeAction - Return how we should legalize values of this type, either 100 /// it is already legal or we need to expand it into multiple registers of 101 /// smaller integer type, or we need to promote it to a larger type. 102 LegalizeAction getTypeAction(EVT VT) const { 103 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 104 } 105 106 /// isTypeLegal - Return true if this type is legal on this target. 107 /// 108 bool isTypeLegal(EVT VT) const { 109 return getTypeAction(VT) == Legal; 110 } 111 112 void LegalizeDAG(); 113 114private: 115 /// LegalizeOp - We know that the specified value has a legal type. 116 /// Recursively ensure that the operands have legal types, then return the 117 /// result. 118 SDValue LegalizeOp(SDValue O); 119 120 SDValue OptimizeFloatStore(StoreSDNode *ST); 121 122 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 123 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 124 /// is necessary to spill the vector being inserted into to memory, perform 125 /// the insert there, and then read the result back. 126 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 127 SDValue Idx, DebugLoc dl); 128 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 129 SDValue Idx, DebugLoc dl); 130 131 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 132 /// performs the same shuffe in terms of order or result bytes, but on a type 133 /// whose vector element type is narrower than the original shuffle type. 134 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 135 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 136 SDValue N1, SDValue N2, 137 SmallVectorImpl<int> &Mask) const; 138 139 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 140 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 141 142 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 143 DebugLoc dl); 144 145 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 146 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC, 147 SDNode *Node, bool isSigned); 148 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 149 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 150 RTLIB::Libcall Call_PPCF128); 151 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 152 RTLIB::Libcall Call_I8, 153 RTLIB::Libcall Call_I16, 154 RTLIB::Libcall Call_I32, 155 RTLIB::Libcall Call_I64, 156 RTLIB::Libcall Call_I128); 157 158 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 159 SDValue ExpandBUILD_VECTOR(SDNode *Node); 160 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 161 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 162 SmallVectorImpl<SDValue> &Results); 163 SDValue ExpandFCOPYSIGN(SDNode *Node); 164 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 165 DebugLoc dl); 166 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 167 DebugLoc dl); 168 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 169 DebugLoc dl); 170 171 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 172 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 173 174 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 175 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 176 177 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node); 178 179 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 180 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 181}; 182} 183 184/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 185/// performs the same shuffe in terms of order or result bytes, but on a type 186/// whose vector element type is narrower than the original shuffle type. 187/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 188SDValue 189SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 190 SDValue N1, SDValue N2, 191 SmallVectorImpl<int> &Mask) const { 192 unsigned NumMaskElts = VT.getVectorNumElements(); 193 unsigned NumDestElts = NVT.getVectorNumElements(); 194 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 195 196 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 197 198 if (NumEltsGrowth == 1) 199 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 200 201 SmallVector<int, 8> NewMask; 202 for (unsigned i = 0; i != NumMaskElts; ++i) { 203 int Idx = Mask[i]; 204 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 205 if (Idx < 0) 206 NewMask.push_back(-1); 207 else 208 NewMask.push_back(Idx * NumEltsGrowth + j); 209 } 210 } 211 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 212 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 213 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 214} 215 216SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 217 CodeGenOpt::Level ol) 218 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 219 DAG(dag), OptLevel(ol), 220 ValueTypeActions(TLI.getValueTypeActions()) { 221 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 222 "Too many value types for ValueTypeActions to hold!"); 223} 224 225void SelectionDAGLegalize::LegalizeDAG() { 226 LastCALLSEQ_END = DAG.getEntryNode(); 227 IsLegalizingCall = false; 228 229 // The legalize process is inherently a bottom-up recursive process (users 230 // legalize their uses before themselves). Given infinite stack space, we 231 // could just start legalizing on the root and traverse the whole graph. In 232 // practice however, this causes us to run out of stack space on large basic 233 // blocks. To avoid this problem, compute an ordering of the nodes where each 234 // node is only legalized after all of its operands are legalized. 235 DAG.AssignTopologicalOrder(); 236 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 237 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 238 LegalizeOp(SDValue(I, 0)); 239 240 // Finally, it's possible the root changed. Get the new root. 241 SDValue OldRoot = DAG.getRoot(); 242 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 243 DAG.setRoot(LegalizedNodes[OldRoot]); 244 245 LegalizedNodes.clear(); 246 247 // Remove dead nodes now. 248 DAG.RemoveDeadNodes(); 249} 250 251 252/// FindCallEndFromCallStart - Given a chained node that is part of a call 253/// sequence, find the CALLSEQ_END node that terminates the call sequence. 254static SDNode *FindCallEndFromCallStart(SDNode *Node) { 255 if (Node->getOpcode() == ISD::CALLSEQ_END) 256 return Node; 257 if (Node->use_empty()) 258 return 0; // No CallSeqEnd 259 260 // The chain is usually at the end. 261 SDValue TheChain(Node, Node->getNumValues()-1); 262 if (TheChain.getValueType() != MVT::Other) { 263 // Sometimes it's at the beginning. 264 TheChain = SDValue(Node, 0); 265 if (TheChain.getValueType() != MVT::Other) { 266 // Otherwise, hunt for it. 267 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 268 if (Node->getValueType(i) == MVT::Other) { 269 TheChain = SDValue(Node, i); 270 break; 271 } 272 273 // Otherwise, we walked into a node without a chain. 274 if (TheChain.getValueType() != MVT::Other) 275 return 0; 276 } 277 } 278 279 for (SDNode::use_iterator UI = Node->use_begin(), 280 E = Node->use_end(); UI != E; ++UI) { 281 282 // Make sure to only follow users of our token chain. 283 SDNode *User = *UI; 284 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 285 if (User->getOperand(i) == TheChain) 286 if (SDNode *Result = FindCallEndFromCallStart(User)) 287 return Result; 288 } 289 return 0; 290} 291 292/// FindCallStartFromCallEnd - Given a chained node that is part of a call 293/// sequence, find the CALLSEQ_START node that initiates the call sequence. 294static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 295 assert(Node && "Didn't find callseq_start for a call??"); 296 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 297 298 assert(Node->getOperand(0).getValueType() == MVT::Other && 299 "Node doesn't have a token chain argument!"); 300 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 301} 302 303/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 304/// see if any uses can reach Dest. If no dest operands can get to dest, 305/// legalize them, legalize ourself, and return false, otherwise, return true. 306/// 307/// Keep track of the nodes we fine that actually do lead to Dest in 308/// NodesLeadingTo. This avoids retraversing them exponential number of times. 309/// 310bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 311 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 312 if (N == Dest) return true; // N certainly leads to Dest :) 313 314 // If we've already processed this node and it does lead to Dest, there is no 315 // need to reprocess it. 316 if (NodesLeadingTo.count(N)) return true; 317 318 // If the first result of this node has been already legalized, then it cannot 319 // reach N. 320 if (LegalizedNodes.count(SDValue(N, 0))) return false; 321 322 // Okay, this node has not already been legalized. Check and legalize all 323 // operands. If none lead to Dest, then we can legalize this node. 324 bool OperandsLeadToDest = false; 325 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 326 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 327 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, 328 NodesLeadingTo); 329 330 if (OperandsLeadToDest) { 331 NodesLeadingTo.insert(N); 332 return true; 333 } 334 335 // Okay, this node looks safe, legalize it and return false. 336 LegalizeOp(SDValue(N, 0)); 337 return false; 338} 339 340/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 341/// a load from the constant pool. 342static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 343 SelectionDAG &DAG, const TargetLowering &TLI) { 344 bool Extend = false; 345 DebugLoc dl = CFP->getDebugLoc(); 346 347 // If a FP immediate is precise when represented as a float and if the 348 // target can do an extending load from float to double, we put it into 349 // the constant pool as a float, even if it's is statically typed as a 350 // double. This shrinks FP constants and canonicalizes them for targets where 351 // an FP extending load is the same cost as a normal load (such as on the x87 352 // fp stack or PPC FP unit). 353 EVT VT = CFP->getValueType(0); 354 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 355 if (!UseCP) { 356 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 357 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 358 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 359 } 360 361 EVT OrigVT = VT; 362 EVT SVT = VT; 363 while (SVT != MVT::f32) { 364 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 365 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) && 366 // Only do this if the target has a native EXTLOAD instruction from 367 // smaller type. 368 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 369 TLI.ShouldShrinkFPConstant(OrigVT)) { 370 const Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 371 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 372 VT = SVT; 373 Extend = true; 374 } 375 } 376 377 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 378 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 379 if (Extend) 380 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, dl, 381 DAG.getEntryNode(), 382 CPIdx, MachinePointerInfo::getConstantPool(), 383 VT, false, false, Alignment); 384 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 385 MachinePointerInfo::getConstantPool(), false, false, 386 Alignment); 387} 388 389/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 390static 391SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 392 const TargetLowering &TLI) { 393 SDValue Chain = ST->getChain(); 394 SDValue Ptr = ST->getBasePtr(); 395 SDValue Val = ST->getValue(); 396 EVT VT = Val.getValueType(); 397 int Alignment = ST->getAlignment(); 398 int SVOffset = ST->getSrcValueOffset(); 399 DebugLoc dl = ST->getDebugLoc(); 400 if (ST->getMemoryVT().isFloatingPoint() || 401 ST->getMemoryVT().isVector()) { 402 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 403 if (TLI.isTypeLegal(intVT)) { 404 // Expand to a bitconvert of the value to the integer type of the 405 // same size, then a (misaligned) int store. 406 // FIXME: Does not handle truncating floating point stores! 407 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 408 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 409 SVOffset, ST->isVolatile(), ST->isNonTemporal(), 410 Alignment); 411 } else { 412 // Do a (aligned) store to a stack slot, then copy from the stack slot 413 // to the final destination using (unaligned) integer loads and stores. 414 EVT StoredVT = ST->getMemoryVT(); 415 EVT RegVT = 416 TLI.getRegisterType(*DAG.getContext(), 417 EVT::getIntegerVT(*DAG.getContext(), 418 StoredVT.getSizeInBits())); 419 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 420 unsigned RegBytes = RegVT.getSizeInBits() / 8; 421 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 422 423 // Make sure the stack slot is also aligned for the register type. 424 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 425 426 // Perform the original store, only redirected to the stack slot. 427 SDValue Store = DAG.getTruncStore(Chain, dl, 428 Val, StackPtr, MachinePointerInfo(), 429 StoredVT, false, false, 0); 430 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 431 SmallVector<SDValue, 8> Stores; 432 unsigned Offset = 0; 433 434 // Do all but one copies using the full register width. 435 for (unsigned i = 1; i < NumRegs; i++) { 436 // Load one integer register's worth from the stack slot. 437 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, 438 MachinePointerInfo(), 439 false, false, 0); 440 // Store it to the final location. Remember the store. 441 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 442 ST->getPointerInfo().getWithOffset(Offset), 443 ST->isVolatile(), ST->isNonTemporal(), 444 MinAlign(ST->getAlignment(), Offset))); 445 // Increment the pointers. 446 Offset += RegBytes; 447 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 448 Increment); 449 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 450 } 451 452 // The last store may be partial. Do a truncating store. On big-endian 453 // machines this requires an extending load from the stack slot to ensure 454 // that the bits are in the right place. 455 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 456 8 * (StoredBytes - Offset)); 457 458 // Load from the stack slot. 459 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Store, StackPtr, 460 MachinePointerInfo(), 461 MemVT, false, false, 0); 462 463 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 464 ST->getPointerInfo() 465 .getWithOffset(Offset), 466 MemVT, ST->isVolatile(), 467 ST->isNonTemporal(), 468 MinAlign(ST->getAlignment(), Offset))); 469 // The order of the stores doesn't matter - say it with a TokenFactor. 470 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 471 Stores.size()); 472 } 473 } 474 assert(ST->getMemoryVT().isInteger() && 475 !ST->getMemoryVT().isVector() && 476 "Unaligned store of unknown type."); 477 // Get the half-size VT 478 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 479 int NumBits = NewStoredVT.getSizeInBits(); 480 int IncrementSize = NumBits / 8; 481 482 // Divide the stored value in two parts. 483 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 484 SDValue Lo = Val; 485 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 486 487 // Store the two parts 488 SDValue Store1, Store2; 489 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 490 ST->getSrcValue(), SVOffset, NewStoredVT, 491 ST->isVolatile(), ST->isNonTemporal(), Alignment); 492 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 493 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 494 Alignment = MinAlign(Alignment, IncrementSize); 495 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 496 ST->getSrcValue(), SVOffset + IncrementSize, 497 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 498 Alignment); 499 500 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 501} 502 503/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 504static 505SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 506 const TargetLowering &TLI) { 507 SDValue Chain = LD->getChain(); 508 SDValue Ptr = LD->getBasePtr(); 509 EVT VT = LD->getValueType(0); 510 EVT LoadedVT = LD->getMemoryVT(); 511 DebugLoc dl = LD->getDebugLoc(); 512 if (VT.isFloatingPoint() || VT.isVector()) { 513 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 514 if (TLI.isTypeLegal(intVT)) { 515 // Expand to a (misaligned) integer load of the same size, 516 // then bitconvert to floating point or vector. 517 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(), 518 LD->isVolatile(), 519 LD->isNonTemporal(), LD->getAlignment()); 520 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 521 if (VT.isFloatingPoint() && LoadedVT != VT) 522 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 523 524 SDValue Ops[] = { Result, Chain }; 525 return DAG.getMergeValues(Ops, 2, dl); 526 } 527 528 // Copy the value to a (aligned) stack slot using (unaligned) integer 529 // loads and stores, then do a (aligned) load from the stack slot. 530 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 531 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 532 unsigned RegBytes = RegVT.getSizeInBits() / 8; 533 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 534 535 // Make sure the stack slot is also aligned for the register type. 536 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 537 538 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 539 SmallVector<SDValue, 8> Stores; 540 SDValue StackPtr = StackBase; 541 unsigned Offset = 0; 542 543 // Do all but one copies using the full register width. 544 for (unsigned i = 1; i < NumRegs; i++) { 545 // Load one integer register's worth from the original location. 546 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, 547 LD->getPointerInfo().getWithOffset(Offset), 548 LD->isVolatile(), LD->isNonTemporal(), 549 MinAlign(LD->getAlignment(), Offset)); 550 // Follow the load with a store to the stack slot. Remember the store. 551 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 552 NULL, 0, false, false, 0)); 553 // Increment the pointers. 554 Offset += RegBytes; 555 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 556 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 557 Increment); 558 } 559 560 // The last copy may be partial. Do an extending load. 561 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 562 8 * (LoadedBytes - Offset)); 563 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Chain, Ptr, 564 LD->getPointerInfo().getWithOffset(Offset), 565 MemVT, LD->isVolatile(), 566 LD->isNonTemporal(), 567 MinAlign(LD->getAlignment(), Offset)); 568 // Follow the load with a store to the stack slot. Remember the store. 569 // On big-endian machines this requires a truncating store to ensure 570 // that the bits end up in the right place. 571 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 572 MachinePointerInfo(), MemVT, 573 false, false, 0)); 574 575 // The order of the stores doesn't matter - say it with a TokenFactor. 576 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 577 Stores.size()); 578 579 // Finally, perform the original load only redirected to the stack slot. 580 Load = DAG.getExtLoad(LD->getExtensionType(), VT, dl, TF, StackBase, 581 MachinePointerInfo(), LoadedVT, false, false, 0); 582 583 // Callers expect a MERGE_VALUES node. 584 SDValue Ops[] = { Load, TF }; 585 return DAG.getMergeValues(Ops, 2, dl); 586 } 587 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 588 "Unaligned load of unsupported type."); 589 590 // Compute the new VT that is half the size of the old one. This is an 591 // integer MVT. 592 unsigned NumBits = LoadedVT.getSizeInBits(); 593 EVT NewLoadedVT; 594 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 595 NumBits >>= 1; 596 597 unsigned Alignment = LD->getAlignment(); 598 unsigned IncrementSize = NumBits / 8; 599 ISD::LoadExtType HiExtType = LD->getExtensionType(); 600 601 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 602 if (HiExtType == ISD::NON_EXTLOAD) 603 HiExtType = ISD::ZEXTLOAD; 604 605 // Load the value in two parts 606 SDValue Lo, Hi; 607 if (TLI.isLittleEndian()) { 608 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getPointerInfo(), 609 NewLoadedVT, LD->isVolatile(), 610 LD->isNonTemporal(), Alignment); 611 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 612 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 613 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, 614 LD->getPointerInfo().getWithOffset(IncrementSize), 615 NewLoadedVT, LD->isVolatile(), 616 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 617 } else { 618 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getPointerInfo(), 619 NewLoadedVT, LD->isVolatile(), 620 LD->isNonTemporal(), Alignment); 621 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 622 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 623 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, 624 LD->getPointerInfo().getWithOffset(IncrementSize), 625 NewLoadedVT, LD->isVolatile(), 626 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 627 } 628 629 // aggregate the two parts 630 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 631 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 632 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 633 634 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 635 Hi.getValue(1)); 636 637 SDValue Ops[] = { Result, TF }; 638 return DAG.getMergeValues(Ops, 2, dl); 639} 640 641/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 642/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 643/// is necessary to spill the vector being inserted into to memory, perform 644/// the insert there, and then read the result back. 645SDValue SelectionDAGLegalize:: 646PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 647 DebugLoc dl) { 648 SDValue Tmp1 = Vec; 649 SDValue Tmp2 = Val; 650 SDValue Tmp3 = Idx; 651 652 // If the target doesn't support this, we have to spill the input vector 653 // to a temporary stack slot, update the element, then reload it. This is 654 // badness. We could also load the value into a vector register (either 655 // with a "move to register" or "extload into register" instruction, then 656 // permute it into place, if the idx is a constant and if the idx is 657 // supported by the target. 658 EVT VT = Tmp1.getValueType(); 659 EVT EltVT = VT.getVectorElementType(); 660 EVT IdxVT = Tmp3.getValueType(); 661 EVT PtrVT = TLI.getPointerTy(); 662 SDValue StackPtr = DAG.CreateStackTemporary(VT); 663 664 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 665 666 // Store the vector. 667 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 668 MachinePointerInfo::getFixedStack(SPFI), 669 false, false, 0); 670 671 // Truncate or zero extend offset to target pointer type. 672 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 673 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 674 // Add the offset to the index. 675 unsigned EltSize = EltVT.getSizeInBits()/8; 676 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 677 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 678 // Store the scalar value. 679 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT, 680 false, false, 0); 681 // Load the updated vector. 682 return DAG.getLoad(VT, dl, Ch, StackPtr, 683 MachinePointerInfo::getFixedStack(SPFI), false, false, 0); 684} 685 686 687SDValue SelectionDAGLegalize:: 688ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 689 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 690 // SCALAR_TO_VECTOR requires that the type of the value being inserted 691 // match the element type of the vector being created, except for 692 // integers in which case the inserted value can be over width. 693 EVT EltVT = Vec.getValueType().getVectorElementType(); 694 if (Val.getValueType() == EltVT || 695 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 696 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 697 Vec.getValueType(), Val); 698 699 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 700 // We generate a shuffle of InVec and ScVec, so the shuffle mask 701 // should be 0,1,2,3,4,5... with the appropriate element replaced with 702 // elt 0 of the RHS. 703 SmallVector<int, 8> ShufOps; 704 for (unsigned i = 0; i != NumElts; ++i) 705 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 706 707 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 708 &ShufOps[0]); 709 } 710 } 711 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 712} 713 714SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 715 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 716 // FIXME: We shouldn't do this for TargetConstantFP's. 717 // FIXME: move this to the DAG Combiner! Note that we can't regress due 718 // to phase ordering between legalized code and the dag combiner. This 719 // probably means that we need to integrate dag combiner and legalizer 720 // together. 721 // We generally can't do this one for long doubles. 722 SDValue Tmp1 = ST->getChain(); 723 SDValue Tmp2 = ST->getBasePtr(); 724 SDValue Tmp3; 725 int SVOffset = ST->getSrcValueOffset(); 726 unsigned Alignment = ST->getAlignment(); 727 bool isVolatile = ST->isVolatile(); 728 bool isNonTemporal = ST->isNonTemporal(); 729 DebugLoc dl = ST->getDebugLoc(); 730 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 731 if (CFP->getValueType(0) == MVT::f32 && 732 getTypeAction(MVT::i32) == Legal) { 733 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 734 bitcastToAPInt().zextOrTrunc(32), 735 MVT::i32); 736 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 737 SVOffset, isVolatile, isNonTemporal, Alignment); 738 } else if (CFP->getValueType(0) == MVT::f64) { 739 // If this target supports 64-bit registers, do a single 64-bit store. 740 if (getTypeAction(MVT::i64) == Legal) { 741 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 742 zextOrTrunc(64), MVT::i64); 743 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 744 SVOffset, isVolatile, isNonTemporal, Alignment); 745 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 746 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 747 // stores. If the target supports neither 32- nor 64-bits, this 748 // xform is certainly not worth it. 749 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 750 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 751 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 752 if (TLI.isBigEndian()) std::swap(Lo, Hi); 753 754 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 755 SVOffset, isVolatile, isNonTemporal, Alignment); 756 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 757 DAG.getIntPtrConstant(4)); 758 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 759 isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); 760 761 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 762 } 763 } 764 } 765 return SDValue(); 766} 767 768/// LegalizeOp - We know that the specified value has a legal type, and 769/// that its operands are legal. Now ensure that the operation itself 770/// is legal, recursively ensuring that the operands' operations remain 771/// legal. 772SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 773 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 774 return Op; 775 776 SDNode *Node = Op.getNode(); 777 DebugLoc dl = Node->getDebugLoc(); 778 779 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 780 assert(getTypeAction(Node->getValueType(i)) == Legal && 781 "Unexpected illegal type!"); 782 783 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 784 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 785 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 786 "Unexpected illegal type!"); 787 788 // Note that LegalizeOp may be reentered even from single-use nodes, which 789 // means that we always must cache transformed nodes. 790 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 791 if (I != LegalizedNodes.end()) return I->second; 792 793 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 794 SDValue Result = Op; 795 bool isCustom = false; 796 797 // Figure out the correct action; the way to query this varies by opcode 798 TargetLowering::LegalizeAction Action; 799 bool SimpleFinishLegalizing = true; 800 switch (Node->getOpcode()) { 801 case ISD::INTRINSIC_W_CHAIN: 802 case ISD::INTRINSIC_WO_CHAIN: 803 case ISD::INTRINSIC_VOID: 804 case ISD::VAARG: 805 case ISD::STACKSAVE: 806 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 807 break; 808 case ISD::SINT_TO_FP: 809 case ISD::UINT_TO_FP: 810 case ISD::EXTRACT_VECTOR_ELT: 811 Action = TLI.getOperationAction(Node->getOpcode(), 812 Node->getOperand(0).getValueType()); 813 break; 814 case ISD::FP_ROUND_INREG: 815 case ISD::SIGN_EXTEND_INREG: { 816 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 817 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 818 break; 819 } 820 case ISD::SELECT_CC: 821 case ISD::SETCC: 822 case ISD::BR_CC: { 823 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 824 Node->getOpcode() == ISD::SETCC ? 2 : 1; 825 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 826 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 827 ISD::CondCode CCCode = 828 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 829 Action = TLI.getCondCodeAction(CCCode, OpVT); 830 if (Action == TargetLowering::Legal) { 831 if (Node->getOpcode() == ISD::SELECT_CC) 832 Action = TLI.getOperationAction(Node->getOpcode(), 833 Node->getValueType(0)); 834 else 835 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 836 } 837 break; 838 } 839 case ISD::LOAD: 840 case ISD::STORE: 841 // FIXME: Model these properly. LOAD and STORE are complicated, and 842 // STORE expects the unlegalized operand in some cases. 843 SimpleFinishLegalizing = false; 844 break; 845 case ISD::CALLSEQ_START: 846 case ISD::CALLSEQ_END: 847 // FIXME: This shouldn't be necessary. These nodes have special properties 848 // dealing with the recursive nature of legalization. Removing this 849 // special case should be done as part of making LegalizeDAG non-recursive. 850 SimpleFinishLegalizing = false; 851 break; 852 case ISD::EXTRACT_ELEMENT: 853 case ISD::FLT_ROUNDS_: 854 case ISD::SADDO: 855 case ISD::SSUBO: 856 case ISD::UADDO: 857 case ISD::USUBO: 858 case ISD::SMULO: 859 case ISD::UMULO: 860 case ISD::FPOWI: 861 case ISD::MERGE_VALUES: 862 case ISD::EH_RETURN: 863 case ISD::FRAME_TO_ARGS_OFFSET: 864 case ISD::EH_SJLJ_SETJMP: 865 case ISD::EH_SJLJ_LONGJMP: 866 // These operations lie about being legal: when they claim to be legal, 867 // they should actually be expanded. 868 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 869 if (Action == TargetLowering::Legal) 870 Action = TargetLowering::Expand; 871 break; 872 case ISD::TRAMPOLINE: 873 case ISD::FRAMEADDR: 874 case ISD::RETURNADDR: 875 // These operations lie about being legal: when they claim to be legal, 876 // they should actually be custom-lowered. 877 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 878 if (Action == TargetLowering::Legal) 879 Action = TargetLowering::Custom; 880 break; 881 case ISD::BUILD_VECTOR: 882 // A weird case: legalization for BUILD_VECTOR never legalizes the 883 // operands! 884 // FIXME: This really sucks... changing it isn't semantically incorrect, 885 // but it massively pessimizes the code for floating-point BUILD_VECTORs 886 // because ConstantFP operands get legalized into constant pool loads 887 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 888 // though, because BUILD_VECTORS usually get lowered into other nodes 889 // which get legalized properly. 890 SimpleFinishLegalizing = false; 891 break; 892 default: 893 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 894 Action = TargetLowering::Legal; 895 } else { 896 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 897 } 898 break; 899 } 900 901 if (SimpleFinishLegalizing) { 902 SmallVector<SDValue, 8> Ops, ResultVals; 903 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 904 Ops.push_back(LegalizeOp(Node->getOperand(i))); 905 switch (Node->getOpcode()) { 906 default: break; 907 case ISD::BR: 908 case ISD::BRIND: 909 case ISD::BR_JT: 910 case ISD::BR_CC: 911 case ISD::BRCOND: 912 // Branches tweak the chain to include LastCALLSEQ_END 913 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 914 LastCALLSEQ_END); 915 Ops[0] = LegalizeOp(Ops[0]); 916 LastCALLSEQ_END = DAG.getEntryNode(); 917 break; 918 case ISD::SHL: 919 case ISD::SRL: 920 case ISD::SRA: 921 case ISD::ROTL: 922 case ISD::ROTR: 923 // Legalizing shifts/rotates requires adjusting the shift amount 924 // to the appropriate width. 925 if (!Ops[1].getValueType().isVector()) 926 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 927 break; 928 case ISD::SRL_PARTS: 929 case ISD::SRA_PARTS: 930 case ISD::SHL_PARTS: 931 // Legalizing shifts/rotates requires adjusting the shift amount 932 // to the appropriate width. 933 if (!Ops[2].getValueType().isVector()) 934 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2])); 935 break; 936 } 937 938 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(), 939 Ops.size()), 0); 940 switch (Action) { 941 case TargetLowering::Legal: 942 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 943 ResultVals.push_back(Result.getValue(i)); 944 break; 945 case TargetLowering::Custom: 946 // FIXME: The handling for custom lowering with multiple results is 947 // a complete mess. 948 Tmp1 = TLI.LowerOperation(Result, DAG); 949 if (Tmp1.getNode()) { 950 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 951 if (e == 1) 952 ResultVals.push_back(Tmp1); 953 else 954 ResultVals.push_back(Tmp1.getValue(i)); 955 } 956 break; 957 } 958 959 // FALL THROUGH 960 case TargetLowering::Expand: 961 ExpandNode(Result.getNode(), ResultVals); 962 break; 963 case TargetLowering::Promote: 964 PromoteNode(Result.getNode(), ResultVals); 965 break; 966 } 967 if (!ResultVals.empty()) { 968 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 969 if (ResultVals[i] != SDValue(Node, i)) 970 ResultVals[i] = LegalizeOp(ResultVals[i]); 971 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 972 } 973 return ResultVals[Op.getResNo()]; 974 } 975 } 976 977 switch (Node->getOpcode()) { 978 default: 979#ifndef NDEBUG 980 dbgs() << "NODE: "; 981 Node->dump( &DAG); 982 dbgs() << "\n"; 983#endif 984 assert(0 && "Do not know how to legalize this operator!"); 985 986 case ISD::BUILD_VECTOR: 987 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 988 default: assert(0 && "This action is not supported yet!"); 989 case TargetLowering::Custom: 990 Tmp3 = TLI.LowerOperation(Result, DAG); 991 if (Tmp3.getNode()) { 992 Result = Tmp3; 993 break; 994 } 995 // FALLTHROUGH 996 case TargetLowering::Expand: 997 Result = ExpandBUILD_VECTOR(Result.getNode()); 998 break; 999 } 1000 break; 1001 case ISD::CALLSEQ_START: { 1002 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1003 1004 // Recursively Legalize all of the inputs of the call end that do not lead 1005 // to this call start. This ensures that any libcalls that need be inserted 1006 // are inserted *before* the CALLSEQ_START. 1007 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1008 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1009 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1010 NodesLeadingTo); 1011 } 1012 1013 // Now that we have legalized all of the inputs (which may have inserted 1014 // libcalls), create the new CALLSEQ_START node. 1015 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1016 1017 // Merge in the last call to ensure that this call starts after the last 1018 // call ended. 1019 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1020 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1021 Tmp1, LastCALLSEQ_END); 1022 Tmp1 = LegalizeOp(Tmp1); 1023 } 1024 1025 // Do not try to legalize the target-specific arguments (#1+). 1026 if (Tmp1 != Node->getOperand(0)) { 1027 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1028 Ops[0] = Tmp1; 1029 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0], 1030 Ops.size()), Result.getResNo()); 1031 } 1032 1033 // Remember that the CALLSEQ_START is legalized. 1034 AddLegalizedOperand(Op.getValue(0), Result); 1035 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1036 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1037 1038 // Now that the callseq_start and all of the non-call nodes above this call 1039 // sequence have been legalized, legalize the call itself. During this 1040 // process, no libcalls can/will be inserted, guaranteeing that no calls 1041 // can overlap. 1042 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1043 // Note that we are selecting this call! 1044 LastCALLSEQ_END = SDValue(CallEnd, 0); 1045 IsLegalizingCall = true; 1046 1047 // Legalize the call, starting from the CALLSEQ_END. 1048 LegalizeOp(LastCALLSEQ_END); 1049 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1050 return Result; 1051 } 1052 case ISD::CALLSEQ_END: 1053 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1054 // will cause this node to be legalized as well as handling libcalls right. 1055 if (LastCALLSEQ_END.getNode() != Node) { 1056 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1057 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1058 assert(I != LegalizedNodes.end() && 1059 "Legalizing the call start should have legalized this node!"); 1060 return I->second; 1061 } 1062 1063 // Otherwise, the call start has been legalized and everything is going 1064 // according to plan. Just legalize ourselves normally here. 1065 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1066 // Do not try to legalize the target-specific arguments (#1+), except for 1067 // an optional flag input. 1068 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1069 if (Tmp1 != Node->getOperand(0)) { 1070 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1071 Ops[0] = Tmp1; 1072 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1073 &Ops[0], Ops.size()), 1074 Result.getResNo()); 1075 } 1076 } else { 1077 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1078 if (Tmp1 != Node->getOperand(0) || 1079 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1080 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1081 Ops[0] = Tmp1; 1082 Ops.back() = Tmp2; 1083 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1084 &Ops[0], Ops.size()), 1085 Result.getResNo()); 1086 } 1087 } 1088 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1089 // This finishes up call legalization. 1090 IsLegalizingCall = false; 1091 1092 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1093 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1094 if (Node->getNumValues() == 2) 1095 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1096 return Result.getValue(Op.getResNo()); 1097 case ISD::LOAD: { 1098 LoadSDNode *LD = cast<LoadSDNode>(Node); 1099 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1100 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1101 1102 ISD::LoadExtType ExtType = LD->getExtensionType(); 1103 if (ExtType == ISD::NON_EXTLOAD) { 1104 EVT VT = Node->getValueType(0); 1105 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1106 Tmp1, Tmp2, LD->getOffset()), 1107 Result.getResNo()); 1108 Tmp3 = Result.getValue(0); 1109 Tmp4 = Result.getValue(1); 1110 1111 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1112 default: assert(0 && "This action is not supported yet!"); 1113 case TargetLowering::Legal: 1114 // If this is an unaligned load and the target doesn't support it, 1115 // expand it. 1116 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1117 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1118 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1119 if (LD->getAlignment() < ABIAlignment){ 1120 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1121 DAG, TLI); 1122 Tmp3 = Result.getOperand(0); 1123 Tmp4 = Result.getOperand(1); 1124 Tmp3 = LegalizeOp(Tmp3); 1125 Tmp4 = LegalizeOp(Tmp4); 1126 } 1127 } 1128 break; 1129 case TargetLowering::Custom: 1130 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1131 if (Tmp1.getNode()) { 1132 Tmp3 = LegalizeOp(Tmp1); 1133 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1134 } 1135 break; 1136 case TargetLowering::Promote: { 1137 // Only promote a load of vector type to another. 1138 assert(VT.isVector() && "Cannot promote this load!"); 1139 // Change base type to a different vector type. 1140 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1141 1142 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(), 1143 LD->isVolatile(), LD->isNonTemporal(), 1144 LD->getAlignment()); 1145 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1146 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1147 break; 1148 } 1149 } 1150 // Since loads produce two values, make sure to remember that we 1151 // legalized both of them. 1152 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1153 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1154 return Op.getResNo() ? Tmp4 : Tmp3; 1155 } 1156 1157 EVT SrcVT = LD->getMemoryVT(); 1158 unsigned SrcWidth = SrcVT.getSizeInBits(); 1159 unsigned Alignment = LD->getAlignment(); 1160 bool isVolatile = LD->isVolatile(); 1161 bool isNonTemporal = LD->isNonTemporal(); 1162 1163 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1164 // Some targets pretend to have an i1 loading operation, and actually 1165 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1166 // bits are guaranteed to be zero; it helps the optimizers understand 1167 // that these bits are zero. It is also useful for EXTLOAD, since it 1168 // tells the optimizers that those bits are undefined. It would be 1169 // nice to have an effective generic way of getting these benefits... 1170 // Until such a way is found, don't insist on promoting i1 here. 1171 (SrcVT != MVT::i1 || 1172 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1173 // Promote to a byte-sized load if not loading an integral number of 1174 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1175 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1176 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 1177 SDValue Ch; 1178 1179 // The extra bits are guaranteed to be zero, since we stored them that 1180 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1181 1182 ISD::LoadExtType NewExtType = 1183 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1184 1185 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), dl, 1186 Tmp1, Tmp2, LD->getPointerInfo(), 1187 NVT, isVolatile, isNonTemporal, Alignment); 1188 1189 Ch = Result.getValue(1); // The chain. 1190 1191 if (ExtType == ISD::SEXTLOAD) 1192 // Having the top bits zero doesn't help when sign extending. 1193 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1194 Result.getValueType(), 1195 Result, DAG.getValueType(SrcVT)); 1196 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1197 // All the top bits are guaranteed to be zero - inform the optimizers. 1198 Result = DAG.getNode(ISD::AssertZext, dl, 1199 Result.getValueType(), Result, 1200 DAG.getValueType(SrcVT)); 1201 1202 Tmp1 = LegalizeOp(Result); 1203 Tmp2 = LegalizeOp(Ch); 1204 } else if (SrcWidth & (SrcWidth - 1)) { 1205 // If not loading a power-of-2 number of bits, expand as two loads. 1206 assert(!SrcVT.isVector() && "Unsupported extload!"); 1207 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1208 assert(RoundWidth < SrcWidth); 1209 unsigned ExtraWidth = SrcWidth - RoundWidth; 1210 assert(ExtraWidth < RoundWidth); 1211 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1212 "Load size not an integral number of bytes!"); 1213 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1214 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1215 SDValue Lo, Hi, Ch; 1216 unsigned IncrementSize; 1217 1218 if (TLI.isLittleEndian()) { 1219 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1220 // Load the bottom RoundWidth bits. 1221 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), dl, 1222 Tmp1, Tmp2, 1223 LD->getPointerInfo(), RoundVT, isVolatile, 1224 isNonTemporal, Alignment); 1225 1226 // Load the remaining ExtraWidth bits. 1227 IncrementSize = RoundWidth / 8; 1228 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1229 DAG.getIntPtrConstant(IncrementSize)); 1230 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2, 1231 LD->getPointerInfo().getWithOffset(IncrementSize), 1232 ExtraVT, isVolatile, isNonTemporal, 1233 MinAlign(Alignment, IncrementSize)); 1234 1235 // Build a factor node to remember that this load is independent of 1236 // the other one. 1237 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1238 Hi.getValue(1)); 1239 1240 // Move the top bits to the right place. 1241 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1242 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1243 1244 // Join the hi and lo parts. 1245 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1246 } else { 1247 // Big endian - avoid unaligned loads. 1248 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1249 // Load the top RoundWidth bits. 1250 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2, 1251 LD->getPointerInfo(), RoundVT, isVolatile, 1252 isNonTemporal, Alignment); 1253 1254 // Load the remaining ExtraWidth bits. 1255 IncrementSize = RoundWidth / 8; 1256 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1257 DAG.getIntPtrConstant(IncrementSize)); 1258 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, 1259 Node->getValueType(0), dl, Tmp1, Tmp2, 1260 LD->getPointerInfo().getWithOffset(IncrementSize), 1261 ExtraVT, isVolatile, isNonTemporal, 1262 MinAlign(Alignment, IncrementSize)); 1263 1264 // Build a factor node to remember that this load is independent of 1265 // the other one. 1266 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1267 Hi.getValue(1)); 1268 1269 // Move the top bits to the right place. 1270 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1271 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1272 1273 // Join the hi and lo parts. 1274 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1275 } 1276 1277 Tmp1 = LegalizeOp(Result); 1278 Tmp2 = LegalizeOp(Ch); 1279 } else { 1280 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1281 default: assert(0 && "This action is not supported yet!"); 1282 case TargetLowering::Custom: 1283 isCustom = true; 1284 // FALLTHROUGH 1285 case TargetLowering::Legal: 1286 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1287 Tmp1, Tmp2, LD->getOffset()), 1288 Result.getResNo()); 1289 Tmp1 = Result.getValue(0); 1290 Tmp2 = Result.getValue(1); 1291 1292 if (isCustom) { 1293 Tmp3 = TLI.LowerOperation(Result, DAG); 1294 if (Tmp3.getNode()) { 1295 Tmp1 = LegalizeOp(Tmp3); 1296 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1297 } 1298 } else { 1299 // If this is an unaligned load and the target doesn't support it, 1300 // expand it. 1301 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1302 const Type *Ty = 1303 LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1304 unsigned ABIAlignment = 1305 TLI.getTargetData()->getABITypeAlignment(Ty); 1306 if (LD->getAlignment() < ABIAlignment){ 1307 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1308 DAG, TLI); 1309 Tmp1 = Result.getOperand(0); 1310 Tmp2 = Result.getOperand(1); 1311 Tmp1 = LegalizeOp(Tmp1); 1312 Tmp2 = LegalizeOp(Tmp2); 1313 } 1314 } 1315 } 1316 break; 1317 case TargetLowering::Expand: 1318 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) { 1319 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, 1320 LD->getPointerInfo(), 1321 LD->isVolatile(), LD->isNonTemporal(), 1322 LD->getAlignment()); 1323 unsigned ExtendOp; 1324 switch (ExtType) { 1325 case ISD::EXTLOAD: 1326 ExtendOp = (SrcVT.isFloatingPoint() ? 1327 ISD::FP_EXTEND : ISD::ANY_EXTEND); 1328 break; 1329 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break; 1330 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break; 1331 default: llvm_unreachable("Unexpected extend load type!"); 1332 } 1333 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load); 1334 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1335 Tmp2 = LegalizeOp(Load.getValue(1)); 1336 break; 1337 } 1338 // FIXME: This does not work for vectors on most targets. Sign- and 1339 // zero-extend operations are currently folded into extending loads, 1340 // whether they are legal or not, and then we end up here without any 1341 // support for legalizing them. 1342 assert(ExtType != ISD::EXTLOAD && 1343 "EXTLOAD should always be supported!"); 1344 // Turn the unsupported load into an EXTLOAD followed by an explicit 1345 // zero/sign extend inreg. 1346 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), dl, 1347 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT, 1348 LD->isVolatile(), LD->isNonTemporal(), 1349 LD->getAlignment()); 1350 SDValue ValRes; 1351 if (ExtType == ISD::SEXTLOAD) 1352 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1353 Result.getValueType(), 1354 Result, DAG.getValueType(SrcVT)); 1355 else 1356 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1357 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1358 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1359 break; 1360 } 1361 } 1362 1363 // Since loads produce two values, make sure to remember that we legalized 1364 // both of them. 1365 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1366 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1367 return Op.getResNo() ? Tmp2 : Tmp1; 1368 } 1369 case ISD::STORE: { 1370 StoreSDNode *ST = cast<StoreSDNode>(Node); 1371 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1372 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1373 int SVOffset = ST->getSrcValueOffset(); 1374 unsigned Alignment = ST->getAlignment(); 1375 bool isVolatile = ST->isVolatile(); 1376 bool isNonTemporal = ST->isNonTemporal(); 1377 1378 if (!ST->isTruncatingStore()) { 1379 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1380 Result = SDValue(OptStore, 0); 1381 break; 1382 } 1383 1384 { 1385 Tmp3 = LegalizeOp(ST->getValue()); 1386 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1387 Tmp1, Tmp3, Tmp2, 1388 ST->getOffset()), 1389 Result.getResNo()); 1390 1391 EVT VT = Tmp3.getValueType(); 1392 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1393 default: assert(0 && "This action is not supported yet!"); 1394 case TargetLowering::Legal: 1395 // If this is an unaligned store and the target doesn't support it, 1396 // expand it. 1397 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1398 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1399 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1400 if (ST->getAlignment() < ABIAlignment) 1401 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1402 DAG, TLI); 1403 } 1404 break; 1405 case TargetLowering::Custom: 1406 Tmp1 = TLI.LowerOperation(Result, DAG); 1407 if (Tmp1.getNode()) Result = Tmp1; 1408 break; 1409 case TargetLowering::Promote: 1410 assert(VT.isVector() && "Unknown legal promote case!"); 1411 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1412 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1413 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1414 ST->getSrcValue(), SVOffset, isVolatile, 1415 isNonTemporal, Alignment); 1416 break; 1417 } 1418 break; 1419 } 1420 } else { 1421 Tmp3 = LegalizeOp(ST->getValue()); 1422 1423 EVT StVT = ST->getMemoryVT(); 1424 unsigned StWidth = StVT.getSizeInBits(); 1425 1426 if (StWidth != StVT.getStoreSizeInBits()) { 1427 // Promote to a byte-sized store with upper bits zero if not 1428 // storing an integral number of bytes. For example, promote 1429 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1430 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), 1431 StVT.getStoreSizeInBits()); 1432 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1433 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1434 SVOffset, NVT, isVolatile, isNonTemporal, 1435 Alignment); 1436 } else if (StWidth & (StWidth - 1)) { 1437 // If not storing a power-of-2 number of bits, expand as two stores. 1438 assert(!StVT.isVector() && "Unsupported truncstore!"); 1439 unsigned RoundWidth = 1 << Log2_32(StWidth); 1440 assert(RoundWidth < StWidth); 1441 unsigned ExtraWidth = StWidth - RoundWidth; 1442 assert(ExtraWidth < RoundWidth); 1443 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1444 "Store size not an integral number of bytes!"); 1445 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1446 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1447 SDValue Lo, Hi; 1448 unsigned IncrementSize; 1449 1450 if (TLI.isLittleEndian()) { 1451 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1452 // Store the bottom RoundWidth bits. 1453 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1454 SVOffset, RoundVT, 1455 isVolatile, isNonTemporal, Alignment); 1456 1457 // Store the remaining ExtraWidth bits. 1458 IncrementSize = RoundWidth / 8; 1459 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1460 DAG.getIntPtrConstant(IncrementSize)); 1461 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1462 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1463 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1464 SVOffset + IncrementSize, ExtraVT, isVolatile, 1465 isNonTemporal, 1466 MinAlign(Alignment, IncrementSize)); 1467 } else { 1468 // Big endian - avoid unaligned stores. 1469 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1470 // Store the top RoundWidth bits. 1471 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1472 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1473 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1474 SVOffset, RoundVT, isVolatile, isNonTemporal, 1475 Alignment); 1476 1477 // Store the remaining ExtraWidth bits. 1478 IncrementSize = RoundWidth / 8; 1479 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1480 DAG.getIntPtrConstant(IncrementSize)); 1481 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1482 SVOffset + IncrementSize, ExtraVT, isVolatile, 1483 isNonTemporal, 1484 MinAlign(Alignment, IncrementSize)); 1485 } 1486 1487 // The order of the stores doesn't matter. 1488 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1489 } else { 1490 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1491 Tmp2 != ST->getBasePtr()) 1492 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1493 Tmp1, Tmp3, Tmp2, 1494 ST->getOffset()), 1495 Result.getResNo()); 1496 1497 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1498 default: assert(0 && "This action is not supported yet!"); 1499 case TargetLowering::Legal: 1500 // If this is an unaligned store and the target doesn't support it, 1501 // expand it. 1502 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1503 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1504 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1505 if (ST->getAlignment() < ABIAlignment) 1506 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1507 DAG, TLI); 1508 } 1509 break; 1510 case TargetLowering::Custom: 1511 Result = TLI.LowerOperation(Result, DAG); 1512 break; 1513 case Expand: 1514 // TRUNCSTORE:i16 i32 -> STORE i16 1515 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1516 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1517 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1518 SVOffset, isVolatile, isNonTemporal, 1519 Alignment); 1520 break; 1521 } 1522 } 1523 } 1524 break; 1525 } 1526 } 1527 assert(Result.getValueType() == Op.getValueType() && 1528 "Bad legalization!"); 1529 1530 // Make sure that the generated code is itself legal. 1531 if (Result != Op) 1532 Result = LegalizeOp(Result); 1533 1534 // Note that LegalizeOp may be reentered even from single-use nodes, which 1535 // means that we always must cache transformed nodes. 1536 AddLegalizedOperand(Op, Result); 1537 return Result; 1538} 1539 1540SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1541 SDValue Vec = Op.getOperand(0); 1542 SDValue Idx = Op.getOperand(1); 1543 DebugLoc dl = Op.getDebugLoc(); 1544 // Store the value to a temporary stack slot, then LOAD the returned part. 1545 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1546 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0, 1547 false, false, 0); 1548 1549 // Add the offset to the index. 1550 unsigned EltSize = 1551 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1552 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1553 DAG.getConstant(EltSize, Idx.getValueType())); 1554 1555 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1556 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1557 else 1558 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1559 1560 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1561 1562 if (Op.getValueType().isVector()) 1563 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(), 1564 false, false, 0); 1565 return DAG.getExtLoad(ISD::EXTLOAD, Op.getValueType(), dl, Ch, StackPtr, 1566 MachinePointerInfo(), 1567 Vec.getValueType().getVectorElementType(), 1568 false, false, 0); 1569} 1570 1571SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1572 // We can't handle this case efficiently. Allocate a sufficiently 1573 // aligned object on the stack, store each element into it, then load 1574 // the result as a vector. 1575 // Create the stack frame object. 1576 EVT VT = Node->getValueType(0); 1577 EVT EltVT = VT.getVectorElementType(); 1578 DebugLoc dl = Node->getDebugLoc(); 1579 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1580 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1581 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI); 1582 1583 // Emit a store of each element to the stack slot. 1584 SmallVector<SDValue, 8> Stores; 1585 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1586 // Store (in the right endianness) the elements to memory. 1587 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1588 // Ignore undef elements. 1589 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1590 1591 unsigned Offset = TypeByteSize*i; 1592 1593 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1594 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1595 1596 // If the destination vector element type is narrower than the source 1597 // element type, only store the bits necessary. 1598 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1599 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1600 Node->getOperand(i), Idx, 1601 PtrInfo.getWithOffset(Offset), 1602 EltVT, false, false, 0)); 1603 } else 1604 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1605 Node->getOperand(i), Idx, 1606 PtrInfo.getWithOffset(Offset), 1607 false, false, 0)); 1608 } 1609 1610 SDValue StoreChain; 1611 if (!Stores.empty()) // Not all undef elements? 1612 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1613 &Stores[0], Stores.size()); 1614 else 1615 StoreChain = DAG.getEntryNode(); 1616 1617 // Result is a load from the stack slot. 1618 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0); 1619} 1620 1621SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1622 DebugLoc dl = Node->getDebugLoc(); 1623 SDValue Tmp1 = Node->getOperand(0); 1624 SDValue Tmp2 = Node->getOperand(1); 1625 1626 // Get the sign bit of the RHS. First obtain a value that has the same 1627 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1628 SDValue SignBit; 1629 EVT FloatVT = Tmp2.getValueType(); 1630 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1631 if (isTypeLegal(IVT)) { 1632 // Convert to an integer with the same sign bit. 1633 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 1634 } else { 1635 // Store the float to memory, then load the sign part out as an integer. 1636 MVT LoadTy = TLI.getPointerTy(); 1637 // First create a temporary that is aligned for both the load and store. 1638 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1639 // Then store the float to it. 1640 SDValue Ch = 1641 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, NULL, 0, 1642 false, false, 0); 1643 if (TLI.isBigEndian()) { 1644 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1645 // Load out a legal integer with the same sign bit as the float. 1646 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(), 1647 false, false, 0); 1648 } else { // Little endian 1649 SDValue LoadPtr = StackPtr; 1650 // The float may be wider than the integer we are going to load. Advance 1651 // the pointer so that the loaded integer will contain the sign bit. 1652 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1653 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1654 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1655 LoadPtr, DAG.getIntPtrConstant(ByteOffset)); 1656 // Load a legal integer containing the sign bit. 1657 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(), 1658 false, false, 0); 1659 // Move the sign bit to the top bit of the loaded integer. 1660 unsigned BitShift = LoadTy.getSizeInBits() - 1661 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1662 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1663 if (BitShift) 1664 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1665 DAG.getConstant(BitShift,TLI.getShiftAmountTy())); 1666 } 1667 } 1668 // Now get the sign bit proper, by seeing whether the value is negative. 1669 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1670 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1671 ISD::SETLT); 1672 // Get the absolute value of the result. 1673 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1674 // Select between the nabs and abs value based on the sign bit of 1675 // the input. 1676 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1677 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1678 AbsVal); 1679} 1680 1681void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1682 SmallVectorImpl<SDValue> &Results) { 1683 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1684 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1685 " not tell us which reg is the stack pointer!"); 1686 DebugLoc dl = Node->getDebugLoc(); 1687 EVT VT = Node->getValueType(0); 1688 SDValue Tmp1 = SDValue(Node, 0); 1689 SDValue Tmp2 = SDValue(Node, 1); 1690 SDValue Tmp3 = Node->getOperand(2); 1691 SDValue Chain = Tmp1.getOperand(0); 1692 1693 // Chain the dynamic stack allocation so that it doesn't modify the stack 1694 // pointer when other instructions are using the stack. 1695 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1696 1697 SDValue Size = Tmp2.getOperand(1); 1698 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1699 Chain = SP.getValue(1); 1700 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1701 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); 1702 if (Align > StackAlign) 1703 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1704 DAG.getConstant(-(uint64_t)Align, VT)); 1705 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1706 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1707 1708 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1709 DAG.getIntPtrConstant(0, true), SDValue()); 1710 1711 Results.push_back(Tmp1); 1712 Results.push_back(Tmp2); 1713} 1714 1715/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1716/// condition code CC on the current target. This routine expands SETCC with 1717/// illegal condition code into AND / OR of multiple SETCC values. 1718void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1719 SDValue &LHS, SDValue &RHS, 1720 SDValue &CC, 1721 DebugLoc dl) { 1722 EVT OpVT = LHS.getValueType(); 1723 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1724 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1725 default: assert(0 && "Unknown condition code action!"); 1726 case TargetLowering::Legal: 1727 // Nothing to do. 1728 break; 1729 case TargetLowering::Expand: { 1730 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1731 unsigned Opc = 0; 1732 switch (CCCode) { 1733 default: assert(0 && "Don't know how to expand this condition!"); 1734 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1735 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1736 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1737 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1738 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1739 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1740 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1741 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1742 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1743 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1744 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1745 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1746 // FIXME: Implement more expansions. 1747 } 1748 1749 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1750 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1751 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1752 RHS = SDValue(); 1753 CC = SDValue(); 1754 break; 1755 } 1756 } 1757} 1758 1759/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1760/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1761/// a load from the stack slot to DestVT, extending it if needed. 1762/// The resultant code need not be legal. 1763SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1764 EVT SlotVT, 1765 EVT DestVT, 1766 DebugLoc dl) { 1767 // Create the stack frame object. 1768 unsigned SrcAlign = 1769 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1770 getTypeForEVT(*DAG.getContext())); 1771 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1772 1773 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1774 int SPFI = StackPtrFI->getIndex(); 1775 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1776 1777 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1778 unsigned SlotSize = SlotVT.getSizeInBits(); 1779 unsigned DestSize = DestVT.getSizeInBits(); 1780 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); 1781 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType); 1782 1783 // Emit a store to the stack slot. Use a truncstore if the input value is 1784 // later than DestVT. 1785 SDValue Store; 1786 1787 if (SrcSize > SlotSize) 1788 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1789 SV, 0, SlotVT, false, false, SrcAlign); 1790 else { 1791 assert(SrcSize == SlotSize && "Invalid store"); 1792 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1793 SV, 0, false, false, SrcAlign); 1794 } 1795 1796 // Result is a load from the stack slot. 1797 if (SlotSize == DestSize) 1798 return DAG.getLoad(DestVT, dl, Store, FIPtr, MachinePointerInfo(SV), 1799 false, false, DestAlign); 1800 1801 assert(SlotSize < DestSize && "Unknown extension!"); 1802 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, Store, FIPtr, 1803 MachinePointerInfo(SV), SlotVT, 1804 false, false, DestAlign); 1805} 1806 1807SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1808 DebugLoc dl = Node->getDebugLoc(); 1809 // Create a vector sized/aligned stack slot, store the value to element #0, 1810 // then load the whole vector back out. 1811 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1812 1813 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1814 int SPFI = StackPtrFI->getIndex(); 1815 1816 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1817 StackPtr, 1818 MachinePointerInfo::getFixedStack(SPFI), 1819 Node->getValueType(0).getVectorElementType(), 1820 false, false, 0); 1821 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1822 MachinePointerInfo::getFixedStack(SPFI), 1823 false, false, 0); 1824} 1825 1826 1827/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1828/// support the operation, but do support the resultant vector type. 1829SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1830 unsigned NumElems = Node->getNumOperands(); 1831 SDValue Value1, Value2; 1832 DebugLoc dl = Node->getDebugLoc(); 1833 EVT VT = Node->getValueType(0); 1834 EVT OpVT = Node->getOperand(0).getValueType(); 1835 EVT EltVT = VT.getVectorElementType(); 1836 1837 // If the only non-undef value is the low element, turn this into a 1838 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1839 bool isOnlyLowElement = true; 1840 bool MoreThanTwoValues = false; 1841 bool isConstant = true; 1842 for (unsigned i = 0; i < NumElems; ++i) { 1843 SDValue V = Node->getOperand(i); 1844 if (V.getOpcode() == ISD::UNDEF) 1845 continue; 1846 if (i > 0) 1847 isOnlyLowElement = false; 1848 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1849 isConstant = false; 1850 1851 if (!Value1.getNode()) { 1852 Value1 = V; 1853 } else if (!Value2.getNode()) { 1854 if (V != Value1) 1855 Value2 = V; 1856 } else if (V != Value1 && V != Value2) { 1857 MoreThanTwoValues = true; 1858 } 1859 } 1860 1861 if (!Value1.getNode()) 1862 return DAG.getUNDEF(VT); 1863 1864 if (isOnlyLowElement) 1865 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1866 1867 // If all elements are constants, create a load from the constant pool. 1868 if (isConstant) { 1869 std::vector<Constant*> CV; 1870 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1871 if (ConstantFPSDNode *V = 1872 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1873 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1874 } else if (ConstantSDNode *V = 1875 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1876 if (OpVT==EltVT) 1877 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1878 else { 1879 // If OpVT and EltVT don't match, EltVT is not legal and the 1880 // element values have been promoted/truncated earlier. Undo this; 1881 // we don't want a v16i8 to become a v16i32 for example. 1882 const ConstantInt *CI = V->getConstantIntValue(); 1883 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1884 CI->getZExtValue())); 1885 } 1886 } else { 1887 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1888 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1889 CV.push_back(UndefValue::get(OpNTy)); 1890 } 1891 } 1892 Constant *CP = ConstantVector::get(CV); 1893 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1894 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1895 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1896 MachinePointerInfo::getConstantPool(), 1897 false, false, Alignment); 1898 } 1899 1900 if (!MoreThanTwoValues) { 1901 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1902 for (unsigned i = 0; i < NumElems; ++i) { 1903 SDValue V = Node->getOperand(i); 1904 if (V.getOpcode() == ISD::UNDEF) 1905 continue; 1906 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1907 } 1908 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1909 // Get the splatted value into the low element of a vector register. 1910 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1911 SDValue Vec2; 1912 if (Value2.getNode()) 1913 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1914 else 1915 Vec2 = DAG.getUNDEF(VT); 1916 1917 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1918 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1919 } 1920 } 1921 1922 // Otherwise, we can't handle this case efficiently. 1923 return ExpandVectorBuildThroughStack(Node); 1924} 1925 1926// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1927// does not fit into a register, return the lo part and set the hi part to the 1928// by-reg argument. If it does fit into a single register, return the result 1929// and leave the Hi part unset. 1930SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1931 bool isSigned) { 1932 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1933 // The input chain to this libcall is the entry node of the function. 1934 // Legalizing the call will automatically add the previous call to the 1935 // dependence. 1936 SDValue InChain = DAG.getEntryNode(); 1937 1938 TargetLowering::ArgListTy Args; 1939 TargetLowering::ArgListEntry Entry; 1940 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1941 EVT ArgVT = Node->getOperand(i).getValueType(); 1942 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1943 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1944 Entry.isSExt = isSigned; 1945 Entry.isZExt = !isSigned; 1946 Args.push_back(Entry); 1947 } 1948 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1949 TLI.getPointerTy()); 1950 1951 // Splice the libcall in wherever FindInputOutputChains tells us to. 1952 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1953 std::pair<SDValue, SDValue> CallInfo = 1954 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1955 0, TLI.getLibcallCallingConv(LC), false, 1956 /*isReturnValueUsed=*/true, 1957 Callee, Args, DAG, Node->getDebugLoc()); 1958 1959 // Legalize the call sequence, starting with the chain. This will advance 1960 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1961 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1962 LegalizeOp(CallInfo.second); 1963 return CallInfo.first; 1964} 1965 1966// ExpandChainLibCall - Expand a node into a call to a libcall. Similar to 1967// ExpandLibCall except that the first operand is the in-chain. 1968std::pair<SDValue, SDValue> 1969SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC, 1970 SDNode *Node, 1971 bool isSigned) { 1972 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1973 SDValue InChain = Node->getOperand(0); 1974 1975 TargetLowering::ArgListTy Args; 1976 TargetLowering::ArgListEntry Entry; 1977 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) { 1978 EVT ArgVT = Node->getOperand(i).getValueType(); 1979 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1980 Entry.Node = Node->getOperand(i); 1981 Entry.Ty = ArgTy; 1982 Entry.isSExt = isSigned; 1983 Entry.isZExt = !isSigned; 1984 Args.push_back(Entry); 1985 } 1986 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1987 TLI.getPointerTy()); 1988 1989 // Splice the libcall in wherever FindInputOutputChains tells us to. 1990 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1991 std::pair<SDValue, SDValue> CallInfo = 1992 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1993 0, TLI.getLibcallCallingConv(LC), false, 1994 /*isReturnValueUsed=*/true, 1995 Callee, Args, DAG, Node->getDebugLoc()); 1996 1997 // Legalize the call sequence, starting with the chain. This will advance 1998 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1999 // was added by LowerCallTo (guaranteeing proper serialization of calls). 2000 LegalizeOp(CallInfo.second); 2001 return CallInfo; 2002} 2003 2004SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 2005 RTLIB::Libcall Call_F32, 2006 RTLIB::Libcall Call_F64, 2007 RTLIB::Libcall Call_F80, 2008 RTLIB::Libcall Call_PPCF128) { 2009 RTLIB::Libcall LC; 2010 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 2011 default: assert(0 && "Unexpected request for libcall!"); 2012 case MVT::f32: LC = Call_F32; break; 2013 case MVT::f64: LC = Call_F64; break; 2014 case MVT::f80: LC = Call_F80; break; 2015 case MVT::ppcf128: LC = Call_PPCF128; break; 2016 } 2017 return ExpandLibCall(LC, Node, false); 2018} 2019 2020SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 2021 RTLIB::Libcall Call_I8, 2022 RTLIB::Libcall Call_I16, 2023 RTLIB::Libcall Call_I32, 2024 RTLIB::Libcall Call_I64, 2025 RTLIB::Libcall Call_I128) { 2026 RTLIB::Libcall LC; 2027 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 2028 default: assert(0 && "Unexpected request for libcall!"); 2029 case MVT::i8: LC = Call_I8; break; 2030 case MVT::i16: LC = Call_I16; break; 2031 case MVT::i32: LC = Call_I32; break; 2032 case MVT::i64: LC = Call_I64; break; 2033 case MVT::i128: LC = Call_I128; break; 2034 } 2035 return ExpandLibCall(LC, Node, isSigned); 2036} 2037 2038/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 2039/// INT_TO_FP operation of the specified operand when the target requests that 2040/// we expand it. At this point, we know that the result and operand types are 2041/// legal for the target. 2042SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 2043 SDValue Op0, 2044 EVT DestVT, 2045 DebugLoc dl) { 2046 if (Op0.getValueType() == MVT::i32) { 2047 // simple 32-bit [signed|unsigned] integer to float/double expansion 2048 2049 // Get the stack frame index of a 8 byte buffer. 2050 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 2051 2052 // word offset constant for Hi/Lo address computation 2053 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 2054 // set up Hi and Lo (into buffer) address based on endian 2055 SDValue Hi = StackSlot; 2056 SDValue Lo = DAG.getNode(ISD::ADD, dl, 2057 TLI.getPointerTy(), StackSlot, WordOff); 2058 if (TLI.isLittleEndian()) 2059 std::swap(Hi, Lo); 2060 2061 // if signed map to unsigned space 2062 SDValue Op0Mapped; 2063 if (isSigned) { 2064 // constant used to invert sign bit (signed to unsigned mapping) 2065 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 2066 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 2067 } else { 2068 Op0Mapped = Op0; 2069 } 2070 // store the lo of the constructed double - based on integer input 2071 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 2072 Op0Mapped, Lo, NULL, 0, 2073 false, false, 0); 2074 // initial hi portion of constructed double 2075 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 2076 // store the hi of the constructed double - biased exponent 2077 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0, 2078 false, false, 0); 2079 // load the constructed double 2080 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, 2081 MachinePointerInfo(), false, false, 0); 2082 // FP constant to bias correct the final result 2083 SDValue Bias = DAG.getConstantFP(isSigned ? 2084 BitsToDouble(0x4330000080000000ULL) : 2085 BitsToDouble(0x4330000000000000ULL), 2086 MVT::f64); 2087 // subtract the bias 2088 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2089 // final result 2090 SDValue Result; 2091 // handle final rounding 2092 if (DestVT == MVT::f64) { 2093 // do nothing 2094 Result = Sub; 2095 } else if (DestVT.bitsLT(MVT::f64)) { 2096 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2097 DAG.getIntPtrConstant(0)); 2098 } else if (DestVT.bitsGT(MVT::f64)) { 2099 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2100 } 2101 return Result; 2102 } 2103 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2104 // Code below here assumes !isSigned without checking again. 2105 2106 // Implementation of unsigned i64 to f64 following the algorithm in 2107 // __floatundidf in compiler_rt. This implementation has the advantage 2108 // of performing rounding correctly, both in the default rounding mode 2109 // and in all alternate rounding modes. 2110 // TODO: Generalize this for use with other types. 2111 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2112 SDValue TwoP52 = 2113 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2114 SDValue TwoP84PlusTwoP52 = 2115 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2116 SDValue TwoP84 = 2117 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2118 2119 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2120 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2121 DAG.getConstant(32, MVT::i64)); 2122 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2123 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2124 SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr); 2125 SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr); 2126 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, 2127 TwoP84PlusTwoP52); 2128 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2129 } 2130 2131 // Implementation of unsigned i64 to f32. This implementation has the 2132 // advantage of performing rounding correctly. 2133 // TODO: Generalize this for use with other types. 2134 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) { 2135 EVT SHVT = TLI.getShiftAmountTy(); 2136 2137 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2138 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64)); 2139 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, 2140 DAG.getConstant(UINT64_C(0x800), MVT::i64)); 2141 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2142 DAG.getConstant(UINT64_C(0x7ff), MVT::i64)); 2143 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2144 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); 2145 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0); 2146 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2147 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64), 2148 ISD::SETUGE); 2149 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0); 2150 2151 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, 2152 DAG.getConstant(32, SHVT)); 2153 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh); 2154 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); 2155 SDValue TwoP32 = 2156 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64); 2157 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); 2158 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2); 2159 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo); 2160 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); 2161 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, 2162 DAG.getIntPtrConstant(0)); 2163 2164 } 2165 2166 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2167 2168 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2169 Op0, DAG.getConstant(0, Op0.getValueType()), 2170 ISD::SETLT); 2171 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2172 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2173 SignSet, Four, Zero); 2174 2175 // If the sign bit of the integer is set, the large number will be treated 2176 // as a negative number. To counteract this, the dynamic code adds an 2177 // offset depending on the data type. 2178 uint64_t FF; 2179 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2180 default: assert(0 && "Unsupported integer type!"); 2181 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2182 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2183 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2184 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2185 } 2186 if (TLI.isLittleEndian()) FF <<= 32; 2187 Constant *FudgeFactor = ConstantInt::get( 2188 Type::getInt64Ty(*DAG.getContext()), FF); 2189 2190 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2191 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2192 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2193 Alignment = std::min(Alignment, 4u); 2194 SDValue FudgeInReg; 2195 if (DestVT == MVT::f32) 2196 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2197 MachinePointerInfo::getConstantPool(), 2198 false, false, Alignment); 2199 else { 2200 FudgeInReg = 2201 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, 2202 DAG.getEntryNode(), CPIdx, 2203 MachinePointerInfo::getConstantPool(), 2204 MVT::f32, false, false, Alignment)); 2205 } 2206 2207 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2208} 2209 2210/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2211/// *INT_TO_FP operation of the specified operand when the target requests that 2212/// we promote it. At this point, we know that the result and operand types are 2213/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2214/// operation that takes a larger input. 2215SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2216 EVT DestVT, 2217 bool isSigned, 2218 DebugLoc dl) { 2219 // First step, figure out the appropriate *INT_TO_FP operation to use. 2220 EVT NewInTy = LegalOp.getValueType(); 2221 2222 unsigned OpToUse = 0; 2223 2224 // Scan for the appropriate larger type to use. 2225 while (1) { 2226 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2227 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2228 2229 // If the target supports SINT_TO_FP of this type, use it. 2230 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2231 OpToUse = ISD::SINT_TO_FP; 2232 break; 2233 } 2234 if (isSigned) continue; 2235 2236 // If the target supports UINT_TO_FP of this type, use it. 2237 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2238 OpToUse = ISD::UINT_TO_FP; 2239 break; 2240 } 2241 2242 // Otherwise, try a larger type. 2243 } 2244 2245 // Okay, we found the operation and type to use. Zero extend our input to the 2246 // desired type then run the operation on it. 2247 return DAG.getNode(OpToUse, dl, DestVT, 2248 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2249 dl, NewInTy, LegalOp)); 2250} 2251 2252/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2253/// FP_TO_*INT operation of the specified operand when the target requests that 2254/// we promote it. At this point, we know that the result and operand types are 2255/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2256/// operation that returns a larger result. 2257SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2258 EVT DestVT, 2259 bool isSigned, 2260 DebugLoc dl) { 2261 // First step, figure out the appropriate FP_TO*INT operation to use. 2262 EVT NewOutTy = DestVT; 2263 2264 unsigned OpToUse = 0; 2265 2266 // Scan for the appropriate larger type to use. 2267 while (1) { 2268 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2269 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2270 2271 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2272 OpToUse = ISD::FP_TO_SINT; 2273 break; 2274 } 2275 2276 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2277 OpToUse = ISD::FP_TO_UINT; 2278 break; 2279 } 2280 2281 // Otherwise, try a larger type. 2282 } 2283 2284 2285 // Okay, we found the operation and type to use. 2286 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2287 2288 // Truncate the result of the extended FP_TO_*INT operation to the desired 2289 // size. 2290 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2291} 2292 2293/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2294/// 2295SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2296 EVT VT = Op.getValueType(); 2297 EVT SHVT = TLI.getShiftAmountTy(); 2298 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2299 switch (VT.getSimpleVT().SimpleTy) { 2300 default: assert(0 && "Unhandled Expand type in BSWAP!"); 2301 case MVT::i16: 2302 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2303 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2304 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2305 case MVT::i32: 2306 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2307 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2308 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2309 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2310 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2311 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2312 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2313 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2314 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2315 case MVT::i64: 2316 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2317 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2318 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2319 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2320 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2321 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2322 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2323 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2324 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2325 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2326 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2327 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2328 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2329 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2330 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2331 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2332 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2333 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2334 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2335 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2336 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2337 } 2338} 2339 2340/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2341/// 2342SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2343 DebugLoc dl) { 2344 switch (Opc) { 2345 default: assert(0 && "Cannot expand this yet!"); 2346 case ISD::CTPOP: { 2347 static const uint64_t mask[6] = { 2348 0x5555555555555555ULL, 0x3333333333333333ULL, 2349 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2350 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2351 }; 2352 EVT VT = Op.getValueType(); 2353 EVT ShVT = TLI.getShiftAmountTy(); 2354 unsigned len = VT.getSizeInBits(); 2355 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2356 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2357 unsigned EltSize = VT.isVector() ? 2358 VT.getVectorElementType().getSizeInBits() : len; 2359 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2360 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2361 Op = DAG.getNode(ISD::ADD, dl, VT, 2362 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2363 DAG.getNode(ISD::AND, dl, VT, 2364 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2365 Tmp2)); 2366 } 2367 return Op; 2368 } 2369 case ISD::CTLZ: { 2370 // for now, we do this: 2371 // x = x | (x >> 1); 2372 // x = x | (x >> 2); 2373 // ... 2374 // x = x | (x >>16); 2375 // x = x | (x >>32); // for 64-bit input 2376 // return popcount(~x); 2377 // 2378 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2379 EVT VT = Op.getValueType(); 2380 EVT ShVT = TLI.getShiftAmountTy(); 2381 unsigned len = VT.getSizeInBits(); 2382 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2383 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2384 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2385 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2386 } 2387 Op = DAG.getNOT(dl, Op, VT); 2388 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2389 } 2390 case ISD::CTTZ: { 2391 // for now, we use: { return popcount(~x & (x - 1)); } 2392 // unless the target has ctlz but not ctpop, in which case we use: 2393 // { return 32 - nlz(~x & (x-1)); } 2394 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2395 EVT VT = Op.getValueType(); 2396 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2397 DAG.getNOT(dl, Op, VT), 2398 DAG.getNode(ISD::SUB, dl, VT, Op, 2399 DAG.getConstant(1, VT))); 2400 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2401 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2402 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2403 return DAG.getNode(ISD::SUB, dl, VT, 2404 DAG.getConstant(VT.getSizeInBits(), VT), 2405 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2406 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2407 } 2408 } 2409} 2410 2411std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) { 2412 unsigned Opc = Node->getOpcode(); 2413 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 2414 RTLIB::Libcall LC; 2415 2416 switch (Opc) { 2417 default: 2418 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 2419 break; 2420 case ISD::ATOMIC_SWAP: 2421 switch (VT.SimpleTy) { 2422 default: llvm_unreachable("Unexpected value type for atomic!"); 2423 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; 2424 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 2425 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; 2426 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; 2427 } 2428 break; 2429 case ISD::ATOMIC_CMP_SWAP: 2430 switch (VT.SimpleTy) { 2431 default: llvm_unreachable("Unexpected value type for atomic!"); 2432 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 2433 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 2434 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 2435 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 2436 } 2437 break; 2438 case ISD::ATOMIC_LOAD_ADD: 2439 switch (VT.SimpleTy) { 2440 default: llvm_unreachable("Unexpected value type for atomic!"); 2441 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 2442 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 2443 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 2444 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 2445 } 2446 break; 2447 case ISD::ATOMIC_LOAD_SUB: 2448 switch (VT.SimpleTy) { 2449 default: llvm_unreachable("Unexpected value type for atomic!"); 2450 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 2451 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 2452 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 2453 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 2454 } 2455 break; 2456 case ISD::ATOMIC_LOAD_AND: 2457 switch (VT.SimpleTy) { 2458 default: llvm_unreachable("Unexpected value type for atomic!"); 2459 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 2460 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 2461 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 2462 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 2463 } 2464 break; 2465 case ISD::ATOMIC_LOAD_OR: 2466 switch (VT.SimpleTy) { 2467 default: llvm_unreachable("Unexpected value type for atomic!"); 2468 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 2469 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 2470 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 2471 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 2472 } 2473 break; 2474 case ISD::ATOMIC_LOAD_XOR: 2475 switch (VT.SimpleTy) { 2476 default: llvm_unreachable("Unexpected value type for atomic!"); 2477 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 2478 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 2479 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 2480 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 2481 } 2482 break; 2483 case ISD::ATOMIC_LOAD_NAND: 2484 switch (VT.SimpleTy) { 2485 default: llvm_unreachable("Unexpected value type for atomic!"); 2486 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 2487 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 2488 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 2489 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 2490 } 2491 break; 2492 } 2493 2494 return ExpandChainLibCall(LC, Node, false); 2495} 2496 2497void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2498 SmallVectorImpl<SDValue> &Results) { 2499 DebugLoc dl = Node->getDebugLoc(); 2500 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2501 switch (Node->getOpcode()) { 2502 case ISD::CTPOP: 2503 case ISD::CTLZ: 2504 case ISD::CTTZ: 2505 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2506 Results.push_back(Tmp1); 2507 break; 2508 case ISD::BSWAP: 2509 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2510 break; 2511 case ISD::FRAMEADDR: 2512 case ISD::RETURNADDR: 2513 case ISD::FRAME_TO_ARGS_OFFSET: 2514 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2515 break; 2516 case ISD::FLT_ROUNDS_: 2517 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2518 break; 2519 case ISD::EH_RETURN: 2520 case ISD::EH_LABEL: 2521 case ISD::PREFETCH: 2522 case ISD::VAEND: 2523 case ISD::EH_SJLJ_LONGJMP: 2524 Results.push_back(Node->getOperand(0)); 2525 break; 2526 case ISD::EH_SJLJ_SETJMP: 2527 Results.push_back(DAG.getConstant(0, MVT::i32)); 2528 Results.push_back(Node->getOperand(0)); 2529 break; 2530 case ISD::MEMBARRIER: { 2531 // If the target didn't lower this, lower it to '__sync_synchronize()' call 2532 TargetLowering::ArgListTy Args; 2533 std::pair<SDValue, SDValue> CallResult = 2534 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2535 false, false, false, false, 0, CallingConv::C, false, 2536 /*isReturnValueUsed=*/true, 2537 DAG.getExternalSymbol("__sync_synchronize", 2538 TLI.getPointerTy()), 2539 Args, DAG, dl); 2540 Results.push_back(CallResult.second); 2541 break; 2542 } 2543 // By default, atomic intrinsics are marked Legal and lowered. Targets 2544 // which don't support them directly, however, may want libcalls, in which 2545 // case they mark them Expand, and we get here. 2546 // FIXME: Unimplemented for now. Add libcalls. 2547 case ISD::ATOMIC_SWAP: 2548 case ISD::ATOMIC_LOAD_ADD: 2549 case ISD::ATOMIC_LOAD_SUB: 2550 case ISD::ATOMIC_LOAD_AND: 2551 case ISD::ATOMIC_LOAD_OR: 2552 case ISD::ATOMIC_LOAD_XOR: 2553 case ISD::ATOMIC_LOAD_NAND: 2554 case ISD::ATOMIC_LOAD_MIN: 2555 case ISD::ATOMIC_LOAD_MAX: 2556 case ISD::ATOMIC_LOAD_UMIN: 2557 case ISD::ATOMIC_LOAD_UMAX: 2558 case ISD::ATOMIC_CMP_SWAP: { 2559 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node); 2560 Results.push_back(Tmp.first); 2561 Results.push_back(Tmp.second); 2562 break; 2563 } 2564 case ISD::DYNAMIC_STACKALLOC: 2565 ExpandDYNAMIC_STACKALLOC(Node, Results); 2566 break; 2567 case ISD::MERGE_VALUES: 2568 for (unsigned i = 0; i < Node->getNumValues(); i++) 2569 Results.push_back(Node->getOperand(i)); 2570 break; 2571 case ISD::UNDEF: { 2572 EVT VT = Node->getValueType(0); 2573 if (VT.isInteger()) 2574 Results.push_back(DAG.getConstant(0, VT)); 2575 else { 2576 assert(VT.isFloatingPoint() && "Unknown value type!"); 2577 Results.push_back(DAG.getConstantFP(0, VT)); 2578 } 2579 break; 2580 } 2581 case ISD::TRAP: { 2582 // If this operation is not supported, lower it to 'abort()' call 2583 TargetLowering::ArgListTy Args; 2584 std::pair<SDValue, SDValue> CallResult = 2585 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2586 false, false, false, false, 0, CallingConv::C, false, 2587 /*isReturnValueUsed=*/true, 2588 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2589 Args, DAG, dl); 2590 Results.push_back(CallResult.second); 2591 break; 2592 } 2593 case ISD::FP_ROUND: 2594 case ISD::BIT_CONVERT: 2595 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2596 Node->getValueType(0), dl); 2597 Results.push_back(Tmp1); 2598 break; 2599 case ISD::FP_EXTEND: 2600 Tmp1 = EmitStackConvert(Node->getOperand(0), 2601 Node->getOperand(0).getValueType(), 2602 Node->getValueType(0), dl); 2603 Results.push_back(Tmp1); 2604 break; 2605 case ISD::SIGN_EXTEND_INREG: { 2606 // NOTE: we could fall back on load/store here too for targets without 2607 // SAR. However, it is doubtful that any exist. 2608 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2609 EVT VT = Node->getValueType(0); 2610 EVT ShiftAmountTy = TLI.getShiftAmountTy(); 2611 if (VT.isVector()) 2612 ShiftAmountTy = VT; 2613 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2614 ExtraVT.getScalarType().getSizeInBits(); 2615 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2616 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2617 Node->getOperand(0), ShiftCst); 2618 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2619 Results.push_back(Tmp1); 2620 break; 2621 } 2622 case ISD::FP_ROUND_INREG: { 2623 // The only way we can lower this is to turn it into a TRUNCSTORE, 2624 // EXTLOAD pair, targetting a temporary location (a stack slot). 2625 2626 // NOTE: there is a choice here between constantly creating new stack 2627 // slots and always reusing the same one. We currently always create 2628 // new ones, as reuse may inhibit scheduling. 2629 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2630 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2631 Node->getValueType(0), dl); 2632 Results.push_back(Tmp1); 2633 break; 2634 } 2635 case ISD::SINT_TO_FP: 2636 case ISD::UINT_TO_FP: 2637 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2638 Node->getOperand(0), Node->getValueType(0), dl); 2639 Results.push_back(Tmp1); 2640 break; 2641 case ISD::FP_TO_UINT: { 2642 SDValue True, False; 2643 EVT VT = Node->getOperand(0).getValueType(); 2644 EVT NVT = Node->getValueType(0); 2645 const uint64_t zero[] = {0, 0}; 2646 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 2647 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2648 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2649 Tmp1 = DAG.getConstantFP(apf, VT); 2650 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2651 Node->getOperand(0), 2652 Tmp1, ISD::SETLT); 2653 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2654 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2655 DAG.getNode(ISD::FSUB, dl, VT, 2656 Node->getOperand(0), Tmp1)); 2657 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2658 DAG.getConstant(x, NVT)); 2659 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2660 Results.push_back(Tmp1); 2661 break; 2662 } 2663 case ISD::VAARG: { 2664 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2665 EVT VT = Node->getValueType(0); 2666 Tmp1 = Node->getOperand(0); 2667 Tmp2 = Node->getOperand(1); 2668 unsigned Align = Node->getConstantOperandVal(3); 2669 2670 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, 2671 MachinePointerInfo(V), false, false, 0); 2672 SDValue VAList = VAListLoad; 2673 2674 if (Align > TLI.getMinStackArgumentAlignment()) { 2675 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2676 2677 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2678 DAG.getConstant(Align - 1, 2679 TLI.getPointerTy())); 2680 2681 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList, 2682 DAG.getConstant(-Align, 2683 TLI.getPointerTy())); 2684 } 2685 2686 // Increment the pointer, VAList, to the next vaarg 2687 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2688 DAG.getConstant(TLI.getTargetData()-> 2689 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2690 TLI.getPointerTy())); 2691 // Store the incremented VAList to the legalized pointer 2692 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, V, 0, 2693 false, false, 0); 2694 // Load the actual argument out of the pointer VAList 2695 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(), 2696 false, false, 0)); 2697 Results.push_back(Results[0].getValue(1)); 2698 break; 2699 } 2700 case ISD::VACOPY: { 2701 // This defaults to loading a pointer from the input and storing it to the 2702 // output, returning the chain. 2703 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2704 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2705 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2706 Node->getOperand(2), MachinePointerInfo(VS), 2707 false, false, 0); 2708 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), 2709 MachinePointerInfo(VD), false, false, 0); 2710 Results.push_back(Tmp1); 2711 break; 2712 } 2713 case ISD::EXTRACT_VECTOR_ELT: 2714 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2715 // This must be an access of the only element. Return it. 2716 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 2717 Node->getOperand(0)); 2718 else 2719 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2720 Results.push_back(Tmp1); 2721 break; 2722 case ISD::EXTRACT_SUBVECTOR: 2723 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2724 break; 2725 case ISD::CONCAT_VECTORS: { 2726 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2727 break; 2728 } 2729 case ISD::SCALAR_TO_VECTOR: 2730 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2731 break; 2732 case ISD::INSERT_VECTOR_ELT: 2733 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2734 Node->getOperand(1), 2735 Node->getOperand(2), dl)); 2736 break; 2737 case ISD::VECTOR_SHUFFLE: { 2738 SmallVector<int, 8> Mask; 2739 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2740 2741 EVT VT = Node->getValueType(0); 2742 EVT EltVT = VT.getVectorElementType(); 2743 if (getTypeAction(EltVT) == Promote) 2744 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT); 2745 unsigned NumElems = VT.getVectorNumElements(); 2746 SmallVector<SDValue, 8> Ops; 2747 for (unsigned i = 0; i != NumElems; ++i) { 2748 if (Mask[i] < 0) { 2749 Ops.push_back(DAG.getUNDEF(EltVT)); 2750 continue; 2751 } 2752 unsigned Idx = Mask[i]; 2753 if (Idx < NumElems) 2754 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2755 Node->getOperand(0), 2756 DAG.getIntPtrConstant(Idx))); 2757 else 2758 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2759 Node->getOperand(1), 2760 DAG.getIntPtrConstant(Idx - NumElems))); 2761 } 2762 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2763 Results.push_back(Tmp1); 2764 break; 2765 } 2766 case ISD::EXTRACT_ELEMENT: { 2767 EVT OpTy = Node->getOperand(0).getValueType(); 2768 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2769 // 1 -> Hi 2770 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2771 DAG.getConstant(OpTy.getSizeInBits()/2, 2772 TLI.getShiftAmountTy())); 2773 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2774 } else { 2775 // 0 -> Lo 2776 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2777 Node->getOperand(0)); 2778 } 2779 Results.push_back(Tmp1); 2780 break; 2781 } 2782 case ISD::STACKSAVE: 2783 // Expand to CopyFromReg if the target set 2784 // StackPointerRegisterToSaveRestore. 2785 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2786 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2787 Node->getValueType(0))); 2788 Results.push_back(Results[0].getValue(1)); 2789 } else { 2790 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2791 Results.push_back(Node->getOperand(0)); 2792 } 2793 break; 2794 case ISD::STACKRESTORE: 2795 // Expand to CopyToReg if the target set 2796 // StackPointerRegisterToSaveRestore. 2797 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2798 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2799 Node->getOperand(1))); 2800 } else { 2801 Results.push_back(Node->getOperand(0)); 2802 } 2803 break; 2804 case ISD::FCOPYSIGN: 2805 Results.push_back(ExpandFCOPYSIGN(Node)); 2806 break; 2807 case ISD::FNEG: 2808 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2809 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2810 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2811 Node->getOperand(0)); 2812 Results.push_back(Tmp1); 2813 break; 2814 case ISD::FABS: { 2815 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2816 EVT VT = Node->getValueType(0); 2817 Tmp1 = Node->getOperand(0); 2818 Tmp2 = DAG.getConstantFP(0.0, VT); 2819 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2820 Tmp1, Tmp2, ISD::SETUGT); 2821 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2822 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2823 Results.push_back(Tmp1); 2824 break; 2825 } 2826 case ISD::FSQRT: 2827 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2828 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2829 break; 2830 case ISD::FSIN: 2831 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2832 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2833 break; 2834 case ISD::FCOS: 2835 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2836 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2837 break; 2838 case ISD::FLOG: 2839 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2840 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2841 break; 2842 case ISD::FLOG2: 2843 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2844 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2845 break; 2846 case ISD::FLOG10: 2847 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2848 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2849 break; 2850 case ISD::FEXP: 2851 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2852 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2853 break; 2854 case ISD::FEXP2: 2855 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2856 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2857 break; 2858 case ISD::FTRUNC: 2859 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2860 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2861 break; 2862 case ISD::FFLOOR: 2863 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2864 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2865 break; 2866 case ISD::FCEIL: 2867 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2868 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2869 break; 2870 case ISD::FRINT: 2871 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2872 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2873 break; 2874 case ISD::FNEARBYINT: 2875 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2876 RTLIB::NEARBYINT_F64, 2877 RTLIB::NEARBYINT_F80, 2878 RTLIB::NEARBYINT_PPCF128)); 2879 break; 2880 case ISD::FPOWI: 2881 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2882 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2883 break; 2884 case ISD::FPOW: 2885 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 2886 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 2887 break; 2888 case ISD::FDIV: 2889 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 2890 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 2891 break; 2892 case ISD::FREM: 2893 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 2894 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 2895 break; 2896 case ISD::FP16_TO_FP32: 2897 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 2898 break; 2899 case ISD::FP32_TO_FP16: 2900 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 2901 break; 2902 case ISD::ConstantFP: { 2903 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 2904 // Check to see if this FP immediate is already legal. 2905 // If this is a legal constant, turn it into a TargetConstantFP node. 2906 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 2907 Results.push_back(SDValue(Node, 0)); 2908 else 2909 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 2910 break; 2911 } 2912 case ISD::EHSELECTION: { 2913 unsigned Reg = TLI.getExceptionSelectorRegister(); 2914 assert(Reg && "Can't expand to unknown register!"); 2915 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 2916 Node->getValueType(0))); 2917 Results.push_back(Results[0].getValue(1)); 2918 break; 2919 } 2920 case ISD::EXCEPTIONADDR: { 2921 unsigned Reg = TLI.getExceptionAddressRegister(); 2922 assert(Reg && "Can't expand to unknown register!"); 2923 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 2924 Node->getValueType(0))); 2925 Results.push_back(Results[0].getValue(1)); 2926 break; 2927 } 2928 case ISD::SUB: { 2929 EVT VT = Node->getValueType(0); 2930 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 2931 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 2932 "Don't know how to expand this subtraction!"); 2933 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 2934 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 2935 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 2936 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 2937 break; 2938 } 2939 case ISD::UREM: 2940 case ISD::SREM: { 2941 EVT VT = Node->getValueType(0); 2942 SDVTList VTs = DAG.getVTList(VT, VT); 2943 bool isSigned = Node->getOpcode() == ISD::SREM; 2944 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 2945 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2946 Tmp2 = Node->getOperand(0); 2947 Tmp3 = Node->getOperand(1); 2948 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 2949 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 2950 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 2951 // X % Y -> X-X/Y*Y 2952 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 2953 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 2954 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 2955 } else if (isSigned) { 2956 Tmp1 = ExpandIntLibCall(Node, true, 2957 RTLIB::SREM_I8, 2958 RTLIB::SREM_I16, RTLIB::SREM_I32, 2959 RTLIB::SREM_I64, RTLIB::SREM_I128); 2960 } else { 2961 Tmp1 = ExpandIntLibCall(Node, false, 2962 RTLIB::UREM_I8, 2963 RTLIB::UREM_I16, RTLIB::UREM_I32, 2964 RTLIB::UREM_I64, RTLIB::UREM_I128); 2965 } 2966 Results.push_back(Tmp1); 2967 break; 2968 } 2969 case ISD::UDIV: 2970 case ISD::SDIV: { 2971 bool isSigned = Node->getOpcode() == ISD::SDIV; 2972 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2973 EVT VT = Node->getValueType(0); 2974 SDVTList VTs = DAG.getVTList(VT, VT); 2975 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 2976 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 2977 Node->getOperand(1)); 2978 else if (isSigned) 2979 Tmp1 = ExpandIntLibCall(Node, true, 2980 RTLIB::SDIV_I8, 2981 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 2982 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 2983 else 2984 Tmp1 = ExpandIntLibCall(Node, false, 2985 RTLIB::UDIV_I8, 2986 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 2987 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 2988 Results.push_back(Tmp1); 2989 break; 2990 } 2991 case ISD::MULHU: 2992 case ISD::MULHS: { 2993 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 2994 ISD::SMUL_LOHI; 2995 EVT VT = Node->getValueType(0); 2996 SDVTList VTs = DAG.getVTList(VT, VT); 2997 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 2998 "If this wasn't legal, it shouldn't have been created!"); 2999 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 3000 Node->getOperand(1)); 3001 Results.push_back(Tmp1.getValue(1)); 3002 break; 3003 } 3004 case ISD::MUL: { 3005 EVT VT = Node->getValueType(0); 3006 SDVTList VTs = DAG.getVTList(VT, VT); 3007 // See if multiply or divide can be lowered using two-result operations. 3008 // We just need the low half of the multiply; try both the signed 3009 // and unsigned forms. If the target supports both SMUL_LOHI and 3010 // UMUL_LOHI, form a preference by checking which forms of plain 3011 // MULH it supports. 3012 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 3013 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 3014 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 3015 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 3016 unsigned OpToUse = 0; 3017 if (HasSMUL_LOHI && !HasMULHS) { 3018 OpToUse = ISD::SMUL_LOHI; 3019 } else if (HasUMUL_LOHI && !HasMULHU) { 3020 OpToUse = ISD::UMUL_LOHI; 3021 } else if (HasSMUL_LOHI) { 3022 OpToUse = ISD::SMUL_LOHI; 3023 } else if (HasUMUL_LOHI) { 3024 OpToUse = ISD::UMUL_LOHI; 3025 } 3026 if (OpToUse) { 3027 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 3028 Node->getOperand(1))); 3029 break; 3030 } 3031 Tmp1 = ExpandIntLibCall(Node, false, 3032 RTLIB::MUL_I8, 3033 RTLIB::MUL_I16, RTLIB::MUL_I32, 3034 RTLIB::MUL_I64, RTLIB::MUL_I128); 3035 Results.push_back(Tmp1); 3036 break; 3037 } 3038 case ISD::SADDO: 3039 case ISD::SSUBO: { 3040 SDValue LHS = Node->getOperand(0); 3041 SDValue RHS = Node->getOperand(1); 3042 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 3043 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3044 LHS, RHS); 3045 Results.push_back(Sum); 3046 EVT OType = Node->getValueType(1); 3047 3048 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 3049 3050 // LHSSign -> LHS >= 0 3051 // RHSSign -> RHS >= 0 3052 // SumSign -> Sum >= 0 3053 // 3054 // Add: 3055 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 3056 // Sub: 3057 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 3058 // 3059 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 3060 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 3061 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 3062 Node->getOpcode() == ISD::SADDO ? 3063 ISD::SETEQ : ISD::SETNE); 3064 3065 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 3066 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 3067 3068 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 3069 Results.push_back(Cmp); 3070 break; 3071 } 3072 case ISD::UADDO: 3073 case ISD::USUBO: { 3074 SDValue LHS = Node->getOperand(0); 3075 SDValue RHS = Node->getOperand(1); 3076 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 3077 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3078 LHS, RHS); 3079 Results.push_back(Sum); 3080 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 3081 Node->getOpcode () == ISD::UADDO ? 3082 ISD::SETULT : ISD::SETUGT)); 3083 break; 3084 } 3085 case ISD::UMULO: 3086 case ISD::SMULO: { 3087 EVT VT = Node->getValueType(0); 3088 SDValue LHS = Node->getOperand(0); 3089 SDValue RHS = Node->getOperand(1); 3090 SDValue BottomHalf; 3091 SDValue TopHalf; 3092 static const unsigned Ops[2][3] = 3093 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 3094 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 3095 bool isSigned = Node->getOpcode() == ISD::SMULO; 3096 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 3097 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 3098 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 3099 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 3100 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 3101 RHS); 3102 TopHalf = BottomHalf.getValue(1); 3103 } else { 3104 // FIXME: We should be able to fall back to a libcall with an illegal 3105 // type in some cases. 3106 // Also, we can fall back to a division in some cases, but that's a big 3107 // performance hit in the general case. 3108 assert(TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), 3109 VT.getSizeInBits() * 2)) && 3110 "Don't know how to expand this operation yet!"); 3111 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 3112 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 3113 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 3114 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 3115 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3116 DAG.getIntPtrConstant(0)); 3117 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3118 DAG.getIntPtrConstant(1)); 3119 } 3120 if (isSigned) { 3121 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); 3122 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 3123 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 3124 ISD::SETNE); 3125 } else { 3126 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 3127 DAG.getConstant(0, VT), ISD::SETNE); 3128 } 3129 Results.push_back(BottomHalf); 3130 Results.push_back(TopHalf); 3131 break; 3132 } 3133 case ISD::BUILD_PAIR: { 3134 EVT PairTy = Node->getValueType(0); 3135 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 3136 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 3137 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 3138 DAG.getConstant(PairTy.getSizeInBits()/2, 3139 TLI.getShiftAmountTy())); 3140 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 3141 break; 3142 } 3143 case ISD::SELECT: 3144 Tmp1 = Node->getOperand(0); 3145 Tmp2 = Node->getOperand(1); 3146 Tmp3 = Node->getOperand(2); 3147 if (Tmp1.getOpcode() == ISD::SETCC) { 3148 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 3149 Tmp2, Tmp3, 3150 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 3151 } else { 3152 Tmp1 = DAG.getSelectCC(dl, Tmp1, 3153 DAG.getConstant(0, Tmp1.getValueType()), 3154 Tmp2, Tmp3, ISD::SETNE); 3155 } 3156 Results.push_back(Tmp1); 3157 break; 3158 case ISD::BR_JT: { 3159 SDValue Chain = Node->getOperand(0); 3160 SDValue Table = Node->getOperand(1); 3161 SDValue Index = Node->getOperand(2); 3162 3163 EVT PTy = TLI.getPointerTy(); 3164 3165 const TargetData &TD = *TLI.getTargetData(); 3166 unsigned EntrySize = 3167 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 3168 3169 Index = DAG.getNode(ISD::MUL, dl, PTy, 3170 Index, DAG.getConstant(EntrySize, PTy)); 3171 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 3172 3173 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 3174 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, dl, Chain, Addr, 3175 MachinePointerInfo::getJumpTable(), MemVT, 3176 false, false, 0); 3177 Addr = LD; 3178 if (TM.getRelocationModel() == Reloc::PIC_) { 3179 // For PIC, the sequence is: 3180 // BRIND(load(Jumptable + index) + RelocBase) 3181 // RelocBase can be JumpTable, GOT or some sort of global base. 3182 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 3183 TLI.getPICJumpTableRelocBase(Table, DAG)); 3184 } 3185 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 3186 Results.push_back(Tmp1); 3187 break; 3188 } 3189 case ISD::BRCOND: 3190 // Expand brcond's setcc into its constituent parts and create a BR_CC 3191 // Node. 3192 Tmp1 = Node->getOperand(0); 3193 Tmp2 = Node->getOperand(1); 3194 if (Tmp2.getOpcode() == ISD::SETCC) { 3195 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 3196 Tmp1, Tmp2.getOperand(2), 3197 Tmp2.getOperand(0), Tmp2.getOperand(1), 3198 Node->getOperand(2)); 3199 } else { 3200 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 3201 DAG.getCondCode(ISD::SETNE), Tmp2, 3202 DAG.getConstant(0, Tmp2.getValueType()), 3203 Node->getOperand(2)); 3204 } 3205 Results.push_back(Tmp1); 3206 break; 3207 case ISD::SETCC: { 3208 Tmp1 = Node->getOperand(0); 3209 Tmp2 = Node->getOperand(1); 3210 Tmp3 = Node->getOperand(2); 3211 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 3212 3213 // If we expanded the SETCC into an AND/OR, return the new node 3214 if (Tmp2.getNode() == 0) { 3215 Results.push_back(Tmp1); 3216 break; 3217 } 3218 3219 // Otherwise, SETCC for the given comparison type must be completely 3220 // illegal; expand it into a SELECT_CC. 3221 EVT VT = Node->getValueType(0); 3222 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3223 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 3224 Results.push_back(Tmp1); 3225 break; 3226 } 3227 case ISD::SELECT_CC: { 3228 Tmp1 = Node->getOperand(0); // LHS 3229 Tmp2 = Node->getOperand(1); // RHS 3230 Tmp3 = Node->getOperand(2); // True 3231 Tmp4 = Node->getOperand(3); // False 3232 SDValue CC = Node->getOperand(4); 3233 3234 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 3235 Tmp1, Tmp2, CC, dl); 3236 3237 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 3238 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3239 CC = DAG.getCondCode(ISD::SETNE); 3240 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 3241 Tmp3, Tmp4, CC); 3242 Results.push_back(Tmp1); 3243 break; 3244 } 3245 case ISD::BR_CC: { 3246 Tmp1 = Node->getOperand(0); // Chain 3247 Tmp2 = Node->getOperand(2); // LHS 3248 Tmp3 = Node->getOperand(3); // RHS 3249 Tmp4 = Node->getOperand(1); // CC 3250 3251 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 3252 Tmp2, Tmp3, Tmp4, dl); 3253 LastCALLSEQ_END = DAG.getEntryNode(); 3254 3255 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 3256 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 3257 Tmp4 = DAG.getCondCode(ISD::SETNE); 3258 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 3259 Tmp3, Node->getOperand(4)); 3260 Results.push_back(Tmp1); 3261 break; 3262 } 3263 case ISD::GLOBAL_OFFSET_TABLE: 3264 case ISD::GlobalAddress: 3265 case ISD::GlobalTLSAddress: 3266 case ISD::ExternalSymbol: 3267 case ISD::ConstantPool: 3268 case ISD::JumpTable: 3269 case ISD::INTRINSIC_W_CHAIN: 3270 case ISD::INTRINSIC_WO_CHAIN: 3271 case ISD::INTRINSIC_VOID: 3272 // FIXME: Custom lowering for these operations shouldn't return null! 3273 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3274 Results.push_back(SDValue(Node, i)); 3275 break; 3276 } 3277} 3278void SelectionDAGLegalize::PromoteNode(SDNode *Node, 3279 SmallVectorImpl<SDValue> &Results) { 3280 EVT OVT = Node->getValueType(0); 3281 if (Node->getOpcode() == ISD::UINT_TO_FP || 3282 Node->getOpcode() == ISD::SINT_TO_FP || 3283 Node->getOpcode() == ISD::SETCC) { 3284 OVT = Node->getOperand(0).getValueType(); 3285 } 3286 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3287 DebugLoc dl = Node->getDebugLoc(); 3288 SDValue Tmp1, Tmp2, Tmp3; 3289 switch (Node->getOpcode()) { 3290 case ISD::CTTZ: 3291 case ISD::CTLZ: 3292 case ISD::CTPOP: 3293 // Zero extend the argument. 3294 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3295 // Perform the larger operation. 3296 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3297 if (Node->getOpcode() == ISD::CTTZ) { 3298 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3299 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 3300 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3301 ISD::SETEQ); 3302 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3303 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3304 } else if (Node->getOpcode() == ISD::CTLZ) { 3305 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3306 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3307 DAG.getConstant(NVT.getSizeInBits() - 3308 OVT.getSizeInBits(), NVT)); 3309 } 3310 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3311 break; 3312 case ISD::BSWAP: { 3313 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3314 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3315 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3316 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3317 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3318 Results.push_back(Tmp1); 3319 break; 3320 } 3321 case ISD::FP_TO_UINT: 3322 case ISD::FP_TO_SINT: 3323 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3324 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3325 Results.push_back(Tmp1); 3326 break; 3327 case ISD::UINT_TO_FP: 3328 case ISD::SINT_TO_FP: 3329 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3330 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3331 Results.push_back(Tmp1); 3332 break; 3333 case ISD::AND: 3334 case ISD::OR: 3335 case ISD::XOR: { 3336 unsigned ExtOp, TruncOp; 3337 if (OVT.isVector()) { 3338 ExtOp = ISD::BIT_CONVERT; 3339 TruncOp = ISD::BIT_CONVERT; 3340 } else { 3341 assert(OVT.isInteger() && "Cannot promote logic operation"); 3342 ExtOp = ISD::ANY_EXTEND; 3343 TruncOp = ISD::TRUNCATE; 3344 } 3345 // Promote each of the values to the new type. 3346 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3347 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3348 // Perform the larger operation, then convert back 3349 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3350 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3351 break; 3352 } 3353 case ISD::SELECT: { 3354 unsigned ExtOp, TruncOp; 3355 if (Node->getValueType(0).isVector()) { 3356 ExtOp = ISD::BIT_CONVERT; 3357 TruncOp = ISD::BIT_CONVERT; 3358 } else if (Node->getValueType(0).isInteger()) { 3359 ExtOp = ISD::ANY_EXTEND; 3360 TruncOp = ISD::TRUNCATE; 3361 } else { 3362 ExtOp = ISD::FP_EXTEND; 3363 TruncOp = ISD::FP_ROUND; 3364 } 3365 Tmp1 = Node->getOperand(0); 3366 // Promote each of the values to the new type. 3367 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3368 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3369 // Perform the larger operation, then round down. 3370 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3371 if (TruncOp != ISD::FP_ROUND) 3372 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3373 else 3374 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3375 DAG.getIntPtrConstant(0)); 3376 Results.push_back(Tmp1); 3377 break; 3378 } 3379 case ISD::VECTOR_SHUFFLE: { 3380 SmallVector<int, 8> Mask; 3381 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3382 3383 // Cast the two input vectors. 3384 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3385 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3386 3387 // Convert the shuffle mask to the right # elements. 3388 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3389 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); 3390 Results.push_back(Tmp1); 3391 break; 3392 } 3393 case ISD::SETCC: { 3394 unsigned ExtOp = ISD::FP_EXTEND; 3395 if (NVT.isInteger()) { 3396 ISD::CondCode CCCode = 3397 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3398 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3399 } 3400 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3401 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3402 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3403 Tmp1, Tmp2, Node->getOperand(2))); 3404 break; 3405 } 3406 } 3407} 3408 3409// SelectionDAG::Legalize - This is the entry point for the file. 3410// 3411void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) { 3412 /// run - This is the main entry point to this class. 3413 /// 3414 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3415} 3416 3417