LegalizeDAG.cpp revision 3d9dffc5863d0319aa9c5cb156045ae6778cba01
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineConstantPool.h" 16#include "llvm/CodeGen/MachineFunction.h" 17#include "llvm/CodeGen/MachineFrameInfo.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/Constants.h" 22#include <iostream> 23using namespace llvm; 24 25//===----------------------------------------------------------------------===// 26/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 27/// hacks on it until the target machine can handle it. This involves 28/// eliminating value sizes the machine cannot handle (promoting small sizes to 29/// large sizes or splitting up large values into small values) as well as 30/// eliminating operations the machine cannot handle. 31/// 32/// This code also does a small amount of optimization and recognition of idioms 33/// as part of its processing. For example, if a target does not support a 34/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 35/// will attempt merge setcc and brc instructions into brcc's. 36/// 37namespace { 38class SelectionDAGLegalize { 39 TargetLowering &TLI; 40 SelectionDAG &DAG; 41 42 /// LegalizeAction - This enum indicates what action we should take for each 43 /// value type the can occur in the program. 44 enum LegalizeAction { 45 Legal, // The target natively supports this value type. 46 Promote, // This should be promoted to the next larger type. 47 Expand, // This integer type should be broken into smaller pieces. 48 }; 49 50 /// ValueTypeActions - This is a bitvector that contains two bits for each 51 /// value type, where the two bits correspond to the LegalizeAction enum. 52 /// This can be queried with "getTypeAction(VT)". 53 unsigned ValueTypeActions; 54 55 /// NeedsAnotherIteration - This is set when we expand a large integer 56 /// operation into smaller integer operations, but the smaller operations are 57 /// not set. This occurs only rarely in practice, for targets that don't have 58 /// 32-bit or larger integer registers. 59 bool NeedsAnotherIteration; 60 61 /// LegalizedNodes - For nodes that are of legal width, and that have more 62 /// than one use, this map indicates what regularized operand to use. This 63 /// allows us to avoid legalizing the same thing more than once. 64 std::map<SDOperand, SDOperand> LegalizedNodes; 65 66 /// PromotedNodes - For nodes that are below legal width, and that have more 67 /// than one use, this map indicates what promoted value to use. This allows 68 /// us to avoid promoting the same thing more than once. 69 std::map<SDOperand, SDOperand> PromotedNodes; 70 71 /// ExpandedNodes - For nodes that need to be expanded, and which have more 72 /// than one use, this map indicates which which operands are the expanded 73 /// version of the input. This allows us to avoid expanding the same node 74 /// more than once. 75 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 76 77 void AddLegalizedOperand(SDOperand From, SDOperand To) { 78 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second; 79 assert(isNew && "Got into the map somehow?"); 80 } 81 void AddPromotedOperand(SDOperand From, SDOperand To) { 82 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 83 assert(isNew && "Got into the map somehow?"); 84 } 85 86public: 87 88 SelectionDAGLegalize(TargetLowering &TLI, SelectionDAG &DAG); 89 90 /// Run - While there is still lowering to do, perform a pass over the DAG. 91 /// Most regularization can be done in a single pass, but targets that require 92 /// large values to be split into registers multiple times (e.g. i64 -> 4x 93 /// i16) require iteration for these values (the first iteration will demote 94 /// to i32, the second will demote to i16). 95 void Run() { 96 do { 97 NeedsAnotherIteration = false; 98 LegalizeDAG(); 99 } while (NeedsAnotherIteration); 100 } 101 102 /// getTypeAction - Return how we should legalize values of this type, either 103 /// it is already legal or we need to expand it into multiple registers of 104 /// smaller integer type, or we need to promote it to a larger type. 105 LegalizeAction getTypeAction(MVT::ValueType VT) const { 106 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 107 } 108 109 /// isTypeLegal - Return true if this type is legal on this target. 110 /// 111 bool isTypeLegal(MVT::ValueType VT) const { 112 return getTypeAction(VT) == Legal; 113 } 114 115private: 116 void LegalizeDAG(); 117 118 SDOperand LegalizeOp(SDOperand O); 119 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 120 SDOperand PromoteOp(SDOperand O); 121 122 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 123 SDOperand &Lo, SDOperand &Hi); 124 125 SDOperand getIntPtrConstant(uint64_t Val) { 126 return DAG.getConstant(Val, TLI.getPointerTy()); 127 } 128}; 129} 130 131 132SelectionDAGLegalize::SelectionDAGLegalize(TargetLowering &tli, 133 SelectionDAG &dag) 134 : TLI(tli), DAG(dag), ValueTypeActions(TLI.getValueTypeActions()) { 135 assert(MVT::LAST_VALUETYPE <= 16 && 136 "Too many value types for ValueTypeActions to hold!"); 137} 138 139void SelectionDAGLegalize::LegalizeDAG() { 140 SDOperand OldRoot = DAG.getRoot(); 141 SDOperand NewRoot = LegalizeOp(OldRoot); 142 DAG.setRoot(NewRoot); 143 144 ExpandedNodes.clear(); 145 LegalizedNodes.clear(); 146 PromotedNodes.clear(); 147 148 // Remove dead nodes now. 149 DAG.RemoveDeadNodes(OldRoot.Val); 150} 151 152SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 153 assert(getTypeAction(Op.getValueType()) == Legal && 154 "Caller should expand or promote operands that are not legal!"); 155 156 // If this operation defines any values that cannot be represented in a 157 // register on this target, make sure to expand or promote them. 158 if (Op.Val->getNumValues() > 1) { 159 for (unsigned i = 0, e = Op.Val->getNumValues(); i != e; ++i) 160 switch (getTypeAction(Op.Val->getValueType(i))) { 161 case Legal: break; // Nothing to do. 162 case Expand: { 163 SDOperand T1, T2; 164 ExpandOp(Op.getValue(i), T1, T2); 165 assert(LegalizedNodes.count(Op) && 166 "Expansion didn't add legal operands!"); 167 return LegalizedNodes[Op]; 168 } 169 case Promote: 170 PromoteOp(Op.getValue(i)); 171 assert(LegalizedNodes.count(Op) && 172 "Expansion didn't add legal operands!"); 173 return LegalizedNodes[Op]; 174 } 175 } 176 177 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 178 if (I != LegalizedNodes.end()) return I->second; 179 180 SDOperand Tmp1, Tmp2, Tmp3; 181 182 SDOperand Result = Op; 183 SDNode *Node = Op.Val; 184 185 switch (Node->getOpcode()) { 186 default: 187 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 188 assert(0 && "Do not know how to legalize this operator!"); 189 abort(); 190 case ISD::EntryToken: 191 case ISD::FrameIndex: 192 case ISD::GlobalAddress: 193 case ISD::ExternalSymbol: 194 case ISD::ConstantPool: // Nothing to do. 195 assert(getTypeAction(Node->getValueType(0)) == Legal && 196 "This must be legal!"); 197 break; 198 case ISD::CopyFromReg: 199 Tmp1 = LegalizeOp(Node->getOperand(0)); 200 if (Tmp1 != Node->getOperand(0)) 201 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), 202 Node->getValueType(0), Tmp1); 203 break; 204 case ISD::ImplicitDef: 205 Tmp1 = LegalizeOp(Node->getOperand(0)); 206 if (Tmp1 != Node->getOperand(0)) 207 Result = DAG.getImplicitDef(Tmp1, cast<RegSDNode>(Node)->getReg()); 208 break; 209 case ISD::Constant: 210 // We know we don't need to expand constants here, constants only have one 211 // value and we check that it is fine above. 212 213 // FIXME: Maybe we should handle things like targets that don't support full 214 // 32-bit immediates? 215 break; 216 case ISD::ConstantFP: { 217 // Spill FP immediates to the constant pool if the target cannot directly 218 // codegen them. Targets often have some immediate values that can be 219 // efficiently generated into an FP register without a load. We explicitly 220 // leave these constants as ConstantFP nodes for the target to deal with. 221 222 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 223 224 // Check to see if this FP immediate is already legal. 225 bool isLegal = false; 226 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 227 E = TLI.legal_fpimm_end(); I != E; ++I) 228 if (CFP->isExactlyValue(*I)) { 229 isLegal = true; 230 break; 231 } 232 233 if (!isLegal) { 234 // Otherwise we need to spill the constant to memory. 235 MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool(); 236 237 bool Extend = false; 238 239 // If a FP immediate is precise when represented as a float, we put it 240 // into the constant pool as a float, even if it's is statically typed 241 // as a double. 242 MVT::ValueType VT = CFP->getValueType(0); 243 bool isDouble = VT == MVT::f64; 244 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 245 Type::FloatTy, CFP->getValue()); 246 if (isDouble && CFP->isExactlyValue((float)CFP->getValue())) { 247 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 248 VT = MVT::f32; 249 Extend = true; 250 } 251 252 SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(LLVMC), 253 TLI.getPointerTy()); 254 if (Extend) { 255 Result = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), CPIdx, 256 MVT::f32); 257 } else { 258 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx); 259 } 260 } 261 break; 262 } 263 case ISD::TokenFactor: { 264 std::vector<SDOperand> Ops; 265 bool Changed = false; 266 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 267 SDOperand Op = Node->getOperand(i); 268 // Fold single-use TokenFactor nodes into this token factor as we go. 269 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 270 Changed = true; 271 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 272 Ops.push_back(LegalizeOp(Op.getOperand(j))); 273 } else { 274 Ops.push_back(LegalizeOp(Op)); // Legalize the operands 275 Changed |= Ops[i] != Op; 276 } 277 } 278 if (Changed) 279 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 280 break; 281 } 282 283 case ISD::ADJCALLSTACKDOWN: 284 case ISD::ADJCALLSTACKUP: 285 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 286 // There is no need to legalize the size argument (Operand #1) 287 if (Tmp1 != Node->getOperand(0)) 288 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 289 Node->getOperand(1)); 290 break; 291 case ISD::DYNAMIC_STACKALLOC: 292 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 293 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 294 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 295 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 296 Tmp3 != Node->getOperand(2)) 297 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, Node->getValueType(0), 298 Tmp1, Tmp2, Tmp3); 299 else 300 Result = Op.getValue(0); 301 302 // Since this op produces two values, make sure to remember that we 303 // legalized both of them. 304 AddLegalizedOperand(SDOperand(Node, 0), Result); 305 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 306 return Result.getValue(Op.ResNo); 307 308 case ISD::CALL: { 309 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 310 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 311 312 bool Changed = false; 313 std::vector<SDOperand> Ops; 314 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 315 Ops.push_back(LegalizeOp(Node->getOperand(i))); 316 Changed |= Ops.back() != Node->getOperand(i); 317 } 318 319 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 320 std::vector<MVT::ValueType> RetTyVTs; 321 RetTyVTs.reserve(Node->getNumValues()); 322 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 323 RetTyVTs.push_back(Node->getValueType(i)); 324 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops), 0); 325 } else { 326 Result = Result.getValue(0); 327 } 328 // Since calls produce multiple values, make sure to remember that we 329 // legalized all of them. 330 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 331 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 332 return Result.getValue(Op.ResNo); 333 } 334 case ISD::BR: 335 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 336 if (Tmp1 != Node->getOperand(0)) 337 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 338 break; 339 340 case ISD::BRCOND: 341 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 342 343 switch (getTypeAction(Node->getOperand(1).getValueType())) { 344 case Expand: assert(0 && "It's impossible to expand bools"); 345 case Legal: 346 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 347 break; 348 case Promote: 349 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 350 break; 351 } 352 // Basic block destination (Op#2) is always legal. 353 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 354 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 355 Node->getOperand(2)); 356 break; 357 358 case ISD::LOAD: 359 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 360 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 361 if (Tmp1 != Node->getOperand(0) || 362 Tmp2 != Node->getOperand(1)) 363 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2); 364 else 365 Result = SDOperand(Node, 0); 366 367 // Since loads produce two values, make sure to remember that we legalized 368 // both of them. 369 AddLegalizedOperand(SDOperand(Node, 0), Result); 370 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 371 return Result.getValue(Op.ResNo); 372 373 case ISD::EXTLOAD: 374 case ISD::SEXTLOAD: 375 case ISD::ZEXTLOAD: 376 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 377 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 378 if (Tmp1 != Node->getOperand(0) || 379 Tmp2 != Node->getOperand(1)) 380 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2, 381 cast<MVTSDNode>(Node)->getExtraValueType()); 382 else 383 Result = SDOperand(Node, 0); 384 385 // Since loads produce two values, make sure to remember that we legalized 386 // both of them. 387 AddLegalizedOperand(SDOperand(Node, 0), Result); 388 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 389 return Result.getValue(Op.ResNo); 390 391 case ISD::EXTRACT_ELEMENT: 392 // Get both the low and high parts. 393 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 394 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 395 Result = Tmp2; // 1 -> Hi 396 else 397 Result = Tmp1; // 0 -> Lo 398 break; 399 400 case ISD::CopyToReg: 401 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 402 403 switch (getTypeAction(Node->getOperand(1).getValueType())) { 404 case Legal: 405 // Legalize the incoming value (must be legal). 406 Tmp2 = LegalizeOp(Node->getOperand(1)); 407 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 408 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg()); 409 break; 410 case Promote: 411 Tmp2 = PromoteOp(Node->getOperand(1)); 412 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg()); 413 break; 414 case Expand: 415 SDOperand Lo, Hi; 416 ExpandOp(Node->getOperand(1), Lo, Hi); 417 unsigned Reg = cast<RegSDNode>(Node)->getReg(); 418 Lo = DAG.getCopyToReg(Tmp1, Lo, Reg); 419 Hi = DAG.getCopyToReg(Tmp1, Hi, Reg+1); 420 // Note that the copytoreg nodes are independent of each other. 421 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 422 assert(isTypeLegal(Result.getValueType()) && 423 "Cannot expand multiple times yet (i64 -> i16)"); 424 break; 425 } 426 break; 427 428 case ISD::RET: 429 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 430 switch (Node->getNumOperands()) { 431 case 2: // ret val 432 switch (getTypeAction(Node->getOperand(1).getValueType())) { 433 case Legal: 434 Tmp2 = LegalizeOp(Node->getOperand(1)); 435 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 436 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 437 break; 438 case Expand: { 439 SDOperand Lo, Hi; 440 ExpandOp(Node->getOperand(1), Lo, Hi); 441 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 442 break; 443 } 444 case Promote: 445 Tmp2 = PromoteOp(Node->getOperand(1)); 446 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 447 break; 448 } 449 break; 450 case 1: // ret void 451 if (Tmp1 != Node->getOperand(0)) 452 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 453 break; 454 default: { // ret <values> 455 std::vector<SDOperand> NewValues; 456 NewValues.push_back(Tmp1); 457 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 458 switch (getTypeAction(Node->getOperand(i).getValueType())) { 459 case Legal: 460 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 461 break; 462 case Expand: { 463 SDOperand Lo, Hi; 464 ExpandOp(Node->getOperand(i), Lo, Hi); 465 NewValues.push_back(Lo); 466 NewValues.push_back(Hi); 467 break; 468 } 469 case Promote: 470 assert(0 && "Can't promote multiple return value yet!"); 471 } 472 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 473 break; 474 } 475 } 476 break; 477 case ISD::STORE: 478 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 479 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 480 481 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 482 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 483 if (CFP->getValueType(0) == MVT::f32) { 484 union { 485 unsigned I; 486 float F; 487 } V; 488 V.F = CFP->getValue(); 489 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 490 DAG.getConstant(V.I, MVT::i32), Tmp2); 491 } else { 492 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 493 union { 494 uint64_t I; 495 double F; 496 } V; 497 V.F = CFP->getValue(); 498 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 499 DAG.getConstant(V.I, MVT::i64), Tmp2); 500 } 501 Op = Result; 502 Node = Op.Val; 503 } 504 505 switch (getTypeAction(Node->getOperand(1).getValueType())) { 506 case Legal: { 507 SDOperand Val = LegalizeOp(Node->getOperand(1)); 508 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 509 Tmp2 != Node->getOperand(2)) 510 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2); 511 break; 512 } 513 case Promote: 514 // Truncate the value and store the result. 515 Tmp3 = PromoteOp(Node->getOperand(1)); 516 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 517 Node->getOperand(1).getValueType()); 518 break; 519 520 case Expand: 521 SDOperand Lo, Hi; 522 ExpandOp(Node->getOperand(1), Lo, Hi); 523 524 if (!TLI.isLittleEndian()) 525 std::swap(Lo, Hi); 526 527 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2); 528 529 unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 530 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 531 getIntPtrConstant(IncrementSize)); 532 assert(isTypeLegal(Tmp2.getValueType()) && 533 "Pointers must be legal!"); 534 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2); 535 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 536 break; 537 } 538 break; 539 case ISD::TRUNCSTORE: 540 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 541 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 542 543 switch (getTypeAction(Node->getOperand(1).getValueType())) { 544 case Legal: 545 Tmp2 = LegalizeOp(Node->getOperand(1)); 546 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 547 Tmp3 != Node->getOperand(2)) 548 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 549 cast<MVTSDNode>(Node)->getExtraValueType()); 550 break; 551 case Promote: 552 case Expand: 553 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 554 } 555 break; 556 case ISD::SELECT: 557 switch (getTypeAction(Node->getOperand(0).getValueType())) { 558 case Expand: assert(0 && "It's impossible to expand bools"); 559 case Legal: 560 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 561 break; 562 case Promote: 563 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 564 break; 565 } 566 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 567 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 568 569 switch (TLI.getOperationAction(Node->getOpcode(), Tmp2.getValueType())) { 570 default: assert(0 && "This action is not supported yet!"); 571 case TargetLowering::Legal: 572 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 573 Tmp3 != Node->getOperand(2)) 574 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 575 Tmp1, Tmp2, Tmp3); 576 break; 577 case TargetLowering::Promote: { 578 MVT::ValueType NVT = 579 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 580 unsigned ExtOp, TruncOp; 581 if (MVT::isInteger(Tmp2.getValueType())) { 582 ExtOp = ISD::ZERO_EXTEND; 583 TruncOp = ISD::TRUNCATE; 584 } else { 585 ExtOp = ISD::FP_EXTEND; 586 TruncOp = ISD::FP_ROUND; 587 } 588 // Promote each of the values to the new type. 589 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 590 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 591 // Perform the larger operation, then round down. 592 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 593 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 594 break; 595 } 596 } 597 break; 598 case ISD::SETCC: 599 switch (getTypeAction(Node->getOperand(0).getValueType())) { 600 case Legal: 601 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 602 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 603 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 604 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 605 Node->getValueType(0), Tmp1, Tmp2); 606 break; 607 case Promote: 608 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 609 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 610 611 // If this is an FP compare, the operands have already been extended. 612 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 613 MVT::ValueType VT = Node->getOperand(0).getValueType(); 614 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 615 616 // Otherwise, we have to insert explicit sign or zero extends. Note 617 // that we could insert sign extends for ALL conditions, but zero extend 618 // is cheaper on many machines (an AND instead of two shifts), so prefer 619 // it. 620 switch (cast<SetCCSDNode>(Node)->getCondition()) { 621 default: assert(0 && "Unknown integer comparison!"); 622 case ISD::SETEQ: 623 case ISD::SETNE: 624 case ISD::SETUGE: 625 case ISD::SETUGT: 626 case ISD::SETULE: 627 case ISD::SETULT: 628 // ALL of these operations will work if we either sign or zero extend 629 // the operands (including the unsigned comparisons!). Zero extend is 630 // usually a simpler/cheaper operation, so prefer it. 631 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp1, VT); 632 Tmp2 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp2, VT); 633 break; 634 case ISD::SETGE: 635 case ISD::SETGT: 636 case ISD::SETLT: 637 case ISD::SETLE: 638 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 639 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT); 640 break; 641 } 642 643 } 644 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 645 Node->getValueType(0), Tmp1, Tmp2); 646 break; 647 case Expand: 648 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 649 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 650 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 651 switch (cast<SetCCSDNode>(Node)->getCondition()) { 652 case ISD::SETEQ: 653 case ISD::SETNE: 654 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 655 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 656 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 657 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 658 Node->getValueType(0), Tmp1, 659 DAG.getConstant(0, Tmp1.getValueType())); 660 break; 661 default: 662 // FIXME: This generated code sucks. 663 ISD::CondCode LowCC; 664 switch (cast<SetCCSDNode>(Node)->getCondition()) { 665 default: assert(0 && "Unknown integer setcc!"); 666 case ISD::SETLT: 667 case ISD::SETULT: LowCC = ISD::SETULT; break; 668 case ISD::SETGT: 669 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 670 case ISD::SETLE: 671 case ISD::SETULE: LowCC = ISD::SETULE; break; 672 case ISD::SETGE: 673 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 674 } 675 676 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 677 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 678 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 679 680 // NOTE: on targets without efficient SELECT of bools, we can always use 681 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 682 Tmp1 = DAG.getSetCC(LowCC, Node->getValueType(0), LHSLo, RHSLo); 683 Tmp2 = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 684 Node->getValueType(0), LHSHi, RHSHi); 685 Result = DAG.getSetCC(ISD::SETEQ, Node->getValueType(0), LHSHi, RHSHi); 686 Result = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 687 Result, Tmp1, Tmp2); 688 break; 689 } 690 } 691 break; 692 693 case ISD::MEMSET: 694 case ISD::MEMCPY: 695 case ISD::MEMMOVE: { 696 Tmp1 = LegalizeOp(Node->getOperand(0)); 697 Tmp2 = LegalizeOp(Node->getOperand(1)); 698 Tmp3 = LegalizeOp(Node->getOperand(2)); 699 SDOperand Tmp4 = LegalizeOp(Node->getOperand(3)); 700 SDOperand Tmp5 = LegalizeOp(Node->getOperand(4)); 701 702 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 703 default: assert(0 && "This action not implemented for this operation!"); 704 case TargetLowering::Legal: 705 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 706 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 707 Tmp5 != Node->getOperand(4)) { 708 std::vector<SDOperand> Ops; 709 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 710 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 711 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 712 } 713 break; 714 case TargetLowering::Expand: { 715 // Otherwise, the target does not support this operation. Lower the 716 // operation to an explicit libcall as appropriate. 717 MVT::ValueType IntPtr = TLI.getPointerTy(); 718 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 719 std::vector<std::pair<SDOperand, const Type*> > Args; 720 721 const char *FnName = 0; 722 if (Node->getOpcode() == ISD::MEMSET) { 723 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 724 // Extend the ubyte argument to be an int value for the call. 725 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 726 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 727 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 728 729 FnName = "memset"; 730 } else if (Node->getOpcode() == ISD::MEMCPY || 731 Node->getOpcode() == ISD::MEMMOVE) { 732 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 733 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 734 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 735 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 736 } else { 737 assert(0 && "Unknown op!"); 738 } 739 std::pair<SDOperand,SDOperand> CallResult = 740 TLI.LowerCallTo(Tmp1, Type::VoidTy, 741 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 742 Result = LegalizeOp(CallResult.second); 743 break; 744 } 745 case TargetLowering::Custom: 746 std::vector<SDOperand> Ops; 747 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 748 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 749 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 750 Result = TLI.LowerOperation(Result); 751 Result = LegalizeOp(Result); 752 break; 753 } 754 break; 755 } 756 case ISD::ADD: 757 case ISD::SUB: 758 case ISD::MUL: 759 case ISD::UDIV: 760 case ISD::SDIV: 761 case ISD::UREM: 762 case ISD::SREM: 763 case ISD::AND: 764 case ISD::OR: 765 case ISD::XOR: 766 case ISD::SHL: 767 case ISD::SRL: 768 case ISD::SRA: 769 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 770 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 771 if (Tmp1 != Node->getOperand(0) || 772 Tmp2 != Node->getOperand(1)) 773 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 774 break; 775 case ISD::ZERO_EXTEND: 776 case ISD::SIGN_EXTEND: 777 case ISD::TRUNCATE: 778 case ISD::FP_EXTEND: 779 case ISD::FP_ROUND: 780 case ISD::FP_TO_SINT: 781 case ISD::FP_TO_UINT: 782 case ISD::SINT_TO_FP: 783 case ISD::UINT_TO_FP: 784 switch (getTypeAction(Node->getOperand(0).getValueType())) { 785 case Legal: 786 Tmp1 = LegalizeOp(Node->getOperand(0)); 787 if (Tmp1 != Node->getOperand(0)) 788 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 789 break; 790 case Expand: 791 assert(Node->getOpcode() != ISD::SINT_TO_FP && 792 Node->getOpcode() != ISD::UINT_TO_FP && 793 "Cannot lower Xint_to_fp to a call yet!"); 794 795 // In the expand case, we must be dealing with a truncate, because 796 // otherwise the result would be larger than the source. 797 assert(Node->getOpcode() == ISD::TRUNCATE && 798 "Shouldn't need to expand other operators here!"); 799 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 800 801 // Since the result is legal, we should just be able to truncate the low 802 // part of the source. 803 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 804 break; 805 806 case Promote: 807 switch (Node->getOpcode()) { 808 case ISD::ZERO_EXTEND: 809 Result = PromoteOp(Node->getOperand(0)); 810 // NOTE: Any extend would work here... 811 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result); 812 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Op.getValueType(), 813 Result, Node->getOperand(0).getValueType()); 814 break; 815 case ISD::SIGN_EXTEND: 816 Result = PromoteOp(Node->getOperand(0)); 817 // NOTE: Any extend would work here... 818 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result); 819 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 820 Result, Node->getOperand(0).getValueType()); 821 break; 822 case ISD::TRUNCATE: 823 Result = PromoteOp(Node->getOperand(0)); 824 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 825 break; 826 case ISD::FP_EXTEND: 827 Result = PromoteOp(Node->getOperand(0)); 828 if (Result.getValueType() != Op.getValueType()) 829 // Dynamically dead while we have only 2 FP types. 830 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 831 break; 832 case ISD::FP_ROUND: 833 case ISD::FP_TO_SINT: 834 case ISD::FP_TO_UINT: 835 Result = PromoteOp(Node->getOperand(0)); 836 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 837 break; 838 case ISD::SINT_TO_FP: 839 Result = PromoteOp(Node->getOperand(0)); 840 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 841 Result, Node->getOperand(0).getValueType()); 842 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 843 break; 844 case ISD::UINT_TO_FP: 845 Result = PromoteOp(Node->getOperand(0)); 846 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Result.getValueType(), 847 Result, Node->getOperand(0).getValueType()); 848 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 849 break; 850 } 851 } 852 break; 853 case ISD::FP_ROUND_INREG: 854 case ISD::SIGN_EXTEND_INREG: 855 case ISD::ZERO_EXTEND_INREG: { 856 Tmp1 = LegalizeOp(Node->getOperand(0)); 857 MVT::ValueType ExtraVT = cast<MVTSDNode>(Node)->getExtraValueType(); 858 859 // If this operation is not supported, convert it to a shl/shr or load/store 860 // pair. 861 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 862 default: assert(0 && "This action not supported for this op yet!"); 863 case TargetLowering::Legal: 864 if (Tmp1 != Node->getOperand(0)) 865 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 866 ExtraVT); 867 break; 868 case TargetLowering::Expand: 869 // If this is an integer extend and shifts are supported, do that. 870 if (Node->getOpcode() == ISD::ZERO_EXTEND_INREG) { 871 // NOTE: we could fall back on load/store here too for targets without 872 // AND. However, it is doubtful that any exist. 873 // AND out the appropriate bits. 874 SDOperand Mask = 875 DAG.getConstant((1ULL << MVT::getSizeInBits(ExtraVT))-1, 876 Node->getValueType(0)); 877 Result = DAG.getNode(ISD::AND, Node->getValueType(0), 878 Node->getOperand(0), Mask); 879 } else if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 880 // NOTE: we could fall back on load/store here too for targets without 881 // SAR. However, it is doubtful that any exist. 882 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 883 MVT::getSizeInBits(ExtraVT); 884 SDOperand ShiftCst = DAG.getConstant(BitsDiff, MVT::i8); 885 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 886 Node->getOperand(0), ShiftCst); 887 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 888 Result, ShiftCst); 889 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 890 // The only way we can lower this is to turn it into a STORETRUNC, 891 // EXTLOAD pair, targetting a temporary location (a stack slot). 892 893 // NOTE: there is a choice here between constantly creating new stack 894 // slots and always reusing the same one. We currently always create 895 // new ones, as reuse may inhibit scheduling. 896 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 897 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 898 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 899 MachineFunction &MF = DAG.getMachineFunction(); 900 int SSFI = 901 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 902 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 903 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 904 Node->getOperand(0), StackSlot, ExtraVT); 905 Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0), 906 Result, StackSlot, ExtraVT); 907 } else { 908 assert(0 && "Unknown op"); 909 } 910 Result = LegalizeOp(Result); 911 break; 912 } 913 break; 914 } 915 } 916 917 if (!Op.Val->hasOneUse()) 918 AddLegalizedOperand(Op, Result); 919 920 return Result; 921} 922 923/// PromoteOp - Given an operation that produces a value in an invalid type, 924/// promote it to compute the value into a larger type. The produced value will 925/// have the correct bits for the low portion of the register, but no guarantee 926/// is made about the top bits: it may be zero, sign-extended, or garbage. 927SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 928 MVT::ValueType VT = Op.getValueType(); 929 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 930 assert(getTypeAction(VT) == Promote && 931 "Caller should expand or legalize operands that are not promotable!"); 932 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 933 "Cannot promote to smaller type!"); 934 935 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 936 if (I != PromotedNodes.end()) return I->second; 937 938 SDOperand Tmp1, Tmp2, Tmp3; 939 940 SDOperand Result; 941 SDNode *Node = Op.Val; 942 943 // Promotion needs an optimization step to clean up after it, and is not 944 // careful to avoid operations the target does not support. Make sure that 945 // all generated operations are legalized in the next iteration. 946 NeedsAnotherIteration = true; 947 948 switch (Node->getOpcode()) { 949 default: 950 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 951 assert(0 && "Do not know how to promote this operator!"); 952 abort(); 953 case ISD::Constant: 954 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 955 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 956 break; 957 case ISD::ConstantFP: 958 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 959 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 960 break; 961 case ISD::CopyFromReg: 962 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), NVT, 963 Node->getOperand(0)); 964 // Remember that we legalized the chain. 965 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 966 break; 967 968 case ISD::SETCC: 969 assert(getTypeAction(TLI.getSetCCResultTy()) == Legal && 970 "SetCC type is not legal??"); 971 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 972 TLI.getSetCCResultTy(), Node->getOperand(0), 973 Node->getOperand(1)); 974 Result = LegalizeOp(Result); 975 break; 976 977 case ISD::TRUNCATE: 978 switch (getTypeAction(Node->getOperand(0).getValueType())) { 979 case Legal: 980 Result = LegalizeOp(Node->getOperand(0)); 981 assert(Result.getValueType() >= NVT && 982 "This truncation doesn't make sense!"); 983 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 984 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 985 break; 986 case Expand: 987 assert(0 && "Cannot handle expand yet"); 988 case Promote: 989 assert(0 && "Cannot handle promote-promote yet"); 990 } 991 break; 992 case ISD::SIGN_EXTEND: 993 case ISD::ZERO_EXTEND: 994 switch (getTypeAction(Node->getOperand(0).getValueType())) { 995 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 996 case Legal: 997 // Input is legal? Just do extend all the way to the larger type. 998 Result = LegalizeOp(Node->getOperand(0)); 999 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 1000 break; 1001 case Promote: 1002 // Promote the reg if it's smaller. 1003 Result = PromoteOp(Node->getOperand(0)); 1004 // The high bits are not guaranteed to be anything. Insert an extend. 1005 if (Node->getOpcode() == ISD::SIGN_EXTEND) 1006 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, VT); 1007 else 1008 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Result, VT); 1009 break; 1010 } 1011 break; 1012 1013 case ISD::FP_EXTEND: 1014 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 1015 case ISD::FP_ROUND: 1016 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1017 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 1018 case Promote: assert(0 && "Unreachable with 2 FP types!"); 1019 case Legal: 1020 // Input is legal? Do an FP_ROUND_INREG. 1021 Result = LegalizeOp(Node->getOperand(0)); 1022 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1023 break; 1024 } 1025 break; 1026 1027 case ISD::SINT_TO_FP: 1028 case ISD::UINT_TO_FP: 1029 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1030 case Legal: 1031 Result = LegalizeOp(Node->getOperand(0)); 1032 break; 1033 1034 case Promote: 1035 Result = PromoteOp(Node->getOperand(0)); 1036 if (Node->getOpcode() == ISD::SINT_TO_FP) 1037 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1038 Result, Node->getOperand(0).getValueType()); 1039 else 1040 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Result.getValueType(), 1041 Result, Node->getOperand(0).getValueType()); 1042 break; 1043 case Expand: 1044 assert(0 && "Unimplemented"); 1045 } 1046 // No extra round required here. 1047 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 1048 break; 1049 1050 case ISD::FP_TO_SINT: 1051 case ISD::FP_TO_UINT: 1052 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1053 case Legal: 1054 Tmp1 = LegalizeOp(Node->getOperand(0)); 1055 break; 1056 case Promote: 1057 // The input result is prerounded, so we don't have to do anything 1058 // special. 1059 Tmp1 = PromoteOp(Node->getOperand(0)); 1060 break; 1061 case Expand: 1062 assert(0 && "not implemented"); 1063 } 1064 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 1065 break; 1066 1067 case ISD::AND: 1068 case ISD::OR: 1069 case ISD::XOR: 1070 case ISD::ADD: 1071 case ISD::SUB: 1072 case ISD::MUL: 1073 // The input may have strange things in the top bits of the registers, but 1074 // these operations don't care. They may have wierd bits going out, but 1075 // that too is okay if they are integer operations. 1076 Tmp1 = PromoteOp(Node->getOperand(0)); 1077 Tmp2 = PromoteOp(Node->getOperand(1)); 1078 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 1079 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1080 1081 // However, if this is a floating point operation, they will give excess 1082 // precision that we may not be able to tolerate. If we DO allow excess 1083 // precision, just leave it, otherwise excise it. 1084 // FIXME: Why would we need to round FP ops more than integer ones? 1085 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 1086 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 1087 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1088 break; 1089 1090 case ISD::SDIV: 1091 case ISD::SREM: 1092 // These operators require that their input be sign extended. 1093 Tmp1 = PromoteOp(Node->getOperand(0)); 1094 Tmp2 = PromoteOp(Node->getOperand(1)); 1095 if (MVT::isInteger(NVT)) { 1096 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 1097 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT); 1098 } 1099 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1100 1101 // Perform FP_ROUND: this is probably overly pessimistic. 1102 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 1103 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1104 break; 1105 1106 case ISD::UDIV: 1107 case ISD::UREM: 1108 // These operators require that their input be zero extended. 1109 Tmp1 = PromoteOp(Node->getOperand(0)); 1110 Tmp2 = PromoteOp(Node->getOperand(1)); 1111 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 1112 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp1, VT); 1113 Tmp2 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp2, VT); 1114 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1115 break; 1116 1117 case ISD::SHL: 1118 Tmp1 = PromoteOp(Node->getOperand(0)); 1119 Tmp2 = LegalizeOp(Node->getOperand(1)); 1120 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 1121 break; 1122 case ISD::SRA: 1123 // The input value must be properly sign extended. 1124 Tmp1 = PromoteOp(Node->getOperand(0)); 1125 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 1126 Tmp2 = LegalizeOp(Node->getOperand(1)); 1127 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 1128 break; 1129 case ISD::SRL: 1130 // The input value must be properly zero extended. 1131 Tmp1 = PromoteOp(Node->getOperand(0)); 1132 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp1, VT); 1133 Tmp2 = LegalizeOp(Node->getOperand(1)); 1134 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 1135 break; 1136 case ISD::LOAD: 1137 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1138 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1139 Result = DAG.getNode(ISD::EXTLOAD, NVT, Tmp1, Tmp2, VT); 1140 1141 // Remember that we legalized the chain. 1142 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1143 break; 1144 case ISD::SELECT: 1145 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1146 case Expand: assert(0 && "It's impossible to expand bools"); 1147 case Legal: 1148 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 1149 break; 1150 case Promote: 1151 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1152 break; 1153 } 1154 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 1155 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 1156 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 1157 break; 1158 case ISD::CALL: { 1159 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1160 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 1161 1162 std::vector<SDOperand> Ops; 1163 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 1164 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1165 1166 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 1167 "Can only promote single result calls"); 1168 std::vector<MVT::ValueType> RetTyVTs; 1169 RetTyVTs.reserve(2); 1170 RetTyVTs.push_back(NVT); 1171 RetTyVTs.push_back(MVT::Other); 1172 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops); 1173 Result = SDOperand(NC, 0); 1174 1175 // Insert the new chain mapping. 1176 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1177 break; 1178 } 1179 } 1180 1181 assert(Result.Val && "Didn't set a result!"); 1182 AddPromotedOperand(Op, Result); 1183 return Result; 1184} 1185 1186/// ExpandShift - Try to find a clever way to expand this shift operation out to 1187/// smaller elements. If we can't find a way that is more efficient than a 1188/// libcall on this target, return false. Otherwise, return true with the 1189/// low-parts expanded into Lo and Hi. 1190bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 1191 SDOperand &Lo, SDOperand &Hi) { 1192 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 1193 "This is not a shift!"); 1194 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 1195 1196 // If we have an efficient select operation (or if the selects will all fold 1197 // away), lower to some complex code, otherwise just emit the libcall. 1198 if (TLI.getOperationAction(ISD::SELECT, NVT) != TargetLowering::Legal && 1199 !isa<ConstantSDNode>(Amt)) 1200 return false; 1201 1202 SDOperand InL, InH; 1203 ExpandOp(Op, InL, InH); 1204 SDOperand ShAmt = LegalizeOp(Amt); 1205 SDOperand OShAmt = ShAmt; // Unmasked shift amount. 1206 MVT::ValueType ShTy = ShAmt.getValueType(); 1207 1208 unsigned NVTBits = MVT::getSizeInBits(NVT); 1209 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 1210 DAG.getConstant(NVTBits, ShTy), ShAmt); 1211 1212 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 1213 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 1214 DAG.getConstant(NVTBits-1, ShTy)); 1215 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 1216 DAG.getConstant(NVTBits-1, ShTy)); 1217 } 1218 1219 if (Opc == ISD::SHL) { 1220 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 1221 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 1222 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 1223 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt 1224 1225 SDOperand Cond = DAG.getSetCC(ISD::SETGE, TLI.getSetCCResultTy(), OShAmt, 1226 DAG.getConstant(NVTBits, ShTy)); 1227 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 1228 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 1229 } else { 1230 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 1231 DAG.getNode(ISD::SHL, NVT, InH, NAmt), 1232 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 1233 bool isSign = Opc == ISD::SRA; 1234 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); 1235 1236 SDOperand HiPart; 1237 if (isSign) 1238 HiPart = DAG.getNode(Opc, NVT, InH, DAG.getConstant(NVTBits-1, ShTy)); 1239 else 1240 HiPart = DAG.getConstant(0, NVT); 1241 SDOperand Cond = DAG.getSetCC(ISD::SETGE, TLI.getSetCCResultTy(), OShAmt, 1242 DAG.getConstant(NVTBits, ShTy)); 1243 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 1244 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart,T2); 1245 } 1246 return true; 1247} 1248 1249 1250 1251/// ExpandOp - Expand the specified SDOperand into its two component pieces 1252/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 1253/// LegalizeNodes map is filled in for any results that are not expanded, the 1254/// ExpandedNodes map is filled in for any results that are expanded, and the 1255/// Lo/Hi values are returned. 1256void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 1257 MVT::ValueType VT = Op.getValueType(); 1258 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1259 SDNode *Node = Op.Val; 1260 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 1261 assert(MVT::isInteger(VT) && "Cannot expand FP values!"); 1262 assert(MVT::isInteger(NVT) && NVT < VT && 1263 "Cannot expand to FP value or to larger int value!"); 1264 1265 // If there is more than one use of this, see if we already expanded it. 1266 // There is no use remembering values that only have a single use, as the map 1267 // entries will never be reused. 1268 if (!Node->hasOneUse()) { 1269 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 1270 = ExpandedNodes.find(Op); 1271 if (I != ExpandedNodes.end()) { 1272 Lo = I->second.first; 1273 Hi = I->second.second; 1274 return; 1275 } 1276 } 1277 1278 // Expanding to multiple registers needs to perform an optimization step, and 1279 // is not careful to avoid operations the target does not support. Make sure 1280 // that all generated operations are legalized in the next iteration. 1281 NeedsAnotherIteration = true; 1282 const char *LibCallName = 0; 1283 1284 switch (Node->getOpcode()) { 1285 default: 1286 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 1287 assert(0 && "Do not know how to expand this operator!"); 1288 abort(); 1289 case ISD::Constant: { 1290 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 1291 Lo = DAG.getConstant(Cst, NVT); 1292 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 1293 break; 1294 } 1295 1296 case ISD::CopyFromReg: { 1297 unsigned Reg = cast<RegSDNode>(Node)->getReg(); 1298 // Aggregate register values are always in consequtive pairs. 1299 Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0)); 1300 Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1)); 1301 1302 // Remember that we legalized the chain. 1303 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 1304 1305 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 1306 break; 1307 } 1308 1309 case ISD::LOAD: { 1310 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1311 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1312 Lo = DAG.getLoad(NVT, Ch, Ptr); 1313 1314 // Increment the pointer to the other half. 1315 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 1316 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1317 getIntPtrConstant(IncrementSize)); 1318 Hi = DAG.getLoad(NVT, Ch, Ptr); 1319 1320 // Build a factor node to remember that this load is independent of the 1321 // other one. 1322 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1323 Hi.getValue(1)); 1324 1325 // Remember that we legalized the chain. 1326 AddLegalizedOperand(Op.getValue(1), TF); 1327 if (!TLI.isLittleEndian()) 1328 std::swap(Lo, Hi); 1329 break; 1330 } 1331 case ISD::CALL: { 1332 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1333 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 1334 1335 bool Changed = false; 1336 std::vector<SDOperand> Ops; 1337 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 1338 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1339 Changed |= Ops.back() != Node->getOperand(i); 1340 } 1341 1342 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 1343 "Can only expand a call once so far, not i64 -> i16!"); 1344 1345 std::vector<MVT::ValueType> RetTyVTs; 1346 RetTyVTs.reserve(3); 1347 RetTyVTs.push_back(NVT); 1348 RetTyVTs.push_back(NVT); 1349 RetTyVTs.push_back(MVT::Other); 1350 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops); 1351 Lo = SDOperand(NC, 0); 1352 Hi = SDOperand(NC, 1); 1353 1354 // Insert the new chain mapping. 1355 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 1356 break; 1357 } 1358 case ISD::AND: 1359 case ISD::OR: 1360 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 1361 SDOperand LL, LH, RL, RH; 1362 ExpandOp(Node->getOperand(0), LL, LH); 1363 ExpandOp(Node->getOperand(1), RL, RH); 1364 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 1365 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 1366 break; 1367 } 1368 case ISD::SELECT: { 1369 SDOperand C, LL, LH, RL, RH; 1370 1371 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1372 case Expand: assert(0 && "It's impossible to expand bools"); 1373 case Legal: 1374 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1375 break; 1376 case Promote: 1377 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 1378 break; 1379 } 1380 ExpandOp(Node->getOperand(1), LL, LH); 1381 ExpandOp(Node->getOperand(2), RL, RH); 1382 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 1383 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 1384 break; 1385 } 1386 case ISD::SIGN_EXTEND: { 1387 // The low part is just a sign extension of the input (which degenerates to 1388 // a copy). 1389 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, LegalizeOp(Node->getOperand(0))); 1390 1391 // The high part is obtained by SRA'ing all but one of the bits of the lo 1392 // part. 1393 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 1394 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, MVT::i8)); 1395 break; 1396 } 1397 case ISD::ZERO_EXTEND: 1398 // The low part is just a zero extension of the input (which degenerates to 1399 // a copy). 1400 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, LegalizeOp(Node->getOperand(0))); 1401 1402 // The high part is just a zero. 1403 Hi = DAG.getConstant(0, NVT); 1404 break; 1405 1406 // These operators cannot be expanded directly, emit them as calls to 1407 // library functions. 1408 case ISD::FP_TO_SINT: 1409 if (Node->getOperand(0).getValueType() == MVT::f32) 1410 LibCallName = "__fixsfdi"; 1411 else 1412 LibCallName = "__fixdfdi"; 1413 break; 1414 case ISD::FP_TO_UINT: 1415 if (Node->getOperand(0).getValueType() == MVT::f32) 1416 LibCallName = "__fixunssfdi"; 1417 else 1418 LibCallName = "__fixunsdfdi"; 1419 break; 1420 1421 case ISD::SHL: 1422 // If we can emit an efficient shift operation, do so now. 1423 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), 1424 Lo, Hi)) 1425 break; 1426 // Otherwise, emit a libcall. 1427 LibCallName = "__ashldi3"; 1428 break; 1429 1430 case ISD::SRA: 1431 // If we can emit an efficient shift operation, do so now. 1432 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), 1433 Lo, Hi)) 1434 break; 1435 // Otherwise, emit a libcall. 1436 LibCallName = "__ashrdi3"; 1437 break; 1438 case ISD::SRL: 1439 // If we can emit an efficient shift operation, do so now. 1440 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), 1441 Lo, Hi)) 1442 break; 1443 // Otherwise, emit a libcall. 1444 LibCallName = "__lshrdi3"; 1445 break; 1446 1447 case ISD::ADD: LibCallName = "__adddi3"; break; 1448 case ISD::SUB: LibCallName = "__subdi3"; break; 1449 case ISD::MUL: LibCallName = "__muldi3"; break; 1450 case ISD::SDIV: LibCallName = "__divdi3"; break; 1451 case ISD::UDIV: LibCallName = "__udivdi3"; break; 1452 case ISD::SREM: LibCallName = "__moddi3"; break; 1453 case ISD::UREM: LibCallName = "__umoddi3"; break; 1454 } 1455 1456 // Int2FP -> __floatdisf/__floatdidf 1457 1458 // If this is to be expanded into a libcall... do so now. 1459 if (LibCallName) { 1460 TargetLowering::ArgListTy Args; 1461 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1462 Args.push_back(std::make_pair(Node->getOperand(i), 1463 MVT::getTypeForValueType(Node->getOperand(i).getValueType()))); 1464 SDOperand Callee = DAG.getExternalSymbol(LibCallName, TLI.getPointerTy()); 1465 1466 // We don't care about token chains for libcalls. We just use the entry 1467 // node as our input and ignore the output chain. This allows us to place 1468 // calls wherever we need them to satisfy data dependences. 1469 SDOperand Result = TLI.LowerCallTo(DAG.getEntryNode(), 1470 MVT::getTypeForValueType(Op.getValueType()), Callee, 1471 Args, DAG).first; 1472 ExpandOp(Result, Lo, Hi); 1473 } 1474 1475 // Remember in a map if the values will be reused later. 1476 if (!Node->hasOneUse()) { 1477 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 1478 std::make_pair(Lo, Hi))).second; 1479 assert(isNew && "Value already expanded?!?"); 1480 } 1481} 1482 1483 1484// SelectionDAG::Legalize - This is the entry point for the file. 1485// 1486void SelectionDAG::Legalize(TargetLowering &TLI) { 1487 /// run - This is the main entry point to this class. 1488 /// 1489 SelectionDAGLegalize(TLI, *this).Run(); 1490} 1491 1492