LegalizeDAG.cpp revision 4c948eb373779718e5be36d7674382b52114bf65
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetMachine.h" 21#include "llvm/Target/TargetOptions.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Support/MathExtras.h" 26#include "llvm/Support/CommandLine.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/ADT/DenseMap.h" 29#include "llvm/ADT/SmallVector.h" 30#include "llvm/ADT/SmallPtrSet.h" 31#include <map> 32using namespace llvm; 33 34#ifndef NDEBUG 35static cl::opt<bool> 36ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 37 cl::desc("Pop up a window to show dags before legalize")); 38#else 39static const bool ViewLegalizeDAGs = 0; 40#endif 41 42namespace llvm { 43template<> 44struct DenseMapKeyInfo<SDOperand> { 45 static inline SDOperand getEmptyKey() { return SDOperand((SDNode*)-1, -1U); } 46 static inline SDOperand getTombstoneKey() { return SDOperand((SDNode*)-1, 0);} 47 static unsigned getHashValue(const SDOperand &Val) { 48 return DenseMapKeyInfo<void*>::getHashValue(Val.Val) + Val.ResNo; 49 } 50 static bool isPod() { return true; } 51}; 52} 53 54//===----------------------------------------------------------------------===// 55/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 56/// hacks on it until the target machine can handle it. This involves 57/// eliminating value sizes the machine cannot handle (promoting small sizes to 58/// large sizes or splitting up large values into small values) as well as 59/// eliminating operations the machine cannot handle. 60/// 61/// This code also does a small amount of optimization and recognition of idioms 62/// as part of its processing. For example, if a target does not support a 63/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 64/// will attempt merge setcc and brc instructions into brcc's. 65/// 66namespace { 67class VISIBILITY_HIDDEN SelectionDAGLegalize { 68 TargetLowering &TLI; 69 SelectionDAG &DAG; 70 71 // Libcall insertion helpers. 72 73 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 74 /// legalized. We use this to ensure that calls are properly serialized 75 /// against each other, including inserted libcalls. 76 SDOperand LastCALLSEQ_END; 77 78 /// IsLegalizingCall - This member is used *only* for purposes of providing 79 /// helpful assertions that a libcall isn't created while another call is 80 /// being legalized (which could lead to non-serialized call sequences). 81 bool IsLegalizingCall; 82 83 enum LegalizeAction { 84 Legal, // The target natively supports this operation. 85 Promote, // This operation should be executed in a larger type. 86 Expand // Try to expand this to other ops, otherwise use a libcall. 87 }; 88 89 /// ValueTypeActions - This is a bitvector that contains two bits for each 90 /// value type, where the two bits correspond to the LegalizeAction enum. 91 /// This can be queried with "getTypeAction(VT)". 92 TargetLowering::ValueTypeActionImpl ValueTypeActions; 93 94 /// LegalizedNodes - For nodes that are of legal width, and that have more 95 /// than one use, this map indicates what regularized operand to use. This 96 /// allows us to avoid legalizing the same thing more than once. 97 DenseMap<SDOperand, SDOperand> LegalizedNodes; 98 99 /// PromotedNodes - For nodes that are below legal width, and that have more 100 /// than one use, this map indicates what promoted value to use. This allows 101 /// us to avoid promoting the same thing more than once. 102 DenseMap<SDOperand, SDOperand> PromotedNodes; 103 104 /// ExpandedNodes - For nodes that need to be expanded this map indicates 105 /// which which operands are the expanded version of the input. This allows 106 /// us to avoid expanding the same node more than once. 107 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 108 109 /// SplitNodes - For vector nodes that need to be split, this map indicates 110 /// which which operands are the split version of the input. This allows us 111 /// to avoid splitting the same node more than once. 112 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 113 114 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to 115 /// concrete packed types, this contains the mapping of ones we have already 116 /// processed to the result. 117 std::map<SDOperand, SDOperand> PackedNodes; 118 119 void AddLegalizedOperand(SDOperand From, SDOperand To) { 120 LegalizedNodes.insert(std::make_pair(From, To)); 121 // If someone requests legalization of the new node, return itself. 122 if (From != To) 123 LegalizedNodes.insert(std::make_pair(To, To)); 124 } 125 void AddPromotedOperand(SDOperand From, SDOperand To) { 126 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 127 assert(isNew && "Got into the map somehow?"); 128 // If someone requests legalization of the new node, return itself. 129 LegalizedNodes.insert(std::make_pair(To, To)); 130 } 131 132public: 133 134 SelectionDAGLegalize(SelectionDAG &DAG); 135 136 /// getTypeAction - Return how we should legalize values of this type, either 137 /// it is already legal or we need to expand it into multiple registers of 138 /// smaller integer type, or we need to promote it to a larger type. 139 LegalizeAction getTypeAction(MVT::ValueType VT) const { 140 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 141 } 142 143 /// isTypeLegal - Return true if this type is legal on this target. 144 /// 145 bool isTypeLegal(MVT::ValueType VT) const { 146 return getTypeAction(VT) == Legal; 147 } 148 149 void LegalizeDAG(); 150 151private: 152 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 153 /// appropriate for its type. 154 void HandleOp(SDOperand Op); 155 156 /// LegalizeOp - We know that the specified value has a legal type. 157 /// Recursively ensure that the operands have legal types, then return the 158 /// result. 159 SDOperand LegalizeOp(SDOperand O); 160 161 /// PromoteOp - Given an operation that produces a value in an invalid type, 162 /// promote it to compute the value into a larger type. The produced value 163 /// will have the correct bits for the low portion of the register, but no 164 /// guarantee is made about the top bits: it may be zero, sign-extended, or 165 /// garbage. 166 SDOperand PromoteOp(SDOperand O); 167 168 /// ExpandOp - Expand the specified SDOperand into its two component pieces 169 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 170 /// the LegalizeNodes map is filled in for any results that are not expanded, 171 /// the ExpandedNodes map is filled in for any results that are expanded, and 172 /// the Lo/Hi values are returned. This applies to integer types and Vector 173 /// types. 174 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 175 176 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 177 /// two smaller values of MVT::Vector type. 178 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 179 180 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 181 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When 182 /// this is called, we know that PackedVT is the right type for the result and 183 /// we know that this type is legal for the target. 184 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT); 185 186 /// isShuffleLegal - Return true if a vector shuffle is legal with the 187 /// specified mask and type. Targets can specify exactly which masks they 188 /// support and the code generator is tasked with not creating illegal masks. 189 /// 190 /// Note that this will also return true for shuffles that are promoted to a 191 /// different type. 192 /// 193 /// If this is a legal shuffle, this method returns the (possibly promoted) 194 /// build_vector Mask. If it's not a legal shuffle, it returns null. 195 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 196 197 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 198 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 199 200 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 201 202 SDOperand CreateStackTemporary(MVT::ValueType VT); 203 204 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 205 SDOperand &Hi); 206 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 207 SDOperand Source); 208 209 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 210 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 211 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 212 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 213 SDOperand LegalOp, 214 MVT::ValueType DestVT); 215 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 216 bool isSigned); 217 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 218 bool isSigned); 219 220 SDOperand ExpandBSWAP(SDOperand Op); 221 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 222 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 223 SDOperand &Lo, SDOperand &Hi); 224 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 225 SDOperand &Lo, SDOperand &Hi); 226 227 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op); 228 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 229 230 SDOperand getIntPtrConstant(uint64_t Val) { 231 return DAG.getConstant(Val, TLI.getPointerTy()); 232 } 233}; 234} 235 236/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 237/// specified mask and type. Targets can specify exactly which masks they 238/// support and the code generator is tasked with not creating illegal masks. 239/// 240/// Note that this will also return true for shuffles that are promoted to a 241/// different type. 242SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 243 SDOperand Mask) const { 244 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 245 default: return 0; 246 case TargetLowering::Legal: 247 case TargetLowering::Custom: 248 break; 249 case TargetLowering::Promote: { 250 // If this is promoted to a different type, convert the shuffle mask and 251 // ask if it is legal in the promoted type! 252 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 253 254 // If we changed # elements, change the shuffle mask. 255 unsigned NumEltsGrowth = 256 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 257 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 258 if (NumEltsGrowth > 1) { 259 // Renumber the elements. 260 SmallVector<SDOperand, 8> Ops; 261 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 262 SDOperand InOp = Mask.getOperand(i); 263 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 264 if (InOp.getOpcode() == ISD::UNDEF) 265 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 266 else { 267 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 268 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 269 } 270 } 271 } 272 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 273 } 274 VT = NVT; 275 break; 276 } 277 } 278 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 279} 280 281/// getScalarizedOpcode - Return the scalar opcode that corresponds to the 282/// specified vector opcode. 283static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 284 switch (VecOp) { 285 default: assert(0 && "Don't know how to scalarize this opcode!"); 286 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 287 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 288 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 289 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV; 290 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV; 291 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0; 292 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0; 293 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0; 294 } 295} 296 297SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 298 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 299 ValueTypeActions(TLI.getValueTypeActions()) { 300 assert(MVT::LAST_VALUETYPE <= 32 && 301 "Too many value types for ValueTypeActions to hold!"); 302} 303 304/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 305/// not been visited yet and if all of its operands have already been visited. 306static void ComputeTopDownOrdering(SDNode *N, SmallVector<SDNode*, 64> &Order, 307 DenseMap<SDNode*, unsigned> &Visited) { 308 if (++Visited[N] != N->getNumOperands()) 309 return; // Haven't visited all operands yet 310 311 Order.push_back(N); 312 313 if (N->hasOneUse()) { // Tail recurse in common case. 314 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 315 return; 316 } 317 318 // Now that we have N in, add anything that uses it if all of their operands 319 // are now done. 320 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 321 ComputeTopDownOrdering(*UI, Order, Visited); 322} 323 324 325void SelectionDAGLegalize::LegalizeDAG() { 326 LastCALLSEQ_END = DAG.getEntryNode(); 327 IsLegalizingCall = false; 328 329 // The legalize process is inherently a bottom-up recursive process (users 330 // legalize their uses before themselves). Given infinite stack space, we 331 // could just start legalizing on the root and traverse the whole graph. In 332 // practice however, this causes us to run out of stack space on large basic 333 // blocks. To avoid this problem, compute an ordering of the nodes where each 334 // node is only legalized after all of its operands are legalized. 335 DenseMap<SDNode*, unsigned> Visited; 336 SmallVector<SDNode*, 64> Order; 337 338 // Compute ordering from all of the leaves in the graphs, those (like the 339 // entry node) that have no operands. 340 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 341 E = DAG.allnodes_end(); I != E; ++I) { 342 if (I->getNumOperands() == 0) { 343 Visited[I] = 0 - 1U; 344 ComputeTopDownOrdering(I, Order, Visited); 345 } 346 } 347 348 assert(Order.size() == Visited.size() && 349 Order.size() == 350 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 351 "Error: DAG is cyclic!"); 352 Visited.clear(); 353 354 for (unsigned i = 0, e = Order.size(); i != e; ++i) 355 HandleOp(SDOperand(Order[i], 0)); 356 357 // Finally, it's possible the root changed. Get the new root. 358 SDOperand OldRoot = DAG.getRoot(); 359 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 360 DAG.setRoot(LegalizedNodes[OldRoot]); 361 362 ExpandedNodes.clear(); 363 LegalizedNodes.clear(); 364 PromotedNodes.clear(); 365 SplitNodes.clear(); 366 PackedNodes.clear(); 367 368 // Remove dead nodes now. 369 DAG.RemoveDeadNodes(); 370} 371 372 373/// FindCallEndFromCallStart - Given a chained node that is part of a call 374/// sequence, find the CALLSEQ_END node that terminates the call sequence. 375static SDNode *FindCallEndFromCallStart(SDNode *Node) { 376 if (Node->getOpcode() == ISD::CALLSEQ_END) 377 return Node; 378 if (Node->use_empty()) 379 return 0; // No CallSeqEnd 380 381 // The chain is usually at the end. 382 SDOperand TheChain(Node, Node->getNumValues()-1); 383 if (TheChain.getValueType() != MVT::Other) { 384 // Sometimes it's at the beginning. 385 TheChain = SDOperand(Node, 0); 386 if (TheChain.getValueType() != MVT::Other) { 387 // Otherwise, hunt for it. 388 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 389 if (Node->getValueType(i) == MVT::Other) { 390 TheChain = SDOperand(Node, i); 391 break; 392 } 393 394 // Otherwise, we walked into a node without a chain. 395 if (TheChain.getValueType() != MVT::Other) 396 return 0; 397 } 398 } 399 400 for (SDNode::use_iterator UI = Node->use_begin(), 401 E = Node->use_end(); UI != E; ++UI) { 402 403 // Make sure to only follow users of our token chain. 404 SDNode *User = *UI; 405 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 406 if (User->getOperand(i) == TheChain) 407 if (SDNode *Result = FindCallEndFromCallStart(User)) 408 return Result; 409 } 410 return 0; 411} 412 413/// FindCallStartFromCallEnd - Given a chained node that is part of a call 414/// sequence, find the CALLSEQ_START node that initiates the call sequence. 415static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 416 assert(Node && "Didn't find callseq_start for a call??"); 417 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 418 419 assert(Node->getOperand(0).getValueType() == MVT::Other && 420 "Node doesn't have a token chain argument!"); 421 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 422} 423 424/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 425/// see if any uses can reach Dest. If no dest operands can get to dest, 426/// legalize them, legalize ourself, and return false, otherwise, return true. 427/// 428/// Keep track of the nodes we fine that actually do lead to Dest in 429/// NodesLeadingTo. This avoids retraversing them exponential number of times. 430/// 431bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 432 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 433 if (N == Dest) return true; // N certainly leads to Dest :) 434 435 // If we've already processed this node and it does lead to Dest, there is no 436 // need to reprocess it. 437 if (NodesLeadingTo.count(N)) return true; 438 439 // If the first result of this node has been already legalized, then it cannot 440 // reach N. 441 switch (getTypeAction(N->getValueType(0))) { 442 case Legal: 443 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 444 break; 445 case Promote: 446 if (PromotedNodes.count(SDOperand(N, 0))) return false; 447 break; 448 case Expand: 449 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 450 break; 451 } 452 453 // Okay, this node has not already been legalized. Check and legalize all 454 // operands. If none lead to Dest, then we can legalize this node. 455 bool OperandsLeadToDest = false; 456 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 457 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 458 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 459 460 if (OperandsLeadToDest) { 461 NodesLeadingTo.insert(N); 462 return true; 463 } 464 465 // Okay, this node looks safe, legalize it and return false. 466 HandleOp(SDOperand(N, 0)); 467 return false; 468} 469 470/// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 471/// appropriate for its type. 472void SelectionDAGLegalize::HandleOp(SDOperand Op) { 473 switch (getTypeAction(Op.getValueType())) { 474 default: assert(0 && "Bad type action!"); 475 case Legal: LegalizeOp(Op); break; 476 case Promote: PromoteOp(Op); break; 477 case Expand: 478 if (Op.getValueType() != MVT::Vector) { 479 SDOperand X, Y; 480 ExpandOp(Op, X, Y); 481 } else { 482 SDNode *N = Op.Val; 483 unsigned NumOps = N->getNumOperands(); 484 unsigned NumElements = 485 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue(); 486 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT(); 487 MVT::ValueType PackedVT = getVectorType(EVT, NumElements); 488 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) { 489 // In the common case, this is a legal vector type, convert it to the 490 // packed operation and type now. 491 PackVectorOp(Op, PackedVT); 492 } else if (NumElements == 1) { 493 // Otherwise, if this is a single element vector, convert it to a 494 // scalar operation. 495 PackVectorOp(Op, EVT); 496 } else { 497 // Otherwise, this is a multiple element vector that isn't supported. 498 // Split it in half and legalize both parts. 499 SDOperand X, Y; 500 SplitVectorOp(Op, X, Y); 501 } 502 } 503 break; 504 } 505} 506 507/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 508/// a load from the constant pool. 509static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 510 SelectionDAG &DAG, TargetLowering &TLI) { 511 bool Extend = false; 512 513 // If a FP immediate is precise when represented as a float and if the 514 // target can do an extending load from float to double, we put it into 515 // the constant pool as a float, even if it's is statically typed as a 516 // double. 517 MVT::ValueType VT = CFP->getValueType(0); 518 bool isDouble = VT == MVT::f64; 519 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 520 Type::FloatTy, CFP->getValue()); 521 if (!UseCP) { 522 double Val = LLVMC->getValue(); 523 return isDouble 524 ? DAG.getConstant(DoubleToBits(Val), MVT::i64) 525 : DAG.getConstant(FloatToBits(Val), MVT::i32); 526 } 527 528 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 529 // Only do this if the target has a native EXTLOAD instruction from f32. 530 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 531 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); 532 VT = MVT::f32; 533 Extend = true; 534 } 535 536 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 537 if (Extend) { 538 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 539 CPIdx, NULL, 0, MVT::f32); 540 } else { 541 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 542 } 543} 544 545 546/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 547/// operations. 548static 549SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 550 SelectionDAG &DAG, TargetLowering &TLI) { 551 MVT::ValueType VT = Node->getValueType(0); 552 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 553 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 554 555 // First get the sign bit of second operand. 556 SDOperand Mask1 = (SrcVT == MVT::f64) 557 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 558 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 559 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 560 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 561 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 562 // Shift right or sign-extend it if the two operands have different types. 563 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 564 if (SizeDiff > 0) { 565 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 566 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 567 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 568 } else if (SizeDiff < 0) 569 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 570 571 // Clear the sign bit of first operand. 572 SDOperand Mask2 = (VT == MVT::f64) 573 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 574 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 575 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 576 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 577 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 578 579 // Or the value with the sign bit. 580 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 581 return Result; 582} 583 584 585/// LegalizeOp - We know that the specified value has a legal type. 586/// Recursively ensure that the operands have legal types, then return the 587/// result. 588SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 589 assert(isTypeLegal(Op.getValueType()) && 590 "Caller should expand or promote operands that are not legal!"); 591 SDNode *Node = Op.Val; 592 593 // If this operation defines any values that cannot be represented in a 594 // register on this target, make sure to expand or promote them. 595 if (Node->getNumValues() > 1) { 596 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 597 if (getTypeAction(Node->getValueType(i)) != Legal) { 598 HandleOp(Op.getValue(i)); 599 assert(LegalizedNodes.count(Op) && 600 "Handling didn't add legal operands!"); 601 return LegalizedNodes[Op]; 602 } 603 } 604 605 // Note that LegalizeOp may be reentered even from single-use nodes, which 606 // means that we always must cache transformed nodes. 607 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 608 if (I != LegalizedNodes.end()) return I->second; 609 610 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 611 SDOperand Result = Op; 612 bool isCustom = false; 613 614 switch (Node->getOpcode()) { 615 case ISD::FrameIndex: 616 case ISD::EntryToken: 617 case ISD::Register: 618 case ISD::BasicBlock: 619 case ISD::TargetFrameIndex: 620 case ISD::TargetJumpTable: 621 case ISD::TargetConstant: 622 case ISD::TargetConstantFP: 623 case ISD::TargetConstantPool: 624 case ISD::TargetGlobalAddress: 625 case ISD::TargetExternalSymbol: 626 case ISD::VALUETYPE: 627 case ISD::SRCVALUE: 628 case ISD::STRING: 629 case ISD::CONDCODE: 630 case ISD::GLOBAL_OFFSET_TABLE: 631 // Primitives must all be legal. 632 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 633 "This must be legal!"); 634 break; 635 default: 636 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 637 // If this is a target node, legalize it by legalizing the operands then 638 // passing it through. 639 SmallVector<SDOperand, 8> Ops; 640 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 641 Ops.push_back(LegalizeOp(Node->getOperand(i))); 642 643 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 644 645 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 646 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 647 return Result.getValue(Op.ResNo); 648 } 649 // Otherwise this is an unhandled builtin node. splat. 650#ifndef NDEBUG 651 cerr << "NODE: "; Node->dump(); cerr << "\n"; 652#endif 653 assert(0 && "Do not know how to legalize this operator!"); 654 abort(); 655 case ISD::GlobalAddress: 656 case ISD::ExternalSymbol: 657 case ISD::ConstantPool: 658 case ISD::JumpTable: // Nothing to do. 659 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 660 default: assert(0 && "This action is not supported yet!"); 661 case TargetLowering::Custom: 662 Tmp1 = TLI.LowerOperation(Op, DAG); 663 if (Tmp1.Val) Result = Tmp1; 664 // FALLTHROUGH if the target doesn't want to lower this op after all. 665 case TargetLowering::Legal: 666 break; 667 } 668 break; 669 case ISD::FRAMEADDR: 670 case ISD::RETURNADDR: 671 // The only option for these nodes is to custom lower them. If the target 672 // does not custom lower them, then return zero. 673 Tmp1 = TLI.LowerOperation(Op, DAG); 674 if (Tmp1.Val) 675 Result = Tmp1; 676 else 677 Result = DAG.getConstant(0, TLI.getPointerTy()); 678 break; 679 case ISD::AssertSext: 680 case ISD::AssertZext: 681 Tmp1 = LegalizeOp(Node->getOperand(0)); 682 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 683 break; 684 case ISD::MERGE_VALUES: 685 // Legalize eliminates MERGE_VALUES nodes. 686 Result = Node->getOperand(Op.ResNo); 687 break; 688 case ISD::CopyFromReg: 689 Tmp1 = LegalizeOp(Node->getOperand(0)); 690 Result = Op.getValue(0); 691 if (Node->getNumValues() == 2) { 692 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 693 } else { 694 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 695 if (Node->getNumOperands() == 3) { 696 Tmp2 = LegalizeOp(Node->getOperand(2)); 697 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 698 } else { 699 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 700 } 701 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 702 } 703 // Since CopyFromReg produces two values, make sure to remember that we 704 // legalized both of them. 705 AddLegalizedOperand(Op.getValue(0), Result); 706 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 707 return Result.getValue(Op.ResNo); 708 case ISD::UNDEF: { 709 MVT::ValueType VT = Op.getValueType(); 710 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 711 default: assert(0 && "This action is not supported yet!"); 712 case TargetLowering::Expand: 713 if (MVT::isInteger(VT)) 714 Result = DAG.getConstant(0, VT); 715 else if (MVT::isFloatingPoint(VT)) 716 Result = DAG.getConstantFP(0, VT); 717 else 718 assert(0 && "Unknown value type!"); 719 break; 720 case TargetLowering::Legal: 721 break; 722 } 723 break; 724 } 725 726 case ISD::INTRINSIC_W_CHAIN: 727 case ISD::INTRINSIC_WO_CHAIN: 728 case ISD::INTRINSIC_VOID: { 729 SmallVector<SDOperand, 8> Ops; 730 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 731 Ops.push_back(LegalizeOp(Node->getOperand(i))); 732 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 733 734 // Allow the target to custom lower its intrinsics if it wants to. 735 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 736 TargetLowering::Custom) { 737 Tmp3 = TLI.LowerOperation(Result, DAG); 738 if (Tmp3.Val) Result = Tmp3; 739 } 740 741 if (Result.Val->getNumValues() == 1) break; 742 743 // Must have return value and chain result. 744 assert(Result.Val->getNumValues() == 2 && 745 "Cannot return more than two values!"); 746 747 // Since loads produce two values, make sure to remember that we 748 // legalized both of them. 749 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 750 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 751 return Result.getValue(Op.ResNo); 752 } 753 754 case ISD::LOCATION: 755 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 756 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 757 758 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 759 case TargetLowering::Promote: 760 default: assert(0 && "This action is not supported yet!"); 761 case TargetLowering::Expand: { 762 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 763 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 764 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 765 766 if (MMI && (useDEBUG_LOC || useLABEL)) { 767 const std::string &FName = 768 cast<StringSDNode>(Node->getOperand(3))->getValue(); 769 const std::string &DirName = 770 cast<StringSDNode>(Node->getOperand(4))->getValue(); 771 unsigned SrcFile = MMI->RecordSource(DirName, FName); 772 773 SmallVector<SDOperand, 8> Ops; 774 Ops.push_back(Tmp1); // chain 775 SDOperand LineOp = Node->getOperand(1); 776 SDOperand ColOp = Node->getOperand(2); 777 778 if (useDEBUG_LOC) { 779 Ops.push_back(LineOp); // line # 780 Ops.push_back(ColOp); // col # 781 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 782 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 783 } else { 784 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 785 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 786 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile); 787 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 788 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size()); 789 } 790 } else { 791 Result = Tmp1; // chain 792 } 793 break; 794 } 795 case TargetLowering::Legal: 796 if (Tmp1 != Node->getOperand(0) || 797 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 798 SmallVector<SDOperand, 8> Ops; 799 Ops.push_back(Tmp1); 800 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 801 Ops.push_back(Node->getOperand(1)); // line # must be legal. 802 Ops.push_back(Node->getOperand(2)); // col # must be legal. 803 } else { 804 // Otherwise promote them. 805 Ops.push_back(PromoteOp(Node->getOperand(1))); 806 Ops.push_back(PromoteOp(Node->getOperand(2))); 807 } 808 Ops.push_back(Node->getOperand(3)); // filename must be legal. 809 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 810 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 811 } 812 break; 813 } 814 break; 815 816 case ISD::DEBUG_LOC: 817 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 818 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 819 default: assert(0 && "This action is not supported yet!"); 820 case TargetLowering::Legal: 821 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 822 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 823 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 824 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 825 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 826 break; 827 } 828 break; 829 830 case ISD::LABEL: 831 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!"); 832 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 833 default: assert(0 && "This action is not supported yet!"); 834 case TargetLowering::Legal: 835 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 836 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 837 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 838 break; 839 } 840 break; 841 842 case ISD::Constant: 843 // We know we don't need to expand constants here, constants only have one 844 // value and we check that it is fine above. 845 846 // FIXME: Maybe we should handle things like targets that don't support full 847 // 32-bit immediates? 848 break; 849 case ISD::ConstantFP: { 850 // Spill FP immediates to the constant pool if the target cannot directly 851 // codegen them. Targets often have some immediate values that can be 852 // efficiently generated into an FP register without a load. We explicitly 853 // leave these constants as ConstantFP nodes for the target to deal with. 854 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 855 856 // Check to see if this FP immediate is already legal. 857 bool isLegal = false; 858 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 859 E = TLI.legal_fpimm_end(); I != E; ++I) 860 if (CFP->isExactlyValue(*I)) { 861 isLegal = true; 862 break; 863 } 864 865 // If this is a legal constant, turn it into a TargetConstantFP node. 866 if (isLegal) { 867 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0)); 868 break; 869 } 870 871 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 872 default: assert(0 && "This action is not supported yet!"); 873 case TargetLowering::Custom: 874 Tmp3 = TLI.LowerOperation(Result, DAG); 875 if (Tmp3.Val) { 876 Result = Tmp3; 877 break; 878 } 879 // FALLTHROUGH 880 case TargetLowering::Expand: 881 Result = ExpandConstantFP(CFP, true, DAG, TLI); 882 } 883 break; 884 } 885 case ISD::TokenFactor: 886 if (Node->getNumOperands() == 2) { 887 Tmp1 = LegalizeOp(Node->getOperand(0)); 888 Tmp2 = LegalizeOp(Node->getOperand(1)); 889 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 890 } else if (Node->getNumOperands() == 3) { 891 Tmp1 = LegalizeOp(Node->getOperand(0)); 892 Tmp2 = LegalizeOp(Node->getOperand(1)); 893 Tmp3 = LegalizeOp(Node->getOperand(2)); 894 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 895 } else { 896 SmallVector<SDOperand, 8> Ops; 897 // Legalize the operands. 898 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 899 Ops.push_back(LegalizeOp(Node->getOperand(i))); 900 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 901 } 902 break; 903 904 case ISD::FORMAL_ARGUMENTS: 905 case ISD::CALL: 906 // The only option for this is to custom lower it. 907 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 908 assert(Tmp3.Val && "Target didn't custom lower this node!"); 909 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() && 910 "Lowering call/formal_arguments produced unexpected # results!"); 911 912 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 913 // remember that we legalized all of them, so it doesn't get relegalized. 914 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 915 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 916 if (Op.ResNo == i) 917 Tmp2 = Tmp1; 918 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 919 } 920 return Tmp2; 921 922 case ISD::BUILD_VECTOR: 923 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 924 default: assert(0 && "This action is not supported yet!"); 925 case TargetLowering::Custom: 926 Tmp3 = TLI.LowerOperation(Result, DAG); 927 if (Tmp3.Val) { 928 Result = Tmp3; 929 break; 930 } 931 // FALLTHROUGH 932 case TargetLowering::Expand: 933 Result = ExpandBUILD_VECTOR(Result.Val); 934 break; 935 } 936 break; 937 case ISD::INSERT_VECTOR_ELT: 938 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 939 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 940 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 941 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 942 943 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 944 Node->getValueType(0))) { 945 default: assert(0 && "This action is not supported yet!"); 946 case TargetLowering::Legal: 947 break; 948 case TargetLowering::Custom: 949 Tmp3 = TLI.LowerOperation(Result, DAG); 950 if (Tmp3.Val) { 951 Result = Tmp3; 952 break; 953 } 954 // FALLTHROUGH 955 case TargetLowering::Expand: { 956 // If the insert index is a constant, codegen this as a scalar_to_vector, 957 // then a shuffle that inserts it into the right position in the vector. 958 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 959 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 960 Tmp1.getValueType(), Tmp2); 961 962 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 963 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 964 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT); 965 966 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 967 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 968 // the RHS. 969 SmallVector<SDOperand, 8> ShufOps; 970 for (unsigned i = 0; i != NumElts; ++i) { 971 if (i != InsertPos->getValue()) 972 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 973 else 974 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 975 } 976 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 977 &ShufOps[0], ShufOps.size()); 978 979 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 980 Tmp1, ScVec, ShufMask); 981 Result = LegalizeOp(Result); 982 break; 983 } 984 985 // If the target doesn't support this, we have to spill the input vector 986 // to a temporary stack slot, update the element, then reload it. This is 987 // badness. We could also load the value into a vector register (either 988 // with a "move to register" or "extload into register" instruction, then 989 // permute it into place, if the idx is a constant and if the idx is 990 // supported by the target. 991 MVT::ValueType VT = Tmp1.getValueType(); 992 MVT::ValueType EltVT = Tmp2.getValueType(); 993 MVT::ValueType IdxVT = Tmp3.getValueType(); 994 MVT::ValueType PtrVT = TLI.getPointerTy(); 995 SDOperand StackPtr = CreateStackTemporary(VT); 996 // Store the vector. 997 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); 998 999 // Truncate or zero extend offset to target pointer type. 1000 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1001 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 1002 // Add the offset to the index. 1003 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 1004 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 1005 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 1006 // Store the scalar value. 1007 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); 1008 // Load the updated vector. 1009 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); 1010 break; 1011 } 1012 } 1013 break; 1014 case ISD::SCALAR_TO_VECTOR: 1015 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1016 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1017 break; 1018 } 1019 1020 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1021 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1022 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1023 Node->getValueType(0))) { 1024 default: assert(0 && "This action is not supported yet!"); 1025 case TargetLowering::Legal: 1026 break; 1027 case TargetLowering::Custom: 1028 Tmp3 = TLI.LowerOperation(Result, DAG); 1029 if (Tmp3.Val) { 1030 Result = Tmp3; 1031 break; 1032 } 1033 // FALLTHROUGH 1034 case TargetLowering::Expand: 1035 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1036 break; 1037 } 1038 break; 1039 case ISD::VECTOR_SHUFFLE: 1040 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1041 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1042 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1043 1044 // Allow targets to custom lower the SHUFFLEs they support. 1045 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1046 default: assert(0 && "Unknown operation action!"); 1047 case TargetLowering::Legal: 1048 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1049 "vector shuffle should not be created if not legal!"); 1050 break; 1051 case TargetLowering::Custom: 1052 Tmp3 = TLI.LowerOperation(Result, DAG); 1053 if (Tmp3.Val) { 1054 Result = Tmp3; 1055 break; 1056 } 1057 // FALLTHROUGH 1058 case TargetLowering::Expand: { 1059 MVT::ValueType VT = Node->getValueType(0); 1060 MVT::ValueType EltVT = MVT::getVectorBaseType(VT); 1061 MVT::ValueType PtrVT = TLI.getPointerTy(); 1062 SDOperand Mask = Node->getOperand(2); 1063 unsigned NumElems = Mask.getNumOperands(); 1064 SmallVector<SDOperand,8> Ops; 1065 for (unsigned i = 0; i != NumElems; ++i) { 1066 SDOperand Arg = Mask.getOperand(i); 1067 if (Arg.getOpcode() == ISD::UNDEF) { 1068 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1069 } else { 1070 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1071 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1072 if (Idx < NumElems) 1073 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1074 DAG.getConstant(Idx, PtrVT))); 1075 else 1076 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1077 DAG.getConstant(Idx - NumElems, PtrVT))); 1078 } 1079 } 1080 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1081 break; 1082 } 1083 case TargetLowering::Promote: { 1084 // Change base type to a different vector type. 1085 MVT::ValueType OVT = Node->getValueType(0); 1086 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1087 1088 // Cast the two input vectors. 1089 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1090 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1091 1092 // Convert the shuffle mask to the right # elements. 1093 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1094 assert(Tmp3.Val && "Shuffle not legal?"); 1095 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1096 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1097 break; 1098 } 1099 } 1100 break; 1101 1102 case ISD::EXTRACT_VECTOR_ELT: 1103 Tmp1 = LegalizeOp(Node->getOperand(0)); 1104 Tmp2 = LegalizeOp(Node->getOperand(1)); 1105 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1106 1107 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, 1108 Tmp1.getValueType())) { 1109 default: assert(0 && "This action is not supported yet!"); 1110 case TargetLowering::Legal: 1111 break; 1112 case TargetLowering::Custom: 1113 Tmp3 = TLI.LowerOperation(Result, DAG); 1114 if (Tmp3.Val) { 1115 Result = Tmp3; 1116 break; 1117 } 1118 // FALLTHROUGH 1119 case TargetLowering::Expand: 1120 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1121 break; 1122 } 1123 break; 1124 1125 case ISD::VEXTRACT_VECTOR_ELT: 1126 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op)); 1127 break; 1128 1129 case ISD::CALLSEQ_START: { 1130 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1131 1132 // Recursively Legalize all of the inputs of the call end that do not lead 1133 // to this call start. This ensures that any libcalls that need be inserted 1134 // are inserted *before* the CALLSEQ_START. 1135 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1136 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1137 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1138 NodesLeadingTo); 1139 } 1140 1141 // Now that we legalized all of the inputs (which may have inserted 1142 // libcalls) create the new CALLSEQ_START node. 1143 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1144 1145 // Merge in the last call, to ensure that this call start after the last 1146 // call ended. 1147 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1148 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1149 Tmp1 = LegalizeOp(Tmp1); 1150 } 1151 1152 // Do not try to legalize the target-specific arguments (#1+). 1153 if (Tmp1 != Node->getOperand(0)) { 1154 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1155 Ops[0] = Tmp1; 1156 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1157 } 1158 1159 // Remember that the CALLSEQ_START is legalized. 1160 AddLegalizedOperand(Op.getValue(0), Result); 1161 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1162 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1163 1164 // Now that the callseq_start and all of the non-call nodes above this call 1165 // sequence have been legalized, legalize the call itself. During this 1166 // process, no libcalls can/will be inserted, guaranteeing that no calls 1167 // can overlap. 1168 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1169 SDOperand InCallSEQ = LastCALLSEQ_END; 1170 // Note that we are selecting this call! 1171 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1172 IsLegalizingCall = true; 1173 1174 // Legalize the call, starting from the CALLSEQ_END. 1175 LegalizeOp(LastCALLSEQ_END); 1176 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1177 return Result; 1178 } 1179 case ISD::CALLSEQ_END: 1180 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1181 // will cause this node to be legalized as well as handling libcalls right. 1182 if (LastCALLSEQ_END.Val != Node) { 1183 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1184 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1185 assert(I != LegalizedNodes.end() && 1186 "Legalizing the call start should have legalized this node!"); 1187 return I->second; 1188 } 1189 1190 // Otherwise, the call start has been legalized and everything is going 1191 // according to plan. Just legalize ourselves normally here. 1192 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1193 // Do not try to legalize the target-specific arguments (#1+), except for 1194 // an optional flag input. 1195 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1196 if (Tmp1 != Node->getOperand(0)) { 1197 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1198 Ops[0] = Tmp1; 1199 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1200 } 1201 } else { 1202 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1203 if (Tmp1 != Node->getOperand(0) || 1204 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1205 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1206 Ops[0] = Tmp1; 1207 Ops.back() = Tmp2; 1208 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1209 } 1210 } 1211 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1212 // This finishes up call legalization. 1213 IsLegalizingCall = false; 1214 1215 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1216 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1217 if (Node->getNumValues() == 2) 1218 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1219 return Result.getValue(Op.ResNo); 1220 case ISD::DYNAMIC_STACKALLOC: { 1221 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1222 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1223 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1224 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1225 1226 Tmp1 = Result.getValue(0); 1227 Tmp2 = Result.getValue(1); 1228 switch (TLI.getOperationAction(Node->getOpcode(), 1229 Node->getValueType(0))) { 1230 default: assert(0 && "This action is not supported yet!"); 1231 case TargetLowering::Expand: { 1232 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1233 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1234 " not tell us which reg is the stack pointer!"); 1235 SDOperand Chain = Tmp1.getOperand(0); 1236 SDOperand Size = Tmp2.getOperand(1); 1237 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0)); 1238 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value 1239 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain 1240 Tmp1 = LegalizeOp(Tmp1); 1241 Tmp2 = LegalizeOp(Tmp2); 1242 break; 1243 } 1244 case TargetLowering::Custom: 1245 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1246 if (Tmp3.Val) { 1247 Tmp1 = LegalizeOp(Tmp3); 1248 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1249 } 1250 break; 1251 case TargetLowering::Legal: 1252 break; 1253 } 1254 // Since this op produce two values, make sure to remember that we 1255 // legalized both of them. 1256 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1257 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1258 return Op.ResNo ? Tmp2 : Tmp1; 1259 } 1260 case ISD::INLINEASM: { 1261 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1262 bool Changed = false; 1263 // Legalize all of the operands of the inline asm, in case they are nodes 1264 // that need to be expanded or something. Note we skip the asm string and 1265 // all of the TargetConstant flags. 1266 SDOperand Op = LegalizeOp(Ops[0]); 1267 Changed = Op != Ops[0]; 1268 Ops[0] = Op; 1269 1270 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1271 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1272 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1273 for (++i; NumVals; ++i, --NumVals) { 1274 SDOperand Op = LegalizeOp(Ops[i]); 1275 if (Op != Ops[i]) { 1276 Changed = true; 1277 Ops[i] = Op; 1278 } 1279 } 1280 } 1281 1282 if (HasInFlag) { 1283 Op = LegalizeOp(Ops.back()); 1284 Changed |= Op != Ops.back(); 1285 Ops.back() = Op; 1286 } 1287 1288 if (Changed) 1289 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1290 1291 // INLINE asm returns a chain and flag, make sure to add both to the map. 1292 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1293 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1294 return Result.getValue(Op.ResNo); 1295 } 1296 case ISD::BR: 1297 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1298 // Ensure that libcalls are emitted before a branch. 1299 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1300 Tmp1 = LegalizeOp(Tmp1); 1301 LastCALLSEQ_END = DAG.getEntryNode(); 1302 1303 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1304 break; 1305 case ISD::BRIND: 1306 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1307 // Ensure that libcalls are emitted before a branch. 1308 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1309 Tmp1 = LegalizeOp(Tmp1); 1310 LastCALLSEQ_END = DAG.getEntryNode(); 1311 1312 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1313 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1314 case Legal: 1315 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1316 break; 1317 } 1318 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1319 break; 1320 case ISD::BR_JT: 1321 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1322 // Ensure that libcalls are emitted before a branch. 1323 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1324 Tmp1 = LegalizeOp(Tmp1); 1325 LastCALLSEQ_END = DAG.getEntryNode(); 1326 1327 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1328 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1329 1330 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1331 default: assert(0 && "This action is not supported yet!"); 1332 case TargetLowering::Legal: break; 1333 case TargetLowering::Custom: 1334 Tmp1 = TLI.LowerOperation(Result, DAG); 1335 if (Tmp1.Val) Result = Tmp1; 1336 break; 1337 case TargetLowering::Expand: { 1338 SDOperand Chain = Result.getOperand(0); 1339 SDOperand Table = Result.getOperand(1); 1340 SDOperand Index = Result.getOperand(2); 1341 1342 MVT::ValueType PTy = TLI.getPointerTy(); 1343 MachineFunction &MF = DAG.getMachineFunction(); 1344 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1345 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1346 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1347 1348 SDOperand LD; 1349 switch (EntrySize) { 1350 default: assert(0 && "Size of jump table not supported yet."); break; 1351 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; 1352 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; 1353 } 1354 1355 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1356 // For PIC, the sequence is: 1357 // BRIND(load(Jumptable + index) + RelocBase) 1358 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha 1359 SDOperand Reloc; 1360 if (TLI.usesGlobalOffsetTable()) 1361 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy); 1362 else 1363 Reloc = Table; 1364 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD; 1365 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc); 1366 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1367 } else { 1368 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD); 1369 } 1370 } 1371 } 1372 break; 1373 case ISD::BRCOND: 1374 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1375 // Ensure that libcalls are emitted before a return. 1376 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1377 Tmp1 = LegalizeOp(Tmp1); 1378 LastCALLSEQ_END = DAG.getEntryNode(); 1379 1380 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1381 case Expand: assert(0 && "It's impossible to expand bools"); 1382 case Legal: 1383 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1384 break; 1385 case Promote: 1386 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1387 1388 // The top bits of the promoted condition are not necessarily zero, ensure 1389 // that the value is properly zero extended. 1390 if (!TLI.MaskedValueIsZero(Tmp2, 1391 MVT::getIntVTBitMask(Tmp2.getValueType())^1)) 1392 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1393 break; 1394 } 1395 1396 // Basic block destination (Op#2) is always legal. 1397 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1398 1399 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1400 default: assert(0 && "This action is not supported yet!"); 1401 case TargetLowering::Legal: break; 1402 case TargetLowering::Custom: 1403 Tmp1 = TLI.LowerOperation(Result, DAG); 1404 if (Tmp1.Val) Result = Tmp1; 1405 break; 1406 case TargetLowering::Expand: 1407 // Expand brcond's setcc into its constituent parts and create a BR_CC 1408 // Node. 1409 if (Tmp2.getOpcode() == ISD::SETCC) { 1410 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1411 Tmp2.getOperand(0), Tmp2.getOperand(1), 1412 Node->getOperand(2)); 1413 } else { 1414 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1415 DAG.getCondCode(ISD::SETNE), Tmp2, 1416 DAG.getConstant(0, Tmp2.getValueType()), 1417 Node->getOperand(2)); 1418 } 1419 break; 1420 } 1421 break; 1422 case ISD::BR_CC: 1423 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1424 // Ensure that libcalls are emitted before a branch. 1425 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1426 Tmp1 = LegalizeOp(Tmp1); 1427 Tmp2 = Node->getOperand(2); // LHS 1428 Tmp3 = Node->getOperand(3); // RHS 1429 Tmp4 = Node->getOperand(1); // CC 1430 1431 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1432 LastCALLSEQ_END = DAG.getEntryNode(); 1433 1434 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1435 // the LHS is a legal SETCC itself. In this case, we need to compare 1436 // the result against zero to select between true and false values. 1437 if (Tmp3.Val == 0) { 1438 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1439 Tmp4 = DAG.getCondCode(ISD::SETNE); 1440 } 1441 1442 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1443 Node->getOperand(4)); 1444 1445 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1446 default: assert(0 && "Unexpected action for BR_CC!"); 1447 case TargetLowering::Legal: break; 1448 case TargetLowering::Custom: 1449 Tmp4 = TLI.LowerOperation(Result, DAG); 1450 if (Tmp4.Val) Result = Tmp4; 1451 break; 1452 } 1453 break; 1454 case ISD::LOAD: { 1455 LoadSDNode *LD = cast<LoadSDNode>(Node); 1456 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1457 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1458 1459 ISD::LoadExtType ExtType = LD->getExtensionType(); 1460 if (ExtType == ISD::NON_EXTLOAD) { 1461 MVT::ValueType VT = Node->getValueType(0); 1462 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1463 Tmp3 = Result.getValue(0); 1464 Tmp4 = Result.getValue(1); 1465 1466 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1467 default: assert(0 && "This action is not supported yet!"); 1468 case TargetLowering::Legal: break; 1469 case TargetLowering::Custom: 1470 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1471 if (Tmp1.Val) { 1472 Tmp3 = LegalizeOp(Tmp1); 1473 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1474 } 1475 break; 1476 case TargetLowering::Promote: { 1477 // Only promote a load of vector type to another. 1478 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1479 // Change base type to a different vector type. 1480 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1481 1482 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1483 LD->getSrcValueOffset()); 1484 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1485 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1486 break; 1487 } 1488 } 1489 // Since loads produce two values, make sure to remember that we 1490 // legalized both of them. 1491 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1492 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1493 return Op.ResNo ? Tmp4 : Tmp3; 1494 } else { 1495 MVT::ValueType SrcVT = LD->getLoadedVT(); 1496 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1497 default: assert(0 && "This action is not supported yet!"); 1498 case TargetLowering::Promote: 1499 assert(SrcVT == MVT::i1 && 1500 "Can only promote extending LOAD from i1 -> i8!"); 1501 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1502 LD->getSrcValue(), LD->getSrcValueOffset(), 1503 MVT::i8); 1504 Tmp1 = Result.getValue(0); 1505 Tmp2 = Result.getValue(1); 1506 break; 1507 case TargetLowering::Custom: 1508 isCustom = true; 1509 // FALLTHROUGH 1510 case TargetLowering::Legal: 1511 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1512 Tmp1 = Result.getValue(0); 1513 Tmp2 = Result.getValue(1); 1514 1515 if (isCustom) { 1516 Tmp3 = TLI.LowerOperation(Result, DAG); 1517 if (Tmp3.Val) { 1518 Tmp1 = LegalizeOp(Tmp3); 1519 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1520 } 1521 } 1522 break; 1523 case TargetLowering::Expand: 1524 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1525 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1526 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 1527 LD->getSrcValueOffset()); 1528 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1529 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1530 Tmp2 = LegalizeOp(Load.getValue(1)); 1531 break; 1532 } 1533 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1534 // Turn the unsupported load into an EXTLOAD followed by an explicit 1535 // zero/sign extend inreg. 1536 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1537 Tmp1, Tmp2, LD->getSrcValue(), 1538 LD->getSrcValueOffset(), SrcVT); 1539 SDOperand ValRes; 1540 if (ExtType == ISD::SEXTLOAD) 1541 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1542 Result, DAG.getValueType(SrcVT)); 1543 else 1544 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1545 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1546 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1547 break; 1548 } 1549 // Since loads produce two values, make sure to remember that we legalized 1550 // both of them. 1551 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1552 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1553 return Op.ResNo ? Tmp2 : Tmp1; 1554 } 1555 } 1556 case ISD::EXTRACT_ELEMENT: { 1557 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1558 switch (getTypeAction(OpTy)) { 1559 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1560 case Legal: 1561 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1562 // 1 -> Hi 1563 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1564 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1565 TLI.getShiftAmountTy())); 1566 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1567 } else { 1568 // 0 -> Lo 1569 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1570 Node->getOperand(0)); 1571 } 1572 break; 1573 case Expand: 1574 // Get both the low and high parts. 1575 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1576 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1577 Result = Tmp2; // 1 -> Hi 1578 else 1579 Result = Tmp1; // 0 -> Lo 1580 break; 1581 } 1582 break; 1583 } 1584 1585 case ISD::CopyToReg: 1586 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1587 1588 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1589 "Register type must be legal!"); 1590 // Legalize the incoming value (must be a legal type). 1591 Tmp2 = LegalizeOp(Node->getOperand(2)); 1592 if (Node->getNumValues() == 1) { 1593 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1594 } else { 1595 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1596 if (Node->getNumOperands() == 4) { 1597 Tmp3 = LegalizeOp(Node->getOperand(3)); 1598 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1599 Tmp3); 1600 } else { 1601 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1602 } 1603 1604 // Since this produces two values, make sure to remember that we legalized 1605 // both of them. 1606 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1607 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1608 return Result; 1609 } 1610 break; 1611 1612 case ISD::RET: 1613 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1614 1615 // Ensure that libcalls are emitted before a return. 1616 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1617 Tmp1 = LegalizeOp(Tmp1); 1618 LastCALLSEQ_END = DAG.getEntryNode(); 1619 1620 switch (Node->getNumOperands()) { 1621 case 3: // ret val 1622 Tmp2 = Node->getOperand(1); 1623 Tmp3 = Node->getOperand(2); // Signness 1624 switch (getTypeAction(Tmp2.getValueType())) { 1625 case Legal: 1626 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1627 break; 1628 case Expand: 1629 if (Tmp2.getValueType() != MVT::Vector) { 1630 SDOperand Lo, Hi; 1631 ExpandOp(Tmp2, Lo, Hi); 1632 if (Hi.Val) 1633 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1634 else 1635 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 1636 Result = LegalizeOp(Result); 1637 } else { 1638 SDNode *InVal = Tmp2.Val; 1639 unsigned NumElems = 1640 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 1641 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 1642 1643 // Figure out if there is a Packed type corresponding to this Vector 1644 // type. If so, convert to the packed type. 1645 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1646 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 1647 // Turn this into a return of the packed type. 1648 Tmp2 = PackVectorOp(Tmp2, TVT); 1649 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1650 } else if (NumElems == 1) { 1651 // Turn this into a return of the scalar type. 1652 Tmp2 = PackVectorOp(Tmp2, EVT); 1653 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1654 1655 // FIXME: Returns of gcc generic vectors smaller than a legal type 1656 // should be returned in integer registers! 1657 1658 // The scalarized value type may not be legal, e.g. it might require 1659 // promotion or expansion. Relegalize the return. 1660 Result = LegalizeOp(Result); 1661 } else { 1662 // FIXME: Returns of gcc generic vectors larger than a legal vector 1663 // type should be returned by reference! 1664 SDOperand Lo, Hi; 1665 SplitVectorOp(Tmp2, Lo, Hi); 1666 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1667 Result = LegalizeOp(Result); 1668 } 1669 } 1670 break; 1671 case Promote: 1672 Tmp2 = PromoteOp(Node->getOperand(1)); 1673 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1674 Result = LegalizeOp(Result); 1675 break; 1676 } 1677 break; 1678 case 1: // ret void 1679 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1680 break; 1681 default: { // ret <values> 1682 SmallVector<SDOperand, 8> NewValues; 1683 NewValues.push_back(Tmp1); 1684 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 1685 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1686 case Legal: 1687 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1688 NewValues.push_back(Node->getOperand(i+1)); 1689 break; 1690 case Expand: { 1691 SDOperand Lo, Hi; 1692 assert(Node->getOperand(i).getValueType() != MVT::Vector && 1693 "FIXME: TODO: implement returning non-legal vector types!"); 1694 ExpandOp(Node->getOperand(i), Lo, Hi); 1695 NewValues.push_back(Lo); 1696 NewValues.push_back(Node->getOperand(i+1)); 1697 if (Hi.Val) { 1698 NewValues.push_back(Hi); 1699 NewValues.push_back(Node->getOperand(i+1)); 1700 } 1701 break; 1702 } 1703 case Promote: 1704 assert(0 && "Can't promote multiple return value yet!"); 1705 } 1706 1707 if (NewValues.size() == Node->getNumOperands()) 1708 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 1709 else 1710 Result = DAG.getNode(ISD::RET, MVT::Other, 1711 &NewValues[0], NewValues.size()); 1712 break; 1713 } 1714 } 1715 1716 if (Result.getOpcode() == ISD::RET) { 1717 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 1718 default: assert(0 && "This action is not supported yet!"); 1719 case TargetLowering::Legal: break; 1720 case TargetLowering::Custom: 1721 Tmp1 = TLI.LowerOperation(Result, DAG); 1722 if (Tmp1.Val) Result = Tmp1; 1723 break; 1724 } 1725 } 1726 break; 1727 case ISD::STORE: { 1728 StoreSDNode *ST = cast<StoreSDNode>(Node); 1729 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1730 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1731 1732 if (!ST->isTruncatingStore()) { 1733 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1734 // FIXME: We shouldn't do this for TargetConstantFP's. 1735 // FIXME: move this to the DAG Combiner! Note that we can't regress due 1736 // to phase ordering between legalized code and the dag combiner. This 1737 // probably means that we need to integrate dag combiner and legalizer 1738 // together. 1739 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 1740 if (CFP->getValueType(0) == MVT::f32) { 1741 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 1742 } else { 1743 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1744 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 1745 } 1746 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1747 ST->getSrcValueOffset()); 1748 break; 1749 } 1750 1751 switch (getTypeAction(ST->getStoredVT())) { 1752 case Legal: { 1753 Tmp3 = LegalizeOp(ST->getValue()); 1754 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1755 ST->getOffset()); 1756 1757 MVT::ValueType VT = Tmp3.getValueType(); 1758 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1759 default: assert(0 && "This action is not supported yet!"); 1760 case TargetLowering::Legal: break; 1761 case TargetLowering::Custom: 1762 Tmp1 = TLI.LowerOperation(Result, DAG); 1763 if (Tmp1.Val) Result = Tmp1; 1764 break; 1765 case TargetLowering::Promote: 1766 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 1767 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 1768 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1769 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 1770 ST->getSrcValue(), ST->getSrcValueOffset()); 1771 break; 1772 } 1773 break; 1774 } 1775 case Promote: 1776 // Truncate the value and store the result. 1777 Tmp3 = PromoteOp(ST->getValue()); 1778 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1779 ST->getSrcValueOffset(), ST->getStoredVT()); 1780 break; 1781 1782 case Expand: 1783 unsigned IncrementSize = 0; 1784 SDOperand Lo, Hi; 1785 1786 // If this is a vector type, then we have to calculate the increment as 1787 // the product of the element size in bytes, and the number of elements 1788 // in the high half of the vector. 1789 if (ST->getValue().getValueType() == MVT::Vector) { 1790 SDNode *InVal = ST->getValue().Val; 1791 unsigned NumElems = 1792 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 1793 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 1794 1795 // Figure out if there is a Packed type corresponding to this Vector 1796 // type. If so, convert to the packed type. 1797 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1798 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 1799 // Turn this into a normal store of the packed type. 1800 Tmp3 = PackVectorOp(Node->getOperand(1), TVT); 1801 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1802 ST->getSrcValueOffset()); 1803 Result = LegalizeOp(Result); 1804 break; 1805 } else if (NumElems == 1) { 1806 // Turn this into a normal store of the scalar type. 1807 Tmp3 = PackVectorOp(Node->getOperand(1), EVT); 1808 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1809 ST->getSrcValueOffset()); 1810 // The scalarized value type may not be legal, e.g. it might require 1811 // promotion or expansion. Relegalize the scalar store. 1812 Result = LegalizeOp(Result); 1813 break; 1814 } else { 1815 SplitVectorOp(Node->getOperand(1), Lo, Hi); 1816 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; 1817 } 1818 } else { 1819 ExpandOp(Node->getOperand(1), Lo, Hi); 1820 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 1821 1822 if (!TLI.isLittleEndian()) 1823 std::swap(Lo, Hi); 1824 } 1825 1826 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 1827 ST->getSrcValueOffset()); 1828 1829 if (Hi.Val == NULL) { 1830 // Must be int <-> float one-to-one expansion. 1831 Result = Lo; 1832 break; 1833 } 1834 1835 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1836 getIntPtrConstant(IncrementSize)); 1837 assert(isTypeLegal(Tmp2.getValueType()) && 1838 "Pointers must be legal!"); 1839 // FIXME: This sets the srcvalue of both halves to be the same, which is 1840 // wrong. 1841 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 1842 ST->getSrcValueOffset()); 1843 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1844 break; 1845 } 1846 } else { 1847 // Truncating store 1848 assert(isTypeLegal(ST->getValue().getValueType()) && 1849 "Cannot handle illegal TRUNCSTORE yet!"); 1850 Tmp3 = LegalizeOp(ST->getValue()); 1851 1852 // The only promote case we handle is TRUNCSTORE:i1 X into 1853 // -> TRUNCSTORE:i8 (and X, 1) 1854 if (ST->getStoredVT() == MVT::i1 && 1855 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) { 1856 // Promote the bool to a mask then store. 1857 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3, 1858 DAG.getConstant(1, Tmp3.getValueType())); 1859 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1860 ST->getSrcValueOffset(), MVT::i8); 1861 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1862 Tmp2 != ST->getBasePtr()) { 1863 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1864 ST->getOffset()); 1865 } 1866 1867 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT(); 1868 switch (TLI.getStoreXAction(StVT)) { 1869 default: assert(0 && "This action is not supported yet!"); 1870 case TargetLowering::Legal: break; 1871 case TargetLowering::Custom: 1872 Tmp1 = TLI.LowerOperation(Result, DAG); 1873 if (Tmp1.Val) Result = Tmp1; 1874 break; 1875 } 1876 } 1877 break; 1878 } 1879 case ISD::PCMARKER: 1880 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1881 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1882 break; 1883 case ISD::STACKSAVE: 1884 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1885 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1886 Tmp1 = Result.getValue(0); 1887 Tmp2 = Result.getValue(1); 1888 1889 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 1890 default: assert(0 && "This action is not supported yet!"); 1891 case TargetLowering::Legal: break; 1892 case TargetLowering::Custom: 1893 Tmp3 = TLI.LowerOperation(Result, DAG); 1894 if (Tmp3.Val) { 1895 Tmp1 = LegalizeOp(Tmp3); 1896 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1897 } 1898 break; 1899 case TargetLowering::Expand: 1900 // Expand to CopyFromReg if the target set 1901 // StackPointerRegisterToSaveRestore. 1902 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1903 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 1904 Node->getValueType(0)); 1905 Tmp2 = Tmp1.getValue(1); 1906 } else { 1907 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 1908 Tmp2 = Node->getOperand(0); 1909 } 1910 break; 1911 } 1912 1913 // Since stacksave produce two values, make sure to remember that we 1914 // legalized both of them. 1915 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1916 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1917 return Op.ResNo ? Tmp2 : Tmp1; 1918 1919 case ISD::STACKRESTORE: 1920 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1921 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1922 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1923 1924 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 1925 default: assert(0 && "This action is not supported yet!"); 1926 case TargetLowering::Legal: break; 1927 case TargetLowering::Custom: 1928 Tmp1 = TLI.LowerOperation(Result, DAG); 1929 if (Tmp1.Val) Result = Tmp1; 1930 break; 1931 case TargetLowering::Expand: 1932 // Expand to CopyToReg if the target set 1933 // StackPointerRegisterToSaveRestore. 1934 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1935 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 1936 } else { 1937 Result = Tmp1; 1938 } 1939 break; 1940 } 1941 break; 1942 1943 case ISD::READCYCLECOUNTER: 1944 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1945 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1946 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 1947 Node->getValueType(0))) { 1948 default: assert(0 && "This action is not supported yet!"); 1949 case TargetLowering::Legal: 1950 Tmp1 = Result.getValue(0); 1951 Tmp2 = Result.getValue(1); 1952 break; 1953 case TargetLowering::Custom: 1954 Result = TLI.LowerOperation(Result, DAG); 1955 Tmp1 = LegalizeOp(Result.getValue(0)); 1956 Tmp2 = LegalizeOp(Result.getValue(1)); 1957 break; 1958 } 1959 1960 // Since rdcc produce two values, make sure to remember that we legalized 1961 // both of them. 1962 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1963 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1964 return Result; 1965 1966 case ISD::SELECT: 1967 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1968 case Expand: assert(0 && "It's impossible to expand bools"); 1969 case Legal: 1970 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1971 break; 1972 case Promote: 1973 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1974 // Make sure the condition is either zero or one. 1975 if (!TLI.MaskedValueIsZero(Tmp1, 1976 MVT::getIntVTBitMask(Tmp1.getValueType())^1)) 1977 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1978 break; 1979 } 1980 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1981 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1982 1983 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1984 1985 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1986 default: assert(0 && "This action is not supported yet!"); 1987 case TargetLowering::Legal: break; 1988 case TargetLowering::Custom: { 1989 Tmp1 = TLI.LowerOperation(Result, DAG); 1990 if (Tmp1.Val) Result = Tmp1; 1991 break; 1992 } 1993 case TargetLowering::Expand: 1994 if (Tmp1.getOpcode() == ISD::SETCC) { 1995 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1996 Tmp2, Tmp3, 1997 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1998 } else { 1999 Result = DAG.getSelectCC(Tmp1, 2000 DAG.getConstant(0, Tmp1.getValueType()), 2001 Tmp2, Tmp3, ISD::SETNE); 2002 } 2003 break; 2004 case TargetLowering::Promote: { 2005 MVT::ValueType NVT = 2006 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2007 unsigned ExtOp, TruncOp; 2008 if (MVT::isVector(Tmp2.getValueType())) { 2009 ExtOp = ISD::BIT_CONVERT; 2010 TruncOp = ISD::BIT_CONVERT; 2011 } else if (MVT::isInteger(Tmp2.getValueType())) { 2012 ExtOp = ISD::ANY_EXTEND; 2013 TruncOp = ISD::TRUNCATE; 2014 } else { 2015 ExtOp = ISD::FP_EXTEND; 2016 TruncOp = ISD::FP_ROUND; 2017 } 2018 // Promote each of the values to the new type. 2019 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2020 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2021 // Perform the larger operation, then round down. 2022 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2023 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2024 break; 2025 } 2026 } 2027 break; 2028 case ISD::SELECT_CC: { 2029 Tmp1 = Node->getOperand(0); // LHS 2030 Tmp2 = Node->getOperand(1); // RHS 2031 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2032 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2033 SDOperand CC = Node->getOperand(4); 2034 2035 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2036 2037 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2038 // the LHS is a legal SETCC itself. In this case, we need to compare 2039 // the result against zero to select between true and false values. 2040 if (Tmp2.Val == 0) { 2041 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2042 CC = DAG.getCondCode(ISD::SETNE); 2043 } 2044 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2045 2046 // Everything is legal, see if we should expand this op or something. 2047 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2048 default: assert(0 && "This action is not supported yet!"); 2049 case TargetLowering::Legal: break; 2050 case TargetLowering::Custom: 2051 Tmp1 = TLI.LowerOperation(Result, DAG); 2052 if (Tmp1.Val) Result = Tmp1; 2053 break; 2054 } 2055 break; 2056 } 2057 case ISD::SETCC: 2058 Tmp1 = Node->getOperand(0); 2059 Tmp2 = Node->getOperand(1); 2060 Tmp3 = Node->getOperand(2); 2061 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2062 2063 // If we had to Expand the SetCC operands into a SELECT node, then it may 2064 // not always be possible to return a true LHS & RHS. In this case, just 2065 // return the value we legalized, returned in the LHS 2066 if (Tmp2.Val == 0) { 2067 Result = Tmp1; 2068 break; 2069 } 2070 2071 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2072 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2073 case TargetLowering::Custom: 2074 isCustom = true; 2075 // FALLTHROUGH. 2076 case TargetLowering::Legal: 2077 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2078 if (isCustom) { 2079 Tmp4 = TLI.LowerOperation(Result, DAG); 2080 if (Tmp4.Val) Result = Tmp4; 2081 } 2082 break; 2083 case TargetLowering::Promote: { 2084 // First step, figure out the appropriate operation to use. 2085 // Allow SETCC to not be supported for all legal data types 2086 // Mostly this targets FP 2087 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2088 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2089 2090 // Scan for the appropriate larger type to use. 2091 while (1) { 2092 NewInTy = (MVT::ValueType)(NewInTy+1); 2093 2094 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2095 "Fell off of the edge of the integer world"); 2096 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2097 "Fell off of the edge of the floating point world"); 2098 2099 // If the target supports SETCC of this type, use it. 2100 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2101 break; 2102 } 2103 if (MVT::isInteger(NewInTy)) 2104 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2105 else { 2106 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2107 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2108 } 2109 Tmp1 = LegalizeOp(Tmp1); 2110 Tmp2 = LegalizeOp(Tmp2); 2111 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2112 Result = LegalizeOp(Result); 2113 break; 2114 } 2115 case TargetLowering::Expand: 2116 // Expand a setcc node into a select_cc of the same condition, lhs, and 2117 // rhs that selects between const 1 (true) and const 0 (false). 2118 MVT::ValueType VT = Node->getValueType(0); 2119 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2120 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2121 Tmp3); 2122 break; 2123 } 2124 break; 2125 case ISD::MEMSET: 2126 case ISD::MEMCPY: 2127 case ISD::MEMMOVE: { 2128 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2129 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2130 2131 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2132 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2133 case Expand: assert(0 && "Cannot expand a byte!"); 2134 case Legal: 2135 Tmp3 = LegalizeOp(Node->getOperand(2)); 2136 break; 2137 case Promote: 2138 Tmp3 = PromoteOp(Node->getOperand(2)); 2139 break; 2140 } 2141 } else { 2142 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2143 } 2144 2145 SDOperand Tmp4; 2146 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2147 case Expand: { 2148 // Length is too big, just take the lo-part of the length. 2149 SDOperand HiPart; 2150 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2151 break; 2152 } 2153 case Legal: 2154 Tmp4 = LegalizeOp(Node->getOperand(3)); 2155 break; 2156 case Promote: 2157 Tmp4 = PromoteOp(Node->getOperand(3)); 2158 break; 2159 } 2160 2161 SDOperand Tmp5; 2162 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2163 case Expand: assert(0 && "Cannot expand this yet!"); 2164 case Legal: 2165 Tmp5 = LegalizeOp(Node->getOperand(4)); 2166 break; 2167 case Promote: 2168 Tmp5 = PromoteOp(Node->getOperand(4)); 2169 break; 2170 } 2171 2172 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2173 default: assert(0 && "This action not implemented for this operation!"); 2174 case TargetLowering::Custom: 2175 isCustom = true; 2176 // FALLTHROUGH 2177 case TargetLowering::Legal: 2178 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 2179 if (isCustom) { 2180 Tmp1 = TLI.LowerOperation(Result, DAG); 2181 if (Tmp1.Val) Result = Tmp1; 2182 } 2183 break; 2184 case TargetLowering::Expand: { 2185 // Otherwise, the target does not support this operation. Lower the 2186 // operation to an explicit libcall as appropriate. 2187 MVT::ValueType IntPtr = TLI.getPointerTy(); 2188 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2189 TargetLowering::ArgListTy Args; 2190 TargetLowering::ArgListEntry Entry; 2191 2192 const char *FnName = 0; 2193 if (Node->getOpcode() == ISD::MEMSET) { 2194 Entry.Node = Tmp2; Entry.isSigned = false; Entry.Ty = IntPtrTy; 2195 Entry.isInReg = false; Entry.isSRet = false; 2196 Args.push_back(Entry); 2197 // Extend the (previously legalized) ubyte argument to be an int value 2198 // for the call. 2199 if (Tmp3.getValueType() > MVT::i32) 2200 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2201 else 2202 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2203 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSigned = true; 2204 Entry.isInReg = false; Entry.isSRet = false; 2205 Args.push_back(Entry); 2206 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSigned = false; 2207 Args.push_back(Entry); 2208 2209 FnName = "memset"; 2210 } else if (Node->getOpcode() == ISD::MEMCPY || 2211 Node->getOpcode() == ISD::MEMMOVE) { 2212 Entry.Ty = IntPtrTy; 2213 Entry.isSigned = false; Entry.isInReg = false; Entry.isSRet = false; 2214 Entry.Node = Tmp2; Args.push_back(Entry); 2215 Entry.Node = Tmp3; Args.push_back(Entry); 2216 Entry.Node = Tmp4; Args.push_back(Entry); 2217 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2218 } else { 2219 assert(0 && "Unknown op!"); 2220 } 2221 2222 std::pair<SDOperand,SDOperand> CallResult = 2223 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 2224 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2225 Result = CallResult.second; 2226 break; 2227 } 2228 } 2229 break; 2230 } 2231 2232 case ISD::SHL_PARTS: 2233 case ISD::SRA_PARTS: 2234 case ISD::SRL_PARTS: { 2235 SmallVector<SDOperand, 8> Ops; 2236 bool Changed = false; 2237 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2238 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2239 Changed |= Ops.back() != Node->getOperand(i); 2240 } 2241 if (Changed) 2242 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2243 2244 switch (TLI.getOperationAction(Node->getOpcode(), 2245 Node->getValueType(0))) { 2246 default: assert(0 && "This action is not supported yet!"); 2247 case TargetLowering::Legal: break; 2248 case TargetLowering::Custom: 2249 Tmp1 = TLI.LowerOperation(Result, DAG); 2250 if (Tmp1.Val) { 2251 SDOperand Tmp2, RetVal(0, 0); 2252 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2253 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2254 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2255 if (i == Op.ResNo) 2256 RetVal = Tmp2; 2257 } 2258 assert(RetVal.Val && "Illegal result number"); 2259 return RetVal; 2260 } 2261 break; 2262 } 2263 2264 // Since these produce multiple values, make sure to remember that we 2265 // legalized all of them. 2266 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2267 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2268 return Result.getValue(Op.ResNo); 2269 } 2270 2271 // Binary operators 2272 case ISD::ADD: 2273 case ISD::SUB: 2274 case ISD::MUL: 2275 case ISD::MULHS: 2276 case ISD::MULHU: 2277 case ISD::UDIV: 2278 case ISD::SDIV: 2279 case ISD::AND: 2280 case ISD::OR: 2281 case ISD::XOR: 2282 case ISD::SHL: 2283 case ISD::SRL: 2284 case ISD::SRA: 2285 case ISD::FADD: 2286 case ISD::FSUB: 2287 case ISD::FMUL: 2288 case ISD::FDIV: 2289 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2290 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2291 case Expand: assert(0 && "Not possible"); 2292 case Legal: 2293 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2294 break; 2295 case Promote: 2296 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2297 break; 2298 } 2299 2300 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2301 2302 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2303 default: assert(0 && "BinOp legalize operation not supported"); 2304 case TargetLowering::Legal: break; 2305 case TargetLowering::Custom: 2306 Tmp1 = TLI.LowerOperation(Result, DAG); 2307 if (Tmp1.Val) Result = Tmp1; 2308 break; 2309 case TargetLowering::Expand: { 2310 if (Node->getValueType(0) == MVT::i32) { 2311 switch (Node->getOpcode()) { 2312 default: assert(0 && "Do not know how to expand this integer BinOp!"); 2313 case ISD::UDIV: 2314 case ISD::SDIV: 2315 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV 2316 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 2317 SDOperand Dummy; 2318 bool isSigned = Node->getOpcode() == ISD::SDIV; 2319 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2320 }; 2321 break; 2322 } 2323 2324 assert(MVT::isVector(Node->getValueType(0)) && 2325 "Cannot expand this binary operator!"); 2326 // Expand the operation into a bunch of nasty scalar code. 2327 SmallVector<SDOperand, 8> Ops; 2328 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0)); 2329 MVT::ValueType PtrVT = TLI.getPointerTy(); 2330 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0)); 2331 i != e; ++i) { 2332 SDOperand Idx = DAG.getConstant(i, PtrVT); 2333 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx); 2334 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx); 2335 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS)); 2336 } 2337 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), 2338 &Ops[0], Ops.size()); 2339 break; 2340 } 2341 case TargetLowering::Promote: { 2342 switch (Node->getOpcode()) { 2343 default: assert(0 && "Do not know how to promote this BinOp!"); 2344 case ISD::AND: 2345 case ISD::OR: 2346 case ISD::XOR: { 2347 MVT::ValueType OVT = Node->getValueType(0); 2348 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2349 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2350 // Bit convert each of the values to the new type. 2351 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2352 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2353 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2354 // Bit convert the result back the original type. 2355 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2356 break; 2357 } 2358 } 2359 } 2360 } 2361 break; 2362 2363 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2364 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2365 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2366 case Expand: assert(0 && "Not possible"); 2367 case Legal: 2368 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2369 break; 2370 case Promote: 2371 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2372 break; 2373 } 2374 2375 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2376 2377 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2378 default: assert(0 && "Operation not supported"); 2379 case TargetLowering::Custom: 2380 Tmp1 = TLI.LowerOperation(Result, DAG); 2381 if (Tmp1.Val) Result = Tmp1; 2382 break; 2383 case TargetLowering::Legal: break; 2384 case TargetLowering::Expand: { 2385 // If this target supports fabs/fneg natively and select is cheap, 2386 // do this efficiently. 2387 if (!TLI.isSelectExpensive() && 2388 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 2389 TargetLowering::Legal && 2390 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 2391 TargetLowering::Legal) { 2392 // Get the sign bit of the RHS. 2393 MVT::ValueType IVT = 2394 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2395 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2396 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2397 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2398 // Get the absolute value of the result. 2399 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2400 // Select between the nabs and abs value based on the sign bit of 2401 // the input. 2402 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2403 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2404 AbsVal), 2405 AbsVal); 2406 Result = LegalizeOp(Result); 2407 break; 2408 } 2409 2410 // Otherwise, do bitwise ops! 2411 MVT::ValueType NVT = 2412 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 2413 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 2414 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 2415 Result = LegalizeOp(Result); 2416 break; 2417 } 2418 } 2419 break; 2420 2421 case ISD::ADDC: 2422 case ISD::SUBC: 2423 Tmp1 = LegalizeOp(Node->getOperand(0)); 2424 Tmp2 = LegalizeOp(Node->getOperand(1)); 2425 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2426 // Since this produces two values, make sure to remember that we legalized 2427 // both of them. 2428 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2429 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2430 return Result; 2431 2432 case ISD::ADDE: 2433 case ISD::SUBE: 2434 Tmp1 = LegalizeOp(Node->getOperand(0)); 2435 Tmp2 = LegalizeOp(Node->getOperand(1)); 2436 Tmp3 = LegalizeOp(Node->getOperand(2)); 2437 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2438 // Since this produces two values, make sure to remember that we legalized 2439 // both of them. 2440 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2441 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2442 return Result; 2443 2444 case ISD::BUILD_PAIR: { 2445 MVT::ValueType PairTy = Node->getValueType(0); 2446 // TODO: handle the case where the Lo and Hi operands are not of legal type 2447 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2448 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2449 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2450 case TargetLowering::Promote: 2451 case TargetLowering::Custom: 2452 assert(0 && "Cannot promote/custom this yet!"); 2453 case TargetLowering::Legal: 2454 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2455 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2456 break; 2457 case TargetLowering::Expand: 2458 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2459 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2460 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2461 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2462 TLI.getShiftAmountTy())); 2463 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2464 break; 2465 } 2466 break; 2467 } 2468 2469 case ISD::UREM: 2470 case ISD::SREM: 2471 case ISD::FREM: 2472 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2473 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2474 2475 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2476 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2477 case TargetLowering::Custom: 2478 isCustom = true; 2479 // FALLTHROUGH 2480 case TargetLowering::Legal: 2481 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2482 if (isCustom) { 2483 Tmp1 = TLI.LowerOperation(Result, DAG); 2484 if (Tmp1.Val) Result = Tmp1; 2485 } 2486 break; 2487 case TargetLowering::Expand: 2488 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2489 bool isSigned = DivOpc == ISD::SDIV; 2490 if (MVT::isInteger(Node->getValueType(0))) { 2491 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) == 2492 TargetLowering::Legal) { 2493 // X % Y -> X-X/Y*Y 2494 MVT::ValueType VT = Node->getValueType(0); 2495 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 2496 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2497 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2498 } else { 2499 assert(Node->getValueType(0) == MVT::i32 && 2500 "Cannot expand this binary operator!"); 2501 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 2502 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 2503 SDOperand Dummy; 2504 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2505 } 2506 } else { 2507 // Floating point mod -> fmod libcall. 2508 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32 2509 ? RTLIB::REM_F32 : RTLIB::REM_F64; 2510 SDOperand Dummy; 2511 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2512 false/*sign irrelevant*/, Dummy); 2513 } 2514 break; 2515 } 2516 break; 2517 case ISD::VAARG: { 2518 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2519 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2520 2521 MVT::ValueType VT = Node->getValueType(0); 2522 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2523 default: assert(0 && "This action is not supported yet!"); 2524 case TargetLowering::Custom: 2525 isCustom = true; 2526 // FALLTHROUGH 2527 case TargetLowering::Legal: 2528 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2529 Result = Result.getValue(0); 2530 Tmp1 = Result.getValue(1); 2531 2532 if (isCustom) { 2533 Tmp2 = TLI.LowerOperation(Result, DAG); 2534 if (Tmp2.Val) { 2535 Result = LegalizeOp(Tmp2); 2536 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 2537 } 2538 } 2539 break; 2540 case TargetLowering::Expand: { 2541 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 2542 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2543 SV->getValue(), SV->getOffset()); 2544 // Increment the pointer, VAList, to the next vaarg 2545 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2546 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2547 TLI.getPointerTy())); 2548 // Store the incremented VAList to the legalized pointer 2549 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 2550 SV->getOffset()); 2551 // Load the actual argument out of the pointer VAList 2552 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 2553 Tmp1 = LegalizeOp(Result.getValue(1)); 2554 Result = LegalizeOp(Result); 2555 break; 2556 } 2557 } 2558 // Since VAARG produces two values, make sure to remember that we 2559 // legalized both of them. 2560 AddLegalizedOperand(SDOperand(Node, 0), Result); 2561 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 2562 return Op.ResNo ? Tmp1 : Result; 2563 } 2564 2565 case ISD::VACOPY: 2566 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2567 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 2568 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 2569 2570 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 2571 default: assert(0 && "This action is not supported yet!"); 2572 case TargetLowering::Custom: 2573 isCustom = true; 2574 // FALLTHROUGH 2575 case TargetLowering::Legal: 2576 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 2577 Node->getOperand(3), Node->getOperand(4)); 2578 if (isCustom) { 2579 Tmp1 = TLI.LowerOperation(Result, DAG); 2580 if (Tmp1.Val) Result = Tmp1; 2581 } 2582 break; 2583 case TargetLowering::Expand: 2584 // This defaults to loading a pointer from the input and storing it to the 2585 // output, returning the chain. 2586 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); 2587 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); 2588 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), 2589 SVD->getOffset()); 2590 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), 2591 SVS->getOffset()); 2592 break; 2593 } 2594 break; 2595 2596 case ISD::VAEND: 2597 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2598 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2599 2600 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 2601 default: assert(0 && "This action is not supported yet!"); 2602 case TargetLowering::Custom: 2603 isCustom = true; 2604 // FALLTHROUGH 2605 case TargetLowering::Legal: 2606 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2607 if (isCustom) { 2608 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 2609 if (Tmp1.Val) Result = Tmp1; 2610 } 2611 break; 2612 case TargetLowering::Expand: 2613 Result = Tmp1; // Default to a no-op, return the chain 2614 break; 2615 } 2616 break; 2617 2618 case ISD::VASTART: 2619 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2620 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2621 2622 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2623 2624 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 2625 default: assert(0 && "This action is not supported yet!"); 2626 case TargetLowering::Legal: break; 2627 case TargetLowering::Custom: 2628 Tmp1 = TLI.LowerOperation(Result, DAG); 2629 if (Tmp1.Val) Result = Tmp1; 2630 break; 2631 } 2632 break; 2633 2634 case ISD::ROTL: 2635 case ISD::ROTR: 2636 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2637 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2638 2639 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 2640 "Cannot handle this yet!"); 2641 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2642 break; 2643 2644 case ISD::BSWAP: 2645 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2646 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2647 case TargetLowering::Custom: 2648 assert(0 && "Cannot custom legalize this yet!"); 2649 case TargetLowering::Legal: 2650 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2651 break; 2652 case TargetLowering::Promote: { 2653 MVT::ValueType OVT = Tmp1.getValueType(); 2654 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2655 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT); 2656 2657 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2658 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 2659 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 2660 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 2661 break; 2662 } 2663 case TargetLowering::Expand: 2664 Result = ExpandBSWAP(Tmp1); 2665 break; 2666 } 2667 break; 2668 2669 case ISD::CTPOP: 2670 case ISD::CTTZ: 2671 case ISD::CTLZ: 2672 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2673 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2674 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!"); 2675 case TargetLowering::Legal: 2676 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2677 break; 2678 case TargetLowering::Promote: { 2679 MVT::ValueType OVT = Tmp1.getValueType(); 2680 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2681 2682 // Zero extend the argument. 2683 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2684 // Perform the larger operation, then subtract if needed. 2685 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2686 switch (Node->getOpcode()) { 2687 case ISD::CTPOP: 2688 Result = Tmp1; 2689 break; 2690 case ISD::CTTZ: 2691 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2692 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2693 DAG.getConstant(getSizeInBits(NVT), NVT), 2694 ISD::SETEQ); 2695 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2696 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 2697 break; 2698 case ISD::CTLZ: 2699 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2700 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2701 DAG.getConstant(getSizeInBits(NVT) - 2702 getSizeInBits(OVT), NVT)); 2703 break; 2704 } 2705 break; 2706 } 2707 case TargetLowering::Expand: 2708 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 2709 break; 2710 } 2711 break; 2712 2713 // Unary operators 2714 case ISD::FABS: 2715 case ISD::FNEG: 2716 case ISD::FSQRT: 2717 case ISD::FSIN: 2718 case ISD::FCOS: 2719 Tmp1 = LegalizeOp(Node->getOperand(0)); 2720 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2721 case TargetLowering::Promote: 2722 case TargetLowering::Custom: 2723 isCustom = true; 2724 // FALLTHROUGH 2725 case TargetLowering::Legal: 2726 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2727 if (isCustom) { 2728 Tmp1 = TLI.LowerOperation(Result, DAG); 2729 if (Tmp1.Val) Result = Tmp1; 2730 } 2731 break; 2732 case TargetLowering::Expand: 2733 switch (Node->getOpcode()) { 2734 default: assert(0 && "Unreachable!"); 2735 case ISD::FNEG: 2736 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2737 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2738 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 2739 break; 2740 case ISD::FABS: { 2741 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2742 MVT::ValueType VT = Node->getValueType(0); 2743 Tmp2 = DAG.getConstantFP(0.0, VT); 2744 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2745 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2746 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2747 break; 2748 } 2749 case ISD::FSQRT: 2750 case ISD::FSIN: 2751 case ISD::FCOS: { 2752 MVT::ValueType VT = Node->getValueType(0); 2753 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2754 switch(Node->getOpcode()) { 2755 case ISD::FSQRT: 2756 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64; 2757 break; 2758 case ISD::FSIN: 2759 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 2760 break; 2761 case ISD::FCOS: 2762 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64; 2763 break; 2764 default: assert(0 && "Unreachable!"); 2765 } 2766 SDOperand Dummy; 2767 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2768 false/*sign irrelevant*/, Dummy); 2769 break; 2770 } 2771 } 2772 break; 2773 } 2774 break; 2775 case ISD::FPOWI: { 2776 // We always lower FPOWI into a libcall. No target support it yet. 2777 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32 2778 ? RTLIB::POWI_F32 : RTLIB::POWI_F64; 2779 SDOperand Dummy; 2780 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2781 false/*sign irrelevant*/, Dummy); 2782 break; 2783 } 2784 case ISD::BIT_CONVERT: 2785 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 2786 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2787 } else { 2788 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 2789 Node->getOperand(0).getValueType())) { 2790 default: assert(0 && "Unknown operation action!"); 2791 case TargetLowering::Expand: 2792 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2793 break; 2794 case TargetLowering::Legal: 2795 Tmp1 = LegalizeOp(Node->getOperand(0)); 2796 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2797 break; 2798 } 2799 } 2800 break; 2801 case ISD::VBIT_CONVERT: { 2802 assert(Op.getOperand(0).getValueType() == MVT::Vector && 2803 "Can only have VBIT_CONVERT where input or output is MVT::Vector!"); 2804 2805 // The input has to be a vector type, we have to either scalarize it, pack 2806 // it, or convert it based on whether the input vector type is legal. 2807 SDNode *InVal = Node->getOperand(0).Val; 2808 unsigned NumElems = 2809 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 2810 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 2811 2812 // Figure out if there is a Packed type corresponding to this Vector 2813 // type. If so, convert to the packed type. 2814 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2815 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 2816 // Turn this into a bit convert of the packed input. 2817 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2818 PackVectorOp(Node->getOperand(0), TVT)); 2819 break; 2820 } else if (NumElems == 1) { 2821 // Turn this into a bit convert of the scalar input. 2822 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2823 PackVectorOp(Node->getOperand(0), EVT)); 2824 break; 2825 } else { 2826 // FIXME: UNIMP! Store then reload 2827 assert(0 && "Cast from unsupported vector type not implemented yet!"); 2828 } 2829 } 2830 2831 // Conversion operators. The source and destination have different types. 2832 case ISD::SINT_TO_FP: 2833 case ISD::UINT_TO_FP: { 2834 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2835 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2836 case Legal: 2837 switch (TLI.getOperationAction(Node->getOpcode(), 2838 Node->getOperand(0).getValueType())) { 2839 default: assert(0 && "Unknown operation action!"); 2840 case TargetLowering::Custom: 2841 isCustom = true; 2842 // FALLTHROUGH 2843 case TargetLowering::Legal: 2844 Tmp1 = LegalizeOp(Node->getOperand(0)); 2845 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2846 if (isCustom) { 2847 Tmp1 = TLI.LowerOperation(Result, DAG); 2848 if (Tmp1.Val) Result = Tmp1; 2849 } 2850 break; 2851 case TargetLowering::Expand: 2852 Result = ExpandLegalINT_TO_FP(isSigned, 2853 LegalizeOp(Node->getOperand(0)), 2854 Node->getValueType(0)); 2855 break; 2856 case TargetLowering::Promote: 2857 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2858 Node->getValueType(0), 2859 isSigned); 2860 break; 2861 } 2862 break; 2863 case Expand: 2864 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2865 Node->getValueType(0), Node->getOperand(0)); 2866 break; 2867 case Promote: 2868 Tmp1 = PromoteOp(Node->getOperand(0)); 2869 if (isSigned) { 2870 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 2871 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 2872 } else { 2873 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 2874 Node->getOperand(0).getValueType()); 2875 } 2876 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2877 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 2878 break; 2879 } 2880 break; 2881 } 2882 case ISD::TRUNCATE: 2883 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2884 case Legal: 2885 Tmp1 = LegalizeOp(Node->getOperand(0)); 2886 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2887 break; 2888 case Expand: 2889 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2890 2891 // Since the result is legal, we should just be able to truncate the low 2892 // part of the source. 2893 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2894 break; 2895 case Promote: 2896 Result = PromoteOp(Node->getOperand(0)); 2897 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2898 break; 2899 } 2900 break; 2901 2902 case ISD::FP_TO_SINT: 2903 case ISD::FP_TO_UINT: 2904 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2905 case Legal: 2906 Tmp1 = LegalizeOp(Node->getOperand(0)); 2907 2908 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2909 default: assert(0 && "Unknown operation action!"); 2910 case TargetLowering::Custom: 2911 isCustom = true; 2912 // FALLTHROUGH 2913 case TargetLowering::Legal: 2914 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2915 if (isCustom) { 2916 Tmp1 = TLI.LowerOperation(Result, DAG); 2917 if (Tmp1.Val) Result = Tmp1; 2918 } 2919 break; 2920 case TargetLowering::Promote: 2921 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2922 Node->getOpcode() == ISD::FP_TO_SINT); 2923 break; 2924 case TargetLowering::Expand: 2925 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2926 SDOperand True, False; 2927 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2928 MVT::ValueType NVT = Node->getValueType(0); 2929 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2930 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2931 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2932 Node->getOperand(0), Tmp2, ISD::SETLT); 2933 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2934 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2935 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2936 Tmp2)); 2937 False = DAG.getNode(ISD::XOR, NVT, False, 2938 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2939 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 2940 break; 2941 } else { 2942 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2943 } 2944 break; 2945 } 2946 break; 2947 case Expand: { 2948 // Convert f32 / f64 to i32 / i64. 2949 MVT::ValueType VT = Op.getValueType(); 2950 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2951 switch (Node->getOpcode()) { 2952 case ISD::FP_TO_SINT: 2953 if (Node->getOperand(0).getValueType() == MVT::f32) 2954 LC = (VT == MVT::i32) 2955 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 2956 else 2957 LC = (VT == MVT::i32) 2958 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 2959 break; 2960 case ISD::FP_TO_UINT: 2961 if (Node->getOperand(0).getValueType() == MVT::f32) 2962 LC = (VT == MVT::i32) 2963 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 2964 else 2965 LC = (VT == MVT::i32) 2966 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 2967 break; 2968 default: assert(0 && "Unreachable!"); 2969 } 2970 SDOperand Dummy; 2971 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2972 false/*sign irrelevant*/, Dummy); 2973 break; 2974 } 2975 case Promote: 2976 Tmp1 = PromoteOp(Node->getOperand(0)); 2977 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 2978 Result = LegalizeOp(Result); 2979 break; 2980 } 2981 break; 2982 2983 case ISD::ANY_EXTEND: 2984 case ISD::ZERO_EXTEND: 2985 case ISD::SIGN_EXTEND: 2986 case ISD::FP_EXTEND: 2987 case ISD::FP_ROUND: 2988 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2989 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 2990 case Legal: 2991 Tmp1 = LegalizeOp(Node->getOperand(0)); 2992 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2993 break; 2994 case Promote: 2995 switch (Node->getOpcode()) { 2996 case ISD::ANY_EXTEND: 2997 Tmp1 = PromoteOp(Node->getOperand(0)); 2998 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 2999 break; 3000 case ISD::ZERO_EXTEND: 3001 Result = PromoteOp(Node->getOperand(0)); 3002 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3003 Result = DAG.getZeroExtendInReg(Result, 3004 Node->getOperand(0).getValueType()); 3005 break; 3006 case ISD::SIGN_EXTEND: 3007 Result = PromoteOp(Node->getOperand(0)); 3008 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3009 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3010 Result, 3011 DAG.getValueType(Node->getOperand(0).getValueType())); 3012 break; 3013 case ISD::FP_EXTEND: 3014 Result = PromoteOp(Node->getOperand(0)); 3015 if (Result.getValueType() != Op.getValueType()) 3016 // Dynamically dead while we have only 2 FP types. 3017 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 3018 break; 3019 case ISD::FP_ROUND: 3020 Result = PromoteOp(Node->getOperand(0)); 3021 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 3022 break; 3023 } 3024 } 3025 break; 3026 case ISD::FP_ROUND_INREG: 3027 case ISD::SIGN_EXTEND_INREG: { 3028 Tmp1 = LegalizeOp(Node->getOperand(0)); 3029 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3030 3031 // If this operation is not supported, convert it to a shl/shr or load/store 3032 // pair. 3033 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3034 default: assert(0 && "This action not supported for this op yet!"); 3035 case TargetLowering::Legal: 3036 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3037 break; 3038 case TargetLowering::Expand: 3039 // If this is an integer extend and shifts are supported, do that. 3040 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3041 // NOTE: we could fall back on load/store here too for targets without 3042 // SAR. However, it is doubtful that any exist. 3043 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3044 MVT::getSizeInBits(ExtraVT); 3045 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3046 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3047 Node->getOperand(0), ShiftCst); 3048 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3049 Result, ShiftCst); 3050 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3051 // The only way we can lower this is to turn it into a TRUNCSTORE, 3052 // EXTLOAD pair, targetting a temporary location (a stack slot). 3053 3054 // NOTE: there is a choice here between constantly creating new stack 3055 // slots and always reusing the same one. We currently always create 3056 // new ones, as reuse may inhibit scheduling. 3057 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 3058 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty); 3059 unsigned Align = TLI.getTargetData()->getTypeAlignmentPref(Ty); 3060 MachineFunction &MF = DAG.getMachineFunction(); 3061 int SSFI = 3062 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 3063 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3064 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3065 StackSlot, NULL, 0, ExtraVT); 3066 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 3067 Result, StackSlot, NULL, 0, ExtraVT); 3068 } else { 3069 assert(0 && "Unknown op"); 3070 } 3071 break; 3072 } 3073 break; 3074 } 3075 } 3076 3077 assert(Result.getValueType() == Op.getValueType() && 3078 "Bad legalization!"); 3079 3080 // Make sure that the generated code is itself legal. 3081 if (Result != Op) 3082 Result = LegalizeOp(Result); 3083 3084 // Note that LegalizeOp may be reentered even from single-use nodes, which 3085 // means that we always must cache transformed nodes. 3086 AddLegalizedOperand(Op, Result); 3087 return Result; 3088} 3089 3090/// PromoteOp - Given an operation that produces a value in an invalid type, 3091/// promote it to compute the value into a larger type. The produced value will 3092/// have the correct bits for the low portion of the register, but no guarantee 3093/// is made about the top bits: it may be zero, sign-extended, or garbage. 3094SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 3095 MVT::ValueType VT = Op.getValueType(); 3096 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3097 assert(getTypeAction(VT) == Promote && 3098 "Caller should expand or legalize operands that are not promotable!"); 3099 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 3100 "Cannot promote to smaller type!"); 3101 3102 SDOperand Tmp1, Tmp2, Tmp3; 3103 SDOperand Result; 3104 SDNode *Node = Op.Val; 3105 3106 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 3107 if (I != PromotedNodes.end()) return I->second; 3108 3109 switch (Node->getOpcode()) { 3110 case ISD::CopyFromReg: 3111 assert(0 && "CopyFromReg must be legal!"); 3112 default: 3113#ifndef NDEBUG 3114 cerr << "NODE: "; Node->dump(); cerr << "\n"; 3115#endif 3116 assert(0 && "Do not know how to promote this operator!"); 3117 abort(); 3118 case ISD::UNDEF: 3119 Result = DAG.getNode(ISD::UNDEF, NVT); 3120 break; 3121 case ISD::Constant: 3122 if (VT != MVT::i1) 3123 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 3124 else 3125 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 3126 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 3127 break; 3128 case ISD::ConstantFP: 3129 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 3130 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 3131 break; 3132 3133 case ISD::SETCC: 3134 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 3135 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 3136 Node->getOperand(1), Node->getOperand(2)); 3137 break; 3138 3139 case ISD::TRUNCATE: 3140 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3141 case Legal: 3142 Result = LegalizeOp(Node->getOperand(0)); 3143 assert(Result.getValueType() >= NVT && 3144 "This truncation doesn't make sense!"); 3145 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 3146 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 3147 break; 3148 case Promote: 3149 // The truncation is not required, because we don't guarantee anything 3150 // about high bits anyway. 3151 Result = PromoteOp(Node->getOperand(0)); 3152 break; 3153 case Expand: 3154 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3155 // Truncate the low part of the expanded value to the result type 3156 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 3157 } 3158 break; 3159 case ISD::SIGN_EXTEND: 3160 case ISD::ZERO_EXTEND: 3161 case ISD::ANY_EXTEND: 3162 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3163 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 3164 case Legal: 3165 // Input is legal? Just do extend all the way to the larger type. 3166 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3167 break; 3168 case Promote: 3169 // Promote the reg if it's smaller. 3170 Result = PromoteOp(Node->getOperand(0)); 3171 // The high bits are not guaranteed to be anything. Insert an extend. 3172 if (Node->getOpcode() == ISD::SIGN_EXTEND) 3173 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3174 DAG.getValueType(Node->getOperand(0).getValueType())); 3175 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 3176 Result = DAG.getZeroExtendInReg(Result, 3177 Node->getOperand(0).getValueType()); 3178 break; 3179 } 3180 break; 3181 case ISD::BIT_CONVERT: 3182 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3183 Result = PromoteOp(Result); 3184 break; 3185 3186 case ISD::FP_EXTEND: 3187 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 3188 case ISD::FP_ROUND: 3189 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3190 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 3191 case Promote: assert(0 && "Unreachable with 2 FP types!"); 3192 case Legal: 3193 // Input is legal? Do an FP_ROUND_INREG. 3194 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 3195 DAG.getValueType(VT)); 3196 break; 3197 } 3198 break; 3199 3200 case ISD::SINT_TO_FP: 3201 case ISD::UINT_TO_FP: 3202 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3203 case Legal: 3204 // No extra round required here. 3205 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3206 break; 3207 3208 case Promote: 3209 Result = PromoteOp(Node->getOperand(0)); 3210 if (Node->getOpcode() == ISD::SINT_TO_FP) 3211 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3212 Result, 3213 DAG.getValueType(Node->getOperand(0).getValueType())); 3214 else 3215 Result = DAG.getZeroExtendInReg(Result, 3216 Node->getOperand(0).getValueType()); 3217 // No extra round required here. 3218 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3219 break; 3220 case Expand: 3221 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3222 Node->getOperand(0)); 3223 // Round if we cannot tolerate excess precision. 3224 if (NoExcessFPPrecision) 3225 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3226 DAG.getValueType(VT)); 3227 break; 3228 } 3229 break; 3230 3231 case ISD::SIGN_EXTEND_INREG: 3232 Result = PromoteOp(Node->getOperand(0)); 3233 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3234 Node->getOperand(1)); 3235 break; 3236 case ISD::FP_TO_SINT: 3237 case ISD::FP_TO_UINT: 3238 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3239 case Legal: 3240 case Expand: 3241 Tmp1 = Node->getOperand(0); 3242 break; 3243 case Promote: 3244 // The input result is prerounded, so we don't have to do anything 3245 // special. 3246 Tmp1 = PromoteOp(Node->getOperand(0)); 3247 break; 3248 } 3249 // If we're promoting a UINT to a larger size, check to see if the new node 3250 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3251 // we can use that instead. This allows us to generate better code for 3252 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3253 // legal, such as PowerPC. 3254 if (Node->getOpcode() == ISD::FP_TO_UINT && 3255 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3256 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3257 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3258 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3259 } else { 3260 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3261 } 3262 break; 3263 3264 case ISD::FABS: 3265 case ISD::FNEG: 3266 Tmp1 = PromoteOp(Node->getOperand(0)); 3267 assert(Tmp1.getValueType() == NVT); 3268 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3269 // NOTE: we do not have to do any extra rounding here for 3270 // NoExcessFPPrecision, because we know the input will have the appropriate 3271 // precision, and these operations don't modify precision at all. 3272 break; 3273 3274 case ISD::FSQRT: 3275 case ISD::FSIN: 3276 case ISD::FCOS: 3277 Tmp1 = PromoteOp(Node->getOperand(0)); 3278 assert(Tmp1.getValueType() == NVT); 3279 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3280 if (NoExcessFPPrecision) 3281 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3282 DAG.getValueType(VT)); 3283 break; 3284 3285 case ISD::AND: 3286 case ISD::OR: 3287 case ISD::XOR: 3288 case ISD::ADD: 3289 case ISD::SUB: 3290 case ISD::MUL: 3291 // The input may have strange things in the top bits of the registers, but 3292 // these operations don't care. They may have weird bits going out, but 3293 // that too is okay if they are integer operations. 3294 Tmp1 = PromoteOp(Node->getOperand(0)); 3295 Tmp2 = PromoteOp(Node->getOperand(1)); 3296 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3297 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3298 break; 3299 case ISD::FADD: 3300 case ISD::FSUB: 3301 case ISD::FMUL: 3302 Tmp1 = PromoteOp(Node->getOperand(0)); 3303 Tmp2 = PromoteOp(Node->getOperand(1)); 3304 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3305 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3306 3307 // Floating point operations will give excess precision that we may not be 3308 // able to tolerate. If we DO allow excess precision, just leave it, 3309 // otherwise excise it. 3310 // FIXME: Why would we need to round FP ops more than integer ones? 3311 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3312 if (NoExcessFPPrecision) 3313 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3314 DAG.getValueType(VT)); 3315 break; 3316 3317 case ISD::SDIV: 3318 case ISD::SREM: 3319 // These operators require that their input be sign extended. 3320 Tmp1 = PromoteOp(Node->getOperand(0)); 3321 Tmp2 = PromoteOp(Node->getOperand(1)); 3322 if (MVT::isInteger(NVT)) { 3323 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3324 DAG.getValueType(VT)); 3325 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3326 DAG.getValueType(VT)); 3327 } 3328 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3329 3330 // Perform FP_ROUND: this is probably overly pessimistic. 3331 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 3332 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3333 DAG.getValueType(VT)); 3334 break; 3335 case ISD::FDIV: 3336 case ISD::FREM: 3337 case ISD::FCOPYSIGN: 3338 // These operators require that their input be fp extended. 3339 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3340 case Legal: 3341 Tmp1 = LegalizeOp(Node->getOperand(0)); 3342 break; 3343 case Promote: 3344 Tmp1 = PromoteOp(Node->getOperand(0)); 3345 break; 3346 case Expand: 3347 assert(0 && "not implemented"); 3348 } 3349 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3350 case Legal: 3351 Tmp2 = LegalizeOp(Node->getOperand(1)); 3352 break; 3353 case Promote: 3354 Tmp2 = PromoteOp(Node->getOperand(1)); 3355 break; 3356 case Expand: 3357 assert(0 && "not implemented"); 3358 } 3359 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3360 3361 // Perform FP_ROUND: this is probably overly pessimistic. 3362 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 3363 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3364 DAG.getValueType(VT)); 3365 break; 3366 3367 case ISD::UDIV: 3368 case ISD::UREM: 3369 // These operators require that their input be zero extended. 3370 Tmp1 = PromoteOp(Node->getOperand(0)); 3371 Tmp2 = PromoteOp(Node->getOperand(1)); 3372 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 3373 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3374 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3375 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3376 break; 3377 3378 case ISD::SHL: 3379 Tmp1 = PromoteOp(Node->getOperand(0)); 3380 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 3381 break; 3382 case ISD::SRA: 3383 // The input value must be properly sign extended. 3384 Tmp1 = PromoteOp(Node->getOperand(0)); 3385 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3386 DAG.getValueType(VT)); 3387 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 3388 break; 3389 case ISD::SRL: 3390 // The input value must be properly zero extended. 3391 Tmp1 = PromoteOp(Node->getOperand(0)); 3392 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3393 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 3394 break; 3395 3396 case ISD::VAARG: 3397 Tmp1 = Node->getOperand(0); // Get the chain. 3398 Tmp2 = Node->getOperand(1); // Get the pointer. 3399 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 3400 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 3401 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 3402 } else { 3403 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 3404 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3405 SV->getValue(), SV->getOffset()); 3406 // Increment the pointer, VAList, to the next vaarg 3407 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3408 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3409 TLI.getPointerTy())); 3410 // Store the incremented VAList to the legalized pointer 3411 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 3412 SV->getOffset()); 3413 // Load the actual argument out of the pointer VAList 3414 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 3415 } 3416 // Remember that we legalized the chain. 3417 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3418 break; 3419 3420 case ISD::LOAD: { 3421 LoadSDNode *LD = cast<LoadSDNode>(Node); 3422 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 3423 ? ISD::EXTLOAD : LD->getExtensionType(); 3424 Result = DAG.getExtLoad(ExtType, NVT, 3425 LD->getChain(), LD->getBasePtr(), 3426 LD->getSrcValue(), LD->getSrcValueOffset(), 3427 LD->getLoadedVT()); 3428 // Remember that we legalized the chain. 3429 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3430 break; 3431 } 3432 case ISD::SELECT: 3433 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 3434 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 3435 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 3436 break; 3437 case ISD::SELECT_CC: 3438 Tmp2 = PromoteOp(Node->getOperand(2)); // True 3439 Tmp3 = PromoteOp(Node->getOperand(3)); // False 3440 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3441 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 3442 break; 3443 case ISD::BSWAP: 3444 Tmp1 = Node->getOperand(0); 3445 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3446 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3447 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3448 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT), 3449 TLI.getShiftAmountTy())); 3450 break; 3451 case ISD::CTPOP: 3452 case ISD::CTTZ: 3453 case ISD::CTLZ: 3454 // Zero extend the argument 3455 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 3456 // Perform the larger operation, then subtract if needed. 3457 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3458 switch(Node->getOpcode()) { 3459 case ISD::CTPOP: 3460 Result = Tmp1; 3461 break; 3462 case ISD::CTTZ: 3463 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3464 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3465 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 3466 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3467 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1); 3468 break; 3469 case ISD::CTLZ: 3470 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3471 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3472 DAG.getConstant(getSizeInBits(NVT) - 3473 getSizeInBits(VT), NVT)); 3474 break; 3475 } 3476 break; 3477 case ISD::VEXTRACT_VECTOR_ELT: 3478 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op)); 3479 break; 3480 case ISD::EXTRACT_VECTOR_ELT: 3481 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 3482 break; 3483 } 3484 3485 assert(Result.Val && "Didn't set a result!"); 3486 3487 // Make sure the result is itself legal. 3488 Result = LegalizeOp(Result); 3489 3490 // Remember that we promoted this! 3491 AddPromotedOperand(Op, Result); 3492 return Result; 3493} 3494 3495/// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a 3496/// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based 3497/// on the vector type. The return type of this matches the element type of the 3498/// vector, which may not be legal for the target. 3499SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) { 3500 // We know that operand #0 is the Vec vector. If the index is a constant 3501 // or if the invec is a supported hardware type, we can use it. Otherwise, 3502 // lower to a store then an indexed load. 3503 SDOperand Vec = Op.getOperand(0); 3504 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 3505 3506 SDNode *InVal = Vec.Val; 3507 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 3508 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 3509 3510 // Figure out if there is a Packed type corresponding to this Vector 3511 // type. If so, convert to the packed type. 3512 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3513 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 3514 // Turn this into a packed extract_vector_elt operation. 3515 Vec = PackVectorOp(Vec, TVT); 3516 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx); 3517 } else if (NumElems == 1) { 3518 // This must be an access of the only element. Return it. 3519 return PackVectorOp(Vec, EVT); 3520 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 3521 SDOperand Lo, Hi; 3522 SplitVectorOp(Vec, Lo, Hi); 3523 if (CIdx->getValue() < NumElems/2) { 3524 Vec = Lo; 3525 } else { 3526 Vec = Hi; 3527 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 3528 } 3529 3530 // It's now an extract from the appropriate high or low part. Recurse. 3531 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3532 return LowerVEXTRACT_VECTOR_ELT(Op); 3533 } else { 3534 // Variable index case for extract element. 3535 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!! 3536 assert(0 && "unimp!"); 3537 return SDOperand(); 3538 } 3539} 3540 3541/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 3542/// memory traffic. 3543SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 3544 SDOperand Vector = Op.getOperand(0); 3545 SDOperand Idx = Op.getOperand(1); 3546 3547 // If the target doesn't support this, store the value to a temporary 3548 // stack slot, then LOAD the scalar element back out. 3549 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType()); 3550 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vector, StackPtr, NULL, 0); 3551 3552 // Add the offset to the index. 3553 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 3554 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 3555 DAG.getConstant(EltSize, Idx.getValueType())); 3556 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 3557 3558 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 3559} 3560 3561 3562/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 3563/// with condition CC on the current target. This usually involves legalizing 3564/// or promoting the arguments. In the case where LHS and RHS must be expanded, 3565/// there may be no choice but to create a new SetCC node to represent the 3566/// legalized value of setcc lhs, rhs. In this case, the value is returned in 3567/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 3568void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 3569 SDOperand &RHS, 3570 SDOperand &CC) { 3571 SDOperand Tmp1, Tmp2, Result; 3572 3573 switch (getTypeAction(LHS.getValueType())) { 3574 case Legal: 3575 Tmp1 = LegalizeOp(LHS); // LHS 3576 Tmp2 = LegalizeOp(RHS); // RHS 3577 break; 3578 case Promote: 3579 Tmp1 = PromoteOp(LHS); // LHS 3580 Tmp2 = PromoteOp(RHS); // RHS 3581 3582 // If this is an FP compare, the operands have already been extended. 3583 if (MVT::isInteger(LHS.getValueType())) { 3584 MVT::ValueType VT = LHS.getValueType(); 3585 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3586 3587 // Otherwise, we have to insert explicit sign or zero extends. Note 3588 // that we could insert sign extends for ALL conditions, but zero extend 3589 // is cheaper on many machines (an AND instead of two shifts), so prefer 3590 // it. 3591 switch (cast<CondCodeSDNode>(CC)->get()) { 3592 default: assert(0 && "Unknown integer comparison!"); 3593 case ISD::SETEQ: 3594 case ISD::SETNE: 3595 case ISD::SETUGE: 3596 case ISD::SETUGT: 3597 case ISD::SETULE: 3598 case ISD::SETULT: 3599 // ALL of these operations will work if we either sign or zero extend 3600 // the operands (including the unsigned comparisons!). Zero extend is 3601 // usually a simpler/cheaper operation, so prefer it. 3602 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3603 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3604 break; 3605 case ISD::SETGE: 3606 case ISD::SETGT: 3607 case ISD::SETLT: 3608 case ISD::SETLE: 3609 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3610 DAG.getValueType(VT)); 3611 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3612 DAG.getValueType(VT)); 3613 break; 3614 } 3615 } 3616 break; 3617 case Expand: { 3618 MVT::ValueType VT = LHS.getValueType(); 3619 if (VT == MVT::f32 || VT == MVT::f64) { 3620 // Expand into one or more soft-fp libcall(s). 3621 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 3622 switch (cast<CondCodeSDNode>(CC)->get()) { 3623 case ISD::SETEQ: 3624 case ISD::SETOEQ: 3625 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 3626 break; 3627 case ISD::SETNE: 3628 case ISD::SETUNE: 3629 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 3630 break; 3631 case ISD::SETGE: 3632 case ISD::SETOGE: 3633 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 3634 break; 3635 case ISD::SETLT: 3636 case ISD::SETOLT: 3637 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3638 break; 3639 case ISD::SETLE: 3640 case ISD::SETOLE: 3641 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 3642 break; 3643 case ISD::SETGT: 3644 case ISD::SETOGT: 3645 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 3646 break; 3647 case ISD::SETUO: 3648 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 3649 break; 3650 case ISD::SETO: 3651 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 3652 break; 3653 default: 3654 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 3655 switch (cast<CondCodeSDNode>(CC)->get()) { 3656 case ISD::SETONE: 3657 // SETONE = SETOLT | SETOGT 3658 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3659 // Fallthrough 3660 case ISD::SETUGT: 3661 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 3662 break; 3663 case ISD::SETUGE: 3664 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 3665 break; 3666 case ISD::SETULT: 3667 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3668 break; 3669 case ISD::SETULE: 3670 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 3671 break; 3672 case ISD::SETUEQ: 3673 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 3674 break; 3675 default: assert(0 && "Unsupported FP setcc!"); 3676 } 3677 } 3678 3679 SDOperand Dummy; 3680 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 3681 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 3682 false /*sign irrelevant*/, Dummy); 3683 Tmp2 = DAG.getConstant(0, MVT::i32); 3684 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 3685 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 3686 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); 3687 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 3688 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 3689 false /*sign irrelevant*/, Dummy); 3690 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, 3691 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 3692 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 3693 Tmp2 = SDOperand(); 3694 } 3695 LHS = Tmp1; 3696 RHS = Tmp2; 3697 return; 3698 } 3699 3700 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 3701 ExpandOp(LHS, LHSLo, LHSHi); 3702 ExpandOp(RHS, RHSLo, RHSHi); 3703 switch (cast<CondCodeSDNode>(CC)->get()) { 3704 case ISD::SETEQ: 3705 case ISD::SETNE: 3706 if (RHSLo == RHSHi) 3707 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 3708 if (RHSCST->isAllOnesValue()) { 3709 // Comparison to -1. 3710 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 3711 Tmp2 = RHSLo; 3712 break; 3713 } 3714 3715 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 3716 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 3717 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 3718 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3719 break; 3720 default: 3721 // If this is a comparison of the sign bit, just look at the top part. 3722 // X > -1, x < 0 3723 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 3724 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 3725 CST->getValue() == 0) || // X < 0 3726 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 3727 CST->isAllOnesValue())) { // X > -1 3728 Tmp1 = LHSHi; 3729 Tmp2 = RHSHi; 3730 break; 3731 } 3732 3733 // FIXME: This generated code sucks. 3734 ISD::CondCode LowCC; 3735 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 3736 switch (CCCode) { 3737 default: assert(0 && "Unknown integer setcc!"); 3738 case ISD::SETLT: 3739 case ISD::SETULT: LowCC = ISD::SETULT; break; 3740 case ISD::SETGT: 3741 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 3742 case ISD::SETLE: 3743 case ISD::SETULE: LowCC = ISD::SETULE; break; 3744 case ISD::SETGE: 3745 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 3746 } 3747 3748 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 3749 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 3750 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 3751 3752 // NOTE: on targets without efficient SELECT of bools, we can always use 3753 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 3754 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 3755 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, 3756 false, DagCombineInfo); 3757 if (!Tmp1.Val) 3758 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 3759 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 3760 CCCode, false, DagCombineInfo); 3761 if (!Tmp2.Val) 3762 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC); 3763 3764 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 3765 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 3766 if ((Tmp1C && Tmp1C->getValue() == 0) || 3767 (Tmp2C && Tmp2C->getValue() == 0 && 3768 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 3769 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 3770 (Tmp2C && Tmp2C->getValue() == 1 && 3771 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 3772 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 3773 // low part is known false, returns high part. 3774 // For LE / GE, if high part is known false, ignore the low part. 3775 // For LT / GT, if high part is known true, ignore the low part. 3776 Tmp1 = Tmp2; 3777 Tmp2 = SDOperand(); 3778 } else { 3779 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 3780 ISD::SETEQ, false, DagCombineInfo); 3781 if (!Result.Val) 3782 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 3783 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 3784 Result, Tmp1, Tmp2)); 3785 Tmp1 = Result; 3786 Tmp2 = SDOperand(); 3787 } 3788 } 3789 } 3790 } 3791 LHS = Tmp1; 3792 RHS = Tmp2; 3793} 3794 3795/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 3796/// The resultant code need not be legal. Note that SrcOp is the input operand 3797/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 3798SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 3799 SDOperand SrcOp) { 3800 // Create the stack frame object. 3801 SDOperand FIPtr = CreateStackTemporary(DestVT); 3802 3803 // Emit a store to the stack slot. 3804 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); 3805 // Result is a load from the stack slot. 3806 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 3807} 3808 3809SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 3810 // Create a vector sized/aligned stack slot, store the value to element #0, 3811 // then load the whole vector back out. 3812 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); 3813 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 3814 NULL, 0); 3815 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); 3816} 3817 3818 3819/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 3820/// support the operation, but do support the resultant packed vector type. 3821SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 3822 3823 // If the only non-undef value is the low element, turn this into a 3824 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 3825 unsigned NumElems = Node->getNumOperands(); 3826 bool isOnlyLowElement = true; 3827 SDOperand SplatValue = Node->getOperand(0); 3828 std::map<SDOperand, std::vector<unsigned> > Values; 3829 Values[SplatValue].push_back(0); 3830 bool isConstant = true; 3831 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 3832 SplatValue.getOpcode() != ISD::UNDEF) 3833 isConstant = false; 3834 3835 for (unsigned i = 1; i < NumElems; ++i) { 3836 SDOperand V = Node->getOperand(i); 3837 Values[V].push_back(i); 3838 if (V.getOpcode() != ISD::UNDEF) 3839 isOnlyLowElement = false; 3840 if (SplatValue != V) 3841 SplatValue = SDOperand(0,0); 3842 3843 // If this isn't a constant element or an undef, we can't use a constant 3844 // pool load. 3845 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 3846 V.getOpcode() != ISD::UNDEF) 3847 isConstant = false; 3848 } 3849 3850 if (isOnlyLowElement) { 3851 // If the low element is an undef too, then this whole things is an undef. 3852 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 3853 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 3854 // Otherwise, turn this into a scalar_to_vector node. 3855 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 3856 Node->getOperand(0)); 3857 } 3858 3859 // If all elements are constants, create a load from the constant pool. 3860 if (isConstant) { 3861 MVT::ValueType VT = Node->getValueType(0); 3862 const Type *OpNTy = 3863 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 3864 std::vector<Constant*> CV; 3865 for (unsigned i = 0, e = NumElems; i != e; ++i) { 3866 if (ConstantFPSDNode *V = 3867 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 3868 CV.push_back(ConstantFP::get(OpNTy, V->getValue())); 3869 } else if (ConstantSDNode *V = 3870 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 3871 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 3872 } else { 3873 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 3874 CV.push_back(UndefValue::get(OpNTy)); 3875 } 3876 } 3877 Constant *CP = ConstantPacked::get(CV); 3878 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 3879 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 3880 } 3881 3882 if (SplatValue.Val) { // Splat of one value? 3883 // Build the shuffle constant vector: <0, 0, 0, 0> 3884 MVT::ValueType MaskVT = 3885 MVT::getIntVectorWithNumElements(NumElems); 3886 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT)); 3887 std::vector<SDOperand> ZeroVec(NumElems, Zero); 3888 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3889 &ZeroVec[0], ZeroVec.size()); 3890 3891 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 3892 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 3893 // Get the splatted value into the low element of a vector register. 3894 SDOperand LowValVec = 3895 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 3896 3897 // Return shuffle(LowValVec, undef, <0,0,0,0>) 3898 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 3899 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 3900 SplatMask); 3901 } 3902 } 3903 3904 // If there are only two unique elements, we may be able to turn this into a 3905 // vector shuffle. 3906 if (Values.size() == 2) { 3907 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 3908 MVT::ValueType MaskVT = 3909 MVT::getIntVectorWithNumElements(NumElems); 3910 std::vector<SDOperand> MaskVec(NumElems); 3911 unsigned i = 0; 3912 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 3913 E = Values.end(); I != E; ++I) { 3914 for (std::vector<unsigned>::iterator II = I->second.begin(), 3915 EE = I->second.end(); II != EE; ++II) 3916 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT)); 3917 i += NumElems; 3918 } 3919 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3920 &MaskVec[0], MaskVec.size()); 3921 3922 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 3923 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 3924 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 3925 SmallVector<SDOperand, 8> Ops; 3926 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 3927 E = Values.end(); I != E; ++I) { 3928 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 3929 I->first); 3930 Ops.push_back(Op); 3931 } 3932 Ops.push_back(ShuffleMask); 3933 3934 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 3935 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 3936 &Ops[0], Ops.size()); 3937 } 3938 } 3939 3940 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 3941 // aligned object on the stack, store each element into it, then load 3942 // the result as a vector. 3943 MVT::ValueType VT = Node->getValueType(0); 3944 // Create the stack frame object. 3945 SDOperand FIPtr = CreateStackTemporary(VT); 3946 3947 // Emit a store of each element to the stack slot. 3948 SmallVector<SDOperand, 8> Stores; 3949 unsigned TypeByteSize = 3950 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 3951 // Store (in the right endianness) the elements to memory. 3952 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3953 // Ignore undef elements. 3954 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3955 3956 unsigned Offset = TypeByteSize*i; 3957 3958 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 3959 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 3960 3961 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 3962 NULL, 0)); 3963 } 3964 3965 SDOperand StoreChain; 3966 if (!Stores.empty()) // Not all undef elements? 3967 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3968 &Stores[0], Stores.size()); 3969 else 3970 StoreChain = DAG.getEntryNode(); 3971 3972 // Result is a load from the stack slot. 3973 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 3974} 3975 3976/// CreateStackTemporary - Create a stack temporary, suitable for holding the 3977/// specified value type. 3978SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) { 3979 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 3980 unsigned ByteSize = MVT::getSizeInBits(VT)/8; 3981 const Type *Ty = MVT::getTypeForValueType(VT); 3982 unsigned StackAlign = (unsigned)TLI.getTargetData()->getTypeAlignmentPref(Ty); 3983 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 3984 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 3985} 3986 3987void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 3988 SDOperand Op, SDOperand Amt, 3989 SDOperand &Lo, SDOperand &Hi) { 3990 // Expand the subcomponents. 3991 SDOperand LHSL, LHSH; 3992 ExpandOp(Op, LHSL, LHSH); 3993 3994 SDOperand Ops[] = { LHSL, LHSH, Amt }; 3995 MVT::ValueType VT = LHSL.getValueType(); 3996 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 3997 Hi = Lo.getValue(1); 3998} 3999 4000 4001/// ExpandShift - Try to find a clever way to expand this shift operation out to 4002/// smaller elements. If we can't find a way that is more efficient than a 4003/// libcall on this target, return false. Otherwise, return true with the 4004/// low-parts expanded into Lo and Hi. 4005bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 4006 SDOperand &Lo, SDOperand &Hi) { 4007 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 4008 "This is not a shift!"); 4009 4010 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 4011 SDOperand ShAmt = LegalizeOp(Amt); 4012 MVT::ValueType ShTy = ShAmt.getValueType(); 4013 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 4014 unsigned NVTBits = MVT::getSizeInBits(NVT); 4015 4016 // Handle the case when Amt is an immediate. Other cases are currently broken 4017 // and are disabled. 4018 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 4019 unsigned Cst = CN->getValue(); 4020 // Expand the incoming operand to be shifted, so that we have its parts 4021 SDOperand InL, InH; 4022 ExpandOp(Op, InL, InH); 4023 switch(Opc) { 4024 case ISD::SHL: 4025 if (Cst > VTBits) { 4026 Lo = DAG.getConstant(0, NVT); 4027 Hi = DAG.getConstant(0, NVT); 4028 } else if (Cst > NVTBits) { 4029 Lo = DAG.getConstant(0, NVT); 4030 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 4031 } else if (Cst == NVTBits) { 4032 Lo = DAG.getConstant(0, NVT); 4033 Hi = InL; 4034 } else { 4035 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 4036 Hi = DAG.getNode(ISD::OR, NVT, 4037 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 4038 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 4039 } 4040 return true; 4041 case ISD::SRL: 4042 if (Cst > VTBits) { 4043 Lo = DAG.getConstant(0, NVT); 4044 Hi = DAG.getConstant(0, NVT); 4045 } else if (Cst > NVTBits) { 4046 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 4047 Hi = DAG.getConstant(0, NVT); 4048 } else if (Cst == NVTBits) { 4049 Lo = InH; 4050 Hi = DAG.getConstant(0, NVT); 4051 } else { 4052 Lo = DAG.getNode(ISD::OR, NVT, 4053 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4054 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4055 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 4056 } 4057 return true; 4058 case ISD::SRA: 4059 if (Cst > VTBits) { 4060 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 4061 DAG.getConstant(NVTBits-1, ShTy)); 4062 } else if (Cst > NVTBits) { 4063 Lo = DAG.getNode(ISD::SRA, NVT, InH, 4064 DAG.getConstant(Cst-NVTBits, ShTy)); 4065 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4066 DAG.getConstant(NVTBits-1, ShTy)); 4067 } else if (Cst == NVTBits) { 4068 Lo = InH; 4069 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4070 DAG.getConstant(NVTBits-1, ShTy)); 4071 } else { 4072 Lo = DAG.getNode(ISD::OR, NVT, 4073 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4074 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4075 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 4076 } 4077 return true; 4078 } 4079 } 4080 4081 // Okay, the shift amount isn't constant. However, if we can tell that it is 4082 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 4083 uint64_t Mask = NVTBits, KnownZero, KnownOne; 4084 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 4085 4086 // If we know that the high bit of the shift amount is one, then we can do 4087 // this as a couple of simple shifts. 4088 if (KnownOne & Mask) { 4089 // Mask out the high bit, which we know is set. 4090 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 4091 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4092 4093 // Expand the incoming operand to be shifted, so that we have its parts 4094 SDOperand InL, InH; 4095 ExpandOp(Op, InL, InH); 4096 switch(Opc) { 4097 case ISD::SHL: 4098 Lo = DAG.getConstant(0, NVT); // Low part is zero. 4099 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 4100 return true; 4101 case ISD::SRL: 4102 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 4103 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 4104 return true; 4105 case ISD::SRA: 4106 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 4107 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4108 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 4109 return true; 4110 } 4111 } 4112 4113 // If we know that the high bit of the shift amount is zero, then we can do 4114 // this as a couple of simple shifts. 4115 if (KnownZero & Mask) { 4116 // Compute 32-amt. 4117 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 4118 DAG.getConstant(NVTBits, Amt.getValueType()), 4119 Amt); 4120 4121 // Expand the incoming operand to be shifted, so that we have its parts 4122 SDOperand InL, InH; 4123 ExpandOp(Op, InL, InH); 4124 switch(Opc) { 4125 case ISD::SHL: 4126 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 4127 Hi = DAG.getNode(ISD::OR, NVT, 4128 DAG.getNode(ISD::SHL, NVT, InH, Amt), 4129 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 4130 return true; 4131 case ISD::SRL: 4132 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 4133 Lo = DAG.getNode(ISD::OR, NVT, 4134 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4135 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4136 return true; 4137 case ISD::SRA: 4138 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 4139 Lo = DAG.getNode(ISD::OR, NVT, 4140 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4141 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4142 return true; 4143 } 4144 } 4145 4146 return false; 4147} 4148 4149 4150// ExpandLibCall - Expand a node into a call to a libcall. If the result value 4151// does not fit into a register, return the lo part and set the hi part to the 4152// by-reg argument. If it does fit into a single register, return the result 4153// and leave the Hi part unset. 4154SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 4155 bool isSigned, SDOperand &Hi) { 4156 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 4157 // The input chain to this libcall is the entry node of the function. 4158 // Legalizing the call will automatically add the previous call to the 4159 // dependence. 4160 SDOperand InChain = DAG.getEntryNode(); 4161 4162 TargetLowering::ArgListTy Args; 4163 TargetLowering::ArgListEntry Entry; 4164 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4165 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 4166 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 4167 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 4168 Entry.isSigned = isSigned; Entry.isInReg = false; Entry.isSRet = false; 4169 Args.push_back(Entry); 4170 } 4171 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 4172 4173 // Splice the libcall in wherever FindInputOutputChains tells us to. 4174 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 4175 std::pair<SDOperand,SDOperand> CallInfo = 4176 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false, 4177 Callee, Args, DAG); 4178 4179 // Legalize the call sequence, starting with the chain. This will advance 4180 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 4181 // was added by LowerCallTo (guaranteeing proper serialization of calls). 4182 LegalizeOp(CallInfo.second); 4183 SDOperand Result; 4184 switch (getTypeAction(CallInfo.first.getValueType())) { 4185 default: assert(0 && "Unknown thing"); 4186 case Legal: 4187 Result = CallInfo.first; 4188 break; 4189 case Expand: 4190 ExpandOp(CallInfo.first, Result, Hi); 4191 break; 4192 } 4193 return Result; 4194} 4195 4196 4197/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 4198/// destination type is legal. 4199SDOperand SelectionDAGLegalize:: 4200ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 4201 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 4202 assert(getTypeAction(Source.getValueType()) == Expand && 4203 "This is not an expansion!"); 4204 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 4205 4206 if (!isSigned) { 4207 assert(Source.getValueType() == MVT::i64 && 4208 "This only works for 64-bit -> FP"); 4209 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 4210 // incoming integer is set. To handle this, we dynamically test to see if 4211 // it is set, and, if so, add a fudge factor. 4212 SDOperand Lo, Hi; 4213 ExpandOp(Source, Lo, Hi); 4214 4215 // If this is unsigned, and not supported, first perform the conversion to 4216 // signed, then adjust the result if the sign bit is set. 4217 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 4218 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 4219 4220 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 4221 DAG.getConstant(0, Hi.getValueType()), 4222 ISD::SETLT); 4223 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4224 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4225 SignSet, Four, Zero); 4226 uint64_t FF = 0x5f800000ULL; 4227 if (TLI.isLittleEndian()) FF <<= 32; 4228 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4229 4230 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4231 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4232 SDOperand FudgeInReg; 4233 if (DestTy == MVT::f32) 4234 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4235 else { 4236 assert(DestTy == MVT::f64 && "Unexpected conversion"); 4237 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 4238 CPIdx, NULL, 0, MVT::f32); 4239 } 4240 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 4241 } 4242 4243 // Check to see if the target has a custom way to lower this. If so, use it. 4244 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 4245 default: assert(0 && "This action not implemented for this operation!"); 4246 case TargetLowering::Legal: 4247 case TargetLowering::Expand: 4248 break; // This case is handled below. 4249 case TargetLowering::Custom: { 4250 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 4251 Source), DAG); 4252 if (NV.Val) 4253 return LegalizeOp(NV); 4254 break; // The target decided this was legal after all 4255 } 4256 } 4257 4258 // Expand the source, then glue it back together for the call. We must expand 4259 // the source in case it is shared (this pass of legalize must traverse it). 4260 SDOperand SrcLo, SrcHi; 4261 ExpandOp(Source, SrcLo, SrcHi); 4262 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 4263 4264 RTLIB::Libcall LC; 4265 if (DestTy == MVT::f32) 4266 LC = RTLIB::SINTTOFP_I64_F32; 4267 else { 4268 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 4269 LC = RTLIB::SINTTOFP_I64_F64; 4270 } 4271 4272 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 4273 SDOperand UnusedHiPart; 4274 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 4275 UnusedHiPart); 4276} 4277 4278/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 4279/// INT_TO_FP operation of the specified operand when the target requests that 4280/// we expand it. At this point, we know that the result and operand types are 4281/// legal for the target. 4282SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 4283 SDOperand Op0, 4284 MVT::ValueType DestVT) { 4285 if (Op0.getValueType() == MVT::i32) { 4286 // simple 32-bit [signed|unsigned] integer to float/double expansion 4287 4288 // get the stack frame index of a 8 byte buffer, pessimistically aligned 4289 MachineFunction &MF = DAG.getMachineFunction(); 4290 const Type *F64Type = MVT::getTypeForValueType(MVT::f64); 4291 unsigned StackAlign = 4292 (unsigned)TLI.getTargetData()->getTypeAlignmentPref(F64Type); 4293 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign); 4294 // get address of 8 byte buffer 4295 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4296 // word offset constant for Hi/Lo address computation 4297 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 4298 // set up Hi and Lo (into buffer) address based on endian 4299 SDOperand Hi = StackSlot; 4300 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 4301 if (TLI.isLittleEndian()) 4302 std::swap(Hi, Lo); 4303 4304 // if signed map to unsigned space 4305 SDOperand Op0Mapped; 4306 if (isSigned) { 4307 // constant used to invert sign bit (signed to unsigned mapping) 4308 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 4309 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 4310 } else { 4311 Op0Mapped = Op0; 4312 } 4313 // store the lo of the constructed double - based on integer input 4314 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 4315 Op0Mapped, Lo, NULL, 0); 4316 // initial hi portion of constructed double 4317 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 4318 // store the hi of the constructed double - biased exponent 4319 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 4320 // load the constructed double 4321 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 4322 // FP constant to bias correct the final result 4323 SDOperand Bias = DAG.getConstantFP(isSigned ? 4324 BitsToDouble(0x4330000080000000ULL) 4325 : BitsToDouble(0x4330000000000000ULL), 4326 MVT::f64); 4327 // subtract the bias 4328 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 4329 // final result 4330 SDOperand Result; 4331 // handle final rounding 4332 if (DestVT == MVT::f64) { 4333 // do nothing 4334 Result = Sub; 4335 } else { 4336 // if f32 then cast to f32 4337 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 4338 } 4339 return Result; 4340 } 4341 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 4342 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 4343 4344 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 4345 DAG.getConstant(0, Op0.getValueType()), 4346 ISD::SETLT); 4347 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4348 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4349 SignSet, Four, Zero); 4350 4351 // If the sign bit of the integer is set, the large number will be treated 4352 // as a negative number. To counteract this, the dynamic code adds an 4353 // offset depending on the data type. 4354 uint64_t FF; 4355 switch (Op0.getValueType()) { 4356 default: assert(0 && "Unsupported integer type!"); 4357 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 4358 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 4359 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 4360 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 4361 } 4362 if (TLI.isLittleEndian()) FF <<= 32; 4363 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4364 4365 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4366 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4367 SDOperand FudgeInReg; 4368 if (DestVT == MVT::f32) 4369 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4370 else { 4371 assert(DestVT == MVT::f64 && "Unexpected conversion"); 4372 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 4373 DAG.getEntryNode(), CPIdx, 4374 NULL, 0, MVT::f32)); 4375 } 4376 4377 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 4378} 4379 4380/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 4381/// *INT_TO_FP operation of the specified operand when the target requests that 4382/// we promote it. At this point, we know that the result and operand types are 4383/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 4384/// operation that takes a larger input. 4385SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 4386 MVT::ValueType DestVT, 4387 bool isSigned) { 4388 // First step, figure out the appropriate *INT_TO_FP operation to use. 4389 MVT::ValueType NewInTy = LegalOp.getValueType(); 4390 4391 unsigned OpToUse = 0; 4392 4393 // Scan for the appropriate larger type to use. 4394 while (1) { 4395 NewInTy = (MVT::ValueType)(NewInTy+1); 4396 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 4397 4398 // If the target supports SINT_TO_FP of this type, use it. 4399 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 4400 default: break; 4401 case TargetLowering::Legal: 4402 if (!TLI.isTypeLegal(NewInTy)) 4403 break; // Can't use this datatype. 4404 // FALL THROUGH. 4405 case TargetLowering::Custom: 4406 OpToUse = ISD::SINT_TO_FP; 4407 break; 4408 } 4409 if (OpToUse) break; 4410 if (isSigned) continue; 4411 4412 // If the target supports UINT_TO_FP of this type, use it. 4413 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 4414 default: break; 4415 case TargetLowering::Legal: 4416 if (!TLI.isTypeLegal(NewInTy)) 4417 break; // Can't use this datatype. 4418 // FALL THROUGH. 4419 case TargetLowering::Custom: 4420 OpToUse = ISD::UINT_TO_FP; 4421 break; 4422 } 4423 if (OpToUse) break; 4424 4425 // Otherwise, try a larger type. 4426 } 4427 4428 // Okay, we found the operation and type to use. Zero extend our input to the 4429 // desired type then run the operation on it. 4430 return DAG.getNode(OpToUse, DestVT, 4431 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 4432 NewInTy, LegalOp)); 4433} 4434 4435/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 4436/// FP_TO_*INT operation of the specified operand when the target requests that 4437/// we promote it. At this point, we know that the result and operand types are 4438/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 4439/// operation that returns a larger result. 4440SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 4441 MVT::ValueType DestVT, 4442 bool isSigned) { 4443 // First step, figure out the appropriate FP_TO*INT operation to use. 4444 MVT::ValueType NewOutTy = DestVT; 4445 4446 unsigned OpToUse = 0; 4447 4448 // Scan for the appropriate larger type to use. 4449 while (1) { 4450 NewOutTy = (MVT::ValueType)(NewOutTy+1); 4451 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 4452 4453 // If the target supports FP_TO_SINT returning this type, use it. 4454 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 4455 default: break; 4456 case TargetLowering::Legal: 4457 if (!TLI.isTypeLegal(NewOutTy)) 4458 break; // Can't use this datatype. 4459 // FALL THROUGH. 4460 case TargetLowering::Custom: 4461 OpToUse = ISD::FP_TO_SINT; 4462 break; 4463 } 4464 if (OpToUse) break; 4465 4466 // If the target supports FP_TO_UINT of this type, use it. 4467 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 4468 default: break; 4469 case TargetLowering::Legal: 4470 if (!TLI.isTypeLegal(NewOutTy)) 4471 break; // Can't use this datatype. 4472 // FALL THROUGH. 4473 case TargetLowering::Custom: 4474 OpToUse = ISD::FP_TO_UINT; 4475 break; 4476 } 4477 if (OpToUse) break; 4478 4479 // Otherwise, try a larger type. 4480 } 4481 4482 // Okay, we found the operation and type to use. Truncate the result of the 4483 // extended FP_TO_*INT operation to the desired size. 4484 return DAG.getNode(ISD::TRUNCATE, DestVT, 4485 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 4486} 4487 4488/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 4489/// 4490SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 4491 MVT::ValueType VT = Op.getValueType(); 4492 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 4493 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 4494 switch (VT) { 4495 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 4496 case MVT::i16: 4497 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4498 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4499 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 4500 case MVT::i32: 4501 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4502 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4503 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4504 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4505 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 4506 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 4507 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4508 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4509 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4510 case MVT::i64: 4511 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 4512 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 4513 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4514 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4515 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4516 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4517 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 4518 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 4519 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 4520 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 4521 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 4522 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 4523 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 4524 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 4525 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 4526 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 4527 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4528 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4529 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 4530 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4531 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 4532 } 4533} 4534 4535/// ExpandBitCount - Expand the specified bitcount instruction into operations. 4536/// 4537SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 4538 switch (Opc) { 4539 default: assert(0 && "Cannot expand this yet!"); 4540 case ISD::CTPOP: { 4541 static const uint64_t mask[6] = { 4542 0x5555555555555555ULL, 0x3333333333333333ULL, 4543 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 4544 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 4545 }; 4546 MVT::ValueType VT = Op.getValueType(); 4547 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4548 unsigned len = getSizeInBits(VT); 4549 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4550 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 4551 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 4552 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4553 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 4554 DAG.getNode(ISD::AND, VT, 4555 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 4556 } 4557 return Op; 4558 } 4559 case ISD::CTLZ: { 4560 // for now, we do this: 4561 // x = x | (x >> 1); 4562 // x = x | (x >> 2); 4563 // ... 4564 // x = x | (x >>16); 4565 // x = x | (x >>32); // for 64-bit input 4566 // return popcount(~x); 4567 // 4568 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 4569 MVT::ValueType VT = Op.getValueType(); 4570 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4571 unsigned len = getSizeInBits(VT); 4572 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4573 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4574 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 4575 } 4576 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 4577 return DAG.getNode(ISD::CTPOP, VT, Op); 4578 } 4579 case ISD::CTTZ: { 4580 // for now, we use: { return popcount(~x & (x - 1)); } 4581 // unless the target has ctlz but not ctpop, in which case we use: 4582 // { return 32 - nlz(~x & (x-1)); } 4583 // see also http://www.hackersdelight.org/HDcode/ntz.cc 4584 MVT::ValueType VT = Op.getValueType(); 4585 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 4586 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 4587 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 4588 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 4589 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 4590 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 4591 TLI.isOperationLegal(ISD::CTLZ, VT)) 4592 return DAG.getNode(ISD::SUB, VT, 4593 DAG.getConstant(getSizeInBits(VT), VT), 4594 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 4595 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 4596 } 4597 } 4598} 4599 4600/// ExpandOp - Expand the specified SDOperand into its two component pieces 4601/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 4602/// LegalizeNodes map is filled in for any results that are not expanded, the 4603/// ExpandedNodes map is filled in for any results that are expanded, and the 4604/// Lo/Hi values are returned. 4605void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 4606 MVT::ValueType VT = Op.getValueType(); 4607 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4608 SDNode *Node = Op.Val; 4609 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 4610 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 4611 VT == MVT::Vector) && 4612 "Cannot expand to FP value or to larger int value!"); 4613 4614 // See if we already expanded it. 4615 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 4616 = ExpandedNodes.find(Op); 4617 if (I != ExpandedNodes.end()) { 4618 Lo = I->second.first; 4619 Hi = I->second.second; 4620 return; 4621 } 4622 4623 switch (Node->getOpcode()) { 4624 case ISD::CopyFromReg: 4625 assert(0 && "CopyFromReg must be legal!"); 4626 default: 4627#ifndef NDEBUG 4628 cerr << "NODE: "; Node->dump(); cerr << "\n"; 4629#endif 4630 assert(0 && "Do not know how to expand this operator!"); 4631 abort(); 4632 case ISD::UNDEF: 4633 NVT = TLI.getTypeToExpandTo(VT); 4634 Lo = DAG.getNode(ISD::UNDEF, NVT); 4635 Hi = DAG.getNode(ISD::UNDEF, NVT); 4636 break; 4637 case ISD::Constant: { 4638 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 4639 Lo = DAG.getConstant(Cst, NVT); 4640 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 4641 break; 4642 } 4643 case ISD::ConstantFP: { 4644 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 4645 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 4646 if (getTypeAction(Lo.getValueType()) == Expand) 4647 ExpandOp(Lo, Lo, Hi); 4648 break; 4649 } 4650 case ISD::BUILD_PAIR: 4651 // Return the operands. 4652 Lo = Node->getOperand(0); 4653 Hi = Node->getOperand(1); 4654 break; 4655 4656 case ISD::SIGN_EXTEND_INREG: 4657 ExpandOp(Node->getOperand(0), Lo, Hi); 4658 // sext_inreg the low part if needed. 4659 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 4660 4661 // The high part gets the sign extension from the lo-part. This handles 4662 // things like sextinreg V:i64 from i8. 4663 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4664 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 4665 TLI.getShiftAmountTy())); 4666 break; 4667 4668 case ISD::BSWAP: { 4669 ExpandOp(Node->getOperand(0), Lo, Hi); 4670 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 4671 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 4672 Lo = TempLo; 4673 break; 4674 } 4675 4676 case ISD::CTPOP: 4677 ExpandOp(Node->getOperand(0), Lo, Hi); 4678 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 4679 DAG.getNode(ISD::CTPOP, NVT, Lo), 4680 DAG.getNode(ISD::CTPOP, NVT, Hi)); 4681 Hi = DAG.getConstant(0, NVT); 4682 break; 4683 4684 case ISD::CTLZ: { 4685 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 4686 ExpandOp(Node->getOperand(0), Lo, Hi); 4687 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4688 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 4689 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 4690 ISD::SETNE); 4691 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 4692 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 4693 4694 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 4695 Hi = DAG.getConstant(0, NVT); 4696 break; 4697 } 4698 4699 case ISD::CTTZ: { 4700 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 4701 ExpandOp(Node->getOperand(0), Lo, Hi); 4702 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4703 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 4704 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 4705 ISD::SETNE); 4706 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 4707 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 4708 4709 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 4710 Hi = DAG.getConstant(0, NVT); 4711 break; 4712 } 4713 4714 case ISD::VAARG: { 4715 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 4716 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 4717 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 4718 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 4719 4720 // Remember that we legalized the chain. 4721 Hi = LegalizeOp(Hi); 4722 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 4723 if (!TLI.isLittleEndian()) 4724 std::swap(Lo, Hi); 4725 break; 4726 } 4727 4728 case ISD::LOAD: { 4729 LoadSDNode *LD = cast<LoadSDNode>(Node); 4730 SDOperand Ch = LD->getChain(); // Legalize the chain. 4731 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 4732 ISD::LoadExtType ExtType = LD->getExtensionType(); 4733 4734 if (ExtType == ISD::NON_EXTLOAD) { 4735 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),LD->getSrcValueOffset()); 4736 if (VT == MVT::f32 || VT == MVT::f64) { 4737 // f32->i32 or f64->i64 one to one expansion. 4738 // Remember that we legalized the chain. 4739 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4740 // Recursively expand the new load. 4741 if (getTypeAction(NVT) == Expand) 4742 ExpandOp(Lo, Lo, Hi); 4743 break; 4744 } 4745 4746 // Increment the pointer to the other half. 4747 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 4748 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4749 getIntPtrConstant(IncrementSize)); 4750 // FIXME: This creates a bogus srcvalue! 4751 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),LD->getSrcValueOffset()); 4752 4753 // Build a factor node to remember that this load is independent of the 4754 // other one. 4755 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 4756 Hi.getValue(1)); 4757 4758 // Remember that we legalized the chain. 4759 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 4760 if (!TLI.isLittleEndian()) 4761 std::swap(Lo, Hi); 4762 } else { 4763 MVT::ValueType EVT = LD->getLoadedVT(); 4764 4765 if (VT == MVT::f64 && EVT == MVT::f32) { 4766 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 4767 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 4768 LD->getSrcValueOffset()); 4769 // Remember that we legalized the chain. 4770 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 4771 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 4772 break; 4773 } 4774 4775 if (EVT == NVT) 4776 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 4777 LD->getSrcValueOffset()); 4778 else 4779 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 4780 LD->getSrcValueOffset(), EVT); 4781 4782 // Remember that we legalized the chain. 4783 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4784 4785 if (ExtType == ISD::SEXTLOAD) { 4786 // The high part is obtained by SRA'ing all but one of the bits of the 4787 // lo part. 4788 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4789 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4790 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 4791 } else if (ExtType == ISD::ZEXTLOAD) { 4792 // The high part is just a zero. 4793 Hi = DAG.getConstant(0, NVT); 4794 } else /* if (ExtType == ISD::EXTLOAD) */ { 4795 // The high part is undefined. 4796 Hi = DAG.getNode(ISD::UNDEF, NVT); 4797 } 4798 } 4799 break; 4800 } 4801 case ISD::AND: 4802 case ISD::OR: 4803 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 4804 SDOperand LL, LH, RL, RH; 4805 ExpandOp(Node->getOperand(0), LL, LH); 4806 ExpandOp(Node->getOperand(1), RL, RH); 4807 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 4808 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 4809 break; 4810 } 4811 case ISD::SELECT: { 4812 SDOperand LL, LH, RL, RH; 4813 ExpandOp(Node->getOperand(1), LL, LH); 4814 ExpandOp(Node->getOperand(2), RL, RH); 4815 if (getTypeAction(NVT) == Expand) 4816 NVT = TLI.getTypeToExpandTo(NVT); 4817 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 4818 if (VT != MVT::f32) 4819 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 4820 break; 4821 } 4822 case ISD::SELECT_CC: { 4823 SDOperand TL, TH, FL, FH; 4824 ExpandOp(Node->getOperand(2), TL, TH); 4825 ExpandOp(Node->getOperand(3), FL, FH); 4826 if (getTypeAction(NVT) == Expand) 4827 NVT = TLI.getTypeToExpandTo(NVT); 4828 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4829 Node->getOperand(1), TL, FL, Node->getOperand(4)); 4830 if (VT != MVT::f32) 4831 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4832 Node->getOperand(1), TH, FH, Node->getOperand(4)); 4833 break; 4834 } 4835 case ISD::ANY_EXTEND: 4836 // The low part is any extension of the input (which degenerates to a copy). 4837 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 4838 // The high part is undefined. 4839 Hi = DAG.getNode(ISD::UNDEF, NVT); 4840 break; 4841 case ISD::SIGN_EXTEND: { 4842 // The low part is just a sign extension of the input (which degenerates to 4843 // a copy). 4844 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 4845 4846 // The high part is obtained by SRA'ing all but one of the bits of the lo 4847 // part. 4848 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4849 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4850 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 4851 break; 4852 } 4853 case ISD::ZERO_EXTEND: 4854 // The low part is just a zero extension of the input (which degenerates to 4855 // a copy). 4856 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4857 4858 // The high part is just a zero. 4859 Hi = DAG.getConstant(0, NVT); 4860 break; 4861 4862 case ISD::TRUNCATE: { 4863 // The input value must be larger than this value. Expand *it*. 4864 SDOperand NewLo; 4865 ExpandOp(Node->getOperand(0), NewLo, Hi); 4866 4867 // The low part is now either the right size, or it is closer. If not the 4868 // right size, make an illegal truncate so we recursively expand it. 4869 if (NewLo.getValueType() != Node->getValueType(0)) 4870 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 4871 ExpandOp(NewLo, Lo, Hi); 4872 break; 4873 } 4874 4875 case ISD::BIT_CONVERT: { 4876 SDOperand Tmp; 4877 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 4878 // If the target wants to, allow it to lower this itself. 4879 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4880 case Expand: assert(0 && "cannot expand FP!"); 4881 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 4882 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 4883 } 4884 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 4885 } 4886 4887 // f32 / f64 must be expanded to i32 / i64. 4888 if (VT == MVT::f32 || VT == MVT::f64) { 4889 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 4890 if (getTypeAction(NVT) == Expand) 4891 ExpandOp(Lo, Lo, Hi); 4892 break; 4893 } 4894 4895 // If source operand will be expanded to the same type as VT, i.e. 4896 // i64 <- f64, i32 <- f32, expand the source operand instead. 4897 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 4898 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 4899 ExpandOp(Node->getOperand(0), Lo, Hi); 4900 break; 4901 } 4902 4903 // Turn this into a load/store pair by default. 4904 if (Tmp.Val == 0) 4905 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0)); 4906 4907 ExpandOp(Tmp, Lo, Hi); 4908 break; 4909 } 4910 4911 case ISD::READCYCLECOUNTER: 4912 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 4913 TargetLowering::Custom && 4914 "Must custom expand ReadCycleCounter"); 4915 Lo = TLI.LowerOperation(Op, DAG); 4916 assert(Lo.Val && "Node must be custom expanded!"); 4917 Hi = Lo.getValue(1); 4918 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 4919 LegalizeOp(Lo.getValue(2))); 4920 break; 4921 4922 // These operators cannot be expanded directly, emit them as calls to 4923 // library functions. 4924 case ISD::FP_TO_SINT: { 4925 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 4926 SDOperand Op; 4927 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4928 case Expand: assert(0 && "cannot expand FP!"); 4929 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 4930 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 4931 } 4932 4933 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 4934 4935 // Now that the custom expander is done, expand the result, which is still 4936 // VT. 4937 if (Op.Val) { 4938 ExpandOp(Op, Lo, Hi); 4939 break; 4940 } 4941 } 4942 4943 RTLIB::Libcall LC; 4944 if (Node->getOperand(0).getValueType() == MVT::f32) 4945 LC = RTLIB::FPTOSINT_F32_I64; 4946 else 4947 LC = RTLIB::FPTOSINT_F64_I64; 4948 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 4949 false/*sign irrelevant*/, Hi); 4950 break; 4951 } 4952 4953 case ISD::FP_TO_UINT: { 4954 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 4955 SDOperand Op; 4956 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4957 case Expand: assert(0 && "cannot expand FP!"); 4958 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 4959 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 4960 } 4961 4962 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 4963 4964 // Now that the custom expander is done, expand the result. 4965 if (Op.Val) { 4966 ExpandOp(Op, Lo, Hi); 4967 break; 4968 } 4969 } 4970 4971 RTLIB::Libcall LC; 4972 if (Node->getOperand(0).getValueType() == MVT::f32) 4973 LC = RTLIB::FPTOUINT_F32_I64; 4974 else 4975 LC = RTLIB::FPTOUINT_F64_I64; 4976 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 4977 false/*sign irrelevant*/, Hi); 4978 break; 4979 } 4980 4981 case ISD::SHL: { 4982 // If the target wants custom lowering, do so. 4983 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4984 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 4985 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 4986 Op = TLI.LowerOperation(Op, DAG); 4987 if (Op.Val) { 4988 // Now that the custom expander is done, expand the result, which is 4989 // still VT. 4990 ExpandOp(Op, Lo, Hi); 4991 break; 4992 } 4993 } 4994 4995 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 4996 // this X << 1 as X+X. 4997 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 4998 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 4999 TLI.isOperationLegal(ISD::ADDE, NVT)) { 5000 SDOperand LoOps[2], HiOps[3]; 5001 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 5002 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 5003 LoOps[1] = LoOps[0]; 5004 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5005 5006 HiOps[1] = HiOps[0]; 5007 HiOps[2] = Lo.getValue(1); 5008 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5009 break; 5010 } 5011 } 5012 5013 // If we can emit an efficient shift operation, do so now. 5014 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5015 break; 5016 5017 // If this target supports SHL_PARTS, use it. 5018 TargetLowering::LegalizeAction Action = 5019 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 5020 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5021 Action == TargetLowering::Custom) { 5022 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5023 break; 5024 } 5025 5026 // Otherwise, emit a libcall. 5027 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 5028 false/*left shift=unsigned*/, Hi); 5029 break; 5030 } 5031 5032 case ISD::SRA: { 5033 // If the target wants custom lowering, do so. 5034 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5035 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 5036 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 5037 Op = TLI.LowerOperation(Op, DAG); 5038 if (Op.Val) { 5039 // Now that the custom expander is done, expand the result, which is 5040 // still VT. 5041 ExpandOp(Op, Lo, Hi); 5042 break; 5043 } 5044 } 5045 5046 // If we can emit an efficient shift operation, do so now. 5047 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5048 break; 5049 5050 // If this target supports SRA_PARTS, use it. 5051 TargetLowering::LegalizeAction Action = 5052 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 5053 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5054 Action == TargetLowering::Custom) { 5055 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5056 break; 5057 } 5058 5059 // Otherwise, emit a libcall. 5060 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 5061 true/*ashr is signed*/, Hi); 5062 break; 5063 } 5064 5065 case ISD::SRL: { 5066 // If the target wants custom lowering, do so. 5067 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5068 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 5069 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 5070 Op = TLI.LowerOperation(Op, DAG); 5071 if (Op.Val) { 5072 // Now that the custom expander is done, expand the result, which is 5073 // still VT. 5074 ExpandOp(Op, Lo, Hi); 5075 break; 5076 } 5077 } 5078 5079 // If we can emit an efficient shift operation, do so now. 5080 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5081 break; 5082 5083 // If this target supports SRL_PARTS, use it. 5084 TargetLowering::LegalizeAction Action = 5085 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 5086 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5087 Action == TargetLowering::Custom) { 5088 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5089 break; 5090 } 5091 5092 // Otherwise, emit a libcall. 5093 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 5094 false/*lshr is unsigned*/, Hi); 5095 break; 5096 } 5097 5098 case ISD::ADD: 5099 case ISD::SUB: { 5100 // If the target wants to custom expand this, let them. 5101 if (TLI.getOperationAction(Node->getOpcode(), VT) == 5102 TargetLowering::Custom) { 5103 Op = TLI.LowerOperation(Op, DAG); 5104 if (Op.Val) { 5105 ExpandOp(Op, Lo, Hi); 5106 break; 5107 } 5108 } 5109 5110 // Expand the subcomponents. 5111 SDOperand LHSL, LHSH, RHSL, RHSH; 5112 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5113 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5114 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5115 SDOperand LoOps[2], HiOps[3]; 5116 LoOps[0] = LHSL; 5117 LoOps[1] = RHSL; 5118 HiOps[0] = LHSH; 5119 HiOps[1] = RHSH; 5120 if (Node->getOpcode() == ISD::ADD) { 5121 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5122 HiOps[2] = Lo.getValue(1); 5123 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5124 } else { 5125 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5126 HiOps[2] = Lo.getValue(1); 5127 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5128 } 5129 break; 5130 } 5131 case ISD::MUL: { 5132 // If the target wants to custom expand this, let them. 5133 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 5134 SDOperand New = TLI.LowerOperation(Op, DAG); 5135 if (New.Val) { 5136 ExpandOp(New, Lo, Hi); 5137 break; 5138 } 5139 } 5140 5141 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 5142 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 5143 if (HasMULHS || HasMULHU) { 5144 SDOperand LL, LH, RL, RH; 5145 ExpandOp(Node->getOperand(0), LL, LH); 5146 ExpandOp(Node->getOperand(1), RL, RH); 5147 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 5148 // FIXME: Move this to the dag combiner. 5149 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 5150 // extended the sign bit of the low half through the upper half, and if so 5151 // emit a MULHS instead of the alternate sequence that is valid for any 5152 // i64 x i64 multiply. 5153 if (HasMULHS && 5154 // is RH an extension of the sign bit of RL? 5155 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 5156 RH.getOperand(1).getOpcode() == ISD::Constant && 5157 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 5158 // is LH an extension of the sign bit of LL? 5159 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 5160 LH.getOperand(1).getOpcode() == ISD::Constant && 5161 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 5162 // Low part: 5163 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5164 // High part: 5165 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 5166 break; 5167 } else if (HasMULHU) { 5168 // Low part: 5169 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5170 5171 // High part: 5172 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 5173 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 5174 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 5175 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 5176 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 5177 break; 5178 } 5179 } 5180 5181 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 5182 false/*sign irrelevant*/, Hi); 5183 break; 5184 } 5185 case ISD::SDIV: 5186 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 5187 break; 5188 case ISD::UDIV: 5189 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 5190 break; 5191 case ISD::SREM: 5192 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 5193 break; 5194 case ISD::UREM: 5195 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 5196 break; 5197 5198 case ISD::FADD: 5199 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5200 ? RTLIB::ADD_F32 : RTLIB::ADD_F64), 5201 Node, false, Hi); 5202 break; 5203 case ISD::FSUB: 5204 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5205 ? RTLIB::SUB_F32 : RTLIB::SUB_F64), 5206 Node, false, Hi); 5207 break; 5208 case ISD::FMUL: 5209 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5210 ? RTLIB::MUL_F32 : RTLIB::MUL_F64), 5211 Node, false, Hi); 5212 break; 5213 case ISD::FDIV: 5214 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5215 ? RTLIB::DIV_F32 : RTLIB::DIV_F64), 5216 Node, false, Hi); 5217 break; 5218 case ISD::FP_EXTEND: 5219 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 5220 break; 5221 case ISD::FP_ROUND: 5222 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 5223 break; 5224 case ISD::FSQRT: 5225 case ISD::FSIN: 5226 case ISD::FCOS: { 5227 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5228 switch(Node->getOpcode()) { 5229 case ISD::FSQRT: 5230 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64; 5231 break; 5232 case ISD::FSIN: 5233 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 5234 break; 5235 case ISD::FCOS: 5236 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64; 5237 break; 5238 default: assert(0 && "Unreachable!"); 5239 } 5240 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 5241 break; 5242 } 5243 case ISD::FABS: { 5244 SDOperand Mask = (VT == MVT::f64) 5245 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 5246 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 5247 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 5248 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5249 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 5250 if (getTypeAction(NVT) == Expand) 5251 ExpandOp(Lo, Lo, Hi); 5252 break; 5253 } 5254 case ISD::FNEG: { 5255 SDOperand Mask = (VT == MVT::f64) 5256 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 5257 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 5258 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 5259 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5260 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 5261 if (getTypeAction(NVT) == Expand) 5262 ExpandOp(Lo, Lo, Hi); 5263 break; 5264 } 5265 case ISD::FCOPYSIGN: { 5266 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 5267 if (getTypeAction(NVT) == Expand) 5268 ExpandOp(Lo, Lo, Hi); 5269 break; 5270 } 5271 case ISD::SINT_TO_FP: 5272 case ISD::UINT_TO_FP: { 5273 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 5274 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 5275 RTLIB::Libcall LC; 5276 if (Node->getOperand(0).getValueType() == MVT::i64) { 5277 if (VT == MVT::f32) 5278 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; 5279 else 5280 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; 5281 } else { 5282 if (VT == MVT::f32) 5283 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 5284 else 5285 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 5286 } 5287 5288 // Promote the operand if needed. 5289 if (getTypeAction(SrcVT) == Promote) { 5290 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 5291 Tmp = isSigned 5292 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 5293 DAG.getValueType(SrcVT)) 5294 : DAG.getZeroExtendInReg(Tmp, SrcVT); 5295 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 5296 } 5297 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi); 5298 break; 5299 } 5300 } 5301 5302 // Make sure the resultant values have been legalized themselves, unless this 5303 // is a type that requires multi-step expansion. 5304 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 5305 Lo = LegalizeOp(Lo); 5306 if (Hi.Val) 5307 // Don't legalize the high part if it is expanded to a single node. 5308 Hi = LegalizeOp(Hi); 5309 } 5310 5311 // Remember in a map if the values will be reused later. 5312 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 5313 assert(isNew && "Value already expanded?!?"); 5314} 5315 5316/// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 5317/// two smaller values of MVT::Vector type. 5318void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 5319 SDOperand &Hi) { 5320 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!"); 5321 SDNode *Node = Op.Val; 5322 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue(); 5323 assert(NumElements > 1 && "Cannot split a single element vector!"); 5324 unsigned NewNumElts = NumElements/2; 5325 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32); 5326 SDOperand TypeNode = *(Node->op_end()-1); 5327 5328 // See if we already split it. 5329 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5330 = SplitNodes.find(Op); 5331 if (I != SplitNodes.end()) { 5332 Lo = I->second.first; 5333 Hi = I->second.second; 5334 return; 5335 } 5336 5337 switch (Node->getOpcode()) { 5338 default: 5339#ifndef NDEBUG 5340 Node->dump(); 5341#endif 5342 assert(0 && "Unhandled operation in SplitVectorOp!"); 5343 case ISD::VBUILD_VECTOR: { 5344 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 5345 Node->op_begin()+NewNumElts); 5346 LoOps.push_back(NewNumEltsNode); 5347 LoOps.push_back(TypeNode); 5348 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size()); 5349 5350 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts, 5351 Node->op_end()-2); 5352 HiOps.push_back(NewNumEltsNode); 5353 HiOps.push_back(TypeNode); 5354 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size()); 5355 break; 5356 } 5357 case ISD::VADD: 5358 case ISD::VSUB: 5359 case ISD::VMUL: 5360 case ISD::VSDIV: 5361 case ISD::VUDIV: 5362 case ISD::VAND: 5363 case ISD::VOR: 5364 case ISD::VXOR: { 5365 SDOperand LL, LH, RL, RH; 5366 SplitVectorOp(Node->getOperand(0), LL, LH); 5367 SplitVectorOp(Node->getOperand(1), RL, RH); 5368 5369 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, 5370 NewNumEltsNode, TypeNode); 5371 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, 5372 NewNumEltsNode, TypeNode); 5373 break; 5374 } 5375 case ISD::VLOAD: { 5376 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5377 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5378 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 5379 5380 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 5381 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8; 5382 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5383 getIntPtrConstant(IncrementSize)); 5384 // FIXME: This creates a bogus srcvalue! 5385 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 5386 5387 // Build a factor node to remember that this load is independent of the 5388 // other one. 5389 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5390 Hi.getValue(1)); 5391 5392 // Remember that we legalized the chain. 5393 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5394 break; 5395 } 5396 case ISD::VBIT_CONVERT: { 5397 // We know the result is a vector. The input may be either a vector or a 5398 // scalar value. 5399 if (Op.getOperand(0).getValueType() != MVT::Vector) { 5400 // Lower to a store/load. FIXME: this could be improved probably. 5401 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType()); 5402 5403 SDOperand St = DAG.getStore(DAG.getEntryNode(), 5404 Op.getOperand(0), Ptr, NULL, 0); 5405 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 5406 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0)); 5407 SplitVectorOp(St, Lo, Hi); 5408 } else { 5409 // If the input is a vector type, we have to either scalarize it, pack it 5410 // or convert it based on whether the input vector type is legal. 5411 SDNode *InVal = Node->getOperand(0).Val; 5412 unsigned NumElems = 5413 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 5414 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 5415 5416 // If the input is from a single element vector, scalarize the vector, 5417 // then treat like a scalar. 5418 if (NumElems == 1) { 5419 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT); 5420 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar, 5421 Op.getOperand(1), Op.getOperand(2)); 5422 SplitVectorOp(Scalar, Lo, Hi); 5423 } else { 5424 // Split the input vector. 5425 SplitVectorOp(Op.getOperand(0), Lo, Hi); 5426 5427 // Convert each of the pieces now. 5428 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo, 5429 NewNumEltsNode, TypeNode); 5430 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi, 5431 NewNumEltsNode, TypeNode); 5432 } 5433 break; 5434 } 5435 } 5436 } 5437 5438 // Remember in a map if the values will be reused later. 5439 bool isNew = 5440 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 5441 assert(isNew && "Value already expanded?!?"); 5442} 5443 5444 5445/// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 5446/// equivalent operation that returns a scalar (e.g. F32) or packed value 5447/// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right 5448/// type for the result. 5449SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, 5450 MVT::ValueType NewVT) { 5451 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!"); 5452 SDNode *Node = Op.Val; 5453 5454 // See if we already packed it. 5455 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op); 5456 if (I != PackedNodes.end()) return I->second; 5457 5458 SDOperand Result; 5459 switch (Node->getOpcode()) { 5460 default: 5461#ifndef NDEBUG 5462 Node->dump(); cerr << "\n"; 5463#endif 5464 assert(0 && "Unknown vector operation in PackVectorOp!"); 5465 case ISD::VADD: 5466 case ISD::VSUB: 5467 case ISD::VMUL: 5468 case ISD::VSDIV: 5469 case ISD::VUDIV: 5470 case ISD::VAND: 5471 case ISD::VOR: 5472 case ISD::VXOR: 5473 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT), 5474 NewVT, 5475 PackVectorOp(Node->getOperand(0), NewVT), 5476 PackVectorOp(Node->getOperand(1), NewVT)); 5477 break; 5478 case ISD::VLOAD: { 5479 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 5480 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 5481 5482 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 5483 Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset()); 5484 5485 // Remember that we legalized the chain. 5486 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 5487 break; 5488 } 5489 case ISD::VBUILD_VECTOR: 5490 if (Node->getOperand(0).getValueType() == NewVT) { 5491 // Returning a scalar? 5492 Result = Node->getOperand(0); 5493 } else { 5494 // Returning a BUILD_VECTOR? 5495 5496 // If all elements of the build_vector are undefs, return an undef. 5497 bool AllUndef = true; 5498 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i) 5499 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) { 5500 AllUndef = false; 5501 break; 5502 } 5503 if (AllUndef) { 5504 Result = DAG.getNode(ISD::UNDEF, NewVT); 5505 } else { 5506 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(), 5507 Node->getNumOperands()-2); 5508 } 5509 } 5510 break; 5511 case ISD::VINSERT_VECTOR_ELT: 5512 if (!MVT::isVector(NewVT)) { 5513 // Returning a scalar? Must be the inserted element. 5514 Result = Node->getOperand(1); 5515 } else { 5516 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, 5517 PackVectorOp(Node->getOperand(0), NewVT), 5518 Node->getOperand(1), Node->getOperand(2)); 5519 } 5520 break; 5521 case ISD::VVECTOR_SHUFFLE: 5522 if (!MVT::isVector(NewVT)) { 5523 // Returning a scalar? Figure out if it is the LHS or RHS and return it. 5524 SDOperand EltNum = Node->getOperand(2).getOperand(0); 5525 if (cast<ConstantSDNode>(EltNum)->getValue()) 5526 Result = PackVectorOp(Node->getOperand(1), NewVT); 5527 else 5528 Result = PackVectorOp(Node->getOperand(0), NewVT); 5529 } else { 5530 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index 5531 // vector from a VBUILD_VECTOR to a BUILD_VECTOR. 5532 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(), 5533 Node->getOperand(2).Val->op_end()-2); 5534 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size()); 5535 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, 5536 Node->getOperand(2).Val->op_begin(), 5537 Node->getOperand(2).Val->getNumOperands()-2); 5538 5539 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, 5540 PackVectorOp(Node->getOperand(0), NewVT), 5541 PackVectorOp(Node->getOperand(1), NewVT), BV); 5542 } 5543 break; 5544 case ISD::VBIT_CONVERT: 5545 if (Op.getOperand(0).getValueType() != MVT::Vector) 5546 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 5547 else { 5548 // If the input is a vector type, we have to either scalarize it, pack it 5549 // or convert it based on whether the input vector type is legal. 5550 SDNode *InVal = Node->getOperand(0).Val; 5551 unsigned NumElems = 5552 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 5553 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 5554 5555 // Figure out if there is a Packed type corresponding to this Vector 5556 // type. If so, convert to the packed type. 5557 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 5558 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 5559 // Turn this into a bit convert of the packed input. 5560 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 5561 PackVectorOp(Node->getOperand(0), TVT)); 5562 break; 5563 } else if (NumElems == 1) { 5564 // Turn this into a bit convert of the scalar input. 5565 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 5566 PackVectorOp(Node->getOperand(0), EVT)); 5567 break; 5568 } else { 5569 // FIXME: UNIMP! 5570 assert(0 && "Cast from unsupported vector type not implemented yet!"); 5571 } 5572 } 5573 break; 5574 case ISD::VSELECT: 5575 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 5576 PackVectorOp(Op.getOperand(1), NewVT), 5577 PackVectorOp(Op.getOperand(2), NewVT)); 5578 break; 5579 } 5580 5581 if (TLI.isTypeLegal(NewVT)) 5582 Result = LegalizeOp(Result); 5583 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second; 5584 assert(isNew && "Value already packed?"); 5585 return Result; 5586} 5587 5588 5589// SelectionDAG::Legalize - This is the entry point for the file. 5590// 5591void SelectionDAG::Legalize() { 5592 if (ViewLegalizeDAGs) viewGraph(); 5593 5594 /// run - This is the main entry point to this class. 5595 /// 5596 SelectionDAGLegalize(*this).LegalizeDAG(); 5597} 5598 5599