LegalizeDAG.cpp revision 4f17f88071260cecffd96c272098549ac5887523
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/ADT/SmallPtrSet.h" 16#include "llvm/ADT/SmallVector.h" 17#include "llvm/ADT/Triple.h" 18#include "llvm/CodeGen/Analysis.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineJumpTableInfo.h" 21#include "llvm/DebugInfo.h" 22#include "llvm/IR/CallingConv.h" 23#include "llvm/IR/Constants.h" 24#include "llvm/IR/DataLayout.h" 25#include "llvm/IR/DerivedTypes.h" 26#include "llvm/IR/Function.h" 27#include "llvm/IR/LLVMContext.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31#include "llvm/Support/raw_ostream.h" 32#include "llvm/Target/TargetFrameLowering.h" 33#include "llvm/Target/TargetLowering.h" 34#include "llvm/Target/TargetMachine.h" 35using namespace llvm; 36 37//===----------------------------------------------------------------------===// 38/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 39/// hacks on it until the target machine can handle it. This involves 40/// eliminating value sizes the machine cannot handle (promoting small sizes to 41/// large sizes or splitting up large values into small values) as well as 42/// eliminating operations the machine cannot handle. 43/// 44/// This code also does a small amount of optimization and recognition of idioms 45/// as part of its processing. For example, if a target does not support a 46/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 47/// will attempt merge setcc and brc instructions into brcc's. 48/// 49namespace { 50class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener { 51 const TargetMachine &TM; 52 const TargetLowering &TLI; 53 SelectionDAG &DAG; 54 55 /// LegalizePosition - The iterator for walking through the node list. 56 SelectionDAG::allnodes_iterator LegalizePosition; 57 58 /// LegalizedNodes - The set of nodes which have already been legalized. 59 SmallPtrSet<SDNode *, 16> LegalizedNodes; 60 61 EVT getSetCCResultType(EVT VT) const { 62 return TLI.getSetCCResultType(*DAG.getContext(), VT); 63 } 64 65 // Libcall insertion helpers. 66 67public: 68 explicit SelectionDAGLegalize(SelectionDAG &DAG); 69 70 void LegalizeDAG(); 71 72private: 73 /// LegalizeOp - Legalizes the given operation. 74 void LegalizeOp(SDNode *Node); 75 76 SDValue OptimizeFloatStore(StoreSDNode *ST); 77 78 void LegalizeLoadOps(SDNode *Node); 79 void LegalizeStoreOps(SDNode *Node); 80 81 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 82 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 83 /// is necessary to spill the vector being inserted into to memory, perform 84 /// the insert there, and then read the result back. 85 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 86 SDValue Idx, SDLoc dl); 87 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 88 SDValue Idx, SDLoc dl); 89 90 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 91 /// performs the same shuffe in terms of order or result bytes, but on a type 92 /// whose vector element type is narrower than the original shuffle type. 93 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 94 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl, 95 SDValue N1, SDValue N2, 96 ArrayRef<int> Mask) const; 97 98 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 99 SDLoc dl); 100 101 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 102 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, 103 unsigned NumOps, bool isSigned, SDLoc dl); 104 105 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC, 106 SDNode *Node, bool isSigned); 107 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 108 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 109 RTLIB::Libcall Call_F128, 110 RTLIB::Libcall Call_PPCF128); 111 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 112 RTLIB::Libcall Call_I8, 113 RTLIB::Libcall Call_I16, 114 RTLIB::Libcall Call_I32, 115 RTLIB::Libcall Call_I64, 116 RTLIB::Libcall Call_I128); 117 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results); 118 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results); 119 120 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl); 121 SDValue ExpandBUILD_VECTOR(SDNode *Node); 122 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 123 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 124 SmallVectorImpl<SDValue> &Results); 125 SDValue ExpandFCOPYSIGN(SDNode *Node); 126 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 127 SDLoc dl); 128 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 129 SDLoc dl); 130 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 131 SDLoc dl); 132 133 SDValue ExpandBSWAP(SDValue Op, SDLoc dl); 134 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl); 135 136 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 137 SDValue ExpandInsertToVectorThroughStack(SDValue Op); 138 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 139 140 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP); 141 142 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node); 143 144 void ExpandNode(SDNode *Node); 145 void PromoteNode(SDNode *Node); 146 147 void ForgetNode(SDNode *N) { 148 LegalizedNodes.erase(N); 149 if (LegalizePosition == SelectionDAG::allnodes_iterator(N)) 150 ++LegalizePosition; 151 } 152 153public: 154 // DAGUpdateListener implementation. 155 virtual void NodeDeleted(SDNode *N, SDNode *E) { 156 ForgetNode(N); 157 } 158 virtual void NodeUpdated(SDNode *N) {} 159 160 // Node replacement helpers 161 void ReplacedNode(SDNode *N) { 162 if (N->use_empty()) { 163 DAG.RemoveDeadNode(N); 164 } else { 165 ForgetNode(N); 166 } 167 } 168 void ReplaceNode(SDNode *Old, SDNode *New) { 169 DAG.ReplaceAllUsesWith(Old, New); 170 ReplacedNode(Old); 171 } 172 void ReplaceNode(SDValue Old, SDValue New) { 173 DAG.ReplaceAllUsesWith(Old, New); 174 ReplacedNode(Old.getNode()); 175 } 176 void ReplaceNode(SDNode *Old, const SDValue *New) { 177 DAG.ReplaceAllUsesWith(Old, New); 178 ReplacedNode(Old); 179 } 180}; 181} 182 183/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 184/// performs the same shuffe in terms of order or result bytes, but on a type 185/// whose vector element type is narrower than the original shuffle type. 186/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 187SDValue 188SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl, 189 SDValue N1, SDValue N2, 190 ArrayRef<int> Mask) const { 191 unsigned NumMaskElts = VT.getVectorNumElements(); 192 unsigned NumDestElts = NVT.getVectorNumElements(); 193 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 194 195 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 196 197 if (NumEltsGrowth == 1) 198 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 199 200 SmallVector<int, 8> NewMask; 201 for (unsigned i = 0; i != NumMaskElts; ++i) { 202 int Idx = Mask[i]; 203 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 204 if (Idx < 0) 205 NewMask.push_back(-1); 206 else 207 NewMask.push_back(Idx * NumEltsGrowth + j); 208 } 209 } 210 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 211 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 213} 214 215SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 216 : SelectionDAG::DAGUpdateListener(dag), 217 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 218 DAG(dag) { 219} 220 221void SelectionDAGLegalize::LegalizeDAG() { 222 DAG.AssignTopologicalOrder(); 223 224 // Visit all the nodes. We start in topological order, so that we see 225 // nodes with their original operands intact. Legalization can produce 226 // new nodes which may themselves need to be legalized. Iterate until all 227 // nodes have been legalized. 228 for (;;) { 229 bool AnyLegalized = false; 230 for (LegalizePosition = DAG.allnodes_end(); 231 LegalizePosition != DAG.allnodes_begin(); ) { 232 --LegalizePosition; 233 234 SDNode *N = LegalizePosition; 235 if (LegalizedNodes.insert(N)) { 236 AnyLegalized = true; 237 LegalizeOp(N); 238 } 239 } 240 if (!AnyLegalized) 241 break; 242 243 } 244 245 // Remove dead nodes now. 246 DAG.RemoveDeadNodes(); 247} 248 249/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 250/// a load from the constant pool. 251SDValue 252SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) { 253 bool Extend = false; 254 SDLoc dl(CFP); 255 256 // If a FP immediate is precise when represented as a float and if the 257 // target can do an extending load from float to double, we put it into 258 // the constant pool as a float, even if it's is statically typed as a 259 // double. This shrinks FP constants and canonicalizes them for targets where 260 // an FP extending load is the same cost as a normal load (such as on the x87 261 // fp stack or PPC FP unit). 262 EVT VT = CFP->getValueType(0); 263 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 264 if (!UseCP) { 265 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 266 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 267 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 268 } 269 270 EVT OrigVT = VT; 271 EVT SVT = VT; 272 while (SVT != MVT::f32) { 273 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 274 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) && 275 // Only do this if the target has a native EXTLOAD instruction from 276 // smaller type. 277 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 278 TLI.ShouldShrinkFPConstant(OrigVT)) { 279 Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 280 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 281 VT = SVT; 282 Extend = true; 283 } 284 } 285 286 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 287 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 288 if (Extend) { 289 SDValue Result = 290 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, 291 DAG.getEntryNode(), 292 CPIdx, MachinePointerInfo::getConstantPool(), 293 VT, false, false, Alignment); 294 return Result; 295 } 296 SDValue Result = 297 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 298 MachinePointerInfo::getConstantPool(), false, false, false, 299 Alignment); 300 return Result; 301} 302 303/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 304static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 305 const TargetLowering &TLI, 306 SelectionDAGLegalize *DAGLegalize) { 307 assert(ST->getAddressingMode() == ISD::UNINDEXED && 308 "unaligned indexed stores not implemented!"); 309 SDValue Chain = ST->getChain(); 310 SDValue Ptr = ST->getBasePtr(); 311 SDValue Val = ST->getValue(); 312 EVT VT = Val.getValueType(); 313 int Alignment = ST->getAlignment(); 314 unsigned AS = ST->getAddressSpace(); 315 316 SDLoc dl(ST); 317 if (ST->getMemoryVT().isFloatingPoint() || 318 ST->getMemoryVT().isVector()) { 319 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 320 if (TLI.isTypeLegal(intVT)) { 321 // Expand to a bitconvert of the value to the integer type of the 322 // same size, then a (misaligned) int store. 323 // FIXME: Does not handle truncating floating point stores! 324 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); 325 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(), 326 ST->isVolatile(), ST->isNonTemporal(), Alignment); 327 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result); 328 return; 329 } 330 // Do a (aligned) store to a stack slot, then copy from the stack slot 331 // to the final destination using (unaligned) integer loads and stores. 332 EVT StoredVT = ST->getMemoryVT(); 333 MVT RegVT = 334 TLI.getRegisterType(*DAG.getContext(), 335 EVT::getIntegerVT(*DAG.getContext(), 336 StoredVT.getSizeInBits())); 337 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 338 unsigned RegBytes = RegVT.getSizeInBits() / 8; 339 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 340 341 // Make sure the stack slot is also aligned for the register type. 342 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 343 344 // Perform the original store, only redirected to the stack slot. 345 SDValue Store = DAG.getTruncStore(Chain, dl, 346 Val, StackPtr, MachinePointerInfo(), 347 StoredVT, false, false, 0); 348 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy(AS)); 349 SmallVector<SDValue, 8> Stores; 350 unsigned Offset = 0; 351 352 // Do all but one copies using the full register width. 353 for (unsigned i = 1; i < NumRegs; i++) { 354 // Load one integer register's worth from the stack slot. 355 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, 356 MachinePointerInfo(), 357 false, false, false, 0); 358 // Store it to the final location. Remember the store. 359 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 360 ST->getPointerInfo().getWithOffset(Offset), 361 ST->isVolatile(), ST->isNonTemporal(), 362 MinAlign(ST->getAlignment(), Offset))); 363 // Increment the pointers. 364 Offset += RegBytes; 365 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 366 Increment); 367 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 368 } 369 370 // The last store may be partial. Do a truncating store. On big-endian 371 // machines this requires an extending load from the stack slot to ensure 372 // that the bits are in the right place. 373 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 374 8 * (StoredBytes - Offset)); 375 376 // Load from the stack slot. 377 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 378 MachinePointerInfo(), 379 MemVT, false, false, 0); 380 381 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 382 ST->getPointerInfo() 383 .getWithOffset(Offset), 384 MemVT, ST->isVolatile(), 385 ST->isNonTemporal(), 386 MinAlign(ST->getAlignment(), Offset), 387 ST->getTBAAInfo())); 388 // The order of the stores doesn't matter - say it with a TokenFactor. 389 SDValue Result = 390 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 391 Stores.size()); 392 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result); 393 return; 394 } 395 assert(ST->getMemoryVT().isInteger() && 396 !ST->getMemoryVT().isVector() && 397 "Unaligned store of unknown type."); 398 // Get the half-size VT 399 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 400 int NumBits = NewStoredVT.getSizeInBits(); 401 int IncrementSize = NumBits / 8; 402 403 // Divide the stored value in two parts. 404 SDValue ShiftAmount = DAG.getConstant(NumBits, 405 TLI.getShiftAmountTy(Val.getValueType())); 406 SDValue Lo = Val; 407 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 408 409 // Store the two parts 410 SDValue Store1, Store2; 411 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 412 ST->getPointerInfo(), NewStoredVT, 413 ST->isVolatile(), ST->isNonTemporal(), Alignment); 414 415 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 416 DAG.getConstant(IncrementSize, TLI.getPointerTy(AS))); 417 Alignment = MinAlign(Alignment, IncrementSize); 418 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 419 ST->getPointerInfo().getWithOffset(IncrementSize), 420 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 421 Alignment, ST->getTBAAInfo()); 422 423 SDValue Result = 424 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 425 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result); 426} 427 428/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 429static void 430ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 431 const TargetLowering &TLI, 432 SDValue &ValResult, SDValue &ChainResult) { 433 assert(LD->getAddressingMode() == ISD::UNINDEXED && 434 "unaligned indexed loads not implemented!"); 435 SDValue Chain = LD->getChain(); 436 SDValue Ptr = LD->getBasePtr(); 437 EVT VT = LD->getValueType(0); 438 EVT LoadedVT = LD->getMemoryVT(); 439 SDLoc dl(LD); 440 if (VT.isFloatingPoint() || VT.isVector()) { 441 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 442 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) { 443 // Expand to a (misaligned) integer load of the same size, 444 // then bitconvert to floating point or vector. 445 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, 446 LD->getMemOperand()); 447 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); 448 if (LoadedVT != VT) 449 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND : 450 ISD::ANY_EXTEND, dl, VT, Result); 451 452 ValResult = Result; 453 ChainResult = Chain; 454 return; 455 } 456 457 // Copy the value to a (aligned) stack slot using (unaligned) integer 458 // loads and stores, then do a (aligned) load from the stack slot. 459 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 460 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 461 unsigned RegBytes = RegVT.getSizeInBits() / 8; 462 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 463 464 // Make sure the stack slot is also aligned for the register type. 465 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 466 467 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 468 SmallVector<SDValue, 8> Stores; 469 SDValue StackPtr = StackBase; 470 unsigned Offset = 0; 471 472 // Do all but one copies using the full register width. 473 for (unsigned i = 1; i < NumRegs; i++) { 474 // Load one integer register's worth from the original location. 475 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, 476 LD->getPointerInfo().getWithOffset(Offset), 477 LD->isVolatile(), LD->isNonTemporal(), 478 LD->isInvariant(), 479 MinAlign(LD->getAlignment(), Offset), 480 LD->getTBAAInfo()); 481 // Follow the load with a store to the stack slot. Remember the store. 482 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 483 MachinePointerInfo(), false, false, 0)); 484 // Increment the pointers. 485 Offset += RegBytes; 486 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 487 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 488 Increment); 489 } 490 491 // The last copy may be partial. Do an extending load. 492 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 493 8 * (LoadedBytes - Offset)); 494 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 495 LD->getPointerInfo().getWithOffset(Offset), 496 MemVT, LD->isVolatile(), 497 LD->isNonTemporal(), 498 MinAlign(LD->getAlignment(), Offset), 499 LD->getTBAAInfo()); 500 // Follow the load with a store to the stack slot. Remember the store. 501 // On big-endian machines this requires a truncating store to ensure 502 // that the bits end up in the right place. 503 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 504 MachinePointerInfo(), MemVT, 505 false, false, 0)); 506 507 // The order of the stores doesn't matter - say it with a TokenFactor. 508 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 509 Stores.size()); 510 511 // Finally, perform the original load only redirected to the stack slot. 512 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 513 MachinePointerInfo(), LoadedVT, false, false, 0); 514 515 // Callers expect a MERGE_VALUES node. 516 ValResult = Load; 517 ChainResult = TF; 518 return; 519 } 520 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 521 "Unaligned load of unsupported type."); 522 523 // Compute the new VT that is half the size of the old one. This is an 524 // integer MVT. 525 unsigned NumBits = LoadedVT.getSizeInBits(); 526 EVT NewLoadedVT; 527 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 528 NumBits >>= 1; 529 530 unsigned Alignment = LD->getAlignment(); 531 unsigned IncrementSize = NumBits / 8; 532 ISD::LoadExtType HiExtType = LD->getExtensionType(); 533 534 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 535 if (HiExtType == ISD::NON_EXTLOAD) 536 HiExtType = ISD::ZEXTLOAD; 537 538 // Load the value in two parts 539 SDValue Lo, Hi; 540 if (TLI.isLittleEndian()) { 541 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), 542 NewLoadedVT, LD->isVolatile(), 543 LD->isNonTemporal(), Alignment, LD->getTBAAInfo()); 544 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 545 DAG.getConstant(IncrementSize, Ptr.getValueType())); 546 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, 547 LD->getPointerInfo().getWithOffset(IncrementSize), 548 NewLoadedVT, LD->isVolatile(), 549 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize), 550 LD->getTBAAInfo()); 551 } else { 552 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(), 553 NewLoadedVT, LD->isVolatile(), 554 LD->isNonTemporal(), Alignment, LD->getTBAAInfo()); 555 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 556 DAG.getConstant(IncrementSize, Ptr.getValueType())); 557 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, 558 LD->getPointerInfo().getWithOffset(IncrementSize), 559 NewLoadedVT, LD->isVolatile(), 560 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize), 561 LD->getTBAAInfo()); 562 } 563 564 // aggregate the two parts 565 SDValue ShiftAmount = DAG.getConstant(NumBits, 566 TLI.getShiftAmountTy(Hi.getValueType())); 567 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 568 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 569 570 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 571 Hi.getValue(1)); 572 573 ValResult = Result; 574 ChainResult = TF; 575} 576 577/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 578/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 579/// is necessary to spill the vector being inserted into to memory, perform 580/// the insert there, and then read the result back. 581SDValue SelectionDAGLegalize:: 582PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 583 SDLoc dl) { 584 SDValue Tmp1 = Vec; 585 SDValue Tmp2 = Val; 586 SDValue Tmp3 = Idx; 587 588 // If the target doesn't support this, we have to spill the input vector 589 // to a temporary stack slot, update the element, then reload it. This is 590 // badness. We could also load the value into a vector register (either 591 // with a "move to register" or "extload into register" instruction, then 592 // permute it into place, if the idx is a constant and if the idx is 593 // supported by the target. 594 EVT VT = Tmp1.getValueType(); 595 EVT EltVT = VT.getVectorElementType(); 596 EVT IdxVT = Tmp3.getValueType(); 597 EVT PtrVT = TLI.getPointerTy(); 598 SDValue StackPtr = DAG.CreateStackTemporary(VT); 599 600 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 601 602 // Store the vector. 603 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 604 MachinePointerInfo::getFixedStack(SPFI), 605 false, false, 0); 606 607 // Truncate or zero extend offset to target pointer type. 608 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 609 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 610 // Add the offset to the index. 611 unsigned EltSize = EltVT.getSizeInBits()/8; 612 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 613 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 614 // Store the scalar value. 615 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT, 616 false, false, 0); 617 // Load the updated vector. 618 return DAG.getLoad(VT, dl, Ch, StackPtr, 619 MachinePointerInfo::getFixedStack(SPFI), false, false, 620 false, 0); 621} 622 623 624SDValue SelectionDAGLegalize:: 625ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) { 626 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 627 // SCALAR_TO_VECTOR requires that the type of the value being inserted 628 // match the element type of the vector being created, except for 629 // integers in which case the inserted value can be over width. 630 EVT EltVT = Vec.getValueType().getVectorElementType(); 631 if (Val.getValueType() == EltVT || 632 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 633 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 634 Vec.getValueType(), Val); 635 636 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 637 // We generate a shuffle of InVec and ScVec, so the shuffle mask 638 // should be 0,1,2,3,4,5... with the appropriate element replaced with 639 // elt 0 of the RHS. 640 SmallVector<int, 8> ShufOps; 641 for (unsigned i = 0; i != NumElts; ++i) 642 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 643 644 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 645 &ShufOps[0]); 646 } 647 } 648 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 649} 650 651SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 652 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 653 // FIXME: We shouldn't do this for TargetConstantFP's. 654 // FIXME: move this to the DAG Combiner! Note that we can't regress due 655 // to phase ordering between legalized code and the dag combiner. This 656 // probably means that we need to integrate dag combiner and legalizer 657 // together. 658 // We generally can't do this one for long doubles. 659 SDValue Chain = ST->getChain(); 660 SDValue Ptr = ST->getBasePtr(); 661 unsigned Alignment = ST->getAlignment(); 662 bool isVolatile = ST->isVolatile(); 663 bool isNonTemporal = ST->isNonTemporal(); 664 const MDNode *TBAAInfo = ST->getTBAAInfo(); 665 SDLoc dl(ST); 666 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 667 if (CFP->getValueType(0) == MVT::f32 && 668 TLI.isTypeLegal(MVT::i32)) { 669 SDValue Con = DAG.getConstant(CFP->getValueAPF(). 670 bitcastToAPInt().zextOrTrunc(32), 671 MVT::i32); 672 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(), 673 isVolatile, isNonTemporal, Alignment, TBAAInfo); 674 } 675 676 if (CFP->getValueType(0) == MVT::f64) { 677 // If this target supports 64-bit registers, do a single 64-bit store. 678 if (TLI.isTypeLegal(MVT::i64)) { 679 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 680 zextOrTrunc(64), MVT::i64); 681 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(), 682 isVolatile, isNonTemporal, Alignment, TBAAInfo); 683 } 684 685 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) { 686 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 687 // stores. If the target supports neither 32- nor 64-bits, this 688 // xform is certainly not worth it. 689 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 690 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32); 691 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 692 if (TLI.isBigEndian()) std::swap(Lo, Hi); 693 694 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile, 695 isNonTemporal, Alignment, TBAAInfo); 696 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 697 DAG.getConstant(4, Ptr.getValueType())); 698 Hi = DAG.getStore(Chain, dl, Hi, Ptr, 699 ST->getPointerInfo().getWithOffset(4), 700 isVolatile, isNonTemporal, MinAlign(Alignment, 4U), 701 TBAAInfo); 702 703 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 704 } 705 } 706 } 707 return SDValue(0, 0); 708} 709 710void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) { 711 StoreSDNode *ST = cast<StoreSDNode>(Node); 712 SDValue Chain = ST->getChain(); 713 SDValue Ptr = ST->getBasePtr(); 714 SDLoc dl(Node); 715 716 unsigned Alignment = ST->getAlignment(); 717 bool isVolatile = ST->isVolatile(); 718 bool isNonTemporal = ST->isNonTemporal(); 719 const MDNode *TBAAInfo = ST->getTBAAInfo(); 720 721 if (!ST->isTruncatingStore()) { 722 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 723 ReplaceNode(ST, OptStore); 724 return; 725 } 726 727 { 728 SDValue Value = ST->getValue(); 729 MVT VT = Value.getSimpleValueType(); 730 switch (TLI.getOperationAction(ISD::STORE, VT)) { 731 default: llvm_unreachable("This action is not supported yet!"); 732 case TargetLowering::Legal: 733 // If this is an unaligned store and the target doesn't support it, 734 // expand it. 735 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 736 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 737 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty); 738 if (ST->getAlignment() < ABIAlignment) 739 ExpandUnalignedStore(cast<StoreSDNode>(Node), 740 DAG, TLI, this); 741 } 742 break; 743 case TargetLowering::Custom: { 744 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG); 745 if (Res.getNode()) 746 ReplaceNode(SDValue(Node, 0), Res); 747 return; 748 } 749 case TargetLowering::Promote: { 750 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT); 751 assert(NVT.getSizeInBits() == VT.getSizeInBits() && 752 "Can only promote stores to same size type"); 753 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value); 754 SDValue Result = 755 DAG.getStore(Chain, dl, Value, Ptr, 756 ST->getPointerInfo(), isVolatile, 757 isNonTemporal, Alignment, TBAAInfo); 758 ReplaceNode(SDValue(Node, 0), Result); 759 break; 760 } 761 } 762 return; 763 } 764 } else { 765 SDValue Value = ST->getValue(); 766 767 EVT StVT = ST->getMemoryVT(); 768 unsigned StWidth = StVT.getSizeInBits(); 769 770 if (StWidth != StVT.getStoreSizeInBits()) { 771 // Promote to a byte-sized store with upper bits zero if not 772 // storing an integral number of bytes. For example, promote 773 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 774 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), 775 StVT.getStoreSizeInBits()); 776 Value = DAG.getZeroExtendInReg(Value, dl, StVT); 777 SDValue Result = 778 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), 779 NVT, isVolatile, isNonTemporal, Alignment, 780 TBAAInfo); 781 ReplaceNode(SDValue(Node, 0), Result); 782 } else if (StWidth & (StWidth - 1)) { 783 // If not storing a power-of-2 number of bits, expand as two stores. 784 assert(!StVT.isVector() && "Unsupported truncstore!"); 785 unsigned RoundWidth = 1 << Log2_32(StWidth); 786 assert(RoundWidth < StWidth); 787 unsigned ExtraWidth = StWidth - RoundWidth; 788 assert(ExtraWidth < RoundWidth); 789 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 790 "Store size not an integral number of bytes!"); 791 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 792 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 793 SDValue Lo, Hi; 794 unsigned IncrementSize; 795 796 if (TLI.isLittleEndian()) { 797 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 798 // Store the bottom RoundWidth bits. 799 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), 800 RoundVT, 801 isVolatile, isNonTemporal, Alignment, 802 TBAAInfo); 803 804 // Store the remaining ExtraWidth bits. 805 IncrementSize = RoundWidth / 8; 806 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 807 DAG.getConstant(IncrementSize, Ptr.getValueType())); 808 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, 809 DAG.getConstant(RoundWidth, 810 TLI.getShiftAmountTy(Value.getValueType()))); 811 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, 812 ST->getPointerInfo().getWithOffset(IncrementSize), 813 ExtraVT, isVolatile, isNonTemporal, 814 MinAlign(Alignment, IncrementSize), TBAAInfo); 815 } else { 816 // Big endian - avoid unaligned stores. 817 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 818 // Store the top RoundWidth bits. 819 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, 820 DAG.getConstant(ExtraWidth, 821 TLI.getShiftAmountTy(Value.getValueType()))); 822 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(), 823 RoundVT, isVolatile, isNonTemporal, Alignment, 824 TBAAInfo); 825 826 // Store the remaining ExtraWidth bits. 827 IncrementSize = RoundWidth / 8; 828 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 829 DAG.getConstant(IncrementSize, Ptr.getValueType())); 830 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, 831 ST->getPointerInfo().getWithOffset(IncrementSize), 832 ExtraVT, isVolatile, isNonTemporal, 833 MinAlign(Alignment, IncrementSize), TBAAInfo); 834 } 835 836 // The order of the stores doesn't matter. 837 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 838 ReplaceNode(SDValue(Node, 0), Result); 839 } else { 840 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(), 841 StVT.getSimpleVT())) { 842 default: llvm_unreachable("This action is not supported yet!"); 843 case TargetLowering::Legal: 844 // If this is an unaligned store and the target doesn't support it, 845 // expand it. 846 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 847 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 848 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty); 849 if (ST->getAlignment() < ABIAlignment) 850 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this); 851 } 852 break; 853 case TargetLowering::Custom: { 854 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG); 855 if (Res.getNode()) 856 ReplaceNode(SDValue(Node, 0), Res); 857 return; 858 } 859 case TargetLowering::Expand: 860 assert(!StVT.isVector() && 861 "Vector Stores are handled in LegalizeVectorOps"); 862 863 // TRUNCSTORE:i16 i32 -> STORE i16 864 assert(TLI.isTypeLegal(StVT) && 865 "Do not know how to expand this store!"); 866 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value); 867 SDValue Result = 868 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), 869 isVolatile, isNonTemporal, Alignment, TBAAInfo); 870 ReplaceNode(SDValue(Node, 0), Result); 871 break; 872 } 873 } 874 } 875} 876 877void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) { 878 LoadSDNode *LD = cast<LoadSDNode>(Node); 879 SDValue Chain = LD->getChain(); // The chain. 880 SDValue Ptr = LD->getBasePtr(); // The base pointer. 881 SDValue Value; // The value returned by the load op. 882 SDLoc dl(Node); 883 884 ISD::LoadExtType ExtType = LD->getExtensionType(); 885 if (ExtType == ISD::NON_EXTLOAD) { 886 MVT VT = Node->getSimpleValueType(0); 887 SDValue RVal = SDValue(Node, 0); 888 SDValue RChain = SDValue(Node, 1); 889 890 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 891 default: llvm_unreachable("This action is not supported yet!"); 892 case TargetLowering::Legal: 893 // If this is an unaligned load and the target doesn't support it, 894 // expand it. 895 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 896 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 897 unsigned ABIAlignment = 898 TLI.getDataLayout()->getABITypeAlignment(Ty); 899 if (LD->getAlignment() < ABIAlignment){ 900 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain); 901 } 902 } 903 break; 904 case TargetLowering::Custom: { 905 SDValue Res = TLI.LowerOperation(RVal, DAG); 906 if (Res.getNode()) { 907 RVal = Res; 908 RChain = Res.getValue(1); 909 } 910 break; 911 } 912 case TargetLowering::Promote: { 913 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 914 assert(NVT.getSizeInBits() == VT.getSizeInBits() && 915 "Can only promote loads to same size type"); 916 917 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand()); 918 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res); 919 RChain = Res.getValue(1); 920 break; 921 } 922 } 923 if (RChain.getNode() != Node) { 924 assert(RVal.getNode() != Node && "Load must be completely replaced"); 925 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal); 926 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain); 927 ReplacedNode(Node); 928 } 929 return; 930 } 931 932 EVT SrcVT = LD->getMemoryVT(); 933 unsigned SrcWidth = SrcVT.getSizeInBits(); 934 unsigned Alignment = LD->getAlignment(); 935 bool isVolatile = LD->isVolatile(); 936 bool isNonTemporal = LD->isNonTemporal(); 937 const MDNode *TBAAInfo = LD->getTBAAInfo(); 938 939 if (SrcWidth != SrcVT.getStoreSizeInBits() && 940 // Some targets pretend to have an i1 loading operation, and actually 941 // load an i8. This trick is correct for ZEXTLOAD because the top 7 942 // bits are guaranteed to be zero; it helps the optimizers understand 943 // that these bits are zero. It is also useful for EXTLOAD, since it 944 // tells the optimizers that those bits are undefined. It would be 945 // nice to have an effective generic way of getting these benefits... 946 // Until such a way is found, don't insist on promoting i1 here. 947 (SrcVT != MVT::i1 || 948 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 949 // Promote to a byte-sized load if not loading an integral number of 950 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 951 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 952 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 953 SDValue Ch; 954 955 // The extra bits are guaranteed to be zero, since we stored them that 956 // way. A zext load from NVT thus automatically gives zext from SrcVT. 957 958 ISD::LoadExtType NewExtType = 959 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 960 961 SDValue Result = 962 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 963 Chain, Ptr, LD->getPointerInfo(), 964 NVT, isVolatile, isNonTemporal, Alignment, TBAAInfo); 965 966 Ch = Result.getValue(1); // The chain. 967 968 if (ExtType == ISD::SEXTLOAD) 969 // Having the top bits zero doesn't help when sign extending. 970 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 971 Result.getValueType(), 972 Result, DAG.getValueType(SrcVT)); 973 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 974 // All the top bits are guaranteed to be zero - inform the optimizers. 975 Result = DAG.getNode(ISD::AssertZext, dl, 976 Result.getValueType(), Result, 977 DAG.getValueType(SrcVT)); 978 979 Value = Result; 980 Chain = Ch; 981 } else if (SrcWidth & (SrcWidth - 1)) { 982 // If not loading a power-of-2 number of bits, expand as two loads. 983 assert(!SrcVT.isVector() && "Unsupported extload!"); 984 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 985 assert(RoundWidth < SrcWidth); 986 unsigned ExtraWidth = SrcWidth - RoundWidth; 987 assert(ExtraWidth < RoundWidth); 988 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 989 "Load size not an integral number of bytes!"); 990 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 991 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 992 SDValue Lo, Hi, Ch; 993 unsigned IncrementSize; 994 995 if (TLI.isLittleEndian()) { 996 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 997 // Load the bottom RoundWidth bits. 998 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), 999 Chain, Ptr, 1000 LD->getPointerInfo(), RoundVT, isVolatile, 1001 isNonTemporal, Alignment, TBAAInfo); 1002 1003 // Load the remaining ExtraWidth bits. 1004 IncrementSize = RoundWidth / 8; 1005 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1006 DAG.getConstant(IncrementSize, Ptr.getValueType())); 1007 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, 1008 LD->getPointerInfo().getWithOffset(IncrementSize), 1009 ExtraVT, isVolatile, isNonTemporal, 1010 MinAlign(Alignment, IncrementSize), TBAAInfo); 1011 1012 // Build a factor node to remember that this load is independent of 1013 // the other one. 1014 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1015 Hi.getValue(1)); 1016 1017 // Move the top bits to the right place. 1018 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1019 DAG.getConstant(RoundWidth, 1020 TLI.getShiftAmountTy(Hi.getValueType()))); 1021 1022 // Join the hi and lo parts. 1023 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1024 } else { 1025 // Big endian - avoid unaligned loads. 1026 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1027 // Load the top RoundWidth bits. 1028 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, 1029 LD->getPointerInfo(), RoundVT, isVolatile, 1030 isNonTemporal, Alignment, TBAAInfo); 1031 1032 // Load the remaining ExtraWidth bits. 1033 IncrementSize = RoundWidth / 8; 1034 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1035 DAG.getConstant(IncrementSize, Ptr.getValueType())); 1036 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, 1037 dl, Node->getValueType(0), Chain, Ptr, 1038 LD->getPointerInfo().getWithOffset(IncrementSize), 1039 ExtraVT, isVolatile, isNonTemporal, 1040 MinAlign(Alignment, IncrementSize), TBAAInfo); 1041 1042 // Build a factor node to remember that this load is independent of 1043 // the other one. 1044 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1045 Hi.getValue(1)); 1046 1047 // Move the top bits to the right place. 1048 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1049 DAG.getConstant(ExtraWidth, 1050 TLI.getShiftAmountTy(Hi.getValueType()))); 1051 1052 // Join the hi and lo parts. 1053 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1054 } 1055 1056 Chain = Ch; 1057 } else { 1058 bool isCustom = false; 1059 switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) { 1060 default: llvm_unreachable("This action is not supported yet!"); 1061 case TargetLowering::Custom: 1062 isCustom = true; 1063 // FALLTHROUGH 1064 case TargetLowering::Legal: { 1065 Value = SDValue(Node, 0); 1066 Chain = SDValue(Node, 1); 1067 1068 if (isCustom) { 1069 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG); 1070 if (Res.getNode()) { 1071 Value = Res; 1072 Chain = Res.getValue(1); 1073 } 1074 } else { 1075 // If this is an unaligned load and the target doesn't support it, 1076 // expand it. 1077 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1078 Type *Ty = 1079 LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1080 unsigned ABIAlignment = 1081 TLI.getDataLayout()->getABITypeAlignment(Ty); 1082 if (LD->getAlignment() < ABIAlignment){ 1083 ExpandUnalignedLoad(cast<LoadSDNode>(Node), 1084 DAG, TLI, Value, Chain); 1085 } 1086 } 1087 } 1088 break; 1089 } 1090 case TargetLowering::Expand: 1091 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) { 1092 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr, 1093 LD->getMemOperand()); 1094 unsigned ExtendOp; 1095 switch (ExtType) { 1096 case ISD::EXTLOAD: 1097 ExtendOp = (SrcVT.isFloatingPoint() ? 1098 ISD::FP_EXTEND : ISD::ANY_EXTEND); 1099 break; 1100 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break; 1101 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break; 1102 default: llvm_unreachable("Unexpected extend load type!"); 1103 } 1104 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load); 1105 Chain = Load.getValue(1); 1106 break; 1107 } 1108 1109 assert(!SrcVT.isVector() && 1110 "Vector Loads are handled in LegalizeVectorOps"); 1111 1112 // FIXME: This does not work for vectors on most targets. Sign- and 1113 // zero-extend operations are currently folded into extending loads, 1114 // whether they are legal or not, and then we end up here without any 1115 // support for legalizing them. 1116 assert(ExtType != ISD::EXTLOAD && 1117 "EXTLOAD should always be supported!"); 1118 // Turn the unsupported load into an EXTLOAD followed by an explicit 1119 // zero/sign extend inreg. 1120 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1121 Chain, Ptr, SrcVT, 1122 LD->getMemOperand()); 1123 SDValue ValRes; 1124 if (ExtType == ISD::SEXTLOAD) 1125 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1126 Result.getValueType(), 1127 Result, DAG.getValueType(SrcVT)); 1128 else 1129 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType()); 1130 Value = ValRes; 1131 Chain = Result.getValue(1); 1132 break; 1133 } 1134 } 1135 1136 // Since loads produce two values, make sure to remember that we legalized 1137 // both of them. 1138 if (Chain.getNode() != Node) { 1139 assert(Value.getNode() != Node && "Load must be completely replaced"); 1140 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value); 1141 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain); 1142 ReplacedNode(Node); 1143 } 1144} 1145 1146/// LegalizeOp - Return a legal replacement for the given operation, with 1147/// all legal operands. 1148void SelectionDAGLegalize::LegalizeOp(SDNode *Node) { 1149 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 1150 return; 1151 1152 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1153 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) == 1154 TargetLowering::TypeLegal && 1155 "Unexpected illegal type!"); 1156 1157 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1158 assert((TLI.getTypeAction(*DAG.getContext(), 1159 Node->getOperand(i).getValueType()) == 1160 TargetLowering::TypeLegal || 1161 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 1162 "Unexpected illegal type!"); 1163 1164 // Figure out the correct action; the way to query this varies by opcode 1165 TargetLowering::LegalizeAction Action = TargetLowering::Legal; 1166 bool SimpleFinishLegalizing = true; 1167 switch (Node->getOpcode()) { 1168 case ISD::INTRINSIC_W_CHAIN: 1169 case ISD::INTRINSIC_WO_CHAIN: 1170 case ISD::INTRINSIC_VOID: 1171 case ISD::STACKSAVE: 1172 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 1173 break; 1174 case ISD::VAARG: 1175 Action = TLI.getOperationAction(Node->getOpcode(), 1176 Node->getValueType(0)); 1177 if (Action != TargetLowering::Promote) 1178 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 1179 break; 1180 case ISD::SINT_TO_FP: 1181 case ISD::UINT_TO_FP: 1182 case ISD::EXTRACT_VECTOR_ELT: 1183 Action = TLI.getOperationAction(Node->getOpcode(), 1184 Node->getOperand(0).getValueType()); 1185 break; 1186 case ISD::FP_ROUND_INREG: 1187 case ISD::SIGN_EXTEND_INREG: { 1188 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 1189 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 1190 break; 1191 } 1192 case ISD::ATOMIC_STORE: { 1193 Action = TLI.getOperationAction(Node->getOpcode(), 1194 Node->getOperand(2).getValueType()); 1195 break; 1196 } 1197 case ISD::SELECT_CC: 1198 case ISD::SETCC: 1199 case ISD::BR_CC: { 1200 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 1201 Node->getOpcode() == ISD::SETCC ? 2 : 1; 1202 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 1203 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType(); 1204 ISD::CondCode CCCode = 1205 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 1206 Action = TLI.getCondCodeAction(CCCode, OpVT); 1207 if (Action == TargetLowering::Legal) { 1208 if (Node->getOpcode() == ISD::SELECT_CC) 1209 Action = TLI.getOperationAction(Node->getOpcode(), 1210 Node->getValueType(0)); 1211 else 1212 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 1213 } 1214 break; 1215 } 1216 case ISD::LOAD: 1217 case ISD::STORE: 1218 // FIXME: Model these properly. LOAD and STORE are complicated, and 1219 // STORE expects the unlegalized operand in some cases. 1220 SimpleFinishLegalizing = false; 1221 break; 1222 case ISD::CALLSEQ_START: 1223 case ISD::CALLSEQ_END: 1224 // FIXME: This shouldn't be necessary. These nodes have special properties 1225 // dealing with the recursive nature of legalization. Removing this 1226 // special case should be done as part of making LegalizeDAG non-recursive. 1227 SimpleFinishLegalizing = false; 1228 break; 1229 case ISD::EXTRACT_ELEMENT: 1230 case ISD::FLT_ROUNDS_: 1231 case ISD::SADDO: 1232 case ISD::SSUBO: 1233 case ISD::UADDO: 1234 case ISD::USUBO: 1235 case ISD::SMULO: 1236 case ISD::UMULO: 1237 case ISD::FPOWI: 1238 case ISD::MERGE_VALUES: 1239 case ISD::EH_RETURN: 1240 case ISD::FRAME_TO_ARGS_OFFSET: 1241 case ISD::EH_SJLJ_SETJMP: 1242 case ISD::EH_SJLJ_LONGJMP: 1243 // These operations lie about being legal: when they claim to be legal, 1244 // they should actually be expanded. 1245 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 1246 if (Action == TargetLowering::Legal) 1247 Action = TargetLowering::Expand; 1248 break; 1249 case ISD::INIT_TRAMPOLINE: 1250 case ISD::ADJUST_TRAMPOLINE: 1251 case ISD::FRAMEADDR: 1252 case ISD::RETURNADDR: 1253 // These operations lie about being legal: when they claim to be legal, 1254 // they should actually be custom-lowered. 1255 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 1256 if (Action == TargetLowering::Legal) 1257 Action = TargetLowering::Custom; 1258 break; 1259 case ISD::DEBUGTRAP: 1260 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 1261 if (Action == TargetLowering::Expand) { 1262 // replace ISD::DEBUGTRAP with ISD::TRAP 1263 SDValue NewVal; 1264 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(), 1265 Node->getOperand(0)); 1266 ReplaceNode(Node, NewVal.getNode()); 1267 LegalizeOp(NewVal.getNode()); 1268 return; 1269 } 1270 break; 1271 1272 default: 1273 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 1274 Action = TargetLowering::Legal; 1275 } else { 1276 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 1277 } 1278 break; 1279 } 1280 1281 if (SimpleFinishLegalizing) { 1282 SDNode *NewNode = Node; 1283 switch (Node->getOpcode()) { 1284 default: break; 1285 case ISD::SHL: 1286 case ISD::SRL: 1287 case ISD::SRA: 1288 case ISD::ROTL: 1289 case ISD::ROTR: 1290 // Legalizing shifts/rotates requires adjusting the shift amount 1291 // to the appropriate width. 1292 if (!Node->getOperand(1).getValueType().isVector()) { 1293 SDValue SAO = 1294 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(), 1295 Node->getOperand(1)); 1296 HandleSDNode Handle(SAO); 1297 LegalizeOp(SAO.getNode()); 1298 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0), 1299 Handle.getValue()); 1300 } 1301 break; 1302 case ISD::SRL_PARTS: 1303 case ISD::SRA_PARTS: 1304 case ISD::SHL_PARTS: 1305 // Legalizing shifts/rotates requires adjusting the shift amount 1306 // to the appropriate width. 1307 if (!Node->getOperand(2).getValueType().isVector()) { 1308 SDValue SAO = 1309 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(), 1310 Node->getOperand(2)); 1311 HandleSDNode Handle(SAO); 1312 LegalizeOp(SAO.getNode()); 1313 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0), 1314 Node->getOperand(1), 1315 Handle.getValue()); 1316 } 1317 break; 1318 } 1319 1320 if (NewNode != Node) { 1321 DAG.ReplaceAllUsesWith(Node, NewNode); 1322 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1323 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i)); 1324 ReplacedNode(Node); 1325 Node = NewNode; 1326 } 1327 switch (Action) { 1328 case TargetLowering::Legal: 1329 return; 1330 case TargetLowering::Custom: { 1331 // FIXME: The handling for custom lowering with multiple results is 1332 // a complete mess. 1333 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG); 1334 if (Res.getNode()) { 1335 SmallVector<SDValue, 8> ResultVals; 1336 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 1337 if (e == 1) 1338 ResultVals.push_back(Res); 1339 else 1340 ResultVals.push_back(Res.getValue(i)); 1341 } 1342 if (Res.getNode() != Node || Res.getResNo() != 0) { 1343 DAG.ReplaceAllUsesWith(Node, ResultVals.data()); 1344 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1345 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]); 1346 ReplacedNode(Node); 1347 } 1348 return; 1349 } 1350 } 1351 // FALL THROUGH 1352 case TargetLowering::Expand: 1353 ExpandNode(Node); 1354 return; 1355 case TargetLowering::Promote: 1356 PromoteNode(Node); 1357 return; 1358 } 1359 } 1360 1361 switch (Node->getOpcode()) { 1362 default: 1363#ifndef NDEBUG 1364 dbgs() << "NODE: "; 1365 Node->dump( &DAG); 1366 dbgs() << "\n"; 1367#endif 1368 llvm_unreachable("Do not know how to legalize this operator!"); 1369 1370 case ISD::CALLSEQ_START: 1371 case ISD::CALLSEQ_END: 1372 break; 1373 case ISD::LOAD: { 1374 return LegalizeLoadOps(Node); 1375 } 1376 case ISD::STORE: { 1377 return LegalizeStoreOps(Node); 1378 } 1379 } 1380} 1381 1382SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1383 SDValue Vec = Op.getOperand(0); 1384 SDValue Idx = Op.getOperand(1); 1385 SDLoc dl(Op); 1386 // Store the value to a temporary stack slot, then LOAD the returned part. 1387 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1388 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 1389 MachinePointerInfo(), false, false, 0); 1390 1391 // Add the offset to the index. 1392 unsigned EltSize = 1393 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1394 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1395 DAG.getConstant(EltSize, Idx.getValueType())); 1396 1397 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1398 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1399 else 1400 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1401 1402 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1403 1404 if (Op.getValueType().isVector()) 1405 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(), 1406 false, false, false, 0); 1407 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1408 MachinePointerInfo(), 1409 Vec.getValueType().getVectorElementType(), 1410 false, false, 0); 1411} 1412 1413SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) { 1414 assert(Op.getValueType().isVector() && "Non-vector insert subvector!"); 1415 1416 SDValue Vec = Op.getOperand(0); 1417 SDValue Part = Op.getOperand(1); 1418 SDValue Idx = Op.getOperand(2); 1419 SDLoc dl(Op); 1420 1421 // Store the value to a temporary stack slot, then LOAD the returned part. 1422 1423 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1424 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 1425 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI); 1426 1427 // First store the whole vector. 1428 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo, 1429 false, false, 0); 1430 1431 // Then store the inserted part. 1432 1433 // Add the offset to the index. 1434 unsigned EltSize = 1435 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1436 1437 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1438 DAG.getConstant(EltSize, Idx.getValueType())); 1439 1440 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1441 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1442 else 1443 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1444 1445 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, 1446 StackPtr); 1447 1448 // Store the subvector. 1449 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr, 1450 MachinePointerInfo(), false, false, 0); 1451 1452 // Finally, load the updated vector. 1453 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo, 1454 false, false, false, 0); 1455} 1456 1457SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1458 // We can't handle this case efficiently. Allocate a sufficiently 1459 // aligned object on the stack, store each element into it, then load 1460 // the result as a vector. 1461 // Create the stack frame object. 1462 EVT VT = Node->getValueType(0); 1463 EVT EltVT = VT.getVectorElementType(); 1464 SDLoc dl(Node); 1465 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1466 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1467 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI); 1468 1469 // Emit a store of each element to the stack slot. 1470 SmallVector<SDValue, 8> Stores; 1471 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1472 // Store (in the right endianness) the elements to memory. 1473 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1474 // Ignore undef elements. 1475 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1476 1477 unsigned Offset = TypeByteSize*i; 1478 1479 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1480 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1481 1482 // If the destination vector element type is narrower than the source 1483 // element type, only store the bits necessary. 1484 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1485 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1486 Node->getOperand(i), Idx, 1487 PtrInfo.getWithOffset(Offset), 1488 EltVT, false, false, 0)); 1489 } else 1490 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1491 Node->getOperand(i), Idx, 1492 PtrInfo.getWithOffset(Offset), 1493 false, false, 0)); 1494 } 1495 1496 SDValue StoreChain; 1497 if (!Stores.empty()) // Not all undef elements? 1498 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1499 &Stores[0], Stores.size()); 1500 else 1501 StoreChain = DAG.getEntryNode(); 1502 1503 // Result is a load from the stack slot. 1504 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, 1505 false, false, false, 0); 1506} 1507 1508SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1509 SDLoc dl(Node); 1510 SDValue Tmp1 = Node->getOperand(0); 1511 SDValue Tmp2 = Node->getOperand(1); 1512 1513 // Get the sign bit of the RHS. First obtain a value that has the same 1514 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1515 SDValue SignBit; 1516 EVT FloatVT = Tmp2.getValueType(); 1517 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1518 if (TLI.isTypeLegal(IVT)) { 1519 // Convert to an integer with the same sign bit. 1520 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2); 1521 } else { 1522 // Store the float to memory, then load the sign part out as an integer. 1523 MVT LoadTy = TLI.getPointerTy(); 1524 // First create a temporary that is aligned for both the load and store. 1525 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1526 // Then store the float to it. 1527 SDValue Ch = 1528 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(), 1529 false, false, 0); 1530 if (TLI.isBigEndian()) { 1531 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1532 // Load out a legal integer with the same sign bit as the float. 1533 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(), 1534 false, false, false, 0); 1535 } else { // Little endian 1536 SDValue LoadPtr = StackPtr; 1537 // The float may be wider than the integer we are going to load. Advance 1538 // the pointer so that the loaded integer will contain the sign bit. 1539 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1540 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1541 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1542 LoadPtr, 1543 DAG.getConstant(ByteOffset, LoadPtr.getValueType())); 1544 // Load a legal integer containing the sign bit. 1545 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(), 1546 false, false, false, 0); 1547 // Move the sign bit to the top bit of the loaded integer. 1548 unsigned BitShift = LoadTy.getSizeInBits() - 1549 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1550 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1551 if (BitShift) 1552 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1553 DAG.getConstant(BitShift, 1554 TLI.getShiftAmountTy(SignBit.getValueType()))); 1555 } 1556 } 1557 // Now get the sign bit proper, by seeing whether the value is negative. 1558 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()), 1559 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1560 ISD::SETLT); 1561 // Get the absolute value of the result. 1562 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1563 // Select between the nabs and abs value based on the sign bit of 1564 // the input. 1565 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit, 1566 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1567 AbsVal); 1568} 1569 1570void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1571 SmallVectorImpl<SDValue> &Results) { 1572 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1573 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1574 " not tell us which reg is the stack pointer!"); 1575 SDLoc dl(Node); 1576 EVT VT = Node->getValueType(0); 1577 SDValue Tmp1 = SDValue(Node, 0); 1578 SDValue Tmp2 = SDValue(Node, 1); 1579 SDValue Tmp3 = Node->getOperand(2); 1580 SDValue Chain = Tmp1.getOperand(0); 1581 1582 // Chain the dynamic stack allocation so that it doesn't modify the stack 1583 // pointer when other instructions are using the stack. 1584 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true), 1585 SDLoc(Node)); 1586 1587 SDValue Size = Tmp2.getOperand(1); 1588 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1589 Chain = SP.getValue(1); 1590 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1591 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 1592 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1593 if (Align > StackAlign) 1594 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1, 1595 DAG.getConstant(-(uint64_t)Align, VT)); 1596 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1597 1598 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1599 DAG.getIntPtrConstant(0, true), SDValue(), 1600 SDLoc(Node)); 1601 1602 Results.push_back(Tmp1); 1603 Results.push_back(Tmp2); 1604} 1605 1606/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1607/// condition code CC on the current target. 1608/// If the SETCC has been legalized using AND / OR, then the legalized node 1609/// will be stored in LHS. RHS and CC will be set to SDValue(). 1610/// If the SETCC has been legalized by using getSetCCSwappedOperands(), 1611/// then the values of LHS and RHS will be swapped and CC will be set to the 1612/// new condition. 1613/// \returns true if the SetCC has been legalized, false if it hasn't. 1614bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1615 SDValue &LHS, SDValue &RHS, 1616 SDValue &CC, 1617 SDLoc dl) { 1618 MVT OpVT = LHS.getSimpleValueType(); 1619 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1620 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1621 default: llvm_unreachable("Unknown condition code action!"); 1622 case TargetLowering::Legal: 1623 // Nothing to do. 1624 break; 1625 case TargetLowering::Expand: { 1626 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode); 1627 if (TLI.isCondCodeLegal(InvCC, OpVT)) { 1628 std::swap(LHS, RHS); 1629 CC = DAG.getCondCode(InvCC); 1630 return true; 1631 } 1632 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1633 unsigned Opc = 0; 1634 switch (CCCode) { 1635 default: llvm_unreachable("Don't know how to expand this condition!"); 1636 case ISD::SETO: 1637 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT) 1638 == TargetLowering::Legal 1639 && "If SETO is expanded, SETOEQ must be legal!"); 1640 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break; 1641 case ISD::SETUO: 1642 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT) 1643 == TargetLowering::Legal 1644 && "If SETUO is expanded, SETUNE must be legal!"); 1645 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break; 1646 case ISD::SETOEQ: 1647 case ISD::SETOGT: 1648 case ISD::SETOGE: 1649 case ISD::SETOLT: 1650 case ISD::SETOLE: 1651 case ISD::SETONE: 1652 case ISD::SETUEQ: 1653 case ISD::SETUNE: 1654 case ISD::SETUGT: 1655 case ISD::SETUGE: 1656 case ISD::SETULT: 1657 case ISD::SETULE: 1658 // If we are floating point, assign and break, otherwise fall through. 1659 if (!OpVT.isInteger()) { 1660 // We can use the 4th bit to tell if we are the unordered 1661 // or ordered version of the opcode. 1662 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO; 1663 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND; 1664 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10); 1665 break; 1666 } 1667 // Fallthrough if we are unsigned integer. 1668 case ISD::SETLE: 1669 case ISD::SETGT: 1670 case ISD::SETGE: 1671 case ISD::SETLT: 1672 case ISD::SETNE: 1673 case ISD::SETEQ: 1674 // We only support using the inverted operation, which is computed above 1675 // and not a different manner of supporting expanding these cases. 1676 llvm_unreachable("Don't know how to expand this condition!"); 1677 } 1678 1679 SDValue SetCC1, SetCC2; 1680 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) { 1681 // If we aren't the ordered or unorder operation, 1682 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS). 1683 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1684 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1685 } else { 1686 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS) 1687 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1); 1688 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2); 1689 } 1690 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1691 RHS = SDValue(); 1692 CC = SDValue(); 1693 return true; 1694 } 1695 } 1696 return false; 1697} 1698 1699/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1700/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1701/// a load from the stack slot to DestVT, extending it if needed. 1702/// The resultant code need not be legal. 1703SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1704 EVT SlotVT, 1705 EVT DestVT, 1706 SDLoc dl) { 1707 // Create the stack frame object. 1708 unsigned SrcAlign = 1709 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType(). 1710 getTypeForEVT(*DAG.getContext())); 1711 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1712 1713 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1714 int SPFI = StackPtrFI->getIndex(); 1715 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI); 1716 1717 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1718 unsigned SlotSize = SlotVT.getSizeInBits(); 1719 unsigned DestSize = DestVT.getSizeInBits(); 1720 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); 1721 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType); 1722 1723 // Emit a store to the stack slot. Use a truncstore if the input value is 1724 // later than DestVT. 1725 SDValue Store; 1726 1727 if (SrcSize > SlotSize) 1728 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1729 PtrInfo, SlotVT, false, false, SrcAlign); 1730 else { 1731 assert(SrcSize == SlotSize && "Invalid store"); 1732 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1733 PtrInfo, false, false, SrcAlign); 1734 } 1735 1736 // Result is a load from the stack slot. 1737 if (SlotSize == DestSize) 1738 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, 1739 false, false, false, DestAlign); 1740 1741 assert(SlotSize < DestSize && "Unknown extension!"); 1742 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, 1743 PtrInfo, SlotVT, false, false, DestAlign); 1744} 1745 1746SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1747 SDLoc dl(Node); 1748 // Create a vector sized/aligned stack slot, store the value to element #0, 1749 // then load the whole vector back out. 1750 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1751 1752 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1753 int SPFI = StackPtrFI->getIndex(); 1754 1755 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1756 StackPtr, 1757 MachinePointerInfo::getFixedStack(SPFI), 1758 Node->getValueType(0).getVectorElementType(), 1759 false, false, 0); 1760 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1761 MachinePointerInfo::getFixedStack(SPFI), 1762 false, false, false, 0); 1763} 1764 1765 1766/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1767/// support the operation, but do support the resultant vector type. 1768SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1769 unsigned NumElems = Node->getNumOperands(); 1770 SDValue Value1, Value2; 1771 SDLoc dl(Node); 1772 EVT VT = Node->getValueType(0); 1773 EVT OpVT = Node->getOperand(0).getValueType(); 1774 EVT EltVT = VT.getVectorElementType(); 1775 1776 // If the only non-undef value is the low element, turn this into a 1777 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1778 bool isOnlyLowElement = true; 1779 bool MoreThanTwoValues = false; 1780 bool isConstant = true; 1781 for (unsigned i = 0; i < NumElems; ++i) { 1782 SDValue V = Node->getOperand(i); 1783 if (V.getOpcode() == ISD::UNDEF) 1784 continue; 1785 if (i > 0) 1786 isOnlyLowElement = false; 1787 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1788 isConstant = false; 1789 1790 if (!Value1.getNode()) { 1791 Value1 = V; 1792 } else if (!Value2.getNode()) { 1793 if (V != Value1) 1794 Value2 = V; 1795 } else if (V != Value1 && V != Value2) { 1796 MoreThanTwoValues = true; 1797 } 1798 } 1799 1800 if (!Value1.getNode()) 1801 return DAG.getUNDEF(VT); 1802 1803 if (isOnlyLowElement) 1804 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1805 1806 // If all elements are constants, create a load from the constant pool. 1807 if (isConstant) { 1808 SmallVector<Constant*, 16> CV; 1809 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1810 if (ConstantFPSDNode *V = 1811 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1812 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1813 } else if (ConstantSDNode *V = 1814 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1815 if (OpVT==EltVT) 1816 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1817 else { 1818 // If OpVT and EltVT don't match, EltVT is not legal and the 1819 // element values have been promoted/truncated earlier. Undo this; 1820 // we don't want a v16i8 to become a v16i32 for example. 1821 const ConstantInt *CI = V->getConstantIntValue(); 1822 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1823 CI->getZExtValue())); 1824 } 1825 } else { 1826 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1827 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1828 CV.push_back(UndefValue::get(OpNTy)); 1829 } 1830 } 1831 Constant *CP = ConstantVector::get(CV); 1832 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1833 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1834 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1835 MachinePointerInfo::getConstantPool(), 1836 false, false, false, Alignment); 1837 } 1838 1839 if (!MoreThanTwoValues) { 1840 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1841 for (unsigned i = 0; i < NumElems; ++i) { 1842 SDValue V = Node->getOperand(i); 1843 if (V.getOpcode() == ISD::UNDEF) 1844 continue; 1845 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1846 } 1847 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1848 // Get the splatted value into the low element of a vector register. 1849 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1850 SDValue Vec2; 1851 if (Value2.getNode()) 1852 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1853 else 1854 Vec2 = DAG.getUNDEF(VT); 1855 1856 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1857 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1858 } 1859 } 1860 1861 // Otherwise, we can't handle this case efficiently. 1862 return ExpandVectorBuildThroughStack(Node); 1863} 1864 1865// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1866// does not fit into a register, return the lo part and set the hi part to the 1867// by-reg argument. If it does fit into a single register, return the result 1868// and leave the Hi part unset. 1869SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1870 bool isSigned) { 1871 TargetLowering::ArgListTy Args; 1872 TargetLowering::ArgListEntry Entry; 1873 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1874 EVT ArgVT = Node->getOperand(i).getValueType(); 1875 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1876 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1877 Entry.isSExt = isSigned; 1878 Entry.isZExt = !isSigned; 1879 Args.push_back(Entry); 1880 } 1881 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1882 TLI.getPointerTy()); 1883 1884 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1885 1886 // By default, the input chain to this libcall is the entry node of the 1887 // function. If the libcall is going to be emitted as a tail call then 1888 // TLI.isUsedByReturnOnly will change it to the right chain if the return 1889 // node which is being folded has a non-entry input chain. 1890 SDValue InChain = DAG.getEntryNode(); 1891 1892 // isTailCall may be true since the callee does not reference caller stack 1893 // frame. Check if it's in the right position. 1894 SDValue TCChain = InChain; 1895 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain); 1896 if (isTailCall) 1897 InChain = TCChain; 1898 1899 TargetLowering:: 1900 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false, 1901 0, TLI.getLibcallCallingConv(LC), isTailCall, 1902 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 1903 Callee, Args, DAG, SDLoc(Node)); 1904 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); 1905 1906 1907 if (!CallInfo.second.getNode()) 1908 // It's a tailcall, return the chain (which is the DAG root). 1909 return DAG.getRoot(); 1910 1911 return CallInfo.first; 1912} 1913 1914/// ExpandLibCall - Generate a libcall taking the given operands as arguments 1915/// and returning a result of type RetVT. 1916SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, 1917 const SDValue *Ops, unsigned NumOps, 1918 bool isSigned, SDLoc dl) { 1919 TargetLowering::ArgListTy Args; 1920 Args.reserve(NumOps); 1921 1922 TargetLowering::ArgListEntry Entry; 1923 for (unsigned i = 0; i != NumOps; ++i) { 1924 Entry.Node = Ops[i]; 1925 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); 1926 Entry.isSExt = isSigned; 1927 Entry.isZExt = !isSigned; 1928 Args.push_back(Entry); 1929 } 1930 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1931 TLI.getPointerTy()); 1932 1933 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 1934 TargetLowering:: 1935 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, 1936 false, 0, TLI.getLibcallCallingConv(LC), 1937 /*isTailCall=*/false, 1938 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 1939 Callee, Args, DAG, dl); 1940 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI); 1941 1942 return CallInfo.first; 1943} 1944 1945// ExpandChainLibCall - Expand a node into a call to a libcall. Similar to 1946// ExpandLibCall except that the first operand is the in-chain. 1947std::pair<SDValue, SDValue> 1948SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC, 1949 SDNode *Node, 1950 bool isSigned) { 1951 SDValue InChain = Node->getOperand(0); 1952 1953 TargetLowering::ArgListTy Args; 1954 TargetLowering::ArgListEntry Entry; 1955 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) { 1956 EVT ArgVT = Node->getOperand(i).getValueType(); 1957 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1958 Entry.Node = Node->getOperand(i); 1959 Entry.Ty = ArgTy; 1960 Entry.isSExt = isSigned; 1961 Entry.isZExt = !isSigned; 1962 Args.push_back(Entry); 1963 } 1964 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1965 TLI.getPointerTy()); 1966 1967 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1968 TargetLowering:: 1969 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false, 1970 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false, 1971 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 1972 Callee, Args, DAG, SDLoc(Node)); 1973 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); 1974 1975 return CallInfo; 1976} 1977 1978SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 1979 RTLIB::Libcall Call_F32, 1980 RTLIB::Libcall Call_F64, 1981 RTLIB::Libcall Call_F80, 1982 RTLIB::Libcall Call_F128, 1983 RTLIB::Libcall Call_PPCF128) { 1984 RTLIB::Libcall LC; 1985 switch (Node->getSimpleValueType(0).SimpleTy) { 1986 default: llvm_unreachable("Unexpected request for libcall!"); 1987 case MVT::f32: LC = Call_F32; break; 1988 case MVT::f64: LC = Call_F64; break; 1989 case MVT::f80: LC = Call_F80; break; 1990 case MVT::f128: LC = Call_F128; break; 1991 case MVT::ppcf128: LC = Call_PPCF128; break; 1992 } 1993 return ExpandLibCall(LC, Node, false); 1994} 1995 1996SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 1997 RTLIB::Libcall Call_I8, 1998 RTLIB::Libcall Call_I16, 1999 RTLIB::Libcall Call_I32, 2000 RTLIB::Libcall Call_I64, 2001 RTLIB::Libcall Call_I128) { 2002 RTLIB::Libcall LC; 2003 switch (Node->getSimpleValueType(0).SimpleTy) { 2004 default: llvm_unreachable("Unexpected request for libcall!"); 2005 case MVT::i8: LC = Call_I8; break; 2006 case MVT::i16: LC = Call_I16; break; 2007 case MVT::i32: LC = Call_I32; break; 2008 case MVT::i64: LC = Call_I64; break; 2009 case MVT::i128: LC = Call_I128; break; 2010 } 2011 return ExpandLibCall(LC, Node, isSigned); 2012} 2013 2014/// isDivRemLibcallAvailable - Return true if divmod libcall is available. 2015static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned, 2016 const TargetLowering &TLI) { 2017 RTLIB::Libcall LC; 2018 switch (Node->getSimpleValueType(0).SimpleTy) { 2019 default: llvm_unreachable("Unexpected request for libcall!"); 2020 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; 2021 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; 2022 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; 2023 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; 2024 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break; 2025 } 2026 2027 return TLI.getLibcallName(LC) != 0; 2028} 2029 2030/// useDivRem - Only issue divrem libcall if both quotient and remainder are 2031/// needed. 2032static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) { 2033 // The other use might have been replaced with a divrem already. 2034 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2035 unsigned OtherOpcode = 0; 2036 if (isSigned) 2037 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV; 2038 else 2039 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV; 2040 2041 SDValue Op0 = Node->getOperand(0); 2042 SDValue Op1 = Node->getOperand(1); 2043 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(), 2044 UE = Op0.getNode()->use_end(); UI != UE; ++UI) { 2045 SDNode *User = *UI; 2046 if (User == Node) 2047 continue; 2048 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) && 2049 User->getOperand(0) == Op0 && 2050 User->getOperand(1) == Op1) 2051 return true; 2052 } 2053 return false; 2054} 2055 2056/// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem 2057/// pairs. 2058void 2059SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node, 2060 SmallVectorImpl<SDValue> &Results) { 2061 unsigned Opcode = Node->getOpcode(); 2062 bool isSigned = Opcode == ISD::SDIVREM; 2063 2064 RTLIB::Libcall LC; 2065 switch (Node->getSimpleValueType(0).SimpleTy) { 2066 default: llvm_unreachable("Unexpected request for libcall!"); 2067 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; 2068 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; 2069 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; 2070 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; 2071 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break; 2072 } 2073 2074 // The input chain to this libcall is the entry node of the function. 2075 // Legalizing the call will automatically add the previous call to the 2076 // dependence. 2077 SDValue InChain = DAG.getEntryNode(); 2078 2079 EVT RetVT = Node->getValueType(0); 2080 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 2081 2082 TargetLowering::ArgListTy Args; 2083 TargetLowering::ArgListEntry Entry; 2084 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2085 EVT ArgVT = Node->getOperand(i).getValueType(); 2086 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 2087 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 2088 Entry.isSExt = isSigned; 2089 Entry.isZExt = !isSigned; 2090 Args.push_back(Entry); 2091 } 2092 2093 // Also pass the return address of the remainder. 2094 SDValue FIPtr = DAG.CreateStackTemporary(RetVT); 2095 Entry.Node = FIPtr; 2096 Entry.Ty = RetTy->getPointerTo(); 2097 Entry.isSExt = isSigned; 2098 Entry.isZExt = !isSigned; 2099 Args.push_back(Entry); 2100 2101 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 2102 TLI.getPointerTy()); 2103 2104 SDLoc dl(Node); 2105 TargetLowering:: 2106 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false, 2107 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false, 2108 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 2109 Callee, Args, DAG, dl); 2110 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); 2111 2112 // Remainder is loaded back from the stack frame. 2113 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr, 2114 MachinePointerInfo(), false, false, false, 0); 2115 Results.push_back(CallInfo.first); 2116 Results.push_back(Rem); 2117} 2118 2119/// isSinCosLibcallAvailable - Return true if sincos libcall is available. 2120static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) { 2121 RTLIB::Libcall LC; 2122 switch (Node->getSimpleValueType(0).SimpleTy) { 2123 default: llvm_unreachable("Unexpected request for libcall!"); 2124 case MVT::f32: LC = RTLIB::SINCOS_F32; break; 2125 case MVT::f64: LC = RTLIB::SINCOS_F64; break; 2126 case MVT::f80: LC = RTLIB::SINCOS_F80; break; 2127 case MVT::f128: LC = RTLIB::SINCOS_F128; break; 2128 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break; 2129 } 2130 return TLI.getLibcallName(LC) != 0; 2131} 2132 2133/// canCombineSinCosLibcall - Return true if sincos libcall is available and 2134/// can be used to combine sin and cos. 2135static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI, 2136 const TargetMachine &TM) { 2137 if (!isSinCosLibcallAvailable(Node, TLI)) 2138 return false; 2139 // GNU sin/cos functions set errno while sincos does not. Therefore 2140 // combining sin and cos is only safe if unsafe-fpmath is enabled. 2141 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU; 2142 if (isGNU && !TM.Options.UnsafeFPMath) 2143 return false; 2144 return true; 2145} 2146 2147/// useSinCos - Only issue sincos libcall if both sin and cos are 2148/// needed. 2149static bool useSinCos(SDNode *Node) { 2150 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN 2151 ? ISD::FCOS : ISD::FSIN; 2152 2153 SDValue Op0 = Node->getOperand(0); 2154 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(), 2155 UE = Op0.getNode()->use_end(); UI != UE; ++UI) { 2156 SDNode *User = *UI; 2157 if (User == Node) 2158 continue; 2159 // The other user might have been turned into sincos already. 2160 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS) 2161 return true; 2162 } 2163 return false; 2164} 2165 2166/// ExpandSinCosLibCall - Issue libcalls to sincos to compute sin / cos 2167/// pairs. 2168void 2169SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node, 2170 SmallVectorImpl<SDValue> &Results) { 2171 RTLIB::Libcall LC; 2172 switch (Node->getSimpleValueType(0).SimpleTy) { 2173 default: llvm_unreachable("Unexpected request for libcall!"); 2174 case MVT::f32: LC = RTLIB::SINCOS_F32; break; 2175 case MVT::f64: LC = RTLIB::SINCOS_F64; break; 2176 case MVT::f80: LC = RTLIB::SINCOS_F80; break; 2177 case MVT::f128: LC = RTLIB::SINCOS_F128; break; 2178 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break; 2179 } 2180 2181 // The input chain to this libcall is the entry node of the function. 2182 // Legalizing the call will automatically add the previous call to the 2183 // dependence. 2184 SDValue InChain = DAG.getEntryNode(); 2185 2186 EVT RetVT = Node->getValueType(0); 2187 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 2188 2189 TargetLowering::ArgListTy Args; 2190 TargetLowering::ArgListEntry Entry; 2191 2192 // Pass the argument. 2193 Entry.Node = Node->getOperand(0); 2194 Entry.Ty = RetTy; 2195 Entry.isSExt = false; 2196 Entry.isZExt = false; 2197 Args.push_back(Entry); 2198 2199 // Pass the return address of sin. 2200 SDValue SinPtr = DAG.CreateStackTemporary(RetVT); 2201 Entry.Node = SinPtr; 2202 Entry.Ty = RetTy->getPointerTo(); 2203 Entry.isSExt = false; 2204 Entry.isZExt = false; 2205 Args.push_back(Entry); 2206 2207 // Also pass the return address of the cos. 2208 SDValue CosPtr = DAG.CreateStackTemporary(RetVT); 2209 Entry.Node = CosPtr; 2210 Entry.Ty = RetTy->getPointerTo(); 2211 Entry.isSExt = false; 2212 Entry.isZExt = false; 2213 Args.push_back(Entry); 2214 2215 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 2216 TLI.getPointerTy()); 2217 2218 SDLoc dl(Node); 2219 TargetLowering:: 2220 CallLoweringInfo CLI(InChain, Type::getVoidTy(*DAG.getContext()), 2221 false, false, false, false, 2222 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false, 2223 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 2224 Callee, Args, DAG, dl); 2225 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); 2226 2227 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr, 2228 MachinePointerInfo(), false, false, false, 0)); 2229 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr, 2230 MachinePointerInfo(), false, false, false, 0)); 2231} 2232 2233/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 2234/// INT_TO_FP operation of the specified operand when the target requests that 2235/// we expand it. At this point, we know that the result and operand types are 2236/// legal for the target. 2237SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 2238 SDValue Op0, 2239 EVT DestVT, 2240 SDLoc dl) { 2241 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) { 2242 // simple 32-bit [signed|unsigned] integer to float/double expansion 2243 2244 // Get the stack frame index of a 8 byte buffer. 2245 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 2246 2247 // word offset constant for Hi/Lo address computation 2248 SDValue WordOff = DAG.getConstant(sizeof(int), StackSlot.getValueType()); 2249 // set up Hi and Lo (into buffer) address based on endian 2250 SDValue Hi = StackSlot; 2251 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(), 2252 StackSlot, WordOff); 2253 if (TLI.isLittleEndian()) 2254 std::swap(Hi, Lo); 2255 2256 // if signed map to unsigned space 2257 SDValue Op0Mapped; 2258 if (isSigned) { 2259 // constant used to invert sign bit (signed to unsigned mapping) 2260 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 2261 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 2262 } else { 2263 Op0Mapped = Op0; 2264 } 2265 // store the lo of the constructed double - based on integer input 2266 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 2267 Op0Mapped, Lo, MachinePointerInfo(), 2268 false, false, 0); 2269 // initial hi portion of constructed double 2270 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 2271 // store the hi of the constructed double - biased exponent 2272 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi, 2273 MachinePointerInfo(), 2274 false, false, 0); 2275 // load the constructed double 2276 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, 2277 MachinePointerInfo(), false, false, false, 0); 2278 // FP constant to bias correct the final result 2279 SDValue Bias = DAG.getConstantFP(isSigned ? 2280 BitsToDouble(0x4330000080000000ULL) : 2281 BitsToDouble(0x4330000000000000ULL), 2282 MVT::f64); 2283 // subtract the bias 2284 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2285 // final result 2286 SDValue Result; 2287 // handle final rounding 2288 if (DestVT == MVT::f64) { 2289 // do nothing 2290 Result = Sub; 2291 } else if (DestVT.bitsLT(MVT::f64)) { 2292 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2293 DAG.getIntPtrConstant(0)); 2294 } else if (DestVT.bitsGT(MVT::f64)) { 2295 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2296 } 2297 return Result; 2298 } 2299 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2300 // Code below here assumes !isSigned without checking again. 2301 2302 // Implementation of unsigned i64 to f64 following the algorithm in 2303 // __floatundidf in compiler_rt. This implementation has the advantage 2304 // of performing rounding correctly, both in the default rounding mode 2305 // and in all alternate rounding modes. 2306 // TODO: Generalize this for use with other types. 2307 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2308 SDValue TwoP52 = 2309 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2310 SDValue TwoP84PlusTwoP52 = 2311 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2312 SDValue TwoP84 = 2313 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2314 2315 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2316 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2317 DAG.getConstant(32, MVT::i64)); 2318 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2319 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2320 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr); 2321 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr); 2322 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, 2323 TwoP84PlusTwoP52); 2324 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2325 } 2326 2327 // Implementation of unsigned i64 to f32. 2328 // TODO: Generalize this for use with other types. 2329 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) { 2330 // For unsigned conversions, convert them to signed conversions using the 2331 // algorithm from the x86_64 __floatundidf in compiler_rt. 2332 if (!isSigned) { 2333 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0); 2334 2335 SDValue ShiftConst = 2336 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType())); 2337 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst); 2338 SDValue AndConst = DAG.getConstant(1, MVT::i64); 2339 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst); 2340 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr); 2341 2342 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or); 2343 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt); 2344 2345 // TODO: This really should be implemented using a branch rather than a 2346 // select. We happen to get lucky and machinesink does the right 2347 // thing most of the time. This would be a good candidate for a 2348 //pseudo-op, or, even better, for whole-function isel. 2349 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 2350 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT); 2351 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast); 2352 } 2353 2354 // Otherwise, implement the fully general conversion. 2355 2356 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2357 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64)); 2358 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, 2359 DAG.getConstant(UINT64_C(0x800), MVT::i64)); 2360 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2361 DAG.getConstant(UINT64_C(0x7ff), MVT::i64)); 2362 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 2363 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); 2364 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0); 2365 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 2366 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64), 2367 ISD::SETUGE); 2368 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0); 2369 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType()); 2370 2371 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, 2372 DAG.getConstant(32, SHVT)); 2373 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh); 2374 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); 2375 SDValue TwoP32 = 2376 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64); 2377 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); 2378 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2); 2379 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo); 2380 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); 2381 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, 2382 DAG.getIntPtrConstant(0)); 2383 } 2384 2385 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2386 2387 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()), 2388 Op0, DAG.getConstant(0, Op0.getValueType()), 2389 ISD::SETLT); 2390 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2391 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(), 2392 SignSet, Four, Zero); 2393 2394 // If the sign bit of the integer is set, the large number will be treated 2395 // as a negative number. To counteract this, the dynamic code adds an 2396 // offset depending on the data type. 2397 uint64_t FF; 2398 switch (Op0.getSimpleValueType().SimpleTy) { 2399 default: llvm_unreachable("Unsupported integer type!"); 2400 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2401 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2402 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2403 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2404 } 2405 if (TLI.isLittleEndian()) FF <<= 32; 2406 Constant *FudgeFactor = ConstantInt::get( 2407 Type::getInt64Ty(*DAG.getContext()), FF); 2408 2409 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2410 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2411 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset); 2412 Alignment = std::min(Alignment, 4u); 2413 SDValue FudgeInReg; 2414 if (DestVT == MVT::f32) 2415 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2416 MachinePointerInfo::getConstantPool(), 2417 false, false, false, Alignment); 2418 else { 2419 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2420 DAG.getEntryNode(), CPIdx, 2421 MachinePointerInfo::getConstantPool(), 2422 MVT::f32, false, false, Alignment); 2423 HandleSDNode Handle(Load); 2424 LegalizeOp(Load.getNode()); 2425 FudgeInReg = Handle.getValue(); 2426 } 2427 2428 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2429} 2430 2431/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2432/// *INT_TO_FP operation of the specified operand when the target requests that 2433/// we promote it. At this point, we know that the result and operand types are 2434/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2435/// operation that takes a larger input. 2436SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2437 EVT DestVT, 2438 bool isSigned, 2439 SDLoc dl) { 2440 // First step, figure out the appropriate *INT_TO_FP operation to use. 2441 EVT NewInTy = LegalOp.getValueType(); 2442 2443 unsigned OpToUse = 0; 2444 2445 // Scan for the appropriate larger type to use. 2446 while (1) { 2447 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2448 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2449 2450 // If the target supports SINT_TO_FP of this type, use it. 2451 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2452 OpToUse = ISD::SINT_TO_FP; 2453 break; 2454 } 2455 if (isSigned) continue; 2456 2457 // If the target supports UINT_TO_FP of this type, use it. 2458 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2459 OpToUse = ISD::UINT_TO_FP; 2460 break; 2461 } 2462 2463 // Otherwise, try a larger type. 2464 } 2465 2466 // Okay, we found the operation and type to use. Zero extend our input to the 2467 // desired type then run the operation on it. 2468 return DAG.getNode(OpToUse, dl, DestVT, 2469 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2470 dl, NewInTy, LegalOp)); 2471} 2472 2473/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2474/// FP_TO_*INT operation of the specified operand when the target requests that 2475/// we promote it. At this point, we know that the result and operand types are 2476/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2477/// operation that returns a larger result. 2478SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2479 EVT DestVT, 2480 bool isSigned, 2481 SDLoc dl) { 2482 // First step, figure out the appropriate FP_TO*INT operation to use. 2483 EVT NewOutTy = DestVT; 2484 2485 unsigned OpToUse = 0; 2486 2487 // Scan for the appropriate larger type to use. 2488 while (1) { 2489 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2490 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2491 2492 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2493 OpToUse = ISD::FP_TO_SINT; 2494 break; 2495 } 2496 2497 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2498 OpToUse = ISD::FP_TO_UINT; 2499 break; 2500 } 2501 2502 // Otherwise, try a larger type. 2503 } 2504 2505 2506 // Okay, we found the operation and type to use. 2507 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2508 2509 // Truncate the result of the extended FP_TO_*INT operation to the desired 2510 // size. 2511 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2512} 2513 2514/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2515/// 2516SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) { 2517 EVT VT = Op.getValueType(); 2518 EVT SHVT = TLI.getShiftAmountTy(VT); 2519 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2520 switch (VT.getSimpleVT().SimpleTy) { 2521 default: llvm_unreachable("Unhandled Expand type in BSWAP!"); 2522 case MVT::i16: 2523 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2524 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2525 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2526 case MVT::i32: 2527 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2528 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2529 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2530 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2531 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2532 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2533 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2534 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2535 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2536 case MVT::i64: 2537 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2538 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2539 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2540 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2541 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2542 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2543 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2544 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2545 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2546 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2547 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2548 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2549 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2550 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2551 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2552 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2553 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2554 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2555 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2556 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2557 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2558 } 2559} 2560 2561/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2562/// 2563SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2564 SDLoc dl) { 2565 switch (Opc) { 2566 default: llvm_unreachable("Cannot expand this yet!"); 2567 case ISD::CTPOP: { 2568 EVT VT = Op.getValueType(); 2569 EVT ShVT = TLI.getShiftAmountTy(VT); 2570 unsigned Len = VT.getSizeInBits(); 2571 2572 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 && 2573 "CTPOP not implemented for this type."); 2574 2575 // This is the "best" algorithm from 2576 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel 2577 2578 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), VT); 2579 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), VT); 2580 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), VT); 2581 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), VT); 2582 2583 // v = v - ((v >> 1) & 0x55555555...) 2584 Op = DAG.getNode(ISD::SUB, dl, VT, Op, 2585 DAG.getNode(ISD::AND, dl, VT, 2586 DAG.getNode(ISD::SRL, dl, VT, Op, 2587 DAG.getConstant(1, ShVT)), 2588 Mask55)); 2589 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...) 2590 Op = DAG.getNode(ISD::ADD, dl, VT, 2591 DAG.getNode(ISD::AND, dl, VT, Op, Mask33), 2592 DAG.getNode(ISD::AND, dl, VT, 2593 DAG.getNode(ISD::SRL, dl, VT, Op, 2594 DAG.getConstant(2, ShVT)), 2595 Mask33)); 2596 // v = (v + (v >> 4)) & 0x0F0F0F0F... 2597 Op = DAG.getNode(ISD::AND, dl, VT, 2598 DAG.getNode(ISD::ADD, dl, VT, Op, 2599 DAG.getNode(ISD::SRL, dl, VT, Op, 2600 DAG.getConstant(4, ShVT))), 2601 Mask0F); 2602 // v = (v * 0x01010101...) >> (Len - 8) 2603 Op = DAG.getNode(ISD::SRL, dl, VT, 2604 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01), 2605 DAG.getConstant(Len - 8, ShVT)); 2606 2607 return Op; 2608 } 2609 case ISD::CTLZ_ZERO_UNDEF: 2610 // This trivially expands to CTLZ. 2611 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op); 2612 case ISD::CTLZ: { 2613 // for now, we do this: 2614 // x = x | (x >> 1); 2615 // x = x | (x >> 2); 2616 // ... 2617 // x = x | (x >>16); 2618 // x = x | (x >>32); // for 64-bit input 2619 // return popcount(~x); 2620 // 2621 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2622 EVT VT = Op.getValueType(); 2623 EVT ShVT = TLI.getShiftAmountTy(VT); 2624 unsigned len = VT.getSizeInBits(); 2625 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2626 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2627 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2628 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2629 } 2630 Op = DAG.getNOT(dl, Op, VT); 2631 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2632 } 2633 case ISD::CTTZ_ZERO_UNDEF: 2634 // This trivially expands to CTTZ. 2635 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op); 2636 case ISD::CTTZ: { 2637 // for now, we use: { return popcount(~x & (x - 1)); } 2638 // unless the target has ctlz but not ctpop, in which case we use: 2639 // { return 32 - nlz(~x & (x-1)); } 2640 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2641 EVT VT = Op.getValueType(); 2642 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2643 DAG.getNOT(dl, Op, VT), 2644 DAG.getNode(ISD::SUB, dl, VT, Op, 2645 DAG.getConstant(1, VT))); 2646 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2647 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2648 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2649 return DAG.getNode(ISD::SUB, dl, VT, 2650 DAG.getConstant(VT.getSizeInBits(), VT), 2651 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2652 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2653 } 2654 } 2655} 2656 2657std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) { 2658 unsigned Opc = Node->getOpcode(); 2659 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 2660 RTLIB::Libcall LC; 2661 2662 switch (Opc) { 2663 default: 2664 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 2665 case ISD::ATOMIC_SWAP: 2666 switch (VT.SimpleTy) { 2667 default: llvm_unreachable("Unexpected value type for atomic!"); 2668 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; 2669 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 2670 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; 2671 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; 2672 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break; 2673 } 2674 break; 2675 case ISD::ATOMIC_CMP_SWAP: 2676 switch (VT.SimpleTy) { 2677 default: llvm_unreachable("Unexpected value type for atomic!"); 2678 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 2679 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 2680 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 2681 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 2682 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break; 2683 } 2684 break; 2685 case ISD::ATOMIC_LOAD_ADD: 2686 switch (VT.SimpleTy) { 2687 default: llvm_unreachable("Unexpected value type for atomic!"); 2688 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 2689 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 2690 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 2691 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 2692 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break; 2693 } 2694 break; 2695 case ISD::ATOMIC_LOAD_SUB: 2696 switch (VT.SimpleTy) { 2697 default: llvm_unreachable("Unexpected value type for atomic!"); 2698 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 2699 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 2700 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 2701 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 2702 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break; 2703 } 2704 break; 2705 case ISD::ATOMIC_LOAD_AND: 2706 switch (VT.SimpleTy) { 2707 default: llvm_unreachable("Unexpected value type for atomic!"); 2708 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 2709 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 2710 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 2711 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 2712 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break; 2713 } 2714 break; 2715 case ISD::ATOMIC_LOAD_OR: 2716 switch (VT.SimpleTy) { 2717 default: llvm_unreachable("Unexpected value type for atomic!"); 2718 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 2719 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 2720 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 2721 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 2722 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break; 2723 } 2724 break; 2725 case ISD::ATOMIC_LOAD_XOR: 2726 switch (VT.SimpleTy) { 2727 default: llvm_unreachable("Unexpected value type for atomic!"); 2728 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 2729 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 2730 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 2731 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 2732 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break; 2733 } 2734 break; 2735 case ISD::ATOMIC_LOAD_NAND: 2736 switch (VT.SimpleTy) { 2737 default: llvm_unreachable("Unexpected value type for atomic!"); 2738 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 2739 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 2740 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 2741 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 2742 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break; 2743 } 2744 break; 2745 case ISD::ATOMIC_LOAD_MAX: 2746 switch (VT.SimpleTy) { 2747 default: llvm_unreachable("Unexpected value type for atomic!"); 2748 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MAX_1; break; 2749 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MAX_2; break; 2750 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MAX_4; break; 2751 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MAX_8; break; 2752 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MAX_16;break; 2753 } 2754 break; 2755 case ISD::ATOMIC_LOAD_UMAX: 2756 switch (VT.SimpleTy) { 2757 default: llvm_unreachable("Unexpected value type for atomic!"); 2758 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMAX_1; break; 2759 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMAX_2; break; 2760 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMAX_4; break; 2761 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMAX_8; break; 2762 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMAX_16;break; 2763 } 2764 break; 2765 case ISD::ATOMIC_LOAD_MIN: 2766 switch (VT.SimpleTy) { 2767 default: llvm_unreachable("Unexpected value type for atomic!"); 2768 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MIN_1; break; 2769 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MIN_2; break; 2770 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MIN_4; break; 2771 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MIN_8; break; 2772 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MIN_16;break; 2773 } 2774 break; 2775 case ISD::ATOMIC_LOAD_UMIN: 2776 switch (VT.SimpleTy) { 2777 default: llvm_unreachable("Unexpected value type for atomic!"); 2778 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMIN_1; break; 2779 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMIN_2; break; 2780 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMIN_4; break; 2781 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMIN_8; break; 2782 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMIN_16;break; 2783 } 2784 break; 2785 } 2786 2787 return ExpandChainLibCall(LC, Node, false); 2788} 2789 2790void SelectionDAGLegalize::ExpandNode(SDNode *Node) { 2791 SmallVector<SDValue, 8> Results; 2792 SDLoc dl(Node); 2793 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2794 switch (Node->getOpcode()) { 2795 case ISD::CTPOP: 2796 case ISD::CTLZ: 2797 case ISD::CTLZ_ZERO_UNDEF: 2798 case ISD::CTTZ: 2799 case ISD::CTTZ_ZERO_UNDEF: 2800 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2801 Results.push_back(Tmp1); 2802 break; 2803 case ISD::BSWAP: 2804 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2805 break; 2806 case ISD::FRAMEADDR: 2807 case ISD::RETURNADDR: 2808 case ISD::FRAME_TO_ARGS_OFFSET: 2809 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2810 break; 2811 case ISD::FLT_ROUNDS_: 2812 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2813 break; 2814 case ISD::EH_RETURN: 2815 case ISD::EH_LABEL: 2816 case ISD::PREFETCH: 2817 case ISD::VAEND: 2818 case ISD::EH_SJLJ_LONGJMP: 2819 // If the target didn't expand these, there's nothing to do, so just 2820 // preserve the chain and be done. 2821 Results.push_back(Node->getOperand(0)); 2822 break; 2823 case ISD::EH_SJLJ_SETJMP: 2824 // If the target didn't expand this, just return 'zero' and preserve the 2825 // chain. 2826 Results.push_back(DAG.getConstant(0, MVT::i32)); 2827 Results.push_back(Node->getOperand(0)); 2828 break; 2829 case ISD::ATOMIC_FENCE: { 2830 // If the target didn't lower this, lower it to '__sync_synchronize()' call 2831 // FIXME: handle "fence singlethread" more efficiently. 2832 TargetLowering::ArgListTy Args; 2833 TargetLowering:: 2834 CallLoweringInfo CLI(Node->getOperand(0), 2835 Type::getVoidTy(*DAG.getContext()), 2836 false, false, false, false, 0, CallingConv::C, 2837 /*isTailCall=*/false, 2838 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 2839 DAG.getExternalSymbol("__sync_synchronize", 2840 TLI.getPointerTy()), 2841 Args, DAG, dl); 2842 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI); 2843 2844 Results.push_back(CallResult.second); 2845 break; 2846 } 2847 case ISD::ATOMIC_LOAD: { 2848 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP. 2849 SDValue Zero = DAG.getConstant(0, Node->getValueType(0)); 2850 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 2851 cast<AtomicSDNode>(Node)->getMemoryVT(), 2852 Node->getOperand(0), 2853 Node->getOperand(1), Zero, Zero, 2854 cast<AtomicSDNode>(Node)->getMemOperand(), 2855 cast<AtomicSDNode>(Node)->getOrdering(), 2856 cast<AtomicSDNode>(Node)->getSynchScope()); 2857 Results.push_back(Swap.getValue(0)); 2858 Results.push_back(Swap.getValue(1)); 2859 break; 2860 } 2861 case ISD::ATOMIC_STORE: { 2862 // There is no libcall for atomic store; fake it with ATOMIC_SWAP. 2863 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 2864 cast<AtomicSDNode>(Node)->getMemoryVT(), 2865 Node->getOperand(0), 2866 Node->getOperand(1), Node->getOperand(2), 2867 cast<AtomicSDNode>(Node)->getMemOperand(), 2868 cast<AtomicSDNode>(Node)->getOrdering(), 2869 cast<AtomicSDNode>(Node)->getSynchScope()); 2870 Results.push_back(Swap.getValue(1)); 2871 break; 2872 } 2873 // By default, atomic intrinsics are marked Legal and lowered. Targets 2874 // which don't support them directly, however, may want libcalls, in which 2875 // case they mark them Expand, and we get here. 2876 case ISD::ATOMIC_SWAP: 2877 case ISD::ATOMIC_LOAD_ADD: 2878 case ISD::ATOMIC_LOAD_SUB: 2879 case ISD::ATOMIC_LOAD_AND: 2880 case ISD::ATOMIC_LOAD_OR: 2881 case ISD::ATOMIC_LOAD_XOR: 2882 case ISD::ATOMIC_LOAD_NAND: 2883 case ISD::ATOMIC_LOAD_MIN: 2884 case ISD::ATOMIC_LOAD_MAX: 2885 case ISD::ATOMIC_LOAD_UMIN: 2886 case ISD::ATOMIC_LOAD_UMAX: 2887 case ISD::ATOMIC_CMP_SWAP: { 2888 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node); 2889 Results.push_back(Tmp.first); 2890 Results.push_back(Tmp.second); 2891 break; 2892 } 2893 case ISD::DYNAMIC_STACKALLOC: 2894 ExpandDYNAMIC_STACKALLOC(Node, Results); 2895 break; 2896 case ISD::MERGE_VALUES: 2897 for (unsigned i = 0; i < Node->getNumValues(); i++) 2898 Results.push_back(Node->getOperand(i)); 2899 break; 2900 case ISD::UNDEF: { 2901 EVT VT = Node->getValueType(0); 2902 if (VT.isInteger()) 2903 Results.push_back(DAG.getConstant(0, VT)); 2904 else { 2905 assert(VT.isFloatingPoint() && "Unknown value type!"); 2906 Results.push_back(DAG.getConstantFP(0, VT)); 2907 } 2908 break; 2909 } 2910 case ISD::TRAP: { 2911 // If this operation is not supported, lower it to 'abort()' call 2912 TargetLowering::ArgListTy Args; 2913 TargetLowering:: 2914 CallLoweringInfo CLI(Node->getOperand(0), 2915 Type::getVoidTy(*DAG.getContext()), 2916 false, false, false, false, 0, CallingConv::C, 2917 /*isTailCall=*/false, 2918 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 2919 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2920 Args, DAG, dl); 2921 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI); 2922 2923 Results.push_back(CallResult.second); 2924 break; 2925 } 2926 case ISD::FP_ROUND: 2927 case ISD::BITCAST: 2928 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2929 Node->getValueType(0), dl); 2930 Results.push_back(Tmp1); 2931 break; 2932 case ISD::FP_EXTEND: 2933 Tmp1 = EmitStackConvert(Node->getOperand(0), 2934 Node->getOperand(0).getValueType(), 2935 Node->getValueType(0), dl); 2936 Results.push_back(Tmp1); 2937 break; 2938 case ISD::SIGN_EXTEND_INREG: { 2939 // NOTE: we could fall back on load/store here too for targets without 2940 // SAR. However, it is doubtful that any exist. 2941 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2942 EVT VT = Node->getValueType(0); 2943 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT); 2944 if (VT.isVector()) 2945 ShiftAmountTy = VT; 2946 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2947 ExtraVT.getScalarType().getSizeInBits(); 2948 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2949 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2950 Node->getOperand(0), ShiftCst); 2951 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2952 Results.push_back(Tmp1); 2953 break; 2954 } 2955 case ISD::FP_ROUND_INREG: { 2956 // The only way we can lower this is to turn it into a TRUNCSTORE, 2957 // EXTLOAD pair, targeting a temporary location (a stack slot). 2958 2959 // NOTE: there is a choice here between constantly creating new stack 2960 // slots and always reusing the same one. We currently always create 2961 // new ones, as reuse may inhibit scheduling. 2962 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2963 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2964 Node->getValueType(0), dl); 2965 Results.push_back(Tmp1); 2966 break; 2967 } 2968 case ISD::SINT_TO_FP: 2969 case ISD::UINT_TO_FP: 2970 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2971 Node->getOperand(0), Node->getValueType(0), dl); 2972 Results.push_back(Tmp1); 2973 break; 2974 case ISD::FP_TO_UINT: { 2975 SDValue True, False; 2976 EVT VT = Node->getOperand(0).getValueType(); 2977 EVT NVT = Node->getValueType(0); 2978 APFloat apf(DAG.EVTToAPFloatSemantics(VT), 2979 APInt::getNullValue(VT.getSizeInBits())); 2980 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2981 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2982 Tmp1 = DAG.getConstantFP(apf, VT); 2983 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT), 2984 Node->getOperand(0), 2985 Tmp1, ISD::SETLT); 2986 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2987 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2988 DAG.getNode(ISD::FSUB, dl, VT, 2989 Node->getOperand(0), Tmp1)); 2990 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2991 DAG.getConstant(x, NVT)); 2992 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False); 2993 Results.push_back(Tmp1); 2994 break; 2995 } 2996 case ISD::VAARG: { 2997 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2998 EVT VT = Node->getValueType(0); 2999 Tmp1 = Node->getOperand(0); 3000 Tmp2 = Node->getOperand(1); 3001 unsigned Align = Node->getConstantOperandVal(3); 3002 3003 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, 3004 MachinePointerInfo(V), 3005 false, false, false, 0); 3006 SDValue VAList = VAListLoad; 3007 3008 if (Align > TLI.getMinStackArgumentAlignment()) { 3009 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 3010 3011 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList, 3012 DAG.getConstant(Align - 1, 3013 VAList.getValueType())); 3014 3015 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList, 3016 DAG.getConstant(-(int64_t)Align, 3017 VAList.getValueType())); 3018 } 3019 3020 // Increment the pointer, VAList, to the next vaarg 3021 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList, 3022 DAG.getConstant(TLI.getDataLayout()-> 3023 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 3024 VAList.getValueType())); 3025 // Store the incremented VAList to the legalized pointer 3026 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, 3027 MachinePointerInfo(V), false, false, 0); 3028 // Load the actual argument out of the pointer VAList 3029 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(), 3030 false, false, false, 0)); 3031 Results.push_back(Results[0].getValue(1)); 3032 break; 3033 } 3034 case ISD::VACOPY: { 3035 // This defaults to loading a pointer from the input and storing it to the 3036 // output, returning the chain. 3037 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3038 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3039 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 3040 Node->getOperand(2), MachinePointerInfo(VS), 3041 false, false, false, 0); 3042 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), 3043 MachinePointerInfo(VD), false, false, 0); 3044 Results.push_back(Tmp1); 3045 break; 3046 } 3047 case ISD::EXTRACT_VECTOR_ELT: 3048 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 3049 // This must be an access of the only element. Return it. 3050 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), 3051 Node->getOperand(0)); 3052 else 3053 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 3054 Results.push_back(Tmp1); 3055 break; 3056 case ISD::EXTRACT_SUBVECTOR: 3057 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 3058 break; 3059 case ISD::INSERT_SUBVECTOR: 3060 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0))); 3061 break; 3062 case ISD::CONCAT_VECTORS: { 3063 Results.push_back(ExpandVectorBuildThroughStack(Node)); 3064 break; 3065 } 3066 case ISD::SCALAR_TO_VECTOR: 3067 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 3068 break; 3069 case ISD::INSERT_VECTOR_ELT: 3070 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 3071 Node->getOperand(1), 3072 Node->getOperand(2), dl)); 3073 break; 3074 case ISD::VECTOR_SHUFFLE: { 3075 SmallVector<int, 32> NewMask; 3076 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask(); 3077 3078 EVT VT = Node->getValueType(0); 3079 EVT EltVT = VT.getVectorElementType(); 3080 SDValue Op0 = Node->getOperand(0); 3081 SDValue Op1 = Node->getOperand(1); 3082 if (!TLI.isTypeLegal(EltVT)) { 3083 3084 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT); 3085 3086 // BUILD_VECTOR operands are allowed to be wider than the element type. 3087 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it 3088 if (NewEltVT.bitsLT(EltVT)) { 3089 3090 // Convert shuffle node. 3091 // If original node was v4i64 and the new EltVT is i32, 3092 // cast operands to v8i32 and re-build the mask. 3093 3094 // Calculate new VT, the size of the new VT should be equal to original. 3095 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT, 3096 VT.getSizeInBits()/NewEltVT.getSizeInBits()); 3097 assert(NewVT.bitsEq(VT)); 3098 3099 // cast operands to new VT 3100 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); 3101 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); 3102 3103 // Convert the shuffle mask 3104 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements(); 3105 3106 // EltVT gets smaller 3107 assert(factor > 0); 3108 3109 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) { 3110 if (Mask[i] < 0) { 3111 for (unsigned fi = 0; fi < factor; ++fi) 3112 NewMask.push_back(Mask[i]); 3113 } 3114 else { 3115 for (unsigned fi = 0; fi < factor; ++fi) 3116 NewMask.push_back(Mask[i]*factor+fi); 3117 } 3118 } 3119 Mask = NewMask; 3120 VT = NewVT; 3121 } 3122 EltVT = NewEltVT; 3123 } 3124 unsigned NumElems = VT.getVectorNumElements(); 3125 SmallVector<SDValue, 16> Ops; 3126 for (unsigned i = 0; i != NumElems; ++i) { 3127 if (Mask[i] < 0) { 3128 Ops.push_back(DAG.getUNDEF(EltVT)); 3129 continue; 3130 } 3131 unsigned Idx = Mask[i]; 3132 if (Idx < NumElems) 3133 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 3134 Op0, 3135 DAG.getConstant(Idx, TLI.getVectorIdxTy()))); 3136 else 3137 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 3138 Op1, 3139 DAG.getConstant(Idx - NumElems, 3140 TLI.getVectorIdxTy()))); 3141 } 3142 3143 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 3144 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type. 3145 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1); 3146 Results.push_back(Tmp1); 3147 break; 3148 } 3149 case ISD::EXTRACT_ELEMENT: { 3150 EVT OpTy = Node->getOperand(0).getValueType(); 3151 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 3152 // 1 -> Hi 3153 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 3154 DAG.getConstant(OpTy.getSizeInBits()/2, 3155 TLI.getShiftAmountTy(Node->getOperand(0).getValueType()))); 3156 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 3157 } else { 3158 // 0 -> Lo 3159 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 3160 Node->getOperand(0)); 3161 } 3162 Results.push_back(Tmp1); 3163 break; 3164 } 3165 case ISD::STACKSAVE: 3166 // Expand to CopyFromReg if the target set 3167 // StackPointerRegisterToSaveRestore. 3168 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 3169 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 3170 Node->getValueType(0))); 3171 Results.push_back(Results[0].getValue(1)); 3172 } else { 3173 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 3174 Results.push_back(Node->getOperand(0)); 3175 } 3176 break; 3177 case ISD::STACKRESTORE: 3178 // Expand to CopyToReg if the target set 3179 // StackPointerRegisterToSaveRestore. 3180 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 3181 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 3182 Node->getOperand(1))); 3183 } else { 3184 Results.push_back(Node->getOperand(0)); 3185 } 3186 break; 3187 case ISD::FCOPYSIGN: 3188 Results.push_back(ExpandFCOPYSIGN(Node)); 3189 break; 3190 case ISD::FNEG: 3191 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3192 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3193 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 3194 Node->getOperand(0)); 3195 Results.push_back(Tmp1); 3196 break; 3197 case ISD::FABS: { 3198 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3199 EVT VT = Node->getValueType(0); 3200 Tmp1 = Node->getOperand(0); 3201 Tmp2 = DAG.getConstantFP(0.0, VT); 3202 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()), 3203 Tmp1, Tmp2, ISD::SETUGT); 3204 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 3205 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3); 3206 Results.push_back(Tmp1); 3207 break; 3208 } 3209 case ISD::FSQRT: 3210 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3211 RTLIB::SQRT_F80, RTLIB::SQRT_F128, 3212 RTLIB::SQRT_PPCF128)); 3213 break; 3214 case ISD::FSIN: 3215 case ISD::FCOS: { 3216 EVT VT = Node->getValueType(0); 3217 bool isSIN = Node->getOpcode() == ISD::FSIN; 3218 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin / 3219 // fcos which share the same operand and both are used. 3220 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) || 3221 canCombineSinCosLibcall(Node, TLI, TM)) 3222 && useSinCos(Node)) { 3223 SDVTList VTs = DAG.getVTList(VT, VT); 3224 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0)); 3225 if (!isSIN) 3226 Tmp1 = Tmp1.getValue(1); 3227 Results.push_back(Tmp1); 3228 } else if (isSIN) { 3229 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 3230 RTLIB::SIN_F80, RTLIB::SIN_F128, 3231 RTLIB::SIN_PPCF128)); 3232 } else { 3233 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 3234 RTLIB::COS_F80, RTLIB::COS_F128, 3235 RTLIB::COS_PPCF128)); 3236 } 3237 break; 3238 } 3239 case ISD::FSINCOS: 3240 // Expand into sincos libcall. 3241 ExpandSinCosLibCall(Node, Results); 3242 break; 3243 case ISD::FLOG: 3244 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 3245 RTLIB::LOG_F80, RTLIB::LOG_F128, 3246 RTLIB::LOG_PPCF128)); 3247 break; 3248 case ISD::FLOG2: 3249 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 3250 RTLIB::LOG2_F80, RTLIB::LOG2_F128, 3251 RTLIB::LOG2_PPCF128)); 3252 break; 3253 case ISD::FLOG10: 3254 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 3255 RTLIB::LOG10_F80, RTLIB::LOG10_F128, 3256 RTLIB::LOG10_PPCF128)); 3257 break; 3258 case ISD::FEXP: 3259 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 3260 RTLIB::EXP_F80, RTLIB::EXP_F128, 3261 RTLIB::EXP_PPCF128)); 3262 break; 3263 case ISD::FEXP2: 3264 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 3265 RTLIB::EXP2_F80, RTLIB::EXP2_F128, 3266 RTLIB::EXP2_PPCF128)); 3267 break; 3268 case ISD::FTRUNC: 3269 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 3270 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128, 3271 RTLIB::TRUNC_PPCF128)); 3272 break; 3273 case ISD::FFLOOR: 3274 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 3275 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128, 3276 RTLIB::FLOOR_PPCF128)); 3277 break; 3278 case ISD::FCEIL: 3279 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 3280 RTLIB::CEIL_F80, RTLIB::CEIL_F128, 3281 RTLIB::CEIL_PPCF128)); 3282 break; 3283 case ISD::FRINT: 3284 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 3285 RTLIB::RINT_F80, RTLIB::RINT_F128, 3286 RTLIB::RINT_PPCF128)); 3287 break; 3288 case ISD::FNEARBYINT: 3289 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 3290 RTLIB::NEARBYINT_F64, 3291 RTLIB::NEARBYINT_F80, 3292 RTLIB::NEARBYINT_F128, 3293 RTLIB::NEARBYINT_PPCF128)); 3294 break; 3295 case ISD::FROUND: 3296 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32, 3297 RTLIB::ROUND_F64, 3298 RTLIB::ROUND_F80, 3299 RTLIB::ROUND_F128, 3300 RTLIB::ROUND_PPCF128)); 3301 break; 3302 case ISD::FPOWI: 3303 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 3304 RTLIB::POWI_F80, RTLIB::POWI_F128, 3305 RTLIB::POWI_PPCF128)); 3306 break; 3307 case ISD::FPOW: 3308 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 3309 RTLIB::POW_F80, RTLIB::POW_F128, 3310 RTLIB::POW_PPCF128)); 3311 break; 3312 case ISD::FDIV: 3313 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 3314 RTLIB::DIV_F80, RTLIB::DIV_F128, 3315 RTLIB::DIV_PPCF128)); 3316 break; 3317 case ISD::FREM: 3318 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 3319 RTLIB::REM_F80, RTLIB::REM_F128, 3320 RTLIB::REM_PPCF128)); 3321 break; 3322 case ISD::FMA: 3323 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64, 3324 RTLIB::FMA_F80, RTLIB::FMA_F128, 3325 RTLIB::FMA_PPCF128)); 3326 break; 3327 case ISD::FP16_TO_FP32: 3328 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 3329 break; 3330 case ISD::FP32_TO_FP16: 3331 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 3332 break; 3333 case ISD::ConstantFP: { 3334 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 3335 // Check to see if this FP immediate is already legal. 3336 // If this is a legal constant, turn it into a TargetConstantFP node. 3337 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 3338 Results.push_back(ExpandConstantFP(CFP, true)); 3339 break; 3340 } 3341 case ISD::FSUB: { 3342 EVT VT = Node->getValueType(0); 3343 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) && 3344 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) && 3345 "Don't know how to expand this FP subtraction!"); 3346 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1)); 3347 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1); 3348 Results.push_back(Tmp1); 3349 break; 3350 } 3351 case ISD::SUB: { 3352 EVT VT = Node->getValueType(0); 3353 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 3354 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 3355 "Don't know how to expand this subtraction!"); 3356 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 3357 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 3358 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT)); 3359 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 3360 break; 3361 } 3362 case ISD::UREM: 3363 case ISD::SREM: { 3364 EVT VT = Node->getValueType(0); 3365 bool isSigned = Node->getOpcode() == ISD::SREM; 3366 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 3367 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 3368 Tmp2 = Node->getOperand(0); 3369 Tmp3 = Node->getOperand(1); 3370 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) || 3371 (isDivRemLibcallAvailable(Node, isSigned, TLI) && 3372 // If div is legal, it's better to do the normal expansion 3373 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) && 3374 useDivRem(Node, isSigned, false))) { 3375 SDVTList VTs = DAG.getVTList(VT, VT); 3376 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 3377 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 3378 // X % Y -> X-X/Y*Y 3379 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 3380 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 3381 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 3382 } else if (isSigned) 3383 Tmp1 = ExpandIntLibCall(Node, true, 3384 RTLIB::SREM_I8, 3385 RTLIB::SREM_I16, RTLIB::SREM_I32, 3386 RTLIB::SREM_I64, RTLIB::SREM_I128); 3387 else 3388 Tmp1 = ExpandIntLibCall(Node, false, 3389 RTLIB::UREM_I8, 3390 RTLIB::UREM_I16, RTLIB::UREM_I32, 3391 RTLIB::UREM_I64, RTLIB::UREM_I128); 3392 Results.push_back(Tmp1); 3393 break; 3394 } 3395 case ISD::UDIV: 3396 case ISD::SDIV: { 3397 bool isSigned = Node->getOpcode() == ISD::SDIV; 3398 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 3399 EVT VT = Node->getValueType(0); 3400 SDVTList VTs = DAG.getVTList(VT, VT); 3401 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) || 3402 (isDivRemLibcallAvailable(Node, isSigned, TLI) && 3403 useDivRem(Node, isSigned, true))) 3404 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 3405 Node->getOperand(1)); 3406 else if (isSigned) 3407 Tmp1 = ExpandIntLibCall(Node, true, 3408 RTLIB::SDIV_I8, 3409 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 3410 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 3411 else 3412 Tmp1 = ExpandIntLibCall(Node, false, 3413 RTLIB::UDIV_I8, 3414 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 3415 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 3416 Results.push_back(Tmp1); 3417 break; 3418 } 3419 case ISD::MULHU: 3420 case ISD::MULHS: { 3421 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 3422 ISD::SMUL_LOHI; 3423 EVT VT = Node->getValueType(0); 3424 SDVTList VTs = DAG.getVTList(VT, VT); 3425 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 3426 "If this wasn't legal, it shouldn't have been created!"); 3427 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 3428 Node->getOperand(1)); 3429 Results.push_back(Tmp1.getValue(1)); 3430 break; 3431 } 3432 case ISD::SDIVREM: 3433 case ISD::UDIVREM: 3434 // Expand into divrem libcall 3435 ExpandDivRemLibCall(Node, Results); 3436 break; 3437 case ISD::MUL: { 3438 EVT VT = Node->getValueType(0); 3439 SDVTList VTs = DAG.getVTList(VT, VT); 3440 // See if multiply or divide can be lowered using two-result operations. 3441 // We just need the low half of the multiply; try both the signed 3442 // and unsigned forms. If the target supports both SMUL_LOHI and 3443 // UMUL_LOHI, form a preference by checking which forms of plain 3444 // MULH it supports. 3445 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 3446 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 3447 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 3448 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 3449 unsigned OpToUse = 0; 3450 if (HasSMUL_LOHI && !HasMULHS) { 3451 OpToUse = ISD::SMUL_LOHI; 3452 } else if (HasUMUL_LOHI && !HasMULHU) { 3453 OpToUse = ISD::UMUL_LOHI; 3454 } else if (HasSMUL_LOHI) { 3455 OpToUse = ISD::SMUL_LOHI; 3456 } else if (HasUMUL_LOHI) { 3457 OpToUse = ISD::UMUL_LOHI; 3458 } 3459 if (OpToUse) { 3460 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 3461 Node->getOperand(1))); 3462 break; 3463 } 3464 Tmp1 = ExpandIntLibCall(Node, false, 3465 RTLIB::MUL_I8, 3466 RTLIB::MUL_I16, RTLIB::MUL_I32, 3467 RTLIB::MUL_I64, RTLIB::MUL_I128); 3468 Results.push_back(Tmp1); 3469 break; 3470 } 3471 case ISD::SADDO: 3472 case ISD::SSUBO: { 3473 SDValue LHS = Node->getOperand(0); 3474 SDValue RHS = Node->getOperand(1); 3475 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 3476 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3477 LHS, RHS); 3478 Results.push_back(Sum); 3479 EVT OType = Node->getValueType(1); 3480 3481 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 3482 3483 // LHSSign -> LHS >= 0 3484 // RHSSign -> RHS >= 0 3485 // SumSign -> Sum >= 0 3486 // 3487 // Add: 3488 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 3489 // Sub: 3490 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 3491 // 3492 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 3493 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 3494 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 3495 Node->getOpcode() == ISD::SADDO ? 3496 ISD::SETEQ : ISD::SETNE); 3497 3498 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 3499 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 3500 3501 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 3502 Results.push_back(Cmp); 3503 break; 3504 } 3505 case ISD::UADDO: 3506 case ISD::USUBO: { 3507 SDValue LHS = Node->getOperand(0); 3508 SDValue RHS = Node->getOperand(1); 3509 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 3510 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3511 LHS, RHS); 3512 Results.push_back(Sum); 3513 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 3514 Node->getOpcode () == ISD::UADDO ? 3515 ISD::SETULT : ISD::SETUGT)); 3516 break; 3517 } 3518 case ISD::UMULO: 3519 case ISD::SMULO: { 3520 EVT VT = Node->getValueType(0); 3521 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 3522 SDValue LHS = Node->getOperand(0); 3523 SDValue RHS = Node->getOperand(1); 3524 SDValue BottomHalf; 3525 SDValue TopHalf; 3526 static const unsigned Ops[2][3] = 3527 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 3528 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 3529 bool isSigned = Node->getOpcode() == ISD::SMULO; 3530 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 3531 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 3532 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 3533 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 3534 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 3535 RHS); 3536 TopHalf = BottomHalf.getValue(1); 3537 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), 3538 VT.getSizeInBits() * 2))) { 3539 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 3540 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 3541 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 3542 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3543 DAG.getIntPtrConstant(0)); 3544 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3545 DAG.getIntPtrConstant(1)); 3546 } else { 3547 // We can fall back to a libcall with an illegal type for the MUL if we 3548 // have a libcall big enough. 3549 // Also, we can fall back to a division in some cases, but that's a big 3550 // performance hit in the general case. 3551 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3552 if (WideVT == MVT::i16) 3553 LC = RTLIB::MUL_I16; 3554 else if (WideVT == MVT::i32) 3555 LC = RTLIB::MUL_I32; 3556 else if (WideVT == MVT::i64) 3557 LC = RTLIB::MUL_I64; 3558 else if (WideVT == MVT::i128) 3559 LC = RTLIB::MUL_I128; 3560 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!"); 3561 3562 // The high part is obtained by SRA'ing all but one of the bits of low 3563 // part. 3564 unsigned LoSize = VT.getSizeInBits(); 3565 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS, 3566 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 3567 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS, 3568 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 3569 3570 // Here we're passing the 2 arguments explicitly as 4 arguments that are 3571 // pre-lowered to the correct types. This all depends upon WideVT not 3572 // being a legal type for the architecture and thus has to be split to 3573 // two arguments. 3574 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS }; 3575 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl); 3576 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret, 3577 DAG.getIntPtrConstant(0)); 3578 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret, 3579 DAG.getIntPtrConstant(1)); 3580 // Ret is a node with an illegal type. Because such things are not 3581 // generally permitted during this phase of legalization, delete the 3582 // node. The above EXTRACT_ELEMENT nodes should have been folded. 3583 DAG.DeleteNode(Ret.getNode()); 3584 } 3585 3586 if (isSigned) { 3587 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, 3588 TLI.getShiftAmountTy(BottomHalf.getValueType())); 3589 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 3590 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1, 3591 ISD::SETNE); 3592 } else { 3593 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, 3594 DAG.getConstant(0, VT), ISD::SETNE); 3595 } 3596 Results.push_back(BottomHalf); 3597 Results.push_back(TopHalf); 3598 break; 3599 } 3600 case ISD::BUILD_PAIR: { 3601 EVT PairTy = Node->getValueType(0); 3602 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 3603 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 3604 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 3605 DAG.getConstant(PairTy.getSizeInBits()/2, 3606 TLI.getShiftAmountTy(PairTy))); 3607 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 3608 break; 3609 } 3610 case ISD::SELECT: 3611 Tmp1 = Node->getOperand(0); 3612 Tmp2 = Node->getOperand(1); 3613 Tmp3 = Node->getOperand(2); 3614 if (Tmp1.getOpcode() == ISD::SETCC) { 3615 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 3616 Tmp2, Tmp3, 3617 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 3618 } else { 3619 Tmp1 = DAG.getSelectCC(dl, Tmp1, 3620 DAG.getConstant(0, Tmp1.getValueType()), 3621 Tmp2, Tmp3, ISD::SETNE); 3622 } 3623 Results.push_back(Tmp1); 3624 break; 3625 case ISD::BR_JT: { 3626 SDValue Chain = Node->getOperand(0); 3627 SDValue Table = Node->getOperand(1); 3628 SDValue Index = Node->getOperand(2); 3629 3630 EVT PTy = TLI.getPointerTy(); 3631 3632 const DataLayout &TD = *TLI.getDataLayout(); 3633 unsigned EntrySize = 3634 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 3635 3636 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), 3637 Index, DAG.getConstant(EntrySize, Index.getValueType())); 3638 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(), 3639 Index, Table); 3640 3641 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 3642 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 3643 MachinePointerInfo::getJumpTable(), MemVT, 3644 false, false, 0); 3645 Addr = LD; 3646 if (TM.getRelocationModel() == Reloc::PIC_) { 3647 // For PIC, the sequence is: 3648 // BRIND(load(Jumptable + index) + RelocBase) 3649 // RelocBase can be JumpTable, GOT or some sort of global base. 3650 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 3651 TLI.getPICJumpTableRelocBase(Table, DAG)); 3652 } 3653 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 3654 Results.push_back(Tmp1); 3655 break; 3656 } 3657 case ISD::BRCOND: 3658 // Expand brcond's setcc into its constituent parts and create a BR_CC 3659 // Node. 3660 Tmp1 = Node->getOperand(0); 3661 Tmp2 = Node->getOperand(1); 3662 if (Tmp2.getOpcode() == ISD::SETCC) { 3663 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 3664 Tmp1, Tmp2.getOperand(2), 3665 Tmp2.getOperand(0), Tmp2.getOperand(1), 3666 Node->getOperand(2)); 3667 } else { 3668 // We test only the i1 bit. Skip the AND if UNDEF. 3669 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 : 3670 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2, 3671 DAG.getConstant(1, Tmp2.getValueType())); 3672 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 3673 DAG.getCondCode(ISD::SETNE), Tmp3, 3674 DAG.getConstant(0, Tmp3.getValueType()), 3675 Node->getOperand(2)); 3676 } 3677 Results.push_back(Tmp1); 3678 break; 3679 case ISD::SETCC: { 3680 Tmp1 = Node->getOperand(0); 3681 Tmp2 = Node->getOperand(1); 3682 Tmp3 = Node->getOperand(2); 3683 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, 3684 Tmp3, dl); 3685 3686 if (Legalized) { 3687 // If we exapanded the SETCC by swapping LHS and RHS, create a new SETCC 3688 // node. 3689 if (Tmp3.getNode()) 3690 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3691 Tmp1, Tmp2, Tmp3); 3692 3693 Results.push_back(Tmp1); 3694 break; 3695 } 3696 3697 // Otherwise, SETCC for the given comparison type must be completely 3698 // illegal; expand it into a SELECT_CC. 3699 EVT VT = Node->getValueType(0); 3700 int TrueValue; 3701 switch (TLI.getBooleanContents(VT.isVector())) { 3702 case TargetLowering::ZeroOrOneBooleanContent: 3703 case TargetLowering::UndefinedBooleanContent: 3704 TrueValue = 1; 3705 break; 3706 case TargetLowering::ZeroOrNegativeOneBooleanContent: 3707 TrueValue = -1; 3708 break; 3709 } 3710 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3711 DAG.getConstant(TrueValue, VT), DAG.getConstant(0, VT), 3712 Tmp3); 3713 Results.push_back(Tmp1); 3714 break; 3715 } 3716 case ISD::SELECT_CC: { 3717 Tmp1 = Node->getOperand(0); // LHS 3718 Tmp2 = Node->getOperand(1); // RHS 3719 Tmp3 = Node->getOperand(2); // True 3720 Tmp4 = Node->getOperand(3); // False 3721 SDValue CC = Node->getOperand(4); 3722 3723 bool Legalized = false; 3724 // Try to legalize by inverting the condition. This is for targets that 3725 // might support an ordered version of a condition, but not the unordered 3726 // version (or vice versa). 3727 ISD::CondCode InvCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3728 Tmp1.getValueType().isInteger()); 3729 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) { 3730 // Use the new condition code and swap true and false 3731 Legalized = true; 3732 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC); 3733 } else { 3734 // If The inverse is not legal, then try to swap the arguments using 3735 // the inverse condition code. 3736 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC); 3737 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) { 3738 // The swapped inverse condition is legal, so swap true and false, 3739 // lhs and rhs. 3740 Legalized = true; 3741 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC); 3742 } 3743 } 3744 3745 if (!Legalized) { 3746 Legalized = LegalizeSetCCCondCode( 3747 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, dl); 3748 3749 assert(Legalized && "Can't legalize SELECT_CC with legal condition!"); 3750 // If we exapanded the SETCC by swapping LHS and RHS, create a new 3751 // SELECT_CC node. 3752 if (CC.getNode()) { 3753 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), 3754 Tmp1, Tmp2, Tmp3, Tmp4, CC); 3755 } else { 3756 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3757 CC = DAG.getCondCode(ISD::SETNE); 3758 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 3759 Tmp3, Tmp4, CC); 3760 } 3761 } 3762 Results.push_back(Tmp1); 3763 break; 3764 } 3765 case ISD::BR_CC: { 3766 Tmp1 = Node->getOperand(0); // Chain 3767 Tmp2 = Node->getOperand(2); // LHS 3768 Tmp3 = Node->getOperand(3); // RHS 3769 Tmp4 = Node->getOperand(1); // CC 3770 3771 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType( 3772 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, dl); 3773 (void)Legalized; 3774 assert(Legalized && "Can't legalize BR_CC with legal condition!"); 3775 3776 // If we exapanded the SETCC by swapping LHS and RHS, create a new BR_CC 3777 // node. 3778 if (Tmp4.getNode()) { 3779 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, 3780 Tmp4, Tmp2, Tmp3, Node->getOperand(4)); 3781 } else { 3782 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 3783 Tmp4 = DAG.getCondCode(ISD::SETNE); 3784 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 3785 Tmp3, Node->getOperand(4)); 3786 } 3787 Results.push_back(Tmp1); 3788 break; 3789 } 3790 case ISD::BUILD_VECTOR: 3791 Results.push_back(ExpandBUILD_VECTOR(Node)); 3792 break; 3793 case ISD::SRA: 3794 case ISD::SRL: 3795 case ISD::SHL: { 3796 // Scalarize vector SRA/SRL/SHL. 3797 EVT VT = Node->getValueType(0); 3798 assert(VT.isVector() && "Unable to legalize non-vector shift"); 3799 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal"); 3800 unsigned NumElem = VT.getVectorNumElements(); 3801 3802 SmallVector<SDValue, 8> Scalars; 3803 for (unsigned Idx = 0; Idx < NumElem; Idx++) { 3804 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 3805 VT.getScalarType(), 3806 Node->getOperand(0), DAG.getConstant(Idx, 3807 TLI.getVectorIdxTy())); 3808 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 3809 VT.getScalarType(), 3810 Node->getOperand(1), DAG.getConstant(Idx, 3811 TLI.getVectorIdxTy())); 3812 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl, 3813 VT.getScalarType(), Ex, Sh)); 3814 } 3815 SDValue Result = 3816 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), 3817 &Scalars[0], Scalars.size()); 3818 ReplaceNode(SDValue(Node, 0), Result); 3819 break; 3820 } 3821 case ISD::GLOBAL_OFFSET_TABLE: 3822 case ISD::GlobalAddress: 3823 case ISD::GlobalTLSAddress: 3824 case ISD::ExternalSymbol: 3825 case ISD::ConstantPool: 3826 case ISD::JumpTable: 3827 case ISD::INTRINSIC_W_CHAIN: 3828 case ISD::INTRINSIC_WO_CHAIN: 3829 case ISD::INTRINSIC_VOID: 3830 // FIXME: Custom lowering for these operations shouldn't return null! 3831 break; 3832 } 3833 3834 // Replace the original node with the legalized result. 3835 if (!Results.empty()) 3836 ReplaceNode(Node, Results.data()); 3837} 3838 3839void SelectionDAGLegalize::PromoteNode(SDNode *Node) { 3840 SmallVector<SDValue, 8> Results; 3841 MVT OVT = Node->getSimpleValueType(0); 3842 if (Node->getOpcode() == ISD::UINT_TO_FP || 3843 Node->getOpcode() == ISD::SINT_TO_FP || 3844 Node->getOpcode() == ISD::SETCC) { 3845 OVT = Node->getOperand(0).getSimpleValueType(); 3846 } 3847 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3848 SDLoc dl(Node); 3849 SDValue Tmp1, Tmp2, Tmp3; 3850 switch (Node->getOpcode()) { 3851 case ISD::CTTZ: 3852 case ISD::CTTZ_ZERO_UNDEF: 3853 case ISD::CTLZ: 3854 case ISD::CTLZ_ZERO_UNDEF: 3855 case ISD::CTPOP: 3856 // Zero extend the argument. 3857 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3858 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is 3859 // already the correct result. 3860 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3861 if (Node->getOpcode() == ISD::CTTZ) { 3862 // FIXME: This should set a bit in the zero extended value instead. 3863 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), 3864 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3865 ISD::SETEQ); 3866 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, 3867 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3868 } else if (Node->getOpcode() == ISD::CTLZ || 3869 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) { 3870 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3871 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3872 DAG.getConstant(NVT.getSizeInBits() - 3873 OVT.getSizeInBits(), NVT)); 3874 } 3875 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3876 break; 3877 case ISD::BSWAP: { 3878 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3879 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3880 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3881 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3882 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT))); 3883 Results.push_back(Tmp1); 3884 break; 3885 } 3886 case ISD::FP_TO_UINT: 3887 case ISD::FP_TO_SINT: 3888 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3889 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3890 Results.push_back(Tmp1); 3891 break; 3892 case ISD::UINT_TO_FP: 3893 case ISD::SINT_TO_FP: 3894 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3895 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3896 Results.push_back(Tmp1); 3897 break; 3898 case ISD::VAARG: { 3899 SDValue Chain = Node->getOperand(0); // Get the chain. 3900 SDValue Ptr = Node->getOperand(1); // Get the pointer. 3901 3902 unsigned TruncOp; 3903 if (OVT.isVector()) { 3904 TruncOp = ISD::BITCAST; 3905 } else { 3906 assert(OVT.isInteger() 3907 && "VAARG promotion is supported only for vectors or integer types"); 3908 TruncOp = ISD::TRUNCATE; 3909 } 3910 3911 // Perform the larger operation, then convert back 3912 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2), 3913 Node->getConstantOperandVal(3)); 3914 Chain = Tmp1.getValue(1); 3915 3916 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1); 3917 3918 // Modified the chain result - switch anything that used the old chain to 3919 // use the new one. 3920 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2); 3921 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain); 3922 ReplacedNode(Node); 3923 break; 3924 } 3925 case ISD::AND: 3926 case ISD::OR: 3927 case ISD::XOR: { 3928 unsigned ExtOp, TruncOp; 3929 if (OVT.isVector()) { 3930 ExtOp = ISD::BITCAST; 3931 TruncOp = ISD::BITCAST; 3932 } else { 3933 assert(OVT.isInteger() && "Cannot promote logic operation"); 3934 ExtOp = ISD::ANY_EXTEND; 3935 TruncOp = ISD::TRUNCATE; 3936 } 3937 // Promote each of the values to the new type. 3938 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3939 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3940 // Perform the larger operation, then convert back 3941 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3942 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3943 break; 3944 } 3945 case ISD::SELECT: { 3946 unsigned ExtOp, TruncOp; 3947 if (Node->getValueType(0).isVector()) { 3948 ExtOp = ISD::BITCAST; 3949 TruncOp = ISD::BITCAST; 3950 } else if (Node->getValueType(0).isInteger()) { 3951 ExtOp = ISD::ANY_EXTEND; 3952 TruncOp = ISD::TRUNCATE; 3953 } else { 3954 ExtOp = ISD::FP_EXTEND; 3955 TruncOp = ISD::FP_ROUND; 3956 } 3957 Tmp1 = Node->getOperand(0); 3958 // Promote each of the values to the new type. 3959 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3960 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3961 // Perform the larger operation, then round down. 3962 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3); 3963 if (TruncOp != ISD::FP_ROUND) 3964 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3965 else 3966 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3967 DAG.getIntPtrConstant(0)); 3968 Results.push_back(Tmp1); 3969 break; 3970 } 3971 case ISD::VECTOR_SHUFFLE: { 3972 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask(); 3973 3974 // Cast the two input vectors. 3975 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0)); 3976 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1)); 3977 3978 // Convert the shuffle mask to the right # elements. 3979 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3980 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1); 3981 Results.push_back(Tmp1); 3982 break; 3983 } 3984 case ISD::SETCC: { 3985 unsigned ExtOp = ISD::FP_EXTEND; 3986 if (NVT.isInteger()) { 3987 ISD::CondCode CCCode = 3988 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3989 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3990 } 3991 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3992 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3993 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3994 Tmp1, Tmp2, Node->getOperand(2))); 3995 break; 3996 } 3997 case ISD::FDIV: 3998 case ISD::FREM: 3999 case ISD::FPOW: { 4000 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); 4001 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); 4002 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 4003 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, 4004 Tmp3, DAG.getIntPtrConstant(0))); 4005 break; 4006 } 4007 case ISD::FLOG2: 4008 case ISD::FEXP2: 4009 case ISD::FLOG: 4010 case ISD::FEXP: { 4011 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); 4012 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 4013 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, 4014 Tmp2, DAG.getIntPtrConstant(0))); 4015 break; 4016 } 4017 } 4018 4019 // Replace the original node with the legalized result. 4020 if (!Results.empty()) 4021 ReplaceNode(Node, Results.data()); 4022} 4023 4024// SelectionDAG::Legalize - This is the entry point for the file. 4025// 4026void SelectionDAG::Legalize() { 4027 /// run - This is the main entry point to this class. 4028 /// 4029 SelectionDAGLegalize(*this).LegalizeDAG(); 4030} 4031