LegalizeDAG.cpp revision 51eaa86758338d5935c0eff0469c418b1256aba7
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetMachine.h" 21#include "llvm/Target/TargetOptions.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Support/MathExtras.h" 26#include "llvm/Support/CommandLine.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/ADT/DenseMap.h" 29#include "llvm/ADT/SmallVector.h" 30#include "llvm/ADT/SmallPtrSet.h" 31#include <map> 32using namespace llvm; 33 34#ifndef NDEBUG 35static cl::opt<bool> 36ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 37 cl::desc("Pop up a window to show dags before legalize")); 38#else 39static const bool ViewLegalizeDAGs = 0; 40#endif 41 42namespace llvm { 43template<> 44struct DenseMapKeyInfo<SDOperand> { 45 static inline SDOperand getEmptyKey() { return SDOperand((SDNode*)-1, -1U); } 46 static inline SDOperand getTombstoneKey() { return SDOperand((SDNode*)-1, 0);} 47 static unsigned getHashValue(const SDOperand &Val) { 48 return DenseMapKeyInfo<void*>::getHashValue(Val.Val) + Val.ResNo; 49 } 50 static bool isPod() { return true; } 51}; 52} 53 54//===----------------------------------------------------------------------===// 55/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 56/// hacks on it until the target machine can handle it. This involves 57/// eliminating value sizes the machine cannot handle (promoting small sizes to 58/// large sizes or splitting up large values into small values) as well as 59/// eliminating operations the machine cannot handle. 60/// 61/// This code also does a small amount of optimization and recognition of idioms 62/// as part of its processing. For example, if a target does not support a 63/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 64/// will attempt merge setcc and brc instructions into brcc's. 65/// 66namespace { 67class VISIBILITY_HIDDEN SelectionDAGLegalize { 68 TargetLowering &TLI; 69 SelectionDAG &DAG; 70 71 // Libcall insertion helpers. 72 73 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 74 /// legalized. We use this to ensure that calls are properly serialized 75 /// against each other, including inserted libcalls. 76 SDOperand LastCALLSEQ_END; 77 78 /// IsLegalizingCall - This member is used *only* for purposes of providing 79 /// helpful assertions that a libcall isn't created while another call is 80 /// being legalized (which could lead to non-serialized call sequences). 81 bool IsLegalizingCall; 82 83 enum LegalizeAction { 84 Legal, // The target natively supports this operation. 85 Promote, // This operation should be executed in a larger type. 86 Expand // Try to expand this to other ops, otherwise use a libcall. 87 }; 88 89 /// ValueTypeActions - This is a bitvector that contains two bits for each 90 /// value type, where the two bits correspond to the LegalizeAction enum. 91 /// This can be queried with "getTypeAction(VT)". 92 TargetLowering::ValueTypeActionImpl ValueTypeActions; 93 94 /// LegalizedNodes - For nodes that are of legal width, and that have more 95 /// than one use, this map indicates what regularized operand to use. This 96 /// allows us to avoid legalizing the same thing more than once. 97 DenseMap<SDOperand, SDOperand> LegalizedNodes; 98 99 /// PromotedNodes - For nodes that are below legal width, and that have more 100 /// than one use, this map indicates what promoted value to use. This allows 101 /// us to avoid promoting the same thing more than once. 102 DenseMap<SDOperand, SDOperand> PromotedNodes; 103 104 /// ExpandedNodes - For nodes that need to be expanded this map indicates 105 /// which which operands are the expanded version of the input. This allows 106 /// us to avoid expanding the same node more than once. 107 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 108 109 /// SplitNodes - For vector nodes that need to be split, this map indicates 110 /// which which operands are the split version of the input. This allows us 111 /// to avoid splitting the same node more than once. 112 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 113 114 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to 115 /// concrete vector types, this contains the mapping of ones we have already 116 /// processed to the result. 117 std::map<SDOperand, SDOperand> PackedNodes; 118 119 void AddLegalizedOperand(SDOperand From, SDOperand To) { 120 LegalizedNodes.insert(std::make_pair(From, To)); 121 // If someone requests legalization of the new node, return itself. 122 if (From != To) 123 LegalizedNodes.insert(std::make_pair(To, To)); 124 } 125 void AddPromotedOperand(SDOperand From, SDOperand To) { 126 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 127 assert(isNew && "Got into the map somehow?"); 128 // If someone requests legalization of the new node, return itself. 129 LegalizedNodes.insert(std::make_pair(To, To)); 130 } 131 132public: 133 134 SelectionDAGLegalize(SelectionDAG &DAG); 135 136 /// getTypeAction - Return how we should legalize values of this type, either 137 /// it is already legal or we need to expand it into multiple registers of 138 /// smaller integer type, or we need to promote it to a larger type. 139 LegalizeAction getTypeAction(MVT::ValueType VT) const { 140 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 141 } 142 143 /// isTypeLegal - Return true if this type is legal on this target. 144 /// 145 bool isTypeLegal(MVT::ValueType VT) const { 146 return getTypeAction(VT) == Legal; 147 } 148 149 void LegalizeDAG(); 150 151private: 152 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 153 /// appropriate for its type. 154 void HandleOp(SDOperand Op); 155 156 /// LegalizeOp - We know that the specified value has a legal type. 157 /// Recursively ensure that the operands have legal types, then return the 158 /// result. 159 SDOperand LegalizeOp(SDOperand O); 160 161 /// PromoteOp - Given an operation that produces a value in an invalid type, 162 /// promote it to compute the value into a larger type. The produced value 163 /// will have the correct bits for the low portion of the register, but no 164 /// guarantee is made about the top bits: it may be zero, sign-extended, or 165 /// garbage. 166 SDOperand PromoteOp(SDOperand O); 167 168 /// ExpandOp - Expand the specified SDOperand into its two component pieces 169 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 170 /// the LegalizeNodes map is filled in for any results that are not expanded, 171 /// the ExpandedNodes map is filled in for any results that are expanded, and 172 /// the Lo/Hi values are returned. This applies to integer types and Vector 173 /// types. 174 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 175 176 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 177 /// two smaller values of MVT::Vector type. 178 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 179 180 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 181 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When 182 /// this is called, we know that PackedVT is the right type for the result and 183 /// we know that this type is legal for the target. 184 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT); 185 186 /// isShuffleLegal - Return true if a vector shuffle is legal with the 187 /// specified mask and type. Targets can specify exactly which masks they 188 /// support and the code generator is tasked with not creating illegal masks. 189 /// 190 /// Note that this will also return true for shuffles that are promoted to a 191 /// different type. 192 /// 193 /// If this is a legal shuffle, this method returns the (possibly promoted) 194 /// build_vector Mask. If it's not a legal shuffle, it returns null. 195 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 196 197 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 198 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 199 200 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 201 202 SDOperand CreateStackTemporary(MVT::ValueType VT); 203 204 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 205 SDOperand &Hi); 206 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 207 SDOperand Source); 208 209 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 210 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 211 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 212 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 213 SDOperand LegalOp, 214 MVT::ValueType DestVT); 215 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 216 bool isSigned); 217 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 218 bool isSigned); 219 220 SDOperand ExpandBSWAP(SDOperand Op); 221 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 222 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 223 SDOperand &Lo, SDOperand &Hi); 224 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 225 SDOperand &Lo, SDOperand &Hi); 226 227 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op); 228 SDOperand LowerVEXTRACT_SUBVECTOR(SDOperand Op); 229 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 230 231 SDOperand getIntPtrConstant(uint64_t Val) { 232 return DAG.getConstant(Val, TLI.getPointerTy()); 233 } 234}; 235} 236 237/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 238/// specified mask and type. Targets can specify exactly which masks they 239/// support and the code generator is tasked with not creating illegal masks. 240/// 241/// Note that this will also return true for shuffles that are promoted to a 242/// different type. 243SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 244 SDOperand Mask) const { 245 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 246 default: return 0; 247 case TargetLowering::Legal: 248 case TargetLowering::Custom: 249 break; 250 case TargetLowering::Promote: { 251 // If this is promoted to a different type, convert the shuffle mask and 252 // ask if it is legal in the promoted type! 253 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 254 255 // If we changed # elements, change the shuffle mask. 256 unsigned NumEltsGrowth = 257 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 258 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 259 if (NumEltsGrowth > 1) { 260 // Renumber the elements. 261 SmallVector<SDOperand, 8> Ops; 262 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 263 SDOperand InOp = Mask.getOperand(i); 264 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 265 if (InOp.getOpcode() == ISD::UNDEF) 266 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 267 else { 268 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 269 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 270 } 271 } 272 } 273 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 274 } 275 VT = NVT; 276 break; 277 } 278 } 279 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 280} 281 282/// getScalarizedOpcode - Return the scalar opcode that corresponds to the 283/// specified vector opcode. 284static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 285 switch (VecOp) { 286 default: assert(0 && "Don't know how to scalarize this opcode!"); 287 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 288 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 289 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 290 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV; 291 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV; 292 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0; 293 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0; 294 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0; 295 } 296} 297 298SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 299 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 300 ValueTypeActions(TLI.getValueTypeActions()) { 301 assert(MVT::LAST_VALUETYPE <= 32 && 302 "Too many value types for ValueTypeActions to hold!"); 303} 304 305/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 306/// not been visited yet and if all of its operands have already been visited. 307static void ComputeTopDownOrdering(SDNode *N, SmallVector<SDNode*, 64> &Order, 308 DenseMap<SDNode*, unsigned> &Visited) { 309 if (++Visited[N] != N->getNumOperands()) 310 return; // Haven't visited all operands yet 311 312 Order.push_back(N); 313 314 if (N->hasOneUse()) { // Tail recurse in common case. 315 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 316 return; 317 } 318 319 // Now that we have N in, add anything that uses it if all of their operands 320 // are now done. 321 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 322 ComputeTopDownOrdering(*UI, Order, Visited); 323} 324 325 326void SelectionDAGLegalize::LegalizeDAG() { 327 LastCALLSEQ_END = DAG.getEntryNode(); 328 IsLegalizingCall = false; 329 330 // The legalize process is inherently a bottom-up recursive process (users 331 // legalize their uses before themselves). Given infinite stack space, we 332 // could just start legalizing on the root and traverse the whole graph. In 333 // practice however, this causes us to run out of stack space on large basic 334 // blocks. To avoid this problem, compute an ordering of the nodes where each 335 // node is only legalized after all of its operands are legalized. 336 DenseMap<SDNode*, unsigned> Visited; 337 SmallVector<SDNode*, 64> Order; 338 339 // Compute ordering from all of the leaves in the graphs, those (like the 340 // entry node) that have no operands. 341 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 342 E = DAG.allnodes_end(); I != E; ++I) { 343 if (I->getNumOperands() == 0) { 344 Visited[I] = 0 - 1U; 345 ComputeTopDownOrdering(I, Order, Visited); 346 } 347 } 348 349 assert(Order.size() == Visited.size() && 350 Order.size() == 351 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 352 "Error: DAG is cyclic!"); 353 Visited.clear(); 354 355 for (unsigned i = 0, e = Order.size(); i != e; ++i) 356 HandleOp(SDOperand(Order[i], 0)); 357 358 // Finally, it's possible the root changed. Get the new root. 359 SDOperand OldRoot = DAG.getRoot(); 360 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 361 DAG.setRoot(LegalizedNodes[OldRoot]); 362 363 ExpandedNodes.clear(); 364 LegalizedNodes.clear(); 365 PromotedNodes.clear(); 366 SplitNodes.clear(); 367 PackedNodes.clear(); 368 369 // Remove dead nodes now. 370 DAG.RemoveDeadNodes(); 371} 372 373 374/// FindCallEndFromCallStart - Given a chained node that is part of a call 375/// sequence, find the CALLSEQ_END node that terminates the call sequence. 376static SDNode *FindCallEndFromCallStart(SDNode *Node) { 377 if (Node->getOpcode() == ISD::CALLSEQ_END) 378 return Node; 379 if (Node->use_empty()) 380 return 0; // No CallSeqEnd 381 382 // The chain is usually at the end. 383 SDOperand TheChain(Node, Node->getNumValues()-1); 384 if (TheChain.getValueType() != MVT::Other) { 385 // Sometimes it's at the beginning. 386 TheChain = SDOperand(Node, 0); 387 if (TheChain.getValueType() != MVT::Other) { 388 // Otherwise, hunt for it. 389 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 390 if (Node->getValueType(i) == MVT::Other) { 391 TheChain = SDOperand(Node, i); 392 break; 393 } 394 395 // Otherwise, we walked into a node without a chain. 396 if (TheChain.getValueType() != MVT::Other) 397 return 0; 398 } 399 } 400 401 for (SDNode::use_iterator UI = Node->use_begin(), 402 E = Node->use_end(); UI != E; ++UI) { 403 404 // Make sure to only follow users of our token chain. 405 SDNode *User = *UI; 406 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 407 if (User->getOperand(i) == TheChain) 408 if (SDNode *Result = FindCallEndFromCallStart(User)) 409 return Result; 410 } 411 return 0; 412} 413 414/// FindCallStartFromCallEnd - Given a chained node that is part of a call 415/// sequence, find the CALLSEQ_START node that initiates the call sequence. 416static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 417 assert(Node && "Didn't find callseq_start for a call??"); 418 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 419 420 assert(Node->getOperand(0).getValueType() == MVT::Other && 421 "Node doesn't have a token chain argument!"); 422 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 423} 424 425/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 426/// see if any uses can reach Dest. If no dest operands can get to dest, 427/// legalize them, legalize ourself, and return false, otherwise, return true. 428/// 429/// Keep track of the nodes we fine that actually do lead to Dest in 430/// NodesLeadingTo. This avoids retraversing them exponential number of times. 431/// 432bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 433 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 434 if (N == Dest) return true; // N certainly leads to Dest :) 435 436 // If we've already processed this node and it does lead to Dest, there is no 437 // need to reprocess it. 438 if (NodesLeadingTo.count(N)) return true; 439 440 // If the first result of this node has been already legalized, then it cannot 441 // reach N. 442 switch (getTypeAction(N->getValueType(0))) { 443 case Legal: 444 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 445 break; 446 case Promote: 447 if (PromotedNodes.count(SDOperand(N, 0))) return false; 448 break; 449 case Expand: 450 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 451 break; 452 } 453 454 // Okay, this node has not already been legalized. Check and legalize all 455 // operands. If none lead to Dest, then we can legalize this node. 456 bool OperandsLeadToDest = false; 457 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 458 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 459 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 460 461 if (OperandsLeadToDest) { 462 NodesLeadingTo.insert(N); 463 return true; 464 } 465 466 // Okay, this node looks safe, legalize it and return false. 467 HandleOp(SDOperand(N, 0)); 468 return false; 469} 470 471/// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 472/// appropriate for its type. 473void SelectionDAGLegalize::HandleOp(SDOperand Op) { 474 switch (getTypeAction(Op.getValueType())) { 475 default: assert(0 && "Bad type action!"); 476 case Legal: LegalizeOp(Op); break; 477 case Promote: PromoteOp(Op); break; 478 case Expand: 479 if (Op.getValueType() != MVT::Vector) { 480 SDOperand X, Y; 481 ExpandOp(Op, X, Y); 482 } else { 483 SDNode *N = Op.Val; 484 unsigned NumOps = N->getNumOperands(); 485 unsigned NumElements = 486 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue(); 487 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT(); 488 MVT::ValueType PackedVT = MVT::getVectorType(EVT, NumElements); 489 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) { 490 // In the common case, this is a legal vector type, convert it to the 491 // packed operation and type now. 492 PackVectorOp(Op, PackedVT); 493 } else if (NumElements == 1) { 494 // Otherwise, if this is a single element vector, convert it to a 495 // scalar operation. 496 PackVectorOp(Op, EVT); 497 } else { 498 // Otherwise, this is a multiple element vector that isn't supported. 499 // Split it in half and legalize both parts. 500 SDOperand X, Y; 501 SplitVectorOp(Op, X, Y); 502 } 503 } 504 break; 505 } 506} 507 508/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 509/// a load from the constant pool. 510static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 511 SelectionDAG &DAG, TargetLowering &TLI) { 512 bool Extend = false; 513 514 // If a FP immediate is precise when represented as a float and if the 515 // target can do an extending load from float to double, we put it into 516 // the constant pool as a float, even if it's is statically typed as a 517 // double. 518 MVT::ValueType VT = CFP->getValueType(0); 519 bool isDouble = VT == MVT::f64; 520 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 521 Type::FloatTy, CFP->getValue()); 522 if (!UseCP) { 523 double Val = LLVMC->getValue(); 524 return isDouble 525 ? DAG.getConstant(DoubleToBits(Val), MVT::i64) 526 : DAG.getConstant(FloatToBits(Val), MVT::i32); 527 } 528 529 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 530 // Only do this if the target has a native EXTLOAD instruction from f32. 531 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 532 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); 533 VT = MVT::f32; 534 Extend = true; 535 } 536 537 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 538 if (Extend) { 539 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 540 CPIdx, NULL, 0, MVT::f32); 541 } else { 542 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 543 } 544} 545 546 547/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 548/// operations. 549static 550SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 551 SelectionDAG &DAG, TargetLowering &TLI) { 552 MVT::ValueType VT = Node->getValueType(0); 553 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 554 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 555 556 // First get the sign bit of second operand. 557 SDOperand Mask1 = (SrcVT == MVT::f64) 558 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 559 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 560 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 561 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 562 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 563 // Shift right or sign-extend it if the two operands have different types. 564 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 565 if (SizeDiff > 0) { 566 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 567 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 568 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 569 } else if (SizeDiff < 0) 570 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 571 572 // Clear the sign bit of first operand. 573 SDOperand Mask2 = (VT == MVT::f64) 574 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 575 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 576 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 577 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 578 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 579 580 // Or the value with the sign bit. 581 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 582 return Result; 583} 584 585 586/// LegalizeOp - We know that the specified value has a legal type. 587/// Recursively ensure that the operands have legal types, then return the 588/// result. 589SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 590 assert(isTypeLegal(Op.getValueType()) && 591 "Caller should expand or promote operands that are not legal!"); 592 SDNode *Node = Op.Val; 593 594 // If this operation defines any values that cannot be represented in a 595 // register on this target, make sure to expand or promote them. 596 if (Node->getNumValues() > 1) { 597 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 598 if (getTypeAction(Node->getValueType(i)) != Legal) { 599 HandleOp(Op.getValue(i)); 600 assert(LegalizedNodes.count(Op) && 601 "Handling didn't add legal operands!"); 602 return LegalizedNodes[Op]; 603 } 604 } 605 606 // Note that LegalizeOp may be reentered even from single-use nodes, which 607 // means that we always must cache transformed nodes. 608 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 609 if (I != LegalizedNodes.end()) return I->second; 610 611 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 612 SDOperand Result = Op; 613 bool isCustom = false; 614 615 switch (Node->getOpcode()) { 616 case ISD::FrameIndex: 617 case ISD::EntryToken: 618 case ISD::Register: 619 case ISD::BasicBlock: 620 case ISD::TargetFrameIndex: 621 case ISD::TargetJumpTable: 622 case ISD::TargetConstant: 623 case ISD::TargetConstantFP: 624 case ISD::TargetConstantPool: 625 case ISD::TargetGlobalAddress: 626 case ISD::TargetGlobalTLSAddress: 627 case ISD::TargetExternalSymbol: 628 case ISD::VALUETYPE: 629 case ISD::SRCVALUE: 630 case ISD::STRING: 631 case ISD::CONDCODE: 632 // Primitives must all be legal. 633 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 634 "This must be legal!"); 635 break; 636 default: 637 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 638 // If this is a target node, legalize it by legalizing the operands then 639 // passing it through. 640 SmallVector<SDOperand, 8> Ops; 641 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 642 Ops.push_back(LegalizeOp(Node->getOperand(i))); 643 644 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 645 646 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 647 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 648 return Result.getValue(Op.ResNo); 649 } 650 // Otherwise this is an unhandled builtin node. splat. 651#ifndef NDEBUG 652 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 653#endif 654 assert(0 && "Do not know how to legalize this operator!"); 655 abort(); 656 case ISD::GLOBAL_OFFSET_TABLE: 657 case ISD::GlobalAddress: 658 case ISD::GlobalTLSAddress: 659 case ISD::ExternalSymbol: 660 case ISD::ConstantPool: 661 case ISD::JumpTable: // Nothing to do. 662 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 663 default: assert(0 && "This action is not supported yet!"); 664 case TargetLowering::Custom: 665 Tmp1 = TLI.LowerOperation(Op, DAG); 666 if (Tmp1.Val) Result = Tmp1; 667 // FALLTHROUGH if the target doesn't want to lower this op after all. 668 case TargetLowering::Legal: 669 break; 670 } 671 break; 672 case ISD::FRAMEADDR: 673 case ISD::RETURNADDR: 674 // The only option for these nodes is to custom lower them. If the target 675 // does not custom lower them, then return zero. 676 Tmp1 = TLI.LowerOperation(Op, DAG); 677 if (Tmp1.Val) 678 Result = Tmp1; 679 else 680 Result = DAG.getConstant(0, TLI.getPointerTy()); 681 break; 682 case ISD::EXCEPTIONADDR: { 683 Tmp1 = LegalizeOp(Node->getOperand(0)); 684 MVT::ValueType VT = Node->getValueType(0); 685 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 686 default: assert(0 && "This action is not supported yet!"); 687 case TargetLowering::Expand: { 688 unsigned Reg = TLI.getExceptionAddressRegister(); 689 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo); 690 } 691 break; 692 case TargetLowering::Custom: 693 Result = TLI.LowerOperation(Op, DAG); 694 if (Result.Val) break; 695 // Fall Thru 696 case TargetLowering::Legal: { 697 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 698 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 699 Ops, 2).getValue(Op.ResNo); 700 break; 701 } 702 } 703 } 704 break; 705 case ISD::EHSELECTION: { 706 Tmp1 = LegalizeOp(Node->getOperand(0)); 707 Tmp2 = LegalizeOp(Node->getOperand(1)); 708 MVT::ValueType VT = Node->getValueType(0); 709 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 710 default: assert(0 && "This action is not supported yet!"); 711 case TargetLowering::Expand: { 712 unsigned Reg = TLI.getExceptionSelectorRegister(); 713 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo); 714 } 715 break; 716 case TargetLowering::Custom: 717 Result = TLI.LowerOperation(Op, DAG); 718 if (Result.Val) break; 719 // Fall Thru 720 case TargetLowering::Legal: { 721 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 722 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 723 Ops, 2).getValue(Op.ResNo); 724 break; 725 } 726 } 727 } 728 break; 729 case ISD::AssertSext: 730 case ISD::AssertZext: 731 Tmp1 = LegalizeOp(Node->getOperand(0)); 732 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 733 break; 734 case ISD::MERGE_VALUES: 735 // Legalize eliminates MERGE_VALUES nodes. 736 Result = Node->getOperand(Op.ResNo); 737 break; 738 case ISD::CopyFromReg: 739 Tmp1 = LegalizeOp(Node->getOperand(0)); 740 Result = Op.getValue(0); 741 if (Node->getNumValues() == 2) { 742 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 743 } else { 744 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 745 if (Node->getNumOperands() == 3) { 746 Tmp2 = LegalizeOp(Node->getOperand(2)); 747 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 748 } else { 749 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 750 } 751 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 752 } 753 // Since CopyFromReg produces two values, make sure to remember that we 754 // legalized both of them. 755 AddLegalizedOperand(Op.getValue(0), Result); 756 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 757 return Result.getValue(Op.ResNo); 758 case ISD::UNDEF: { 759 MVT::ValueType VT = Op.getValueType(); 760 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 761 default: assert(0 && "This action is not supported yet!"); 762 case TargetLowering::Expand: 763 if (MVT::isInteger(VT)) 764 Result = DAG.getConstant(0, VT); 765 else if (MVT::isFloatingPoint(VT)) 766 Result = DAG.getConstantFP(0, VT); 767 else 768 assert(0 && "Unknown value type!"); 769 break; 770 case TargetLowering::Legal: 771 break; 772 } 773 break; 774 } 775 776 case ISD::INTRINSIC_W_CHAIN: 777 case ISD::INTRINSIC_WO_CHAIN: 778 case ISD::INTRINSIC_VOID: { 779 SmallVector<SDOperand, 8> Ops; 780 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 781 Ops.push_back(LegalizeOp(Node->getOperand(i))); 782 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 783 784 // Allow the target to custom lower its intrinsics if it wants to. 785 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 786 TargetLowering::Custom) { 787 Tmp3 = TLI.LowerOperation(Result, DAG); 788 if (Tmp3.Val) Result = Tmp3; 789 } 790 791 if (Result.Val->getNumValues() == 1) break; 792 793 // Must have return value and chain result. 794 assert(Result.Val->getNumValues() == 2 && 795 "Cannot return more than two values!"); 796 797 // Since loads produce two values, make sure to remember that we 798 // legalized both of them. 799 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 800 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 801 return Result.getValue(Op.ResNo); 802 } 803 804 case ISD::LOCATION: 805 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 806 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 807 808 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 809 case TargetLowering::Promote: 810 default: assert(0 && "This action is not supported yet!"); 811 case TargetLowering::Expand: { 812 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 813 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 814 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 815 816 if (MMI && (useDEBUG_LOC || useLABEL)) { 817 const std::string &FName = 818 cast<StringSDNode>(Node->getOperand(3))->getValue(); 819 const std::string &DirName = 820 cast<StringSDNode>(Node->getOperand(4))->getValue(); 821 unsigned SrcFile = MMI->RecordSource(DirName, FName); 822 823 SmallVector<SDOperand, 8> Ops; 824 Ops.push_back(Tmp1); // chain 825 SDOperand LineOp = Node->getOperand(1); 826 SDOperand ColOp = Node->getOperand(2); 827 828 if (useDEBUG_LOC) { 829 Ops.push_back(LineOp); // line # 830 Ops.push_back(ColOp); // col # 831 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 832 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 833 } else { 834 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 835 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 836 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile); 837 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 838 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size()); 839 } 840 } else { 841 Result = Tmp1; // chain 842 } 843 break; 844 } 845 case TargetLowering::Legal: 846 if (Tmp1 != Node->getOperand(0) || 847 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 848 SmallVector<SDOperand, 8> Ops; 849 Ops.push_back(Tmp1); 850 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 851 Ops.push_back(Node->getOperand(1)); // line # must be legal. 852 Ops.push_back(Node->getOperand(2)); // col # must be legal. 853 } else { 854 // Otherwise promote them. 855 Ops.push_back(PromoteOp(Node->getOperand(1))); 856 Ops.push_back(PromoteOp(Node->getOperand(2))); 857 } 858 Ops.push_back(Node->getOperand(3)); // filename must be legal. 859 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 860 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 861 } 862 break; 863 } 864 break; 865 866 case ISD::DEBUG_LOC: 867 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 868 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 869 default: assert(0 && "This action is not supported yet!"); 870 case TargetLowering::Legal: 871 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 872 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 873 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 874 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 875 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 876 break; 877 } 878 break; 879 880 case ISD::LABEL: 881 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!"); 882 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 883 default: assert(0 && "This action is not supported yet!"); 884 case TargetLowering::Legal: 885 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 886 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 887 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 888 break; 889 case TargetLowering::Expand: 890 Result = LegalizeOp(Node->getOperand(0)); 891 break; 892 } 893 break; 894 895 case ISD::Constant: 896 // We know we don't need to expand constants here, constants only have one 897 // value and we check that it is fine above. 898 899 // FIXME: Maybe we should handle things like targets that don't support full 900 // 32-bit immediates? 901 break; 902 case ISD::ConstantFP: { 903 // Spill FP immediates to the constant pool if the target cannot directly 904 // codegen them. Targets often have some immediate values that can be 905 // efficiently generated into an FP register without a load. We explicitly 906 // leave these constants as ConstantFP nodes for the target to deal with. 907 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 908 909 // Check to see if this FP immediate is already legal. 910 bool isLegal = false; 911 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 912 E = TLI.legal_fpimm_end(); I != E; ++I) 913 if (CFP->isExactlyValue(*I)) { 914 isLegal = true; 915 break; 916 } 917 918 // If this is a legal constant, turn it into a TargetConstantFP node. 919 if (isLegal) { 920 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0)); 921 break; 922 } 923 924 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 925 default: assert(0 && "This action is not supported yet!"); 926 case TargetLowering::Custom: 927 Tmp3 = TLI.LowerOperation(Result, DAG); 928 if (Tmp3.Val) { 929 Result = Tmp3; 930 break; 931 } 932 // FALLTHROUGH 933 case TargetLowering::Expand: 934 Result = ExpandConstantFP(CFP, true, DAG, TLI); 935 } 936 break; 937 } 938 case ISD::TokenFactor: 939 if (Node->getNumOperands() == 2) { 940 Tmp1 = LegalizeOp(Node->getOperand(0)); 941 Tmp2 = LegalizeOp(Node->getOperand(1)); 942 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 943 } else if (Node->getNumOperands() == 3) { 944 Tmp1 = LegalizeOp(Node->getOperand(0)); 945 Tmp2 = LegalizeOp(Node->getOperand(1)); 946 Tmp3 = LegalizeOp(Node->getOperand(2)); 947 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 948 } else { 949 SmallVector<SDOperand, 8> Ops; 950 // Legalize the operands. 951 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 952 Ops.push_back(LegalizeOp(Node->getOperand(i))); 953 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 954 } 955 break; 956 957 case ISD::FORMAL_ARGUMENTS: 958 case ISD::CALL: 959 // The only option for this is to custom lower it. 960 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 961 assert(Tmp3.Val && "Target didn't custom lower this node!"); 962 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() && 963 "Lowering call/formal_arguments produced unexpected # results!"); 964 965 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 966 // remember that we legalized all of them, so it doesn't get relegalized. 967 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 968 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 969 if (Op.ResNo == i) 970 Tmp2 = Tmp1; 971 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 972 } 973 return Tmp2; 974 975 case ISD::BUILD_VECTOR: 976 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 977 default: assert(0 && "This action is not supported yet!"); 978 case TargetLowering::Custom: 979 Tmp3 = TLI.LowerOperation(Result, DAG); 980 if (Tmp3.Val) { 981 Result = Tmp3; 982 break; 983 } 984 // FALLTHROUGH 985 case TargetLowering::Expand: 986 Result = ExpandBUILD_VECTOR(Result.Val); 987 break; 988 } 989 break; 990 case ISD::INSERT_VECTOR_ELT: 991 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 992 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 993 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 994 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 995 996 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 997 Node->getValueType(0))) { 998 default: assert(0 && "This action is not supported yet!"); 999 case TargetLowering::Legal: 1000 break; 1001 case TargetLowering::Custom: 1002 Tmp3 = TLI.LowerOperation(Result, DAG); 1003 if (Tmp3.Val) { 1004 Result = Tmp3; 1005 break; 1006 } 1007 // FALLTHROUGH 1008 case TargetLowering::Expand: { 1009 // If the insert index is a constant, codegen this as a scalar_to_vector, 1010 // then a shuffle that inserts it into the right position in the vector. 1011 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1012 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1013 Tmp1.getValueType(), Tmp2); 1014 1015 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1016 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1017 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); 1018 1019 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 1020 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 1021 // the RHS. 1022 SmallVector<SDOperand, 8> ShufOps; 1023 for (unsigned i = 0; i != NumElts; ++i) { 1024 if (i != InsertPos->getValue()) 1025 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1026 else 1027 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1028 } 1029 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1030 &ShufOps[0], ShufOps.size()); 1031 1032 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1033 Tmp1, ScVec, ShufMask); 1034 Result = LegalizeOp(Result); 1035 break; 1036 } 1037 1038 // If the target doesn't support this, we have to spill the input vector 1039 // to a temporary stack slot, update the element, then reload it. This is 1040 // badness. We could also load the value into a vector register (either 1041 // with a "move to register" or "extload into register" instruction, then 1042 // permute it into place, if the idx is a constant and if the idx is 1043 // supported by the target. 1044 MVT::ValueType VT = Tmp1.getValueType(); 1045 MVT::ValueType EltVT = Tmp2.getValueType(); 1046 MVT::ValueType IdxVT = Tmp3.getValueType(); 1047 MVT::ValueType PtrVT = TLI.getPointerTy(); 1048 SDOperand StackPtr = CreateStackTemporary(VT); 1049 // Store the vector. 1050 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); 1051 1052 // Truncate or zero extend offset to target pointer type. 1053 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1054 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 1055 // Add the offset to the index. 1056 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 1057 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 1058 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 1059 // Store the scalar value. 1060 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); 1061 // Load the updated vector. 1062 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); 1063 break; 1064 } 1065 } 1066 break; 1067 case ISD::SCALAR_TO_VECTOR: 1068 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1069 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1070 break; 1071 } 1072 1073 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1074 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1075 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1076 Node->getValueType(0))) { 1077 default: assert(0 && "This action is not supported yet!"); 1078 case TargetLowering::Legal: 1079 break; 1080 case TargetLowering::Custom: 1081 Tmp3 = TLI.LowerOperation(Result, DAG); 1082 if (Tmp3.Val) { 1083 Result = Tmp3; 1084 break; 1085 } 1086 // FALLTHROUGH 1087 case TargetLowering::Expand: 1088 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1089 break; 1090 } 1091 break; 1092 case ISD::VECTOR_SHUFFLE: 1093 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1094 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1095 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1096 1097 // Allow targets to custom lower the SHUFFLEs they support. 1098 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1099 default: assert(0 && "Unknown operation action!"); 1100 case TargetLowering::Legal: 1101 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1102 "vector shuffle should not be created if not legal!"); 1103 break; 1104 case TargetLowering::Custom: 1105 Tmp3 = TLI.LowerOperation(Result, DAG); 1106 if (Tmp3.Val) { 1107 Result = Tmp3; 1108 break; 1109 } 1110 // FALLTHROUGH 1111 case TargetLowering::Expand: { 1112 MVT::ValueType VT = Node->getValueType(0); 1113 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1114 MVT::ValueType PtrVT = TLI.getPointerTy(); 1115 SDOperand Mask = Node->getOperand(2); 1116 unsigned NumElems = Mask.getNumOperands(); 1117 SmallVector<SDOperand,8> Ops; 1118 for (unsigned i = 0; i != NumElems; ++i) { 1119 SDOperand Arg = Mask.getOperand(i); 1120 if (Arg.getOpcode() == ISD::UNDEF) { 1121 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1122 } else { 1123 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1124 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1125 if (Idx < NumElems) 1126 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1127 DAG.getConstant(Idx, PtrVT))); 1128 else 1129 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1130 DAG.getConstant(Idx - NumElems, PtrVT))); 1131 } 1132 } 1133 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1134 break; 1135 } 1136 case TargetLowering::Promote: { 1137 // Change base type to a different vector type. 1138 MVT::ValueType OVT = Node->getValueType(0); 1139 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1140 1141 // Cast the two input vectors. 1142 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1143 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1144 1145 // Convert the shuffle mask to the right # elements. 1146 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1147 assert(Tmp3.Val && "Shuffle not legal?"); 1148 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1149 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1150 break; 1151 } 1152 } 1153 break; 1154 1155 case ISD::EXTRACT_VECTOR_ELT: 1156 Tmp1 = LegalizeOp(Node->getOperand(0)); 1157 Tmp2 = LegalizeOp(Node->getOperand(1)); 1158 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1159 1160 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, 1161 Tmp1.getValueType())) { 1162 default: assert(0 && "This action is not supported yet!"); 1163 case TargetLowering::Legal: 1164 break; 1165 case TargetLowering::Custom: 1166 Tmp3 = TLI.LowerOperation(Result, DAG); 1167 if (Tmp3.Val) { 1168 Result = Tmp3; 1169 break; 1170 } 1171 // FALLTHROUGH 1172 case TargetLowering::Expand: 1173 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1174 break; 1175 } 1176 break; 1177 1178 case ISD::VEXTRACT_VECTOR_ELT: 1179 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op)); 1180 break; 1181 1182 case ISD::VEXTRACT_SUBVECTOR: 1183 Result = LegalizeOp(LowerVEXTRACT_SUBVECTOR(Op)); 1184 break; 1185 1186 case ISD::CALLSEQ_START: { 1187 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1188 1189 // Recursively Legalize all of the inputs of the call end that do not lead 1190 // to this call start. This ensures that any libcalls that need be inserted 1191 // are inserted *before* the CALLSEQ_START. 1192 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1193 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1194 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1195 NodesLeadingTo); 1196 } 1197 1198 // Now that we legalized all of the inputs (which may have inserted 1199 // libcalls) create the new CALLSEQ_START node. 1200 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1201 1202 // Merge in the last call, to ensure that this call start after the last 1203 // call ended. 1204 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1205 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1206 Tmp1 = LegalizeOp(Tmp1); 1207 } 1208 1209 // Do not try to legalize the target-specific arguments (#1+). 1210 if (Tmp1 != Node->getOperand(0)) { 1211 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1212 Ops[0] = Tmp1; 1213 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1214 } 1215 1216 // Remember that the CALLSEQ_START is legalized. 1217 AddLegalizedOperand(Op.getValue(0), Result); 1218 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1219 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1220 1221 // Now that the callseq_start and all of the non-call nodes above this call 1222 // sequence have been legalized, legalize the call itself. During this 1223 // process, no libcalls can/will be inserted, guaranteeing that no calls 1224 // can overlap. 1225 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1226 SDOperand InCallSEQ = LastCALLSEQ_END; 1227 // Note that we are selecting this call! 1228 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1229 IsLegalizingCall = true; 1230 1231 // Legalize the call, starting from the CALLSEQ_END. 1232 LegalizeOp(LastCALLSEQ_END); 1233 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1234 return Result; 1235 } 1236 case ISD::CALLSEQ_END: 1237 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1238 // will cause this node to be legalized as well as handling libcalls right. 1239 if (LastCALLSEQ_END.Val != Node) { 1240 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1241 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1242 assert(I != LegalizedNodes.end() && 1243 "Legalizing the call start should have legalized this node!"); 1244 return I->second; 1245 } 1246 1247 // Otherwise, the call start has been legalized and everything is going 1248 // according to plan. Just legalize ourselves normally here. 1249 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1250 // Do not try to legalize the target-specific arguments (#1+), except for 1251 // an optional flag input. 1252 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1253 if (Tmp1 != Node->getOperand(0)) { 1254 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1255 Ops[0] = Tmp1; 1256 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1257 } 1258 } else { 1259 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1260 if (Tmp1 != Node->getOperand(0) || 1261 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1262 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1263 Ops[0] = Tmp1; 1264 Ops.back() = Tmp2; 1265 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1266 } 1267 } 1268 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1269 // This finishes up call legalization. 1270 IsLegalizingCall = false; 1271 1272 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1273 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1274 if (Node->getNumValues() == 2) 1275 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1276 return Result.getValue(Op.ResNo); 1277 case ISD::DYNAMIC_STACKALLOC: { 1278 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1279 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1280 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1281 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1282 1283 Tmp1 = Result.getValue(0); 1284 Tmp2 = Result.getValue(1); 1285 switch (TLI.getOperationAction(Node->getOpcode(), 1286 Node->getValueType(0))) { 1287 default: assert(0 && "This action is not supported yet!"); 1288 case TargetLowering::Expand: { 1289 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1290 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1291 " not tell us which reg is the stack pointer!"); 1292 SDOperand Chain = Tmp1.getOperand(0); 1293 SDOperand Size = Tmp2.getOperand(1); 1294 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0)); 1295 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value 1296 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain 1297 Tmp1 = LegalizeOp(Tmp1); 1298 Tmp2 = LegalizeOp(Tmp2); 1299 break; 1300 } 1301 case TargetLowering::Custom: 1302 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1303 if (Tmp3.Val) { 1304 Tmp1 = LegalizeOp(Tmp3); 1305 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1306 } 1307 break; 1308 case TargetLowering::Legal: 1309 break; 1310 } 1311 // Since this op produce two values, make sure to remember that we 1312 // legalized both of them. 1313 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1314 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1315 return Op.ResNo ? Tmp2 : Tmp1; 1316 } 1317 case ISD::INLINEASM: { 1318 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1319 bool Changed = false; 1320 // Legalize all of the operands of the inline asm, in case they are nodes 1321 // that need to be expanded or something. Note we skip the asm string and 1322 // all of the TargetConstant flags. 1323 SDOperand Op = LegalizeOp(Ops[0]); 1324 Changed = Op != Ops[0]; 1325 Ops[0] = Op; 1326 1327 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1328 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1329 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1330 for (++i; NumVals; ++i, --NumVals) { 1331 SDOperand Op = LegalizeOp(Ops[i]); 1332 if (Op != Ops[i]) { 1333 Changed = true; 1334 Ops[i] = Op; 1335 } 1336 } 1337 } 1338 1339 if (HasInFlag) { 1340 Op = LegalizeOp(Ops.back()); 1341 Changed |= Op != Ops.back(); 1342 Ops.back() = Op; 1343 } 1344 1345 if (Changed) 1346 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1347 1348 // INLINE asm returns a chain and flag, make sure to add both to the map. 1349 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1350 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1351 return Result.getValue(Op.ResNo); 1352 } 1353 case ISD::BR: 1354 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1355 // Ensure that libcalls are emitted before a branch. 1356 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1357 Tmp1 = LegalizeOp(Tmp1); 1358 LastCALLSEQ_END = DAG.getEntryNode(); 1359 1360 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1361 break; 1362 case ISD::BRIND: 1363 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1364 // Ensure that libcalls are emitted before a branch. 1365 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1366 Tmp1 = LegalizeOp(Tmp1); 1367 LastCALLSEQ_END = DAG.getEntryNode(); 1368 1369 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1370 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1371 case Legal: 1372 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1373 break; 1374 } 1375 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1376 break; 1377 case ISD::BR_JT: 1378 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1379 // Ensure that libcalls are emitted before a branch. 1380 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1381 Tmp1 = LegalizeOp(Tmp1); 1382 LastCALLSEQ_END = DAG.getEntryNode(); 1383 1384 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1385 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1386 1387 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1388 default: assert(0 && "This action is not supported yet!"); 1389 case TargetLowering::Legal: break; 1390 case TargetLowering::Custom: 1391 Tmp1 = TLI.LowerOperation(Result, DAG); 1392 if (Tmp1.Val) Result = Tmp1; 1393 break; 1394 case TargetLowering::Expand: { 1395 SDOperand Chain = Result.getOperand(0); 1396 SDOperand Table = Result.getOperand(1); 1397 SDOperand Index = Result.getOperand(2); 1398 1399 MVT::ValueType PTy = TLI.getPointerTy(); 1400 MachineFunction &MF = DAG.getMachineFunction(); 1401 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1402 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1403 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1404 1405 SDOperand LD; 1406 switch (EntrySize) { 1407 default: assert(0 && "Size of jump table not supported yet."); break; 1408 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; 1409 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; 1410 } 1411 1412 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1413 // For PIC, the sequence is: 1414 // BRIND(load(Jumptable + index) + RelocBase) 1415 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha 1416 SDOperand Reloc; 1417 if (TLI.usesGlobalOffsetTable()) 1418 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy); 1419 else 1420 Reloc = Table; 1421 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD; 1422 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc); 1423 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1424 } else { 1425 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD); 1426 } 1427 } 1428 } 1429 break; 1430 case ISD::BRCOND: 1431 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1432 // Ensure that libcalls are emitted before a return. 1433 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1434 Tmp1 = LegalizeOp(Tmp1); 1435 LastCALLSEQ_END = DAG.getEntryNode(); 1436 1437 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1438 case Expand: assert(0 && "It's impossible to expand bools"); 1439 case Legal: 1440 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1441 break; 1442 case Promote: 1443 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1444 1445 // The top bits of the promoted condition are not necessarily zero, ensure 1446 // that the value is properly zero extended. 1447 if (!TLI.MaskedValueIsZero(Tmp2, 1448 MVT::getIntVTBitMask(Tmp2.getValueType())^1)) 1449 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1450 break; 1451 } 1452 1453 // Basic block destination (Op#2) is always legal. 1454 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1455 1456 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1457 default: assert(0 && "This action is not supported yet!"); 1458 case TargetLowering::Legal: break; 1459 case TargetLowering::Custom: 1460 Tmp1 = TLI.LowerOperation(Result, DAG); 1461 if (Tmp1.Val) Result = Tmp1; 1462 break; 1463 case TargetLowering::Expand: 1464 // Expand brcond's setcc into its constituent parts and create a BR_CC 1465 // Node. 1466 if (Tmp2.getOpcode() == ISD::SETCC) { 1467 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1468 Tmp2.getOperand(0), Tmp2.getOperand(1), 1469 Node->getOperand(2)); 1470 } else { 1471 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1472 DAG.getCondCode(ISD::SETNE), Tmp2, 1473 DAG.getConstant(0, Tmp2.getValueType()), 1474 Node->getOperand(2)); 1475 } 1476 break; 1477 } 1478 break; 1479 case ISD::BR_CC: 1480 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1481 // Ensure that libcalls are emitted before a branch. 1482 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1483 Tmp1 = LegalizeOp(Tmp1); 1484 Tmp2 = Node->getOperand(2); // LHS 1485 Tmp3 = Node->getOperand(3); // RHS 1486 Tmp4 = Node->getOperand(1); // CC 1487 1488 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1489 LastCALLSEQ_END = DAG.getEntryNode(); 1490 1491 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1492 // the LHS is a legal SETCC itself. In this case, we need to compare 1493 // the result against zero to select between true and false values. 1494 if (Tmp3.Val == 0) { 1495 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1496 Tmp4 = DAG.getCondCode(ISD::SETNE); 1497 } 1498 1499 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1500 Node->getOperand(4)); 1501 1502 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1503 default: assert(0 && "Unexpected action for BR_CC!"); 1504 case TargetLowering::Legal: break; 1505 case TargetLowering::Custom: 1506 Tmp4 = TLI.LowerOperation(Result, DAG); 1507 if (Tmp4.Val) Result = Tmp4; 1508 break; 1509 } 1510 break; 1511 case ISD::LOAD: { 1512 LoadSDNode *LD = cast<LoadSDNode>(Node); 1513 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1514 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1515 1516 ISD::LoadExtType ExtType = LD->getExtensionType(); 1517 if (ExtType == ISD::NON_EXTLOAD) { 1518 MVT::ValueType VT = Node->getValueType(0); 1519 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1520 Tmp3 = Result.getValue(0); 1521 Tmp4 = Result.getValue(1); 1522 1523 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1524 default: assert(0 && "This action is not supported yet!"); 1525 case TargetLowering::Legal: break; 1526 case TargetLowering::Custom: 1527 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1528 if (Tmp1.Val) { 1529 Tmp3 = LegalizeOp(Tmp1); 1530 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1531 } 1532 break; 1533 case TargetLowering::Promote: { 1534 // Only promote a load of vector type to another. 1535 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1536 // Change base type to a different vector type. 1537 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1538 1539 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1540 LD->getSrcValueOffset()); 1541 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1542 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1543 break; 1544 } 1545 } 1546 // Since loads produce two values, make sure to remember that we 1547 // legalized both of them. 1548 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1549 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1550 return Op.ResNo ? Tmp4 : Tmp3; 1551 } else { 1552 MVT::ValueType SrcVT = LD->getLoadedVT(); 1553 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1554 default: assert(0 && "This action is not supported yet!"); 1555 case TargetLowering::Promote: 1556 assert(SrcVT == MVT::i1 && 1557 "Can only promote extending LOAD from i1 -> i8!"); 1558 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1559 LD->getSrcValue(), LD->getSrcValueOffset(), 1560 MVT::i8); 1561 Tmp1 = Result.getValue(0); 1562 Tmp2 = Result.getValue(1); 1563 break; 1564 case TargetLowering::Custom: 1565 isCustom = true; 1566 // FALLTHROUGH 1567 case TargetLowering::Legal: 1568 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1569 Tmp1 = Result.getValue(0); 1570 Tmp2 = Result.getValue(1); 1571 1572 if (isCustom) { 1573 Tmp3 = TLI.LowerOperation(Result, DAG); 1574 if (Tmp3.Val) { 1575 Tmp1 = LegalizeOp(Tmp3); 1576 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1577 } 1578 } 1579 break; 1580 case TargetLowering::Expand: 1581 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1582 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1583 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 1584 LD->getSrcValueOffset()); 1585 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1586 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1587 Tmp2 = LegalizeOp(Load.getValue(1)); 1588 break; 1589 } 1590 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1591 // Turn the unsupported load into an EXTLOAD followed by an explicit 1592 // zero/sign extend inreg. 1593 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1594 Tmp1, Tmp2, LD->getSrcValue(), 1595 LD->getSrcValueOffset(), SrcVT); 1596 SDOperand ValRes; 1597 if (ExtType == ISD::SEXTLOAD) 1598 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1599 Result, DAG.getValueType(SrcVT)); 1600 else 1601 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1602 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1603 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1604 break; 1605 } 1606 // Since loads produce two values, make sure to remember that we legalized 1607 // both of them. 1608 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1609 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1610 return Op.ResNo ? Tmp2 : Tmp1; 1611 } 1612 } 1613 case ISD::EXTRACT_ELEMENT: { 1614 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1615 switch (getTypeAction(OpTy)) { 1616 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1617 case Legal: 1618 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1619 // 1 -> Hi 1620 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1621 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1622 TLI.getShiftAmountTy())); 1623 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1624 } else { 1625 // 0 -> Lo 1626 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1627 Node->getOperand(0)); 1628 } 1629 break; 1630 case Expand: 1631 // Get both the low and high parts. 1632 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1633 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1634 Result = Tmp2; // 1 -> Hi 1635 else 1636 Result = Tmp1; // 0 -> Lo 1637 break; 1638 } 1639 break; 1640 } 1641 1642 case ISD::CopyToReg: 1643 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1644 1645 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1646 "Register type must be legal!"); 1647 // Legalize the incoming value (must be a legal type). 1648 Tmp2 = LegalizeOp(Node->getOperand(2)); 1649 if (Node->getNumValues() == 1) { 1650 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1651 } else { 1652 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1653 if (Node->getNumOperands() == 4) { 1654 Tmp3 = LegalizeOp(Node->getOperand(3)); 1655 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1656 Tmp3); 1657 } else { 1658 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1659 } 1660 1661 // Since this produces two values, make sure to remember that we legalized 1662 // both of them. 1663 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1664 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1665 return Result; 1666 } 1667 break; 1668 1669 case ISD::RET: 1670 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1671 1672 // Ensure that libcalls are emitted before a return. 1673 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1674 Tmp1 = LegalizeOp(Tmp1); 1675 LastCALLSEQ_END = DAG.getEntryNode(); 1676 1677 switch (Node->getNumOperands()) { 1678 case 3: // ret val 1679 Tmp2 = Node->getOperand(1); 1680 Tmp3 = Node->getOperand(2); // Signness 1681 switch (getTypeAction(Tmp2.getValueType())) { 1682 case Legal: 1683 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1684 break; 1685 case Expand: 1686 if (Tmp2.getValueType() != MVT::Vector) { 1687 SDOperand Lo, Hi; 1688 ExpandOp(Tmp2, Lo, Hi); 1689 1690 // Big endian systems want the hi reg first. 1691 if (!TLI.isLittleEndian()) 1692 std::swap(Lo, Hi); 1693 1694 if (Hi.Val) 1695 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1696 else 1697 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 1698 Result = LegalizeOp(Result); 1699 } else { 1700 SDNode *InVal = Tmp2.Val; 1701 unsigned NumElems = 1702 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 1703 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 1704 1705 // Figure out if there is a Packed type corresponding to this Vector 1706 // type. If so, convert to the vector type. 1707 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1708 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 1709 // Turn this into a return of the vector type. 1710 Tmp2 = PackVectorOp(Tmp2, TVT); 1711 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1712 } else if (NumElems == 1) { 1713 // Turn this into a return of the scalar type. 1714 Tmp2 = PackVectorOp(Tmp2, EVT); 1715 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1716 1717 // FIXME: Returns of gcc generic vectors smaller than a legal type 1718 // should be returned in integer registers! 1719 1720 // The scalarized value type may not be legal, e.g. it might require 1721 // promotion or expansion. Relegalize the return. 1722 Result = LegalizeOp(Result); 1723 } else { 1724 // FIXME: Returns of gcc generic vectors larger than a legal vector 1725 // type should be returned by reference! 1726 SDOperand Lo, Hi; 1727 SplitVectorOp(Tmp2, Lo, Hi); 1728 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1729 Result = LegalizeOp(Result); 1730 } 1731 } 1732 break; 1733 case Promote: 1734 Tmp2 = PromoteOp(Node->getOperand(1)); 1735 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1736 Result = LegalizeOp(Result); 1737 break; 1738 } 1739 break; 1740 case 1: // ret void 1741 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1742 break; 1743 default: { // ret <values> 1744 SmallVector<SDOperand, 8> NewValues; 1745 NewValues.push_back(Tmp1); 1746 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 1747 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1748 case Legal: 1749 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1750 NewValues.push_back(Node->getOperand(i+1)); 1751 break; 1752 case Expand: { 1753 SDOperand Lo, Hi; 1754 assert(Node->getOperand(i).getValueType() != MVT::Vector && 1755 "FIXME: TODO: implement returning non-legal vector types!"); 1756 ExpandOp(Node->getOperand(i), Lo, Hi); 1757 NewValues.push_back(Lo); 1758 NewValues.push_back(Node->getOperand(i+1)); 1759 if (Hi.Val) { 1760 NewValues.push_back(Hi); 1761 NewValues.push_back(Node->getOperand(i+1)); 1762 } 1763 break; 1764 } 1765 case Promote: 1766 assert(0 && "Can't promote multiple return value yet!"); 1767 } 1768 1769 if (NewValues.size() == Node->getNumOperands()) 1770 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 1771 else 1772 Result = DAG.getNode(ISD::RET, MVT::Other, 1773 &NewValues[0], NewValues.size()); 1774 break; 1775 } 1776 } 1777 1778 if (Result.getOpcode() == ISD::RET) { 1779 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 1780 default: assert(0 && "This action is not supported yet!"); 1781 case TargetLowering::Legal: break; 1782 case TargetLowering::Custom: 1783 Tmp1 = TLI.LowerOperation(Result, DAG); 1784 if (Tmp1.Val) Result = Tmp1; 1785 break; 1786 } 1787 } 1788 break; 1789 case ISD::STORE: { 1790 StoreSDNode *ST = cast<StoreSDNode>(Node); 1791 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1792 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1793 1794 if (!ST->isTruncatingStore()) { 1795 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1796 // FIXME: We shouldn't do this for TargetConstantFP's. 1797 // FIXME: move this to the DAG Combiner! Note that we can't regress due 1798 // to phase ordering between legalized code and the dag combiner. This 1799 // probably means that we need to integrate dag combiner and legalizer 1800 // together. 1801 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 1802 if (CFP->getValueType(0) == MVT::f32) { 1803 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 1804 } else { 1805 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1806 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 1807 } 1808 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1809 ST->getSrcValueOffset()); 1810 break; 1811 } 1812 1813 switch (getTypeAction(ST->getStoredVT())) { 1814 case Legal: { 1815 Tmp3 = LegalizeOp(ST->getValue()); 1816 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1817 ST->getOffset()); 1818 1819 MVT::ValueType VT = Tmp3.getValueType(); 1820 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1821 default: assert(0 && "This action is not supported yet!"); 1822 case TargetLowering::Legal: break; 1823 case TargetLowering::Custom: 1824 Tmp1 = TLI.LowerOperation(Result, DAG); 1825 if (Tmp1.Val) Result = Tmp1; 1826 break; 1827 case TargetLowering::Promote: 1828 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 1829 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 1830 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1831 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 1832 ST->getSrcValue(), ST->getSrcValueOffset()); 1833 break; 1834 } 1835 break; 1836 } 1837 case Promote: 1838 // Truncate the value and store the result. 1839 Tmp3 = PromoteOp(ST->getValue()); 1840 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1841 ST->getSrcValueOffset(), ST->getStoredVT()); 1842 break; 1843 1844 case Expand: 1845 unsigned IncrementSize = 0; 1846 SDOperand Lo, Hi; 1847 1848 // If this is a vector type, then we have to calculate the increment as 1849 // the product of the element size in bytes, and the number of elements 1850 // in the high half of the vector. 1851 if (ST->getValue().getValueType() == MVT::Vector) { 1852 SDNode *InVal = ST->getValue().Val; 1853 unsigned NumElems = 1854 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 1855 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 1856 1857 // Figure out if there is a Packed type corresponding to this Vector 1858 // type. If so, convert to the vector type. 1859 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1860 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 1861 // Turn this into a normal store of the vector type. 1862 Tmp3 = PackVectorOp(Node->getOperand(1), TVT); 1863 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1864 ST->getSrcValueOffset()); 1865 Result = LegalizeOp(Result); 1866 break; 1867 } else if (NumElems == 1) { 1868 // Turn this into a normal store of the scalar type. 1869 Tmp3 = PackVectorOp(Node->getOperand(1), EVT); 1870 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1871 ST->getSrcValueOffset()); 1872 // The scalarized value type may not be legal, e.g. it might require 1873 // promotion or expansion. Relegalize the scalar store. 1874 Result = LegalizeOp(Result); 1875 break; 1876 } else { 1877 SplitVectorOp(Node->getOperand(1), Lo, Hi); 1878 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; 1879 } 1880 } else { 1881 ExpandOp(Node->getOperand(1), Lo, Hi); 1882 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 1883 1884 if (!TLI.isLittleEndian()) 1885 std::swap(Lo, Hi); 1886 } 1887 1888 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 1889 ST->getSrcValueOffset(), ST->isVolatile(), 1890 ST->getAlignment()); 1891 1892 if (Hi.Val == NULL) { 1893 // Must be int <-> float one-to-one expansion. 1894 Result = Lo; 1895 break; 1896 } 1897 1898 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1899 getIntPtrConstant(IncrementSize)); 1900 assert(isTypeLegal(Tmp2.getValueType()) && 1901 "Pointers must be legal!"); 1902 // FIXME: This sets the srcvalue of both halves to be the same, which is 1903 // wrong. 1904 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 1905 ST->getSrcValueOffset(), ST->isVolatile(), 1906 std::min(ST->getAlignment(), IncrementSize)); 1907 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1908 break; 1909 } 1910 } else { 1911 // Truncating store 1912 assert(isTypeLegal(ST->getValue().getValueType()) && 1913 "Cannot handle illegal TRUNCSTORE yet!"); 1914 Tmp3 = LegalizeOp(ST->getValue()); 1915 1916 // The only promote case we handle is TRUNCSTORE:i1 X into 1917 // -> TRUNCSTORE:i8 (and X, 1) 1918 if (ST->getStoredVT() == MVT::i1 && 1919 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) { 1920 // Promote the bool to a mask then store. 1921 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3, 1922 DAG.getConstant(1, Tmp3.getValueType())); 1923 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1924 ST->getSrcValueOffset(), MVT::i8); 1925 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1926 Tmp2 != ST->getBasePtr()) { 1927 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1928 ST->getOffset()); 1929 } 1930 1931 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT(); 1932 switch (TLI.getStoreXAction(StVT)) { 1933 default: assert(0 && "This action is not supported yet!"); 1934 case TargetLowering::Legal: break; 1935 case TargetLowering::Custom: 1936 Tmp1 = TLI.LowerOperation(Result, DAG); 1937 if (Tmp1.Val) Result = Tmp1; 1938 break; 1939 } 1940 } 1941 break; 1942 } 1943 case ISD::PCMARKER: 1944 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1945 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1946 break; 1947 case ISD::STACKSAVE: 1948 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1949 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1950 Tmp1 = Result.getValue(0); 1951 Tmp2 = Result.getValue(1); 1952 1953 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 1954 default: assert(0 && "This action is not supported yet!"); 1955 case TargetLowering::Legal: break; 1956 case TargetLowering::Custom: 1957 Tmp3 = TLI.LowerOperation(Result, DAG); 1958 if (Tmp3.Val) { 1959 Tmp1 = LegalizeOp(Tmp3); 1960 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1961 } 1962 break; 1963 case TargetLowering::Expand: 1964 // Expand to CopyFromReg if the target set 1965 // StackPointerRegisterToSaveRestore. 1966 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1967 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 1968 Node->getValueType(0)); 1969 Tmp2 = Tmp1.getValue(1); 1970 } else { 1971 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 1972 Tmp2 = Node->getOperand(0); 1973 } 1974 break; 1975 } 1976 1977 // Since stacksave produce two values, make sure to remember that we 1978 // legalized both of them. 1979 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1980 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1981 return Op.ResNo ? Tmp2 : Tmp1; 1982 1983 case ISD::STACKRESTORE: 1984 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1985 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1986 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1987 1988 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 1989 default: assert(0 && "This action is not supported yet!"); 1990 case TargetLowering::Legal: break; 1991 case TargetLowering::Custom: 1992 Tmp1 = TLI.LowerOperation(Result, DAG); 1993 if (Tmp1.Val) Result = Tmp1; 1994 break; 1995 case TargetLowering::Expand: 1996 // Expand to CopyToReg if the target set 1997 // StackPointerRegisterToSaveRestore. 1998 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1999 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2000 } else { 2001 Result = Tmp1; 2002 } 2003 break; 2004 } 2005 break; 2006 2007 case ISD::READCYCLECOUNTER: 2008 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2009 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2010 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2011 Node->getValueType(0))) { 2012 default: assert(0 && "This action is not supported yet!"); 2013 case TargetLowering::Legal: 2014 Tmp1 = Result.getValue(0); 2015 Tmp2 = Result.getValue(1); 2016 break; 2017 case TargetLowering::Custom: 2018 Result = TLI.LowerOperation(Result, DAG); 2019 Tmp1 = LegalizeOp(Result.getValue(0)); 2020 Tmp2 = LegalizeOp(Result.getValue(1)); 2021 break; 2022 } 2023 2024 // Since rdcc produce two values, make sure to remember that we legalized 2025 // both of them. 2026 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2027 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2028 return Result; 2029 2030 case ISD::SELECT: 2031 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2032 case Expand: assert(0 && "It's impossible to expand bools"); 2033 case Legal: 2034 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2035 break; 2036 case Promote: 2037 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2038 // Make sure the condition is either zero or one. 2039 if (!TLI.MaskedValueIsZero(Tmp1, 2040 MVT::getIntVTBitMask(Tmp1.getValueType())^1)) 2041 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2042 break; 2043 } 2044 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2045 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2046 2047 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2048 2049 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2050 default: assert(0 && "This action is not supported yet!"); 2051 case TargetLowering::Legal: break; 2052 case TargetLowering::Custom: { 2053 Tmp1 = TLI.LowerOperation(Result, DAG); 2054 if (Tmp1.Val) Result = Tmp1; 2055 break; 2056 } 2057 case TargetLowering::Expand: 2058 if (Tmp1.getOpcode() == ISD::SETCC) { 2059 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2060 Tmp2, Tmp3, 2061 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2062 } else { 2063 Result = DAG.getSelectCC(Tmp1, 2064 DAG.getConstant(0, Tmp1.getValueType()), 2065 Tmp2, Tmp3, ISD::SETNE); 2066 } 2067 break; 2068 case TargetLowering::Promote: { 2069 MVT::ValueType NVT = 2070 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2071 unsigned ExtOp, TruncOp; 2072 if (MVT::isVector(Tmp2.getValueType())) { 2073 ExtOp = ISD::BIT_CONVERT; 2074 TruncOp = ISD::BIT_CONVERT; 2075 } else if (MVT::isInteger(Tmp2.getValueType())) { 2076 ExtOp = ISD::ANY_EXTEND; 2077 TruncOp = ISD::TRUNCATE; 2078 } else { 2079 ExtOp = ISD::FP_EXTEND; 2080 TruncOp = ISD::FP_ROUND; 2081 } 2082 // Promote each of the values to the new type. 2083 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2084 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2085 // Perform the larger operation, then round down. 2086 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2087 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2088 break; 2089 } 2090 } 2091 break; 2092 case ISD::SELECT_CC: { 2093 Tmp1 = Node->getOperand(0); // LHS 2094 Tmp2 = Node->getOperand(1); // RHS 2095 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2096 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2097 SDOperand CC = Node->getOperand(4); 2098 2099 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2100 2101 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2102 // the LHS is a legal SETCC itself. In this case, we need to compare 2103 // the result against zero to select between true and false values. 2104 if (Tmp2.Val == 0) { 2105 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2106 CC = DAG.getCondCode(ISD::SETNE); 2107 } 2108 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2109 2110 // Everything is legal, see if we should expand this op or something. 2111 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2112 default: assert(0 && "This action is not supported yet!"); 2113 case TargetLowering::Legal: break; 2114 case TargetLowering::Custom: 2115 Tmp1 = TLI.LowerOperation(Result, DAG); 2116 if (Tmp1.Val) Result = Tmp1; 2117 break; 2118 } 2119 break; 2120 } 2121 case ISD::SETCC: 2122 Tmp1 = Node->getOperand(0); 2123 Tmp2 = Node->getOperand(1); 2124 Tmp3 = Node->getOperand(2); 2125 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2126 2127 // If we had to Expand the SetCC operands into a SELECT node, then it may 2128 // not always be possible to return a true LHS & RHS. In this case, just 2129 // return the value we legalized, returned in the LHS 2130 if (Tmp2.Val == 0) { 2131 Result = Tmp1; 2132 break; 2133 } 2134 2135 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2136 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2137 case TargetLowering::Custom: 2138 isCustom = true; 2139 // FALLTHROUGH. 2140 case TargetLowering::Legal: 2141 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2142 if (isCustom) { 2143 Tmp4 = TLI.LowerOperation(Result, DAG); 2144 if (Tmp4.Val) Result = Tmp4; 2145 } 2146 break; 2147 case TargetLowering::Promote: { 2148 // First step, figure out the appropriate operation to use. 2149 // Allow SETCC to not be supported for all legal data types 2150 // Mostly this targets FP 2151 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2152 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2153 2154 // Scan for the appropriate larger type to use. 2155 while (1) { 2156 NewInTy = (MVT::ValueType)(NewInTy+1); 2157 2158 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2159 "Fell off of the edge of the integer world"); 2160 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2161 "Fell off of the edge of the floating point world"); 2162 2163 // If the target supports SETCC of this type, use it. 2164 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2165 break; 2166 } 2167 if (MVT::isInteger(NewInTy)) 2168 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2169 else { 2170 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2171 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2172 } 2173 Tmp1 = LegalizeOp(Tmp1); 2174 Tmp2 = LegalizeOp(Tmp2); 2175 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2176 Result = LegalizeOp(Result); 2177 break; 2178 } 2179 case TargetLowering::Expand: 2180 // Expand a setcc node into a select_cc of the same condition, lhs, and 2181 // rhs that selects between const 1 (true) and const 0 (false). 2182 MVT::ValueType VT = Node->getValueType(0); 2183 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2184 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2185 Tmp3); 2186 break; 2187 } 2188 break; 2189 case ISD::MEMSET: 2190 case ISD::MEMCPY: 2191 case ISD::MEMMOVE: { 2192 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2193 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2194 2195 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2196 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2197 case Expand: assert(0 && "Cannot expand a byte!"); 2198 case Legal: 2199 Tmp3 = LegalizeOp(Node->getOperand(2)); 2200 break; 2201 case Promote: 2202 Tmp3 = PromoteOp(Node->getOperand(2)); 2203 break; 2204 } 2205 } else { 2206 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2207 } 2208 2209 SDOperand Tmp4; 2210 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2211 case Expand: { 2212 // Length is too big, just take the lo-part of the length. 2213 SDOperand HiPart; 2214 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2215 break; 2216 } 2217 case Legal: 2218 Tmp4 = LegalizeOp(Node->getOperand(3)); 2219 break; 2220 case Promote: 2221 Tmp4 = PromoteOp(Node->getOperand(3)); 2222 break; 2223 } 2224 2225 SDOperand Tmp5; 2226 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2227 case Expand: assert(0 && "Cannot expand this yet!"); 2228 case Legal: 2229 Tmp5 = LegalizeOp(Node->getOperand(4)); 2230 break; 2231 case Promote: 2232 Tmp5 = PromoteOp(Node->getOperand(4)); 2233 break; 2234 } 2235 2236 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2237 default: assert(0 && "This action not implemented for this operation!"); 2238 case TargetLowering::Custom: 2239 isCustom = true; 2240 // FALLTHROUGH 2241 case TargetLowering::Legal: 2242 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 2243 if (isCustom) { 2244 Tmp1 = TLI.LowerOperation(Result, DAG); 2245 if (Tmp1.Val) Result = Tmp1; 2246 } 2247 break; 2248 case TargetLowering::Expand: { 2249 // Otherwise, the target does not support this operation. Lower the 2250 // operation to an explicit libcall as appropriate. 2251 MVT::ValueType IntPtr = TLI.getPointerTy(); 2252 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2253 TargetLowering::ArgListTy Args; 2254 TargetLowering::ArgListEntry Entry; 2255 2256 const char *FnName = 0; 2257 if (Node->getOpcode() == ISD::MEMSET) { 2258 Entry.Node = Tmp2; Entry.Ty = IntPtrTy; 2259 Args.push_back(Entry); 2260 // Extend the (previously legalized) ubyte argument to be an int value 2261 // for the call. 2262 if (Tmp3.getValueType() > MVT::i32) 2263 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2264 else 2265 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2266 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 2267 Args.push_back(Entry); 2268 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false; 2269 Args.push_back(Entry); 2270 2271 FnName = "memset"; 2272 } else if (Node->getOpcode() == ISD::MEMCPY || 2273 Node->getOpcode() == ISD::MEMMOVE) { 2274 Entry.Ty = IntPtrTy; 2275 Entry.Node = Tmp2; Args.push_back(Entry); 2276 Entry.Node = Tmp3; Args.push_back(Entry); 2277 Entry.Node = Tmp4; Args.push_back(Entry); 2278 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2279 } else { 2280 assert(0 && "Unknown op!"); 2281 } 2282 2283 std::pair<SDOperand,SDOperand> CallResult = 2284 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 2285 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2286 Result = CallResult.second; 2287 break; 2288 } 2289 } 2290 break; 2291 } 2292 2293 case ISD::SHL_PARTS: 2294 case ISD::SRA_PARTS: 2295 case ISD::SRL_PARTS: { 2296 SmallVector<SDOperand, 8> Ops; 2297 bool Changed = false; 2298 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2299 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2300 Changed |= Ops.back() != Node->getOperand(i); 2301 } 2302 if (Changed) 2303 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2304 2305 switch (TLI.getOperationAction(Node->getOpcode(), 2306 Node->getValueType(0))) { 2307 default: assert(0 && "This action is not supported yet!"); 2308 case TargetLowering::Legal: break; 2309 case TargetLowering::Custom: 2310 Tmp1 = TLI.LowerOperation(Result, DAG); 2311 if (Tmp1.Val) { 2312 SDOperand Tmp2, RetVal(0, 0); 2313 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2314 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2315 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2316 if (i == Op.ResNo) 2317 RetVal = Tmp2; 2318 } 2319 assert(RetVal.Val && "Illegal result number"); 2320 return RetVal; 2321 } 2322 break; 2323 } 2324 2325 // Since these produce multiple values, make sure to remember that we 2326 // legalized all of them. 2327 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2328 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2329 return Result.getValue(Op.ResNo); 2330 } 2331 2332 // Binary operators 2333 case ISD::ADD: 2334 case ISD::SUB: 2335 case ISD::MUL: 2336 case ISD::MULHS: 2337 case ISD::MULHU: 2338 case ISD::UDIV: 2339 case ISD::SDIV: 2340 case ISD::AND: 2341 case ISD::OR: 2342 case ISD::XOR: 2343 case ISD::SHL: 2344 case ISD::SRL: 2345 case ISD::SRA: 2346 case ISD::FADD: 2347 case ISD::FSUB: 2348 case ISD::FMUL: 2349 case ISD::FDIV: 2350 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2351 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2352 case Expand: assert(0 && "Not possible"); 2353 case Legal: 2354 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2355 break; 2356 case Promote: 2357 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2358 break; 2359 } 2360 2361 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2362 2363 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2364 default: assert(0 && "BinOp legalize operation not supported"); 2365 case TargetLowering::Legal: break; 2366 case TargetLowering::Custom: 2367 Tmp1 = TLI.LowerOperation(Result, DAG); 2368 if (Tmp1.Val) Result = Tmp1; 2369 break; 2370 case TargetLowering::Expand: { 2371 if (Node->getValueType(0) == MVT::i32) { 2372 switch (Node->getOpcode()) { 2373 default: assert(0 && "Do not know how to expand this integer BinOp!"); 2374 case ISD::UDIV: 2375 case ISD::SDIV: 2376 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV 2377 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 2378 SDOperand Dummy; 2379 bool isSigned = Node->getOpcode() == ISD::SDIV; 2380 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2381 }; 2382 break; 2383 } 2384 2385 assert(MVT::isVector(Node->getValueType(0)) && 2386 "Cannot expand this binary operator!"); 2387 // Expand the operation into a bunch of nasty scalar code. 2388 SmallVector<SDOperand, 8> Ops; 2389 MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0)); 2390 MVT::ValueType PtrVT = TLI.getPointerTy(); 2391 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0)); 2392 i != e; ++i) { 2393 SDOperand Idx = DAG.getConstant(i, PtrVT); 2394 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx); 2395 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx); 2396 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS)); 2397 } 2398 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), 2399 &Ops[0], Ops.size()); 2400 break; 2401 } 2402 case TargetLowering::Promote: { 2403 switch (Node->getOpcode()) { 2404 default: assert(0 && "Do not know how to promote this BinOp!"); 2405 case ISD::AND: 2406 case ISD::OR: 2407 case ISD::XOR: { 2408 MVT::ValueType OVT = Node->getValueType(0); 2409 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2410 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2411 // Bit convert each of the values to the new type. 2412 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2413 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2414 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2415 // Bit convert the result back the original type. 2416 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2417 break; 2418 } 2419 } 2420 } 2421 } 2422 break; 2423 2424 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2425 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2426 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2427 case Expand: assert(0 && "Not possible"); 2428 case Legal: 2429 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2430 break; 2431 case Promote: 2432 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2433 break; 2434 } 2435 2436 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2437 2438 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2439 default: assert(0 && "Operation not supported"); 2440 case TargetLowering::Custom: 2441 Tmp1 = TLI.LowerOperation(Result, DAG); 2442 if (Tmp1.Val) Result = Tmp1; 2443 break; 2444 case TargetLowering::Legal: break; 2445 case TargetLowering::Expand: { 2446 // If this target supports fabs/fneg natively and select is cheap, 2447 // do this efficiently. 2448 if (!TLI.isSelectExpensive() && 2449 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 2450 TargetLowering::Legal && 2451 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 2452 TargetLowering::Legal) { 2453 // Get the sign bit of the RHS. 2454 MVT::ValueType IVT = 2455 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2456 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2457 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2458 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2459 // Get the absolute value of the result. 2460 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2461 // Select between the nabs and abs value based on the sign bit of 2462 // the input. 2463 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2464 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2465 AbsVal), 2466 AbsVal); 2467 Result = LegalizeOp(Result); 2468 break; 2469 } 2470 2471 // Otherwise, do bitwise ops! 2472 MVT::ValueType NVT = 2473 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 2474 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 2475 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 2476 Result = LegalizeOp(Result); 2477 break; 2478 } 2479 } 2480 break; 2481 2482 case ISD::ADDC: 2483 case ISD::SUBC: 2484 Tmp1 = LegalizeOp(Node->getOperand(0)); 2485 Tmp2 = LegalizeOp(Node->getOperand(1)); 2486 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2487 // Since this produces two values, make sure to remember that we legalized 2488 // both of them. 2489 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2490 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2491 return Result; 2492 2493 case ISD::ADDE: 2494 case ISD::SUBE: 2495 Tmp1 = LegalizeOp(Node->getOperand(0)); 2496 Tmp2 = LegalizeOp(Node->getOperand(1)); 2497 Tmp3 = LegalizeOp(Node->getOperand(2)); 2498 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2499 // Since this produces two values, make sure to remember that we legalized 2500 // both of them. 2501 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2502 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2503 return Result; 2504 2505 case ISD::BUILD_PAIR: { 2506 MVT::ValueType PairTy = Node->getValueType(0); 2507 // TODO: handle the case where the Lo and Hi operands are not of legal type 2508 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2509 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2510 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2511 case TargetLowering::Promote: 2512 case TargetLowering::Custom: 2513 assert(0 && "Cannot promote/custom this yet!"); 2514 case TargetLowering::Legal: 2515 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2516 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2517 break; 2518 case TargetLowering::Expand: 2519 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2520 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2521 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2522 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2523 TLI.getShiftAmountTy())); 2524 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2525 break; 2526 } 2527 break; 2528 } 2529 2530 case ISD::UREM: 2531 case ISD::SREM: 2532 case ISD::FREM: 2533 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2534 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2535 2536 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2537 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2538 case TargetLowering::Custom: 2539 isCustom = true; 2540 // FALLTHROUGH 2541 case TargetLowering::Legal: 2542 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2543 if (isCustom) { 2544 Tmp1 = TLI.LowerOperation(Result, DAG); 2545 if (Tmp1.Val) Result = Tmp1; 2546 } 2547 break; 2548 case TargetLowering::Expand: 2549 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2550 bool isSigned = DivOpc == ISD::SDIV; 2551 if (MVT::isInteger(Node->getValueType(0))) { 2552 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) == 2553 TargetLowering::Legal) { 2554 // X % Y -> X-X/Y*Y 2555 MVT::ValueType VT = Node->getValueType(0); 2556 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 2557 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2558 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2559 } else { 2560 assert(Node->getValueType(0) == MVT::i32 && 2561 "Cannot expand this binary operator!"); 2562 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 2563 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 2564 SDOperand Dummy; 2565 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2566 } 2567 } else { 2568 // Floating point mod -> fmod libcall. 2569 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32 2570 ? RTLIB::REM_F32 : RTLIB::REM_F64; 2571 SDOperand Dummy; 2572 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2573 false/*sign irrelevant*/, Dummy); 2574 } 2575 break; 2576 } 2577 break; 2578 case ISD::VAARG: { 2579 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2580 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2581 2582 MVT::ValueType VT = Node->getValueType(0); 2583 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2584 default: assert(0 && "This action is not supported yet!"); 2585 case TargetLowering::Custom: 2586 isCustom = true; 2587 // FALLTHROUGH 2588 case TargetLowering::Legal: 2589 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2590 Result = Result.getValue(0); 2591 Tmp1 = Result.getValue(1); 2592 2593 if (isCustom) { 2594 Tmp2 = TLI.LowerOperation(Result, DAG); 2595 if (Tmp2.Val) { 2596 Result = LegalizeOp(Tmp2); 2597 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 2598 } 2599 } 2600 break; 2601 case TargetLowering::Expand: { 2602 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 2603 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2604 SV->getValue(), SV->getOffset()); 2605 // Increment the pointer, VAList, to the next vaarg 2606 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2607 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2608 TLI.getPointerTy())); 2609 // Store the incremented VAList to the legalized pointer 2610 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 2611 SV->getOffset()); 2612 // Load the actual argument out of the pointer VAList 2613 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 2614 Tmp1 = LegalizeOp(Result.getValue(1)); 2615 Result = LegalizeOp(Result); 2616 break; 2617 } 2618 } 2619 // Since VAARG produces two values, make sure to remember that we 2620 // legalized both of them. 2621 AddLegalizedOperand(SDOperand(Node, 0), Result); 2622 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 2623 return Op.ResNo ? Tmp1 : Result; 2624 } 2625 2626 case ISD::VACOPY: 2627 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2628 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 2629 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 2630 2631 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 2632 default: assert(0 && "This action is not supported yet!"); 2633 case TargetLowering::Custom: 2634 isCustom = true; 2635 // FALLTHROUGH 2636 case TargetLowering::Legal: 2637 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 2638 Node->getOperand(3), Node->getOperand(4)); 2639 if (isCustom) { 2640 Tmp1 = TLI.LowerOperation(Result, DAG); 2641 if (Tmp1.Val) Result = Tmp1; 2642 } 2643 break; 2644 case TargetLowering::Expand: 2645 // This defaults to loading a pointer from the input and storing it to the 2646 // output, returning the chain. 2647 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); 2648 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); 2649 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), 2650 SVD->getOffset()); 2651 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), 2652 SVS->getOffset()); 2653 break; 2654 } 2655 break; 2656 2657 case ISD::VAEND: 2658 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2659 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2660 2661 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 2662 default: assert(0 && "This action is not supported yet!"); 2663 case TargetLowering::Custom: 2664 isCustom = true; 2665 // FALLTHROUGH 2666 case TargetLowering::Legal: 2667 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2668 if (isCustom) { 2669 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 2670 if (Tmp1.Val) Result = Tmp1; 2671 } 2672 break; 2673 case TargetLowering::Expand: 2674 Result = Tmp1; // Default to a no-op, return the chain 2675 break; 2676 } 2677 break; 2678 2679 case ISD::VASTART: 2680 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2681 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2682 2683 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2684 2685 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 2686 default: assert(0 && "This action is not supported yet!"); 2687 case TargetLowering::Legal: break; 2688 case TargetLowering::Custom: 2689 Tmp1 = TLI.LowerOperation(Result, DAG); 2690 if (Tmp1.Val) Result = Tmp1; 2691 break; 2692 } 2693 break; 2694 2695 case ISD::ROTL: 2696 case ISD::ROTR: 2697 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2698 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2699 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2700 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2701 default: 2702 assert(0 && "ROTL/ROTR legalize operation not supported"); 2703 break; 2704 case TargetLowering::Legal: 2705 break; 2706 case TargetLowering::Custom: 2707 Tmp1 = TLI.LowerOperation(Result, DAG); 2708 if (Tmp1.Val) Result = Tmp1; 2709 break; 2710 case TargetLowering::Promote: 2711 assert(0 && "Do not know how to promote ROTL/ROTR"); 2712 break; 2713 case TargetLowering::Expand: 2714 assert(0 && "Do not know how to expand ROTL/ROTR"); 2715 break; 2716 } 2717 break; 2718 2719 case ISD::BSWAP: 2720 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2721 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2722 case TargetLowering::Custom: 2723 assert(0 && "Cannot custom legalize this yet!"); 2724 case TargetLowering::Legal: 2725 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2726 break; 2727 case TargetLowering::Promote: { 2728 MVT::ValueType OVT = Tmp1.getValueType(); 2729 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2730 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); 2731 2732 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2733 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 2734 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 2735 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 2736 break; 2737 } 2738 case TargetLowering::Expand: 2739 Result = ExpandBSWAP(Tmp1); 2740 break; 2741 } 2742 break; 2743 2744 case ISD::CTPOP: 2745 case ISD::CTTZ: 2746 case ISD::CTLZ: 2747 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2748 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2749 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!"); 2750 case TargetLowering::Legal: 2751 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2752 break; 2753 case TargetLowering::Promote: { 2754 MVT::ValueType OVT = Tmp1.getValueType(); 2755 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2756 2757 // Zero extend the argument. 2758 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2759 // Perform the larger operation, then subtract if needed. 2760 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2761 switch (Node->getOpcode()) { 2762 case ISD::CTPOP: 2763 Result = Tmp1; 2764 break; 2765 case ISD::CTTZ: 2766 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2767 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2768 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 2769 ISD::SETEQ); 2770 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2771 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); 2772 break; 2773 case ISD::CTLZ: 2774 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2775 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2776 DAG.getConstant(MVT::getSizeInBits(NVT) - 2777 MVT::getSizeInBits(OVT), NVT)); 2778 break; 2779 } 2780 break; 2781 } 2782 case TargetLowering::Expand: 2783 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 2784 break; 2785 } 2786 break; 2787 2788 // Unary operators 2789 case ISD::FABS: 2790 case ISD::FNEG: 2791 case ISD::FSQRT: 2792 case ISD::FSIN: 2793 case ISD::FCOS: 2794 Tmp1 = LegalizeOp(Node->getOperand(0)); 2795 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2796 case TargetLowering::Promote: 2797 case TargetLowering::Custom: 2798 isCustom = true; 2799 // FALLTHROUGH 2800 case TargetLowering::Legal: 2801 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2802 if (isCustom) { 2803 Tmp1 = TLI.LowerOperation(Result, DAG); 2804 if (Tmp1.Val) Result = Tmp1; 2805 } 2806 break; 2807 case TargetLowering::Expand: 2808 switch (Node->getOpcode()) { 2809 default: assert(0 && "Unreachable!"); 2810 case ISD::FNEG: 2811 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2812 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2813 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 2814 break; 2815 case ISD::FABS: { 2816 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2817 MVT::ValueType VT = Node->getValueType(0); 2818 Tmp2 = DAG.getConstantFP(0.0, VT); 2819 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2820 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2821 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2822 break; 2823 } 2824 case ISD::FSQRT: 2825 case ISD::FSIN: 2826 case ISD::FCOS: { 2827 MVT::ValueType VT = Node->getValueType(0); 2828 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2829 switch(Node->getOpcode()) { 2830 case ISD::FSQRT: 2831 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64; 2832 break; 2833 case ISD::FSIN: 2834 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 2835 break; 2836 case ISD::FCOS: 2837 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64; 2838 break; 2839 default: assert(0 && "Unreachable!"); 2840 } 2841 SDOperand Dummy; 2842 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2843 false/*sign irrelevant*/, Dummy); 2844 break; 2845 } 2846 } 2847 break; 2848 } 2849 break; 2850 case ISD::FPOWI: { 2851 // We always lower FPOWI into a libcall. No target support it yet. 2852 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32 2853 ? RTLIB::POWI_F32 : RTLIB::POWI_F64; 2854 SDOperand Dummy; 2855 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2856 false/*sign irrelevant*/, Dummy); 2857 break; 2858 } 2859 case ISD::BIT_CONVERT: 2860 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 2861 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2862 } else { 2863 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 2864 Node->getOperand(0).getValueType())) { 2865 default: assert(0 && "Unknown operation action!"); 2866 case TargetLowering::Expand: 2867 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2868 break; 2869 case TargetLowering::Legal: 2870 Tmp1 = LegalizeOp(Node->getOperand(0)); 2871 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2872 break; 2873 } 2874 } 2875 break; 2876 case ISD::VBIT_CONVERT: { 2877 assert(Op.getOperand(0).getValueType() == MVT::Vector && 2878 "Can only have VBIT_CONVERT where input or output is MVT::Vector!"); 2879 2880 // The input has to be a vector type, we have to either scalarize it, pack 2881 // it, or convert it based on whether the input vector type is legal. 2882 SDNode *InVal = Node->getOperand(0).Val; 2883 unsigned NumElems = 2884 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 2885 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 2886 2887 // Figure out if there is a Packed type corresponding to this Vector 2888 // type. If so, convert to the vector type. 2889 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2890 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 2891 // Turn this into a bit convert of the packed input. 2892 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2893 PackVectorOp(Node->getOperand(0), TVT)); 2894 break; 2895 } else if (NumElems == 1) { 2896 // Turn this into a bit convert of the scalar input. 2897 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2898 PackVectorOp(Node->getOperand(0), EVT)); 2899 break; 2900 } else { 2901 // FIXME: UNIMP! Store then reload 2902 assert(0 && "Cast from unsupported vector type not implemented yet!"); 2903 } 2904 } 2905 2906 // Conversion operators. The source and destination have different types. 2907 case ISD::SINT_TO_FP: 2908 case ISD::UINT_TO_FP: { 2909 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2910 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2911 case Legal: 2912 switch (TLI.getOperationAction(Node->getOpcode(), 2913 Node->getOperand(0).getValueType())) { 2914 default: assert(0 && "Unknown operation action!"); 2915 case TargetLowering::Custom: 2916 isCustom = true; 2917 // FALLTHROUGH 2918 case TargetLowering::Legal: 2919 Tmp1 = LegalizeOp(Node->getOperand(0)); 2920 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2921 if (isCustom) { 2922 Tmp1 = TLI.LowerOperation(Result, DAG); 2923 if (Tmp1.Val) Result = Tmp1; 2924 } 2925 break; 2926 case TargetLowering::Expand: 2927 Result = ExpandLegalINT_TO_FP(isSigned, 2928 LegalizeOp(Node->getOperand(0)), 2929 Node->getValueType(0)); 2930 break; 2931 case TargetLowering::Promote: 2932 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2933 Node->getValueType(0), 2934 isSigned); 2935 break; 2936 } 2937 break; 2938 case Expand: 2939 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2940 Node->getValueType(0), Node->getOperand(0)); 2941 break; 2942 case Promote: 2943 Tmp1 = PromoteOp(Node->getOperand(0)); 2944 if (isSigned) { 2945 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 2946 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 2947 } else { 2948 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 2949 Node->getOperand(0).getValueType()); 2950 } 2951 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2952 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 2953 break; 2954 } 2955 break; 2956 } 2957 case ISD::TRUNCATE: 2958 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2959 case Legal: 2960 Tmp1 = LegalizeOp(Node->getOperand(0)); 2961 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2962 break; 2963 case Expand: 2964 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2965 2966 // Since the result is legal, we should just be able to truncate the low 2967 // part of the source. 2968 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2969 break; 2970 case Promote: 2971 Result = PromoteOp(Node->getOperand(0)); 2972 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2973 break; 2974 } 2975 break; 2976 2977 case ISD::FP_TO_SINT: 2978 case ISD::FP_TO_UINT: 2979 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2980 case Legal: 2981 Tmp1 = LegalizeOp(Node->getOperand(0)); 2982 2983 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2984 default: assert(0 && "Unknown operation action!"); 2985 case TargetLowering::Custom: 2986 isCustom = true; 2987 // FALLTHROUGH 2988 case TargetLowering::Legal: 2989 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2990 if (isCustom) { 2991 Tmp1 = TLI.LowerOperation(Result, DAG); 2992 if (Tmp1.Val) Result = Tmp1; 2993 } 2994 break; 2995 case TargetLowering::Promote: 2996 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2997 Node->getOpcode() == ISD::FP_TO_SINT); 2998 break; 2999 case TargetLowering::Expand: 3000 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3001 SDOperand True, False; 3002 MVT::ValueType VT = Node->getOperand(0).getValueType(); 3003 MVT::ValueType NVT = Node->getValueType(0); 3004 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 3005 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 3006 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 3007 Node->getOperand(0), Tmp2, ISD::SETLT); 3008 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3009 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3010 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3011 Tmp2)); 3012 False = DAG.getNode(ISD::XOR, NVT, False, 3013 DAG.getConstant(1ULL << ShiftAmt, NVT)); 3014 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3015 break; 3016 } else { 3017 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3018 } 3019 break; 3020 } 3021 break; 3022 case Expand: { 3023 // Convert f32 / f64 to i32 / i64. 3024 MVT::ValueType VT = Op.getValueType(); 3025 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3026 switch (Node->getOpcode()) { 3027 case ISD::FP_TO_SINT: 3028 if (Node->getOperand(0).getValueType() == MVT::f32) 3029 LC = (VT == MVT::i32) 3030 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3031 else 3032 LC = (VT == MVT::i32) 3033 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3034 break; 3035 case ISD::FP_TO_UINT: 3036 if (Node->getOperand(0).getValueType() == MVT::f32) 3037 LC = (VT == MVT::i32) 3038 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3039 else 3040 LC = (VT == MVT::i32) 3041 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3042 break; 3043 default: assert(0 && "Unreachable!"); 3044 } 3045 SDOperand Dummy; 3046 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3047 false/*sign irrelevant*/, Dummy); 3048 break; 3049 } 3050 case Promote: 3051 Tmp1 = PromoteOp(Node->getOperand(0)); 3052 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3053 Result = LegalizeOp(Result); 3054 break; 3055 } 3056 break; 3057 3058 case ISD::ANY_EXTEND: 3059 case ISD::ZERO_EXTEND: 3060 case ISD::SIGN_EXTEND: 3061 case ISD::FP_EXTEND: 3062 case ISD::FP_ROUND: 3063 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3064 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3065 case Legal: 3066 Tmp1 = LegalizeOp(Node->getOperand(0)); 3067 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3068 break; 3069 case Promote: 3070 switch (Node->getOpcode()) { 3071 case ISD::ANY_EXTEND: 3072 Tmp1 = PromoteOp(Node->getOperand(0)); 3073 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3074 break; 3075 case ISD::ZERO_EXTEND: 3076 Result = PromoteOp(Node->getOperand(0)); 3077 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3078 Result = DAG.getZeroExtendInReg(Result, 3079 Node->getOperand(0).getValueType()); 3080 break; 3081 case ISD::SIGN_EXTEND: 3082 Result = PromoteOp(Node->getOperand(0)); 3083 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3084 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3085 Result, 3086 DAG.getValueType(Node->getOperand(0).getValueType())); 3087 break; 3088 case ISD::FP_EXTEND: 3089 Result = PromoteOp(Node->getOperand(0)); 3090 if (Result.getValueType() != Op.getValueType()) 3091 // Dynamically dead while we have only 2 FP types. 3092 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 3093 break; 3094 case ISD::FP_ROUND: 3095 Result = PromoteOp(Node->getOperand(0)); 3096 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 3097 break; 3098 } 3099 } 3100 break; 3101 case ISD::FP_ROUND_INREG: 3102 case ISD::SIGN_EXTEND_INREG: { 3103 Tmp1 = LegalizeOp(Node->getOperand(0)); 3104 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3105 3106 // If this operation is not supported, convert it to a shl/shr or load/store 3107 // pair. 3108 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3109 default: assert(0 && "This action not supported for this op yet!"); 3110 case TargetLowering::Legal: 3111 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3112 break; 3113 case TargetLowering::Expand: 3114 // If this is an integer extend and shifts are supported, do that. 3115 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3116 // NOTE: we could fall back on load/store here too for targets without 3117 // SAR. However, it is doubtful that any exist. 3118 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3119 MVT::getSizeInBits(ExtraVT); 3120 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3121 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3122 Node->getOperand(0), ShiftCst); 3123 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3124 Result, ShiftCst); 3125 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3126 // The only way we can lower this is to turn it into a TRUNCSTORE, 3127 // EXTLOAD pair, targetting a temporary location (a stack slot). 3128 3129 // NOTE: there is a choice here between constantly creating new stack 3130 // slots and always reusing the same one. We currently always create 3131 // new ones, as reuse may inhibit scheduling. 3132 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 3133 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3134 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3135 MachineFunction &MF = DAG.getMachineFunction(); 3136 int SSFI = 3137 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3138 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3139 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3140 StackSlot, NULL, 0, ExtraVT); 3141 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 3142 Result, StackSlot, NULL, 0, ExtraVT); 3143 } else { 3144 assert(0 && "Unknown op"); 3145 } 3146 break; 3147 } 3148 break; 3149 } 3150 } 3151 3152 assert(Result.getValueType() == Op.getValueType() && 3153 "Bad legalization!"); 3154 3155 // Make sure that the generated code is itself legal. 3156 if (Result != Op) 3157 Result = LegalizeOp(Result); 3158 3159 // Note that LegalizeOp may be reentered even from single-use nodes, which 3160 // means that we always must cache transformed nodes. 3161 AddLegalizedOperand(Op, Result); 3162 return Result; 3163} 3164 3165/// PromoteOp - Given an operation that produces a value in an invalid type, 3166/// promote it to compute the value into a larger type. The produced value will 3167/// have the correct bits for the low portion of the register, but no guarantee 3168/// is made about the top bits: it may be zero, sign-extended, or garbage. 3169SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 3170 MVT::ValueType VT = Op.getValueType(); 3171 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3172 assert(getTypeAction(VT) == Promote && 3173 "Caller should expand or legalize operands that are not promotable!"); 3174 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 3175 "Cannot promote to smaller type!"); 3176 3177 SDOperand Tmp1, Tmp2, Tmp3; 3178 SDOperand Result; 3179 SDNode *Node = Op.Val; 3180 3181 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 3182 if (I != PromotedNodes.end()) return I->second; 3183 3184 switch (Node->getOpcode()) { 3185 case ISD::CopyFromReg: 3186 assert(0 && "CopyFromReg must be legal!"); 3187 default: 3188#ifndef NDEBUG 3189 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 3190#endif 3191 assert(0 && "Do not know how to promote this operator!"); 3192 abort(); 3193 case ISD::UNDEF: 3194 Result = DAG.getNode(ISD::UNDEF, NVT); 3195 break; 3196 case ISD::Constant: 3197 if (VT != MVT::i1) 3198 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 3199 else 3200 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 3201 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 3202 break; 3203 case ISD::ConstantFP: 3204 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 3205 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 3206 break; 3207 3208 case ISD::SETCC: 3209 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 3210 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 3211 Node->getOperand(1), Node->getOperand(2)); 3212 break; 3213 3214 case ISD::TRUNCATE: 3215 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3216 case Legal: 3217 Result = LegalizeOp(Node->getOperand(0)); 3218 assert(Result.getValueType() >= NVT && 3219 "This truncation doesn't make sense!"); 3220 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 3221 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 3222 break; 3223 case Promote: 3224 // The truncation is not required, because we don't guarantee anything 3225 // about high bits anyway. 3226 Result = PromoteOp(Node->getOperand(0)); 3227 break; 3228 case Expand: 3229 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3230 // Truncate the low part of the expanded value to the result type 3231 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 3232 } 3233 break; 3234 case ISD::SIGN_EXTEND: 3235 case ISD::ZERO_EXTEND: 3236 case ISD::ANY_EXTEND: 3237 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3238 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 3239 case Legal: 3240 // Input is legal? Just do extend all the way to the larger type. 3241 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3242 break; 3243 case Promote: 3244 // Promote the reg if it's smaller. 3245 Result = PromoteOp(Node->getOperand(0)); 3246 // The high bits are not guaranteed to be anything. Insert an extend. 3247 if (Node->getOpcode() == ISD::SIGN_EXTEND) 3248 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3249 DAG.getValueType(Node->getOperand(0).getValueType())); 3250 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 3251 Result = DAG.getZeroExtendInReg(Result, 3252 Node->getOperand(0).getValueType()); 3253 break; 3254 } 3255 break; 3256 case ISD::BIT_CONVERT: 3257 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3258 Result = PromoteOp(Result); 3259 break; 3260 3261 case ISD::FP_EXTEND: 3262 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 3263 case ISD::FP_ROUND: 3264 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3265 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 3266 case Promote: assert(0 && "Unreachable with 2 FP types!"); 3267 case Legal: 3268 // Input is legal? Do an FP_ROUND_INREG. 3269 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 3270 DAG.getValueType(VT)); 3271 break; 3272 } 3273 break; 3274 3275 case ISD::SINT_TO_FP: 3276 case ISD::UINT_TO_FP: 3277 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3278 case Legal: 3279 // No extra round required here. 3280 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3281 break; 3282 3283 case Promote: 3284 Result = PromoteOp(Node->getOperand(0)); 3285 if (Node->getOpcode() == ISD::SINT_TO_FP) 3286 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3287 Result, 3288 DAG.getValueType(Node->getOperand(0).getValueType())); 3289 else 3290 Result = DAG.getZeroExtendInReg(Result, 3291 Node->getOperand(0).getValueType()); 3292 // No extra round required here. 3293 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3294 break; 3295 case Expand: 3296 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3297 Node->getOperand(0)); 3298 // Round if we cannot tolerate excess precision. 3299 if (NoExcessFPPrecision) 3300 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3301 DAG.getValueType(VT)); 3302 break; 3303 } 3304 break; 3305 3306 case ISD::SIGN_EXTEND_INREG: 3307 Result = PromoteOp(Node->getOperand(0)); 3308 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3309 Node->getOperand(1)); 3310 break; 3311 case ISD::FP_TO_SINT: 3312 case ISD::FP_TO_UINT: 3313 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3314 case Legal: 3315 case Expand: 3316 Tmp1 = Node->getOperand(0); 3317 break; 3318 case Promote: 3319 // The input result is prerounded, so we don't have to do anything 3320 // special. 3321 Tmp1 = PromoteOp(Node->getOperand(0)); 3322 break; 3323 } 3324 // If we're promoting a UINT to a larger size, check to see if the new node 3325 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3326 // we can use that instead. This allows us to generate better code for 3327 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3328 // legal, such as PowerPC. 3329 if (Node->getOpcode() == ISD::FP_TO_UINT && 3330 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3331 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3332 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3333 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3334 } else { 3335 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3336 } 3337 break; 3338 3339 case ISD::FABS: 3340 case ISD::FNEG: 3341 Tmp1 = PromoteOp(Node->getOperand(0)); 3342 assert(Tmp1.getValueType() == NVT); 3343 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3344 // NOTE: we do not have to do any extra rounding here for 3345 // NoExcessFPPrecision, because we know the input will have the appropriate 3346 // precision, and these operations don't modify precision at all. 3347 break; 3348 3349 case ISD::FSQRT: 3350 case ISD::FSIN: 3351 case ISD::FCOS: 3352 Tmp1 = PromoteOp(Node->getOperand(0)); 3353 assert(Tmp1.getValueType() == NVT); 3354 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3355 if (NoExcessFPPrecision) 3356 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3357 DAG.getValueType(VT)); 3358 break; 3359 3360 case ISD::FPOWI: { 3361 // Promote f32 powi to f64 powi. Note that this could insert a libcall 3362 // directly as well, which may be better. 3363 Tmp1 = PromoteOp(Node->getOperand(0)); 3364 assert(Tmp1.getValueType() == NVT); 3365 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 3366 if (NoExcessFPPrecision) 3367 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3368 DAG.getValueType(VT)); 3369 break; 3370 } 3371 3372 case ISD::AND: 3373 case ISD::OR: 3374 case ISD::XOR: 3375 case ISD::ADD: 3376 case ISD::SUB: 3377 case ISD::MUL: 3378 // The input may have strange things in the top bits of the registers, but 3379 // these operations don't care. They may have weird bits going out, but 3380 // that too is okay if they are integer operations. 3381 Tmp1 = PromoteOp(Node->getOperand(0)); 3382 Tmp2 = PromoteOp(Node->getOperand(1)); 3383 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3384 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3385 break; 3386 case ISD::FADD: 3387 case ISD::FSUB: 3388 case ISD::FMUL: 3389 Tmp1 = PromoteOp(Node->getOperand(0)); 3390 Tmp2 = PromoteOp(Node->getOperand(1)); 3391 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3392 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3393 3394 // Floating point operations will give excess precision that we may not be 3395 // able to tolerate. If we DO allow excess precision, just leave it, 3396 // otherwise excise it. 3397 // FIXME: Why would we need to round FP ops more than integer ones? 3398 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3399 if (NoExcessFPPrecision) 3400 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3401 DAG.getValueType(VT)); 3402 break; 3403 3404 case ISD::SDIV: 3405 case ISD::SREM: 3406 // These operators require that their input be sign extended. 3407 Tmp1 = PromoteOp(Node->getOperand(0)); 3408 Tmp2 = PromoteOp(Node->getOperand(1)); 3409 if (MVT::isInteger(NVT)) { 3410 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3411 DAG.getValueType(VT)); 3412 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3413 DAG.getValueType(VT)); 3414 } 3415 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3416 3417 // Perform FP_ROUND: this is probably overly pessimistic. 3418 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 3419 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3420 DAG.getValueType(VT)); 3421 break; 3422 case ISD::FDIV: 3423 case ISD::FREM: 3424 case ISD::FCOPYSIGN: 3425 // These operators require that their input be fp extended. 3426 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3427 case Legal: 3428 Tmp1 = LegalizeOp(Node->getOperand(0)); 3429 break; 3430 case Promote: 3431 Tmp1 = PromoteOp(Node->getOperand(0)); 3432 break; 3433 case Expand: 3434 assert(0 && "not implemented"); 3435 } 3436 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3437 case Legal: 3438 Tmp2 = LegalizeOp(Node->getOperand(1)); 3439 break; 3440 case Promote: 3441 Tmp2 = PromoteOp(Node->getOperand(1)); 3442 break; 3443 case Expand: 3444 assert(0 && "not implemented"); 3445 } 3446 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3447 3448 // Perform FP_ROUND: this is probably overly pessimistic. 3449 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 3450 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3451 DAG.getValueType(VT)); 3452 break; 3453 3454 case ISD::UDIV: 3455 case ISD::UREM: 3456 // These operators require that their input be zero extended. 3457 Tmp1 = PromoteOp(Node->getOperand(0)); 3458 Tmp2 = PromoteOp(Node->getOperand(1)); 3459 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 3460 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3461 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3462 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3463 break; 3464 3465 case ISD::SHL: 3466 Tmp1 = PromoteOp(Node->getOperand(0)); 3467 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 3468 break; 3469 case ISD::SRA: 3470 // The input value must be properly sign extended. 3471 Tmp1 = PromoteOp(Node->getOperand(0)); 3472 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3473 DAG.getValueType(VT)); 3474 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 3475 break; 3476 case ISD::SRL: 3477 // The input value must be properly zero extended. 3478 Tmp1 = PromoteOp(Node->getOperand(0)); 3479 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3480 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 3481 break; 3482 3483 case ISD::VAARG: 3484 Tmp1 = Node->getOperand(0); // Get the chain. 3485 Tmp2 = Node->getOperand(1); // Get the pointer. 3486 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 3487 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 3488 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 3489 } else { 3490 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 3491 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3492 SV->getValue(), SV->getOffset()); 3493 // Increment the pointer, VAList, to the next vaarg 3494 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3495 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3496 TLI.getPointerTy())); 3497 // Store the incremented VAList to the legalized pointer 3498 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 3499 SV->getOffset()); 3500 // Load the actual argument out of the pointer VAList 3501 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 3502 } 3503 // Remember that we legalized the chain. 3504 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3505 break; 3506 3507 case ISD::LOAD: { 3508 LoadSDNode *LD = cast<LoadSDNode>(Node); 3509 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 3510 ? ISD::EXTLOAD : LD->getExtensionType(); 3511 Result = DAG.getExtLoad(ExtType, NVT, 3512 LD->getChain(), LD->getBasePtr(), 3513 LD->getSrcValue(), LD->getSrcValueOffset(), 3514 LD->getLoadedVT()); 3515 // Remember that we legalized the chain. 3516 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3517 break; 3518 } 3519 case ISD::SELECT: 3520 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 3521 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 3522 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 3523 break; 3524 case ISD::SELECT_CC: 3525 Tmp2 = PromoteOp(Node->getOperand(2)); // True 3526 Tmp3 = PromoteOp(Node->getOperand(3)); // False 3527 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3528 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 3529 break; 3530 case ISD::BSWAP: 3531 Tmp1 = Node->getOperand(0); 3532 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3533 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3534 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3535 DAG.getConstant(MVT::getSizeInBits(NVT) - 3536 MVT::getSizeInBits(VT), 3537 TLI.getShiftAmountTy())); 3538 break; 3539 case ISD::CTPOP: 3540 case ISD::CTTZ: 3541 case ISD::CTLZ: 3542 // Zero extend the argument 3543 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 3544 // Perform the larger operation, then subtract if needed. 3545 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3546 switch(Node->getOpcode()) { 3547 case ISD::CTPOP: 3548 Result = Tmp1; 3549 break; 3550 case ISD::CTTZ: 3551 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3552 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3553 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 3554 ISD::SETEQ); 3555 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3556 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); 3557 break; 3558 case ISD::CTLZ: 3559 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3560 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3561 DAG.getConstant(MVT::getSizeInBits(NVT) - 3562 MVT::getSizeInBits(VT), NVT)); 3563 break; 3564 } 3565 break; 3566 case ISD::VEXTRACT_VECTOR_ELT: 3567 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op)); 3568 break; 3569 case ISD::VEXTRACT_SUBVECTOR: 3570 Result = PromoteOp(LowerVEXTRACT_SUBVECTOR(Op)); 3571 break; 3572 case ISD::EXTRACT_VECTOR_ELT: 3573 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 3574 break; 3575 } 3576 3577 assert(Result.Val && "Didn't set a result!"); 3578 3579 // Make sure the result is itself legal. 3580 Result = LegalizeOp(Result); 3581 3582 // Remember that we promoted this! 3583 AddPromotedOperand(Op, Result); 3584 return Result; 3585} 3586 3587/// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a 3588/// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based 3589/// on the vector type. The return type of this matches the element type of the 3590/// vector, which may not be legal for the target. 3591SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) { 3592 // We know that operand #0 is the Vec vector. If the index is a constant 3593 // or if the invec is a supported hardware type, we can use it. Otherwise, 3594 // lower to a store then an indexed load. 3595 SDOperand Vec = Op.getOperand(0); 3596 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 3597 3598 SDNode *InVal = Vec.Val; 3599 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 3600 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 3601 3602 // Figure out if there is a Packed type corresponding to this Vector 3603 // type. If so, convert to the vector type. 3604 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3605 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 3606 // Turn this into a packed extract_vector_elt operation. 3607 Vec = PackVectorOp(Vec, TVT); 3608 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx); 3609 } else if (NumElems == 1) { 3610 // This must be an access of the only element. Return it. 3611 return PackVectorOp(Vec, EVT); 3612 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 3613 SDOperand Lo, Hi; 3614 SplitVectorOp(Vec, Lo, Hi); 3615 if (CIdx->getValue() < NumElems/2) { 3616 Vec = Lo; 3617 } else { 3618 Vec = Hi; 3619 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 3620 } 3621 3622 // It's now an extract from the appropriate high or low part. Recurse. 3623 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3624 return LowerVEXTRACT_VECTOR_ELT(Op); 3625 } else { 3626 // Variable index case for extract element. 3627 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!! 3628 assert(0 && "unimp!"); 3629 return SDOperand(); 3630 } 3631} 3632 3633/// LowerVEXTRACT_SUBVECTOR - Lower a VEXTRACT_SUBVECTOR operation. For now 3634/// we assume the operation can be split if it is not already legal. 3635SDOperand SelectionDAGLegalize::LowerVEXTRACT_SUBVECTOR(SDOperand Op) { 3636 // We know that operand #0 is the Vec vector. For now we assume the index 3637 // is a constant and that the extracted result is a supported hardware type. 3638 SDOperand Vec = Op.getOperand(0); 3639 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 3640 3641 SDNode *InVal = Vec.Val; 3642 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 3643 3644 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { 3645 // This must be an access of the desired vector length. Return it. 3646 return PackVectorOp(Vec, Op.getValueType()); 3647 } 3648 3649 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 3650 SDOperand Lo, Hi; 3651 SplitVectorOp(Vec, Lo, Hi); 3652 if (CIdx->getValue() < NumElems/2) { 3653 Vec = Lo; 3654 } else { 3655 Vec = Hi; 3656 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 3657 } 3658 3659 // It's now an extract from the appropriate high or low part. Recurse. 3660 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3661 return LowerVEXTRACT_SUBVECTOR(Op); 3662} 3663 3664/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 3665/// memory traffic. 3666SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 3667 SDOperand Vector = Op.getOperand(0); 3668 SDOperand Idx = Op.getOperand(1); 3669 3670 // If the target doesn't support this, store the value to a temporary 3671 // stack slot, then LOAD the scalar element back out. 3672 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType()); 3673 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vector, StackPtr, NULL, 0); 3674 3675 // Add the offset to the index. 3676 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 3677 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 3678 DAG.getConstant(EltSize, Idx.getValueType())); 3679 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 3680 3681 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 3682} 3683 3684 3685/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 3686/// with condition CC on the current target. This usually involves legalizing 3687/// or promoting the arguments. In the case where LHS and RHS must be expanded, 3688/// there may be no choice but to create a new SetCC node to represent the 3689/// legalized value of setcc lhs, rhs. In this case, the value is returned in 3690/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 3691void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 3692 SDOperand &RHS, 3693 SDOperand &CC) { 3694 SDOperand Tmp1, Tmp2, Result; 3695 3696 switch (getTypeAction(LHS.getValueType())) { 3697 case Legal: 3698 Tmp1 = LegalizeOp(LHS); // LHS 3699 Tmp2 = LegalizeOp(RHS); // RHS 3700 break; 3701 case Promote: 3702 Tmp1 = PromoteOp(LHS); // LHS 3703 Tmp2 = PromoteOp(RHS); // RHS 3704 3705 // If this is an FP compare, the operands have already been extended. 3706 if (MVT::isInteger(LHS.getValueType())) { 3707 MVT::ValueType VT = LHS.getValueType(); 3708 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3709 3710 // Otherwise, we have to insert explicit sign or zero extends. Note 3711 // that we could insert sign extends for ALL conditions, but zero extend 3712 // is cheaper on many machines (an AND instead of two shifts), so prefer 3713 // it. 3714 switch (cast<CondCodeSDNode>(CC)->get()) { 3715 default: assert(0 && "Unknown integer comparison!"); 3716 case ISD::SETEQ: 3717 case ISD::SETNE: 3718 case ISD::SETUGE: 3719 case ISD::SETUGT: 3720 case ISD::SETULE: 3721 case ISD::SETULT: 3722 // ALL of these operations will work if we either sign or zero extend 3723 // the operands (including the unsigned comparisons!). Zero extend is 3724 // usually a simpler/cheaper operation, so prefer it. 3725 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3726 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3727 break; 3728 case ISD::SETGE: 3729 case ISD::SETGT: 3730 case ISD::SETLT: 3731 case ISD::SETLE: 3732 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3733 DAG.getValueType(VT)); 3734 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3735 DAG.getValueType(VT)); 3736 break; 3737 } 3738 } 3739 break; 3740 case Expand: { 3741 MVT::ValueType VT = LHS.getValueType(); 3742 if (VT == MVT::f32 || VT == MVT::f64) { 3743 // Expand into one or more soft-fp libcall(s). 3744 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 3745 switch (cast<CondCodeSDNode>(CC)->get()) { 3746 case ISD::SETEQ: 3747 case ISD::SETOEQ: 3748 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 3749 break; 3750 case ISD::SETNE: 3751 case ISD::SETUNE: 3752 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 3753 break; 3754 case ISD::SETGE: 3755 case ISD::SETOGE: 3756 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 3757 break; 3758 case ISD::SETLT: 3759 case ISD::SETOLT: 3760 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3761 break; 3762 case ISD::SETLE: 3763 case ISD::SETOLE: 3764 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 3765 break; 3766 case ISD::SETGT: 3767 case ISD::SETOGT: 3768 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 3769 break; 3770 case ISD::SETUO: 3771 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 3772 break; 3773 case ISD::SETO: 3774 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 3775 break; 3776 default: 3777 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 3778 switch (cast<CondCodeSDNode>(CC)->get()) { 3779 case ISD::SETONE: 3780 // SETONE = SETOLT | SETOGT 3781 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3782 // Fallthrough 3783 case ISD::SETUGT: 3784 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 3785 break; 3786 case ISD::SETUGE: 3787 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 3788 break; 3789 case ISD::SETULT: 3790 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3791 break; 3792 case ISD::SETULE: 3793 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 3794 break; 3795 case ISD::SETUEQ: 3796 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 3797 break; 3798 default: assert(0 && "Unsupported FP setcc!"); 3799 } 3800 } 3801 3802 SDOperand Dummy; 3803 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 3804 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 3805 false /*sign irrelevant*/, Dummy); 3806 Tmp2 = DAG.getConstant(0, MVT::i32); 3807 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 3808 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 3809 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); 3810 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 3811 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 3812 false /*sign irrelevant*/, Dummy); 3813 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, 3814 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 3815 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 3816 Tmp2 = SDOperand(); 3817 } 3818 LHS = Tmp1; 3819 RHS = Tmp2; 3820 return; 3821 } 3822 3823 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 3824 ExpandOp(LHS, LHSLo, LHSHi); 3825 ExpandOp(RHS, RHSLo, RHSHi); 3826 switch (cast<CondCodeSDNode>(CC)->get()) { 3827 case ISD::SETEQ: 3828 case ISD::SETNE: 3829 if (RHSLo == RHSHi) 3830 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 3831 if (RHSCST->isAllOnesValue()) { 3832 // Comparison to -1. 3833 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 3834 Tmp2 = RHSLo; 3835 break; 3836 } 3837 3838 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 3839 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 3840 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 3841 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3842 break; 3843 default: 3844 // If this is a comparison of the sign bit, just look at the top part. 3845 // X > -1, x < 0 3846 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 3847 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 3848 CST->getValue() == 0) || // X < 0 3849 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 3850 CST->isAllOnesValue())) { // X > -1 3851 Tmp1 = LHSHi; 3852 Tmp2 = RHSHi; 3853 break; 3854 } 3855 3856 // FIXME: This generated code sucks. 3857 ISD::CondCode LowCC; 3858 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 3859 switch (CCCode) { 3860 default: assert(0 && "Unknown integer setcc!"); 3861 case ISD::SETLT: 3862 case ISD::SETULT: LowCC = ISD::SETULT; break; 3863 case ISD::SETGT: 3864 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 3865 case ISD::SETLE: 3866 case ISD::SETULE: LowCC = ISD::SETULE; break; 3867 case ISD::SETGE: 3868 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 3869 } 3870 3871 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 3872 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 3873 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 3874 3875 // NOTE: on targets without efficient SELECT of bools, we can always use 3876 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 3877 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 3878 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, 3879 false, DagCombineInfo); 3880 if (!Tmp1.Val) 3881 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 3882 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 3883 CCCode, false, DagCombineInfo); 3884 if (!Tmp2.Val) 3885 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC); 3886 3887 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 3888 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 3889 if ((Tmp1C && Tmp1C->getValue() == 0) || 3890 (Tmp2C && Tmp2C->getValue() == 0 && 3891 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 3892 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 3893 (Tmp2C && Tmp2C->getValue() == 1 && 3894 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 3895 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 3896 // low part is known false, returns high part. 3897 // For LE / GE, if high part is known false, ignore the low part. 3898 // For LT / GT, if high part is known true, ignore the low part. 3899 Tmp1 = Tmp2; 3900 Tmp2 = SDOperand(); 3901 } else { 3902 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 3903 ISD::SETEQ, false, DagCombineInfo); 3904 if (!Result.Val) 3905 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 3906 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 3907 Result, Tmp1, Tmp2)); 3908 Tmp1 = Result; 3909 Tmp2 = SDOperand(); 3910 } 3911 } 3912 } 3913 } 3914 LHS = Tmp1; 3915 RHS = Tmp2; 3916} 3917 3918/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 3919/// The resultant code need not be legal. Note that SrcOp is the input operand 3920/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 3921SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 3922 SDOperand SrcOp) { 3923 // Create the stack frame object. 3924 SDOperand FIPtr = CreateStackTemporary(DestVT); 3925 3926 // Emit a store to the stack slot. 3927 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); 3928 // Result is a load from the stack slot. 3929 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 3930} 3931 3932SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 3933 // Create a vector sized/aligned stack slot, store the value to element #0, 3934 // then load the whole vector back out. 3935 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); 3936 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 3937 NULL, 0); 3938 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); 3939} 3940 3941 3942/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 3943/// support the operation, but do support the resultant packed vector type. 3944SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 3945 3946 // If the only non-undef value is the low element, turn this into a 3947 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 3948 unsigned NumElems = Node->getNumOperands(); 3949 bool isOnlyLowElement = true; 3950 SDOperand SplatValue = Node->getOperand(0); 3951 std::map<SDOperand, std::vector<unsigned> > Values; 3952 Values[SplatValue].push_back(0); 3953 bool isConstant = true; 3954 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 3955 SplatValue.getOpcode() != ISD::UNDEF) 3956 isConstant = false; 3957 3958 for (unsigned i = 1; i < NumElems; ++i) { 3959 SDOperand V = Node->getOperand(i); 3960 Values[V].push_back(i); 3961 if (V.getOpcode() != ISD::UNDEF) 3962 isOnlyLowElement = false; 3963 if (SplatValue != V) 3964 SplatValue = SDOperand(0,0); 3965 3966 // If this isn't a constant element or an undef, we can't use a constant 3967 // pool load. 3968 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 3969 V.getOpcode() != ISD::UNDEF) 3970 isConstant = false; 3971 } 3972 3973 if (isOnlyLowElement) { 3974 // If the low element is an undef too, then this whole things is an undef. 3975 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 3976 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 3977 // Otherwise, turn this into a scalar_to_vector node. 3978 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 3979 Node->getOperand(0)); 3980 } 3981 3982 // If all elements are constants, create a load from the constant pool. 3983 if (isConstant) { 3984 MVT::ValueType VT = Node->getValueType(0); 3985 const Type *OpNTy = 3986 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 3987 std::vector<Constant*> CV; 3988 for (unsigned i = 0, e = NumElems; i != e; ++i) { 3989 if (ConstantFPSDNode *V = 3990 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 3991 CV.push_back(ConstantFP::get(OpNTy, V->getValue())); 3992 } else if (ConstantSDNode *V = 3993 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 3994 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 3995 } else { 3996 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 3997 CV.push_back(UndefValue::get(OpNTy)); 3998 } 3999 } 4000 Constant *CP = ConstantVector::get(CV); 4001 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4002 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 4003 } 4004 4005 if (SplatValue.Val) { // Splat of one value? 4006 // Build the shuffle constant vector: <0, 0, 0, 0> 4007 MVT::ValueType MaskVT = 4008 MVT::getIntVectorWithNumElements(NumElems); 4009 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); 4010 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4011 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4012 &ZeroVec[0], ZeroVec.size()); 4013 4014 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4015 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 4016 // Get the splatted value into the low element of a vector register. 4017 SDOperand LowValVec = 4018 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 4019 4020 // Return shuffle(LowValVec, undef, <0,0,0,0>) 4021 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 4022 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 4023 SplatMask); 4024 } 4025 } 4026 4027 // If there are only two unique elements, we may be able to turn this into a 4028 // vector shuffle. 4029 if (Values.size() == 2) { 4030 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 4031 MVT::ValueType MaskVT = 4032 MVT::getIntVectorWithNumElements(NumElems); 4033 std::vector<SDOperand> MaskVec(NumElems); 4034 unsigned i = 0; 4035 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4036 E = Values.end(); I != E; ++I) { 4037 for (std::vector<unsigned>::iterator II = I->second.begin(), 4038 EE = I->second.end(); II != EE; ++II) 4039 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT)); 4040 i += NumElems; 4041 } 4042 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4043 &MaskVec[0], MaskVec.size()); 4044 4045 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4046 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 4047 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 4048 SmallVector<SDOperand, 8> Ops; 4049 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4050 E = Values.end(); I != E; ++I) { 4051 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4052 I->first); 4053 Ops.push_back(Op); 4054 } 4055 Ops.push_back(ShuffleMask); 4056 4057 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 4058 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 4059 &Ops[0], Ops.size()); 4060 } 4061 } 4062 4063 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 4064 // aligned object on the stack, store each element into it, then load 4065 // the result as a vector. 4066 MVT::ValueType VT = Node->getValueType(0); 4067 // Create the stack frame object. 4068 SDOperand FIPtr = CreateStackTemporary(VT); 4069 4070 // Emit a store of each element to the stack slot. 4071 SmallVector<SDOperand, 8> Stores; 4072 unsigned TypeByteSize = 4073 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 4074 // Store (in the right endianness) the elements to memory. 4075 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4076 // Ignore undef elements. 4077 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4078 4079 unsigned Offset = TypeByteSize*i; 4080 4081 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 4082 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 4083 4084 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 4085 NULL, 0)); 4086 } 4087 4088 SDOperand StoreChain; 4089 if (!Stores.empty()) // Not all undef elements? 4090 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4091 &Stores[0], Stores.size()); 4092 else 4093 StoreChain = DAG.getEntryNode(); 4094 4095 // Result is a load from the stack slot. 4096 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 4097} 4098 4099/// CreateStackTemporary - Create a stack temporary, suitable for holding the 4100/// specified value type. 4101SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) { 4102 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4103 unsigned ByteSize = MVT::getSizeInBits(VT)/8; 4104 const Type *Ty = MVT::getTypeForValueType(VT); 4105 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty); 4106 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 4107 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 4108} 4109 4110void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 4111 SDOperand Op, SDOperand Amt, 4112 SDOperand &Lo, SDOperand &Hi) { 4113 // Expand the subcomponents. 4114 SDOperand LHSL, LHSH; 4115 ExpandOp(Op, LHSL, LHSH); 4116 4117 SDOperand Ops[] = { LHSL, LHSH, Amt }; 4118 MVT::ValueType VT = LHSL.getValueType(); 4119 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 4120 Hi = Lo.getValue(1); 4121} 4122 4123 4124/// ExpandShift - Try to find a clever way to expand this shift operation out to 4125/// smaller elements. If we can't find a way that is more efficient than a 4126/// libcall on this target, return false. Otherwise, return true with the 4127/// low-parts expanded into Lo and Hi. 4128bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 4129 SDOperand &Lo, SDOperand &Hi) { 4130 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 4131 "This is not a shift!"); 4132 4133 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 4134 SDOperand ShAmt = LegalizeOp(Amt); 4135 MVT::ValueType ShTy = ShAmt.getValueType(); 4136 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 4137 unsigned NVTBits = MVT::getSizeInBits(NVT); 4138 4139 // Handle the case when Amt is an immediate. Other cases are currently broken 4140 // and are disabled. 4141 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 4142 unsigned Cst = CN->getValue(); 4143 // Expand the incoming operand to be shifted, so that we have its parts 4144 SDOperand InL, InH; 4145 ExpandOp(Op, InL, InH); 4146 switch(Opc) { 4147 case ISD::SHL: 4148 if (Cst > VTBits) { 4149 Lo = DAG.getConstant(0, NVT); 4150 Hi = DAG.getConstant(0, NVT); 4151 } else if (Cst > NVTBits) { 4152 Lo = DAG.getConstant(0, NVT); 4153 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 4154 } else if (Cst == NVTBits) { 4155 Lo = DAG.getConstant(0, NVT); 4156 Hi = InL; 4157 } else { 4158 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 4159 Hi = DAG.getNode(ISD::OR, NVT, 4160 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 4161 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 4162 } 4163 return true; 4164 case ISD::SRL: 4165 if (Cst > VTBits) { 4166 Lo = DAG.getConstant(0, NVT); 4167 Hi = DAG.getConstant(0, NVT); 4168 } else if (Cst > NVTBits) { 4169 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 4170 Hi = DAG.getConstant(0, NVT); 4171 } else if (Cst == NVTBits) { 4172 Lo = InH; 4173 Hi = DAG.getConstant(0, NVT); 4174 } else { 4175 Lo = DAG.getNode(ISD::OR, NVT, 4176 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4177 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4178 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 4179 } 4180 return true; 4181 case ISD::SRA: 4182 if (Cst > VTBits) { 4183 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 4184 DAG.getConstant(NVTBits-1, ShTy)); 4185 } else if (Cst > NVTBits) { 4186 Lo = DAG.getNode(ISD::SRA, NVT, InH, 4187 DAG.getConstant(Cst-NVTBits, ShTy)); 4188 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4189 DAG.getConstant(NVTBits-1, ShTy)); 4190 } else if (Cst == NVTBits) { 4191 Lo = InH; 4192 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4193 DAG.getConstant(NVTBits-1, ShTy)); 4194 } else { 4195 Lo = DAG.getNode(ISD::OR, NVT, 4196 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4197 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4198 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 4199 } 4200 return true; 4201 } 4202 } 4203 4204 // Okay, the shift amount isn't constant. However, if we can tell that it is 4205 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 4206 uint64_t Mask = NVTBits, KnownZero, KnownOne; 4207 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 4208 4209 // If we know that the high bit of the shift amount is one, then we can do 4210 // this as a couple of simple shifts. 4211 if (KnownOne & Mask) { 4212 // Mask out the high bit, which we know is set. 4213 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 4214 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4215 4216 // Expand the incoming operand to be shifted, so that we have its parts 4217 SDOperand InL, InH; 4218 ExpandOp(Op, InL, InH); 4219 switch(Opc) { 4220 case ISD::SHL: 4221 Lo = DAG.getConstant(0, NVT); // Low part is zero. 4222 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 4223 return true; 4224 case ISD::SRL: 4225 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 4226 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 4227 return true; 4228 case ISD::SRA: 4229 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 4230 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4231 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 4232 return true; 4233 } 4234 } 4235 4236 // If we know that the high bit of the shift amount is zero, then we can do 4237 // this as a couple of simple shifts. 4238 if (KnownZero & Mask) { 4239 // Compute 32-amt. 4240 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 4241 DAG.getConstant(NVTBits, Amt.getValueType()), 4242 Amt); 4243 4244 // Expand the incoming operand to be shifted, so that we have its parts 4245 SDOperand InL, InH; 4246 ExpandOp(Op, InL, InH); 4247 switch(Opc) { 4248 case ISD::SHL: 4249 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 4250 Hi = DAG.getNode(ISD::OR, NVT, 4251 DAG.getNode(ISD::SHL, NVT, InH, Amt), 4252 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 4253 return true; 4254 case ISD::SRL: 4255 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 4256 Lo = DAG.getNode(ISD::OR, NVT, 4257 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4258 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4259 return true; 4260 case ISD::SRA: 4261 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 4262 Lo = DAG.getNode(ISD::OR, NVT, 4263 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4264 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4265 return true; 4266 } 4267 } 4268 4269 return false; 4270} 4271 4272 4273// ExpandLibCall - Expand a node into a call to a libcall. If the result value 4274// does not fit into a register, return the lo part and set the hi part to the 4275// by-reg argument. If it does fit into a single register, return the result 4276// and leave the Hi part unset. 4277SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 4278 bool isSigned, SDOperand &Hi) { 4279 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 4280 // The input chain to this libcall is the entry node of the function. 4281 // Legalizing the call will automatically add the previous call to the 4282 // dependence. 4283 SDOperand InChain = DAG.getEntryNode(); 4284 4285 TargetLowering::ArgListTy Args; 4286 TargetLowering::ArgListEntry Entry; 4287 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4288 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 4289 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 4290 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 4291 Entry.isSExt = isSigned; 4292 Args.push_back(Entry); 4293 } 4294 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 4295 4296 // Splice the libcall in wherever FindInputOutputChains tells us to. 4297 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 4298 std::pair<SDOperand,SDOperand> CallInfo = 4299 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false, 4300 Callee, Args, DAG); 4301 4302 // Legalize the call sequence, starting with the chain. This will advance 4303 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 4304 // was added by LowerCallTo (guaranteeing proper serialization of calls). 4305 LegalizeOp(CallInfo.second); 4306 SDOperand Result; 4307 switch (getTypeAction(CallInfo.first.getValueType())) { 4308 default: assert(0 && "Unknown thing"); 4309 case Legal: 4310 Result = CallInfo.first; 4311 break; 4312 case Expand: 4313 ExpandOp(CallInfo.first, Result, Hi); 4314 break; 4315 } 4316 return Result; 4317} 4318 4319 4320/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 4321/// 4322SDOperand SelectionDAGLegalize:: 4323ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 4324 assert(getTypeAction(Source.getValueType()) == Expand && 4325 "This is not an expansion!"); 4326 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 4327 4328 if (!isSigned) { 4329 assert(Source.getValueType() == MVT::i64 && 4330 "This only works for 64-bit -> FP"); 4331 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 4332 // incoming integer is set. To handle this, we dynamically test to see if 4333 // it is set, and, if so, add a fudge factor. 4334 SDOperand Lo, Hi; 4335 ExpandOp(Source, Lo, Hi); 4336 4337 // If this is unsigned, and not supported, first perform the conversion to 4338 // signed, then adjust the result if the sign bit is set. 4339 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 4340 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 4341 4342 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 4343 DAG.getConstant(0, Hi.getValueType()), 4344 ISD::SETLT); 4345 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4346 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4347 SignSet, Four, Zero); 4348 uint64_t FF = 0x5f800000ULL; 4349 if (TLI.isLittleEndian()) FF <<= 32; 4350 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4351 4352 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4353 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4354 SDOperand FudgeInReg; 4355 if (DestTy == MVT::f32) 4356 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4357 else { 4358 assert(DestTy == MVT::f64 && "Unexpected conversion"); 4359 // FIXME: Avoid the extend by construction the right constantpool? 4360 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 4361 CPIdx, NULL, 0, MVT::f32); 4362 } 4363 MVT::ValueType SCVT = SignedConv.getValueType(); 4364 if (SCVT != DestTy) { 4365 // Destination type needs to be expanded as well. The FADD now we are 4366 // constructing will be expanded into a libcall. 4367 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { 4368 assert(SCVT == MVT::i32 && DestTy == MVT::f64); 4369 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, 4370 SignedConv, SignedConv.getValue(1)); 4371 } 4372 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 4373 } 4374 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 4375 } 4376 4377 // Check to see if the target has a custom way to lower this. If so, use it. 4378 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 4379 default: assert(0 && "This action not implemented for this operation!"); 4380 case TargetLowering::Legal: 4381 case TargetLowering::Expand: 4382 break; // This case is handled below. 4383 case TargetLowering::Custom: { 4384 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 4385 Source), DAG); 4386 if (NV.Val) 4387 return LegalizeOp(NV); 4388 break; // The target decided this was legal after all 4389 } 4390 } 4391 4392 // Expand the source, then glue it back together for the call. We must expand 4393 // the source in case it is shared (this pass of legalize must traverse it). 4394 SDOperand SrcLo, SrcHi; 4395 ExpandOp(Source, SrcLo, SrcHi); 4396 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 4397 4398 RTLIB::Libcall LC; 4399 if (DestTy == MVT::f32) 4400 LC = RTLIB::SINTTOFP_I64_F32; 4401 else { 4402 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 4403 LC = RTLIB::SINTTOFP_I64_F64; 4404 } 4405 4406 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 4407 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 4408 SDOperand UnusedHiPart; 4409 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 4410 UnusedHiPart); 4411} 4412 4413/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 4414/// INT_TO_FP operation of the specified operand when the target requests that 4415/// we expand it. At this point, we know that the result and operand types are 4416/// legal for the target. 4417SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 4418 SDOperand Op0, 4419 MVT::ValueType DestVT) { 4420 if (Op0.getValueType() == MVT::i32) { 4421 // simple 32-bit [signed|unsigned] integer to float/double expansion 4422 4423 // get the stack frame index of a 8 byte buffer, pessimistically aligned 4424 MachineFunction &MF = DAG.getMachineFunction(); 4425 const Type *F64Type = MVT::getTypeForValueType(MVT::f64); 4426 unsigned StackAlign = 4427 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type); 4428 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign); 4429 // get address of 8 byte buffer 4430 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4431 // word offset constant for Hi/Lo address computation 4432 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 4433 // set up Hi and Lo (into buffer) address based on endian 4434 SDOperand Hi = StackSlot; 4435 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 4436 if (TLI.isLittleEndian()) 4437 std::swap(Hi, Lo); 4438 4439 // if signed map to unsigned space 4440 SDOperand Op0Mapped; 4441 if (isSigned) { 4442 // constant used to invert sign bit (signed to unsigned mapping) 4443 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 4444 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 4445 } else { 4446 Op0Mapped = Op0; 4447 } 4448 // store the lo of the constructed double - based on integer input 4449 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 4450 Op0Mapped, Lo, NULL, 0); 4451 // initial hi portion of constructed double 4452 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 4453 // store the hi of the constructed double - biased exponent 4454 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 4455 // load the constructed double 4456 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 4457 // FP constant to bias correct the final result 4458 SDOperand Bias = DAG.getConstantFP(isSigned ? 4459 BitsToDouble(0x4330000080000000ULL) 4460 : BitsToDouble(0x4330000000000000ULL), 4461 MVT::f64); 4462 // subtract the bias 4463 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 4464 // final result 4465 SDOperand Result; 4466 // handle final rounding 4467 if (DestVT == MVT::f64) { 4468 // do nothing 4469 Result = Sub; 4470 } else { 4471 // if f32 then cast to f32 4472 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 4473 } 4474 return Result; 4475 } 4476 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 4477 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 4478 4479 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 4480 DAG.getConstant(0, Op0.getValueType()), 4481 ISD::SETLT); 4482 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4483 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4484 SignSet, Four, Zero); 4485 4486 // If the sign bit of the integer is set, the large number will be treated 4487 // as a negative number. To counteract this, the dynamic code adds an 4488 // offset depending on the data type. 4489 uint64_t FF; 4490 switch (Op0.getValueType()) { 4491 default: assert(0 && "Unsupported integer type!"); 4492 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 4493 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 4494 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 4495 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 4496 } 4497 if (TLI.isLittleEndian()) FF <<= 32; 4498 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4499 4500 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4501 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4502 SDOperand FudgeInReg; 4503 if (DestVT == MVT::f32) 4504 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4505 else { 4506 assert(DestVT == MVT::f64 && "Unexpected conversion"); 4507 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 4508 DAG.getEntryNode(), CPIdx, 4509 NULL, 0, MVT::f32)); 4510 } 4511 4512 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 4513} 4514 4515/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 4516/// *INT_TO_FP operation of the specified operand when the target requests that 4517/// we promote it. At this point, we know that the result and operand types are 4518/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 4519/// operation that takes a larger input. 4520SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 4521 MVT::ValueType DestVT, 4522 bool isSigned) { 4523 // First step, figure out the appropriate *INT_TO_FP operation to use. 4524 MVT::ValueType NewInTy = LegalOp.getValueType(); 4525 4526 unsigned OpToUse = 0; 4527 4528 // Scan for the appropriate larger type to use. 4529 while (1) { 4530 NewInTy = (MVT::ValueType)(NewInTy+1); 4531 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 4532 4533 // If the target supports SINT_TO_FP of this type, use it. 4534 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 4535 default: break; 4536 case TargetLowering::Legal: 4537 if (!TLI.isTypeLegal(NewInTy)) 4538 break; // Can't use this datatype. 4539 // FALL THROUGH. 4540 case TargetLowering::Custom: 4541 OpToUse = ISD::SINT_TO_FP; 4542 break; 4543 } 4544 if (OpToUse) break; 4545 if (isSigned) continue; 4546 4547 // If the target supports UINT_TO_FP of this type, use it. 4548 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 4549 default: break; 4550 case TargetLowering::Legal: 4551 if (!TLI.isTypeLegal(NewInTy)) 4552 break; // Can't use this datatype. 4553 // FALL THROUGH. 4554 case TargetLowering::Custom: 4555 OpToUse = ISD::UINT_TO_FP; 4556 break; 4557 } 4558 if (OpToUse) break; 4559 4560 // Otherwise, try a larger type. 4561 } 4562 4563 // Okay, we found the operation and type to use. Zero extend our input to the 4564 // desired type then run the operation on it. 4565 return DAG.getNode(OpToUse, DestVT, 4566 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 4567 NewInTy, LegalOp)); 4568} 4569 4570/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 4571/// FP_TO_*INT operation of the specified operand when the target requests that 4572/// we promote it. At this point, we know that the result and operand types are 4573/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 4574/// operation that returns a larger result. 4575SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 4576 MVT::ValueType DestVT, 4577 bool isSigned) { 4578 // First step, figure out the appropriate FP_TO*INT operation to use. 4579 MVT::ValueType NewOutTy = DestVT; 4580 4581 unsigned OpToUse = 0; 4582 4583 // Scan for the appropriate larger type to use. 4584 while (1) { 4585 NewOutTy = (MVT::ValueType)(NewOutTy+1); 4586 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 4587 4588 // If the target supports FP_TO_SINT returning this type, use it. 4589 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 4590 default: break; 4591 case TargetLowering::Legal: 4592 if (!TLI.isTypeLegal(NewOutTy)) 4593 break; // Can't use this datatype. 4594 // FALL THROUGH. 4595 case TargetLowering::Custom: 4596 OpToUse = ISD::FP_TO_SINT; 4597 break; 4598 } 4599 if (OpToUse) break; 4600 4601 // If the target supports FP_TO_UINT of this type, use it. 4602 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 4603 default: break; 4604 case TargetLowering::Legal: 4605 if (!TLI.isTypeLegal(NewOutTy)) 4606 break; // Can't use this datatype. 4607 // FALL THROUGH. 4608 case TargetLowering::Custom: 4609 OpToUse = ISD::FP_TO_UINT; 4610 break; 4611 } 4612 if (OpToUse) break; 4613 4614 // Otherwise, try a larger type. 4615 } 4616 4617 // Okay, we found the operation and type to use. Truncate the result of the 4618 // extended FP_TO_*INT operation to the desired size. 4619 return DAG.getNode(ISD::TRUNCATE, DestVT, 4620 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 4621} 4622 4623/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 4624/// 4625SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 4626 MVT::ValueType VT = Op.getValueType(); 4627 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 4628 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 4629 switch (VT) { 4630 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 4631 case MVT::i16: 4632 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4633 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4634 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 4635 case MVT::i32: 4636 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4637 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4638 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4639 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4640 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 4641 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 4642 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4643 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4644 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4645 case MVT::i64: 4646 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 4647 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 4648 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4649 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4650 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4651 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4652 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 4653 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 4654 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 4655 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 4656 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 4657 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 4658 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 4659 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 4660 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 4661 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 4662 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4663 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4664 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 4665 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4666 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 4667 } 4668} 4669 4670/// ExpandBitCount - Expand the specified bitcount instruction into operations. 4671/// 4672SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 4673 switch (Opc) { 4674 default: assert(0 && "Cannot expand this yet!"); 4675 case ISD::CTPOP: { 4676 static const uint64_t mask[6] = { 4677 0x5555555555555555ULL, 0x3333333333333333ULL, 4678 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 4679 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 4680 }; 4681 MVT::ValueType VT = Op.getValueType(); 4682 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4683 unsigned len = MVT::getSizeInBits(VT); 4684 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4685 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 4686 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 4687 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4688 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 4689 DAG.getNode(ISD::AND, VT, 4690 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 4691 } 4692 return Op; 4693 } 4694 case ISD::CTLZ: { 4695 // for now, we do this: 4696 // x = x | (x >> 1); 4697 // x = x | (x >> 2); 4698 // ... 4699 // x = x | (x >>16); 4700 // x = x | (x >>32); // for 64-bit input 4701 // return popcount(~x); 4702 // 4703 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 4704 MVT::ValueType VT = Op.getValueType(); 4705 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4706 unsigned len = MVT::getSizeInBits(VT); 4707 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4708 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4709 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 4710 } 4711 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 4712 return DAG.getNode(ISD::CTPOP, VT, Op); 4713 } 4714 case ISD::CTTZ: { 4715 // for now, we use: { return popcount(~x & (x - 1)); } 4716 // unless the target has ctlz but not ctpop, in which case we use: 4717 // { return 32 - nlz(~x & (x-1)); } 4718 // see also http://www.hackersdelight.org/HDcode/ntz.cc 4719 MVT::ValueType VT = Op.getValueType(); 4720 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 4721 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 4722 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 4723 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 4724 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 4725 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 4726 TLI.isOperationLegal(ISD::CTLZ, VT)) 4727 return DAG.getNode(ISD::SUB, VT, 4728 DAG.getConstant(MVT::getSizeInBits(VT), VT), 4729 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 4730 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 4731 } 4732 } 4733} 4734 4735/// ExpandOp - Expand the specified SDOperand into its two component pieces 4736/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 4737/// LegalizeNodes map is filled in for any results that are not expanded, the 4738/// ExpandedNodes map is filled in for any results that are expanded, and the 4739/// Lo/Hi values are returned. 4740void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 4741 MVT::ValueType VT = Op.getValueType(); 4742 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4743 SDNode *Node = Op.Val; 4744 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 4745 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 4746 VT == MVT::Vector) && 4747 "Cannot expand to FP value or to larger int value!"); 4748 4749 // See if we already expanded it. 4750 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 4751 = ExpandedNodes.find(Op); 4752 if (I != ExpandedNodes.end()) { 4753 Lo = I->second.first; 4754 Hi = I->second.second; 4755 return; 4756 } 4757 4758 switch (Node->getOpcode()) { 4759 case ISD::CopyFromReg: 4760 assert(0 && "CopyFromReg must be legal!"); 4761 default: 4762#ifndef NDEBUG 4763 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4764#endif 4765 assert(0 && "Do not know how to expand this operator!"); 4766 abort(); 4767 case ISD::UNDEF: 4768 NVT = TLI.getTypeToExpandTo(VT); 4769 Lo = DAG.getNode(ISD::UNDEF, NVT); 4770 Hi = DAG.getNode(ISD::UNDEF, NVT); 4771 break; 4772 case ISD::Constant: { 4773 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 4774 Lo = DAG.getConstant(Cst, NVT); 4775 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 4776 break; 4777 } 4778 case ISD::ConstantFP: { 4779 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 4780 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 4781 if (getTypeAction(Lo.getValueType()) == Expand) 4782 ExpandOp(Lo, Lo, Hi); 4783 break; 4784 } 4785 case ISD::BUILD_PAIR: 4786 // Return the operands. 4787 Lo = Node->getOperand(0); 4788 Hi = Node->getOperand(1); 4789 break; 4790 4791 case ISD::SIGN_EXTEND_INREG: 4792 ExpandOp(Node->getOperand(0), Lo, Hi); 4793 // sext_inreg the low part if needed. 4794 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 4795 4796 // The high part gets the sign extension from the lo-part. This handles 4797 // things like sextinreg V:i64 from i8. 4798 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4799 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 4800 TLI.getShiftAmountTy())); 4801 break; 4802 4803 case ISD::BSWAP: { 4804 ExpandOp(Node->getOperand(0), Lo, Hi); 4805 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 4806 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 4807 Lo = TempLo; 4808 break; 4809 } 4810 4811 case ISD::CTPOP: 4812 ExpandOp(Node->getOperand(0), Lo, Hi); 4813 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 4814 DAG.getNode(ISD::CTPOP, NVT, Lo), 4815 DAG.getNode(ISD::CTPOP, NVT, Hi)); 4816 Hi = DAG.getConstant(0, NVT); 4817 break; 4818 4819 case ISD::CTLZ: { 4820 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 4821 ExpandOp(Node->getOperand(0), Lo, Hi); 4822 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4823 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 4824 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 4825 ISD::SETNE); 4826 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 4827 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 4828 4829 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 4830 Hi = DAG.getConstant(0, NVT); 4831 break; 4832 } 4833 4834 case ISD::CTTZ: { 4835 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 4836 ExpandOp(Node->getOperand(0), Lo, Hi); 4837 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4838 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 4839 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 4840 ISD::SETNE); 4841 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 4842 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 4843 4844 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 4845 Hi = DAG.getConstant(0, NVT); 4846 break; 4847 } 4848 4849 case ISD::VAARG: { 4850 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 4851 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 4852 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 4853 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 4854 4855 // Remember that we legalized the chain. 4856 Hi = LegalizeOp(Hi); 4857 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 4858 if (!TLI.isLittleEndian()) 4859 std::swap(Lo, Hi); 4860 break; 4861 } 4862 4863 case ISD::LOAD: { 4864 LoadSDNode *LD = cast<LoadSDNode>(Node); 4865 SDOperand Ch = LD->getChain(); // Legalize the chain. 4866 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 4867 ISD::LoadExtType ExtType = LD->getExtensionType(); 4868 4869 if (ExtType == ISD::NON_EXTLOAD) { 4870 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),LD->getSrcValueOffset()); 4871 if (VT == MVT::f32 || VT == MVT::f64) { 4872 // f32->i32 or f64->i64 one to one expansion. 4873 // Remember that we legalized the chain. 4874 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4875 // Recursively expand the new load. 4876 if (getTypeAction(NVT) == Expand) 4877 ExpandOp(Lo, Lo, Hi); 4878 break; 4879 } 4880 4881 // Increment the pointer to the other half. 4882 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 4883 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4884 getIntPtrConstant(IncrementSize)); 4885 // FIXME: This creates a bogus srcvalue! 4886 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),LD->getSrcValueOffset()); 4887 4888 // Build a factor node to remember that this load is independent of the 4889 // other one. 4890 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 4891 Hi.getValue(1)); 4892 4893 // Remember that we legalized the chain. 4894 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 4895 if (!TLI.isLittleEndian()) 4896 std::swap(Lo, Hi); 4897 } else { 4898 MVT::ValueType EVT = LD->getLoadedVT(); 4899 4900 if (VT == MVT::f64 && EVT == MVT::f32) { 4901 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 4902 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 4903 LD->getSrcValueOffset()); 4904 // Remember that we legalized the chain. 4905 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 4906 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 4907 break; 4908 } 4909 4910 if (EVT == NVT) 4911 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 4912 LD->getSrcValueOffset()); 4913 else 4914 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 4915 LD->getSrcValueOffset(), EVT); 4916 4917 // Remember that we legalized the chain. 4918 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4919 4920 if (ExtType == ISD::SEXTLOAD) { 4921 // The high part is obtained by SRA'ing all but one of the bits of the 4922 // lo part. 4923 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4924 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4925 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 4926 } else if (ExtType == ISD::ZEXTLOAD) { 4927 // The high part is just a zero. 4928 Hi = DAG.getConstant(0, NVT); 4929 } else /* if (ExtType == ISD::EXTLOAD) */ { 4930 // The high part is undefined. 4931 Hi = DAG.getNode(ISD::UNDEF, NVT); 4932 } 4933 } 4934 break; 4935 } 4936 case ISD::AND: 4937 case ISD::OR: 4938 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 4939 SDOperand LL, LH, RL, RH; 4940 ExpandOp(Node->getOperand(0), LL, LH); 4941 ExpandOp(Node->getOperand(1), RL, RH); 4942 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 4943 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 4944 break; 4945 } 4946 case ISD::SELECT: { 4947 SDOperand LL, LH, RL, RH; 4948 ExpandOp(Node->getOperand(1), LL, LH); 4949 ExpandOp(Node->getOperand(2), RL, RH); 4950 if (getTypeAction(NVT) == Expand) 4951 NVT = TLI.getTypeToExpandTo(NVT); 4952 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 4953 if (VT != MVT::f32) 4954 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 4955 break; 4956 } 4957 case ISD::SELECT_CC: { 4958 SDOperand TL, TH, FL, FH; 4959 ExpandOp(Node->getOperand(2), TL, TH); 4960 ExpandOp(Node->getOperand(3), FL, FH); 4961 if (getTypeAction(NVT) == Expand) 4962 NVT = TLI.getTypeToExpandTo(NVT); 4963 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4964 Node->getOperand(1), TL, FL, Node->getOperand(4)); 4965 if (VT != MVT::f32) 4966 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4967 Node->getOperand(1), TH, FH, Node->getOperand(4)); 4968 break; 4969 } 4970 case ISD::ANY_EXTEND: 4971 // The low part is any extension of the input (which degenerates to a copy). 4972 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 4973 // The high part is undefined. 4974 Hi = DAG.getNode(ISD::UNDEF, NVT); 4975 break; 4976 case ISD::SIGN_EXTEND: { 4977 // The low part is just a sign extension of the input (which degenerates to 4978 // a copy). 4979 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 4980 4981 // The high part is obtained by SRA'ing all but one of the bits of the lo 4982 // part. 4983 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4984 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4985 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 4986 break; 4987 } 4988 case ISD::ZERO_EXTEND: 4989 // The low part is just a zero extension of the input (which degenerates to 4990 // a copy). 4991 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4992 4993 // The high part is just a zero. 4994 Hi = DAG.getConstant(0, NVT); 4995 break; 4996 4997 case ISD::TRUNCATE: { 4998 // The input value must be larger than this value. Expand *it*. 4999 SDOperand NewLo; 5000 ExpandOp(Node->getOperand(0), NewLo, Hi); 5001 5002 // The low part is now either the right size, or it is closer. If not the 5003 // right size, make an illegal truncate so we recursively expand it. 5004 if (NewLo.getValueType() != Node->getValueType(0)) 5005 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 5006 ExpandOp(NewLo, Lo, Hi); 5007 break; 5008 } 5009 5010 case ISD::BIT_CONVERT: { 5011 SDOperand Tmp; 5012 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 5013 // If the target wants to, allow it to lower this itself. 5014 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5015 case Expand: assert(0 && "cannot expand FP!"); 5016 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 5017 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 5018 } 5019 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 5020 } 5021 5022 // f32 / f64 must be expanded to i32 / i64. 5023 if (VT == MVT::f32 || VT == MVT::f64) { 5024 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5025 if (getTypeAction(NVT) == Expand) 5026 ExpandOp(Lo, Lo, Hi); 5027 break; 5028 } 5029 5030 // If source operand will be expanded to the same type as VT, i.e. 5031 // i64 <- f64, i32 <- f32, expand the source operand instead. 5032 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 5033 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 5034 ExpandOp(Node->getOperand(0), Lo, Hi); 5035 break; 5036 } 5037 5038 // Turn this into a load/store pair by default. 5039 if (Tmp.Val == 0) 5040 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0)); 5041 5042 ExpandOp(Tmp, Lo, Hi); 5043 break; 5044 } 5045 5046 case ISD::READCYCLECOUNTER: 5047 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 5048 TargetLowering::Custom && 5049 "Must custom expand ReadCycleCounter"); 5050 Lo = TLI.LowerOperation(Op, DAG); 5051 assert(Lo.Val && "Node must be custom expanded!"); 5052 Hi = Lo.getValue(1); 5053 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 5054 LegalizeOp(Lo.getValue(2))); 5055 break; 5056 5057 // These operators cannot be expanded directly, emit them as calls to 5058 // library functions. 5059 case ISD::FP_TO_SINT: { 5060 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 5061 SDOperand Op; 5062 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5063 case Expand: assert(0 && "cannot expand FP!"); 5064 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5065 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5066 } 5067 5068 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 5069 5070 // Now that the custom expander is done, expand the result, which is still 5071 // VT. 5072 if (Op.Val) { 5073 ExpandOp(Op, Lo, Hi); 5074 break; 5075 } 5076 } 5077 5078 RTLIB::Libcall LC; 5079 if (Node->getOperand(0).getValueType() == MVT::f32) 5080 LC = RTLIB::FPTOSINT_F32_I64; 5081 else 5082 LC = RTLIB::FPTOSINT_F64_I64; 5083 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5084 false/*sign irrelevant*/, Hi); 5085 break; 5086 } 5087 5088 case ISD::FP_TO_UINT: { 5089 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 5090 SDOperand Op; 5091 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5092 case Expand: assert(0 && "cannot expand FP!"); 5093 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5094 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5095 } 5096 5097 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 5098 5099 // Now that the custom expander is done, expand the result. 5100 if (Op.Val) { 5101 ExpandOp(Op, Lo, Hi); 5102 break; 5103 } 5104 } 5105 5106 RTLIB::Libcall LC; 5107 if (Node->getOperand(0).getValueType() == MVT::f32) 5108 LC = RTLIB::FPTOUINT_F32_I64; 5109 else 5110 LC = RTLIB::FPTOUINT_F64_I64; 5111 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5112 false/*sign irrelevant*/, Hi); 5113 break; 5114 } 5115 5116 case ISD::SHL: { 5117 // If the target wants custom lowering, do so. 5118 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5119 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 5120 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 5121 Op = TLI.LowerOperation(Op, DAG); 5122 if (Op.Val) { 5123 // Now that the custom expander is done, expand the result, which is 5124 // still VT. 5125 ExpandOp(Op, Lo, Hi); 5126 break; 5127 } 5128 } 5129 5130 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 5131 // this X << 1 as X+X. 5132 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 5133 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 5134 TLI.isOperationLegal(ISD::ADDE, NVT)) { 5135 SDOperand LoOps[2], HiOps[3]; 5136 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 5137 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 5138 LoOps[1] = LoOps[0]; 5139 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5140 5141 HiOps[1] = HiOps[0]; 5142 HiOps[2] = Lo.getValue(1); 5143 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5144 break; 5145 } 5146 } 5147 5148 // If we can emit an efficient shift operation, do so now. 5149 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5150 break; 5151 5152 // If this target supports SHL_PARTS, use it. 5153 TargetLowering::LegalizeAction Action = 5154 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 5155 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5156 Action == TargetLowering::Custom) { 5157 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5158 break; 5159 } 5160 5161 // Otherwise, emit a libcall. 5162 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 5163 false/*left shift=unsigned*/, Hi); 5164 break; 5165 } 5166 5167 case ISD::SRA: { 5168 // If the target wants custom lowering, do so. 5169 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5170 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 5171 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 5172 Op = TLI.LowerOperation(Op, DAG); 5173 if (Op.Val) { 5174 // Now that the custom expander is done, expand the result, which is 5175 // still VT. 5176 ExpandOp(Op, Lo, Hi); 5177 break; 5178 } 5179 } 5180 5181 // If we can emit an efficient shift operation, do so now. 5182 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5183 break; 5184 5185 // If this target supports SRA_PARTS, use it. 5186 TargetLowering::LegalizeAction Action = 5187 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 5188 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5189 Action == TargetLowering::Custom) { 5190 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5191 break; 5192 } 5193 5194 // Otherwise, emit a libcall. 5195 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 5196 true/*ashr is signed*/, Hi); 5197 break; 5198 } 5199 5200 case ISD::SRL: { 5201 // If the target wants custom lowering, do so. 5202 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5203 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 5204 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 5205 Op = TLI.LowerOperation(Op, DAG); 5206 if (Op.Val) { 5207 // Now that the custom expander is done, expand the result, which is 5208 // still VT. 5209 ExpandOp(Op, Lo, Hi); 5210 break; 5211 } 5212 } 5213 5214 // If we can emit an efficient shift operation, do so now. 5215 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5216 break; 5217 5218 // If this target supports SRL_PARTS, use it. 5219 TargetLowering::LegalizeAction Action = 5220 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 5221 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5222 Action == TargetLowering::Custom) { 5223 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5224 break; 5225 } 5226 5227 // Otherwise, emit a libcall. 5228 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 5229 false/*lshr is unsigned*/, Hi); 5230 break; 5231 } 5232 5233 case ISD::ADD: 5234 case ISD::SUB: { 5235 // If the target wants to custom expand this, let them. 5236 if (TLI.getOperationAction(Node->getOpcode(), VT) == 5237 TargetLowering::Custom) { 5238 Op = TLI.LowerOperation(Op, DAG); 5239 if (Op.Val) { 5240 ExpandOp(Op, Lo, Hi); 5241 break; 5242 } 5243 } 5244 5245 // Expand the subcomponents. 5246 SDOperand LHSL, LHSH, RHSL, RHSH; 5247 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5248 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5249 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5250 SDOperand LoOps[2], HiOps[3]; 5251 LoOps[0] = LHSL; 5252 LoOps[1] = RHSL; 5253 HiOps[0] = LHSH; 5254 HiOps[1] = RHSH; 5255 if (Node->getOpcode() == ISD::ADD) { 5256 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5257 HiOps[2] = Lo.getValue(1); 5258 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5259 } else { 5260 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5261 HiOps[2] = Lo.getValue(1); 5262 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5263 } 5264 break; 5265 } 5266 5267 case ISD::ADDC: 5268 case ISD::SUBC: { 5269 // Expand the subcomponents. 5270 SDOperand LHSL, LHSH, RHSL, RHSH; 5271 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5272 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5273 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5274 SDOperand LoOps[2] = { LHSL, RHSL }; 5275 SDOperand HiOps[3] = { LHSH, RHSH }; 5276 5277 if (Node->getOpcode() == ISD::ADDC) { 5278 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5279 HiOps[2] = Lo.getValue(1); 5280 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5281 } else { 5282 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5283 HiOps[2] = Lo.getValue(1); 5284 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5285 } 5286 // Remember that we legalized the flag. 5287 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5288 break; 5289 } 5290 case ISD::ADDE: 5291 case ISD::SUBE: { 5292 // Expand the subcomponents. 5293 SDOperand LHSL, LHSH, RHSL, RHSH; 5294 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5295 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5296 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5297 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 5298 SDOperand HiOps[3] = { LHSH, RHSH }; 5299 5300 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 5301 HiOps[2] = Lo.getValue(1); 5302 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 5303 5304 // Remember that we legalized the flag. 5305 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5306 break; 5307 } 5308 case ISD::MUL: { 5309 // If the target wants to custom expand this, let them. 5310 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 5311 SDOperand New = TLI.LowerOperation(Op, DAG); 5312 if (New.Val) { 5313 ExpandOp(New, Lo, Hi); 5314 break; 5315 } 5316 } 5317 5318 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 5319 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 5320 if (HasMULHS || HasMULHU) { 5321 SDOperand LL, LH, RL, RH; 5322 ExpandOp(Node->getOperand(0), LL, LH); 5323 ExpandOp(Node->getOperand(1), RL, RH); 5324 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 5325 // FIXME: Move this to the dag combiner. 5326 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 5327 // extended the sign bit of the low half through the upper half, and if so 5328 // emit a MULHS instead of the alternate sequence that is valid for any 5329 // i64 x i64 multiply. 5330 if (HasMULHS && 5331 // is RH an extension of the sign bit of RL? 5332 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 5333 RH.getOperand(1).getOpcode() == ISD::Constant && 5334 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 5335 // is LH an extension of the sign bit of LL? 5336 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 5337 LH.getOperand(1).getOpcode() == ISD::Constant && 5338 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 5339 // Low part: 5340 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5341 // High part: 5342 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 5343 break; 5344 } else if (HasMULHU) { 5345 // Low part: 5346 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5347 5348 // High part: 5349 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 5350 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 5351 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 5352 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 5353 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 5354 break; 5355 } 5356 } 5357 5358 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 5359 false/*sign irrelevant*/, Hi); 5360 break; 5361 } 5362 case ISD::SDIV: 5363 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 5364 break; 5365 case ISD::UDIV: 5366 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 5367 break; 5368 case ISD::SREM: 5369 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 5370 break; 5371 case ISD::UREM: 5372 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 5373 break; 5374 5375 case ISD::FADD: 5376 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5377 ? RTLIB::ADD_F32 : RTLIB::ADD_F64), 5378 Node, false, Hi); 5379 break; 5380 case ISD::FSUB: 5381 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5382 ? RTLIB::SUB_F32 : RTLIB::SUB_F64), 5383 Node, false, Hi); 5384 break; 5385 case ISD::FMUL: 5386 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5387 ? RTLIB::MUL_F32 : RTLIB::MUL_F64), 5388 Node, false, Hi); 5389 break; 5390 case ISD::FDIV: 5391 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5392 ? RTLIB::DIV_F32 : RTLIB::DIV_F64), 5393 Node, false, Hi); 5394 break; 5395 case ISD::FP_EXTEND: 5396 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 5397 break; 5398 case ISD::FP_ROUND: 5399 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 5400 break; 5401 case ISD::FSQRT: 5402 case ISD::FSIN: 5403 case ISD::FCOS: { 5404 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5405 switch(Node->getOpcode()) { 5406 case ISD::FSQRT: 5407 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64; 5408 break; 5409 case ISD::FSIN: 5410 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 5411 break; 5412 case ISD::FCOS: 5413 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64; 5414 break; 5415 default: assert(0 && "Unreachable!"); 5416 } 5417 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 5418 break; 5419 } 5420 case ISD::FABS: { 5421 SDOperand Mask = (VT == MVT::f64) 5422 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 5423 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 5424 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 5425 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5426 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 5427 if (getTypeAction(NVT) == Expand) 5428 ExpandOp(Lo, Lo, Hi); 5429 break; 5430 } 5431 case ISD::FNEG: { 5432 SDOperand Mask = (VT == MVT::f64) 5433 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 5434 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 5435 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 5436 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5437 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 5438 if (getTypeAction(NVT) == Expand) 5439 ExpandOp(Lo, Lo, Hi); 5440 break; 5441 } 5442 case ISD::FCOPYSIGN: { 5443 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 5444 if (getTypeAction(NVT) == Expand) 5445 ExpandOp(Lo, Lo, Hi); 5446 break; 5447 } 5448 case ISD::SINT_TO_FP: 5449 case ISD::UINT_TO_FP: { 5450 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 5451 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 5452 RTLIB::Libcall LC; 5453 if (Node->getOperand(0).getValueType() == MVT::i64) { 5454 if (VT == MVT::f32) 5455 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; 5456 else 5457 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; 5458 } else { 5459 if (VT == MVT::f32) 5460 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 5461 else 5462 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 5463 } 5464 5465 // Promote the operand if needed. 5466 if (getTypeAction(SrcVT) == Promote) { 5467 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 5468 Tmp = isSigned 5469 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 5470 DAG.getValueType(SrcVT)) 5471 : DAG.getZeroExtendInReg(Tmp, SrcVT); 5472 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 5473 } 5474 5475 const char *LibCall = TLI.getLibcallName(LC); 5476 if (LibCall) 5477 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi); 5478 else { 5479 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 5480 Node->getOperand(0)); 5481 if (getTypeAction(Lo.getValueType()) == Expand) 5482 ExpandOp(Lo, Lo, Hi); 5483 } 5484 break; 5485 } 5486 } 5487 5488 // Make sure the resultant values have been legalized themselves, unless this 5489 // is a type that requires multi-step expansion. 5490 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 5491 Lo = LegalizeOp(Lo); 5492 if (Hi.Val) 5493 // Don't legalize the high part if it is expanded to a single node. 5494 Hi = LegalizeOp(Hi); 5495 } 5496 5497 // Remember in a map if the values will be reused later. 5498 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 5499 assert(isNew && "Value already expanded?!?"); 5500} 5501 5502/// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 5503/// two smaller values of MVT::Vector type. 5504void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 5505 SDOperand &Hi) { 5506 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!"); 5507 SDNode *Node = Op.Val; 5508 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue(); 5509 assert(NumElements > 1 && "Cannot split a single element vector!"); 5510 unsigned NewNumElts = NumElements/2; 5511 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32); 5512 SDOperand TypeNode = *(Node->op_end()-1); 5513 5514 // See if we already split it. 5515 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5516 = SplitNodes.find(Op); 5517 if (I != SplitNodes.end()) { 5518 Lo = I->second.first; 5519 Hi = I->second.second; 5520 return; 5521 } 5522 5523 switch (Node->getOpcode()) { 5524 default: 5525#ifndef NDEBUG 5526 Node->dump(&DAG); 5527#endif 5528 assert(0 && "Unhandled operation in SplitVectorOp!"); 5529 case ISD::VBUILD_VECTOR: { 5530 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 5531 Node->op_begin()+NewNumElts); 5532 LoOps.push_back(NewNumEltsNode); 5533 LoOps.push_back(TypeNode); 5534 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size()); 5535 5536 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts, 5537 Node->op_end()-2); 5538 HiOps.push_back(NewNumEltsNode); 5539 HiOps.push_back(TypeNode); 5540 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size()); 5541 break; 5542 } 5543 case ISD::VCONCAT_VECTORS: { 5544 unsigned NewNumSubvectors = (Node->getNumOperands() - 2) / 2; 5545 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 5546 Node->op_begin()+NewNumSubvectors); 5547 LoOps.push_back(NewNumEltsNode); 5548 LoOps.push_back(TypeNode); 5549 Lo = DAG.getNode(ISD::VCONCAT_VECTORS, MVT::Vector, &LoOps[0], LoOps.size()); 5550 5551 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 5552 Node->op_end()-2); 5553 HiOps.push_back(NewNumEltsNode); 5554 HiOps.push_back(TypeNode); 5555 Hi = DAG.getNode(ISD::VCONCAT_VECTORS, MVT::Vector, &HiOps[0], HiOps.size()); 5556 break; 5557 } 5558 case ISD::VADD: 5559 case ISD::VSUB: 5560 case ISD::VMUL: 5561 case ISD::VSDIV: 5562 case ISD::VUDIV: 5563 case ISD::VAND: 5564 case ISD::VOR: 5565 case ISD::VXOR: { 5566 SDOperand LL, LH, RL, RH; 5567 SplitVectorOp(Node->getOperand(0), LL, LH); 5568 SplitVectorOp(Node->getOperand(1), RL, RH); 5569 5570 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, 5571 NewNumEltsNode, TypeNode); 5572 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, 5573 NewNumEltsNode, TypeNode); 5574 break; 5575 } 5576 case ISD::VLOAD: { 5577 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5578 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5579 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 5580 5581 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 5582 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8; 5583 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5584 getIntPtrConstant(IncrementSize)); 5585 // FIXME: This creates a bogus srcvalue! 5586 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 5587 5588 // Build a factor node to remember that this load is independent of the 5589 // other one. 5590 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5591 Hi.getValue(1)); 5592 5593 // Remember that we legalized the chain. 5594 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5595 break; 5596 } 5597 case ISD::VBIT_CONVERT: { 5598 // We know the result is a vector. The input may be either a vector or a 5599 // scalar value. 5600 if (Op.getOperand(0).getValueType() != MVT::Vector) { 5601 // Lower to a store/load. FIXME: this could be improved probably. 5602 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType()); 5603 5604 SDOperand St = DAG.getStore(DAG.getEntryNode(), 5605 Op.getOperand(0), Ptr, NULL, 0); 5606 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 5607 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0)); 5608 SplitVectorOp(St, Lo, Hi); 5609 } else { 5610 // If the input is a vector type, we have to either scalarize it, pack it 5611 // or convert it based on whether the input vector type is legal. 5612 SDNode *InVal = Node->getOperand(0).Val; 5613 unsigned NumElems = 5614 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 5615 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 5616 5617 // If the input is from a single element vector, scalarize the vector, 5618 // then treat like a scalar. 5619 if (NumElems == 1) { 5620 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT); 5621 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar, 5622 Op.getOperand(1), Op.getOperand(2)); 5623 SplitVectorOp(Scalar, Lo, Hi); 5624 } else { 5625 // Split the input vector. 5626 SplitVectorOp(Op.getOperand(0), Lo, Hi); 5627 5628 // Convert each of the pieces now. 5629 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo, 5630 NewNumEltsNode, TypeNode); 5631 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi, 5632 NewNumEltsNode, TypeNode); 5633 } 5634 break; 5635 } 5636 } 5637 } 5638 5639 // Remember in a map if the values will be reused later. 5640 bool isNew = 5641 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 5642 assert(isNew && "Value already expanded?!?"); 5643} 5644 5645 5646/// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 5647/// equivalent operation that returns a scalar (e.g. F32) or packed value 5648/// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right 5649/// type for the result. 5650SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, 5651 MVT::ValueType NewVT) { 5652 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!"); 5653 SDNode *Node = Op.Val; 5654 5655 // See if we already packed it. 5656 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op); 5657 if (I != PackedNodes.end()) return I->second; 5658 5659 SDOperand Result; 5660 switch (Node->getOpcode()) { 5661 default: 5662#ifndef NDEBUG 5663 Node->dump(&DAG); cerr << "\n"; 5664#endif 5665 assert(0 && "Unknown vector operation in PackVectorOp!"); 5666 case ISD::VADD: 5667 case ISD::VSUB: 5668 case ISD::VMUL: 5669 case ISD::VSDIV: 5670 case ISD::VUDIV: 5671 case ISD::VAND: 5672 case ISD::VOR: 5673 case ISD::VXOR: 5674 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT), 5675 NewVT, 5676 PackVectorOp(Node->getOperand(0), NewVT), 5677 PackVectorOp(Node->getOperand(1), NewVT)); 5678 break; 5679 case ISD::VLOAD: { 5680 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 5681 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 5682 5683 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 5684 Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset()); 5685 5686 // Remember that we legalized the chain. 5687 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 5688 break; 5689 } 5690 case ISD::VBUILD_VECTOR: 5691 if (Node->getOperand(0).getValueType() == NewVT) { 5692 // Returning a scalar? 5693 Result = Node->getOperand(0); 5694 } else { 5695 // Returning a BUILD_VECTOR? 5696 5697 // If all elements of the build_vector are undefs, return an undef. 5698 bool AllUndef = true; 5699 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i) 5700 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) { 5701 AllUndef = false; 5702 break; 5703 } 5704 if (AllUndef) { 5705 Result = DAG.getNode(ISD::UNDEF, NewVT); 5706 } else { 5707 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(), 5708 Node->getNumOperands()-2); 5709 } 5710 } 5711 break; 5712 case ISD::VCONCAT_VECTORS: 5713 assert(Node->getOperand(0).getValueType() == NewVT && 5714 "Concat of non-legal vectors not yet supported!"); 5715 Result = Node->getOperand(0); 5716 break; 5717 case ISD::VINSERT_VECTOR_ELT: 5718 if (!MVT::isVector(NewVT)) { 5719 // Returning a scalar? Must be the inserted element. 5720 Result = Node->getOperand(1); 5721 } else { 5722 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, 5723 PackVectorOp(Node->getOperand(0), NewVT), 5724 Node->getOperand(1), Node->getOperand(2)); 5725 } 5726 break; 5727 case ISD::VEXTRACT_SUBVECTOR: 5728 Result = PackVectorOp(Node->getOperand(0), NewVT); 5729 assert(Result.getValueType() == NewVT); 5730 break; 5731 case ISD::VVECTOR_SHUFFLE: 5732 if (!MVT::isVector(NewVT)) { 5733 // Returning a scalar? Figure out if it is the LHS or RHS and return it. 5734 SDOperand EltNum = Node->getOperand(2).getOperand(0); 5735 if (cast<ConstantSDNode>(EltNum)->getValue()) 5736 Result = PackVectorOp(Node->getOperand(1), NewVT); 5737 else 5738 Result = PackVectorOp(Node->getOperand(0), NewVT); 5739 } else { 5740 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index 5741 // vector from a VBUILD_VECTOR to a BUILD_VECTOR. 5742 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(), 5743 Node->getOperand(2).Val->op_end()-2); 5744 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size()); 5745 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, 5746 Node->getOperand(2).Val->op_begin(), 5747 Node->getOperand(2).Val->getNumOperands()-2); 5748 5749 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, 5750 PackVectorOp(Node->getOperand(0), NewVT), 5751 PackVectorOp(Node->getOperand(1), NewVT), BV); 5752 } 5753 break; 5754 case ISD::VBIT_CONVERT: 5755 if (Op.getOperand(0).getValueType() != MVT::Vector) 5756 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 5757 else { 5758 // If the input is a vector type, we have to either scalarize it, pack it 5759 // or convert it based on whether the input vector type is legal. 5760 SDNode *InVal = Node->getOperand(0).Val; 5761 unsigned NumElems = 5762 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 5763 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 5764 5765 // Figure out if there is a Packed type corresponding to this Vector 5766 // type. If so, convert to the vector type. 5767 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 5768 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 5769 // Turn this into a bit convert of the packed input. 5770 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 5771 PackVectorOp(Node->getOperand(0), TVT)); 5772 break; 5773 } else if (NumElems == 1) { 5774 // Turn this into a bit convert of the scalar input. 5775 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 5776 PackVectorOp(Node->getOperand(0), EVT)); 5777 break; 5778 } else { 5779 // If the input vector type isn't legal, then go through memory. 5780 SDOperand Ptr = CreateStackTemporary(NewVT); 5781 // Get the alignment for the store. 5782 const TargetData &TD = *TLI.getTargetData(); 5783 unsigned Align = 5784 TD.getABITypeAlignment(MVT::getTypeForValueType(NewVT)); 5785 5786 SDOperand St = DAG.getStore(DAG.getEntryNode(), 5787 Node->getOperand(0), Ptr, NULL, 0, false, 5788 Align); 5789 Result = DAG.getLoad(NewVT, St, Ptr, 0, 0); 5790 break; 5791 } 5792 } 5793 break; 5794 case ISD::VSELECT: 5795 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 5796 PackVectorOp(Op.getOperand(1), NewVT), 5797 PackVectorOp(Op.getOperand(2), NewVT)); 5798 break; 5799 } 5800 5801 if (TLI.isTypeLegal(NewVT)) 5802 Result = LegalizeOp(Result); 5803 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second; 5804 assert(isNew && "Value already packed?"); 5805 return Result; 5806} 5807 5808 5809// SelectionDAG::Legalize - This is the entry point for the file. 5810// 5811void SelectionDAG::Legalize() { 5812 if (ViewLegalizeDAGs) viewGraph(); 5813 5814 /// run - This is the main entry point to this class. 5815 /// 5816 SelectionDAGLegalize(*this).LegalizeDAG(); 5817} 5818 5819