LegalizeDAG.cpp revision 55ba8fba750ee0a51a9d74fa33b7242d24a4ff35
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineConstantPool.h" 16#include "llvm/CodeGen/MachineFunction.h" 17#include "llvm/CodeGen/MachineFrameInfo.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/Constants.h" 22#include <iostream> 23using namespace llvm; 24 25//===----------------------------------------------------------------------===// 26/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 27/// hacks on it until the target machine can handle it. This involves 28/// eliminating value sizes the machine cannot handle (promoting small sizes to 29/// large sizes or splitting up large values into small values) as well as 30/// eliminating operations the machine cannot handle. 31/// 32/// This code also does a small amount of optimization and recognition of idioms 33/// as part of its processing. For example, if a target does not support a 34/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 35/// will attempt merge setcc and brc instructions into brcc's. 36/// 37namespace { 38class SelectionDAGLegalize { 39 TargetLowering &TLI; 40 SelectionDAG &DAG; 41 42 /// LegalizeAction - This enum indicates what action we should take for each 43 /// value type the can occur in the program. 44 enum LegalizeAction { 45 Legal, // The target natively supports this value type. 46 Promote, // This should be promoted to the next larger type. 47 Expand, // This integer type should be broken into smaller pieces. 48 }; 49 50 /// ValueTypeActions - This is a bitvector that contains two bits for each 51 /// value type, where the two bits correspond to the LegalizeAction enum. 52 /// This can be queried with "getTypeAction(VT)". 53 unsigned ValueTypeActions; 54 55 /// NeedsAnotherIteration - This is set when we expand a large integer 56 /// operation into smaller integer operations, but the smaller operations are 57 /// not set. This occurs only rarely in practice, for targets that don't have 58 /// 32-bit or larger integer registers. 59 bool NeedsAnotherIteration; 60 61 /// LegalizedNodes - For nodes that are of legal width, and that have more 62 /// than one use, this map indicates what regularized operand to use. This 63 /// allows us to avoid legalizing the same thing more than once. 64 std::map<SDOperand, SDOperand> LegalizedNodes; 65 66 /// PromotedNodes - For nodes that are below legal width, and that have more 67 /// than one use, this map indicates what promoted value to use. This allows 68 /// us to avoid promoting the same thing more than once. 69 std::map<SDOperand, SDOperand> PromotedNodes; 70 71 /// ExpandedNodes - For nodes that need to be expanded, and which have more 72 /// than one use, this map indicates which which operands are the expanded 73 /// version of the input. This allows us to avoid expanding the same node 74 /// more than once. 75 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 76 77 void AddLegalizedOperand(SDOperand From, SDOperand To) { 78 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second; 79 assert(isNew && "Got into the map somehow?"); 80 } 81 void AddPromotedOperand(SDOperand From, SDOperand To) { 82 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 83 assert(isNew && "Got into the map somehow?"); 84 } 85 86public: 87 88 SelectionDAGLegalize(TargetLowering &TLI, SelectionDAG &DAG); 89 90 /// Run - While there is still lowering to do, perform a pass over the DAG. 91 /// Most regularization can be done in a single pass, but targets that require 92 /// large values to be split into registers multiple times (e.g. i64 -> 4x 93 /// i16) require iteration for these values (the first iteration will demote 94 /// to i32, the second will demote to i16). 95 void Run() { 96 do { 97 NeedsAnotherIteration = false; 98 LegalizeDAG(); 99 } while (NeedsAnotherIteration); 100 } 101 102 /// getTypeAction - Return how we should legalize values of this type, either 103 /// it is already legal or we need to expand it into multiple registers of 104 /// smaller integer type, or we need to promote it to a larger type. 105 LegalizeAction getTypeAction(MVT::ValueType VT) const { 106 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 107 } 108 109 /// isTypeLegal - Return true if this type is legal on this target. 110 /// 111 bool isTypeLegal(MVT::ValueType VT) const { 112 return getTypeAction(VT) == Legal; 113 } 114 115private: 116 void LegalizeDAG(); 117 118 SDOperand LegalizeOp(SDOperand O); 119 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 120 SDOperand PromoteOp(SDOperand O); 121 122 SDOperand getIntPtrConstant(uint64_t Val) { 123 return DAG.getConstant(Val, TLI.getPointerTy()); 124 } 125}; 126} 127 128 129SelectionDAGLegalize::SelectionDAGLegalize(TargetLowering &tli, 130 SelectionDAG &dag) 131 : TLI(tli), DAG(dag), ValueTypeActions(TLI.getValueTypeActions()) { 132 assert(MVT::LAST_VALUETYPE <= 16 && 133 "Too many value types for ValueTypeActions to hold!"); 134} 135 136void SelectionDAGLegalize::LegalizeDAG() { 137 SDOperand OldRoot = DAG.getRoot(); 138 SDOperand NewRoot = LegalizeOp(OldRoot); 139 DAG.setRoot(NewRoot); 140 141 ExpandedNodes.clear(); 142 LegalizedNodes.clear(); 143 PromotedNodes.clear(); 144 145 // Remove dead nodes now. 146 DAG.RemoveDeadNodes(OldRoot.Val); 147} 148 149SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 150 assert(getTypeAction(Op.getValueType()) == Legal && 151 "Caller should expand or promote operands that are not legal!"); 152 153 // If this operation defines any values that cannot be represented in a 154 // register on this target, make sure to expand or promote them. 155 if (Op.Val->getNumValues() > 1) { 156 for (unsigned i = 0, e = Op.Val->getNumValues(); i != e; ++i) 157 switch (getTypeAction(Op.Val->getValueType(i))) { 158 case Legal: break; // Nothing to do. 159 case Expand: { 160 SDOperand T1, T2; 161 ExpandOp(Op.getValue(i), T1, T2); 162 assert(LegalizedNodes.count(Op) && 163 "Expansion didn't add legal operands!"); 164 return LegalizedNodes[Op]; 165 } 166 case Promote: 167 PromoteOp(Op.getValue(i)); 168 assert(LegalizedNodes.count(Op) && 169 "Expansion didn't add legal operands!"); 170 return LegalizedNodes[Op]; 171 } 172 } 173 174 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 175 if (I != LegalizedNodes.end()) return I->second; 176 177 SDOperand Tmp1, Tmp2, Tmp3; 178 179 SDOperand Result = Op; 180 SDNode *Node = Op.Val; 181 182 switch (Node->getOpcode()) { 183 default: 184 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 185 assert(0 && "Do not know how to legalize this operator!"); 186 abort(); 187 case ISD::EntryToken: 188 case ISD::FrameIndex: 189 case ISD::GlobalAddress: 190 case ISD::ExternalSymbol: 191 case ISD::ConstantPool: // Nothing to do. 192 assert(getTypeAction(Node->getValueType(0)) == Legal && 193 "This must be legal!"); 194 break; 195 case ISD::CopyFromReg: 196 Tmp1 = LegalizeOp(Node->getOperand(0)); 197 if (Tmp1 != Node->getOperand(0)) 198 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), 199 Node->getValueType(0), Tmp1); 200 break; 201 case ISD::ImplicitDef: 202 Tmp1 = LegalizeOp(Node->getOperand(0)); 203 if (Tmp1 != Node->getOperand(0)) 204 Result = DAG.getImplicitDef(Tmp1, cast<RegSDNode>(Node)->getReg()); 205 break; 206 case ISD::Constant: 207 // We know we don't need to expand constants here, constants only have one 208 // value and we check that it is fine above. 209 210 // FIXME: Maybe we should handle things like targets that don't support full 211 // 32-bit immediates? 212 break; 213 case ISD::ConstantFP: { 214 // Spill FP immediates to the constant pool if the target cannot directly 215 // codegen them. Targets often have some immediate values that can be 216 // efficiently generated into an FP register without a load. We explicitly 217 // leave these constants as ConstantFP nodes for the target to deal with. 218 219 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 220 221 // Check to see if this FP immediate is already legal. 222 bool isLegal = false; 223 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 224 E = TLI.legal_fpimm_end(); I != E; ++I) 225 if (CFP->isExactlyValue(*I)) { 226 isLegal = true; 227 break; 228 } 229 230 if (!isLegal) { 231 // Otherwise we need to spill the constant to memory. 232 MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool(); 233 234 bool Extend = false; 235 236 // If a FP immediate is precise when represented as a float, we put it 237 // into the constant pool as a float, even if it's is statically typed 238 // as a double. 239 MVT::ValueType VT = CFP->getValueType(0); 240 bool isDouble = VT == MVT::f64; 241 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 242 Type::FloatTy, CFP->getValue()); 243 if (isDouble && CFP->isExactlyValue((float)CFP->getValue())) { 244 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 245 VT = MVT::f32; 246 Extend = true; 247 } 248 249 SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(LLVMC), 250 TLI.getPointerTy()); 251 if (Extend) { 252 Result = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), CPIdx, 253 MVT::f32); 254 } else { 255 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx); 256 } 257 } 258 break; 259 } 260 case ISD::TokenFactor: { 261 std::vector<SDOperand> Ops; 262 bool Changed = false; 263 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 264 Ops.push_back(LegalizeOp(Node->getOperand(i))); // Legalize the operands 265 Changed |= Ops[i] != Node->getOperand(i); 266 } 267 if (Changed) 268 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 269 break; 270 } 271 272 case ISD::ADJCALLSTACKDOWN: 273 case ISD::ADJCALLSTACKUP: 274 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 275 // There is no need to legalize the size argument (Operand #1) 276 if (Tmp1 != Node->getOperand(0)) 277 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 278 Node->getOperand(1)); 279 break; 280 case ISD::DYNAMIC_STACKALLOC: 281 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 282 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 283 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 284 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 285 Tmp3 != Node->getOperand(2)) 286 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, Node->getValueType(0), 287 Tmp1, Tmp2, Tmp3); 288 else 289 Result = Op.getValue(0); 290 291 // Since this op produces two values, make sure to remember that we 292 // legalized both of them. 293 AddLegalizedOperand(SDOperand(Node, 0), Result); 294 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 295 return Result.getValue(Op.ResNo); 296 297 case ISD::CALL: 298 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 299 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 300 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 301 std::vector<MVT::ValueType> RetTyVTs; 302 RetTyVTs.reserve(Node->getNumValues()); 303 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 304 RetTyVTs.push_back(Node->getValueType(i)); 305 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2), 0); 306 } else { 307 Result = Result.getValue(0); 308 } 309 // Since calls produce multiple values, make sure to remember that we 310 // legalized all of them. 311 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 312 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 313 return Result.getValue(Op.ResNo); 314 315 case ISD::BR: 316 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 317 if (Tmp1 != Node->getOperand(0)) 318 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 319 break; 320 321 case ISD::BRCOND: 322 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 323 // FIXME: booleans might not be legal! 324 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 325 // Basic block destination (Op#2) is always legal. 326 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 327 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 328 Node->getOperand(2)); 329 break; 330 331 case ISD::LOAD: 332 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 333 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 334 if (Tmp1 != Node->getOperand(0) || 335 Tmp2 != Node->getOperand(1)) 336 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2); 337 else 338 Result = SDOperand(Node, 0); 339 340 // Since loads produce two values, make sure to remember that we legalized 341 // both of them. 342 AddLegalizedOperand(SDOperand(Node, 0), Result); 343 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 344 return Result.getValue(Op.ResNo); 345 346 case ISD::EXTLOAD: 347 case ISD::SEXTLOAD: 348 case ISD::ZEXTLOAD: 349 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 350 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 351 if (Tmp1 != Node->getOperand(0) || 352 Tmp2 != Node->getOperand(1)) 353 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2, 354 cast<MVTSDNode>(Node)->getExtraValueType()); 355 else 356 Result = SDOperand(Node, 0); 357 358 // Since loads produce two values, make sure to remember that we legalized 359 // both of them. 360 AddLegalizedOperand(SDOperand(Node, 0), Result); 361 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 362 return Result.getValue(Op.ResNo); 363 364 case ISD::EXTRACT_ELEMENT: 365 // Get both the low and high parts. 366 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 367 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 368 Result = Tmp2; // 1 -> Hi 369 else 370 Result = Tmp1; // 0 -> Lo 371 break; 372 373 case ISD::CopyToReg: 374 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 375 376 switch (getTypeAction(Node->getOperand(1).getValueType())) { 377 case Legal: 378 // Legalize the incoming value (must be legal). 379 Tmp2 = LegalizeOp(Node->getOperand(1)); 380 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 381 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg()); 382 break; 383 case Expand: { 384 SDOperand Lo, Hi; 385 ExpandOp(Node->getOperand(1), Lo, Hi); 386 unsigned Reg = cast<RegSDNode>(Node)->getReg(); 387 Result = DAG.getCopyToReg(Tmp1, Lo, Reg); 388 Result = DAG.getCopyToReg(Result, Hi, Reg+1); 389 assert(isTypeLegal(Result.getValueType()) && 390 "Cannot expand multiple times yet (i64 -> i16)"); 391 break; 392 } 393 case Promote: 394 assert(0 && "CopyToReg should not require promotion!"); 395 abort(); 396 } 397 break; 398 399 case ISD::RET: 400 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 401 switch (Node->getNumOperands()) { 402 case 2: // ret val 403 switch (getTypeAction(Node->getOperand(1).getValueType())) { 404 case Legal: 405 Tmp2 = LegalizeOp(Node->getOperand(1)); 406 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 407 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 408 break; 409 case Expand: { 410 SDOperand Lo, Hi; 411 ExpandOp(Node->getOperand(1), Lo, Hi); 412 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 413 break; 414 } 415 case Promote: 416 Tmp2 = PromoteOp(Node->getOperand(1)); 417 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 418 break; 419 } 420 break; 421 case 1: // ret void 422 if (Tmp1 != Node->getOperand(0)) 423 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 424 break; 425 default: { // ret <values> 426 std::vector<SDOperand> NewValues; 427 NewValues.push_back(Tmp1); 428 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 429 switch (getTypeAction(Node->getOperand(i).getValueType())) { 430 case Legal: 431 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 432 break; 433 case Expand: { 434 SDOperand Lo, Hi; 435 ExpandOp(Node->getOperand(i), Lo, Hi); 436 NewValues.push_back(Lo); 437 NewValues.push_back(Hi); 438 break; 439 } 440 case Promote: 441 assert(0 && "Can't promote multiple return value yet!"); 442 } 443 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 444 break; 445 } 446 } 447 break; 448 case ISD::STORE: 449 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 450 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 451 452 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 453 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 454 if (CFP->getValueType(0) == MVT::f32) { 455 union { 456 unsigned I; 457 float F; 458 } V; 459 V.F = CFP->getValue(); 460 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 461 DAG.getConstant(V.I, MVT::i32), Tmp2); 462 } else { 463 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 464 union { 465 uint64_t I; 466 double F; 467 } V; 468 V.F = CFP->getValue(); 469 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 470 DAG.getConstant(V.I, MVT::i64), Tmp2); 471 } 472 Op = Result; 473 Node = Op.Val; 474 } 475 476 switch (getTypeAction(Node->getOperand(1).getValueType())) { 477 case Legal: { 478 SDOperand Val = LegalizeOp(Node->getOperand(1)); 479 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 480 Tmp2 != Node->getOperand(2)) 481 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2); 482 break; 483 } 484 case Promote: 485 // Truncate the value and store the result. 486 Tmp3 = PromoteOp(Node->getOperand(1)); 487 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 488 Node->getOperand(1).getValueType()); 489 break; 490 491 case Expand: 492 SDOperand Lo, Hi; 493 ExpandOp(Node->getOperand(1), Lo, Hi); 494 495 if (!TLI.isLittleEndian()) 496 std::swap(Lo, Hi); 497 498 // FIXME: These two stores are independent of each other! 499 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2); 500 501 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 502 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 503 getIntPtrConstant(IncrementSize)); 504 assert(isTypeLegal(Tmp2.getValueType()) && 505 "Pointers must be legal!"); 506 Result = DAG.getNode(ISD::STORE, MVT::Other, Result, Hi, Tmp2); 507 } 508 break; 509 case ISD::TRUNCSTORE: 510 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 511 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 512 513 switch (getTypeAction(Node->getOperand(1).getValueType())) { 514 case Legal: 515 Tmp2 = LegalizeOp(Node->getOperand(1)); 516 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 517 Tmp3 != Node->getOperand(2)) 518 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 519 cast<MVTSDNode>(Node)->getExtraValueType()); 520 break; 521 case Promote: 522 case Expand: 523 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 524 } 525 break; 526 case ISD::SELECT: 527 // FIXME: BOOLS MAY REQUIRE PROMOTION! 528 Tmp1 = LegalizeOp(Node->getOperand(0)); // Cond 529 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 530 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 531 532 switch (TLI.getOperationAction(Node->getOpcode(), Tmp2.getValueType())) { 533 default: assert(0 && "This action is not supported yet!"); 534 case TargetLowering::Legal: 535 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 536 Tmp3 != Node->getOperand(2)) 537 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 538 Tmp1, Tmp2, Tmp3); 539 break; 540 case TargetLowering::Promote: { 541 MVT::ValueType NVT = 542 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 543 unsigned ExtOp, TruncOp; 544 if (MVT::isInteger(Tmp2.getValueType())) { 545 ExtOp = ISD::ZERO_EXTEND; 546 TruncOp = ISD::TRUNCATE; 547 } else { 548 ExtOp = ISD::FP_EXTEND; 549 TruncOp = ISD::FP_ROUND; 550 } 551 // Promote each of the values to the new type. 552 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 553 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 554 // Perform the larger operation, then round down. 555 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 556 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 557 break; 558 } 559 } 560 break; 561 case ISD::SETCC: 562 switch (getTypeAction(Node->getOperand(0).getValueType())) { 563 case Legal: 564 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 565 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 566 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 567 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 568 Tmp1, Tmp2); 569 break; 570 case Promote: 571 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 572 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 573 574 // If this is an FP compare, the operands have already been extended. 575 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 576 MVT::ValueType VT = Node->getOperand(0).getValueType(); 577 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 578 579 // Otherwise, we have to insert explicit sign or zero extends. Note 580 // that we could insert sign extends for ALL conditions, but zero extend 581 // is cheaper on many machines (an AND instead of two shifts), so prefer 582 // it. 583 switch (cast<SetCCSDNode>(Node)->getCondition()) { 584 default: assert(0 && "Unknown integer comparison!"); 585 case ISD::SETEQ: 586 case ISD::SETNE: 587 case ISD::SETUGE: 588 case ISD::SETUGT: 589 case ISD::SETULE: 590 case ISD::SETULT: 591 // ALL of these operations will work if we either sign or zero extend 592 // the operands (including the unsigned comparisons!). Zero extend is 593 // usually a simpler/cheaper operation, so prefer it. 594 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp1, VT); 595 Tmp2 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp2, VT); 596 break; 597 case ISD::SETGE: 598 case ISD::SETGT: 599 case ISD::SETLT: 600 case ISD::SETLE: 601 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 602 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT); 603 break; 604 } 605 606 } 607 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 608 Tmp1, Tmp2); 609 break; 610 case Expand: 611 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 612 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 613 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 614 switch (cast<SetCCSDNode>(Node)->getCondition()) { 615 case ISD::SETEQ: 616 case ISD::SETNE: 617 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 618 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 619 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 620 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), Tmp1, 621 DAG.getConstant(0, Tmp1.getValueType())); 622 break; 623 default: 624 // FIXME: This generated code sucks. 625 ISD::CondCode LowCC; 626 switch (cast<SetCCSDNode>(Node)->getCondition()) { 627 default: assert(0 && "Unknown integer setcc!"); 628 case ISD::SETLT: 629 case ISD::SETULT: LowCC = ISD::SETULT; break; 630 case ISD::SETGT: 631 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 632 case ISD::SETLE: 633 case ISD::SETULE: LowCC = ISD::SETULE; break; 634 case ISD::SETGE: 635 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 636 } 637 638 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 639 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 640 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 641 642 // NOTE: on targets without efficient SELECT of bools, we can always use 643 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 644 Tmp1 = DAG.getSetCC(LowCC, LHSLo, RHSLo); 645 Tmp2 = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 646 LHSHi, RHSHi); 647 Result = DAG.getSetCC(ISD::SETEQ, LHSHi, RHSHi); 648 Result = DAG.getNode(ISD::SELECT, MVT::i1, Result, Tmp1, Tmp2); 649 break; 650 } 651 } 652 break; 653 654 case ISD::MEMSET: 655 case ISD::MEMCPY: 656 case ISD::MEMMOVE: { 657 Tmp1 = LegalizeOp(Node->getOperand(0)); 658 Tmp2 = LegalizeOp(Node->getOperand(1)); 659 Tmp3 = LegalizeOp(Node->getOperand(2)); 660 SDOperand Tmp4 = LegalizeOp(Node->getOperand(3)); 661 SDOperand Tmp5 = LegalizeOp(Node->getOperand(4)); 662 663 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 664 default: assert(0 && "This action not implemented for this operation!"); 665 case TargetLowering::Legal: 666 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 667 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 668 Tmp5 != Node->getOperand(4)) { 669 std::vector<SDOperand> Ops; 670 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 671 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 672 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 673 } 674 break; 675 case TargetLowering::Expand: { 676 // Otherwise, the target does not support this operation. Lower the 677 // operation to an explicit libcall as appropriate. 678 MVT::ValueType IntPtr = TLI.getPointerTy(); 679 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 680 std::vector<std::pair<SDOperand, const Type*> > Args; 681 682 const char *FnName = 0; 683 if (Node->getOpcode() == ISD::MEMSET) { 684 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 685 // Extend the ubyte argument to be an int value for the call. 686 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 687 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 688 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 689 690 FnName = "memset"; 691 } else if (Node->getOpcode() == ISD::MEMCPY || 692 Node->getOpcode() == ISD::MEMMOVE) { 693 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 694 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 695 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 696 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 697 } else { 698 assert(0 && "Unknown op!"); 699 } 700 std::pair<SDOperand,SDOperand> CallResult = 701 TLI.LowerCallTo(Tmp1, Type::VoidTy, 702 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 703 Result = LegalizeOp(CallResult.second); 704 break; 705 } 706 case TargetLowering::Custom: 707 std::vector<SDOperand> Ops; 708 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 709 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 710 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 711 Result = TLI.LowerOperation(Result); 712 Result = LegalizeOp(Result); 713 break; 714 } 715 break; 716 } 717 case ISD::ADD: 718 case ISD::SUB: 719 case ISD::MUL: 720 case ISD::UDIV: 721 case ISD::SDIV: 722 case ISD::UREM: 723 case ISD::SREM: 724 case ISD::AND: 725 case ISD::OR: 726 case ISD::XOR: 727 case ISD::SHL: 728 case ISD::SRL: 729 case ISD::SRA: 730 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 731 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 732 if (Tmp1 != Node->getOperand(0) || 733 Tmp2 != Node->getOperand(1)) 734 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 735 break; 736 case ISD::ZERO_EXTEND: 737 case ISD::SIGN_EXTEND: 738 case ISD::TRUNCATE: 739 case ISD::FP_EXTEND: 740 case ISD::FP_ROUND: 741 case ISD::FP_TO_SINT: 742 case ISD::FP_TO_UINT: 743 case ISD::SINT_TO_FP: 744 case ISD::UINT_TO_FP: 745 switch (getTypeAction(Node->getOperand(0).getValueType())) { 746 case Legal: 747 Tmp1 = LegalizeOp(Node->getOperand(0)); 748 if (Tmp1 != Node->getOperand(0)) 749 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 750 break; 751 case Expand: 752 assert(Node->getOpcode() != ISD::SINT_TO_FP && 753 Node->getOpcode() != ISD::UINT_TO_FP && 754 "Cannot lower Xint_to_fp to a call yet!"); 755 756 // In the expand case, we must be dealing with a truncate, because 757 // otherwise the result would be larger than the source. 758 assert(Node->getOpcode() == ISD::TRUNCATE && 759 "Shouldn't need to expand other operators here!"); 760 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 761 762 // Since the result is legal, we should just be able to truncate the low 763 // part of the source. 764 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 765 break; 766 767 case Promote: 768 switch (Node->getOpcode()) { 769 case ISD::ZERO_EXTEND: 770 Result = PromoteOp(Node->getOperand(0)); 771 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Result.getValueType(), 772 Result, Node->getOperand(0).getValueType()); 773 break; 774 case ISD::SIGN_EXTEND: 775 Result = PromoteOp(Node->getOperand(0)); 776 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 777 Result, Node->getOperand(0).getValueType()); 778 break; 779 case ISD::TRUNCATE: 780 Result = PromoteOp(Node->getOperand(0)); 781 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 782 break; 783 case ISD::FP_EXTEND: 784 Result = PromoteOp(Node->getOperand(0)); 785 if (Result.getValueType() != Op.getValueType()) 786 // Dynamically dead while we have only 2 FP types. 787 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 788 break; 789 case ISD::FP_ROUND: 790 case ISD::FP_TO_SINT: 791 case ISD::FP_TO_UINT: 792 Result = PromoteOp(Node->getOperand(0)); 793 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 794 break; 795 case ISD::SINT_TO_FP: 796 Result = PromoteOp(Node->getOperand(0)); 797 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 798 Result, Node->getOperand(0).getValueType()); 799 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 800 break; 801 case ISD::UINT_TO_FP: 802 Result = PromoteOp(Node->getOperand(0)); 803 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Result.getValueType(), 804 Result, Node->getOperand(0).getValueType()); 805 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 806 break; 807 } 808 } 809 break; 810 case ISD::FP_ROUND_INREG: 811 case ISD::SIGN_EXTEND_INREG: 812 case ISD::ZERO_EXTEND_INREG: { 813 Tmp1 = LegalizeOp(Node->getOperand(0)); 814 MVT::ValueType ExtraVT = cast<MVTSDNode>(Node)->getExtraValueType(); 815 816 // If this operation is not supported, convert it to a shl/shr or load/store 817 // pair. 818 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 819 default: assert(0 && "This action not supported for this op yet!"); 820 case TargetLowering::Legal: 821 if (Tmp1 != Node->getOperand(0)) 822 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 823 ExtraVT); 824 break; 825 case TargetLowering::Expand: 826 // If this is an integer extend and shifts are supported, do that. 827 if (Node->getOpcode() == ISD::ZERO_EXTEND_INREG) { 828 // NOTE: we could fall back on load/store here too for targets without 829 // AND. However, it is doubtful that any exist. 830 // AND out the appropriate bits. 831 SDOperand Mask = 832 DAG.getConstant((1ULL << MVT::getSizeInBits(ExtraVT))-1, 833 Node->getValueType(0)); 834 Result = DAG.getNode(ISD::AND, Node->getValueType(0), 835 Node->getOperand(0), Mask); 836 } else if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 837 // NOTE: we could fall back on load/store here too for targets without 838 // SAR. However, it is doubtful that any exist. 839 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 840 MVT::getSizeInBits(ExtraVT); 841 SDOperand ShiftCst = DAG.getConstant(BitsDiff, MVT::i8); 842 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 843 Node->getOperand(0), ShiftCst); 844 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 845 Result, ShiftCst); 846 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 847 // The only way we can lower this is to turn it into a STORETRUNC, 848 // EXTLOAD pair, targetting a temporary location (a stack slot). 849 850 // NOTE: there is a choice here between constantly creating new stack 851 // slots and always reusing the same one. We currently always create 852 // new ones, as reuse may inhibit scheduling. 853 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 854 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 855 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 856 MachineFunction &MF = DAG.getMachineFunction(); 857 int SSFI = 858 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 859 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 860 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 861 Node->getOperand(0), StackSlot, ExtraVT); 862 Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0), 863 Result, StackSlot, ExtraVT); 864 } else { 865 assert(0 && "Unknown op"); 866 } 867 Result = LegalizeOp(Result); 868 break; 869 } 870 break; 871 } 872 } 873 874 if (!Op.Val->hasOneUse()) 875 AddLegalizedOperand(Op, Result); 876 877 return Result; 878} 879 880/// PromoteOp - Given an operation that produces a value in an invalid type, 881/// promote it to compute the value into a larger type. The produced value will 882/// have the correct bits for the low portion of the register, but no guarantee 883/// is made about the top bits: it may be zero, sign-extended, or garbage. 884SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 885 MVT::ValueType VT = Op.getValueType(); 886 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 887 assert(getTypeAction(VT) == Promote && 888 "Caller should expand or legalize operands that are not promotable!"); 889 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 890 "Cannot promote to smaller type!"); 891 892 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 893 if (I != PromotedNodes.end()) return I->second; 894 895 SDOperand Tmp1, Tmp2, Tmp3; 896 897 SDOperand Result; 898 SDNode *Node = Op.Val; 899 900 // Promotion needs an optimization step to clean up after it, and is not 901 // careful to avoid operations the target does not support. Make sure that 902 // all generated operations are legalized in the next iteration. 903 NeedsAnotherIteration = true; 904 905 switch (Node->getOpcode()) { 906 default: 907 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 908 assert(0 && "Do not know how to promote this operator!"); 909 abort(); 910 case ISD::CALL: 911 assert(0 && "Target's LowerCallTo implementation is buggy, returning value" 912 " types that are not supported by the target!"); 913 case ISD::Constant: 914 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 915 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 916 break; 917 case ISD::ConstantFP: 918 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 919 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 920 break; 921 922 case ISD::TRUNCATE: 923 switch (getTypeAction(Node->getOperand(0).getValueType())) { 924 case Legal: 925 Result = LegalizeOp(Node->getOperand(0)); 926 assert(Result.getValueType() >= NVT && 927 "This truncation doesn't make sense!"); 928 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 929 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 930 break; 931 case Expand: 932 assert(0 && "Cannot handle expand yet"); 933 case Promote: 934 assert(0 && "Cannot handle promote-promote yet"); 935 } 936 break; 937 case ISD::SIGN_EXTEND: 938 case ISD::ZERO_EXTEND: 939 switch (getTypeAction(Node->getOperand(0).getValueType())) { 940 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 941 case Legal: 942 // Input is legal? Just do extend all the way to the larger type. 943 Result = LegalizeOp(Node->getOperand(0)); 944 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 945 break; 946 case Promote: 947 // Promote the reg if it's smaller. 948 Result = PromoteOp(Node->getOperand(0)); 949 // The high bits are not guaranteed to be anything. Insert an extend. 950 if (Node->getOpcode() == ISD::SIGN_EXTEND) 951 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, VT); 952 else 953 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Result, VT); 954 break; 955 } 956 break; 957 958 case ISD::FP_EXTEND: 959 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 960 case ISD::FP_ROUND: 961 switch (getTypeAction(Node->getOperand(0).getValueType())) { 962 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 963 case Promote: assert(0 && "Unreachable with 2 FP types!"); 964 case Legal: 965 // Input is legal? Do an FP_ROUND_INREG. 966 Result = LegalizeOp(Node->getOperand(0)); 967 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 968 break; 969 } 970 break; 971 972 case ISD::SINT_TO_FP: 973 case ISD::UINT_TO_FP: 974 switch (getTypeAction(Node->getOperand(0).getValueType())) { 975 case Legal: 976 Result = LegalizeOp(Node->getOperand(0)); 977 break; 978 979 case Promote: 980 Result = PromoteOp(Node->getOperand(0)); 981 if (Node->getOpcode() == ISD::SINT_TO_FP) 982 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 983 Result, Node->getOperand(0).getValueType()); 984 else 985 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Result.getValueType(), 986 Result, Node->getOperand(0).getValueType()); 987 break; 988 case Expand: 989 assert(0 && "Unimplemented"); 990 } 991 // No extra round required here. 992 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 993 break; 994 995 case ISD::FP_TO_SINT: 996 case ISD::FP_TO_UINT: 997 switch (getTypeAction(Node->getOperand(0).getValueType())) { 998 case Legal: 999 Tmp1 = LegalizeOp(Node->getOperand(0)); 1000 break; 1001 case Promote: 1002 // The input result is prerounded, so we don't have to do anything 1003 // special. 1004 Tmp1 = PromoteOp(Node->getOperand(0)); 1005 break; 1006 case Expand: 1007 assert(0 && "not implemented"); 1008 } 1009 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 1010 break; 1011 1012 case ISD::AND: 1013 case ISD::OR: 1014 case ISD::XOR: 1015 case ISD::ADD: 1016 case ISD::SUB: 1017 case ISD::MUL: 1018 // The input may have strange things in the top bits of the registers, but 1019 // these operations don't care. They may have wierd bits going out, but 1020 // that too is okay if they are integer operations. 1021 Tmp1 = PromoteOp(Node->getOperand(0)); 1022 Tmp2 = PromoteOp(Node->getOperand(1)); 1023 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 1024 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1025 1026 // However, if this is a floating point operation, they will give excess 1027 // precision that we may not be able to tolerate. If we DO allow excess 1028 // precision, just leave it, otherwise excise it. 1029 // FIXME: Why would we need to round FP ops more than integer ones? 1030 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 1031 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 1032 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1033 break; 1034 1035 case ISD::SDIV: 1036 case ISD::SREM: 1037 // These operators require that their input be sign extended. 1038 Tmp1 = PromoteOp(Node->getOperand(0)); 1039 Tmp2 = PromoteOp(Node->getOperand(1)); 1040 if (MVT::isInteger(NVT)) { 1041 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 1042 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT); 1043 } 1044 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1045 1046 // Perform FP_ROUND: this is probably overly pessimistic. 1047 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 1048 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1049 break; 1050 1051 case ISD::UDIV: 1052 case ISD::UREM: 1053 // These operators require that their input be zero extended. 1054 Tmp1 = PromoteOp(Node->getOperand(0)); 1055 Tmp2 = PromoteOp(Node->getOperand(1)); 1056 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 1057 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp1, VT); 1058 Tmp2 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp2, VT); 1059 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1060 break; 1061 1062 case ISD::SHL: 1063 Tmp1 = PromoteOp(Node->getOperand(0)); 1064 Tmp2 = LegalizeOp(Node->getOperand(1)); 1065 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 1066 break; 1067 case ISD::SRA: 1068 // The input value must be properly sign extended. 1069 Tmp1 = PromoteOp(Node->getOperand(0)); 1070 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 1071 Tmp2 = LegalizeOp(Node->getOperand(1)); 1072 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 1073 break; 1074 case ISD::SRL: 1075 // The input value must be properly zero extended. 1076 Tmp1 = PromoteOp(Node->getOperand(0)); 1077 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp1, VT); 1078 Tmp2 = LegalizeOp(Node->getOperand(1)); 1079 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 1080 break; 1081 case ISD::LOAD: 1082 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1083 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1084 Result = DAG.getNode(ISD::EXTLOAD, NVT, Tmp1, Tmp2, VT); 1085 1086 // Remember that we legalized the chain. 1087 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1088 break; 1089 case ISD::SELECT: 1090 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition 1091 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 1092 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 1093 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 1094 break; 1095 } 1096 1097 assert(Result.Val && "Didn't set a result!"); 1098 AddPromotedOperand(Op, Result); 1099 return Result; 1100} 1101 1102/// ExpandOp - Expand the specified SDOperand into its two component pieces 1103/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 1104/// LegalizeNodes map is filled in for any results that are not expanded, the 1105/// ExpandedNodes map is filled in for any results that are expanded, and the 1106/// Lo/Hi values are returned. 1107void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 1108 MVT::ValueType VT = Op.getValueType(); 1109 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1110 SDNode *Node = Op.Val; 1111 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 1112 assert(MVT::isInteger(VT) && "Cannot expand FP values!"); 1113 assert(MVT::isInteger(NVT) && NVT < VT && 1114 "Cannot expand to FP value or to larger int value!"); 1115 1116 // If there is more than one use of this, see if we already expanded it. 1117 // There is no use remembering values that only have a single use, as the map 1118 // entries will never be reused. 1119 if (!Node->hasOneUse()) { 1120 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 1121 = ExpandedNodes.find(Op); 1122 if (I != ExpandedNodes.end()) { 1123 Lo = I->second.first; 1124 Hi = I->second.second; 1125 return; 1126 } 1127 } 1128 1129 // Expanding to multiple registers needs to perform an optimization step, and 1130 // is not careful to avoid operations the target does not support. Make sure 1131 // that all generated operations are legalized in the next iteration. 1132 NeedsAnotherIteration = true; 1133 const char *LibCallName = 0; 1134 1135 switch (Node->getOpcode()) { 1136 default: 1137 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 1138 assert(0 && "Do not know how to expand this operator!"); 1139 abort(); 1140 case ISD::Constant: { 1141 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 1142 Lo = DAG.getConstant(Cst, NVT); 1143 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 1144 break; 1145 } 1146 1147 case ISD::CopyFromReg: { 1148 unsigned Reg = cast<RegSDNode>(Node)->getReg(); 1149 // Aggregate register values are always in consequtive pairs. 1150 Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0)); 1151 Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1)); 1152 1153 // Remember that we legalized the chain. 1154 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 1155 1156 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 1157 break; 1158 } 1159 1160 case ISD::LOAD: { 1161 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1162 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1163 Lo = DAG.getLoad(NVT, Ch, Ptr); 1164 1165 // Increment the pointer to the other half. 1166 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 1167 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1168 getIntPtrConstant(IncrementSize)); 1169 // FIXME: This load is independent of the first one. 1170 Hi = DAG.getLoad(NVT, Lo.getValue(1), Ptr); 1171 1172 // Remember that we legalized the chain. 1173 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 1174 if (!TLI.isLittleEndian()) 1175 std::swap(Lo, Hi); 1176 break; 1177 } 1178 case ISD::CALL: { 1179 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1180 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 1181 1182 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 1183 "Can only expand a call once so far, not i64 -> i16!"); 1184 1185 std::vector<MVT::ValueType> RetTyVTs; 1186 RetTyVTs.reserve(3); 1187 RetTyVTs.push_back(NVT); 1188 RetTyVTs.push_back(NVT); 1189 RetTyVTs.push_back(MVT::Other); 1190 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee); 1191 Lo = SDOperand(NC, 0); 1192 Hi = SDOperand(NC, 1); 1193 1194 // Insert the new chain mapping. 1195 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 1196 break; 1197 } 1198 case ISD::AND: 1199 case ISD::OR: 1200 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 1201 SDOperand LL, LH, RL, RH; 1202 ExpandOp(Node->getOperand(0), LL, LH); 1203 ExpandOp(Node->getOperand(1), RL, RH); 1204 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 1205 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 1206 break; 1207 } 1208 case ISD::SELECT: { 1209 SDOperand C, LL, LH, RL, RH; 1210 // FIXME: BOOLS MAY REQUIRE PROMOTION! 1211 C = LegalizeOp(Node->getOperand(0)); 1212 ExpandOp(Node->getOperand(1), LL, LH); 1213 ExpandOp(Node->getOperand(2), RL, RH); 1214 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 1215 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 1216 break; 1217 } 1218 case ISD::SIGN_EXTEND: { 1219 // The low part is just a sign extension of the input (which degenerates to 1220 // a copy). 1221 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, LegalizeOp(Node->getOperand(0))); 1222 1223 // The high part is obtained by SRA'ing all but one of the bits of the lo 1224 // part. 1225 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 1226 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, MVT::i8)); 1227 break; 1228 } 1229 case ISD::ZERO_EXTEND: 1230 // The low part is just a zero extension of the input (which degenerates to 1231 // a copy). 1232 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, LegalizeOp(Node->getOperand(0))); 1233 1234 // The high part is just a zero. 1235 Hi = DAG.getConstant(0, NVT); 1236 break; 1237 1238 // These operators cannot be expanded directly, emit them as calls to 1239 // library functions. 1240 case ISD::FP_TO_SINT: 1241 if (Node->getOperand(0).getValueType() == MVT::f32) 1242 LibCallName = "__fixsfdi"; 1243 else 1244 LibCallName = "__fixdfdi"; 1245 break; 1246 case ISD::FP_TO_UINT: 1247 if (Node->getOperand(0).getValueType() == MVT::f32) 1248 LibCallName = "__fixunssfdi"; 1249 else 1250 LibCallName = "__fixunsdfdi"; 1251 break; 1252 1253 case ISD::ADD: LibCallName = "__adddi3"; break; 1254 case ISD::SUB: LibCallName = "__subdi3"; break; 1255 case ISD::MUL: LibCallName = "__muldi3"; break; 1256 case ISD::SDIV: LibCallName = "__divdi3"; break; 1257 case ISD::UDIV: LibCallName = "__udivdi3"; break; 1258 case ISD::SREM: LibCallName = "__moddi3"; break; 1259 case ISD::UREM: LibCallName = "__umoddi3"; break; 1260 case ISD::SHL: LibCallName = "__ashldi3"; break; 1261 case ISD::SRA: LibCallName = "__ashrdi3"; break; 1262 case ISD::SRL: LibCallName = "__lshrdi3"; break; 1263 } 1264 1265 // Int2FP -> __floatdisf/__floatdidf 1266 1267 // If this is to be expanded into a libcall... do so now. 1268 if (LibCallName) { 1269 TargetLowering::ArgListTy Args; 1270 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1271 Args.push_back(std::make_pair(Node->getOperand(i), 1272 MVT::getTypeForValueType(Node->getOperand(i).getValueType()))); 1273 SDOperand Callee = DAG.getExternalSymbol(LibCallName, TLI.getPointerTy()); 1274 1275 // We don't care about token chains for libcalls. We just use the entry 1276 // node as our input and ignore the output chain. This allows us to place 1277 // calls wherever we need them to satisfy data dependences. 1278 SDOperand Result = TLI.LowerCallTo(DAG.getEntryNode(), 1279 MVT::getTypeForValueType(Op.getValueType()), Callee, 1280 Args, DAG).first; 1281 ExpandOp(Result, Lo, Hi); 1282 } 1283 1284 // Remember in a map if the values will be reused later. 1285 if (!Node->hasOneUse()) { 1286 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 1287 std::make_pair(Lo, Hi))).second; 1288 assert(isNew && "Value already expanded?!?"); 1289 } 1290} 1291 1292 1293// SelectionDAG::Legalize - This is the entry point for the file. 1294// 1295void SelectionDAG::Legalize(TargetLowering &TLI) { 1296 /// run - This is the main entry point to this class. 1297 /// 1298 SelectionDAGLegalize(TLI, *this).Run(); 1299} 1300 1301