LegalizeDAG.cpp revision 5666e684f4a22393526786ce6cd8c354b0a30ced
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/DwarfWriter.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/CodeGen/PseudoSourceValue.h" 22#include "llvm/Target/TargetFrameInfo.h" 23#include "llvm/Target/TargetLowering.h" 24#include "llvm/Target/TargetData.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Target/TargetSubtarget.h" 28#include "llvm/CallingConv.h" 29#include "llvm/Constants.h" 30#include "llvm/DerivedTypes.h" 31#include "llvm/Function.h" 32#include "llvm/GlobalVariable.h" 33#include "llvm/LLVMContext.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Compiler.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/ADT/DenseMap.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/ADT/SmallPtrSet.h" 41#include <map> 42using namespace llvm; 43 44//===----------------------------------------------------------------------===// 45/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 46/// hacks on it until the target machine can handle it. This involves 47/// eliminating value sizes the machine cannot handle (promoting small sizes to 48/// large sizes or splitting up large values into small values) as well as 49/// eliminating operations the machine cannot handle. 50/// 51/// This code also does a small amount of optimization and recognition of idioms 52/// as part of its processing. For example, if a target does not support a 53/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 54/// will attempt merge setcc and brc instructions into brcc's. 55/// 56namespace { 57class VISIBILITY_HIDDEN SelectionDAGLegalize { 58 TargetLowering &TLI; 59 SelectionDAG &DAG; 60 CodeGenOpt::Level OptLevel; 61 62 // Libcall insertion helpers. 63 64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 65 /// legalized. We use this to ensure that calls are properly serialized 66 /// against each other, including inserted libcalls. 67 SDValue LastCALLSEQ_END; 68 69 /// IsLegalizingCall - This member is used *only* for purposes of providing 70 /// helpful assertions that a libcall isn't created while another call is 71 /// being legalized (which could lead to non-serialized call sequences). 72 bool IsLegalizingCall; 73 74 enum LegalizeAction { 75 Legal, // The target natively supports this operation. 76 Promote, // This operation should be executed in a larger type. 77 Expand // Try to expand this to other ops, otherwise use a libcall. 78 }; 79 80 /// ValueTypeActions - This is a bitvector that contains two bits for each 81 /// value type, where the two bits correspond to the LegalizeAction enum. 82 /// This can be queried with "getTypeAction(VT)". 83 TargetLowering::ValueTypeActionImpl ValueTypeActions; 84 85 /// LegalizedNodes - For nodes that are of legal width, and that have more 86 /// than one use, this map indicates what regularized operand to use. This 87 /// allows us to avoid legalizing the same thing more than once. 88 DenseMap<SDValue, SDValue> LegalizedNodes; 89 90 void AddLegalizedOperand(SDValue From, SDValue To) { 91 LegalizedNodes.insert(std::make_pair(From, To)); 92 // If someone requests legalization of the new node, return itself. 93 if (From != To) 94 LegalizedNodes.insert(std::make_pair(To, To)); 95 } 96 97public: 98 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 99 100 /// getTypeAction - Return how we should legalize values of this type, either 101 /// it is already legal or we need to expand it into multiple registers of 102 /// smaller integer type, or we need to promote it to a larger type. 103 LegalizeAction getTypeAction(MVT VT) const { 104 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 105 } 106 107 /// isTypeLegal - Return true if this type is legal on this target. 108 /// 109 bool isTypeLegal(MVT VT) const { 110 return getTypeAction(VT) == Legal; 111 } 112 113 void LegalizeDAG(); 114 115private: 116 /// LegalizeOp - We know that the specified value has a legal type. 117 /// Recursively ensure that the operands have legal types, then return the 118 /// result. 119 SDValue LegalizeOp(SDValue O); 120 121 SDValue OptimizeFloatStore(StoreSDNode *ST); 122 123 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 124 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 125 /// is necessary to spill the vector being inserted into to memory, perform 126 /// the insert there, and then read the result back. 127 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 128 SDValue Idx, DebugLoc dl); 129 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 130 SDValue Idx, DebugLoc dl); 131 132 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 133 /// performs the same shuffe in terms of order or result bytes, but on a type 134 /// whose vector element type is narrower than the original shuffle type. 135 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 136 SDValue ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl, 137 SDValue N1, SDValue N2, 138 SmallVectorImpl<int> &Mask) const; 139 140 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 141 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 142 143 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 144 DebugLoc dl); 145 146 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 147 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 148 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 149 RTLIB::Libcall Call_PPCF128); 150 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, RTLIB::Libcall Call_I16, 151 RTLIB::Libcall Call_I32, RTLIB::Libcall Call_I64, 152 RTLIB::Libcall Call_I128); 153 154 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl); 155 SDValue ExpandBUILD_VECTOR(SDNode *Node); 156 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 157 SDValue ExpandDBG_STOPPOINT(SDNode *Node); 158 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 159 SmallVectorImpl<SDValue> &Results); 160 SDValue ExpandFCOPYSIGN(SDNode *Node); 161 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT, 162 DebugLoc dl); 163 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned, 164 DebugLoc dl); 165 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned, 166 DebugLoc dl); 167 168 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 169 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 170 171 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 172 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 173 174 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 175 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 176}; 177} 178 179/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 180/// performs the same shuffe in terms of order or result bytes, but on a type 181/// whose vector element type is narrower than the original shuffle type. 182/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 183SDValue 184SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl, 185 SDValue N1, SDValue N2, 186 SmallVectorImpl<int> &Mask) const { 187 MVT EltVT = NVT.getVectorElementType(); 188 unsigned NumMaskElts = VT.getVectorNumElements(); 189 unsigned NumDestElts = NVT.getVectorNumElements(); 190 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 191 192 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 193 194 if (NumEltsGrowth == 1) 195 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 196 197 SmallVector<int, 8> NewMask; 198 for (unsigned i = 0; i != NumMaskElts; ++i) { 199 int Idx = Mask[i]; 200 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 201 if (Idx < 0) 202 NewMask.push_back(-1); 203 else 204 NewMask.push_back(Idx * NumEltsGrowth + j); 205 } 206 } 207 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 208 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 209 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 210} 211 212SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 213 CodeGenOpt::Level ol) 214 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), 215 ValueTypeActions(TLI.getValueTypeActions()) { 216 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 217 "Too many value types for ValueTypeActions to hold!"); 218} 219 220void SelectionDAGLegalize::LegalizeDAG() { 221 LastCALLSEQ_END = DAG.getEntryNode(); 222 IsLegalizingCall = false; 223 224 // The legalize process is inherently a bottom-up recursive process (users 225 // legalize their uses before themselves). Given infinite stack space, we 226 // could just start legalizing on the root and traverse the whole graph. In 227 // practice however, this causes us to run out of stack space on large basic 228 // blocks. To avoid this problem, compute an ordering of the nodes where each 229 // node is only legalized after all of its operands are legalized. 230 DAG.AssignTopologicalOrder(); 231 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 232 E = prior(DAG.allnodes_end()); I != next(E); ++I) 233 LegalizeOp(SDValue(I, 0)); 234 235 // Finally, it's possible the root changed. Get the new root. 236 SDValue OldRoot = DAG.getRoot(); 237 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 238 DAG.setRoot(LegalizedNodes[OldRoot]); 239 240 LegalizedNodes.clear(); 241 242 // Remove dead nodes now. 243 DAG.RemoveDeadNodes(); 244} 245 246 247/// FindCallEndFromCallStart - Given a chained node that is part of a call 248/// sequence, find the CALLSEQ_END node that terminates the call sequence. 249static SDNode *FindCallEndFromCallStart(SDNode *Node) { 250 if (Node->getOpcode() == ISD::CALLSEQ_END) 251 return Node; 252 if (Node->use_empty()) 253 return 0; // No CallSeqEnd 254 255 // The chain is usually at the end. 256 SDValue TheChain(Node, Node->getNumValues()-1); 257 if (TheChain.getValueType() != MVT::Other) { 258 // Sometimes it's at the beginning. 259 TheChain = SDValue(Node, 0); 260 if (TheChain.getValueType() != MVT::Other) { 261 // Otherwise, hunt for it. 262 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 263 if (Node->getValueType(i) == MVT::Other) { 264 TheChain = SDValue(Node, i); 265 break; 266 } 267 268 // Otherwise, we walked into a node without a chain. 269 if (TheChain.getValueType() != MVT::Other) 270 return 0; 271 } 272 } 273 274 for (SDNode::use_iterator UI = Node->use_begin(), 275 E = Node->use_end(); UI != E; ++UI) { 276 277 // Make sure to only follow users of our token chain. 278 SDNode *User = *UI; 279 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 280 if (User->getOperand(i) == TheChain) 281 if (SDNode *Result = FindCallEndFromCallStart(User)) 282 return Result; 283 } 284 return 0; 285} 286 287/// FindCallStartFromCallEnd - Given a chained node that is part of a call 288/// sequence, find the CALLSEQ_START node that initiates the call sequence. 289static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 290 assert(Node && "Didn't find callseq_start for a call??"); 291 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 292 293 assert(Node->getOperand(0).getValueType() == MVT::Other && 294 "Node doesn't have a token chain argument!"); 295 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 296} 297 298/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 299/// see if any uses can reach Dest. If no dest operands can get to dest, 300/// legalize them, legalize ourself, and return false, otherwise, return true. 301/// 302/// Keep track of the nodes we fine that actually do lead to Dest in 303/// NodesLeadingTo. This avoids retraversing them exponential number of times. 304/// 305bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 306 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 307 if (N == Dest) return true; // N certainly leads to Dest :) 308 309 // If we've already processed this node and it does lead to Dest, there is no 310 // need to reprocess it. 311 if (NodesLeadingTo.count(N)) return true; 312 313 // If the first result of this node has been already legalized, then it cannot 314 // reach N. 315 if (LegalizedNodes.count(SDValue(N, 0))) return false; 316 317 // Okay, this node has not already been legalized. Check and legalize all 318 // operands. If none lead to Dest, then we can legalize this node. 319 bool OperandsLeadToDest = false; 320 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 321 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 322 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 323 324 if (OperandsLeadToDest) { 325 NodesLeadingTo.insert(N); 326 return true; 327 } 328 329 // Okay, this node looks safe, legalize it and return false. 330 LegalizeOp(SDValue(N, 0)); 331 return false; 332} 333 334/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 335/// a load from the constant pool. 336static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 337 SelectionDAG &DAG, const TargetLowering &TLI) { 338 bool Extend = false; 339 DebugLoc dl = CFP->getDebugLoc(); 340 341 // If a FP immediate is precise when represented as a float and if the 342 // target can do an extending load from float to double, we put it into 343 // the constant pool as a float, even if it's is statically typed as a 344 // double. This shrinks FP constants and canonicalizes them for targets where 345 // an FP extending load is the same cost as a normal load (such as on the x87 346 // fp stack or PPC FP unit). 347 MVT VT = CFP->getValueType(0); 348 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 349 if (!UseCP) { 350 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 351 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 352 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 353 } 354 355 MVT OrigVT = VT; 356 MVT SVT = VT; 357 while (SVT != MVT::f32) { 358 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 359 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 360 // Only do this if the target has a native EXTLOAD instruction from 361 // smaller type. 362 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 363 TLI.ShouldShrinkFPConstant(OrigVT)) { 364 const Type *SType = SVT.getTypeForMVT(*DAG.getContext()); 365 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 366 VT = SVT; 367 Extend = true; 368 } 369 } 370 371 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 372 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 373 if (Extend) 374 return DAG.getExtLoad(ISD::EXTLOAD, dl, 375 OrigVT, DAG.getEntryNode(), 376 CPIdx, PseudoSourceValue::getConstantPool(), 377 0, VT, false, Alignment); 378 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 379 PseudoSourceValue::getConstantPool(), 0, false, Alignment); 380} 381 382/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 383static 384SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 385 const TargetLowering &TLI) { 386 SDValue Chain = ST->getChain(); 387 SDValue Ptr = ST->getBasePtr(); 388 SDValue Val = ST->getValue(); 389 MVT VT = Val.getValueType(); 390 int Alignment = ST->getAlignment(); 391 int SVOffset = ST->getSrcValueOffset(); 392 DebugLoc dl = ST->getDebugLoc(); 393 if (ST->getMemoryVT().isFloatingPoint() || 394 ST->getMemoryVT().isVector()) { 395 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits()); 396 if (TLI.isTypeLegal(intVT)) { 397 // Expand to a bitconvert of the value to the integer type of the 398 // same size, then a (misaligned) int store. 399 // FIXME: Does not handle truncating floating point stores! 400 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 401 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 402 SVOffset, ST->isVolatile(), Alignment); 403 } else { 404 // Do a (aligned) store to a stack slot, then copy from the stack slot 405 // to the final destination using (unaligned) integer loads and stores. 406 MVT StoredVT = ST->getMemoryVT(); 407 MVT RegVT = 408 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits())); 409 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 410 unsigned RegBytes = RegVT.getSizeInBits() / 8; 411 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 412 413 // Make sure the stack slot is also aligned for the register type. 414 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 415 416 // Perform the original store, only redirected to the stack slot. 417 SDValue Store = DAG.getTruncStore(Chain, dl, 418 Val, StackPtr, NULL, 0, StoredVT); 419 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 420 SmallVector<SDValue, 8> Stores; 421 unsigned Offset = 0; 422 423 // Do all but one copies using the full register width. 424 for (unsigned i = 1; i < NumRegs; i++) { 425 // Load one integer register's worth from the stack slot. 426 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0); 427 // Store it to the final location. Remember the store. 428 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 429 ST->getSrcValue(), SVOffset + Offset, 430 ST->isVolatile(), 431 MinAlign(ST->getAlignment(), Offset))); 432 // Increment the pointers. 433 Offset += RegBytes; 434 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 435 Increment); 436 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 437 } 438 439 // The last store may be partial. Do a truncating store. On big-endian 440 // machines this requires an extending load from the stack slot to ensure 441 // that the bits are in the right place. 442 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset)); 443 444 // Load from the stack slot. 445 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 446 NULL, 0, MemVT); 447 448 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 449 ST->getSrcValue(), SVOffset + Offset, 450 MemVT, ST->isVolatile(), 451 MinAlign(ST->getAlignment(), Offset))); 452 // The order of the stores doesn't matter - say it with a TokenFactor. 453 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 454 Stores.size()); 455 } 456 } 457 assert(ST->getMemoryVT().isInteger() && 458 !ST->getMemoryVT().isVector() && 459 "Unaligned store of unknown type."); 460 // Get the half-size VT 461 MVT NewStoredVT = 462 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 463 int NumBits = NewStoredVT.getSizeInBits(); 464 int IncrementSize = NumBits / 8; 465 466 // Divide the stored value in two parts. 467 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 468 SDValue Lo = Val; 469 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 470 471 // Store the two parts 472 SDValue Store1, Store2; 473 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 474 ST->getSrcValue(), SVOffset, NewStoredVT, 475 ST->isVolatile(), Alignment); 476 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 477 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 478 Alignment = MinAlign(Alignment, IncrementSize); 479 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 480 ST->getSrcValue(), SVOffset + IncrementSize, 481 NewStoredVT, ST->isVolatile(), Alignment); 482 483 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 484} 485 486/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 487static 488SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 489 const TargetLowering &TLI) { 490 int SVOffset = LD->getSrcValueOffset(); 491 SDValue Chain = LD->getChain(); 492 SDValue Ptr = LD->getBasePtr(); 493 MVT VT = LD->getValueType(0); 494 MVT LoadedVT = LD->getMemoryVT(); 495 DebugLoc dl = LD->getDebugLoc(); 496 if (VT.isFloatingPoint() || VT.isVector()) { 497 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits()); 498 if (TLI.isTypeLegal(intVT)) { 499 // Expand to a (misaligned) integer load of the same size, 500 // then bitconvert to floating point or vector. 501 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 502 SVOffset, LD->isVolatile(), 503 LD->getAlignment()); 504 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 505 if (VT.isFloatingPoint() && LoadedVT != VT) 506 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 507 508 SDValue Ops[] = { Result, Chain }; 509 return DAG.getMergeValues(Ops, 2, dl); 510 } else { 511 // Copy the value to a (aligned) stack slot using (unaligned) integer 512 // loads and stores, then do a (aligned) load from the stack slot. 513 MVT RegVT = TLI.getRegisterType(intVT); 514 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 515 unsigned RegBytes = RegVT.getSizeInBits() / 8; 516 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 517 518 // Make sure the stack slot is also aligned for the register type. 519 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 520 521 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 522 SmallVector<SDValue, 8> Stores; 523 SDValue StackPtr = StackBase; 524 unsigned Offset = 0; 525 526 // Do all but one copies using the full register width. 527 for (unsigned i = 1; i < NumRegs; i++) { 528 // Load one integer register's worth from the original location. 529 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 530 SVOffset + Offset, LD->isVolatile(), 531 MinAlign(LD->getAlignment(), Offset)); 532 // Follow the load with a store to the stack slot. Remember the store. 533 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 534 NULL, 0)); 535 // Increment the pointers. 536 Offset += RegBytes; 537 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 538 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 539 Increment); 540 } 541 542 // The last copy may be partial. Do an extending load. 543 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset)); 544 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 545 LD->getSrcValue(), SVOffset + Offset, 546 MemVT, LD->isVolatile(), 547 MinAlign(LD->getAlignment(), Offset)); 548 // Follow the load with a store to the stack slot. Remember the store. 549 // On big-endian machines this requires a truncating store to ensure 550 // that the bits end up in the right place. 551 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 552 NULL, 0, MemVT)); 553 554 // The order of the stores doesn't matter - say it with a TokenFactor. 555 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 556 Stores.size()); 557 558 // Finally, perform the original load only redirected to the stack slot. 559 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 560 NULL, 0, LoadedVT); 561 562 // Callers expect a MERGE_VALUES node. 563 SDValue Ops[] = { Load, TF }; 564 return DAG.getMergeValues(Ops, 2, dl); 565 } 566 } 567 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 568 "Unaligned load of unsupported type."); 569 570 // Compute the new VT that is half the size of the old one. This is an 571 // integer MVT. 572 unsigned NumBits = LoadedVT.getSizeInBits(); 573 MVT NewLoadedVT; 574 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 575 NumBits >>= 1; 576 577 unsigned Alignment = LD->getAlignment(); 578 unsigned IncrementSize = NumBits / 8; 579 ISD::LoadExtType HiExtType = LD->getExtensionType(); 580 581 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 582 if (HiExtType == ISD::NON_EXTLOAD) 583 HiExtType = ISD::ZEXTLOAD; 584 585 // Load the value in two parts 586 SDValue Lo, Hi; 587 if (TLI.isLittleEndian()) { 588 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 589 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 590 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 591 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 592 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 593 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 594 MinAlign(Alignment, IncrementSize)); 595 } else { 596 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 597 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 598 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 599 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 600 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 601 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 602 MinAlign(Alignment, IncrementSize)); 603 } 604 605 // aggregate the two parts 606 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 607 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 608 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 609 610 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 611 Hi.getValue(1)); 612 613 SDValue Ops[] = { Result, TF }; 614 return DAG.getMergeValues(Ops, 2, dl); 615} 616 617/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 618/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 619/// is necessary to spill the vector being inserted into to memory, perform 620/// the insert there, and then read the result back. 621SDValue SelectionDAGLegalize:: 622PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 623 DebugLoc dl) { 624 SDValue Tmp1 = Vec; 625 SDValue Tmp2 = Val; 626 SDValue Tmp3 = Idx; 627 628 // If the target doesn't support this, we have to spill the input vector 629 // to a temporary stack slot, update the element, then reload it. This is 630 // badness. We could also load the value into a vector register (either 631 // with a "move to register" or "extload into register" instruction, then 632 // permute it into place, if the idx is a constant and if the idx is 633 // supported by the target. 634 MVT VT = Tmp1.getValueType(); 635 MVT EltVT = VT.getVectorElementType(); 636 MVT IdxVT = Tmp3.getValueType(); 637 MVT PtrVT = TLI.getPointerTy(); 638 SDValue StackPtr = DAG.CreateStackTemporary(VT); 639 640 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 641 642 // Store the vector. 643 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 644 PseudoSourceValue::getFixedStack(SPFI), 0); 645 646 // Truncate or zero extend offset to target pointer type. 647 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 648 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 649 // Add the offset to the index. 650 unsigned EltSize = EltVT.getSizeInBits()/8; 651 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 652 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 653 // Store the scalar value. 654 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 655 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); 656 // Load the updated vector. 657 return DAG.getLoad(VT, dl, Ch, StackPtr, 658 PseudoSourceValue::getFixedStack(SPFI), 0); 659} 660 661 662SDValue SelectionDAGLegalize:: 663ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 664 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 665 // SCALAR_TO_VECTOR requires that the type of the value being inserted 666 // match the element type of the vector being created, except for 667 // integers in which case the inserted value can be over width. 668 MVT EltVT = Vec.getValueType().getVectorElementType(); 669 if (Val.getValueType() == EltVT || 670 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 671 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 672 Vec.getValueType(), Val); 673 674 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 675 // We generate a shuffle of InVec and ScVec, so the shuffle mask 676 // should be 0,1,2,3,4,5... with the appropriate element replaced with 677 // elt 0 of the RHS. 678 SmallVector<int, 8> ShufOps; 679 for (unsigned i = 0; i != NumElts; ++i) 680 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 681 682 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 683 &ShufOps[0]); 684 } 685 } 686 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 687} 688 689SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 690 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 691 // FIXME: We shouldn't do this for TargetConstantFP's. 692 // FIXME: move this to the DAG Combiner! Note that we can't regress due 693 // to phase ordering between legalized code and the dag combiner. This 694 // probably means that we need to integrate dag combiner and legalizer 695 // together. 696 // We generally can't do this one for long doubles. 697 SDValue Tmp1 = ST->getChain(); 698 SDValue Tmp2 = ST->getBasePtr(); 699 SDValue Tmp3; 700 int SVOffset = ST->getSrcValueOffset(); 701 unsigned Alignment = ST->getAlignment(); 702 bool isVolatile = ST->isVolatile(); 703 DebugLoc dl = ST->getDebugLoc(); 704 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 705 if (CFP->getValueType(0) == MVT::f32 && 706 getTypeAction(MVT::i32) == Legal) { 707 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 708 bitcastToAPInt().zextOrTrunc(32), 709 MVT::i32); 710 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 711 SVOffset, isVolatile, Alignment); 712 } else if (CFP->getValueType(0) == MVT::f64) { 713 // If this target supports 64-bit registers, do a single 64-bit store. 714 if (getTypeAction(MVT::i64) == Legal) { 715 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 716 zextOrTrunc(64), MVT::i64); 717 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 718 SVOffset, isVolatile, Alignment); 719 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 720 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 721 // stores. If the target supports neither 32- nor 64-bits, this 722 // xform is certainly not worth it. 723 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 724 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 725 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 726 if (TLI.isBigEndian()) std::swap(Lo, Hi); 727 728 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 729 SVOffset, isVolatile, Alignment); 730 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 731 DAG.getIntPtrConstant(4)); 732 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 733 isVolatile, MinAlign(Alignment, 4U)); 734 735 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 736 } 737 } 738 } 739 return SDValue(); 740} 741 742/// LegalizeOp - We know that the specified value has a legal type, and 743/// that its operands are legal. Now ensure that the operation itself 744/// is legal, recursively ensuring that the operands' operations remain 745/// legal. 746SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 747 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 748 return Op; 749 750 SDNode *Node = Op.getNode(); 751 DebugLoc dl = Node->getDebugLoc(); 752 753 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 754 assert(getTypeAction(Node->getValueType(i)) == Legal && 755 "Unexpected illegal type!"); 756 757 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 758 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 759 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 760 "Unexpected illegal type!"); 761 762 // Note that LegalizeOp may be reentered even from single-use nodes, which 763 // means that we always must cache transformed nodes. 764 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 765 if (I != LegalizedNodes.end()) return I->second; 766 767 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 768 SDValue Result = Op; 769 bool isCustom = false; 770 771 // Figure out the correct action; the way to query this varies by opcode 772 TargetLowering::LegalizeAction Action; 773 bool SimpleFinishLegalizing = true; 774 switch (Node->getOpcode()) { 775 case ISD::INTRINSIC_W_CHAIN: 776 case ISD::INTRINSIC_WO_CHAIN: 777 case ISD::INTRINSIC_VOID: 778 case ISD::VAARG: 779 case ISD::STACKSAVE: 780 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 781 break; 782 case ISD::SINT_TO_FP: 783 case ISD::UINT_TO_FP: 784 case ISD::EXTRACT_VECTOR_ELT: 785 Action = TLI.getOperationAction(Node->getOpcode(), 786 Node->getOperand(0).getValueType()); 787 break; 788 case ISD::FP_ROUND_INREG: 789 case ISD::SIGN_EXTEND_INREG: { 790 MVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 791 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 792 break; 793 } 794 case ISD::SELECT_CC: 795 case ISD::SETCC: 796 case ISD::BR_CC: { 797 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 798 Node->getOpcode() == ISD::SETCC ? 2 : 1; 799 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 800 MVT OpVT = Node->getOperand(CompareOperand).getValueType(); 801 ISD::CondCode CCCode = 802 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 803 Action = TLI.getCondCodeAction(CCCode, OpVT); 804 if (Action == TargetLowering::Legal) { 805 if (Node->getOpcode() == ISD::SELECT_CC) 806 Action = TLI.getOperationAction(Node->getOpcode(), 807 Node->getValueType(0)); 808 else 809 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 810 } 811 break; 812 } 813 case ISD::LOAD: 814 case ISD::STORE: 815 // FIXME: Model these properly. LOAD and STORE are complicated, and 816 // STORE expects the unlegalized operand in some cases. 817 SimpleFinishLegalizing = false; 818 break; 819 case ISD::CALLSEQ_START: 820 case ISD::CALLSEQ_END: 821 // FIXME: This shouldn't be necessary. These nodes have special properties 822 // dealing with the recursive nature of legalization. Removing this 823 // special case should be done as part of making LegalizeDAG non-recursive. 824 SimpleFinishLegalizing = false; 825 break; 826 case ISD::CALL: 827 // FIXME: Legalization for calls requires custom-lowering the call before 828 // legalizing the operands! (I haven't looked into precisely why.) 829 SimpleFinishLegalizing = false; 830 break; 831 case ISD::EXTRACT_ELEMENT: 832 case ISD::FLT_ROUNDS_: 833 case ISD::SADDO: 834 case ISD::SSUBO: 835 case ISD::UADDO: 836 case ISD::USUBO: 837 case ISD::SMULO: 838 case ISD::UMULO: 839 case ISD::FPOWI: 840 case ISD::MERGE_VALUES: 841 case ISD::EH_RETURN: 842 case ISD::FRAME_TO_ARGS_OFFSET: 843 // These operations lie about being legal: when they claim to be legal, 844 // they should actually be expanded. 845 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 846 if (Action == TargetLowering::Legal) 847 Action = TargetLowering::Expand; 848 break; 849 case ISD::TRAMPOLINE: 850 case ISD::FRAMEADDR: 851 case ISD::RETURNADDR: 852 case ISD::FORMAL_ARGUMENTS: 853 // These operations lie about being legal: when they claim to be legal, 854 // they should actually be custom-lowered. 855 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 856 if (Action == TargetLowering::Legal) 857 Action = TargetLowering::Custom; 858 break; 859 case ISD::BUILD_VECTOR: 860 // A weird case: legalization for BUILD_VECTOR never legalizes the 861 // operands! 862 // FIXME: This really sucks... changing it isn't semantically incorrect, 863 // but it massively pessimizes the code for floating-point BUILD_VECTORs 864 // because ConstantFP operands get legalized into constant pool loads 865 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 866 // though, because BUILD_VECTORS usually get lowered into other nodes 867 // which get legalized properly. 868 SimpleFinishLegalizing = false; 869 break; 870 default: 871 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 872 Action = TargetLowering::Legal; 873 } else { 874 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 875 } 876 break; 877 } 878 879 if (SimpleFinishLegalizing) { 880 SmallVector<SDValue, 8> Ops, ResultVals; 881 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 882 Ops.push_back(LegalizeOp(Node->getOperand(i))); 883 switch (Node->getOpcode()) { 884 default: break; 885 case ISD::BR: 886 case ISD::BRIND: 887 case ISD::BR_JT: 888 case ISD::BR_CC: 889 case ISD::BRCOND: 890 case ISD::RET: 891 // Branches tweak the chain to include LastCALLSEQ_END 892 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 893 LastCALLSEQ_END); 894 Ops[0] = LegalizeOp(Ops[0]); 895 LastCALLSEQ_END = DAG.getEntryNode(); 896 break; 897 case ISD::SHL: 898 case ISD::SRL: 899 case ISD::SRA: 900 case ISD::ROTL: 901 case ISD::ROTR: 902 // Legalizing shifts/rotates requires adjusting the shift amount 903 // to the appropriate width. 904 if (!Ops[1].getValueType().isVector()) 905 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 906 break; 907 } 908 909 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(), 910 Ops.size()); 911 switch (Action) { 912 case TargetLowering::Legal: 913 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 914 ResultVals.push_back(Result.getValue(i)); 915 break; 916 case TargetLowering::Custom: 917 // FIXME: The handling for custom lowering with multiple results is 918 // a complete mess. 919 Tmp1 = TLI.LowerOperation(Result, DAG); 920 if (Tmp1.getNode()) { 921 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 922 if (e == 1) 923 ResultVals.push_back(Tmp1); 924 else 925 ResultVals.push_back(Tmp1.getValue(i)); 926 } 927 break; 928 } 929 930 // FALL THROUGH 931 case TargetLowering::Expand: 932 ExpandNode(Result.getNode(), ResultVals); 933 break; 934 case TargetLowering::Promote: 935 PromoteNode(Result.getNode(), ResultVals); 936 break; 937 } 938 if (!ResultVals.empty()) { 939 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 940 if (ResultVals[i] != SDValue(Node, i)) 941 ResultVals[i] = LegalizeOp(ResultVals[i]); 942 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 943 } 944 return ResultVals[Op.getResNo()]; 945 } 946 } 947 948 switch (Node->getOpcode()) { 949 default: 950#ifndef NDEBUG 951 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 952#endif 953 llvm_unreachable("Do not know how to legalize this operator!"); 954 case ISD::CALL: 955 // The only option for this is to custom lower it. 956 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 957 assert(Tmp3.getNode() && "Target didn't custom lower this node!"); 958 // A call within a calling sequence must be legalized to something 959 // other than the normal CALLSEQ_END. Violating this gets Legalize 960 // into an infinite loop. 961 assert ((!IsLegalizingCall || 962 Node->getOpcode() != ISD::CALL || 963 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) && 964 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 965 966 // The number of incoming and outgoing values should match; unless the final 967 // outgoing value is a flag. 968 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() || 969 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 && 970 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) == 971 MVT::Flag)) && 972 "Lowering call/formal_arguments produced unexpected # results!"); 973 974 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 975 // remember that we legalized all of them, so it doesn't get relegalized. 976 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) { 977 if (Tmp3.getNode()->getValueType(i) == MVT::Flag) 978 continue; 979 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 980 if (Op.getResNo() == i) 981 Tmp2 = Tmp1; 982 AddLegalizedOperand(SDValue(Node, i), Tmp1); 983 } 984 return Tmp2; 985 case ISD::BUILD_VECTOR: 986 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 987 default: llvm_unreachable("This action is not supported yet!"); 988 case TargetLowering::Custom: 989 Tmp3 = TLI.LowerOperation(Result, DAG); 990 if (Tmp3.getNode()) { 991 Result = Tmp3; 992 break; 993 } 994 // FALLTHROUGH 995 case TargetLowering::Expand: 996 Result = ExpandBUILD_VECTOR(Result.getNode()); 997 break; 998 } 999 break; 1000 case ISD::CALLSEQ_START: { 1001 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1002 1003 // Recursively Legalize all of the inputs of the call end that do not lead 1004 // to this call start. This ensures that any libcalls that need be inserted 1005 // are inserted *before* the CALLSEQ_START. 1006 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1007 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1008 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1009 NodesLeadingTo); 1010 } 1011 1012 // Now that we legalized all of the inputs (which may have inserted 1013 // libcalls) create the new CALLSEQ_START node. 1014 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1015 1016 // Merge in the last call, to ensure that this call start after the last 1017 // call ended. 1018 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1019 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1020 Tmp1, LastCALLSEQ_END); 1021 Tmp1 = LegalizeOp(Tmp1); 1022 } 1023 1024 // Do not try to legalize the target-specific arguments (#1+). 1025 if (Tmp1 != Node->getOperand(0)) { 1026 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1027 Ops[0] = Tmp1; 1028 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1029 } 1030 1031 // Remember that the CALLSEQ_START is legalized. 1032 AddLegalizedOperand(Op.getValue(0), Result); 1033 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1034 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1035 1036 // Now that the callseq_start and all of the non-call nodes above this call 1037 // sequence have been legalized, legalize the call itself. During this 1038 // process, no libcalls can/will be inserted, guaranteeing that no calls 1039 // can overlap. 1040 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1041 // Note that we are selecting this call! 1042 LastCALLSEQ_END = SDValue(CallEnd, 0); 1043 IsLegalizingCall = true; 1044 1045 // Legalize the call, starting from the CALLSEQ_END. 1046 LegalizeOp(LastCALLSEQ_END); 1047 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1048 return Result; 1049 } 1050 case ISD::CALLSEQ_END: 1051 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1052 // will cause this node to be legalized as well as handling libcalls right. 1053 if (LastCALLSEQ_END.getNode() != Node) { 1054 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1055 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1056 assert(I != LegalizedNodes.end() && 1057 "Legalizing the call start should have legalized this node!"); 1058 return I->second; 1059 } 1060 1061 // Otherwise, the call start has been legalized and everything is going 1062 // according to plan. Just legalize ourselves normally here. 1063 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1064 // Do not try to legalize the target-specific arguments (#1+), except for 1065 // an optional flag input. 1066 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1067 if (Tmp1 != Node->getOperand(0)) { 1068 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1069 Ops[0] = Tmp1; 1070 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1071 } 1072 } else { 1073 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1074 if (Tmp1 != Node->getOperand(0) || 1075 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1076 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1077 Ops[0] = Tmp1; 1078 Ops.back() = Tmp2; 1079 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1080 } 1081 } 1082 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1083 // This finishes up call legalization. 1084 IsLegalizingCall = false; 1085 1086 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1087 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1088 if (Node->getNumValues() == 2) 1089 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1090 return Result.getValue(Op.getResNo()); 1091 case ISD::LOAD: { 1092 LoadSDNode *LD = cast<LoadSDNode>(Node); 1093 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1094 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1095 1096 ISD::LoadExtType ExtType = LD->getExtensionType(); 1097 if (ExtType == ISD::NON_EXTLOAD) { 1098 MVT VT = Node->getValueType(0); 1099 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1100 Tmp3 = Result.getValue(0); 1101 Tmp4 = Result.getValue(1); 1102 1103 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1104 default: llvm_unreachable("This action is not supported yet!"); 1105 case TargetLowering::Legal: 1106 // If this is an unaligned load and the target doesn't support it, 1107 // expand it. 1108 if (!TLI.allowsUnalignedMemoryAccesses()) { 1109 unsigned ABIAlignment = TLI.getTargetData()-> 1110 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT( 1111 *DAG.getContext())); 1112 if (LD->getAlignment() < ABIAlignment){ 1113 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 1114 TLI); 1115 Tmp3 = Result.getOperand(0); 1116 Tmp4 = Result.getOperand(1); 1117 Tmp3 = LegalizeOp(Tmp3); 1118 Tmp4 = LegalizeOp(Tmp4); 1119 } 1120 } 1121 break; 1122 case TargetLowering::Custom: 1123 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1124 if (Tmp1.getNode()) { 1125 Tmp3 = LegalizeOp(Tmp1); 1126 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1127 } 1128 break; 1129 case TargetLowering::Promote: { 1130 // Only promote a load of vector type to another. 1131 assert(VT.isVector() && "Cannot promote this load!"); 1132 // Change base type to a different vector type. 1133 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1134 1135 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1136 LD->getSrcValueOffset(), 1137 LD->isVolatile(), LD->getAlignment()); 1138 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1139 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1140 break; 1141 } 1142 } 1143 // Since loads produce two values, make sure to remember that we 1144 // legalized both of them. 1145 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1146 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1147 return Op.getResNo() ? Tmp4 : Tmp3; 1148 } else { 1149 MVT SrcVT = LD->getMemoryVT(); 1150 unsigned SrcWidth = SrcVT.getSizeInBits(); 1151 int SVOffset = LD->getSrcValueOffset(); 1152 unsigned Alignment = LD->getAlignment(); 1153 bool isVolatile = LD->isVolatile(); 1154 1155 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1156 // Some targets pretend to have an i1 loading operation, and actually 1157 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1158 // bits are guaranteed to be zero; it helps the optimizers understand 1159 // that these bits are zero. It is also useful for EXTLOAD, since it 1160 // tells the optimizers that those bits are undefined. It would be 1161 // nice to have an effective generic way of getting these benefits... 1162 // Until such a way is found, don't insist on promoting i1 here. 1163 (SrcVT != MVT::i1 || 1164 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1165 // Promote to a byte-sized load if not loading an integral number of 1166 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1167 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1168 MVT NVT = MVT::getIntegerVT(NewWidth); 1169 SDValue Ch; 1170 1171 // The extra bits are guaranteed to be zero, since we stored them that 1172 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1173 1174 ISD::LoadExtType NewExtType = 1175 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1176 1177 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 1178 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1179 NVT, isVolatile, Alignment); 1180 1181 Ch = Result.getValue(1); // The chain. 1182 1183 if (ExtType == ISD::SEXTLOAD) 1184 // Having the top bits zero doesn't help when sign extending. 1185 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1186 Result.getValueType(), 1187 Result, DAG.getValueType(SrcVT)); 1188 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1189 // All the top bits are guaranteed to be zero - inform the optimizers. 1190 Result = DAG.getNode(ISD::AssertZext, dl, 1191 Result.getValueType(), Result, 1192 DAG.getValueType(SrcVT)); 1193 1194 Tmp1 = LegalizeOp(Result); 1195 Tmp2 = LegalizeOp(Ch); 1196 } else if (SrcWidth & (SrcWidth - 1)) { 1197 // If not loading a power-of-2 number of bits, expand as two loads. 1198 assert(SrcVT.isExtended() && !SrcVT.isVector() && 1199 "Unsupported extload!"); 1200 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1201 assert(RoundWidth < SrcWidth); 1202 unsigned ExtraWidth = SrcWidth - RoundWidth; 1203 assert(ExtraWidth < RoundWidth); 1204 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1205 "Load size not an integral number of bytes!"); 1206 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 1207 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 1208 SDValue Lo, Hi, Ch; 1209 unsigned IncrementSize; 1210 1211 if (TLI.isLittleEndian()) { 1212 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1213 // Load the bottom RoundWidth bits. 1214 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1215 Node->getValueType(0), Tmp1, Tmp2, 1216 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1217 Alignment); 1218 1219 // Load the remaining ExtraWidth bits. 1220 IncrementSize = RoundWidth / 8; 1221 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1222 DAG.getIntPtrConstant(IncrementSize)); 1223 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1224 LD->getSrcValue(), SVOffset + IncrementSize, 1225 ExtraVT, isVolatile, 1226 MinAlign(Alignment, IncrementSize)); 1227 1228 // Build a factor node to remember that this load is independent of the 1229 // other one. 1230 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1231 Hi.getValue(1)); 1232 1233 // Move the top bits to the right place. 1234 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1235 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1236 1237 // Join the hi and lo parts. 1238 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1239 } else { 1240 // Big endian - avoid unaligned loads. 1241 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1242 // Load the top RoundWidth bits. 1243 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1244 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1245 Alignment); 1246 1247 // Load the remaining ExtraWidth bits. 1248 IncrementSize = RoundWidth / 8; 1249 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1250 DAG.getIntPtrConstant(IncrementSize)); 1251 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1252 Node->getValueType(0), Tmp1, Tmp2, 1253 LD->getSrcValue(), SVOffset + IncrementSize, 1254 ExtraVT, isVolatile, 1255 MinAlign(Alignment, IncrementSize)); 1256 1257 // Build a factor node to remember that this load is independent of the 1258 // other one. 1259 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1260 Hi.getValue(1)); 1261 1262 // Move the top bits to the right place. 1263 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1264 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1265 1266 // Join the hi and lo parts. 1267 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1268 } 1269 1270 Tmp1 = LegalizeOp(Result); 1271 Tmp2 = LegalizeOp(Ch); 1272 } else { 1273 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1274 default: llvm_unreachable("This action is not supported yet!"); 1275 case TargetLowering::Custom: 1276 isCustom = true; 1277 // FALLTHROUGH 1278 case TargetLowering::Legal: 1279 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1280 Tmp1 = Result.getValue(0); 1281 Tmp2 = Result.getValue(1); 1282 1283 if (isCustom) { 1284 Tmp3 = TLI.LowerOperation(Result, DAG); 1285 if (Tmp3.getNode()) { 1286 Tmp1 = LegalizeOp(Tmp3); 1287 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1288 } 1289 } else { 1290 // If this is an unaligned load and the target doesn't support it, 1291 // expand it. 1292 if (!TLI.allowsUnalignedMemoryAccesses()) { 1293 unsigned ABIAlignment = TLI.getTargetData()-> 1294 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT( 1295 *DAG.getContext())); 1296 if (LD->getAlignment() < ABIAlignment){ 1297 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 1298 TLI); 1299 Tmp1 = Result.getOperand(0); 1300 Tmp2 = Result.getOperand(1); 1301 Tmp1 = LegalizeOp(Tmp1); 1302 Tmp2 = LegalizeOp(Tmp2); 1303 } 1304 } 1305 } 1306 break; 1307 case TargetLowering::Expand: 1308 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1309 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1310 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1311 LD->getSrcValueOffset(), 1312 LD->isVolatile(), LD->getAlignment()); 1313 Result = DAG.getNode(ISD::FP_EXTEND, dl, 1314 Node->getValueType(0), Load); 1315 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1316 Tmp2 = LegalizeOp(Load.getValue(1)); 1317 break; 1318 } 1319 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1320 // Turn the unsupported load into an EXTLOAD followed by an explicit 1321 // zero/sign extend inreg. 1322 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1323 Tmp1, Tmp2, LD->getSrcValue(), 1324 LD->getSrcValueOffset(), SrcVT, 1325 LD->isVolatile(), LD->getAlignment()); 1326 SDValue ValRes; 1327 if (ExtType == ISD::SEXTLOAD) 1328 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1329 Result.getValueType(), 1330 Result, DAG.getValueType(SrcVT)); 1331 else 1332 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1333 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1334 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1335 break; 1336 } 1337 } 1338 1339 // Since loads produce two values, make sure to remember that we legalized 1340 // both of them. 1341 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1342 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1343 return Op.getResNo() ? Tmp2 : Tmp1; 1344 } 1345 } 1346 case ISD::STORE: { 1347 StoreSDNode *ST = cast<StoreSDNode>(Node); 1348 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1349 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1350 int SVOffset = ST->getSrcValueOffset(); 1351 unsigned Alignment = ST->getAlignment(); 1352 bool isVolatile = ST->isVolatile(); 1353 1354 if (!ST->isTruncatingStore()) { 1355 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1356 Result = SDValue(OptStore, 0); 1357 break; 1358 } 1359 1360 { 1361 Tmp3 = LegalizeOp(ST->getValue()); 1362 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1363 ST->getOffset()); 1364 1365 MVT VT = Tmp3.getValueType(); 1366 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1367 default: llvm_unreachable("This action is not supported yet!"); 1368 case TargetLowering::Legal: 1369 // If this is an unaligned store and the target doesn't support it, 1370 // expand it. 1371 if (!TLI.allowsUnalignedMemoryAccesses()) { 1372 unsigned ABIAlignment = TLI.getTargetData()-> 1373 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT( 1374 *DAG.getContext())); 1375 if (ST->getAlignment() < ABIAlignment) 1376 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 1377 TLI); 1378 } 1379 break; 1380 case TargetLowering::Custom: 1381 Tmp1 = TLI.LowerOperation(Result, DAG); 1382 if (Tmp1.getNode()) Result = Tmp1; 1383 break; 1384 case TargetLowering::Promote: 1385 assert(VT.isVector() && "Unknown legal promote case!"); 1386 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1387 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1388 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1389 ST->getSrcValue(), SVOffset, isVolatile, 1390 Alignment); 1391 break; 1392 } 1393 break; 1394 } 1395 } else { 1396 Tmp3 = LegalizeOp(ST->getValue()); 1397 1398 MVT StVT = ST->getMemoryVT(); 1399 unsigned StWidth = StVT.getSizeInBits(); 1400 1401 if (StWidth != StVT.getStoreSizeInBits()) { 1402 // Promote to a byte-sized store with upper bits zero if not 1403 // storing an integral number of bytes. For example, promote 1404 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1405 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 1406 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1407 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1408 SVOffset, NVT, isVolatile, Alignment); 1409 } else if (StWidth & (StWidth - 1)) { 1410 // If not storing a power-of-2 number of bits, expand as two stores. 1411 assert(StVT.isExtended() && !StVT.isVector() && 1412 "Unsupported truncstore!"); 1413 unsigned RoundWidth = 1 << Log2_32(StWidth); 1414 assert(RoundWidth < StWidth); 1415 unsigned ExtraWidth = StWidth - RoundWidth; 1416 assert(ExtraWidth < RoundWidth); 1417 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1418 "Store size not an integral number of bytes!"); 1419 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 1420 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 1421 SDValue Lo, Hi; 1422 unsigned IncrementSize; 1423 1424 if (TLI.isLittleEndian()) { 1425 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1426 // Store the bottom RoundWidth bits. 1427 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1428 SVOffset, RoundVT, 1429 isVolatile, Alignment); 1430 1431 // Store the remaining ExtraWidth bits. 1432 IncrementSize = RoundWidth / 8; 1433 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1434 DAG.getIntPtrConstant(IncrementSize)); 1435 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1436 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1437 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1438 SVOffset + IncrementSize, ExtraVT, isVolatile, 1439 MinAlign(Alignment, IncrementSize)); 1440 } else { 1441 // Big endian - avoid unaligned stores. 1442 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1443 // Store the top RoundWidth bits. 1444 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1445 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1446 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1447 SVOffset, RoundVT, isVolatile, Alignment); 1448 1449 // Store the remaining ExtraWidth bits. 1450 IncrementSize = RoundWidth / 8; 1451 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1452 DAG.getIntPtrConstant(IncrementSize)); 1453 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1454 SVOffset + IncrementSize, ExtraVT, isVolatile, 1455 MinAlign(Alignment, IncrementSize)); 1456 } 1457 1458 // The order of the stores doesn't matter. 1459 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1460 } else { 1461 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1462 Tmp2 != ST->getBasePtr()) 1463 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1464 ST->getOffset()); 1465 1466 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1467 default: llvm_unreachable("This action is not supported yet!"); 1468 case TargetLowering::Legal: 1469 // If this is an unaligned store and the target doesn't support it, 1470 // expand it. 1471 if (!TLI.allowsUnalignedMemoryAccesses()) { 1472 unsigned ABIAlignment = TLI.getTargetData()-> 1473 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT( 1474 *DAG.getContext())); 1475 if (ST->getAlignment() < ABIAlignment) 1476 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 1477 TLI); 1478 } 1479 break; 1480 case TargetLowering::Custom: 1481 Result = TLI.LowerOperation(Result, DAG); 1482 break; 1483 case Expand: 1484 // TRUNCSTORE:i16 i32 -> STORE i16 1485 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1486 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1487 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1488 SVOffset, isVolatile, Alignment); 1489 break; 1490 } 1491 } 1492 } 1493 break; 1494 } 1495 } 1496 assert(Result.getValueType() == Op.getValueType() && 1497 "Bad legalization!"); 1498 1499 // Make sure that the generated code is itself legal. 1500 if (Result != Op) 1501 Result = LegalizeOp(Result); 1502 1503 // Note that LegalizeOp may be reentered even from single-use nodes, which 1504 // means that we always must cache transformed nodes. 1505 AddLegalizedOperand(Op, Result); 1506 return Result; 1507} 1508 1509SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1510 SDValue Vec = Op.getOperand(0); 1511 SDValue Idx = Op.getOperand(1); 1512 DebugLoc dl = Op.getDebugLoc(); 1513 // Store the value to a temporary stack slot, then LOAD the returned part. 1514 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1515 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0); 1516 1517 // Add the offset to the index. 1518 unsigned EltSize = 1519 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1520 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1521 DAG.getConstant(EltSize, Idx.getValueType())); 1522 1523 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1524 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1525 else 1526 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1527 1528 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1529 1530 if (Op.getValueType().isVector()) 1531 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0); 1532 else 1533 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1534 NULL, 0, Vec.getValueType().getVectorElementType()); 1535} 1536 1537SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1538 // We can't handle this case efficiently. Allocate a sufficiently 1539 // aligned object on the stack, store each element into it, then load 1540 // the result as a vector. 1541 // Create the stack frame object. 1542 MVT VT = Node->getValueType(0); 1543 MVT OpVT = Node->getOperand(0).getValueType(); 1544 DebugLoc dl = Node->getDebugLoc(); 1545 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1546 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1547 const Value *SV = PseudoSourceValue::getFixedStack(FI); 1548 1549 // Emit a store of each element to the stack slot. 1550 SmallVector<SDValue, 8> Stores; 1551 unsigned TypeByteSize = OpVT.getSizeInBits() / 8; 1552 // Store (in the right endianness) the elements to memory. 1553 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1554 // Ignore undef elements. 1555 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1556 1557 unsigned Offset = TypeByteSize*i; 1558 1559 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1560 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1561 1562 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i), 1563 Idx, SV, Offset)); 1564 } 1565 1566 SDValue StoreChain; 1567 if (!Stores.empty()) // Not all undef elements? 1568 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1569 &Stores[0], Stores.size()); 1570 else 1571 StoreChain = DAG.getEntryNode(); 1572 1573 // Result is a load from the stack slot. 1574 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0); 1575} 1576 1577SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1578 DebugLoc dl = Node->getDebugLoc(); 1579 SDValue Tmp1 = Node->getOperand(0); 1580 SDValue Tmp2 = Node->getOperand(1); 1581 assert((Tmp2.getValueType() == MVT::f32 || 1582 Tmp2.getValueType() == MVT::f64) && 1583 "Ugly special-cased code!"); 1584 // Get the sign bit of the RHS. 1585 SDValue SignBit; 1586 MVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32; 1587 if (isTypeLegal(IVT)) { 1588 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 1589 } else { 1590 assert(isTypeLegal(TLI.getPointerTy()) && 1591 (TLI.getPointerTy() == MVT::i32 || 1592 TLI.getPointerTy() == MVT::i64) && 1593 "Legal type for load?!"); 1594 SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType()); 1595 SDValue StorePtr = StackPtr, LoadPtr = StackPtr; 1596 SDValue Ch = 1597 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0); 1598 if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian()) 1599 LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), 1600 LoadPtr, DAG.getIntPtrConstant(4)); 1601 SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(), 1602 Ch, LoadPtr, NULL, 0, MVT::i32); 1603 } 1604 SignBit = 1605 DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1606 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1607 ISD::SETLT); 1608 // Get the absolute value of the result. 1609 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1610 // Select between the nabs and abs value based on the sign bit of 1611 // the input. 1612 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1613 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1614 AbsVal); 1615} 1616 1617SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) { 1618 DebugLoc dl = Node->getDebugLoc(); 1619 DwarfWriter *DW = DAG.getDwarfWriter(); 1620 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC, 1621 MVT::Other); 1622 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other); 1623 1624 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 1625 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit()); 1626 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) { 1627 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit())); 1628 1629 unsigned Line = DSP->getLine(); 1630 unsigned Col = DSP->getColumn(); 1631 1632 if (OptLevel == CodeGenOpt::None) { 1633 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it 1634 // won't hurt anything. 1635 if (useDEBUG_LOC) { 1636 return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0), 1637 DAG.getConstant(Line, MVT::i32), 1638 DAG.getConstant(Col, MVT::i32), 1639 DAG.getSrcValue(CU.getGV())); 1640 } else { 1641 unsigned ID = DW->RecordSourceLine(Line, Col, CU); 1642 return DAG.getLabel(ISD::DBG_LABEL, dl, Node->getOperand(0), ID); 1643 } 1644 } 1645 } 1646 return Node->getOperand(0); 1647} 1648 1649void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1650 SmallVectorImpl<SDValue> &Results) { 1651 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1652 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1653 " not tell us which reg is the stack pointer!"); 1654 DebugLoc dl = Node->getDebugLoc(); 1655 MVT VT = Node->getValueType(0); 1656 SDValue Tmp1 = SDValue(Node, 0); 1657 SDValue Tmp2 = SDValue(Node, 1); 1658 SDValue Tmp3 = Node->getOperand(2); 1659 SDValue Chain = Tmp1.getOperand(0); 1660 1661 // Chain the dynamic stack allocation so that it doesn't modify the stack 1662 // pointer when other instructions are using the stack. 1663 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1664 1665 SDValue Size = Tmp2.getOperand(1); 1666 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1667 Chain = SP.getValue(1); 1668 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1669 unsigned StackAlign = 1670 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1671 if (Align > StackAlign) 1672 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1673 DAG.getConstant(-(uint64_t)Align, VT)); 1674 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1675 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1676 1677 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1678 DAG.getIntPtrConstant(0, true), SDValue()); 1679 1680 Results.push_back(Tmp1); 1681 Results.push_back(Tmp2); 1682} 1683 1684/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1685/// condition code CC on the current target. This routine assumes LHS and rHS 1686/// have already been legalized by LegalizeSetCCOperands. It expands SETCC with 1687/// illegal condition code into AND / OR of multiple SETCC values. 1688void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, 1689 SDValue &LHS, SDValue &RHS, 1690 SDValue &CC, 1691 DebugLoc dl) { 1692 MVT OpVT = LHS.getValueType(); 1693 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1694 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1695 default: llvm_unreachable("Unknown condition code action!"); 1696 case TargetLowering::Legal: 1697 // Nothing to do. 1698 break; 1699 case TargetLowering::Expand: { 1700 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1701 unsigned Opc = 0; 1702 switch (CCCode) { 1703 default: llvm_unreachable("Don't know how to expand this condition!"); 1704 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1705 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1706 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1707 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1708 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1709 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1710 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1711 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1712 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1713 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1714 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1715 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1716 // FIXME: Implement more expansions. 1717 } 1718 1719 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1720 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1721 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1722 RHS = SDValue(); 1723 CC = SDValue(); 1724 break; 1725 } 1726 } 1727} 1728 1729/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1730/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1731/// a load from the stack slot to DestVT, extending it if needed. 1732/// The resultant code need not be legal. 1733SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1734 MVT SlotVT, 1735 MVT DestVT, 1736 DebugLoc dl) { 1737 // Create the stack frame object. 1738 unsigned SrcAlign = 1739 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1740 getTypeForMVT(*DAG.getContext())); 1741 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1742 1743 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1744 int SPFI = StackPtrFI->getIndex(); 1745 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1746 1747 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1748 unsigned SlotSize = SlotVT.getSizeInBits(); 1749 unsigned DestSize = DestVT.getSizeInBits(); 1750 unsigned DestAlign = 1751 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT( 1752 *DAG.getContext())); 1753 1754 // Emit a store to the stack slot. Use a truncstore if the input value is 1755 // later than DestVT. 1756 SDValue Store; 1757 1758 if (SrcSize > SlotSize) 1759 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1760 SV, 0, SlotVT, false, SrcAlign); 1761 else { 1762 assert(SrcSize == SlotSize && "Invalid store"); 1763 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1764 SV, 0, false, SrcAlign); 1765 } 1766 1767 // Result is a load from the stack slot. 1768 if (SlotSize == DestSize) 1769 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign); 1770 1771 assert(SlotSize < DestSize && "Unknown extension!"); 1772 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, 1773 false, DestAlign); 1774} 1775 1776SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1777 DebugLoc dl = Node->getDebugLoc(); 1778 // Create a vector sized/aligned stack slot, store the value to element #0, 1779 // then load the whole vector back out. 1780 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1781 1782 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1783 int SPFI = StackPtrFI->getIndex(); 1784 1785 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1786 StackPtr, 1787 PseudoSourceValue::getFixedStack(SPFI), 0, 1788 Node->getValueType(0).getVectorElementType()); 1789 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1790 PseudoSourceValue::getFixedStack(SPFI), 0); 1791} 1792 1793 1794/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1795/// support the operation, but do support the resultant vector type. 1796SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1797 LLVMContext *Context = DAG.getContext(); 1798 unsigned NumElems = Node->getNumOperands(); 1799 SDValue Value1, Value2; 1800 DebugLoc dl = Node->getDebugLoc(); 1801 MVT VT = Node->getValueType(0); 1802 MVT OpVT = Node->getOperand(0).getValueType(); 1803 MVT EltVT = VT.getVectorElementType(); 1804 1805 // If the only non-undef value is the low element, turn this into a 1806 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1807 bool isOnlyLowElement = true; 1808 bool MoreThanTwoValues = false; 1809 bool isConstant = true; 1810 for (unsigned i = 0; i < NumElems; ++i) { 1811 SDValue V = Node->getOperand(i); 1812 if (V.getOpcode() == ISD::UNDEF) 1813 continue; 1814 if (i > 0) 1815 isOnlyLowElement = false; 1816 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1817 isConstant = false; 1818 1819 if (!Value1.getNode()) { 1820 Value1 = V; 1821 } else if (!Value2.getNode()) { 1822 if (V != Value1) 1823 Value2 = V; 1824 } else if (V != Value1 && V != Value2) { 1825 MoreThanTwoValues = true; 1826 } 1827 } 1828 1829 if (!Value1.getNode()) 1830 return DAG.getUNDEF(VT); 1831 1832 if (isOnlyLowElement) 1833 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1834 1835 // If all elements are constants, create a load from the constant pool. 1836 if (isConstant) { 1837 std::vector<Constant*> CV; 1838 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1839 if (ConstantFPSDNode *V = 1840 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1841 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1842 } else if (ConstantSDNode *V = 1843 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1844 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1845 } else { 1846 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1847 const Type *OpNTy = OpVT.getTypeForMVT(*DAG.getContext()); 1848 CV.push_back(Context->getUndef(OpNTy)); 1849 } 1850 } 1851 Constant *CP = ConstantVector::get(CV); 1852 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1853 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1854 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1855 PseudoSourceValue::getConstantPool(), 0, 1856 false, Alignment); 1857 } 1858 1859 if (!MoreThanTwoValues) { 1860 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1861 for (unsigned i = 0; i < NumElems; ++i) { 1862 SDValue V = Node->getOperand(i); 1863 if (V.getOpcode() == ISD::UNDEF) 1864 continue; 1865 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1866 } 1867 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1868 // Get the splatted value into the low element of a vector register. 1869 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1870 SDValue Vec2; 1871 if (Value2.getNode()) 1872 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1873 else 1874 Vec2 = DAG.getUNDEF(VT); 1875 1876 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1877 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1878 } 1879 } 1880 1881 // Otherwise, we can't handle this case efficiently. 1882 return ExpandVectorBuildThroughStack(Node); 1883} 1884 1885// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1886// does not fit into a register, return the lo part and set the hi part to the 1887// by-reg argument. If it does fit into a single register, return the result 1888// and leave the Hi part unset. 1889SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1890 bool isSigned) { 1891 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1892 // The input chain to this libcall is the entry node of the function. 1893 // Legalizing the call will automatically add the previous call to the 1894 // dependence. 1895 SDValue InChain = DAG.getEntryNode(); 1896 1897 TargetLowering::ArgListTy Args; 1898 TargetLowering::ArgListEntry Entry; 1899 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1900 MVT ArgVT = Node->getOperand(i).getValueType(); 1901 const Type *ArgTy = ArgVT.getTypeForMVT(*DAG.getContext()); 1902 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1903 Entry.isSExt = isSigned; 1904 Entry.isZExt = !isSigned; 1905 Args.push_back(Entry); 1906 } 1907 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1908 TLI.getPointerTy()); 1909 1910 // Splice the libcall in wherever FindInputOutputChains tells us to. 1911 const Type *RetTy = Node->getValueType(0).getTypeForMVT(*DAG.getContext()); 1912 std::pair<SDValue, SDValue> CallInfo = 1913 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1914 0, CallingConv::C, false, Callee, Args, DAG, 1915 Node->getDebugLoc()); 1916 1917 // Legalize the call sequence, starting with the chain. This will advance 1918 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1919 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1920 LegalizeOp(CallInfo.second); 1921 return CallInfo.first; 1922} 1923 1924SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 1925 RTLIB::Libcall Call_F32, 1926 RTLIB::Libcall Call_F64, 1927 RTLIB::Libcall Call_F80, 1928 RTLIB::Libcall Call_PPCF128) { 1929 RTLIB::Libcall LC; 1930 switch (Node->getValueType(0).getSimpleVT()) { 1931 default: llvm_unreachable("Unexpected request for libcall!"); 1932 case MVT::f32: LC = Call_F32; break; 1933 case MVT::f64: LC = Call_F64; break; 1934 case MVT::f80: LC = Call_F80; break; 1935 case MVT::ppcf128: LC = Call_PPCF128; break; 1936 } 1937 return ExpandLibCall(LC, Node, false); 1938} 1939 1940SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 1941 RTLIB::Libcall Call_I16, 1942 RTLIB::Libcall Call_I32, 1943 RTLIB::Libcall Call_I64, 1944 RTLIB::Libcall Call_I128) { 1945 RTLIB::Libcall LC; 1946 switch (Node->getValueType(0).getSimpleVT()) { 1947 default: llvm_unreachable("Unexpected request for libcall!"); 1948 case MVT::i16: LC = Call_I16; break; 1949 case MVT::i32: LC = Call_I32; break; 1950 case MVT::i64: LC = Call_I64; break; 1951 case MVT::i128: LC = Call_I128; break; 1952 } 1953 return ExpandLibCall(LC, Node, isSigned); 1954} 1955 1956/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 1957/// INT_TO_FP operation of the specified operand when the target requests that 1958/// we expand it. At this point, we know that the result and operand types are 1959/// legal for the target. 1960SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 1961 SDValue Op0, 1962 MVT DestVT, 1963 DebugLoc dl) { 1964 if (Op0.getValueType() == MVT::i32) { 1965 // simple 32-bit [signed|unsigned] integer to float/double expansion 1966 1967 // Get the stack frame index of a 8 byte buffer. 1968 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 1969 1970 // word offset constant for Hi/Lo address computation 1971 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 1972 // set up Hi and Lo (into buffer) address based on endian 1973 SDValue Hi = StackSlot; 1974 SDValue Lo = DAG.getNode(ISD::ADD, dl, 1975 TLI.getPointerTy(), StackSlot, WordOff); 1976 if (TLI.isLittleEndian()) 1977 std::swap(Hi, Lo); 1978 1979 // if signed map to unsigned space 1980 SDValue Op0Mapped; 1981 if (isSigned) { 1982 // constant used to invert sign bit (signed to unsigned mapping) 1983 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 1984 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 1985 } else { 1986 Op0Mapped = Op0; 1987 } 1988 // store the lo of the constructed double - based on integer input 1989 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 1990 Op0Mapped, Lo, NULL, 0); 1991 // initial hi portion of constructed double 1992 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 1993 // store the hi of the constructed double - biased exponent 1994 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0); 1995 // load the constructed double 1996 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0); 1997 // FP constant to bias correct the final result 1998 SDValue Bias = DAG.getConstantFP(isSigned ? 1999 BitsToDouble(0x4330000080000000ULL) : 2000 BitsToDouble(0x4330000000000000ULL), 2001 MVT::f64); 2002 // subtract the bias 2003 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2004 // final result 2005 SDValue Result; 2006 // handle final rounding 2007 if (DestVT == MVT::f64) { 2008 // do nothing 2009 Result = Sub; 2010 } else if (DestVT.bitsLT(MVT::f64)) { 2011 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2012 DAG.getIntPtrConstant(0)); 2013 } else if (DestVT.bitsGT(MVT::f64)) { 2014 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2015 } 2016 return Result; 2017 } 2018 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2019 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2020 2021 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2022 Op0, DAG.getConstant(0, Op0.getValueType()), 2023 ISD::SETLT); 2024 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2025 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2026 SignSet, Four, Zero); 2027 2028 // If the sign bit of the integer is set, the large number will be treated 2029 // as a negative number. To counteract this, the dynamic code adds an 2030 // offset depending on the data type. 2031 uint64_t FF; 2032 switch (Op0.getValueType().getSimpleVT()) { 2033 default: llvm_unreachable("Unsupported integer type!"); 2034 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2035 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2036 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2037 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2038 } 2039 if (TLI.isLittleEndian()) FF <<= 32; 2040 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 2041 2042 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2043 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2044 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2045 Alignment = std::min(Alignment, 4u); 2046 SDValue FudgeInReg; 2047 if (DestVT == MVT::f32) 2048 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2049 PseudoSourceValue::getConstantPool(), 0, 2050 false, Alignment); 2051 else { 2052 FudgeInReg = 2053 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2054 DAG.getEntryNode(), CPIdx, 2055 PseudoSourceValue::getConstantPool(), 0, 2056 MVT::f32, false, Alignment)); 2057 } 2058 2059 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2060} 2061 2062/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2063/// *INT_TO_FP operation of the specified operand when the target requests that 2064/// we promote it. At this point, we know that the result and operand types are 2065/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2066/// operation that takes a larger input. 2067SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2068 MVT DestVT, 2069 bool isSigned, 2070 DebugLoc dl) { 2071 // First step, figure out the appropriate *INT_TO_FP operation to use. 2072 MVT NewInTy = LegalOp.getValueType(); 2073 2074 unsigned OpToUse = 0; 2075 2076 // Scan for the appropriate larger type to use. 2077 while (1) { 2078 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 2079 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2080 2081 // If the target supports SINT_TO_FP of this type, use it. 2082 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2083 OpToUse = ISD::SINT_TO_FP; 2084 break; 2085 } 2086 if (isSigned) continue; 2087 2088 // If the target supports UINT_TO_FP of this type, use it. 2089 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2090 OpToUse = ISD::UINT_TO_FP; 2091 break; 2092 } 2093 2094 // Otherwise, try a larger type. 2095 } 2096 2097 // Okay, we found the operation and type to use. Zero extend our input to the 2098 // desired type then run the operation on it. 2099 return DAG.getNode(OpToUse, dl, DestVT, 2100 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2101 dl, NewInTy, LegalOp)); 2102} 2103 2104/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2105/// FP_TO_*INT operation of the specified operand when the target requests that 2106/// we promote it. At this point, we know that the result and operand types are 2107/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2108/// operation that returns a larger result. 2109SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2110 MVT DestVT, 2111 bool isSigned, 2112 DebugLoc dl) { 2113 // First step, figure out the appropriate FP_TO*INT operation to use. 2114 MVT NewOutTy = DestVT; 2115 2116 unsigned OpToUse = 0; 2117 2118 // Scan for the appropriate larger type to use. 2119 while (1) { 2120 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 2121 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2122 2123 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2124 OpToUse = ISD::FP_TO_SINT; 2125 break; 2126 } 2127 2128 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2129 OpToUse = ISD::FP_TO_UINT; 2130 break; 2131 } 2132 2133 // Otherwise, try a larger type. 2134 } 2135 2136 2137 // Okay, we found the operation and type to use. 2138 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2139 2140 // Truncate the result of the extended FP_TO_*INT operation to the desired 2141 // size. 2142 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2143} 2144 2145/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2146/// 2147SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2148 MVT VT = Op.getValueType(); 2149 MVT SHVT = TLI.getShiftAmountTy(); 2150 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2151 switch (VT.getSimpleVT()) { 2152 default: llvm_unreachable("Unhandled Expand type in BSWAP!"); 2153 case MVT::i16: 2154 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2155 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2156 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2157 case MVT::i32: 2158 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2159 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2160 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2161 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2162 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2163 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2164 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2165 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2166 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2167 case MVT::i64: 2168 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2169 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2170 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2171 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2172 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2173 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2174 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2175 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2176 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2177 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2178 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2179 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2180 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2181 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2182 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2183 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2184 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2185 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2186 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2187 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2188 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2189 } 2190} 2191 2192/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2193/// 2194SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2195 DebugLoc dl) { 2196 switch (Opc) { 2197 default: llvm_unreachable("Cannot expand this yet!"); 2198 case ISD::CTPOP: { 2199 static const uint64_t mask[6] = { 2200 0x5555555555555555ULL, 0x3333333333333333ULL, 2201 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2202 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2203 }; 2204 MVT VT = Op.getValueType(); 2205 MVT ShVT = TLI.getShiftAmountTy(); 2206 unsigned len = VT.getSizeInBits(); 2207 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2208 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2209 unsigned EltSize = VT.isVector() ? 2210 VT.getVectorElementType().getSizeInBits() : len; 2211 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2212 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2213 Op = DAG.getNode(ISD::ADD, dl, VT, 2214 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2215 DAG.getNode(ISD::AND, dl, VT, 2216 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2217 Tmp2)); 2218 } 2219 return Op; 2220 } 2221 case ISD::CTLZ: { 2222 // for now, we do this: 2223 // x = x | (x >> 1); 2224 // x = x | (x >> 2); 2225 // ... 2226 // x = x | (x >>16); 2227 // x = x | (x >>32); // for 64-bit input 2228 // return popcount(~x); 2229 // 2230 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2231 MVT VT = Op.getValueType(); 2232 MVT ShVT = TLI.getShiftAmountTy(); 2233 unsigned len = VT.getSizeInBits(); 2234 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2235 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2236 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2237 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2238 } 2239 Op = DAG.getNOT(dl, Op, VT); 2240 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2241 } 2242 case ISD::CTTZ: { 2243 // for now, we use: { return popcount(~x & (x - 1)); } 2244 // unless the target has ctlz but not ctpop, in which case we use: 2245 // { return 32 - nlz(~x & (x-1)); } 2246 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2247 MVT VT = Op.getValueType(); 2248 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2249 DAG.getNOT(dl, Op, VT), 2250 DAG.getNode(ISD::SUB, dl, VT, Op, 2251 DAG.getConstant(1, VT))); 2252 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2253 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2254 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2255 return DAG.getNode(ISD::SUB, dl, VT, 2256 DAG.getConstant(VT.getSizeInBits(), VT), 2257 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2258 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2259 } 2260 } 2261} 2262 2263void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2264 SmallVectorImpl<SDValue> &Results) { 2265 DebugLoc dl = Node->getDebugLoc(); 2266 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2267 switch (Node->getOpcode()) { 2268 case ISD::CTPOP: 2269 case ISD::CTLZ: 2270 case ISD::CTTZ: 2271 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2272 Results.push_back(Tmp1); 2273 break; 2274 case ISD::BSWAP: 2275 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2276 break; 2277 case ISD::FRAMEADDR: 2278 case ISD::RETURNADDR: 2279 case ISD::FRAME_TO_ARGS_OFFSET: 2280 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2281 break; 2282 case ISD::FLT_ROUNDS_: 2283 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2284 break; 2285 case ISD::EH_RETURN: 2286 case ISD::DECLARE: 2287 case ISD::DBG_LABEL: 2288 case ISD::EH_LABEL: 2289 case ISD::PREFETCH: 2290 case ISD::MEMBARRIER: 2291 case ISD::VAEND: 2292 Results.push_back(Node->getOperand(0)); 2293 break; 2294 case ISD::DBG_STOPPOINT: 2295 Results.push_back(ExpandDBG_STOPPOINT(Node)); 2296 break; 2297 case ISD::DYNAMIC_STACKALLOC: 2298 ExpandDYNAMIC_STACKALLOC(Node, Results); 2299 break; 2300 case ISD::MERGE_VALUES: 2301 for (unsigned i = 0; i < Node->getNumValues(); i++) 2302 Results.push_back(Node->getOperand(i)); 2303 break; 2304 case ISD::UNDEF: { 2305 MVT VT = Node->getValueType(0); 2306 if (VT.isInteger()) 2307 Results.push_back(DAG.getConstant(0, VT)); 2308 else if (VT.isFloatingPoint()) 2309 Results.push_back(DAG.getConstantFP(0, VT)); 2310 else 2311 llvm_unreachable("Unknown value type!"); 2312 break; 2313 } 2314 case ISD::TRAP: { 2315 // If this operation is not supported, lower it to 'abort()' call 2316 TargetLowering::ArgListTy Args; 2317 std::pair<SDValue, SDValue> CallResult = 2318 TLI.LowerCallTo(Node->getOperand(0), Type::VoidTy, 2319 false, false, false, false, 0, CallingConv::C, false, 2320 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2321 Args, DAG, dl); 2322 Results.push_back(CallResult.second); 2323 break; 2324 } 2325 case ISD::FP_ROUND: 2326 case ISD::BIT_CONVERT: 2327 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2328 Node->getValueType(0), dl); 2329 Results.push_back(Tmp1); 2330 break; 2331 case ISD::FP_EXTEND: 2332 Tmp1 = EmitStackConvert(Node->getOperand(0), 2333 Node->getOperand(0).getValueType(), 2334 Node->getValueType(0), dl); 2335 Results.push_back(Tmp1); 2336 break; 2337 case ISD::SIGN_EXTEND_INREG: { 2338 // NOTE: we could fall back on load/store here too for targets without 2339 // SAR. However, it is doubtful that any exist. 2340 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2341 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 2342 ExtraVT.getSizeInBits(); 2343 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2344 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2345 Node->getOperand(0), ShiftCst); 2346 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2347 Results.push_back(Tmp1); 2348 break; 2349 } 2350 case ISD::FP_ROUND_INREG: { 2351 // The only way we can lower this is to turn it into a TRUNCSTORE, 2352 // EXTLOAD pair, targetting a temporary location (a stack slot). 2353 2354 // NOTE: there is a choice here between constantly creating new stack 2355 // slots and always reusing the same one. We currently always create 2356 // new ones, as reuse may inhibit scheduling. 2357 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2358 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2359 Node->getValueType(0), dl); 2360 Results.push_back(Tmp1); 2361 break; 2362 } 2363 case ISD::SINT_TO_FP: 2364 case ISD::UINT_TO_FP: 2365 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2366 Node->getOperand(0), Node->getValueType(0), dl); 2367 Results.push_back(Tmp1); 2368 break; 2369 case ISD::FP_TO_UINT: { 2370 SDValue True, False; 2371 MVT VT = Node->getOperand(0).getValueType(); 2372 MVT NVT = Node->getValueType(0); 2373 const uint64_t zero[] = {0, 0}; 2374 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 2375 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2376 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2377 Tmp1 = DAG.getConstantFP(apf, VT); 2378 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2379 Node->getOperand(0), 2380 Tmp1, ISD::SETLT); 2381 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2382 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2383 DAG.getNode(ISD::FSUB, dl, VT, 2384 Node->getOperand(0), Tmp1)); 2385 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2386 DAG.getConstant(x, NVT)); 2387 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2388 Results.push_back(Tmp1); 2389 break; 2390 } 2391 case ISD::VAARG: { 2392 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2393 MVT VT = Node->getValueType(0); 2394 Tmp1 = Node->getOperand(0); 2395 Tmp2 = Node->getOperand(1); 2396 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0); 2397 // Increment the pointer, VAList, to the next vaarg 2398 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2399 DAG.getConstant(TLI.getTargetData()-> 2400 getTypeAllocSize(VT.getTypeForMVT( 2401 *DAG.getContext())), 2402 TLI.getPointerTy())); 2403 // Store the incremented VAList to the legalized pointer 2404 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0); 2405 // Load the actual argument out of the pointer VAList 2406 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0)); 2407 Results.push_back(Results[0].getValue(1)); 2408 break; 2409 } 2410 case ISD::VACOPY: { 2411 // This defaults to loading a pointer from the input and storing it to the 2412 // output, returning the chain. 2413 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2414 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2415 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2416 Node->getOperand(2), VS, 0); 2417 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0); 2418 Results.push_back(Tmp1); 2419 break; 2420 } 2421 case ISD::EXTRACT_VECTOR_ELT: 2422 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2423 // This must be an access of the only element. Return it. 2424 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 2425 Node->getOperand(0)); 2426 else 2427 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2428 Results.push_back(Tmp1); 2429 break; 2430 case ISD::EXTRACT_SUBVECTOR: 2431 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2432 break; 2433 case ISD::CONCAT_VECTORS: { 2434 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2435 break; 2436 } 2437 case ISD::SCALAR_TO_VECTOR: 2438 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2439 break; 2440 case ISD::INSERT_VECTOR_ELT: 2441 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2442 Node->getOperand(1), 2443 Node->getOperand(2), dl)); 2444 break; 2445 case ISD::VECTOR_SHUFFLE: { 2446 SmallVector<int, 8> Mask; 2447 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2448 2449 MVT VT = Node->getValueType(0); 2450 MVT EltVT = VT.getVectorElementType(); 2451 unsigned NumElems = VT.getVectorNumElements(); 2452 SmallVector<SDValue, 8> Ops; 2453 for (unsigned i = 0; i != NumElems; ++i) { 2454 if (Mask[i] < 0) { 2455 Ops.push_back(DAG.getUNDEF(EltVT)); 2456 continue; 2457 } 2458 unsigned Idx = Mask[i]; 2459 if (Idx < NumElems) 2460 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2461 Node->getOperand(0), 2462 DAG.getIntPtrConstant(Idx))); 2463 else 2464 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2465 Node->getOperand(1), 2466 DAG.getIntPtrConstant(Idx - NumElems))); 2467 } 2468 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2469 Results.push_back(Tmp1); 2470 break; 2471 } 2472 case ISD::EXTRACT_ELEMENT: { 2473 MVT OpTy = Node->getOperand(0).getValueType(); 2474 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2475 // 1 -> Hi 2476 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2477 DAG.getConstant(OpTy.getSizeInBits()/2, 2478 TLI.getShiftAmountTy())); 2479 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2480 } else { 2481 // 0 -> Lo 2482 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2483 Node->getOperand(0)); 2484 } 2485 Results.push_back(Tmp1); 2486 break; 2487 } 2488 case ISD::STACKSAVE: 2489 // Expand to CopyFromReg if the target set 2490 // StackPointerRegisterToSaveRestore. 2491 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2492 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2493 Node->getValueType(0))); 2494 Results.push_back(Results[0].getValue(1)); 2495 } else { 2496 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2497 Results.push_back(Node->getOperand(0)); 2498 } 2499 break; 2500 case ISD::STACKRESTORE: 2501 // Expand to CopyToReg if the target set 2502 // StackPointerRegisterToSaveRestore. 2503 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2504 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2505 Node->getOperand(1))); 2506 } else { 2507 Results.push_back(Node->getOperand(0)); 2508 } 2509 break; 2510 case ISD::FCOPYSIGN: 2511 Results.push_back(ExpandFCOPYSIGN(Node)); 2512 break; 2513 case ISD::FNEG: 2514 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2515 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2516 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2517 Node->getOperand(0)); 2518 Results.push_back(Tmp1); 2519 break; 2520 case ISD::FABS: { 2521 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2522 MVT VT = Node->getValueType(0); 2523 Tmp1 = Node->getOperand(0); 2524 Tmp2 = DAG.getConstantFP(0.0, VT); 2525 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2526 Tmp1, Tmp2, ISD::SETUGT); 2527 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2528 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2529 Results.push_back(Tmp1); 2530 break; 2531 } 2532 case ISD::FSQRT: 2533 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2534 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2535 break; 2536 case ISD::FSIN: 2537 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2538 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2539 break; 2540 case ISD::FCOS: 2541 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2542 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2543 break; 2544 case ISD::FLOG: 2545 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2546 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2547 break; 2548 case ISD::FLOG2: 2549 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2550 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2551 break; 2552 case ISD::FLOG10: 2553 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2554 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2555 break; 2556 case ISD::FEXP: 2557 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2558 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2559 break; 2560 case ISD::FEXP2: 2561 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2562 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2563 break; 2564 case ISD::FTRUNC: 2565 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2566 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2567 break; 2568 case ISD::FFLOOR: 2569 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2570 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2571 break; 2572 case ISD::FCEIL: 2573 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2574 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2575 break; 2576 case ISD::FRINT: 2577 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2578 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2579 break; 2580 case ISD::FNEARBYINT: 2581 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2582 RTLIB::NEARBYINT_F64, 2583 RTLIB::NEARBYINT_F80, 2584 RTLIB::NEARBYINT_PPCF128)); 2585 break; 2586 case ISD::FPOWI: 2587 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2588 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2589 break; 2590 case ISD::FPOW: 2591 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 2592 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 2593 break; 2594 case ISD::FDIV: 2595 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 2596 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 2597 break; 2598 case ISD::FREM: 2599 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 2600 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 2601 break; 2602 case ISD::ConstantFP: { 2603 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 2604 // Check to see if this FP immediate is already legal. 2605 bool isLegal = false; 2606 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 2607 E = TLI.legal_fpimm_end(); I != E; ++I) { 2608 if (CFP->isExactlyValue(*I)) { 2609 isLegal = true; 2610 break; 2611 } 2612 } 2613 // If this is a legal constant, turn it into a TargetConstantFP node. 2614 if (isLegal) 2615 Results.push_back(SDValue(Node, 0)); 2616 else 2617 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 2618 break; 2619 } 2620 case ISD::EHSELECTION: { 2621 unsigned Reg = TLI.getExceptionSelectorRegister(); 2622 assert(Reg && "Can't expand to unknown register!"); 2623 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 2624 Node->getValueType(0))); 2625 Results.push_back(Results[0].getValue(1)); 2626 break; 2627 } 2628 case ISD::EXCEPTIONADDR: { 2629 unsigned Reg = TLI.getExceptionAddressRegister(); 2630 assert(Reg && "Can't expand to unknown register!"); 2631 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 2632 Node->getValueType(0))); 2633 Results.push_back(Results[0].getValue(1)); 2634 break; 2635 } 2636 case ISD::SUB: { 2637 MVT VT = Node->getValueType(0); 2638 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 2639 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 2640 "Don't know how to expand this subtraction!"); 2641 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 2642 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 2643 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 2644 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 2645 break; 2646 } 2647 case ISD::UREM: 2648 case ISD::SREM: { 2649 MVT VT = Node->getValueType(0); 2650 SDVTList VTs = DAG.getVTList(VT, VT); 2651 bool isSigned = Node->getOpcode() == ISD::SREM; 2652 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 2653 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2654 Tmp2 = Node->getOperand(0); 2655 Tmp3 = Node->getOperand(1); 2656 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 2657 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 2658 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 2659 // X % Y -> X-X/Y*Y 2660 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 2661 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 2662 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 2663 } else if (isSigned) { 2664 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SREM_I16, RTLIB::SREM_I32, 2665 RTLIB::SREM_I64, RTLIB::SREM_I128); 2666 } else { 2667 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UREM_I16, RTLIB::UREM_I32, 2668 RTLIB::UREM_I64, RTLIB::UREM_I128); 2669 } 2670 Results.push_back(Tmp1); 2671 break; 2672 } 2673 case ISD::UDIV: 2674 case ISD::SDIV: { 2675 bool isSigned = Node->getOpcode() == ISD::SDIV; 2676 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2677 MVT VT = Node->getValueType(0); 2678 SDVTList VTs = DAG.getVTList(VT, VT); 2679 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 2680 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 2681 Node->getOperand(1)); 2682 else if (isSigned) 2683 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SDIV_I16, RTLIB::SDIV_I32, 2684 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 2685 else 2686 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UDIV_I16, RTLIB::UDIV_I32, 2687 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 2688 Results.push_back(Tmp1); 2689 break; 2690 } 2691 case ISD::MULHU: 2692 case ISD::MULHS: { 2693 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 2694 ISD::SMUL_LOHI; 2695 MVT VT = Node->getValueType(0); 2696 SDVTList VTs = DAG.getVTList(VT, VT); 2697 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 2698 "If this wasn't legal, it shouldn't have been created!"); 2699 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 2700 Node->getOperand(1)); 2701 Results.push_back(Tmp1.getValue(1)); 2702 break; 2703 } 2704 case ISD::MUL: { 2705 MVT VT = Node->getValueType(0); 2706 SDVTList VTs = DAG.getVTList(VT, VT); 2707 // See if multiply or divide can be lowered using two-result operations. 2708 // We just need the low half of the multiply; try both the signed 2709 // and unsigned forms. If the target supports both SMUL_LOHI and 2710 // UMUL_LOHI, form a preference by checking which forms of plain 2711 // MULH it supports. 2712 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 2713 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 2714 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 2715 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 2716 unsigned OpToUse = 0; 2717 if (HasSMUL_LOHI && !HasMULHS) { 2718 OpToUse = ISD::SMUL_LOHI; 2719 } else if (HasUMUL_LOHI && !HasMULHU) { 2720 OpToUse = ISD::UMUL_LOHI; 2721 } else if (HasSMUL_LOHI) { 2722 OpToUse = ISD::SMUL_LOHI; 2723 } else if (HasUMUL_LOHI) { 2724 OpToUse = ISD::UMUL_LOHI; 2725 } 2726 if (OpToUse) { 2727 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 2728 Node->getOperand(1))); 2729 break; 2730 } 2731 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::MUL_I16, RTLIB::MUL_I32, 2732 RTLIB::MUL_I64, RTLIB::MUL_I128); 2733 Results.push_back(Tmp1); 2734 break; 2735 } 2736 case ISD::SADDO: 2737 case ISD::SSUBO: { 2738 SDValue LHS = Node->getOperand(0); 2739 SDValue RHS = Node->getOperand(1); 2740 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 2741 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2742 LHS, RHS); 2743 Results.push_back(Sum); 2744 MVT OType = Node->getValueType(1); 2745 2746 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 2747 2748 // LHSSign -> LHS >= 0 2749 // RHSSign -> RHS >= 0 2750 // SumSign -> Sum >= 0 2751 // 2752 // Add: 2753 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 2754 // Sub: 2755 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 2756 // 2757 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 2758 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 2759 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 2760 Node->getOpcode() == ISD::SADDO ? 2761 ISD::SETEQ : ISD::SETNE); 2762 2763 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 2764 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 2765 2766 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 2767 Results.push_back(Cmp); 2768 break; 2769 } 2770 case ISD::UADDO: 2771 case ISD::USUBO: { 2772 SDValue LHS = Node->getOperand(0); 2773 SDValue RHS = Node->getOperand(1); 2774 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 2775 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2776 LHS, RHS); 2777 Results.push_back(Sum); 2778 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 2779 Node->getOpcode () == ISD::UADDO ? 2780 ISD::SETULT : ISD::SETUGT)); 2781 break; 2782 } 2783 case ISD::UMULO: 2784 case ISD::SMULO: { 2785 MVT VT = Node->getValueType(0); 2786 SDValue LHS = Node->getOperand(0); 2787 SDValue RHS = Node->getOperand(1); 2788 SDValue BottomHalf; 2789 SDValue TopHalf; 2790 static unsigned Ops[2][3] = 2791 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 2792 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 2793 bool isSigned = Node->getOpcode() == ISD::SMULO; 2794 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 2795 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 2796 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 2797 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 2798 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 2799 RHS); 2800 TopHalf = BottomHalf.getValue(1); 2801 } else if (TLI.isTypeLegal(MVT::getIntegerVT(VT.getSizeInBits() * 2))) { 2802 MVT WideVT = MVT::getIntegerVT(VT.getSizeInBits() * 2); 2803 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 2804 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 2805 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 2806 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2807 DAG.getIntPtrConstant(0)); 2808 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2809 DAG.getIntPtrConstant(1)); 2810 } else { 2811 // FIXME: We should be able to fall back to a libcall with an illegal 2812 // type in some cases cases. 2813 // Also, we can fall back to a division in some cases, but that's a big 2814 // performance hit in the general case. 2815 llvm_unreachable("Don't know how to expand this operation yet!"); 2816 } 2817 if (isSigned) { 2818 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); 2819 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 2820 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 2821 ISD::SETNE); 2822 } else { 2823 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 2824 DAG.getConstant(0, VT), ISD::SETNE); 2825 } 2826 Results.push_back(BottomHalf); 2827 Results.push_back(TopHalf); 2828 break; 2829 } 2830 case ISD::BUILD_PAIR: { 2831 MVT PairTy = Node->getValueType(0); 2832 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 2833 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 2834 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 2835 DAG.getConstant(PairTy.getSizeInBits()/2, 2836 TLI.getShiftAmountTy())); 2837 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 2838 break; 2839 } 2840 case ISD::SELECT: 2841 Tmp1 = Node->getOperand(0); 2842 Tmp2 = Node->getOperand(1); 2843 Tmp3 = Node->getOperand(2); 2844 if (Tmp1.getOpcode() == ISD::SETCC) { 2845 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 2846 Tmp2, Tmp3, 2847 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2848 } else { 2849 Tmp1 = DAG.getSelectCC(dl, Tmp1, 2850 DAG.getConstant(0, Tmp1.getValueType()), 2851 Tmp2, Tmp3, ISD::SETNE); 2852 } 2853 Results.push_back(Tmp1); 2854 break; 2855 case ISD::BR_JT: { 2856 SDValue Chain = Node->getOperand(0); 2857 SDValue Table = Node->getOperand(1); 2858 SDValue Index = Node->getOperand(2); 2859 2860 MVT PTy = TLI.getPointerTy(); 2861 MachineFunction &MF = DAG.getMachineFunction(); 2862 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 2863 Index= DAG.getNode(ISD::MUL, dl, PTy, 2864 Index, DAG.getConstant(EntrySize, PTy)); 2865 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2866 2867 MVT MemVT = MVT::getIntegerVT(EntrySize * 8); 2868 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 2869 PseudoSourceValue::getJumpTable(), 0, MemVT); 2870 Addr = LD; 2871 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2872 // For PIC, the sequence is: 2873 // BRIND(load(Jumptable + index) + RelocBase) 2874 // RelocBase can be JumpTable, GOT or some sort of global base. 2875 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 2876 TLI.getPICJumpTableRelocBase(Table, DAG)); 2877 } 2878 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 2879 Results.push_back(Tmp1); 2880 break; 2881 } 2882 case ISD::BRCOND: 2883 // Expand brcond's setcc into its constituent parts and create a BR_CC 2884 // Node. 2885 Tmp1 = Node->getOperand(0); 2886 Tmp2 = Node->getOperand(1); 2887 if (Tmp2.getOpcode() == ISD::SETCC) { 2888 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 2889 Tmp1, Tmp2.getOperand(2), 2890 Tmp2.getOperand(0), Tmp2.getOperand(1), 2891 Node->getOperand(2)); 2892 } else { 2893 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 2894 DAG.getCondCode(ISD::SETNE), Tmp2, 2895 DAG.getConstant(0, Tmp2.getValueType()), 2896 Node->getOperand(2)); 2897 } 2898 Results.push_back(Tmp1); 2899 break; 2900 case ISD::SETCC: { 2901 Tmp1 = Node->getOperand(0); 2902 Tmp2 = Node->getOperand(1); 2903 Tmp3 = Node->getOperand(2); 2904 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 2905 2906 // If we expanded the SETCC into an AND/OR, return the new node 2907 if (Tmp2.getNode() == 0) { 2908 Results.push_back(Tmp1); 2909 break; 2910 } 2911 2912 // Otherwise, SETCC for the given comparison type must be completely 2913 // illegal; expand it into a SELECT_CC. 2914 MVT VT = Node->getValueType(0); 2915 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 2916 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 2917 Results.push_back(Tmp1); 2918 break; 2919 } 2920 case ISD::SELECT_CC: { 2921 Tmp1 = Node->getOperand(0); // LHS 2922 Tmp2 = Node->getOperand(1); // RHS 2923 Tmp3 = Node->getOperand(2); // True 2924 Tmp4 = Node->getOperand(3); // False 2925 SDValue CC = Node->getOperand(4); 2926 2927 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 2928 Tmp1, Tmp2, CC, dl); 2929 2930 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 2931 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2932 CC = DAG.getCondCode(ISD::SETNE); 2933 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 2934 Tmp3, Tmp4, CC); 2935 Results.push_back(Tmp1); 2936 break; 2937 } 2938 case ISD::BR_CC: { 2939 Tmp1 = Node->getOperand(0); // Chain 2940 Tmp2 = Node->getOperand(2); // LHS 2941 Tmp3 = Node->getOperand(3); // RHS 2942 Tmp4 = Node->getOperand(1); // CC 2943 2944 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 2945 Tmp2, Tmp3, Tmp4, dl); 2946 LastCALLSEQ_END = DAG.getEntryNode(); 2947 2948 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 2949 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 2950 Tmp4 = DAG.getCondCode(ISD::SETNE); 2951 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 2952 Tmp3, Node->getOperand(4)); 2953 Results.push_back(Tmp1); 2954 break; 2955 } 2956 case ISD::GLOBAL_OFFSET_TABLE: 2957 case ISD::GlobalAddress: 2958 case ISD::GlobalTLSAddress: 2959 case ISD::ExternalSymbol: 2960 case ISD::ConstantPool: 2961 case ISD::JumpTable: 2962 case ISD::INTRINSIC_W_CHAIN: 2963 case ISD::INTRINSIC_WO_CHAIN: 2964 case ISD::INTRINSIC_VOID: 2965 // FIXME: Custom lowering for these operations shouldn't return null! 2966 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2967 Results.push_back(SDValue(Node, i)); 2968 break; 2969 } 2970} 2971void SelectionDAGLegalize::PromoteNode(SDNode *Node, 2972 SmallVectorImpl<SDValue> &Results) { 2973 MVT OVT = Node->getValueType(0); 2974 if (Node->getOpcode() == ISD::UINT_TO_FP || 2975 Node->getOpcode() == ISD::SINT_TO_FP || 2976 Node->getOpcode() == ISD::SETCC) { 2977 OVT = Node->getOperand(0).getValueType(); 2978 } 2979 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2980 DebugLoc dl = Node->getDebugLoc(); 2981 SDValue Tmp1, Tmp2, Tmp3; 2982 switch (Node->getOpcode()) { 2983 case ISD::CTTZ: 2984 case ISD::CTLZ: 2985 case ISD::CTPOP: 2986 // Zero extend the argument. 2987 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 2988 // Perform the larger operation. 2989 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 2990 if (Node->getOpcode() == ISD::CTTZ) { 2991 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2992 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 2993 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 2994 ISD::SETEQ); 2995 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 2996 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 2997 } else if (Node->getOpcode() == ISD::CTLZ) { 2998 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2999 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3000 DAG.getConstant(NVT.getSizeInBits() - 3001 OVT.getSizeInBits(), NVT)); 3002 } 3003 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3004 break; 3005 case ISD::BSWAP: { 3006 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3007 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); 3008 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3009 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3010 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3011 Results.push_back(Tmp1); 3012 break; 3013 } 3014 case ISD::FP_TO_UINT: 3015 case ISD::FP_TO_SINT: 3016 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3017 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3018 Results.push_back(Tmp1); 3019 break; 3020 case ISD::UINT_TO_FP: 3021 case ISD::SINT_TO_FP: 3022 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3023 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3024 Results.push_back(Tmp1); 3025 break; 3026 case ISD::AND: 3027 case ISD::OR: 3028 case ISD::XOR: { 3029 unsigned ExtOp, TruncOp; 3030 if (OVT.isVector()) { 3031 ExtOp = ISD::BIT_CONVERT; 3032 TruncOp = ISD::BIT_CONVERT; 3033 } else if (OVT.isInteger()) { 3034 ExtOp = ISD::ANY_EXTEND; 3035 TruncOp = ISD::TRUNCATE; 3036 } else { 3037 llvm_report_error("Cannot promote logic operation"); 3038 } 3039 // Promote each of the values to the new type. 3040 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3041 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3042 // Perform the larger operation, then convert back 3043 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3044 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3045 break; 3046 } 3047 case ISD::SELECT: { 3048 unsigned ExtOp, TruncOp; 3049 if (Node->getValueType(0).isVector()) { 3050 ExtOp = ISD::BIT_CONVERT; 3051 TruncOp = ISD::BIT_CONVERT; 3052 } else if (Node->getValueType(0).isInteger()) { 3053 ExtOp = ISD::ANY_EXTEND; 3054 TruncOp = ISD::TRUNCATE; 3055 } else { 3056 ExtOp = ISD::FP_EXTEND; 3057 TruncOp = ISD::FP_ROUND; 3058 } 3059 Tmp1 = Node->getOperand(0); 3060 // Promote each of the values to the new type. 3061 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3062 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3063 // Perform the larger operation, then round down. 3064 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3065 if (TruncOp != ISD::FP_ROUND) 3066 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3067 else 3068 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3069 DAG.getIntPtrConstant(0)); 3070 Results.push_back(Tmp1); 3071 break; 3072 } 3073 case ISD::VECTOR_SHUFFLE: { 3074 SmallVector<int, 8> Mask; 3075 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3076 3077 // Cast the two input vectors. 3078 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3079 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3080 3081 // Convert the shuffle mask to the right # elements. 3082 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3083 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); 3084 Results.push_back(Tmp1); 3085 break; 3086 } 3087 case ISD::SETCC: { 3088 unsigned ExtOp = ISD::FP_EXTEND; 3089 if (NVT.isInteger()) { 3090 ISD::CondCode CCCode = 3091 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3092 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3093 } 3094 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3095 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3096 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3097 Tmp1, Tmp2, Node->getOperand(2))); 3098 break; 3099 } 3100 } 3101} 3102 3103// SelectionDAG::Legalize - This is the entry point for the file. 3104// 3105void SelectionDAG::Legalize(bool TypesNeedLegalizing, 3106 CodeGenOpt::Level OptLevel) { 3107 /// run - This is the main entry point to this class. 3108 /// 3109 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3110} 3111 3112