LegalizeDAG.cpp revision 56966225d1eed9f9a6951d2167bfbbec9628c8d6
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetMachine.h" 21#include "llvm/Target/TargetOptions.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/Support/MathExtras.h" 25#include "llvm/Support/CommandLine.h" 26#include "llvm/Support/Compiler.h" 27#include "llvm/ADT/SmallVector.h" 28#include <map> 29using namespace llvm; 30 31#ifndef NDEBUG 32static cl::opt<bool> 33ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 34 cl::desc("Pop up a window to show dags before legalize")); 35#else 36static const bool ViewLegalizeDAGs = 0; 37#endif 38 39//===----------------------------------------------------------------------===// 40/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 41/// hacks on it until the target machine can handle it. This involves 42/// eliminating value sizes the machine cannot handle (promoting small sizes to 43/// large sizes or splitting up large values into small values) as well as 44/// eliminating operations the machine cannot handle. 45/// 46/// This code also does a small amount of optimization and recognition of idioms 47/// as part of its processing. For example, if a target does not support a 48/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 49/// will attempt merge setcc and brc instructions into brcc's. 50/// 51namespace { 52class VISIBILITY_HIDDEN SelectionDAGLegalize { 53 TargetLowering &TLI; 54 SelectionDAG &DAG; 55 56 // Libcall insertion helpers. 57 58 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 59 /// legalized. We use this to ensure that calls are properly serialized 60 /// against each other, including inserted libcalls. 61 SDOperand LastCALLSEQ_END; 62 63 /// IsLegalizingCall - This member is used *only* for purposes of providing 64 /// helpful assertions that a libcall isn't created while another call is 65 /// being legalized (which could lead to non-serialized call sequences). 66 bool IsLegalizingCall; 67 68 enum LegalizeAction { 69 Legal, // The target natively supports this operation. 70 Promote, // This operation should be executed in a larger type. 71 Expand // Try to expand this to other ops, otherwise use a libcall. 72 }; 73 74 /// ValueTypeActions - This is a bitvector that contains two bits for each 75 /// value type, where the two bits correspond to the LegalizeAction enum. 76 /// This can be queried with "getTypeAction(VT)". 77 TargetLowering::ValueTypeActionImpl ValueTypeActions; 78 79 /// LegalizedNodes - For nodes that are of legal width, and that have more 80 /// than one use, this map indicates what regularized operand to use. This 81 /// allows us to avoid legalizing the same thing more than once. 82 std::map<SDOperand, SDOperand> LegalizedNodes; 83 84 /// PromotedNodes - For nodes that are below legal width, and that have more 85 /// than one use, this map indicates what promoted value to use. This allows 86 /// us to avoid promoting the same thing more than once. 87 std::map<SDOperand, SDOperand> PromotedNodes; 88 89 /// ExpandedNodes - For nodes that need to be expanded this map indicates 90 /// which which operands are the expanded version of the input. This allows 91 /// us to avoid expanding the same node more than once. 92 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 93 94 /// SplitNodes - For vector nodes that need to be split, this map indicates 95 /// which which operands are the split version of the input. This allows us 96 /// to avoid splitting the same node more than once. 97 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 98 99 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to 100 /// concrete packed types, this contains the mapping of ones we have already 101 /// processed to the result. 102 std::map<SDOperand, SDOperand> PackedNodes; 103 104 void AddLegalizedOperand(SDOperand From, SDOperand To) { 105 LegalizedNodes.insert(std::make_pair(From, To)); 106 // If someone requests legalization of the new node, return itself. 107 if (From != To) 108 LegalizedNodes.insert(std::make_pair(To, To)); 109 } 110 void AddPromotedOperand(SDOperand From, SDOperand To) { 111 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 112 assert(isNew && "Got into the map somehow?"); 113 // If someone requests legalization of the new node, return itself. 114 LegalizedNodes.insert(std::make_pair(To, To)); 115 } 116 117public: 118 119 SelectionDAGLegalize(SelectionDAG &DAG); 120 121 /// getTypeAction - Return how we should legalize values of this type, either 122 /// it is already legal or we need to expand it into multiple registers of 123 /// smaller integer type, or we need to promote it to a larger type. 124 LegalizeAction getTypeAction(MVT::ValueType VT) const { 125 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 126 } 127 128 /// isTypeLegal - Return true if this type is legal on this target. 129 /// 130 bool isTypeLegal(MVT::ValueType VT) const { 131 return getTypeAction(VT) == Legal; 132 } 133 134 void LegalizeDAG(); 135 136private: 137 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 138 /// appropriate for its type. 139 void HandleOp(SDOperand Op); 140 141 /// LegalizeOp - We know that the specified value has a legal type. 142 /// Recursively ensure that the operands have legal types, then return the 143 /// result. 144 SDOperand LegalizeOp(SDOperand O); 145 146 /// PromoteOp - Given an operation that produces a value in an invalid type, 147 /// promote it to compute the value into a larger type. The produced value 148 /// will have the correct bits for the low portion of the register, but no 149 /// guarantee is made about the top bits: it may be zero, sign-extended, or 150 /// garbage. 151 SDOperand PromoteOp(SDOperand O); 152 153 /// ExpandOp - Expand the specified SDOperand into its two component pieces 154 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 155 /// the LegalizeNodes map is filled in for any results that are not expanded, 156 /// the ExpandedNodes map is filled in for any results that are expanded, and 157 /// the Lo/Hi values are returned. This applies to integer types and Vector 158 /// types. 159 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 160 161 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 162 /// two smaller values of MVT::Vector type. 163 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 164 165 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 166 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When 167 /// this is called, we know that PackedVT is the right type for the result and 168 /// we know that this type is legal for the target. 169 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT); 170 171 /// isShuffleLegal - Return true if a vector shuffle is legal with the 172 /// specified mask and type. Targets can specify exactly which masks they 173 /// support and the code generator is tasked with not creating illegal masks. 174 /// 175 /// Note that this will also return true for shuffles that are promoted to a 176 /// different type. 177 /// 178 /// If this is a legal shuffle, this method returns the (possibly promoted) 179 /// build_vector Mask. If it's not a legal shuffle, it returns null. 180 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 181 182 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 183 std::set<SDNode*> &NodesLeadingTo); 184 185 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 186 187 SDOperand CreateStackTemporary(MVT::ValueType VT); 188 189 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 190 SDOperand &Hi); 191 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 192 SDOperand Source); 193 194 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 195 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 196 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 197 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 198 SDOperand LegalOp, 199 MVT::ValueType DestVT); 200 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 201 bool isSigned); 202 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 203 bool isSigned); 204 205 SDOperand ExpandBSWAP(SDOperand Op); 206 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 207 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 208 SDOperand &Lo, SDOperand &Hi); 209 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 210 SDOperand &Lo, SDOperand &Hi); 211 212 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op); 213 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 214 215 SDOperand getIntPtrConstant(uint64_t Val) { 216 return DAG.getConstant(Val, TLI.getPointerTy()); 217 } 218}; 219} 220 221/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 222/// specified mask and type. Targets can specify exactly which masks they 223/// support and the code generator is tasked with not creating illegal masks. 224/// 225/// Note that this will also return true for shuffles that are promoted to a 226/// different type. 227SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 228 SDOperand Mask) const { 229 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 230 default: return 0; 231 case TargetLowering::Legal: 232 case TargetLowering::Custom: 233 break; 234 case TargetLowering::Promote: { 235 // If this is promoted to a different type, convert the shuffle mask and 236 // ask if it is legal in the promoted type! 237 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 238 239 // If we changed # elements, change the shuffle mask. 240 unsigned NumEltsGrowth = 241 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 242 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 243 if (NumEltsGrowth > 1) { 244 // Renumber the elements. 245 SmallVector<SDOperand, 8> Ops; 246 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 247 SDOperand InOp = Mask.getOperand(i); 248 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 249 if (InOp.getOpcode() == ISD::UNDEF) 250 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 251 else { 252 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 253 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 254 } 255 } 256 } 257 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 258 } 259 VT = NVT; 260 break; 261 } 262 } 263 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 264} 265 266/// getScalarizedOpcode - Return the scalar opcode that corresponds to the 267/// specified vector opcode. 268static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 269 switch (VecOp) { 270 default: assert(0 && "Don't know how to scalarize this opcode!"); 271 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 272 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 273 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 274 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV; 275 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV; 276 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0; 277 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0; 278 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0; 279 } 280} 281 282SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 283 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 284 ValueTypeActions(TLI.getValueTypeActions()) { 285 assert(MVT::LAST_VALUETYPE <= 32 && 286 "Too many value types for ValueTypeActions to hold!"); 287} 288 289/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 290/// not been visited yet and if all of its operands have already been visited. 291static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 292 std::map<SDNode*, unsigned> &Visited) { 293 if (++Visited[N] != N->getNumOperands()) 294 return; // Haven't visited all operands yet 295 296 Order.push_back(N); 297 298 if (N->hasOneUse()) { // Tail recurse in common case. 299 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 300 return; 301 } 302 303 // Now that we have N in, add anything that uses it if all of their operands 304 // are now done. 305 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 306 ComputeTopDownOrdering(*UI, Order, Visited); 307} 308 309 310void SelectionDAGLegalize::LegalizeDAG() { 311 LastCALLSEQ_END = DAG.getEntryNode(); 312 IsLegalizingCall = false; 313 314 // The legalize process is inherently a bottom-up recursive process (users 315 // legalize their uses before themselves). Given infinite stack space, we 316 // could just start legalizing on the root and traverse the whole graph. In 317 // practice however, this causes us to run out of stack space on large basic 318 // blocks. To avoid this problem, compute an ordering of the nodes where each 319 // node is only legalized after all of its operands are legalized. 320 std::map<SDNode*, unsigned> Visited; 321 std::vector<SDNode*> Order; 322 323 // Compute ordering from all of the leaves in the graphs, those (like the 324 // entry node) that have no operands. 325 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 326 E = DAG.allnodes_end(); I != E; ++I) { 327 if (I->getNumOperands() == 0) { 328 Visited[I] = 0 - 1U; 329 ComputeTopDownOrdering(I, Order, Visited); 330 } 331 } 332 333 assert(Order.size() == Visited.size() && 334 Order.size() == 335 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 336 "Error: DAG is cyclic!"); 337 Visited.clear(); 338 339 for (unsigned i = 0, e = Order.size(); i != e; ++i) 340 HandleOp(SDOperand(Order[i], 0)); 341 342 // Finally, it's possible the root changed. Get the new root. 343 SDOperand OldRoot = DAG.getRoot(); 344 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 345 DAG.setRoot(LegalizedNodes[OldRoot]); 346 347 ExpandedNodes.clear(); 348 LegalizedNodes.clear(); 349 PromotedNodes.clear(); 350 SplitNodes.clear(); 351 PackedNodes.clear(); 352 353 // Remove dead nodes now. 354 DAG.RemoveDeadNodes(); 355} 356 357 358/// FindCallEndFromCallStart - Given a chained node that is part of a call 359/// sequence, find the CALLSEQ_END node that terminates the call sequence. 360static SDNode *FindCallEndFromCallStart(SDNode *Node) { 361 if (Node->getOpcode() == ISD::CALLSEQ_END) 362 return Node; 363 if (Node->use_empty()) 364 return 0; // No CallSeqEnd 365 366 // The chain is usually at the end. 367 SDOperand TheChain(Node, Node->getNumValues()-1); 368 if (TheChain.getValueType() != MVT::Other) { 369 // Sometimes it's at the beginning. 370 TheChain = SDOperand(Node, 0); 371 if (TheChain.getValueType() != MVT::Other) { 372 // Otherwise, hunt for it. 373 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 374 if (Node->getValueType(i) == MVT::Other) { 375 TheChain = SDOperand(Node, i); 376 break; 377 } 378 379 // Otherwise, we walked into a node without a chain. 380 if (TheChain.getValueType() != MVT::Other) 381 return 0; 382 } 383 } 384 385 for (SDNode::use_iterator UI = Node->use_begin(), 386 E = Node->use_end(); UI != E; ++UI) { 387 388 // Make sure to only follow users of our token chain. 389 SDNode *User = *UI; 390 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 391 if (User->getOperand(i) == TheChain) 392 if (SDNode *Result = FindCallEndFromCallStart(User)) 393 return Result; 394 } 395 return 0; 396} 397 398/// FindCallStartFromCallEnd - Given a chained node that is part of a call 399/// sequence, find the CALLSEQ_START node that initiates the call sequence. 400static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 401 assert(Node && "Didn't find callseq_start for a call??"); 402 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 403 404 assert(Node->getOperand(0).getValueType() == MVT::Other && 405 "Node doesn't have a token chain argument!"); 406 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 407} 408 409/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 410/// see if any uses can reach Dest. If no dest operands can get to dest, 411/// legalize them, legalize ourself, and return false, otherwise, return true. 412/// 413/// Keep track of the nodes we fine that actually do lead to Dest in 414/// NodesLeadingTo. This avoids retraversing them exponential number of times. 415/// 416bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 417 std::set<SDNode*> &NodesLeadingTo) { 418 if (N == Dest) return true; // N certainly leads to Dest :) 419 420 // If we've already processed this node and it does lead to Dest, there is no 421 // need to reprocess it. 422 if (NodesLeadingTo.count(N)) return true; 423 424 // If the first result of this node has been already legalized, then it cannot 425 // reach N. 426 switch (getTypeAction(N->getValueType(0))) { 427 case Legal: 428 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 429 break; 430 case Promote: 431 if (PromotedNodes.count(SDOperand(N, 0))) return false; 432 break; 433 case Expand: 434 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 435 break; 436 } 437 438 // Okay, this node has not already been legalized. Check and legalize all 439 // operands. If none lead to Dest, then we can legalize this node. 440 bool OperandsLeadToDest = false; 441 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 442 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 443 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 444 445 if (OperandsLeadToDest) { 446 NodesLeadingTo.insert(N); 447 return true; 448 } 449 450 // Okay, this node looks safe, legalize it and return false. 451 HandleOp(SDOperand(N, 0)); 452 return false; 453} 454 455/// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 456/// appropriate for its type. 457void SelectionDAGLegalize::HandleOp(SDOperand Op) { 458 switch (getTypeAction(Op.getValueType())) { 459 default: assert(0 && "Bad type action!"); 460 case Legal: LegalizeOp(Op); break; 461 case Promote: PromoteOp(Op); break; 462 case Expand: 463 if (Op.getValueType() != MVT::Vector) { 464 SDOperand X, Y; 465 ExpandOp(Op, X, Y); 466 } else { 467 SDNode *N = Op.Val; 468 unsigned NumOps = N->getNumOperands(); 469 unsigned NumElements = 470 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue(); 471 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT(); 472 MVT::ValueType PackedVT = getVectorType(EVT, NumElements); 473 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) { 474 // In the common case, this is a legal vector type, convert it to the 475 // packed operation and type now. 476 PackVectorOp(Op, PackedVT); 477 } else if (NumElements == 1) { 478 // Otherwise, if this is a single element vector, convert it to a 479 // scalar operation. 480 PackVectorOp(Op, EVT); 481 } else { 482 // Otherwise, this is a multiple element vector that isn't supported. 483 // Split it in half and legalize both parts. 484 SDOperand X, Y; 485 SplitVectorOp(Op, X, Y); 486 } 487 } 488 break; 489 } 490} 491 492/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 493/// a load from the constant pool. 494static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 495 SelectionDAG &DAG, TargetLowering &TLI) { 496 bool Extend = false; 497 498 // If a FP immediate is precise when represented as a float and if the 499 // target can do an extending load from float to double, we put it into 500 // the constant pool as a float, even if it's is statically typed as a 501 // double. 502 MVT::ValueType VT = CFP->getValueType(0); 503 bool isDouble = VT == MVT::f64; 504 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 505 Type::FloatTy, CFP->getValue()); 506 if (!UseCP) { 507 double Val = LLVMC->getValue(); 508 return isDouble 509 ? DAG.getConstant(DoubleToBits(Val), MVT::i64) 510 : DAG.getConstant(FloatToBits(Val), MVT::i32); 511 } 512 513 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 514 // Only do this if the target has a native EXTLOAD instruction from f32. 515 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 516 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); 517 VT = MVT::f32; 518 Extend = true; 519 } 520 521 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 522 if (Extend) { 523 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 524 CPIdx, NULL, 0, MVT::f32); 525 } else { 526 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 527 } 528} 529 530 531/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 532/// operations. 533static 534SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 535 SelectionDAG &DAG, TargetLowering &TLI) { 536 MVT::ValueType VT = Node->getValueType(0); 537 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 538 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 539 540 // First get the sign bit of second operand. 541 SDOperand Mask1 = (SrcVT == MVT::f64) 542 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 543 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 544 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 545 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 546 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 547 // Shift right or sign-extend it if the two operands have different types. 548 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 549 if (SizeDiff > 0) { 550 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 551 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 552 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 553 } else if (SizeDiff < 0) 554 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 555 556 // Clear the sign bit of first operand. 557 SDOperand Mask2 = (VT == MVT::f64) 558 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 559 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 560 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 561 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 562 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 563 564 // Or the value with the sign bit. 565 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 566 return Result; 567} 568 569 570/// LegalizeOp - We know that the specified value has a legal type. 571/// Recursively ensure that the operands have legal types, then return the 572/// result. 573SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 574 assert(isTypeLegal(Op.getValueType()) && 575 "Caller should expand or promote operands that are not legal!"); 576 SDNode *Node = Op.Val; 577 578 // If this operation defines any values that cannot be represented in a 579 // register on this target, make sure to expand or promote them. 580 if (Node->getNumValues() > 1) { 581 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 582 if (getTypeAction(Node->getValueType(i)) != Legal) { 583 HandleOp(Op.getValue(i)); 584 assert(LegalizedNodes.count(Op) && 585 "Handling didn't add legal operands!"); 586 return LegalizedNodes[Op]; 587 } 588 } 589 590 // Note that LegalizeOp may be reentered even from single-use nodes, which 591 // means that we always must cache transformed nodes. 592 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 593 if (I != LegalizedNodes.end()) return I->second; 594 595 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 596 SDOperand Result = Op; 597 bool isCustom = false; 598 599 switch (Node->getOpcode()) { 600 case ISD::FrameIndex: 601 case ISD::EntryToken: 602 case ISD::Register: 603 case ISD::BasicBlock: 604 case ISD::TargetFrameIndex: 605 case ISD::TargetJumpTable: 606 case ISD::TargetConstant: 607 case ISD::TargetConstantFP: 608 case ISD::TargetConstantPool: 609 case ISD::TargetGlobalAddress: 610 case ISD::TargetExternalSymbol: 611 case ISD::VALUETYPE: 612 case ISD::SRCVALUE: 613 case ISD::STRING: 614 case ISD::CONDCODE: 615 case ISD::GLOBAL_OFFSET_TABLE: 616 // Primitives must all be legal. 617 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 618 "This must be legal!"); 619 break; 620 default: 621 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 622 // If this is a target node, legalize it by legalizing the operands then 623 // passing it through. 624 SmallVector<SDOperand, 8> Ops; 625 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 626 Ops.push_back(LegalizeOp(Node->getOperand(i))); 627 628 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 629 630 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 631 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 632 return Result.getValue(Op.ResNo); 633 } 634 // Otherwise this is an unhandled builtin node. splat. 635#ifndef NDEBUG 636 cerr << "NODE: "; Node->dump(); cerr << "\n"; 637#endif 638 assert(0 && "Do not know how to legalize this operator!"); 639 abort(); 640 case ISD::GlobalAddress: 641 case ISD::ExternalSymbol: 642 case ISD::ConstantPool: 643 case ISD::JumpTable: // Nothing to do. 644 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 645 default: assert(0 && "This action is not supported yet!"); 646 case TargetLowering::Custom: 647 Tmp1 = TLI.LowerOperation(Op, DAG); 648 if (Tmp1.Val) Result = Tmp1; 649 // FALLTHROUGH if the target doesn't want to lower this op after all. 650 case TargetLowering::Legal: 651 break; 652 } 653 break; 654 case ISD::AssertSext: 655 case ISD::AssertZext: 656 Tmp1 = LegalizeOp(Node->getOperand(0)); 657 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 658 break; 659 case ISD::MERGE_VALUES: 660 // Legalize eliminates MERGE_VALUES nodes. 661 Result = Node->getOperand(Op.ResNo); 662 break; 663 case ISD::CopyFromReg: 664 Tmp1 = LegalizeOp(Node->getOperand(0)); 665 Result = Op.getValue(0); 666 if (Node->getNumValues() == 2) { 667 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 668 } else { 669 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 670 if (Node->getNumOperands() == 3) { 671 Tmp2 = LegalizeOp(Node->getOperand(2)); 672 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 673 } else { 674 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 675 } 676 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 677 } 678 // Since CopyFromReg produces two values, make sure to remember that we 679 // legalized both of them. 680 AddLegalizedOperand(Op.getValue(0), Result); 681 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 682 return Result.getValue(Op.ResNo); 683 case ISD::UNDEF: { 684 MVT::ValueType VT = Op.getValueType(); 685 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 686 default: assert(0 && "This action is not supported yet!"); 687 case TargetLowering::Expand: 688 if (MVT::isInteger(VT)) 689 Result = DAG.getConstant(0, VT); 690 else if (MVT::isFloatingPoint(VT)) 691 Result = DAG.getConstantFP(0, VT); 692 else 693 assert(0 && "Unknown value type!"); 694 break; 695 case TargetLowering::Legal: 696 break; 697 } 698 break; 699 } 700 701 case ISD::INTRINSIC_W_CHAIN: 702 case ISD::INTRINSIC_WO_CHAIN: 703 case ISD::INTRINSIC_VOID: { 704 SmallVector<SDOperand, 8> Ops; 705 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 706 Ops.push_back(LegalizeOp(Node->getOperand(i))); 707 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 708 709 // Allow the target to custom lower its intrinsics if it wants to. 710 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 711 TargetLowering::Custom) { 712 Tmp3 = TLI.LowerOperation(Result, DAG); 713 if (Tmp3.Val) Result = Tmp3; 714 } 715 716 if (Result.Val->getNumValues() == 1) break; 717 718 // Must have return value and chain result. 719 assert(Result.Val->getNumValues() == 2 && 720 "Cannot return more than two values!"); 721 722 // Since loads produce two values, make sure to remember that we 723 // legalized both of them. 724 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 725 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 726 return Result.getValue(Op.ResNo); 727 } 728 729 case ISD::LOCATION: 730 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 731 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 732 733 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 734 case TargetLowering::Promote: 735 default: assert(0 && "This action is not supported yet!"); 736 case TargetLowering::Expand: { 737 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 738 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 739 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other); 740 741 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) { 742 const std::string &FName = 743 cast<StringSDNode>(Node->getOperand(3))->getValue(); 744 const std::string &DirName = 745 cast<StringSDNode>(Node->getOperand(4))->getValue(); 746 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName); 747 748 SmallVector<SDOperand, 8> Ops; 749 Ops.push_back(Tmp1); // chain 750 SDOperand LineOp = Node->getOperand(1); 751 SDOperand ColOp = Node->getOperand(2); 752 753 if (useDEBUG_LOC) { 754 Ops.push_back(LineOp); // line # 755 Ops.push_back(ColOp); // col # 756 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 757 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 758 } else { 759 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 760 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 761 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile); 762 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 763 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size()); 764 } 765 } else { 766 Result = Tmp1; // chain 767 } 768 break; 769 } 770 case TargetLowering::Legal: 771 if (Tmp1 != Node->getOperand(0) || 772 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 773 SmallVector<SDOperand, 8> Ops; 774 Ops.push_back(Tmp1); 775 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 776 Ops.push_back(Node->getOperand(1)); // line # must be legal. 777 Ops.push_back(Node->getOperand(2)); // col # must be legal. 778 } else { 779 // Otherwise promote them. 780 Ops.push_back(PromoteOp(Node->getOperand(1))); 781 Ops.push_back(PromoteOp(Node->getOperand(2))); 782 } 783 Ops.push_back(Node->getOperand(3)); // filename must be legal. 784 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 785 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 786 } 787 break; 788 } 789 break; 790 791 case ISD::DEBUG_LOC: 792 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 793 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 794 default: assert(0 && "This action is not supported yet!"); 795 case TargetLowering::Legal: 796 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 797 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 798 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 799 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 800 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 801 break; 802 } 803 break; 804 805 case ISD::DEBUG_LABEL: 806 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!"); 807 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) { 808 default: assert(0 && "This action is not supported yet!"); 809 case TargetLowering::Legal: 810 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 811 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 812 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 813 break; 814 } 815 break; 816 817 case ISD::Constant: 818 // We know we don't need to expand constants here, constants only have one 819 // value and we check that it is fine above. 820 821 // FIXME: Maybe we should handle things like targets that don't support full 822 // 32-bit immediates? 823 break; 824 case ISD::ConstantFP: { 825 // Spill FP immediates to the constant pool if the target cannot directly 826 // codegen them. Targets often have some immediate values that can be 827 // efficiently generated into an FP register without a load. We explicitly 828 // leave these constants as ConstantFP nodes for the target to deal with. 829 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 830 831 // Check to see if this FP immediate is already legal. 832 bool isLegal = false; 833 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 834 E = TLI.legal_fpimm_end(); I != E; ++I) 835 if (CFP->isExactlyValue(*I)) { 836 isLegal = true; 837 break; 838 } 839 840 // If this is a legal constant, turn it into a TargetConstantFP node. 841 if (isLegal) { 842 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0)); 843 break; 844 } 845 846 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 847 default: assert(0 && "This action is not supported yet!"); 848 case TargetLowering::Custom: 849 Tmp3 = TLI.LowerOperation(Result, DAG); 850 if (Tmp3.Val) { 851 Result = Tmp3; 852 break; 853 } 854 // FALLTHROUGH 855 case TargetLowering::Expand: 856 Result = ExpandConstantFP(CFP, true, DAG, TLI); 857 } 858 break; 859 } 860 case ISD::TokenFactor: 861 if (Node->getNumOperands() == 2) { 862 Tmp1 = LegalizeOp(Node->getOperand(0)); 863 Tmp2 = LegalizeOp(Node->getOperand(1)); 864 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 865 } else if (Node->getNumOperands() == 3) { 866 Tmp1 = LegalizeOp(Node->getOperand(0)); 867 Tmp2 = LegalizeOp(Node->getOperand(1)); 868 Tmp3 = LegalizeOp(Node->getOperand(2)); 869 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 870 } else { 871 SmallVector<SDOperand, 8> Ops; 872 // Legalize the operands. 873 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 874 Ops.push_back(LegalizeOp(Node->getOperand(i))); 875 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 876 } 877 break; 878 879 case ISD::FORMAL_ARGUMENTS: 880 case ISD::CALL: 881 // The only option for this is to custom lower it. 882 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 883 assert(Tmp3.Val && "Target didn't custom lower this node!"); 884 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() && 885 "Lowering call/formal_arguments produced unexpected # results!"); 886 887 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 888 // remember that we legalized all of them, so it doesn't get relegalized. 889 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 890 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 891 if (Op.ResNo == i) 892 Tmp2 = Tmp1; 893 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 894 } 895 return Tmp2; 896 897 case ISD::BUILD_VECTOR: 898 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 899 default: assert(0 && "This action is not supported yet!"); 900 case TargetLowering::Custom: 901 Tmp3 = TLI.LowerOperation(Result, DAG); 902 if (Tmp3.Val) { 903 Result = Tmp3; 904 break; 905 } 906 // FALLTHROUGH 907 case TargetLowering::Expand: 908 Result = ExpandBUILD_VECTOR(Result.Val); 909 break; 910 } 911 break; 912 case ISD::INSERT_VECTOR_ELT: 913 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 914 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 915 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 916 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 917 918 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 919 Node->getValueType(0))) { 920 default: assert(0 && "This action is not supported yet!"); 921 case TargetLowering::Legal: 922 break; 923 case TargetLowering::Custom: 924 Tmp3 = TLI.LowerOperation(Result, DAG); 925 if (Tmp3.Val) { 926 Result = Tmp3; 927 break; 928 } 929 // FALLTHROUGH 930 case TargetLowering::Expand: { 931 // If the insert index is a constant, codegen this as a scalar_to_vector, 932 // then a shuffle that inserts it into the right position in the vector. 933 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 934 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 935 Tmp1.getValueType(), Tmp2); 936 937 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 938 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 939 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT); 940 941 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 942 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 943 // the RHS. 944 SmallVector<SDOperand, 8> ShufOps; 945 for (unsigned i = 0; i != NumElts; ++i) { 946 if (i != InsertPos->getValue()) 947 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 948 else 949 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 950 } 951 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 952 &ShufOps[0], ShufOps.size()); 953 954 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 955 Tmp1, ScVec, ShufMask); 956 Result = LegalizeOp(Result); 957 break; 958 } 959 960 // If the target doesn't support this, we have to spill the input vector 961 // to a temporary stack slot, update the element, then reload it. This is 962 // badness. We could also load the value into a vector register (either 963 // with a "move to register" or "extload into register" instruction, then 964 // permute it into place, if the idx is a constant and if the idx is 965 // supported by the target. 966 MVT::ValueType VT = Tmp1.getValueType(); 967 MVT::ValueType EltVT = Tmp2.getValueType(); 968 MVT::ValueType IdxVT = Tmp3.getValueType(); 969 MVT::ValueType PtrVT = TLI.getPointerTy(); 970 SDOperand StackPtr = CreateStackTemporary(VT); 971 // Store the vector. 972 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); 973 974 // Truncate or zero extend offset to target pointer type. 975 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 976 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 977 // Add the offset to the index. 978 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 979 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 980 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 981 // Store the scalar value. 982 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); 983 // Load the updated vector. 984 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); 985 break; 986 } 987 } 988 break; 989 case ISD::SCALAR_TO_VECTOR: 990 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 991 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 992 break; 993 } 994 995 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 996 Result = DAG.UpdateNodeOperands(Result, Tmp1); 997 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 998 Node->getValueType(0))) { 999 default: assert(0 && "This action is not supported yet!"); 1000 case TargetLowering::Legal: 1001 break; 1002 case TargetLowering::Custom: 1003 Tmp3 = TLI.LowerOperation(Result, DAG); 1004 if (Tmp3.Val) { 1005 Result = Tmp3; 1006 break; 1007 } 1008 // FALLTHROUGH 1009 case TargetLowering::Expand: 1010 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1011 break; 1012 } 1013 break; 1014 case ISD::VECTOR_SHUFFLE: 1015 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1016 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1017 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1018 1019 // Allow targets to custom lower the SHUFFLEs they support. 1020 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1021 default: assert(0 && "Unknown operation action!"); 1022 case TargetLowering::Legal: 1023 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1024 "vector shuffle should not be created if not legal!"); 1025 break; 1026 case TargetLowering::Custom: 1027 Tmp3 = TLI.LowerOperation(Result, DAG); 1028 if (Tmp3.Val) { 1029 Result = Tmp3; 1030 break; 1031 } 1032 // FALLTHROUGH 1033 case TargetLowering::Expand: { 1034 MVT::ValueType VT = Node->getValueType(0); 1035 MVT::ValueType EltVT = MVT::getVectorBaseType(VT); 1036 MVT::ValueType PtrVT = TLI.getPointerTy(); 1037 SDOperand Mask = Node->getOperand(2); 1038 unsigned NumElems = Mask.getNumOperands(); 1039 SmallVector<SDOperand,8> Ops; 1040 for (unsigned i = 0; i != NumElems; ++i) { 1041 SDOperand Arg = Mask.getOperand(i); 1042 if (Arg.getOpcode() == ISD::UNDEF) { 1043 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1044 } else { 1045 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1046 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1047 if (Idx < NumElems) 1048 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1049 DAG.getConstant(Idx, PtrVT))); 1050 else 1051 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1052 DAG.getConstant(Idx - NumElems, PtrVT))); 1053 } 1054 } 1055 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1056 break; 1057 } 1058 case TargetLowering::Promote: { 1059 // Change base type to a different vector type. 1060 MVT::ValueType OVT = Node->getValueType(0); 1061 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1062 1063 // Cast the two input vectors. 1064 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1065 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1066 1067 // Convert the shuffle mask to the right # elements. 1068 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1069 assert(Tmp3.Val && "Shuffle not legal?"); 1070 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1071 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1072 break; 1073 } 1074 } 1075 break; 1076 1077 case ISD::EXTRACT_VECTOR_ELT: 1078 Tmp1 = LegalizeOp(Node->getOperand(0)); 1079 Tmp2 = LegalizeOp(Node->getOperand(1)); 1080 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1081 1082 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, 1083 Tmp1.getValueType())) { 1084 default: assert(0 && "This action is not supported yet!"); 1085 case TargetLowering::Legal: 1086 break; 1087 case TargetLowering::Custom: 1088 Tmp3 = TLI.LowerOperation(Result, DAG); 1089 if (Tmp3.Val) { 1090 Result = Tmp3; 1091 break; 1092 } 1093 // FALLTHROUGH 1094 case TargetLowering::Expand: 1095 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1096 break; 1097 } 1098 break; 1099 1100 case ISD::VEXTRACT_VECTOR_ELT: 1101 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op)); 1102 break; 1103 1104 case ISD::CALLSEQ_START: { 1105 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1106 1107 // Recursively Legalize all of the inputs of the call end that do not lead 1108 // to this call start. This ensures that any libcalls that need be inserted 1109 // are inserted *before* the CALLSEQ_START. 1110 {std::set<SDNode*> NodesLeadingTo; 1111 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1112 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1113 NodesLeadingTo); 1114 } 1115 1116 // Now that we legalized all of the inputs (which may have inserted 1117 // libcalls) create the new CALLSEQ_START node. 1118 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1119 1120 // Merge in the last call, to ensure that this call start after the last 1121 // call ended. 1122 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1123 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1124 Tmp1 = LegalizeOp(Tmp1); 1125 } 1126 1127 // Do not try to legalize the target-specific arguments (#1+). 1128 if (Tmp1 != Node->getOperand(0)) { 1129 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1130 Ops[0] = Tmp1; 1131 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1132 } 1133 1134 // Remember that the CALLSEQ_START is legalized. 1135 AddLegalizedOperand(Op.getValue(0), Result); 1136 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1137 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1138 1139 // Now that the callseq_start and all of the non-call nodes above this call 1140 // sequence have been legalized, legalize the call itself. During this 1141 // process, no libcalls can/will be inserted, guaranteeing that no calls 1142 // can overlap. 1143 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1144 SDOperand InCallSEQ = LastCALLSEQ_END; 1145 // Note that we are selecting this call! 1146 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1147 IsLegalizingCall = true; 1148 1149 // Legalize the call, starting from the CALLSEQ_END. 1150 LegalizeOp(LastCALLSEQ_END); 1151 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1152 return Result; 1153 } 1154 case ISD::CALLSEQ_END: 1155 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1156 // will cause this node to be legalized as well as handling libcalls right. 1157 if (LastCALLSEQ_END.Val != Node) { 1158 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1159 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1160 assert(I != LegalizedNodes.end() && 1161 "Legalizing the call start should have legalized this node!"); 1162 return I->second; 1163 } 1164 1165 // Otherwise, the call start has been legalized and everything is going 1166 // according to plan. Just legalize ourselves normally here. 1167 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1168 // Do not try to legalize the target-specific arguments (#1+), except for 1169 // an optional flag input. 1170 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1171 if (Tmp1 != Node->getOperand(0)) { 1172 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1173 Ops[0] = Tmp1; 1174 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1175 } 1176 } else { 1177 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1178 if (Tmp1 != Node->getOperand(0) || 1179 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1180 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1181 Ops[0] = Tmp1; 1182 Ops.back() = Tmp2; 1183 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1184 } 1185 } 1186 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1187 // This finishes up call legalization. 1188 IsLegalizingCall = false; 1189 1190 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1191 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1192 if (Node->getNumValues() == 2) 1193 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1194 return Result.getValue(Op.ResNo); 1195 case ISD::DYNAMIC_STACKALLOC: { 1196 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1197 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1198 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1199 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1200 1201 Tmp1 = Result.getValue(0); 1202 Tmp2 = Result.getValue(1); 1203 switch (TLI.getOperationAction(Node->getOpcode(), 1204 Node->getValueType(0))) { 1205 default: assert(0 && "This action is not supported yet!"); 1206 case TargetLowering::Expand: { 1207 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1208 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1209 " not tell us which reg is the stack pointer!"); 1210 SDOperand Chain = Tmp1.getOperand(0); 1211 SDOperand Size = Tmp2.getOperand(1); 1212 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0)); 1213 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value 1214 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain 1215 Tmp1 = LegalizeOp(Tmp1); 1216 Tmp2 = LegalizeOp(Tmp2); 1217 break; 1218 } 1219 case TargetLowering::Custom: 1220 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1221 if (Tmp3.Val) { 1222 Tmp1 = LegalizeOp(Tmp3); 1223 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1224 } 1225 break; 1226 case TargetLowering::Legal: 1227 break; 1228 } 1229 // Since this op produce two values, make sure to remember that we 1230 // legalized both of them. 1231 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1232 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1233 return Op.ResNo ? Tmp2 : Tmp1; 1234 } 1235 case ISD::INLINEASM: { 1236 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1237 bool Changed = false; 1238 // Legalize all of the operands of the inline asm, in case they are nodes 1239 // that need to be expanded or something. Note we skip the asm string and 1240 // all of the TargetConstant flags. 1241 SDOperand Op = LegalizeOp(Ops[0]); 1242 Changed = Op != Ops[0]; 1243 Ops[0] = Op; 1244 1245 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1246 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1247 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1248 for (++i; NumVals; ++i, --NumVals) { 1249 SDOperand Op = LegalizeOp(Ops[i]); 1250 if (Op != Ops[i]) { 1251 Changed = true; 1252 Ops[i] = Op; 1253 } 1254 } 1255 } 1256 1257 if (HasInFlag) { 1258 Op = LegalizeOp(Ops.back()); 1259 Changed |= Op != Ops.back(); 1260 Ops.back() = Op; 1261 } 1262 1263 if (Changed) 1264 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1265 1266 // INLINE asm returns a chain and flag, make sure to add both to the map. 1267 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1268 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1269 return Result.getValue(Op.ResNo); 1270 } 1271 case ISD::BR: 1272 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1273 // Ensure that libcalls are emitted before a branch. 1274 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1275 Tmp1 = LegalizeOp(Tmp1); 1276 LastCALLSEQ_END = DAG.getEntryNode(); 1277 1278 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1279 break; 1280 case ISD::BRIND: 1281 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1282 // Ensure that libcalls are emitted before a branch. 1283 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1284 Tmp1 = LegalizeOp(Tmp1); 1285 LastCALLSEQ_END = DAG.getEntryNode(); 1286 1287 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1288 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1289 case Legal: 1290 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1291 break; 1292 } 1293 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1294 break; 1295 case ISD::BR_JT: 1296 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1297 // Ensure that libcalls are emitted before a branch. 1298 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1299 Tmp1 = LegalizeOp(Tmp1); 1300 LastCALLSEQ_END = DAG.getEntryNode(); 1301 1302 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1303 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1304 1305 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1306 default: assert(0 && "This action is not supported yet!"); 1307 case TargetLowering::Legal: break; 1308 case TargetLowering::Custom: 1309 Tmp1 = TLI.LowerOperation(Result, DAG); 1310 if (Tmp1.Val) Result = Tmp1; 1311 break; 1312 case TargetLowering::Expand: { 1313 SDOperand Chain = Result.getOperand(0); 1314 SDOperand Table = Result.getOperand(1); 1315 SDOperand Index = Result.getOperand(2); 1316 1317 MVT::ValueType PTy = TLI.getPointerTy(); 1318 MachineFunction &MF = DAG.getMachineFunction(); 1319 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1320 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1321 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1322 1323 SDOperand LD; 1324 switch (EntrySize) { 1325 default: assert(0 && "Size of jump table not supported yet."); break; 1326 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; 1327 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; 1328 } 1329 1330 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1331 // For PIC, the sequence is: 1332 // BRIND(load(Jumptable + index) + RelocBase) 1333 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha 1334 SDOperand Reloc; 1335 if (TLI.usesGlobalOffsetTable()) 1336 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy); 1337 else 1338 Reloc = Table; 1339 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD; 1340 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc); 1341 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1342 } else { 1343 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD); 1344 } 1345 } 1346 } 1347 break; 1348 case ISD::BRCOND: 1349 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1350 // Ensure that libcalls are emitted before a return. 1351 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1352 Tmp1 = LegalizeOp(Tmp1); 1353 LastCALLSEQ_END = DAG.getEntryNode(); 1354 1355 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1356 case Expand: assert(0 && "It's impossible to expand bools"); 1357 case Legal: 1358 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1359 break; 1360 case Promote: 1361 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1362 1363 // The top bits of the promoted condition are not necessarily zero, ensure 1364 // that the value is properly zero extended. 1365 if (!TLI.MaskedValueIsZero(Tmp2, 1366 MVT::getIntVTBitMask(Tmp2.getValueType())^1)) 1367 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1368 break; 1369 } 1370 1371 // Basic block destination (Op#2) is always legal. 1372 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1373 1374 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1375 default: assert(0 && "This action is not supported yet!"); 1376 case TargetLowering::Legal: break; 1377 case TargetLowering::Custom: 1378 Tmp1 = TLI.LowerOperation(Result, DAG); 1379 if (Tmp1.Val) Result = Tmp1; 1380 break; 1381 case TargetLowering::Expand: 1382 // Expand brcond's setcc into its constituent parts and create a BR_CC 1383 // Node. 1384 if (Tmp2.getOpcode() == ISD::SETCC) { 1385 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1386 Tmp2.getOperand(0), Tmp2.getOperand(1), 1387 Node->getOperand(2)); 1388 } else { 1389 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1390 DAG.getCondCode(ISD::SETNE), Tmp2, 1391 DAG.getConstant(0, Tmp2.getValueType()), 1392 Node->getOperand(2)); 1393 } 1394 break; 1395 } 1396 break; 1397 case ISD::BR_CC: 1398 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1399 // Ensure that libcalls are emitted before a branch. 1400 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1401 Tmp1 = LegalizeOp(Tmp1); 1402 Tmp2 = Node->getOperand(2); // LHS 1403 Tmp3 = Node->getOperand(3); // RHS 1404 Tmp4 = Node->getOperand(1); // CC 1405 1406 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1407 LastCALLSEQ_END = DAG.getEntryNode(); 1408 1409 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1410 // the LHS is a legal SETCC itself. In this case, we need to compare 1411 // the result against zero to select between true and false values. 1412 if (Tmp3.Val == 0) { 1413 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1414 Tmp4 = DAG.getCondCode(ISD::SETNE); 1415 } 1416 1417 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1418 Node->getOperand(4)); 1419 1420 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1421 default: assert(0 && "Unexpected action for BR_CC!"); 1422 case TargetLowering::Legal: break; 1423 case TargetLowering::Custom: 1424 Tmp4 = TLI.LowerOperation(Result, DAG); 1425 if (Tmp4.Val) Result = Tmp4; 1426 break; 1427 } 1428 break; 1429 case ISD::LOAD: { 1430 LoadSDNode *LD = cast<LoadSDNode>(Node); 1431 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1432 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1433 1434 ISD::LoadExtType ExtType = LD->getExtensionType(); 1435 if (ExtType == ISD::NON_EXTLOAD) { 1436 MVT::ValueType VT = Node->getValueType(0); 1437 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1438 Tmp3 = Result.getValue(0); 1439 Tmp4 = Result.getValue(1); 1440 1441 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1442 default: assert(0 && "This action is not supported yet!"); 1443 case TargetLowering::Legal: break; 1444 case TargetLowering::Custom: 1445 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1446 if (Tmp1.Val) { 1447 Tmp3 = LegalizeOp(Tmp1); 1448 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1449 } 1450 break; 1451 case TargetLowering::Promote: { 1452 // Only promote a load of vector type to another. 1453 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1454 // Change base type to a different vector type. 1455 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1456 1457 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1458 LD->getSrcValueOffset()); 1459 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1460 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1461 break; 1462 } 1463 } 1464 // Since loads produce two values, make sure to remember that we 1465 // legalized both of them. 1466 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1467 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1468 return Op.ResNo ? Tmp4 : Tmp3; 1469 } else { 1470 MVT::ValueType SrcVT = LD->getLoadedVT(); 1471 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1472 default: assert(0 && "This action is not supported yet!"); 1473 case TargetLowering::Promote: 1474 assert(SrcVT == MVT::i1 && 1475 "Can only promote extending LOAD from i1 -> i8!"); 1476 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1477 LD->getSrcValue(), LD->getSrcValueOffset(), 1478 MVT::i8); 1479 Tmp1 = Result.getValue(0); 1480 Tmp2 = Result.getValue(1); 1481 break; 1482 case TargetLowering::Custom: 1483 isCustom = true; 1484 // FALLTHROUGH 1485 case TargetLowering::Legal: 1486 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1487 Tmp1 = Result.getValue(0); 1488 Tmp2 = Result.getValue(1); 1489 1490 if (isCustom) { 1491 Tmp3 = TLI.LowerOperation(Result, DAG); 1492 if (Tmp3.Val) { 1493 Tmp1 = LegalizeOp(Tmp3); 1494 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1495 } 1496 } 1497 break; 1498 case TargetLowering::Expand: 1499 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1500 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1501 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 1502 LD->getSrcValueOffset()); 1503 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1504 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1505 Tmp2 = LegalizeOp(Load.getValue(1)); 1506 break; 1507 } 1508 assert(ExtType != ISD::EXTLOAD && "EXTLOAD should always be supported!"); 1509 // Turn the unsupported load into an EXTLOAD followed by an explicit 1510 // zero/sign extend inreg. 1511 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1512 Tmp1, Tmp2, LD->getSrcValue(), 1513 LD->getSrcValueOffset(), SrcVT); 1514 SDOperand ValRes; 1515 if (ExtType == ISD::SEXTLOAD) 1516 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1517 Result, DAG.getValueType(SrcVT)); 1518 else 1519 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1520 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1521 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1522 break; 1523 } 1524 // Since loads produce two values, make sure to remember that we legalized 1525 // both of them. 1526 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1527 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1528 return Op.ResNo ? Tmp2 : Tmp1; 1529 } 1530 } 1531 case ISD::EXTRACT_ELEMENT: { 1532 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1533 switch (getTypeAction(OpTy)) { 1534 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1535 case Legal: 1536 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1537 // 1 -> Hi 1538 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1539 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1540 TLI.getShiftAmountTy())); 1541 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1542 } else { 1543 // 0 -> Lo 1544 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1545 Node->getOperand(0)); 1546 } 1547 break; 1548 case Expand: 1549 // Get both the low and high parts. 1550 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1551 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1552 Result = Tmp2; // 1 -> Hi 1553 else 1554 Result = Tmp1; // 0 -> Lo 1555 break; 1556 } 1557 break; 1558 } 1559 1560 case ISD::CopyToReg: 1561 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1562 1563 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1564 "Register type must be legal!"); 1565 // Legalize the incoming value (must be a legal type). 1566 Tmp2 = LegalizeOp(Node->getOperand(2)); 1567 if (Node->getNumValues() == 1) { 1568 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1569 } else { 1570 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1571 if (Node->getNumOperands() == 4) { 1572 Tmp3 = LegalizeOp(Node->getOperand(3)); 1573 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1574 Tmp3); 1575 } else { 1576 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1577 } 1578 1579 // Since this produces two values, make sure to remember that we legalized 1580 // both of them. 1581 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1582 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1583 return Result; 1584 } 1585 break; 1586 1587 case ISD::RET: 1588 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1589 1590 // Ensure that libcalls are emitted before a return. 1591 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1592 Tmp1 = LegalizeOp(Tmp1); 1593 LastCALLSEQ_END = DAG.getEntryNode(); 1594 1595 switch (Node->getNumOperands()) { 1596 case 3: // ret val 1597 Tmp2 = Node->getOperand(1); 1598 Tmp3 = Node->getOperand(2); // Signness 1599 switch (getTypeAction(Tmp2.getValueType())) { 1600 case Legal: 1601 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1602 break; 1603 case Expand: 1604 if (Tmp2.getValueType() != MVT::Vector) { 1605 SDOperand Lo, Hi; 1606 ExpandOp(Tmp2, Lo, Hi); 1607 if (Hi.Val) 1608 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1609 else 1610 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 1611 Result = LegalizeOp(Result); 1612 } else { 1613 SDNode *InVal = Tmp2.Val; 1614 unsigned NumElems = 1615 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 1616 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 1617 1618 // Figure out if there is a Packed type corresponding to this Vector 1619 // type. If so, convert to the packed type. 1620 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1621 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 1622 // Turn this into a return of the packed type. 1623 Tmp2 = PackVectorOp(Tmp2, TVT); 1624 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1625 } else if (NumElems == 1) { 1626 // Turn this into a return of the scalar type. 1627 Tmp2 = PackVectorOp(Tmp2, EVT); 1628 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1629 1630 // FIXME: Returns of gcc generic vectors smaller than a legal type 1631 // should be returned in integer registers! 1632 1633 // The scalarized value type may not be legal, e.g. it might require 1634 // promotion or expansion. Relegalize the return. 1635 Result = LegalizeOp(Result); 1636 } else { 1637 // FIXME: Returns of gcc generic vectors larger than a legal vector 1638 // type should be returned by reference! 1639 SDOperand Lo, Hi; 1640 SplitVectorOp(Tmp2, Lo, Hi); 1641 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3); 1642 Result = LegalizeOp(Result); 1643 } 1644 } 1645 break; 1646 case Promote: 1647 Tmp2 = PromoteOp(Node->getOperand(1)); 1648 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1649 Result = LegalizeOp(Result); 1650 break; 1651 } 1652 break; 1653 case 1: // ret void 1654 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1655 break; 1656 default: { // ret <values> 1657 SmallVector<SDOperand, 8> NewValues; 1658 NewValues.push_back(Tmp1); 1659 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 1660 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1661 case Legal: 1662 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1663 NewValues.push_back(Node->getOperand(i+1)); 1664 break; 1665 case Expand: { 1666 SDOperand Lo, Hi; 1667 assert(Node->getOperand(i).getValueType() != MVT::Vector && 1668 "FIXME: TODO: implement returning non-legal vector types!"); 1669 ExpandOp(Node->getOperand(i), Lo, Hi); 1670 NewValues.push_back(Lo); 1671 NewValues.push_back(Node->getOperand(i+1)); 1672 if (Hi.Val) { 1673 NewValues.push_back(Hi); 1674 NewValues.push_back(Node->getOperand(i+1)); 1675 } 1676 break; 1677 } 1678 case Promote: 1679 assert(0 && "Can't promote multiple return value yet!"); 1680 } 1681 1682 if (NewValues.size() == Node->getNumOperands()) 1683 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 1684 else 1685 Result = DAG.getNode(ISD::RET, MVT::Other, 1686 &NewValues[0], NewValues.size()); 1687 break; 1688 } 1689 } 1690 1691 if (Result.getOpcode() == ISD::RET) { 1692 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 1693 default: assert(0 && "This action is not supported yet!"); 1694 case TargetLowering::Legal: break; 1695 case TargetLowering::Custom: 1696 Tmp1 = TLI.LowerOperation(Result, DAG); 1697 if (Tmp1.Val) Result = Tmp1; 1698 break; 1699 } 1700 } 1701 break; 1702 case ISD::STORE: { 1703 StoreSDNode *ST = cast<StoreSDNode>(Node); 1704 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1705 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1706 1707 if (!ST->isTruncatingStore()) { 1708 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1709 // FIXME: We shouldn't do this for TargetConstantFP's. 1710 // FIXME: move this to the DAG Combiner! Note that we can't regress due 1711 // to phase ordering between legalized code and the dag combiner. This 1712 // probably means that we need to integrate dag combiner and legalizer 1713 // together. 1714 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 1715 if (CFP->getValueType(0) == MVT::f32) { 1716 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 1717 } else { 1718 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1719 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 1720 } 1721 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1722 ST->getSrcValueOffset()); 1723 break; 1724 } 1725 1726 switch (getTypeAction(ST->getStoredVT())) { 1727 case Legal: { 1728 Tmp3 = LegalizeOp(ST->getValue()); 1729 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1730 ST->getOffset()); 1731 1732 MVT::ValueType VT = Tmp3.getValueType(); 1733 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1734 default: assert(0 && "This action is not supported yet!"); 1735 case TargetLowering::Legal: break; 1736 case TargetLowering::Custom: 1737 Tmp1 = TLI.LowerOperation(Result, DAG); 1738 if (Tmp1.Val) Result = Tmp1; 1739 break; 1740 case TargetLowering::Promote: 1741 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 1742 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 1743 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1744 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 1745 ST->getSrcValue(), ST->getSrcValueOffset()); 1746 break; 1747 } 1748 break; 1749 } 1750 case Promote: 1751 // Truncate the value and store the result. 1752 Tmp3 = PromoteOp(ST->getValue()); 1753 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1754 ST->getSrcValueOffset(), ST->getStoredVT()); 1755 break; 1756 1757 case Expand: 1758 unsigned IncrementSize = 0; 1759 SDOperand Lo, Hi; 1760 1761 // If this is a vector type, then we have to calculate the increment as 1762 // the product of the element size in bytes, and the number of elements 1763 // in the high half of the vector. 1764 if (ST->getValue().getValueType() == MVT::Vector) { 1765 SDNode *InVal = ST->getValue().Val; 1766 unsigned NumElems = 1767 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 1768 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 1769 1770 // Figure out if there is a Packed type corresponding to this Vector 1771 // type. If so, convert to the packed type. 1772 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1773 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 1774 // Turn this into a normal store of the packed type. 1775 Tmp3 = PackVectorOp(Node->getOperand(1), TVT); 1776 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1777 ST->getSrcValueOffset()); 1778 Result = LegalizeOp(Result); 1779 break; 1780 } else if (NumElems == 1) { 1781 // Turn this into a normal store of the scalar type. 1782 Tmp3 = PackVectorOp(Node->getOperand(1), EVT); 1783 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1784 ST->getSrcValueOffset()); 1785 // The scalarized value type may not be legal, e.g. it might require 1786 // promotion or expansion. Relegalize the scalar store. 1787 Result = LegalizeOp(Result); 1788 break; 1789 } else { 1790 SplitVectorOp(Node->getOperand(1), Lo, Hi); 1791 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; 1792 } 1793 } else { 1794 ExpandOp(Node->getOperand(1), Lo, Hi); 1795 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 1796 1797 if (!TLI.isLittleEndian()) 1798 std::swap(Lo, Hi); 1799 } 1800 1801 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 1802 ST->getSrcValueOffset()); 1803 1804 if (Hi.Val == NULL) { 1805 // Must be int <-> float one-to-one expansion. 1806 Result = Lo; 1807 break; 1808 } 1809 1810 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1811 getIntPtrConstant(IncrementSize)); 1812 assert(isTypeLegal(Tmp2.getValueType()) && 1813 "Pointers must be legal!"); 1814 // FIXME: This sets the srcvalue of both halves to be the same, which is 1815 // wrong. 1816 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 1817 ST->getSrcValueOffset()); 1818 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1819 break; 1820 } 1821 } else { 1822 // Truncating store 1823 assert(isTypeLegal(ST->getValue().getValueType()) && 1824 "Cannot handle illegal TRUNCSTORE yet!"); 1825 Tmp3 = LegalizeOp(ST->getValue()); 1826 1827 // The only promote case we handle is TRUNCSTORE:i1 X into 1828 // -> TRUNCSTORE:i8 (and X, 1) 1829 if (ST->getStoredVT() == MVT::i1 && 1830 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) { 1831 // Promote the bool to a mask then store. 1832 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3, 1833 DAG.getConstant(1, Tmp3.getValueType())); 1834 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1835 ST->getSrcValueOffset(), MVT::i8); 1836 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1837 Tmp2 != ST->getBasePtr()) { 1838 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1839 ST->getOffset()); 1840 } 1841 1842 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT(); 1843 switch (TLI.getStoreXAction(StVT)) { 1844 default: assert(0 && "This action is not supported yet!"); 1845 case TargetLowering::Legal: break; 1846 case TargetLowering::Custom: 1847 Tmp1 = TLI.LowerOperation(Result, DAG); 1848 if (Tmp1.Val) Result = Tmp1; 1849 break; 1850 } 1851 } 1852 break; 1853 } 1854 case ISD::PCMARKER: 1855 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1856 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1857 break; 1858 case ISD::STACKSAVE: 1859 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1860 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1861 Tmp1 = Result.getValue(0); 1862 Tmp2 = Result.getValue(1); 1863 1864 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 1865 default: assert(0 && "This action is not supported yet!"); 1866 case TargetLowering::Legal: break; 1867 case TargetLowering::Custom: 1868 Tmp3 = TLI.LowerOperation(Result, DAG); 1869 if (Tmp3.Val) { 1870 Tmp1 = LegalizeOp(Tmp3); 1871 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1872 } 1873 break; 1874 case TargetLowering::Expand: 1875 // Expand to CopyFromReg if the target set 1876 // StackPointerRegisterToSaveRestore. 1877 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1878 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 1879 Node->getValueType(0)); 1880 Tmp2 = Tmp1.getValue(1); 1881 } else { 1882 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 1883 Tmp2 = Node->getOperand(0); 1884 } 1885 break; 1886 } 1887 1888 // Since stacksave produce two values, make sure to remember that we 1889 // legalized both of them. 1890 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1891 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1892 return Op.ResNo ? Tmp2 : Tmp1; 1893 1894 case ISD::STACKRESTORE: 1895 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1896 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1897 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1898 1899 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 1900 default: assert(0 && "This action is not supported yet!"); 1901 case TargetLowering::Legal: break; 1902 case TargetLowering::Custom: 1903 Tmp1 = TLI.LowerOperation(Result, DAG); 1904 if (Tmp1.Val) Result = Tmp1; 1905 break; 1906 case TargetLowering::Expand: 1907 // Expand to CopyToReg if the target set 1908 // StackPointerRegisterToSaveRestore. 1909 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1910 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 1911 } else { 1912 Result = Tmp1; 1913 } 1914 break; 1915 } 1916 break; 1917 1918 case ISD::READCYCLECOUNTER: 1919 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1920 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1921 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 1922 Node->getValueType(0))) { 1923 default: assert(0 && "This action is not supported yet!"); 1924 case TargetLowering::Legal: 1925 Tmp1 = Result.getValue(0); 1926 Tmp2 = Result.getValue(1); 1927 break; 1928 case TargetLowering::Custom: 1929 Result = TLI.LowerOperation(Result, DAG); 1930 Tmp1 = LegalizeOp(Result.getValue(0)); 1931 Tmp2 = LegalizeOp(Result.getValue(1)); 1932 break; 1933 } 1934 1935 // Since rdcc produce two values, make sure to remember that we legalized 1936 // both of them. 1937 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1938 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1939 return Result; 1940 1941 case ISD::SELECT: 1942 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1943 case Expand: assert(0 && "It's impossible to expand bools"); 1944 case Legal: 1945 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1946 break; 1947 case Promote: 1948 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1949 // Make sure the condition is either zero or one. 1950 if (!TLI.MaskedValueIsZero(Tmp1, 1951 MVT::getIntVTBitMask(Tmp1.getValueType())^1)) 1952 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1953 break; 1954 } 1955 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1956 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1957 1958 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1959 1960 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1961 default: assert(0 && "This action is not supported yet!"); 1962 case TargetLowering::Legal: break; 1963 case TargetLowering::Custom: { 1964 Tmp1 = TLI.LowerOperation(Result, DAG); 1965 if (Tmp1.Val) Result = Tmp1; 1966 break; 1967 } 1968 case TargetLowering::Expand: 1969 if (Tmp1.getOpcode() == ISD::SETCC) { 1970 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1971 Tmp2, Tmp3, 1972 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1973 } else { 1974 Result = DAG.getSelectCC(Tmp1, 1975 DAG.getConstant(0, Tmp1.getValueType()), 1976 Tmp2, Tmp3, ISD::SETNE); 1977 } 1978 break; 1979 case TargetLowering::Promote: { 1980 MVT::ValueType NVT = 1981 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1982 unsigned ExtOp, TruncOp; 1983 if (MVT::isVector(Tmp2.getValueType())) { 1984 ExtOp = ISD::BIT_CONVERT; 1985 TruncOp = ISD::BIT_CONVERT; 1986 } else if (MVT::isInteger(Tmp2.getValueType())) { 1987 ExtOp = ISD::ANY_EXTEND; 1988 TruncOp = ISD::TRUNCATE; 1989 } else { 1990 ExtOp = ISD::FP_EXTEND; 1991 TruncOp = ISD::FP_ROUND; 1992 } 1993 // Promote each of the values to the new type. 1994 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1995 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1996 // Perform the larger operation, then round down. 1997 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1998 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1999 break; 2000 } 2001 } 2002 break; 2003 case ISD::SELECT_CC: { 2004 Tmp1 = Node->getOperand(0); // LHS 2005 Tmp2 = Node->getOperand(1); // RHS 2006 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2007 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2008 SDOperand CC = Node->getOperand(4); 2009 2010 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2011 2012 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2013 // the LHS is a legal SETCC itself. In this case, we need to compare 2014 // the result against zero to select between true and false values. 2015 if (Tmp2.Val == 0) { 2016 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2017 CC = DAG.getCondCode(ISD::SETNE); 2018 } 2019 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2020 2021 // Everything is legal, see if we should expand this op or something. 2022 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2023 default: assert(0 && "This action is not supported yet!"); 2024 case TargetLowering::Legal: break; 2025 case TargetLowering::Custom: 2026 Tmp1 = TLI.LowerOperation(Result, DAG); 2027 if (Tmp1.Val) Result = Tmp1; 2028 break; 2029 } 2030 break; 2031 } 2032 case ISD::SETCC: 2033 Tmp1 = Node->getOperand(0); 2034 Tmp2 = Node->getOperand(1); 2035 Tmp3 = Node->getOperand(2); 2036 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2037 2038 // If we had to Expand the SetCC operands into a SELECT node, then it may 2039 // not always be possible to return a true LHS & RHS. In this case, just 2040 // return the value we legalized, returned in the LHS 2041 if (Tmp2.Val == 0) { 2042 Result = Tmp1; 2043 break; 2044 } 2045 2046 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2047 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2048 case TargetLowering::Custom: 2049 isCustom = true; 2050 // FALLTHROUGH. 2051 case TargetLowering::Legal: 2052 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2053 if (isCustom) { 2054 Tmp4 = TLI.LowerOperation(Result, DAG); 2055 if (Tmp4.Val) Result = Tmp4; 2056 } 2057 break; 2058 case TargetLowering::Promote: { 2059 // First step, figure out the appropriate operation to use. 2060 // Allow SETCC to not be supported for all legal data types 2061 // Mostly this targets FP 2062 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2063 MVT::ValueType OldVT = NewInTy; 2064 2065 // Scan for the appropriate larger type to use. 2066 while (1) { 2067 NewInTy = (MVT::ValueType)(NewInTy+1); 2068 2069 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2070 "Fell off of the edge of the integer world"); 2071 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2072 "Fell off of the edge of the floating point world"); 2073 2074 // If the target supports SETCC of this type, use it. 2075 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2076 break; 2077 } 2078 if (MVT::isInteger(NewInTy)) 2079 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2080 else { 2081 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2082 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2083 } 2084 Tmp1 = LegalizeOp(Tmp1); 2085 Tmp2 = LegalizeOp(Tmp2); 2086 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2087 Result = LegalizeOp(Result); 2088 break; 2089 } 2090 case TargetLowering::Expand: 2091 // Expand a setcc node into a select_cc of the same condition, lhs, and 2092 // rhs that selects between const 1 (true) and const 0 (false). 2093 MVT::ValueType VT = Node->getValueType(0); 2094 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2095 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2096 Tmp3); 2097 break; 2098 } 2099 break; 2100 case ISD::MEMSET: 2101 case ISD::MEMCPY: 2102 case ISD::MEMMOVE: { 2103 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2104 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2105 2106 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2107 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2108 case Expand: assert(0 && "Cannot expand a byte!"); 2109 case Legal: 2110 Tmp3 = LegalizeOp(Node->getOperand(2)); 2111 break; 2112 case Promote: 2113 Tmp3 = PromoteOp(Node->getOperand(2)); 2114 break; 2115 } 2116 } else { 2117 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2118 } 2119 2120 SDOperand Tmp4; 2121 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2122 case Expand: { 2123 // Length is too big, just take the lo-part of the length. 2124 SDOperand HiPart; 2125 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2126 break; 2127 } 2128 case Legal: 2129 Tmp4 = LegalizeOp(Node->getOperand(3)); 2130 break; 2131 case Promote: 2132 Tmp4 = PromoteOp(Node->getOperand(3)); 2133 break; 2134 } 2135 2136 SDOperand Tmp5; 2137 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2138 case Expand: assert(0 && "Cannot expand this yet!"); 2139 case Legal: 2140 Tmp5 = LegalizeOp(Node->getOperand(4)); 2141 break; 2142 case Promote: 2143 Tmp5 = PromoteOp(Node->getOperand(4)); 2144 break; 2145 } 2146 2147 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2148 default: assert(0 && "This action not implemented for this operation!"); 2149 case TargetLowering::Custom: 2150 isCustom = true; 2151 // FALLTHROUGH 2152 case TargetLowering::Legal: 2153 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 2154 if (isCustom) { 2155 Tmp1 = TLI.LowerOperation(Result, DAG); 2156 if (Tmp1.Val) Result = Tmp1; 2157 } 2158 break; 2159 case TargetLowering::Expand: { 2160 // Otherwise, the target does not support this operation. Lower the 2161 // operation to an explicit libcall as appropriate. 2162 MVT::ValueType IntPtr = TLI.getPointerTy(); 2163 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2164 TargetLowering::ArgListTy Args; 2165 TargetLowering::ArgListEntry Entry; 2166 2167 const char *FnName = 0; 2168 if (Node->getOpcode() == ISD::MEMSET) { 2169 Entry.Node = Tmp2; Entry.isSigned = false; Entry.Ty = IntPtrTy; 2170 Args.push_back(Entry); 2171 // Extend the (previously legalized) ubyte argument to be an int value 2172 // for the call. 2173 if (Tmp3.getValueType() > MVT::i32) 2174 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2175 else 2176 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2177 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSigned = true; 2178 Args.push_back(Entry); 2179 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSigned = false; 2180 Args.push_back(Entry); 2181 2182 FnName = "memset"; 2183 } else if (Node->getOpcode() == ISD::MEMCPY || 2184 Node->getOpcode() == ISD::MEMMOVE) { 2185 Entry.Ty = IntPtrTy; Entry.isSigned = false; 2186 Entry.Node = Tmp2; Args.push_back(Entry); 2187 Entry.Node = Tmp3; Args.push_back(Entry); 2188 Entry.Node = Tmp4; Args.push_back(Entry); 2189 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2190 } else { 2191 assert(0 && "Unknown op!"); 2192 } 2193 2194 std::pair<SDOperand,SDOperand> CallResult = 2195 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 2196 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2197 Result = CallResult.second; 2198 break; 2199 } 2200 } 2201 break; 2202 } 2203 2204 case ISD::SHL_PARTS: 2205 case ISD::SRA_PARTS: 2206 case ISD::SRL_PARTS: { 2207 SmallVector<SDOperand, 8> Ops; 2208 bool Changed = false; 2209 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2210 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2211 Changed |= Ops.back() != Node->getOperand(i); 2212 } 2213 if (Changed) 2214 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2215 2216 switch (TLI.getOperationAction(Node->getOpcode(), 2217 Node->getValueType(0))) { 2218 default: assert(0 && "This action is not supported yet!"); 2219 case TargetLowering::Legal: break; 2220 case TargetLowering::Custom: 2221 Tmp1 = TLI.LowerOperation(Result, DAG); 2222 if (Tmp1.Val) { 2223 SDOperand Tmp2, RetVal(0, 0); 2224 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2225 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2226 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2227 if (i == Op.ResNo) 2228 RetVal = Tmp2; 2229 } 2230 assert(RetVal.Val && "Illegal result number"); 2231 return RetVal; 2232 } 2233 break; 2234 } 2235 2236 // Since these produce multiple values, make sure to remember that we 2237 // legalized all of them. 2238 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2239 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2240 return Result.getValue(Op.ResNo); 2241 } 2242 2243 // Binary operators 2244 case ISD::ADD: 2245 case ISD::SUB: 2246 case ISD::MUL: 2247 case ISD::MULHS: 2248 case ISD::MULHU: 2249 case ISD::UDIV: 2250 case ISD::SDIV: 2251 case ISD::AND: 2252 case ISD::OR: 2253 case ISD::XOR: 2254 case ISD::SHL: 2255 case ISD::SRL: 2256 case ISD::SRA: 2257 case ISD::FADD: 2258 case ISD::FSUB: 2259 case ISD::FMUL: 2260 case ISD::FDIV: 2261 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2262 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2263 case Expand: assert(0 && "Not possible"); 2264 case Legal: 2265 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2266 break; 2267 case Promote: 2268 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2269 break; 2270 } 2271 2272 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2273 2274 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2275 default: assert(0 && "BinOp legalize operation not supported"); 2276 case TargetLowering::Legal: break; 2277 case TargetLowering::Custom: 2278 Tmp1 = TLI.LowerOperation(Result, DAG); 2279 if (Tmp1.Val) Result = Tmp1; 2280 break; 2281 case TargetLowering::Expand: { 2282 if (Node->getValueType(0) == MVT::i32) { 2283 switch (Node->getOpcode()) { 2284 default: assert(0 && "Do not know how to expand this integer BinOp!"); 2285 case ISD::UDIV: 2286 case ISD::SDIV: 2287 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV 2288 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 2289 SDOperand Dummy; 2290 bool isSigned = Node->getOpcode() == ISD::SDIV; 2291 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2292 }; 2293 break; 2294 } 2295 2296 assert(MVT::isVector(Node->getValueType(0)) && 2297 "Cannot expand this binary operator!"); 2298 // Expand the operation into a bunch of nasty scalar code. 2299 SmallVector<SDOperand, 8> Ops; 2300 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0)); 2301 MVT::ValueType PtrVT = TLI.getPointerTy(); 2302 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0)); 2303 i != e; ++i) { 2304 SDOperand Idx = DAG.getConstant(i, PtrVT); 2305 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx); 2306 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx); 2307 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS)); 2308 } 2309 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), 2310 &Ops[0], Ops.size()); 2311 break; 2312 } 2313 case TargetLowering::Promote: { 2314 switch (Node->getOpcode()) { 2315 default: assert(0 && "Do not know how to promote this BinOp!"); 2316 case ISD::AND: 2317 case ISD::OR: 2318 case ISD::XOR: { 2319 MVT::ValueType OVT = Node->getValueType(0); 2320 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2321 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2322 // Bit convert each of the values to the new type. 2323 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2324 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2325 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2326 // Bit convert the result back the original type. 2327 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2328 break; 2329 } 2330 } 2331 } 2332 } 2333 break; 2334 2335 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2336 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2337 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2338 case Expand: assert(0 && "Not possible"); 2339 case Legal: 2340 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2341 break; 2342 case Promote: 2343 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2344 break; 2345 } 2346 2347 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2348 2349 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2350 default: assert(0 && "Operation not supported"); 2351 case TargetLowering::Custom: 2352 Tmp1 = TLI.LowerOperation(Result, DAG); 2353 if (Tmp1.Val) Result = Tmp1; 2354 break; 2355 case TargetLowering::Legal: break; 2356 case TargetLowering::Expand: { 2357 // If this target supports fabs/fneg natively and select is cheap, 2358 // do this efficiently. 2359 if (!TLI.isSelectExpensive() && 2360 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 2361 TargetLowering::Legal && 2362 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 2363 TargetLowering::Legal) { 2364 // Get the sign bit of the RHS. 2365 MVT::ValueType IVT = 2366 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2367 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2368 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2369 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2370 // Get the absolute value of the result. 2371 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2372 // Select between the nabs and abs value based on the sign bit of 2373 // the input. 2374 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2375 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2376 AbsVal), 2377 AbsVal); 2378 Result = LegalizeOp(Result); 2379 break; 2380 } 2381 2382 // Otherwise, do bitwise ops! 2383 MVT::ValueType NVT = 2384 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 2385 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 2386 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 2387 Result = LegalizeOp(Result); 2388 break; 2389 } 2390 } 2391 break; 2392 2393 case ISD::ADDC: 2394 case ISD::SUBC: 2395 Tmp1 = LegalizeOp(Node->getOperand(0)); 2396 Tmp2 = LegalizeOp(Node->getOperand(1)); 2397 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2398 // Since this produces two values, make sure to remember that we legalized 2399 // both of them. 2400 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2401 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2402 return Result; 2403 2404 case ISD::ADDE: 2405 case ISD::SUBE: 2406 Tmp1 = LegalizeOp(Node->getOperand(0)); 2407 Tmp2 = LegalizeOp(Node->getOperand(1)); 2408 Tmp3 = LegalizeOp(Node->getOperand(2)); 2409 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2410 // Since this produces two values, make sure to remember that we legalized 2411 // both of them. 2412 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2413 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2414 return Result; 2415 2416 case ISD::BUILD_PAIR: { 2417 MVT::ValueType PairTy = Node->getValueType(0); 2418 // TODO: handle the case where the Lo and Hi operands are not of legal type 2419 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2420 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2421 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2422 case TargetLowering::Promote: 2423 case TargetLowering::Custom: 2424 assert(0 && "Cannot promote/custom this yet!"); 2425 case TargetLowering::Legal: 2426 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2427 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2428 break; 2429 case TargetLowering::Expand: 2430 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2431 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2432 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2433 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2434 TLI.getShiftAmountTy())); 2435 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2436 break; 2437 } 2438 break; 2439 } 2440 2441 case ISD::UREM: 2442 case ISD::SREM: 2443 case ISD::FREM: 2444 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2445 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2446 2447 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2448 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2449 case TargetLowering::Custom: 2450 isCustom = true; 2451 // FALLTHROUGH 2452 case TargetLowering::Legal: 2453 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2454 if (isCustom) { 2455 Tmp1 = TLI.LowerOperation(Result, DAG); 2456 if (Tmp1.Val) Result = Tmp1; 2457 } 2458 break; 2459 case TargetLowering::Expand: 2460 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2461 bool isSigned = DivOpc == ISD::SDIV; 2462 if (MVT::isInteger(Node->getValueType(0))) { 2463 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) == 2464 TargetLowering::Legal) { 2465 // X % Y -> X-X/Y*Y 2466 MVT::ValueType VT = Node->getValueType(0); 2467 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 2468 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2469 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2470 } else { 2471 assert(Node->getValueType(0) == MVT::i32 && 2472 "Cannot expand this binary operator!"); 2473 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 2474 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 2475 SDOperand Dummy; 2476 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2477 } 2478 } else { 2479 // Floating point mod -> fmod libcall. 2480 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32 2481 ? RTLIB::REM_F32 : RTLIB::REM_F64; 2482 SDOperand Dummy; 2483 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2484 false/*sign irrelevant*/, Dummy); 2485 } 2486 break; 2487 } 2488 break; 2489 case ISD::VAARG: { 2490 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2491 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2492 2493 MVT::ValueType VT = Node->getValueType(0); 2494 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2495 default: assert(0 && "This action is not supported yet!"); 2496 case TargetLowering::Custom: 2497 isCustom = true; 2498 // FALLTHROUGH 2499 case TargetLowering::Legal: 2500 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2501 Result = Result.getValue(0); 2502 Tmp1 = Result.getValue(1); 2503 2504 if (isCustom) { 2505 Tmp2 = TLI.LowerOperation(Result, DAG); 2506 if (Tmp2.Val) { 2507 Result = LegalizeOp(Tmp2); 2508 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 2509 } 2510 } 2511 break; 2512 case TargetLowering::Expand: { 2513 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 2514 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2515 SV->getValue(), SV->getOffset()); 2516 // Increment the pointer, VAList, to the next vaarg 2517 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2518 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2519 TLI.getPointerTy())); 2520 // Store the incremented VAList to the legalized pointer 2521 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 2522 SV->getOffset()); 2523 // Load the actual argument out of the pointer VAList 2524 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 2525 Tmp1 = LegalizeOp(Result.getValue(1)); 2526 Result = LegalizeOp(Result); 2527 break; 2528 } 2529 } 2530 // Since VAARG produces two values, make sure to remember that we 2531 // legalized both of them. 2532 AddLegalizedOperand(SDOperand(Node, 0), Result); 2533 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 2534 return Op.ResNo ? Tmp1 : Result; 2535 } 2536 2537 case ISD::VACOPY: 2538 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2539 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 2540 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 2541 2542 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 2543 default: assert(0 && "This action is not supported yet!"); 2544 case TargetLowering::Custom: 2545 isCustom = true; 2546 // FALLTHROUGH 2547 case TargetLowering::Legal: 2548 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 2549 Node->getOperand(3), Node->getOperand(4)); 2550 if (isCustom) { 2551 Tmp1 = TLI.LowerOperation(Result, DAG); 2552 if (Tmp1.Val) Result = Tmp1; 2553 } 2554 break; 2555 case TargetLowering::Expand: 2556 // This defaults to loading a pointer from the input and storing it to the 2557 // output, returning the chain. 2558 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); 2559 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); 2560 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), 2561 SVD->getOffset()); 2562 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), 2563 SVS->getOffset()); 2564 break; 2565 } 2566 break; 2567 2568 case ISD::VAEND: 2569 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2570 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2571 2572 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 2573 default: assert(0 && "This action is not supported yet!"); 2574 case TargetLowering::Custom: 2575 isCustom = true; 2576 // FALLTHROUGH 2577 case TargetLowering::Legal: 2578 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2579 if (isCustom) { 2580 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 2581 if (Tmp1.Val) Result = Tmp1; 2582 } 2583 break; 2584 case TargetLowering::Expand: 2585 Result = Tmp1; // Default to a no-op, return the chain 2586 break; 2587 } 2588 break; 2589 2590 case ISD::VASTART: 2591 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2592 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2593 2594 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2595 2596 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 2597 default: assert(0 && "This action is not supported yet!"); 2598 case TargetLowering::Legal: break; 2599 case TargetLowering::Custom: 2600 Tmp1 = TLI.LowerOperation(Result, DAG); 2601 if (Tmp1.Val) Result = Tmp1; 2602 break; 2603 } 2604 break; 2605 2606 case ISD::ROTL: 2607 case ISD::ROTR: 2608 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2609 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2610 2611 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 2612 "Cannot handle this yet!"); 2613 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2614 break; 2615 2616 case ISD::BSWAP: 2617 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2618 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2619 case TargetLowering::Custom: 2620 assert(0 && "Cannot custom legalize this yet!"); 2621 case TargetLowering::Legal: 2622 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2623 break; 2624 case TargetLowering::Promote: { 2625 MVT::ValueType OVT = Tmp1.getValueType(); 2626 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2627 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT); 2628 2629 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2630 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 2631 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 2632 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 2633 break; 2634 } 2635 case TargetLowering::Expand: 2636 Result = ExpandBSWAP(Tmp1); 2637 break; 2638 } 2639 break; 2640 2641 case ISD::CTPOP: 2642 case ISD::CTTZ: 2643 case ISD::CTLZ: 2644 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2645 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2646 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!"); 2647 case TargetLowering::Legal: 2648 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2649 break; 2650 case TargetLowering::Promote: { 2651 MVT::ValueType OVT = Tmp1.getValueType(); 2652 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2653 2654 // Zero extend the argument. 2655 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2656 // Perform the larger operation, then subtract if needed. 2657 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2658 switch (Node->getOpcode()) { 2659 case ISD::CTPOP: 2660 Result = Tmp1; 2661 break; 2662 case ISD::CTTZ: 2663 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2664 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2665 DAG.getConstant(getSizeInBits(NVT), NVT), 2666 ISD::SETEQ); 2667 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2668 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 2669 break; 2670 case ISD::CTLZ: 2671 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2672 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2673 DAG.getConstant(getSizeInBits(NVT) - 2674 getSizeInBits(OVT), NVT)); 2675 break; 2676 } 2677 break; 2678 } 2679 case TargetLowering::Expand: 2680 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 2681 break; 2682 } 2683 break; 2684 2685 // Unary operators 2686 case ISD::FABS: 2687 case ISD::FNEG: 2688 case ISD::FSQRT: 2689 case ISD::FSIN: 2690 case ISD::FCOS: 2691 Tmp1 = LegalizeOp(Node->getOperand(0)); 2692 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2693 case TargetLowering::Promote: 2694 case TargetLowering::Custom: 2695 isCustom = true; 2696 // FALLTHROUGH 2697 case TargetLowering::Legal: 2698 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2699 if (isCustom) { 2700 Tmp1 = TLI.LowerOperation(Result, DAG); 2701 if (Tmp1.Val) Result = Tmp1; 2702 } 2703 break; 2704 case TargetLowering::Expand: 2705 switch (Node->getOpcode()) { 2706 default: assert(0 && "Unreachable!"); 2707 case ISD::FNEG: 2708 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2709 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2710 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 2711 break; 2712 case ISD::FABS: { 2713 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2714 MVT::ValueType VT = Node->getValueType(0); 2715 Tmp2 = DAG.getConstantFP(0.0, VT); 2716 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2717 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2718 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2719 break; 2720 } 2721 case ISD::FSQRT: 2722 case ISD::FSIN: 2723 case ISD::FCOS: { 2724 MVT::ValueType VT = Node->getValueType(0); 2725 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2726 switch(Node->getOpcode()) { 2727 case ISD::FSQRT: 2728 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64; 2729 break; 2730 case ISD::FSIN: 2731 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 2732 break; 2733 case ISD::FCOS: 2734 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64; 2735 break; 2736 default: assert(0 && "Unreachable!"); 2737 } 2738 SDOperand Dummy; 2739 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2740 false/*sign irrelevant*/, Dummy); 2741 break; 2742 } 2743 } 2744 break; 2745 } 2746 break; 2747 case ISD::FPOWI: { 2748 // We always lower FPOWI into a libcall. No target support it yet. 2749 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32 2750 ? RTLIB::POWI_F32 : RTLIB::POWI_F64; 2751 SDOperand Dummy; 2752 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2753 false/*sign irrelevant*/, Dummy); 2754 break; 2755 } 2756 case ISD::BIT_CONVERT: 2757 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 2758 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2759 } else { 2760 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 2761 Node->getOperand(0).getValueType())) { 2762 default: assert(0 && "Unknown operation action!"); 2763 case TargetLowering::Expand: 2764 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2765 break; 2766 case TargetLowering::Legal: 2767 Tmp1 = LegalizeOp(Node->getOperand(0)); 2768 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2769 break; 2770 } 2771 } 2772 break; 2773 case ISD::VBIT_CONVERT: { 2774 assert(Op.getOperand(0).getValueType() == MVT::Vector && 2775 "Can only have VBIT_CONVERT where input or output is MVT::Vector!"); 2776 2777 // The input has to be a vector type, we have to either scalarize it, pack 2778 // it, or convert it based on whether the input vector type is legal. 2779 SDNode *InVal = Node->getOperand(0).Val; 2780 unsigned NumElems = 2781 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 2782 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 2783 2784 // Figure out if there is a Packed type corresponding to this Vector 2785 // type. If so, convert to the packed type. 2786 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2787 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 2788 // Turn this into a bit convert of the packed input. 2789 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2790 PackVectorOp(Node->getOperand(0), TVT)); 2791 break; 2792 } else if (NumElems == 1) { 2793 // Turn this into a bit convert of the scalar input. 2794 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2795 PackVectorOp(Node->getOperand(0), EVT)); 2796 break; 2797 } else { 2798 // FIXME: UNIMP! Store then reload 2799 assert(0 && "Cast from unsupported vector type not implemented yet!"); 2800 } 2801 } 2802 2803 // Conversion operators. The source and destination have different types. 2804 case ISD::SINT_TO_FP: 2805 case ISD::UINT_TO_FP: { 2806 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2807 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2808 case Legal: 2809 switch (TLI.getOperationAction(Node->getOpcode(), 2810 Node->getOperand(0).getValueType())) { 2811 default: assert(0 && "Unknown operation action!"); 2812 case TargetLowering::Custom: 2813 isCustom = true; 2814 // FALLTHROUGH 2815 case TargetLowering::Legal: 2816 Tmp1 = LegalizeOp(Node->getOperand(0)); 2817 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2818 if (isCustom) { 2819 Tmp1 = TLI.LowerOperation(Result, DAG); 2820 if (Tmp1.Val) Result = Tmp1; 2821 } 2822 break; 2823 case TargetLowering::Expand: 2824 Result = ExpandLegalINT_TO_FP(isSigned, 2825 LegalizeOp(Node->getOperand(0)), 2826 Node->getValueType(0)); 2827 break; 2828 case TargetLowering::Promote: 2829 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2830 Node->getValueType(0), 2831 isSigned); 2832 break; 2833 } 2834 break; 2835 case Expand: 2836 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2837 Node->getValueType(0), Node->getOperand(0)); 2838 break; 2839 case Promote: 2840 Tmp1 = PromoteOp(Node->getOperand(0)); 2841 if (isSigned) { 2842 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 2843 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 2844 } else { 2845 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 2846 Node->getOperand(0).getValueType()); 2847 } 2848 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2849 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 2850 break; 2851 } 2852 break; 2853 } 2854 case ISD::TRUNCATE: 2855 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2856 case Legal: 2857 Tmp1 = LegalizeOp(Node->getOperand(0)); 2858 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2859 break; 2860 case Expand: 2861 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2862 2863 // Since the result is legal, we should just be able to truncate the low 2864 // part of the source. 2865 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2866 break; 2867 case Promote: 2868 Result = PromoteOp(Node->getOperand(0)); 2869 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2870 break; 2871 } 2872 break; 2873 2874 case ISD::FP_TO_SINT: 2875 case ISD::FP_TO_UINT: 2876 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2877 case Legal: 2878 Tmp1 = LegalizeOp(Node->getOperand(0)); 2879 2880 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2881 default: assert(0 && "Unknown operation action!"); 2882 case TargetLowering::Custom: 2883 isCustom = true; 2884 // FALLTHROUGH 2885 case TargetLowering::Legal: 2886 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2887 if (isCustom) { 2888 Tmp1 = TLI.LowerOperation(Result, DAG); 2889 if (Tmp1.Val) Result = Tmp1; 2890 } 2891 break; 2892 case TargetLowering::Promote: 2893 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2894 Node->getOpcode() == ISD::FP_TO_SINT); 2895 break; 2896 case TargetLowering::Expand: 2897 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2898 SDOperand True, False; 2899 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2900 MVT::ValueType NVT = Node->getValueType(0); 2901 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2902 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2903 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2904 Node->getOperand(0), Tmp2, ISD::SETLT); 2905 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2906 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2907 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2908 Tmp2)); 2909 False = DAG.getNode(ISD::XOR, NVT, False, 2910 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2911 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 2912 break; 2913 } else { 2914 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2915 } 2916 break; 2917 } 2918 break; 2919 case Expand: { 2920 // Convert f32 / f64 to i32 / i64. 2921 MVT::ValueType VT = Op.getValueType(); 2922 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2923 switch (Node->getOpcode()) { 2924 case ISD::FP_TO_SINT: 2925 if (Node->getOperand(0).getValueType() == MVT::f32) 2926 LC = (VT == MVT::i32) 2927 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 2928 else 2929 LC = (VT == MVT::i32) 2930 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 2931 break; 2932 case ISD::FP_TO_UINT: 2933 if (Node->getOperand(0).getValueType() == MVT::f32) 2934 LC = (VT == MVT::i32) 2935 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 2936 else 2937 LC = (VT == MVT::i32) 2938 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 2939 break; 2940 default: assert(0 && "Unreachable!"); 2941 } 2942 SDOperand Dummy; 2943 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2944 false/*sign irrelevant*/, Dummy); 2945 break; 2946 } 2947 case Promote: 2948 Tmp1 = PromoteOp(Node->getOperand(0)); 2949 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 2950 Result = LegalizeOp(Result); 2951 break; 2952 } 2953 break; 2954 2955 case ISD::ANY_EXTEND: 2956 case ISD::ZERO_EXTEND: 2957 case ISD::SIGN_EXTEND: 2958 case ISD::FP_EXTEND: 2959 case ISD::FP_ROUND: 2960 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2961 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 2962 case Legal: 2963 Tmp1 = LegalizeOp(Node->getOperand(0)); 2964 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2965 break; 2966 case Promote: 2967 switch (Node->getOpcode()) { 2968 case ISD::ANY_EXTEND: 2969 Tmp1 = PromoteOp(Node->getOperand(0)); 2970 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 2971 break; 2972 case ISD::ZERO_EXTEND: 2973 Result = PromoteOp(Node->getOperand(0)); 2974 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2975 Result = DAG.getZeroExtendInReg(Result, 2976 Node->getOperand(0).getValueType()); 2977 break; 2978 case ISD::SIGN_EXTEND: 2979 Result = PromoteOp(Node->getOperand(0)); 2980 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2981 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2982 Result, 2983 DAG.getValueType(Node->getOperand(0).getValueType())); 2984 break; 2985 case ISD::FP_EXTEND: 2986 Result = PromoteOp(Node->getOperand(0)); 2987 if (Result.getValueType() != Op.getValueType()) 2988 // Dynamically dead while we have only 2 FP types. 2989 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2990 break; 2991 case ISD::FP_ROUND: 2992 Result = PromoteOp(Node->getOperand(0)); 2993 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2994 break; 2995 } 2996 } 2997 break; 2998 case ISD::FP_ROUND_INREG: 2999 case ISD::SIGN_EXTEND_INREG: { 3000 Tmp1 = LegalizeOp(Node->getOperand(0)); 3001 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3002 3003 // If this operation is not supported, convert it to a shl/shr or load/store 3004 // pair. 3005 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3006 default: assert(0 && "This action not supported for this op yet!"); 3007 case TargetLowering::Legal: 3008 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3009 break; 3010 case TargetLowering::Expand: 3011 // If this is an integer extend and shifts are supported, do that. 3012 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3013 // NOTE: we could fall back on load/store here too for targets without 3014 // SAR. However, it is doubtful that any exist. 3015 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3016 MVT::getSizeInBits(ExtraVT); 3017 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3018 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3019 Node->getOperand(0), ShiftCst); 3020 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3021 Result, ShiftCst); 3022 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3023 // The only way we can lower this is to turn it into a TRUNCSTORE, 3024 // EXTLOAD pair, targetting a temporary location (a stack slot). 3025 3026 // NOTE: there is a choice here between constantly creating new stack 3027 // slots and always reusing the same one. We currently always create 3028 // new ones, as reuse may inhibit scheduling. 3029 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 3030 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty); 3031 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty); 3032 MachineFunction &MF = DAG.getMachineFunction(); 3033 int SSFI = 3034 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 3035 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3036 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3037 StackSlot, NULL, 0, ExtraVT); 3038 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 3039 Result, StackSlot, NULL, 0, ExtraVT); 3040 } else { 3041 assert(0 && "Unknown op"); 3042 } 3043 break; 3044 } 3045 break; 3046 } 3047 } 3048 3049 assert(Result.getValueType() == Op.getValueType() && 3050 "Bad legalization!"); 3051 3052 // Make sure that the generated code is itself legal. 3053 if (Result != Op) 3054 Result = LegalizeOp(Result); 3055 3056 // Note that LegalizeOp may be reentered even from single-use nodes, which 3057 // means that we always must cache transformed nodes. 3058 AddLegalizedOperand(Op, Result); 3059 return Result; 3060} 3061 3062/// PromoteOp - Given an operation that produces a value in an invalid type, 3063/// promote it to compute the value into a larger type. The produced value will 3064/// have the correct bits for the low portion of the register, but no guarantee 3065/// is made about the top bits: it may be zero, sign-extended, or garbage. 3066SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 3067 MVT::ValueType VT = Op.getValueType(); 3068 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3069 assert(getTypeAction(VT) == Promote && 3070 "Caller should expand or legalize operands that are not promotable!"); 3071 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 3072 "Cannot promote to smaller type!"); 3073 3074 SDOperand Tmp1, Tmp2, Tmp3; 3075 SDOperand Result; 3076 SDNode *Node = Op.Val; 3077 3078 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 3079 if (I != PromotedNodes.end()) return I->second; 3080 3081 switch (Node->getOpcode()) { 3082 case ISD::CopyFromReg: 3083 assert(0 && "CopyFromReg must be legal!"); 3084 default: 3085#ifndef NDEBUG 3086 cerr << "NODE: "; Node->dump(); cerr << "\n"; 3087#endif 3088 assert(0 && "Do not know how to promote this operator!"); 3089 abort(); 3090 case ISD::UNDEF: 3091 Result = DAG.getNode(ISD::UNDEF, NVT); 3092 break; 3093 case ISD::Constant: 3094 if (VT != MVT::i1) 3095 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 3096 else 3097 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 3098 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 3099 break; 3100 case ISD::ConstantFP: 3101 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 3102 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 3103 break; 3104 3105 case ISD::SETCC: 3106 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 3107 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 3108 Node->getOperand(1), Node->getOperand(2)); 3109 break; 3110 3111 case ISD::TRUNCATE: 3112 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3113 case Legal: 3114 Result = LegalizeOp(Node->getOperand(0)); 3115 assert(Result.getValueType() >= NVT && 3116 "This truncation doesn't make sense!"); 3117 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 3118 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 3119 break; 3120 case Promote: 3121 // The truncation is not required, because we don't guarantee anything 3122 // about high bits anyway. 3123 Result = PromoteOp(Node->getOperand(0)); 3124 break; 3125 case Expand: 3126 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3127 // Truncate the low part of the expanded value to the result type 3128 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 3129 } 3130 break; 3131 case ISD::SIGN_EXTEND: 3132 case ISD::ZERO_EXTEND: 3133 case ISD::ANY_EXTEND: 3134 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3135 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 3136 case Legal: 3137 // Input is legal? Just do extend all the way to the larger type. 3138 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3139 break; 3140 case Promote: 3141 // Promote the reg if it's smaller. 3142 Result = PromoteOp(Node->getOperand(0)); 3143 // The high bits are not guaranteed to be anything. Insert an extend. 3144 if (Node->getOpcode() == ISD::SIGN_EXTEND) 3145 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3146 DAG.getValueType(Node->getOperand(0).getValueType())); 3147 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 3148 Result = DAG.getZeroExtendInReg(Result, 3149 Node->getOperand(0).getValueType()); 3150 break; 3151 } 3152 break; 3153 case ISD::BIT_CONVERT: 3154 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3155 Result = PromoteOp(Result); 3156 break; 3157 3158 case ISD::FP_EXTEND: 3159 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 3160 case ISD::FP_ROUND: 3161 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3162 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 3163 case Promote: assert(0 && "Unreachable with 2 FP types!"); 3164 case Legal: 3165 // Input is legal? Do an FP_ROUND_INREG. 3166 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 3167 DAG.getValueType(VT)); 3168 break; 3169 } 3170 break; 3171 3172 case ISD::SINT_TO_FP: 3173 case ISD::UINT_TO_FP: 3174 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3175 case Legal: 3176 // No extra round required here. 3177 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3178 break; 3179 3180 case Promote: 3181 Result = PromoteOp(Node->getOperand(0)); 3182 if (Node->getOpcode() == ISD::SINT_TO_FP) 3183 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3184 Result, 3185 DAG.getValueType(Node->getOperand(0).getValueType())); 3186 else 3187 Result = DAG.getZeroExtendInReg(Result, 3188 Node->getOperand(0).getValueType()); 3189 // No extra round required here. 3190 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3191 break; 3192 case Expand: 3193 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3194 Node->getOperand(0)); 3195 // Round if we cannot tolerate excess precision. 3196 if (NoExcessFPPrecision) 3197 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3198 DAG.getValueType(VT)); 3199 break; 3200 } 3201 break; 3202 3203 case ISD::SIGN_EXTEND_INREG: 3204 Result = PromoteOp(Node->getOperand(0)); 3205 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3206 Node->getOperand(1)); 3207 break; 3208 case ISD::FP_TO_SINT: 3209 case ISD::FP_TO_UINT: 3210 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3211 case Legal: 3212 case Expand: 3213 Tmp1 = Node->getOperand(0); 3214 break; 3215 case Promote: 3216 // The input result is prerounded, so we don't have to do anything 3217 // special. 3218 Tmp1 = PromoteOp(Node->getOperand(0)); 3219 break; 3220 } 3221 // If we're promoting a UINT to a larger size, check to see if the new node 3222 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3223 // we can use that instead. This allows us to generate better code for 3224 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3225 // legal, such as PowerPC. 3226 if (Node->getOpcode() == ISD::FP_TO_UINT && 3227 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3228 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3229 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3230 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3231 } else { 3232 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3233 } 3234 break; 3235 3236 case ISD::FABS: 3237 case ISD::FNEG: 3238 Tmp1 = PromoteOp(Node->getOperand(0)); 3239 assert(Tmp1.getValueType() == NVT); 3240 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3241 // NOTE: we do not have to do any extra rounding here for 3242 // NoExcessFPPrecision, because we know the input will have the appropriate 3243 // precision, and these operations don't modify precision at all. 3244 break; 3245 3246 case ISD::FSQRT: 3247 case ISD::FSIN: 3248 case ISD::FCOS: 3249 Tmp1 = PromoteOp(Node->getOperand(0)); 3250 assert(Tmp1.getValueType() == NVT); 3251 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3252 if (NoExcessFPPrecision) 3253 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3254 DAG.getValueType(VT)); 3255 break; 3256 3257 case ISD::AND: 3258 case ISD::OR: 3259 case ISD::XOR: 3260 case ISD::ADD: 3261 case ISD::SUB: 3262 case ISD::MUL: 3263 // The input may have strange things in the top bits of the registers, but 3264 // these operations don't care. They may have weird bits going out, but 3265 // that too is okay if they are integer operations. 3266 Tmp1 = PromoteOp(Node->getOperand(0)); 3267 Tmp2 = PromoteOp(Node->getOperand(1)); 3268 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3269 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3270 break; 3271 case ISD::FADD: 3272 case ISD::FSUB: 3273 case ISD::FMUL: 3274 Tmp1 = PromoteOp(Node->getOperand(0)); 3275 Tmp2 = PromoteOp(Node->getOperand(1)); 3276 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3277 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3278 3279 // Floating point operations will give excess precision that we may not be 3280 // able to tolerate. If we DO allow excess precision, just leave it, 3281 // otherwise excise it. 3282 // FIXME: Why would we need to round FP ops more than integer ones? 3283 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3284 if (NoExcessFPPrecision) 3285 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3286 DAG.getValueType(VT)); 3287 break; 3288 3289 case ISD::SDIV: 3290 case ISD::SREM: 3291 // These operators require that their input be sign extended. 3292 Tmp1 = PromoteOp(Node->getOperand(0)); 3293 Tmp2 = PromoteOp(Node->getOperand(1)); 3294 if (MVT::isInteger(NVT)) { 3295 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3296 DAG.getValueType(VT)); 3297 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3298 DAG.getValueType(VT)); 3299 } 3300 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3301 3302 // Perform FP_ROUND: this is probably overly pessimistic. 3303 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 3304 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3305 DAG.getValueType(VT)); 3306 break; 3307 case ISD::FDIV: 3308 case ISD::FREM: 3309 case ISD::FCOPYSIGN: 3310 // These operators require that their input be fp extended. 3311 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3312 case Legal: 3313 Tmp1 = LegalizeOp(Node->getOperand(0)); 3314 break; 3315 case Promote: 3316 Tmp1 = PromoteOp(Node->getOperand(0)); 3317 break; 3318 case Expand: 3319 assert(0 && "not implemented"); 3320 } 3321 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3322 case Legal: 3323 Tmp2 = LegalizeOp(Node->getOperand(1)); 3324 break; 3325 case Promote: 3326 Tmp2 = PromoteOp(Node->getOperand(1)); 3327 break; 3328 case Expand: 3329 assert(0 && "not implemented"); 3330 } 3331 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3332 3333 // Perform FP_ROUND: this is probably overly pessimistic. 3334 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 3335 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3336 DAG.getValueType(VT)); 3337 break; 3338 3339 case ISD::UDIV: 3340 case ISD::UREM: 3341 // These operators require that their input be zero extended. 3342 Tmp1 = PromoteOp(Node->getOperand(0)); 3343 Tmp2 = PromoteOp(Node->getOperand(1)); 3344 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 3345 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3346 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3347 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3348 break; 3349 3350 case ISD::SHL: 3351 Tmp1 = PromoteOp(Node->getOperand(0)); 3352 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 3353 break; 3354 case ISD::SRA: 3355 // The input value must be properly sign extended. 3356 Tmp1 = PromoteOp(Node->getOperand(0)); 3357 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3358 DAG.getValueType(VT)); 3359 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 3360 break; 3361 case ISD::SRL: 3362 // The input value must be properly zero extended. 3363 Tmp1 = PromoteOp(Node->getOperand(0)); 3364 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3365 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 3366 break; 3367 3368 case ISD::VAARG: 3369 Tmp1 = Node->getOperand(0); // Get the chain. 3370 Tmp2 = Node->getOperand(1); // Get the pointer. 3371 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 3372 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 3373 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 3374 } else { 3375 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 3376 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3377 SV->getValue(), SV->getOffset()); 3378 // Increment the pointer, VAList, to the next vaarg 3379 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3380 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3381 TLI.getPointerTy())); 3382 // Store the incremented VAList to the legalized pointer 3383 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 3384 SV->getOffset()); 3385 // Load the actual argument out of the pointer VAList 3386 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 3387 } 3388 // Remember that we legalized the chain. 3389 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3390 break; 3391 3392 case ISD::LOAD: { 3393 LoadSDNode *LD = cast<LoadSDNode>(Node); 3394 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 3395 ? ISD::EXTLOAD : LD->getExtensionType(); 3396 Result = DAG.getExtLoad(ExtType, NVT, 3397 LD->getChain(), LD->getBasePtr(), 3398 LD->getSrcValue(), LD->getSrcValueOffset(), 3399 LD->getLoadedVT()); 3400 // Remember that we legalized the chain. 3401 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3402 break; 3403 } 3404 case ISD::SELECT: 3405 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 3406 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 3407 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 3408 break; 3409 case ISD::SELECT_CC: 3410 Tmp2 = PromoteOp(Node->getOperand(2)); // True 3411 Tmp3 = PromoteOp(Node->getOperand(3)); // False 3412 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3413 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 3414 break; 3415 case ISD::BSWAP: 3416 Tmp1 = Node->getOperand(0); 3417 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3418 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3419 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3420 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT), 3421 TLI.getShiftAmountTy())); 3422 break; 3423 case ISD::CTPOP: 3424 case ISD::CTTZ: 3425 case ISD::CTLZ: 3426 // Zero extend the argument 3427 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 3428 // Perform the larger operation, then subtract if needed. 3429 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3430 switch(Node->getOpcode()) { 3431 case ISD::CTPOP: 3432 Result = Tmp1; 3433 break; 3434 case ISD::CTTZ: 3435 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3436 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3437 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 3438 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3439 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1); 3440 break; 3441 case ISD::CTLZ: 3442 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3443 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3444 DAG.getConstant(getSizeInBits(NVT) - 3445 getSizeInBits(VT), NVT)); 3446 break; 3447 } 3448 break; 3449 case ISD::VEXTRACT_VECTOR_ELT: 3450 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op)); 3451 break; 3452 case ISD::EXTRACT_VECTOR_ELT: 3453 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 3454 break; 3455 } 3456 3457 assert(Result.Val && "Didn't set a result!"); 3458 3459 // Make sure the result is itself legal. 3460 Result = LegalizeOp(Result); 3461 3462 // Remember that we promoted this! 3463 AddPromotedOperand(Op, Result); 3464 return Result; 3465} 3466 3467/// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a 3468/// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based 3469/// on the vector type. The return type of this matches the element type of the 3470/// vector, which may not be legal for the target. 3471SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) { 3472 // We know that operand #0 is the Vec vector. If the index is a constant 3473 // or if the invec is a supported hardware type, we can use it. Otherwise, 3474 // lower to a store then an indexed load. 3475 SDOperand Vec = Op.getOperand(0); 3476 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 3477 3478 SDNode *InVal = Vec.Val; 3479 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 3480 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 3481 3482 // Figure out if there is a Packed type corresponding to this Vector 3483 // type. If so, convert to the packed type. 3484 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3485 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 3486 // Turn this into a packed extract_vector_elt operation. 3487 Vec = PackVectorOp(Vec, TVT); 3488 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx); 3489 } else if (NumElems == 1) { 3490 // This must be an access of the only element. Return it. 3491 return PackVectorOp(Vec, EVT); 3492 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 3493 SDOperand Lo, Hi; 3494 SplitVectorOp(Vec, Lo, Hi); 3495 if (CIdx->getValue() < NumElems/2) { 3496 Vec = Lo; 3497 } else { 3498 Vec = Hi; 3499 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 3500 } 3501 3502 // It's now an extract from the appropriate high or low part. Recurse. 3503 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3504 return LowerVEXTRACT_VECTOR_ELT(Op); 3505 } else { 3506 // Variable index case for extract element. 3507 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!! 3508 assert(0 && "unimp!"); 3509 return SDOperand(); 3510 } 3511} 3512 3513/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 3514/// memory traffic. 3515SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 3516 SDOperand Vector = Op.getOperand(0); 3517 SDOperand Idx = Op.getOperand(1); 3518 3519 // If the target doesn't support this, store the value to a temporary 3520 // stack slot, then LOAD the scalar element back out. 3521 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType()); 3522 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vector, StackPtr, NULL, 0); 3523 3524 // Add the offset to the index. 3525 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 3526 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 3527 DAG.getConstant(EltSize, Idx.getValueType())); 3528 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 3529 3530 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 3531} 3532 3533 3534/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 3535/// with condition CC on the current target. This usually involves legalizing 3536/// or promoting the arguments. In the case where LHS and RHS must be expanded, 3537/// there may be no choice but to create a new SetCC node to represent the 3538/// legalized value of setcc lhs, rhs. In this case, the value is returned in 3539/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 3540void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 3541 SDOperand &RHS, 3542 SDOperand &CC) { 3543 SDOperand Tmp1, Tmp2, Result; 3544 3545 switch (getTypeAction(LHS.getValueType())) { 3546 case Legal: 3547 Tmp1 = LegalizeOp(LHS); // LHS 3548 Tmp2 = LegalizeOp(RHS); // RHS 3549 break; 3550 case Promote: 3551 Tmp1 = PromoteOp(LHS); // LHS 3552 Tmp2 = PromoteOp(RHS); // RHS 3553 3554 // If this is an FP compare, the operands have already been extended. 3555 if (MVT::isInteger(LHS.getValueType())) { 3556 MVT::ValueType VT = LHS.getValueType(); 3557 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3558 3559 // Otherwise, we have to insert explicit sign or zero extends. Note 3560 // that we could insert sign extends for ALL conditions, but zero extend 3561 // is cheaper on many machines (an AND instead of two shifts), so prefer 3562 // it. 3563 switch (cast<CondCodeSDNode>(CC)->get()) { 3564 default: assert(0 && "Unknown integer comparison!"); 3565 case ISD::SETEQ: 3566 case ISD::SETNE: 3567 case ISD::SETUGE: 3568 case ISD::SETUGT: 3569 case ISD::SETULE: 3570 case ISD::SETULT: 3571 // ALL of these operations will work if we either sign or zero extend 3572 // the operands (including the unsigned comparisons!). Zero extend is 3573 // usually a simpler/cheaper operation, so prefer it. 3574 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3575 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3576 break; 3577 case ISD::SETGE: 3578 case ISD::SETGT: 3579 case ISD::SETLT: 3580 case ISD::SETLE: 3581 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3582 DAG.getValueType(VT)); 3583 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3584 DAG.getValueType(VT)); 3585 break; 3586 } 3587 } 3588 break; 3589 case Expand: { 3590 MVT::ValueType VT = LHS.getValueType(); 3591 if (VT == MVT::f32 || VT == MVT::f64) { 3592 // Expand into one or more soft-fp libcall(s). 3593 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 3594 ISD::CondCode CC1, CC2 = ISD::SETCC_INVALID; 3595 switch (cast<CondCodeSDNode>(CC)->get()) { 3596 case ISD::SETEQ: 3597 case ISD::SETOEQ: 3598 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 3599 CC1 = ISD::SETEQ; 3600 break; 3601 case ISD::SETNE: 3602 case ISD::SETUNE: 3603 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 3604 CC1 = ISD::SETNE; 3605 break; 3606 case ISD::SETGE: 3607 case ISD::SETOGE: 3608 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 3609 CC1 = ISD::SETGE; 3610 break; 3611 case ISD::SETLT: 3612 case ISD::SETOLT: 3613 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3614 CC1 = ISD::SETLT; 3615 break; 3616 case ISD::SETLE: 3617 case ISD::SETOLE: 3618 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 3619 CC1 = ISD::SETLE; 3620 break; 3621 case ISD::SETGT: 3622 case ISD::SETOGT: 3623 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 3624 CC1 = ISD::SETGT; 3625 break; 3626 case ISD::SETUO: 3627 case ISD::SETO: 3628 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 3629 CC1 = cast<CondCodeSDNode>(CC)->get() == ISD::SETO 3630 ? ISD::SETEQ : ISD::SETNE; 3631 break; 3632 default: 3633 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 3634 CC1 = ISD::SETNE; 3635 switch (cast<CondCodeSDNode>(CC)->get()) { 3636 case ISD::SETONE: 3637 // SETONE = SETOLT | SETOGT 3638 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3639 CC1 = ISD::SETLT; 3640 // Fallthrough 3641 case ISD::SETUGT: 3642 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 3643 CC2 = ISD::SETGT; 3644 break; 3645 case ISD::SETUGE: 3646 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 3647 CC2 = ISD::SETGE; 3648 break; 3649 case ISD::SETULT: 3650 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3651 CC2 = ISD::SETLT; 3652 break; 3653 case ISD::SETULE: 3654 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 3655 CC2 = ISD::SETLE; 3656 break; 3657 case ISD::SETUEQ: 3658 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 3659 CC2 = ISD::SETEQ; 3660 break; 3661 default: assert(0 && "Unsupported FP setcc!"); 3662 } 3663 } 3664 3665 SDOperand Dummy; 3666 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 3667 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 3668 false /*sign irrelevant*/, Dummy); 3669 Tmp2 = DAG.getConstant(0, MVT::i32); 3670 CC = DAG.getCondCode(CC1); 3671 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 3672 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); 3673 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 3674 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 3675 false /*sign irrelevant*/, Dummy); 3676 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, 3677 DAG.getCondCode(CC2)); 3678 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 3679 Tmp2 = SDOperand(); 3680 } 3681 LHS = Tmp1; 3682 RHS = Tmp2; 3683 return; 3684 } 3685 3686 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 3687 ExpandOp(LHS, LHSLo, LHSHi); 3688 ExpandOp(RHS, RHSLo, RHSHi); 3689 switch (cast<CondCodeSDNode>(CC)->get()) { 3690 case ISD::SETEQ: 3691 case ISD::SETNE: 3692 if (RHSLo == RHSHi) 3693 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 3694 if (RHSCST->isAllOnesValue()) { 3695 // Comparison to -1. 3696 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 3697 Tmp2 = RHSLo; 3698 break; 3699 } 3700 3701 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 3702 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 3703 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 3704 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3705 break; 3706 default: 3707 // If this is a comparison of the sign bit, just look at the top part. 3708 // X > -1, x < 0 3709 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 3710 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 3711 CST->getValue() == 0) || // X < 0 3712 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 3713 CST->isAllOnesValue())) { // X > -1 3714 Tmp1 = LHSHi; 3715 Tmp2 = RHSHi; 3716 break; 3717 } 3718 3719 // FIXME: This generated code sucks. 3720 ISD::CondCode LowCC; 3721 switch (cast<CondCodeSDNode>(CC)->get()) { 3722 default: assert(0 && "Unknown integer setcc!"); 3723 case ISD::SETLT: 3724 case ISD::SETULT: LowCC = ISD::SETULT; break; 3725 case ISD::SETGT: 3726 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 3727 case ISD::SETLE: 3728 case ISD::SETULE: LowCC = ISD::SETULE; break; 3729 case ISD::SETGE: 3730 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 3731 } 3732 3733 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 3734 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 3735 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 3736 3737 // NOTE: on targets without efficient SELECT of bools, we can always use 3738 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 3739 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 3740 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC); 3741 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 3742 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 3743 Result, Tmp1, Tmp2)); 3744 Tmp1 = Result; 3745 Tmp2 = SDOperand(); 3746 } 3747 } 3748 } 3749 LHS = Tmp1; 3750 RHS = Tmp2; 3751} 3752 3753/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 3754/// The resultant code need not be legal. Note that SrcOp is the input operand 3755/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 3756SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 3757 SDOperand SrcOp) { 3758 // Create the stack frame object. 3759 SDOperand FIPtr = CreateStackTemporary(DestVT); 3760 3761 // Emit a store to the stack slot. 3762 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); 3763 // Result is a load from the stack slot. 3764 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 3765} 3766 3767SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 3768 // Create a vector sized/aligned stack slot, store the value to element #0, 3769 // then load the whole vector back out. 3770 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); 3771 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 3772 NULL, 0); 3773 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); 3774} 3775 3776 3777/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 3778/// support the operation, but do support the resultant packed vector type. 3779SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 3780 3781 // If the only non-undef value is the low element, turn this into a 3782 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 3783 unsigned NumElems = Node->getNumOperands(); 3784 bool isOnlyLowElement = true; 3785 SDOperand SplatValue = Node->getOperand(0); 3786 std::map<SDOperand, std::vector<unsigned> > Values; 3787 Values[SplatValue].push_back(0); 3788 bool isConstant = true; 3789 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 3790 SplatValue.getOpcode() != ISD::UNDEF) 3791 isConstant = false; 3792 3793 for (unsigned i = 1; i < NumElems; ++i) { 3794 SDOperand V = Node->getOperand(i); 3795 Values[V].push_back(i); 3796 if (V.getOpcode() != ISD::UNDEF) 3797 isOnlyLowElement = false; 3798 if (SplatValue != V) 3799 SplatValue = SDOperand(0,0); 3800 3801 // If this isn't a constant element or an undef, we can't use a constant 3802 // pool load. 3803 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 3804 V.getOpcode() != ISD::UNDEF) 3805 isConstant = false; 3806 } 3807 3808 if (isOnlyLowElement) { 3809 // If the low element is an undef too, then this whole things is an undef. 3810 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 3811 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 3812 // Otherwise, turn this into a scalar_to_vector node. 3813 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 3814 Node->getOperand(0)); 3815 } 3816 3817 // If all elements are constants, create a load from the constant pool. 3818 if (isConstant) { 3819 MVT::ValueType VT = Node->getValueType(0); 3820 const Type *OpNTy = 3821 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 3822 std::vector<Constant*> CV; 3823 for (unsigned i = 0, e = NumElems; i != e; ++i) { 3824 if (ConstantFPSDNode *V = 3825 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 3826 CV.push_back(ConstantFP::get(OpNTy, V->getValue())); 3827 } else if (ConstantSDNode *V = 3828 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 3829 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 3830 } else { 3831 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 3832 CV.push_back(UndefValue::get(OpNTy)); 3833 } 3834 } 3835 Constant *CP = ConstantPacked::get(CV); 3836 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 3837 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 3838 } 3839 3840 if (SplatValue.Val) { // Splat of one value? 3841 // Build the shuffle constant vector: <0, 0, 0, 0> 3842 MVT::ValueType MaskVT = 3843 MVT::getIntVectorWithNumElements(NumElems); 3844 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT)); 3845 std::vector<SDOperand> ZeroVec(NumElems, Zero); 3846 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3847 &ZeroVec[0], ZeroVec.size()); 3848 3849 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 3850 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 3851 // Get the splatted value into the low element of a vector register. 3852 SDOperand LowValVec = 3853 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 3854 3855 // Return shuffle(LowValVec, undef, <0,0,0,0>) 3856 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 3857 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 3858 SplatMask); 3859 } 3860 } 3861 3862 // If there are only two unique elements, we may be able to turn this into a 3863 // vector shuffle. 3864 if (Values.size() == 2) { 3865 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 3866 MVT::ValueType MaskVT = 3867 MVT::getIntVectorWithNumElements(NumElems); 3868 std::vector<SDOperand> MaskVec(NumElems); 3869 unsigned i = 0; 3870 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 3871 E = Values.end(); I != E; ++I) { 3872 for (std::vector<unsigned>::iterator II = I->second.begin(), 3873 EE = I->second.end(); II != EE; ++II) 3874 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT)); 3875 i += NumElems; 3876 } 3877 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3878 &MaskVec[0], MaskVec.size()); 3879 3880 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 3881 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 3882 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 3883 SmallVector<SDOperand, 8> Ops; 3884 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 3885 E = Values.end(); I != E; ++I) { 3886 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 3887 I->first); 3888 Ops.push_back(Op); 3889 } 3890 Ops.push_back(ShuffleMask); 3891 3892 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 3893 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 3894 &Ops[0], Ops.size()); 3895 } 3896 } 3897 3898 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 3899 // aligned object on the stack, store each element into it, then load 3900 // the result as a vector. 3901 MVT::ValueType VT = Node->getValueType(0); 3902 // Create the stack frame object. 3903 SDOperand FIPtr = CreateStackTemporary(VT); 3904 3905 // Emit a store of each element to the stack slot. 3906 SmallVector<SDOperand, 8> Stores; 3907 unsigned TypeByteSize = 3908 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 3909 // Store (in the right endianness) the elements to memory. 3910 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3911 // Ignore undef elements. 3912 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3913 3914 unsigned Offset = TypeByteSize*i; 3915 3916 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 3917 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 3918 3919 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 3920 NULL, 0)); 3921 } 3922 3923 SDOperand StoreChain; 3924 if (!Stores.empty()) // Not all undef elements? 3925 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3926 &Stores[0], Stores.size()); 3927 else 3928 StoreChain = DAG.getEntryNode(); 3929 3930 // Result is a load from the stack slot. 3931 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 3932} 3933 3934/// CreateStackTemporary - Create a stack temporary, suitable for holding the 3935/// specified value type. 3936SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) { 3937 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 3938 unsigned ByteSize = MVT::getSizeInBits(VT)/8; 3939 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize); 3940 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 3941} 3942 3943void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 3944 SDOperand Op, SDOperand Amt, 3945 SDOperand &Lo, SDOperand &Hi) { 3946 // Expand the subcomponents. 3947 SDOperand LHSL, LHSH; 3948 ExpandOp(Op, LHSL, LHSH); 3949 3950 SDOperand Ops[] = { LHSL, LHSH, Amt }; 3951 MVT::ValueType VT = LHSL.getValueType(); 3952 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 3953 Hi = Lo.getValue(1); 3954} 3955 3956 3957/// ExpandShift - Try to find a clever way to expand this shift operation out to 3958/// smaller elements. If we can't find a way that is more efficient than a 3959/// libcall on this target, return false. Otherwise, return true with the 3960/// low-parts expanded into Lo and Hi. 3961bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 3962 SDOperand &Lo, SDOperand &Hi) { 3963 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 3964 "This is not a shift!"); 3965 3966 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 3967 SDOperand ShAmt = LegalizeOp(Amt); 3968 MVT::ValueType ShTy = ShAmt.getValueType(); 3969 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 3970 unsigned NVTBits = MVT::getSizeInBits(NVT); 3971 3972 // Handle the case when Amt is an immediate. Other cases are currently broken 3973 // and are disabled. 3974 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 3975 unsigned Cst = CN->getValue(); 3976 // Expand the incoming operand to be shifted, so that we have its parts 3977 SDOperand InL, InH; 3978 ExpandOp(Op, InL, InH); 3979 switch(Opc) { 3980 case ISD::SHL: 3981 if (Cst > VTBits) { 3982 Lo = DAG.getConstant(0, NVT); 3983 Hi = DAG.getConstant(0, NVT); 3984 } else if (Cst > NVTBits) { 3985 Lo = DAG.getConstant(0, NVT); 3986 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 3987 } else if (Cst == NVTBits) { 3988 Lo = DAG.getConstant(0, NVT); 3989 Hi = InL; 3990 } else { 3991 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 3992 Hi = DAG.getNode(ISD::OR, NVT, 3993 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 3994 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 3995 } 3996 return true; 3997 case ISD::SRL: 3998 if (Cst > VTBits) { 3999 Lo = DAG.getConstant(0, NVT); 4000 Hi = DAG.getConstant(0, NVT); 4001 } else if (Cst > NVTBits) { 4002 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 4003 Hi = DAG.getConstant(0, NVT); 4004 } else if (Cst == NVTBits) { 4005 Lo = InH; 4006 Hi = DAG.getConstant(0, NVT); 4007 } else { 4008 Lo = DAG.getNode(ISD::OR, NVT, 4009 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4010 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4011 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 4012 } 4013 return true; 4014 case ISD::SRA: 4015 if (Cst > VTBits) { 4016 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 4017 DAG.getConstant(NVTBits-1, ShTy)); 4018 } else if (Cst > NVTBits) { 4019 Lo = DAG.getNode(ISD::SRA, NVT, InH, 4020 DAG.getConstant(Cst-NVTBits, ShTy)); 4021 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4022 DAG.getConstant(NVTBits-1, ShTy)); 4023 } else if (Cst == NVTBits) { 4024 Lo = InH; 4025 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4026 DAG.getConstant(NVTBits-1, ShTy)); 4027 } else { 4028 Lo = DAG.getNode(ISD::OR, NVT, 4029 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4030 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4031 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 4032 } 4033 return true; 4034 } 4035 } 4036 4037 // Okay, the shift amount isn't constant. However, if we can tell that it is 4038 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 4039 uint64_t Mask = NVTBits, KnownZero, KnownOne; 4040 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 4041 4042 // If we know that the high bit of the shift amount is one, then we can do 4043 // this as a couple of simple shifts. 4044 if (KnownOne & Mask) { 4045 // Mask out the high bit, which we know is set. 4046 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 4047 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4048 4049 // Expand the incoming operand to be shifted, so that we have its parts 4050 SDOperand InL, InH; 4051 ExpandOp(Op, InL, InH); 4052 switch(Opc) { 4053 case ISD::SHL: 4054 Lo = DAG.getConstant(0, NVT); // Low part is zero. 4055 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 4056 return true; 4057 case ISD::SRL: 4058 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 4059 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 4060 return true; 4061 case ISD::SRA: 4062 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 4063 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4064 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 4065 return true; 4066 } 4067 } 4068 4069 // If we know that the high bit of the shift amount is zero, then we can do 4070 // this as a couple of simple shifts. 4071 if (KnownZero & Mask) { 4072 // Compute 32-amt. 4073 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 4074 DAG.getConstant(NVTBits, Amt.getValueType()), 4075 Amt); 4076 4077 // Expand the incoming operand to be shifted, so that we have its parts 4078 SDOperand InL, InH; 4079 ExpandOp(Op, InL, InH); 4080 switch(Opc) { 4081 case ISD::SHL: 4082 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 4083 Hi = DAG.getNode(ISD::OR, NVT, 4084 DAG.getNode(ISD::SHL, NVT, InH, Amt), 4085 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 4086 return true; 4087 case ISD::SRL: 4088 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 4089 Lo = DAG.getNode(ISD::OR, NVT, 4090 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4091 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4092 return true; 4093 case ISD::SRA: 4094 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 4095 Lo = DAG.getNode(ISD::OR, NVT, 4096 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4097 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4098 return true; 4099 } 4100 } 4101 4102 return false; 4103} 4104 4105 4106// ExpandLibCall - Expand a node into a call to a libcall. If the result value 4107// does not fit into a register, return the lo part and set the hi part to the 4108// by-reg argument. If it does fit into a single register, return the result 4109// and leave the Hi part unset. 4110SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 4111 bool isSigned, SDOperand &Hi) { 4112 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 4113 // The input chain to this libcall is the entry node of the function. 4114 // Legalizing the call will automatically add the previous call to the 4115 // dependence. 4116 SDOperand InChain = DAG.getEntryNode(); 4117 4118 TargetLowering::ArgListTy Args; 4119 TargetLowering::ArgListEntry Entry; 4120 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4121 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 4122 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 4123 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 4124 Entry.isSigned = isSigned; 4125 Args.push_back(Entry); 4126 } 4127 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 4128 4129 // Splice the libcall in wherever FindInputOutputChains tells us to. 4130 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 4131 std::pair<SDOperand,SDOperand> CallInfo = 4132 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false, 4133 Callee, Args, DAG); 4134 4135 // Legalize the call sequence, starting with the chain. This will advance 4136 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 4137 // was added by LowerCallTo (guaranteeing proper serialization of calls). 4138 LegalizeOp(CallInfo.second); 4139 SDOperand Result; 4140 switch (getTypeAction(CallInfo.first.getValueType())) { 4141 default: assert(0 && "Unknown thing"); 4142 case Legal: 4143 Result = CallInfo.first; 4144 break; 4145 case Expand: 4146 ExpandOp(CallInfo.first, Result, Hi); 4147 break; 4148 } 4149 return Result; 4150} 4151 4152 4153/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 4154/// destination type is legal. 4155SDOperand SelectionDAGLegalize:: 4156ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 4157 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 4158 assert(getTypeAction(Source.getValueType()) == Expand && 4159 "This is not an expansion!"); 4160 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 4161 4162 if (!isSigned) { 4163 assert(Source.getValueType() == MVT::i64 && 4164 "This only works for 64-bit -> FP"); 4165 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 4166 // incoming integer is set. To handle this, we dynamically test to see if 4167 // it is set, and, if so, add a fudge factor. 4168 SDOperand Lo, Hi; 4169 ExpandOp(Source, Lo, Hi); 4170 4171 // If this is unsigned, and not supported, first perform the conversion to 4172 // signed, then adjust the result if the sign bit is set. 4173 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 4174 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 4175 4176 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 4177 DAG.getConstant(0, Hi.getValueType()), 4178 ISD::SETLT); 4179 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4180 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4181 SignSet, Four, Zero); 4182 uint64_t FF = 0x5f800000ULL; 4183 if (TLI.isLittleEndian()) FF <<= 32; 4184 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4185 4186 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4187 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4188 SDOperand FudgeInReg; 4189 if (DestTy == MVT::f32) 4190 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4191 else { 4192 assert(DestTy == MVT::f64 && "Unexpected conversion"); 4193 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 4194 CPIdx, NULL, 0, MVT::f32); 4195 } 4196 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 4197 } 4198 4199 // Check to see if the target has a custom way to lower this. If so, use it. 4200 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 4201 default: assert(0 && "This action not implemented for this operation!"); 4202 case TargetLowering::Legal: 4203 case TargetLowering::Expand: 4204 break; // This case is handled below. 4205 case TargetLowering::Custom: { 4206 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 4207 Source), DAG); 4208 if (NV.Val) 4209 return LegalizeOp(NV); 4210 break; // The target decided this was legal after all 4211 } 4212 } 4213 4214 // Expand the source, then glue it back together for the call. We must expand 4215 // the source in case it is shared (this pass of legalize must traverse it). 4216 SDOperand SrcLo, SrcHi; 4217 ExpandOp(Source, SrcLo, SrcHi); 4218 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 4219 4220 RTLIB::Libcall LC; 4221 if (DestTy == MVT::f32) 4222 LC = RTLIB::SINTTOFP_I64_F32; 4223 else { 4224 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 4225 LC = RTLIB::SINTTOFP_I64_F64; 4226 } 4227 4228 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 4229 SDOperand UnusedHiPart; 4230 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 4231 UnusedHiPart); 4232} 4233 4234/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 4235/// INT_TO_FP operation of the specified operand when the target requests that 4236/// we expand it. At this point, we know that the result and operand types are 4237/// legal for the target. 4238SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 4239 SDOperand Op0, 4240 MVT::ValueType DestVT) { 4241 if (Op0.getValueType() == MVT::i32) { 4242 // simple 32-bit [signed|unsigned] integer to float/double expansion 4243 4244 // get the stack frame index of a 8 byte buffer 4245 MachineFunction &MF = DAG.getMachineFunction(); 4246 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 4247 // get address of 8 byte buffer 4248 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4249 // word offset constant for Hi/Lo address computation 4250 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 4251 // set up Hi and Lo (into buffer) address based on endian 4252 SDOperand Hi = StackSlot; 4253 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 4254 if (TLI.isLittleEndian()) 4255 std::swap(Hi, Lo); 4256 4257 // if signed map to unsigned space 4258 SDOperand Op0Mapped; 4259 if (isSigned) { 4260 // constant used to invert sign bit (signed to unsigned mapping) 4261 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 4262 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 4263 } else { 4264 Op0Mapped = Op0; 4265 } 4266 // store the lo of the constructed double - based on integer input 4267 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 4268 Op0Mapped, Lo, NULL, 0); 4269 // initial hi portion of constructed double 4270 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 4271 // store the hi of the constructed double - biased exponent 4272 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 4273 // load the constructed double 4274 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 4275 // FP constant to bias correct the final result 4276 SDOperand Bias = DAG.getConstantFP(isSigned ? 4277 BitsToDouble(0x4330000080000000ULL) 4278 : BitsToDouble(0x4330000000000000ULL), 4279 MVT::f64); 4280 // subtract the bias 4281 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 4282 // final result 4283 SDOperand Result; 4284 // handle final rounding 4285 if (DestVT == MVT::f64) { 4286 // do nothing 4287 Result = Sub; 4288 } else { 4289 // if f32 then cast to f32 4290 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 4291 } 4292 return Result; 4293 } 4294 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 4295 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 4296 4297 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 4298 DAG.getConstant(0, Op0.getValueType()), 4299 ISD::SETLT); 4300 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4301 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4302 SignSet, Four, Zero); 4303 4304 // If the sign bit of the integer is set, the large number will be treated 4305 // as a negative number. To counteract this, the dynamic code adds an 4306 // offset depending on the data type. 4307 uint64_t FF; 4308 switch (Op0.getValueType()) { 4309 default: assert(0 && "Unsupported integer type!"); 4310 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 4311 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 4312 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 4313 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 4314 } 4315 if (TLI.isLittleEndian()) FF <<= 32; 4316 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4317 4318 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4319 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4320 SDOperand FudgeInReg; 4321 if (DestVT == MVT::f32) 4322 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4323 else { 4324 assert(DestVT == MVT::f64 && "Unexpected conversion"); 4325 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 4326 DAG.getEntryNode(), CPIdx, 4327 NULL, 0, MVT::f32)); 4328 } 4329 4330 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 4331} 4332 4333/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 4334/// *INT_TO_FP operation of the specified operand when the target requests that 4335/// we promote it. At this point, we know that the result and operand types are 4336/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 4337/// operation that takes a larger input. 4338SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 4339 MVT::ValueType DestVT, 4340 bool isSigned) { 4341 // First step, figure out the appropriate *INT_TO_FP operation to use. 4342 MVT::ValueType NewInTy = LegalOp.getValueType(); 4343 4344 unsigned OpToUse = 0; 4345 4346 // Scan for the appropriate larger type to use. 4347 while (1) { 4348 NewInTy = (MVT::ValueType)(NewInTy+1); 4349 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 4350 4351 // If the target supports SINT_TO_FP of this type, use it. 4352 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 4353 default: break; 4354 case TargetLowering::Legal: 4355 if (!TLI.isTypeLegal(NewInTy)) 4356 break; // Can't use this datatype. 4357 // FALL THROUGH. 4358 case TargetLowering::Custom: 4359 OpToUse = ISD::SINT_TO_FP; 4360 break; 4361 } 4362 if (OpToUse) break; 4363 if (isSigned) continue; 4364 4365 // If the target supports UINT_TO_FP of this type, use it. 4366 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 4367 default: break; 4368 case TargetLowering::Legal: 4369 if (!TLI.isTypeLegal(NewInTy)) 4370 break; // Can't use this datatype. 4371 // FALL THROUGH. 4372 case TargetLowering::Custom: 4373 OpToUse = ISD::UINT_TO_FP; 4374 break; 4375 } 4376 if (OpToUse) break; 4377 4378 // Otherwise, try a larger type. 4379 } 4380 4381 // Okay, we found the operation and type to use. Zero extend our input to the 4382 // desired type then run the operation on it. 4383 return DAG.getNode(OpToUse, DestVT, 4384 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 4385 NewInTy, LegalOp)); 4386} 4387 4388/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 4389/// FP_TO_*INT operation of the specified operand when the target requests that 4390/// we promote it. At this point, we know that the result and operand types are 4391/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 4392/// operation that returns a larger result. 4393SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 4394 MVT::ValueType DestVT, 4395 bool isSigned) { 4396 // First step, figure out the appropriate FP_TO*INT operation to use. 4397 MVT::ValueType NewOutTy = DestVT; 4398 4399 unsigned OpToUse = 0; 4400 4401 // Scan for the appropriate larger type to use. 4402 while (1) { 4403 NewOutTy = (MVT::ValueType)(NewOutTy+1); 4404 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 4405 4406 // If the target supports FP_TO_SINT returning this type, use it. 4407 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 4408 default: break; 4409 case TargetLowering::Legal: 4410 if (!TLI.isTypeLegal(NewOutTy)) 4411 break; // Can't use this datatype. 4412 // FALL THROUGH. 4413 case TargetLowering::Custom: 4414 OpToUse = ISD::FP_TO_SINT; 4415 break; 4416 } 4417 if (OpToUse) break; 4418 4419 // If the target supports FP_TO_UINT of this type, use it. 4420 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 4421 default: break; 4422 case TargetLowering::Legal: 4423 if (!TLI.isTypeLegal(NewOutTy)) 4424 break; // Can't use this datatype. 4425 // FALL THROUGH. 4426 case TargetLowering::Custom: 4427 OpToUse = ISD::FP_TO_UINT; 4428 break; 4429 } 4430 if (OpToUse) break; 4431 4432 // Otherwise, try a larger type. 4433 } 4434 4435 // Okay, we found the operation and type to use. Truncate the result of the 4436 // extended FP_TO_*INT operation to the desired size. 4437 return DAG.getNode(ISD::TRUNCATE, DestVT, 4438 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 4439} 4440 4441/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 4442/// 4443SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 4444 MVT::ValueType VT = Op.getValueType(); 4445 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 4446 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 4447 switch (VT) { 4448 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 4449 case MVT::i16: 4450 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4451 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4452 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 4453 case MVT::i32: 4454 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4455 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4456 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4457 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4458 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 4459 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 4460 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4461 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4462 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4463 case MVT::i64: 4464 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 4465 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 4466 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4467 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4468 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4469 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4470 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 4471 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 4472 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 4473 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 4474 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 4475 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 4476 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 4477 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 4478 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 4479 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 4480 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4481 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4482 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 4483 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4484 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 4485 } 4486} 4487 4488/// ExpandBitCount - Expand the specified bitcount instruction into operations. 4489/// 4490SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 4491 switch (Opc) { 4492 default: assert(0 && "Cannot expand this yet!"); 4493 case ISD::CTPOP: { 4494 static const uint64_t mask[6] = { 4495 0x5555555555555555ULL, 0x3333333333333333ULL, 4496 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 4497 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 4498 }; 4499 MVT::ValueType VT = Op.getValueType(); 4500 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4501 unsigned len = getSizeInBits(VT); 4502 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4503 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 4504 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 4505 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4506 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 4507 DAG.getNode(ISD::AND, VT, 4508 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 4509 } 4510 return Op; 4511 } 4512 case ISD::CTLZ: { 4513 // for now, we do this: 4514 // x = x | (x >> 1); 4515 // x = x | (x >> 2); 4516 // ... 4517 // x = x | (x >>16); 4518 // x = x | (x >>32); // for 64-bit input 4519 // return popcount(~x); 4520 // 4521 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 4522 MVT::ValueType VT = Op.getValueType(); 4523 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4524 unsigned len = getSizeInBits(VT); 4525 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4526 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4527 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 4528 } 4529 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 4530 return DAG.getNode(ISD::CTPOP, VT, Op); 4531 } 4532 case ISD::CTTZ: { 4533 // for now, we use: { return popcount(~x & (x - 1)); } 4534 // unless the target has ctlz but not ctpop, in which case we use: 4535 // { return 32 - nlz(~x & (x-1)); } 4536 // see also http://www.hackersdelight.org/HDcode/ntz.cc 4537 MVT::ValueType VT = Op.getValueType(); 4538 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 4539 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 4540 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 4541 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 4542 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 4543 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 4544 TLI.isOperationLegal(ISD::CTLZ, VT)) 4545 return DAG.getNode(ISD::SUB, VT, 4546 DAG.getConstant(getSizeInBits(VT), VT), 4547 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 4548 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 4549 } 4550 } 4551} 4552 4553/// ExpandOp - Expand the specified SDOperand into its two component pieces 4554/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 4555/// LegalizeNodes map is filled in for any results that are not expanded, the 4556/// ExpandedNodes map is filled in for any results that are expanded, and the 4557/// Lo/Hi values are returned. 4558void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 4559 MVT::ValueType VT = Op.getValueType(); 4560 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4561 SDNode *Node = Op.Val; 4562 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 4563 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 4564 VT == MVT::Vector) && 4565 "Cannot expand to FP value or to larger int value!"); 4566 4567 // See if we already expanded it. 4568 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 4569 = ExpandedNodes.find(Op); 4570 if (I != ExpandedNodes.end()) { 4571 Lo = I->second.first; 4572 Hi = I->second.second; 4573 return; 4574 } 4575 4576 switch (Node->getOpcode()) { 4577 case ISD::CopyFromReg: 4578 assert(0 && "CopyFromReg must be legal!"); 4579 default: 4580#ifndef NDEBUG 4581 cerr << "NODE: "; Node->dump(); cerr << "\n"; 4582#endif 4583 assert(0 && "Do not know how to expand this operator!"); 4584 abort(); 4585 case ISD::UNDEF: 4586 NVT = TLI.getTypeToExpandTo(VT); 4587 Lo = DAG.getNode(ISD::UNDEF, NVT); 4588 Hi = DAG.getNode(ISD::UNDEF, NVT); 4589 break; 4590 case ISD::Constant: { 4591 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 4592 Lo = DAG.getConstant(Cst, NVT); 4593 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 4594 break; 4595 } 4596 case ISD::ConstantFP: { 4597 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 4598 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 4599 if (getTypeAction(Lo.getValueType()) == Expand) 4600 ExpandOp(Lo, Lo, Hi); 4601 break; 4602 } 4603 case ISD::BUILD_PAIR: 4604 // Return the operands. 4605 Lo = Node->getOperand(0); 4606 Hi = Node->getOperand(1); 4607 break; 4608 4609 case ISD::SIGN_EXTEND_INREG: 4610 ExpandOp(Node->getOperand(0), Lo, Hi); 4611 // sext_inreg the low part if needed. 4612 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 4613 4614 // The high part gets the sign extension from the lo-part. This handles 4615 // things like sextinreg V:i64 from i8. 4616 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4617 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 4618 TLI.getShiftAmountTy())); 4619 break; 4620 4621 case ISD::BSWAP: { 4622 ExpandOp(Node->getOperand(0), Lo, Hi); 4623 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 4624 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 4625 Lo = TempLo; 4626 break; 4627 } 4628 4629 case ISD::CTPOP: 4630 ExpandOp(Node->getOperand(0), Lo, Hi); 4631 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 4632 DAG.getNode(ISD::CTPOP, NVT, Lo), 4633 DAG.getNode(ISD::CTPOP, NVT, Hi)); 4634 Hi = DAG.getConstant(0, NVT); 4635 break; 4636 4637 case ISD::CTLZ: { 4638 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 4639 ExpandOp(Node->getOperand(0), Lo, Hi); 4640 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4641 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 4642 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 4643 ISD::SETNE); 4644 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 4645 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 4646 4647 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 4648 Hi = DAG.getConstant(0, NVT); 4649 break; 4650 } 4651 4652 case ISD::CTTZ: { 4653 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 4654 ExpandOp(Node->getOperand(0), Lo, Hi); 4655 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4656 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 4657 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 4658 ISD::SETNE); 4659 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 4660 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 4661 4662 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 4663 Hi = DAG.getConstant(0, NVT); 4664 break; 4665 } 4666 4667 case ISD::VAARG: { 4668 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 4669 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 4670 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 4671 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 4672 4673 // Remember that we legalized the chain. 4674 Hi = LegalizeOp(Hi); 4675 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 4676 if (!TLI.isLittleEndian()) 4677 std::swap(Lo, Hi); 4678 break; 4679 } 4680 4681 case ISD::LOAD: { 4682 LoadSDNode *LD = cast<LoadSDNode>(Node); 4683 SDOperand Ch = LD->getChain(); // Legalize the chain. 4684 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 4685 ISD::LoadExtType ExtType = LD->getExtensionType(); 4686 4687 if (ExtType == ISD::NON_EXTLOAD) { 4688 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset()); 4689 if (VT == MVT::f32 || VT == MVT::f64) { 4690 // f32->i32 or f64->i64 one to one expansion. 4691 // Remember that we legalized the chain. 4692 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4693 // Recursively expand the new load. 4694 if (getTypeAction(NVT) == Expand) 4695 ExpandOp(Lo, Lo, Hi); 4696 break; 4697 } 4698 4699 // Increment the pointer to the other half. 4700 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 4701 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4702 getIntPtrConstant(IncrementSize)); 4703 // FIXME: This creates a bogus srcvalue! 4704 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset()); 4705 4706 // Build a factor node to remember that this load is independent of the 4707 // other one. 4708 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 4709 Hi.getValue(1)); 4710 4711 // Remember that we legalized the chain. 4712 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 4713 if (!TLI.isLittleEndian()) 4714 std::swap(Lo, Hi); 4715 } else { 4716 MVT::ValueType EVT = LD->getLoadedVT(); 4717 4718 if (VT == MVT::f64 && EVT == MVT::f32) { 4719 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 4720 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 4721 LD->getSrcValueOffset()); 4722 // Remember that we legalized the chain. 4723 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 4724 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 4725 break; 4726 } 4727 4728 if (EVT == NVT) 4729 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 4730 LD->getSrcValueOffset()); 4731 else 4732 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 4733 LD->getSrcValueOffset(), EVT); 4734 4735 // Remember that we legalized the chain. 4736 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4737 4738 if (ExtType == ISD::SEXTLOAD) { 4739 // The high part is obtained by SRA'ing all but one of the bits of the 4740 // lo part. 4741 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4742 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4743 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 4744 } else if (ExtType == ISD::ZEXTLOAD) { 4745 // The high part is just a zero. 4746 Hi = DAG.getConstant(0, NVT); 4747 } else /* if (ExtType == ISD::EXTLOAD) */ { 4748 // The high part is undefined. 4749 Hi = DAG.getNode(ISD::UNDEF, NVT); 4750 } 4751 } 4752 break; 4753 } 4754 case ISD::AND: 4755 case ISD::OR: 4756 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 4757 SDOperand LL, LH, RL, RH; 4758 ExpandOp(Node->getOperand(0), LL, LH); 4759 ExpandOp(Node->getOperand(1), RL, RH); 4760 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 4761 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 4762 break; 4763 } 4764 case ISD::SELECT: { 4765 SDOperand LL, LH, RL, RH; 4766 ExpandOp(Node->getOperand(1), LL, LH); 4767 ExpandOp(Node->getOperand(2), RL, RH); 4768 if (getTypeAction(NVT) == Expand) 4769 NVT = TLI.getTypeToExpandTo(NVT); 4770 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 4771 if (VT != MVT::f32) 4772 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 4773 break; 4774 } 4775 case ISD::SELECT_CC: { 4776 SDOperand TL, TH, FL, FH; 4777 ExpandOp(Node->getOperand(2), TL, TH); 4778 ExpandOp(Node->getOperand(3), FL, FH); 4779 if (getTypeAction(NVT) == Expand) 4780 NVT = TLI.getTypeToExpandTo(NVT); 4781 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4782 Node->getOperand(1), TL, FL, Node->getOperand(4)); 4783 if (VT != MVT::f32) 4784 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4785 Node->getOperand(1), TH, FH, Node->getOperand(4)); 4786 break; 4787 } 4788 case ISD::ANY_EXTEND: 4789 // The low part is any extension of the input (which degenerates to a copy). 4790 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 4791 // The high part is undefined. 4792 Hi = DAG.getNode(ISD::UNDEF, NVT); 4793 break; 4794 case ISD::SIGN_EXTEND: { 4795 // The low part is just a sign extension of the input (which degenerates to 4796 // a copy). 4797 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 4798 4799 // The high part is obtained by SRA'ing all but one of the bits of the lo 4800 // part. 4801 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4802 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4803 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 4804 break; 4805 } 4806 case ISD::ZERO_EXTEND: 4807 // The low part is just a zero extension of the input (which degenerates to 4808 // a copy). 4809 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4810 4811 // The high part is just a zero. 4812 Hi = DAG.getConstant(0, NVT); 4813 break; 4814 4815 case ISD::BIT_CONVERT: { 4816 SDOperand Tmp; 4817 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 4818 // If the target wants to, allow it to lower this itself. 4819 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4820 case Expand: assert(0 && "cannot expand FP!"); 4821 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 4822 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 4823 } 4824 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 4825 } 4826 4827 // f32 / f64 must be expanded to i32 / i64. 4828 if (VT == MVT::f32 || VT == MVT::f64) { 4829 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 4830 if (getTypeAction(NVT) == Expand) 4831 ExpandOp(Lo, Lo, Hi); 4832 break; 4833 } 4834 4835 // If source operand will be expanded to the same type as VT, i.e. 4836 // i64 <- f64, i32 <- f32, expand the source operand instead. 4837 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 4838 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 4839 ExpandOp(Node->getOperand(0), Lo, Hi); 4840 break; 4841 } 4842 4843 // Turn this into a load/store pair by default. 4844 if (Tmp.Val == 0) 4845 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0)); 4846 4847 ExpandOp(Tmp, Lo, Hi); 4848 break; 4849 } 4850 4851 case ISD::READCYCLECOUNTER: 4852 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 4853 TargetLowering::Custom && 4854 "Must custom expand ReadCycleCounter"); 4855 Lo = TLI.LowerOperation(Op, DAG); 4856 assert(Lo.Val && "Node must be custom expanded!"); 4857 Hi = Lo.getValue(1); 4858 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 4859 LegalizeOp(Lo.getValue(2))); 4860 break; 4861 4862 // These operators cannot be expanded directly, emit them as calls to 4863 // library functions. 4864 case ISD::FP_TO_SINT: { 4865 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 4866 SDOperand Op; 4867 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4868 case Expand: assert(0 && "cannot expand FP!"); 4869 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 4870 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 4871 } 4872 4873 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 4874 4875 // Now that the custom expander is done, expand the result, which is still 4876 // VT. 4877 if (Op.Val) { 4878 ExpandOp(Op, Lo, Hi); 4879 break; 4880 } 4881 } 4882 4883 RTLIB::Libcall LC; 4884 if (Node->getOperand(0).getValueType() == MVT::f32) 4885 LC = RTLIB::FPTOSINT_F32_I64; 4886 else 4887 LC = RTLIB::FPTOSINT_F64_I64; 4888 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 4889 false/*sign irrelevant*/, Hi); 4890 break; 4891 } 4892 4893 case ISD::FP_TO_UINT: { 4894 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 4895 SDOperand Op; 4896 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4897 case Expand: assert(0 && "cannot expand FP!"); 4898 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 4899 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 4900 } 4901 4902 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 4903 4904 // Now that the custom expander is done, expand the result. 4905 if (Op.Val) { 4906 ExpandOp(Op, Lo, Hi); 4907 break; 4908 } 4909 } 4910 4911 RTLIB::Libcall LC; 4912 if (Node->getOperand(0).getValueType() == MVT::f32) 4913 LC = RTLIB::FPTOUINT_F32_I64; 4914 else 4915 LC = RTLIB::FPTOUINT_F64_I64; 4916 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 4917 false/*sign irrelevant*/, Hi); 4918 break; 4919 } 4920 4921 case ISD::SHL: { 4922 // If the target wants custom lowering, do so. 4923 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4924 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 4925 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 4926 Op = TLI.LowerOperation(Op, DAG); 4927 if (Op.Val) { 4928 // Now that the custom expander is done, expand the result, which is 4929 // still VT. 4930 ExpandOp(Op, Lo, Hi); 4931 break; 4932 } 4933 } 4934 4935 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 4936 // this X << 1 as X+X. 4937 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 4938 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 4939 TLI.isOperationLegal(ISD::ADDE, NVT)) { 4940 SDOperand LoOps[2], HiOps[3]; 4941 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 4942 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 4943 LoOps[1] = LoOps[0]; 4944 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 4945 4946 HiOps[1] = HiOps[0]; 4947 HiOps[2] = Lo.getValue(1); 4948 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 4949 break; 4950 } 4951 } 4952 4953 // If we can emit an efficient shift operation, do so now. 4954 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4955 break; 4956 4957 // If this target supports SHL_PARTS, use it. 4958 TargetLowering::LegalizeAction Action = 4959 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 4960 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4961 Action == TargetLowering::Custom) { 4962 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4963 break; 4964 } 4965 4966 // Otherwise, emit a libcall. 4967 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 4968 false/*left shift=unsigned*/, Hi); 4969 break; 4970 } 4971 4972 case ISD::SRA: { 4973 // If the target wants custom lowering, do so. 4974 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4975 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 4976 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 4977 Op = TLI.LowerOperation(Op, DAG); 4978 if (Op.Val) { 4979 // Now that the custom expander is done, expand the result, which is 4980 // still VT. 4981 ExpandOp(Op, Lo, Hi); 4982 break; 4983 } 4984 } 4985 4986 // If we can emit an efficient shift operation, do so now. 4987 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4988 break; 4989 4990 // If this target supports SRA_PARTS, use it. 4991 TargetLowering::LegalizeAction Action = 4992 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 4993 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4994 Action == TargetLowering::Custom) { 4995 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4996 break; 4997 } 4998 4999 // Otherwise, emit a libcall. 5000 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 5001 true/*ashr is signed*/, Hi); 5002 break; 5003 } 5004 5005 case ISD::SRL: { 5006 // If the target wants custom lowering, do so. 5007 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5008 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 5009 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 5010 Op = TLI.LowerOperation(Op, DAG); 5011 if (Op.Val) { 5012 // Now that the custom expander is done, expand the result, which is 5013 // still VT. 5014 ExpandOp(Op, Lo, Hi); 5015 break; 5016 } 5017 } 5018 5019 // If we can emit an efficient shift operation, do so now. 5020 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5021 break; 5022 5023 // If this target supports SRL_PARTS, use it. 5024 TargetLowering::LegalizeAction Action = 5025 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 5026 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5027 Action == TargetLowering::Custom) { 5028 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5029 break; 5030 } 5031 5032 // Otherwise, emit a libcall. 5033 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 5034 false/*lshr is unsigned*/, Hi); 5035 break; 5036 } 5037 5038 case ISD::ADD: 5039 case ISD::SUB: { 5040 // If the target wants to custom expand this, let them. 5041 if (TLI.getOperationAction(Node->getOpcode(), VT) == 5042 TargetLowering::Custom) { 5043 Op = TLI.LowerOperation(Op, DAG); 5044 if (Op.Val) { 5045 ExpandOp(Op, Lo, Hi); 5046 break; 5047 } 5048 } 5049 5050 // Expand the subcomponents. 5051 SDOperand LHSL, LHSH, RHSL, RHSH; 5052 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5053 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5054 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5055 SDOperand LoOps[2], HiOps[3]; 5056 LoOps[0] = LHSL; 5057 LoOps[1] = RHSL; 5058 HiOps[0] = LHSH; 5059 HiOps[1] = RHSH; 5060 if (Node->getOpcode() == ISD::ADD) { 5061 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5062 HiOps[2] = Lo.getValue(1); 5063 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5064 } else { 5065 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5066 HiOps[2] = Lo.getValue(1); 5067 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5068 } 5069 break; 5070 } 5071 case ISD::MUL: { 5072 // If the target wants to custom expand this, let them. 5073 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 5074 SDOperand New = TLI.LowerOperation(Op, DAG); 5075 if (New.Val) { 5076 ExpandOp(New, Lo, Hi); 5077 break; 5078 } 5079 } 5080 5081 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 5082 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 5083 if (HasMULHS || HasMULHU) { 5084 SDOperand LL, LH, RL, RH; 5085 ExpandOp(Node->getOperand(0), LL, LH); 5086 ExpandOp(Node->getOperand(1), RL, RH); 5087 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 5088 // FIXME: Move this to the dag combiner. 5089 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 5090 // extended the sign bit of the low half through the upper half, and if so 5091 // emit a MULHS instead of the alternate sequence that is valid for any 5092 // i64 x i64 multiply. 5093 if (HasMULHS && 5094 // is RH an extension of the sign bit of RL? 5095 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 5096 RH.getOperand(1).getOpcode() == ISD::Constant && 5097 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 5098 // is LH an extension of the sign bit of LL? 5099 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 5100 LH.getOperand(1).getOpcode() == ISD::Constant && 5101 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 5102 // Low part: 5103 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5104 // High part: 5105 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 5106 break; 5107 } else if (HasMULHU) { 5108 // Low part: 5109 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5110 5111 // High part: 5112 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 5113 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 5114 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 5115 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 5116 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 5117 break; 5118 } 5119 } 5120 5121 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 5122 false/*sign irrelevant*/, Hi); 5123 break; 5124 } 5125 case ISD::SDIV: 5126 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 5127 break; 5128 case ISD::UDIV: 5129 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 5130 break; 5131 case ISD::SREM: 5132 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 5133 break; 5134 case ISD::UREM: 5135 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 5136 break; 5137 5138 case ISD::FADD: 5139 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5140 ? RTLIB::ADD_F32 : RTLIB::ADD_F64), 5141 Node, false, Hi); 5142 break; 5143 case ISD::FSUB: 5144 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5145 ? RTLIB::SUB_F32 : RTLIB::SUB_F64), 5146 Node, false, Hi); 5147 break; 5148 case ISD::FMUL: 5149 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5150 ? RTLIB::MUL_F32 : RTLIB::MUL_F64), 5151 Node, false, Hi); 5152 break; 5153 case ISD::FDIV: 5154 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5155 ? RTLIB::DIV_F32 : RTLIB::DIV_F64), 5156 Node, false, Hi); 5157 break; 5158 case ISD::FP_EXTEND: 5159 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 5160 break; 5161 case ISD::FP_ROUND: 5162 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 5163 break; 5164 case ISD::FSQRT: 5165 case ISD::FSIN: 5166 case ISD::FCOS: { 5167 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5168 switch(Node->getOpcode()) { 5169 case ISD::FSQRT: 5170 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64; 5171 break; 5172 case ISD::FSIN: 5173 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 5174 break; 5175 case ISD::FCOS: 5176 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64; 5177 break; 5178 default: assert(0 && "Unreachable!"); 5179 } 5180 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 5181 break; 5182 } 5183 case ISD::FABS: { 5184 SDOperand Mask = (VT == MVT::f64) 5185 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 5186 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 5187 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 5188 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5189 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 5190 if (getTypeAction(NVT) == Expand) 5191 ExpandOp(Lo, Lo, Hi); 5192 break; 5193 } 5194 case ISD::FNEG: { 5195 SDOperand Mask = (VT == MVT::f64) 5196 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 5197 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 5198 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 5199 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5200 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 5201 if (getTypeAction(NVT) == Expand) 5202 ExpandOp(Lo, Lo, Hi); 5203 break; 5204 } 5205 case ISD::FCOPYSIGN: { 5206 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 5207 if (getTypeAction(NVT) == Expand) 5208 ExpandOp(Lo, Lo, Hi); 5209 break; 5210 } 5211 case ISD::SINT_TO_FP: 5212 case ISD::UINT_TO_FP: { 5213 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 5214 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 5215 RTLIB::Libcall LC; 5216 if (Node->getOperand(0).getValueType() == MVT::i64) { 5217 if (VT == MVT::f32) 5218 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; 5219 else 5220 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; 5221 } else { 5222 if (VT == MVT::f32) 5223 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 5224 else 5225 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 5226 } 5227 5228 // Promote the operand if needed. 5229 if (getTypeAction(SrcVT) == Promote) { 5230 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 5231 Tmp = isSigned 5232 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 5233 DAG.getValueType(SrcVT)) 5234 : DAG.getZeroExtendInReg(Tmp, SrcVT); 5235 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 5236 } 5237 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi); 5238 break; 5239 } 5240 } 5241 5242 // Make sure the resultant values have been legalized themselves, unless this 5243 // is a type that requires multi-step expansion. 5244 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 5245 Lo = LegalizeOp(Lo); 5246 if (Hi.Val) 5247 // Don't legalize the high part if it is expanded to a single node. 5248 Hi = LegalizeOp(Hi); 5249 } 5250 5251 // Remember in a map if the values will be reused later. 5252 bool isNew = 5253 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 5254 assert(isNew && "Value already expanded?!?"); 5255} 5256 5257/// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 5258/// two smaller values of MVT::Vector type. 5259void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 5260 SDOperand &Hi) { 5261 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!"); 5262 SDNode *Node = Op.Val; 5263 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue(); 5264 assert(NumElements > 1 && "Cannot split a single element vector!"); 5265 unsigned NewNumElts = NumElements/2; 5266 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32); 5267 SDOperand TypeNode = *(Node->op_end()-1); 5268 5269 // See if we already split it. 5270 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5271 = SplitNodes.find(Op); 5272 if (I != SplitNodes.end()) { 5273 Lo = I->second.first; 5274 Hi = I->second.second; 5275 return; 5276 } 5277 5278 switch (Node->getOpcode()) { 5279 default: 5280#ifndef NDEBUG 5281 Node->dump(); 5282#endif 5283 assert(0 && "Unhandled operation in SplitVectorOp!"); 5284 case ISD::VBUILD_VECTOR: { 5285 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 5286 Node->op_begin()+NewNumElts); 5287 LoOps.push_back(NewNumEltsNode); 5288 LoOps.push_back(TypeNode); 5289 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size()); 5290 5291 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts, 5292 Node->op_end()-2); 5293 HiOps.push_back(NewNumEltsNode); 5294 HiOps.push_back(TypeNode); 5295 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size()); 5296 break; 5297 } 5298 case ISD::VADD: 5299 case ISD::VSUB: 5300 case ISD::VMUL: 5301 case ISD::VSDIV: 5302 case ISD::VUDIV: 5303 case ISD::VAND: 5304 case ISD::VOR: 5305 case ISD::VXOR: { 5306 SDOperand LL, LH, RL, RH; 5307 SplitVectorOp(Node->getOperand(0), LL, LH); 5308 SplitVectorOp(Node->getOperand(1), RL, RH); 5309 5310 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, 5311 NewNumEltsNode, TypeNode); 5312 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, 5313 NewNumEltsNode, TypeNode); 5314 break; 5315 } 5316 case ISD::VLOAD: { 5317 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5318 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5319 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 5320 5321 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 5322 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8; 5323 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5324 getIntPtrConstant(IncrementSize)); 5325 // FIXME: This creates a bogus srcvalue! 5326 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 5327 5328 // Build a factor node to remember that this load is independent of the 5329 // other one. 5330 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5331 Hi.getValue(1)); 5332 5333 // Remember that we legalized the chain. 5334 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5335 break; 5336 } 5337 case ISD::VBIT_CONVERT: { 5338 // We know the result is a vector. The input may be either a vector or a 5339 // scalar value. 5340 if (Op.getOperand(0).getValueType() != MVT::Vector) { 5341 // Lower to a store/load. FIXME: this could be improved probably. 5342 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType()); 5343 5344 SDOperand St = DAG.getStore(DAG.getEntryNode(), 5345 Op.getOperand(0), Ptr, NULL, 0); 5346 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 5347 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0)); 5348 SplitVectorOp(St, Lo, Hi); 5349 } else { 5350 // If the input is a vector type, we have to either scalarize it, pack it 5351 // or convert it based on whether the input vector type is legal. 5352 SDNode *InVal = Node->getOperand(0).Val; 5353 unsigned NumElems = 5354 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 5355 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 5356 5357 // If the input is from a single element vector, scalarize the vector, 5358 // then treat like a scalar. 5359 if (NumElems == 1) { 5360 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT); 5361 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar, 5362 Op.getOperand(1), Op.getOperand(2)); 5363 SplitVectorOp(Scalar, Lo, Hi); 5364 } else { 5365 // Split the input vector. 5366 SplitVectorOp(Op.getOperand(0), Lo, Hi); 5367 5368 // Convert each of the pieces now. 5369 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo, 5370 NewNumEltsNode, TypeNode); 5371 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi, 5372 NewNumEltsNode, TypeNode); 5373 } 5374 break; 5375 } 5376 } 5377 } 5378 5379 // Remember in a map if the values will be reused later. 5380 bool isNew = 5381 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 5382 assert(isNew && "Value already expanded?!?"); 5383} 5384 5385 5386/// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 5387/// equivalent operation that returns a scalar (e.g. F32) or packed value 5388/// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right 5389/// type for the result. 5390SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, 5391 MVT::ValueType NewVT) { 5392 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!"); 5393 SDNode *Node = Op.Val; 5394 5395 // See if we already packed it. 5396 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op); 5397 if (I != PackedNodes.end()) return I->second; 5398 5399 SDOperand Result; 5400 switch (Node->getOpcode()) { 5401 default: 5402#ifndef NDEBUG 5403 Node->dump(); cerr << "\n"; 5404#endif 5405 assert(0 && "Unknown vector operation in PackVectorOp!"); 5406 case ISD::VADD: 5407 case ISD::VSUB: 5408 case ISD::VMUL: 5409 case ISD::VSDIV: 5410 case ISD::VUDIV: 5411 case ISD::VAND: 5412 case ISD::VOR: 5413 case ISD::VXOR: 5414 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT), 5415 NewVT, 5416 PackVectorOp(Node->getOperand(0), NewVT), 5417 PackVectorOp(Node->getOperand(1), NewVT)); 5418 break; 5419 case ISD::VLOAD: { 5420 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 5421 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 5422 5423 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 5424 Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset()); 5425 5426 // Remember that we legalized the chain. 5427 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 5428 break; 5429 } 5430 case ISD::VBUILD_VECTOR: 5431 if (Node->getOperand(0).getValueType() == NewVT) { 5432 // Returning a scalar? 5433 Result = Node->getOperand(0); 5434 } else { 5435 // Returning a BUILD_VECTOR? 5436 5437 // If all elements of the build_vector are undefs, return an undef. 5438 bool AllUndef = true; 5439 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i) 5440 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) { 5441 AllUndef = false; 5442 break; 5443 } 5444 if (AllUndef) { 5445 Result = DAG.getNode(ISD::UNDEF, NewVT); 5446 } else { 5447 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(), 5448 Node->getNumOperands()-2); 5449 } 5450 } 5451 break; 5452 case ISD::VINSERT_VECTOR_ELT: 5453 if (!MVT::isVector(NewVT)) { 5454 // Returning a scalar? Must be the inserted element. 5455 Result = Node->getOperand(1); 5456 } else { 5457 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, 5458 PackVectorOp(Node->getOperand(0), NewVT), 5459 Node->getOperand(1), Node->getOperand(2)); 5460 } 5461 break; 5462 case ISD::VVECTOR_SHUFFLE: 5463 if (!MVT::isVector(NewVT)) { 5464 // Returning a scalar? Figure out if it is the LHS or RHS and return it. 5465 SDOperand EltNum = Node->getOperand(2).getOperand(0); 5466 if (cast<ConstantSDNode>(EltNum)->getValue()) 5467 Result = PackVectorOp(Node->getOperand(1), NewVT); 5468 else 5469 Result = PackVectorOp(Node->getOperand(0), NewVT); 5470 } else { 5471 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index 5472 // vector from a VBUILD_VECTOR to a BUILD_VECTOR. 5473 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(), 5474 Node->getOperand(2).Val->op_end()-2); 5475 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size()); 5476 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, 5477 Node->getOperand(2).Val->op_begin(), 5478 Node->getOperand(2).Val->getNumOperands()-2); 5479 5480 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, 5481 PackVectorOp(Node->getOperand(0), NewVT), 5482 PackVectorOp(Node->getOperand(1), NewVT), BV); 5483 } 5484 break; 5485 case ISD::VBIT_CONVERT: 5486 if (Op.getOperand(0).getValueType() != MVT::Vector) 5487 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 5488 else { 5489 // If the input is a vector type, we have to either scalarize it, pack it 5490 // or convert it based on whether the input vector type is legal. 5491 SDNode *InVal = Node->getOperand(0).Val; 5492 unsigned NumElems = 5493 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 5494 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 5495 5496 // Figure out if there is a Packed type corresponding to this Vector 5497 // type. If so, convert to the packed type. 5498 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 5499 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 5500 // Turn this into a bit convert of the packed input. 5501 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 5502 PackVectorOp(Node->getOperand(0), TVT)); 5503 break; 5504 } else if (NumElems == 1) { 5505 // Turn this into a bit convert of the scalar input. 5506 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 5507 PackVectorOp(Node->getOperand(0), EVT)); 5508 break; 5509 } else { 5510 // FIXME: UNIMP! 5511 assert(0 && "Cast from unsupported vector type not implemented yet!"); 5512 } 5513 } 5514 break; 5515 case ISD::VSELECT: 5516 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 5517 PackVectorOp(Op.getOperand(1), NewVT), 5518 PackVectorOp(Op.getOperand(2), NewVT)); 5519 break; 5520 } 5521 5522 if (TLI.isTypeLegal(NewVT)) 5523 Result = LegalizeOp(Result); 5524 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second; 5525 assert(isNew && "Value already packed?"); 5526 return Result; 5527} 5528 5529 5530// SelectionDAG::Legalize - This is the entry point for the file. 5531// 5532void SelectionDAG::Legalize() { 5533 if (ViewLegalizeDAGs) viewGraph(); 5534 5535 /// run - This is the main entry point to this class. 5536 /// 5537 SelectionDAGLegalize(*this).LegalizeDAG(); 5538} 5539 5540