LegalizeDAG.cpp revision 5872a361d5332fddcdb89c6df684243c19a75f88
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/Target/TargetFrameInfo.h" 20#include "llvm/Target/TargetLowering.h" 21#include "llvm/Target/TargetData.h" 22#include "llvm/Target/TargetMachine.h" 23#include "llvm/Target/TargetOptions.h" 24#include "llvm/CallingConv.h" 25#include "llvm/Constants.h" 26#include "llvm/DerivedTypes.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Compiler.h" 29#include "llvm/Support/MathExtras.h" 30#include "llvm/ADT/DenseMap.h" 31#include "llvm/ADT/SmallVector.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include <map> 34using namespace llvm; 35 36#ifndef NDEBUG 37static cl::opt<bool> 38ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 39 cl::desc("Pop up a window to show dags before legalize")); 40#else 41static const bool ViewLegalizeDAGs = 0; 42#endif 43 44//===----------------------------------------------------------------------===// 45/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 46/// hacks on it until the target machine can handle it. This involves 47/// eliminating value sizes the machine cannot handle (promoting small sizes to 48/// large sizes or splitting up large values into small values) as well as 49/// eliminating operations the machine cannot handle. 50/// 51/// This code also does a small amount of optimization and recognition of idioms 52/// as part of its processing. For example, if a target does not support a 53/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 54/// will attempt merge setcc and brc instructions into brcc's. 55/// 56namespace { 57class VISIBILITY_HIDDEN SelectionDAGLegalize { 58 TargetLowering &TLI; 59 SelectionDAG &DAG; 60 61 // Libcall insertion helpers. 62 63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 64 /// legalized. We use this to ensure that calls are properly serialized 65 /// against each other, including inserted libcalls. 66 SDOperand LastCALLSEQ_END; 67 68 /// IsLegalizingCall - This member is used *only* for purposes of providing 69 /// helpful assertions that a libcall isn't created while another call is 70 /// being legalized (which could lead to non-serialized call sequences). 71 bool IsLegalizingCall; 72 73 enum LegalizeAction { 74 Legal, // The target natively supports this operation. 75 Promote, // This operation should be executed in a larger type. 76 Expand // Try to expand this to other ops, otherwise use a libcall. 77 }; 78 79 /// ValueTypeActions - This is a bitvector that contains two bits for each 80 /// value type, where the two bits correspond to the LegalizeAction enum. 81 /// This can be queried with "getTypeAction(VT)". 82 TargetLowering::ValueTypeActionImpl ValueTypeActions; 83 84 /// LegalizedNodes - For nodes that are of legal width, and that have more 85 /// than one use, this map indicates what regularized operand to use. This 86 /// allows us to avoid legalizing the same thing more than once. 87 DenseMap<SDOperand, SDOperand> LegalizedNodes; 88 89 /// PromotedNodes - For nodes that are below legal width, and that have more 90 /// than one use, this map indicates what promoted value to use. This allows 91 /// us to avoid promoting the same thing more than once. 92 DenseMap<SDOperand, SDOperand> PromotedNodes; 93 94 /// ExpandedNodes - For nodes that need to be expanded this map indicates 95 /// which which operands are the expanded version of the input. This allows 96 /// us to avoid expanding the same node more than once. 97 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 98 99 /// SplitNodes - For vector nodes that need to be split, this map indicates 100 /// which which operands are the split version of the input. This allows us 101 /// to avoid splitting the same node more than once. 102 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 103 104 /// ScalarizedNodes - For nodes that need to be converted from vector types to 105 /// scalar types, this contains the mapping of ones we have already 106 /// processed to the result. 107 std::map<SDOperand, SDOperand> ScalarizedNodes; 108 109 void AddLegalizedOperand(SDOperand From, SDOperand To) { 110 LegalizedNodes.insert(std::make_pair(From, To)); 111 // If someone requests legalization of the new node, return itself. 112 if (From != To) 113 LegalizedNodes.insert(std::make_pair(To, To)); 114 } 115 void AddPromotedOperand(SDOperand From, SDOperand To) { 116 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 117 assert(isNew && "Got into the map somehow?"); 118 // If someone requests legalization of the new node, return itself. 119 LegalizedNodes.insert(std::make_pair(To, To)); 120 } 121 122public: 123 124 SelectionDAGLegalize(SelectionDAG &DAG); 125 126 /// getTypeAction - Return how we should legalize values of this type, either 127 /// it is already legal or we need to expand it into multiple registers of 128 /// smaller integer type, or we need to promote it to a larger type. 129 LegalizeAction getTypeAction(MVT::ValueType VT) const { 130 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 131 } 132 133 /// isTypeLegal - Return true if this type is legal on this target. 134 /// 135 bool isTypeLegal(MVT::ValueType VT) const { 136 return getTypeAction(VT) == Legal; 137 } 138 139 void LegalizeDAG(); 140 141private: 142 /// HandleOp - Legalize, Promote, or Expand the specified operand as 143 /// appropriate for its type. 144 void HandleOp(SDOperand Op); 145 146 /// LegalizeOp - We know that the specified value has a legal type. 147 /// Recursively ensure that the operands have legal types, then return the 148 /// result. 149 SDOperand LegalizeOp(SDOperand O); 150 151 /// UnrollVectorOp - We know that the given vector has a legal type, however 152 /// the operation it performs is not legal and is an operation that we have 153 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 154 /// operating on each element individually. 155 SDOperand UnrollVectorOp(SDOperand O); 156 157 /// PromoteOp - Given an operation that produces a value in an invalid type, 158 /// promote it to compute the value into a larger type. The produced value 159 /// will have the correct bits for the low portion of the register, but no 160 /// guarantee is made about the top bits: it may be zero, sign-extended, or 161 /// garbage. 162 SDOperand PromoteOp(SDOperand O); 163 164 /// ExpandOp - Expand the specified SDOperand into its two component pieces 165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 166 /// the LegalizeNodes map is filled in for any results that are not expanded, 167 /// the ExpandedNodes map is filled in for any results that are expanded, and 168 /// the Lo/Hi values are returned. This applies to integer types and Vector 169 /// types. 170 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 171 172 /// SplitVectorOp - Given an operand of vector type, break it down into 173 /// two smaller values. 174 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 175 176 /// ScalarizeVectorOp - Given an operand of single-element vector type 177 /// (e.g. v1f32), convert it into the equivalent operation that returns a 178 /// scalar (e.g. f32) value. 179 SDOperand ScalarizeVectorOp(SDOperand O); 180 181 /// isShuffleLegal - Return true if a vector shuffle is legal with the 182 /// specified mask and type. Targets can specify exactly which masks they 183 /// support and the code generator is tasked with not creating illegal masks. 184 /// 185 /// Note that this will also return true for shuffles that are promoted to a 186 /// different type. 187 /// 188 /// If this is a legal shuffle, this method returns the (possibly promoted) 189 /// build_vector Mask. If it's not a legal shuffle, it returns null. 190 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 191 192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 194 195 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 196 197 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 198 SDOperand &Hi); 199 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 200 SDOperand Source); 201 202 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT, 203 MVT::ValueType DestVT); 204 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 205 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 206 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 207 SDOperand LegalOp, 208 MVT::ValueType DestVT); 209 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 210 bool isSigned); 211 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 212 bool isSigned); 213 214 SDOperand ExpandBSWAP(SDOperand Op); 215 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 216 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 217 SDOperand &Lo, SDOperand &Hi); 218 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 219 SDOperand &Lo, SDOperand &Hi); 220 221 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 222 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 223}; 224} 225 226/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 227/// specified mask and type. Targets can specify exactly which masks they 228/// support and the code generator is tasked with not creating illegal masks. 229/// 230/// Note that this will also return true for shuffles that are promoted to a 231/// different type. 232SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 233 SDOperand Mask) const { 234 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 235 default: return 0; 236 case TargetLowering::Legal: 237 case TargetLowering::Custom: 238 break; 239 case TargetLowering::Promote: { 240 // If this is promoted to a different type, convert the shuffle mask and 241 // ask if it is legal in the promoted type! 242 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 243 244 // If we changed # elements, change the shuffle mask. 245 unsigned NumEltsGrowth = 246 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 247 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 248 if (NumEltsGrowth > 1) { 249 // Renumber the elements. 250 SmallVector<SDOperand, 8> Ops; 251 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 252 SDOperand InOp = Mask.getOperand(i); 253 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 254 if (InOp.getOpcode() == ISD::UNDEF) 255 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 256 else { 257 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 258 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 259 } 260 } 261 } 262 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 263 } 264 VT = NVT; 265 break; 266 } 267 } 268 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 269} 270 271SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 272 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 273 ValueTypeActions(TLI.getValueTypeActions()) { 274 assert(MVT::LAST_VALUETYPE <= 32 && 275 "Too many value types for ValueTypeActions to hold!"); 276} 277 278/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 279/// contains all of a nodes operands before it contains the node. 280static void ComputeTopDownOrdering(SelectionDAG &DAG, 281 SmallVector<SDNode*, 64> &Order) { 282 283 DenseMap<SDNode*, unsigned> Visited; 284 std::vector<SDNode*> Worklist; 285 Worklist.reserve(128); 286 287 // Compute ordering from all of the leaves in the graphs, those (like the 288 // entry node) that have no operands. 289 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 290 E = DAG.allnodes_end(); I != E; ++I) { 291 if (I->getNumOperands() == 0) { 292 Visited[I] = 0 - 1U; 293 Worklist.push_back(I); 294 } 295 } 296 297 while (!Worklist.empty()) { 298 SDNode *N = Worklist.back(); 299 Worklist.pop_back(); 300 301 if (++Visited[N] != N->getNumOperands()) 302 continue; // Haven't visited all operands yet 303 304 Order.push_back(N); 305 306 // Now that we have N in, add anything that uses it if all of their operands 307 // are now done. 308 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 309 UI != E; ++UI) 310 Worklist.push_back(*UI); 311 } 312 313 assert(Order.size() == Visited.size() && 314 Order.size() == 315 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 316 "Error: DAG is cyclic!"); 317} 318 319 320void SelectionDAGLegalize::LegalizeDAG() { 321 LastCALLSEQ_END = DAG.getEntryNode(); 322 IsLegalizingCall = false; 323 324 // The legalize process is inherently a bottom-up recursive process (users 325 // legalize their uses before themselves). Given infinite stack space, we 326 // could just start legalizing on the root and traverse the whole graph. In 327 // practice however, this causes us to run out of stack space on large basic 328 // blocks. To avoid this problem, compute an ordering of the nodes where each 329 // node is only legalized after all of its operands are legalized. 330 SmallVector<SDNode*, 64> Order; 331 ComputeTopDownOrdering(DAG, Order); 332 333 for (unsigned i = 0, e = Order.size(); i != e; ++i) 334 HandleOp(SDOperand(Order[i], 0)); 335 336 // Finally, it's possible the root changed. Get the new root. 337 SDOperand OldRoot = DAG.getRoot(); 338 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 339 DAG.setRoot(LegalizedNodes[OldRoot]); 340 341 ExpandedNodes.clear(); 342 LegalizedNodes.clear(); 343 PromotedNodes.clear(); 344 SplitNodes.clear(); 345 ScalarizedNodes.clear(); 346 347 // Remove dead nodes now. 348 DAG.RemoveDeadNodes(); 349} 350 351 352/// FindCallEndFromCallStart - Given a chained node that is part of a call 353/// sequence, find the CALLSEQ_END node that terminates the call sequence. 354static SDNode *FindCallEndFromCallStart(SDNode *Node) { 355 if (Node->getOpcode() == ISD::CALLSEQ_END) 356 return Node; 357 if (Node->use_empty()) 358 return 0; // No CallSeqEnd 359 360 // The chain is usually at the end. 361 SDOperand TheChain(Node, Node->getNumValues()-1); 362 if (TheChain.getValueType() != MVT::Other) { 363 // Sometimes it's at the beginning. 364 TheChain = SDOperand(Node, 0); 365 if (TheChain.getValueType() != MVT::Other) { 366 // Otherwise, hunt for it. 367 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 368 if (Node->getValueType(i) == MVT::Other) { 369 TheChain = SDOperand(Node, i); 370 break; 371 } 372 373 // Otherwise, we walked into a node without a chain. 374 if (TheChain.getValueType() != MVT::Other) 375 return 0; 376 } 377 } 378 379 for (SDNode::use_iterator UI = Node->use_begin(), 380 E = Node->use_end(); UI != E; ++UI) { 381 382 // Make sure to only follow users of our token chain. 383 SDNode *User = *UI; 384 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 385 if (User->getOperand(i) == TheChain) 386 if (SDNode *Result = FindCallEndFromCallStart(User)) 387 return Result; 388 } 389 return 0; 390} 391 392/// FindCallStartFromCallEnd - Given a chained node that is part of a call 393/// sequence, find the CALLSEQ_START node that initiates the call sequence. 394static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 395 assert(Node && "Didn't find callseq_start for a call??"); 396 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 397 398 assert(Node->getOperand(0).getValueType() == MVT::Other && 399 "Node doesn't have a token chain argument!"); 400 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 401} 402 403/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 404/// see if any uses can reach Dest. If no dest operands can get to dest, 405/// legalize them, legalize ourself, and return false, otherwise, return true. 406/// 407/// Keep track of the nodes we fine that actually do lead to Dest in 408/// NodesLeadingTo. This avoids retraversing them exponential number of times. 409/// 410bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 411 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 412 if (N == Dest) return true; // N certainly leads to Dest :) 413 414 // If we've already processed this node and it does lead to Dest, there is no 415 // need to reprocess it. 416 if (NodesLeadingTo.count(N)) return true; 417 418 // If the first result of this node has been already legalized, then it cannot 419 // reach N. 420 switch (getTypeAction(N->getValueType(0))) { 421 case Legal: 422 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 423 break; 424 case Promote: 425 if (PromotedNodes.count(SDOperand(N, 0))) return false; 426 break; 427 case Expand: 428 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 429 break; 430 } 431 432 // Okay, this node has not already been legalized. Check and legalize all 433 // operands. If none lead to Dest, then we can legalize this node. 434 bool OperandsLeadToDest = false; 435 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 436 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 437 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 438 439 if (OperandsLeadToDest) { 440 NodesLeadingTo.insert(N); 441 return true; 442 } 443 444 // Okay, this node looks safe, legalize it and return false. 445 HandleOp(SDOperand(N, 0)); 446 return false; 447} 448 449/// HandleOp - Legalize, Promote, or Expand the specified operand as 450/// appropriate for its type. 451void SelectionDAGLegalize::HandleOp(SDOperand Op) { 452 MVT::ValueType VT = Op.getValueType(); 453 switch (getTypeAction(VT)) { 454 default: assert(0 && "Bad type action!"); 455 case Legal: (void)LegalizeOp(Op); break; 456 case Promote: (void)PromoteOp(Op); break; 457 case Expand: 458 if (!MVT::isVector(VT)) { 459 // If this is an illegal scalar, expand it into its two component 460 // pieces. 461 SDOperand X, Y; 462 if (Op.getOpcode() == ISD::TargetConstant) 463 break; // Allow illegal target nodes. 464 ExpandOp(Op, X, Y); 465 } else if (MVT::getVectorNumElements(VT) == 1) { 466 // If this is an illegal single element vector, convert it to a 467 // scalar operation. 468 (void)ScalarizeVectorOp(Op); 469 } else { 470 // Otherwise, this is an illegal multiple element vector. 471 // Split it in half and legalize both parts. 472 SDOperand X, Y; 473 SplitVectorOp(Op, X, Y); 474 } 475 break; 476 } 477} 478 479/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 480/// a load from the constant pool. 481static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 482 SelectionDAG &DAG, TargetLowering &TLI) { 483 bool Extend = false; 484 485 // If a FP immediate is precise when represented as a float and if the 486 // target can do an extending load from float to double, we put it into 487 // the constant pool as a float, even if it's is statically typed as a 488 // double. 489 MVT::ValueType VT = CFP->getValueType(0); 490 bool isDouble = VT == MVT::f64; 491 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT), 492 CFP->getValueAPF()); 493 if (!UseCP) { 494 if (VT!=MVT::f64 && VT!=MVT::f32) 495 assert(0 && "Invalid type expansion"); 496 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(), 497 isDouble ? MVT::i64 : MVT::i32); 498 } 499 500 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) && 501 // Only do this if the target has a native EXTLOAD instruction from f32. 502 // Do not try to be clever about long doubles (so far) 503 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 504 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); 505 VT = MVT::f32; 506 Extend = true; 507 } 508 509 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 510 if (Extend) { 511 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 512 CPIdx, NULL, 0, MVT::f32); 513 } else { 514 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 515 } 516} 517 518 519/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 520/// operations. 521static 522SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 523 SelectionDAG &DAG, TargetLowering &TLI) { 524 MVT::ValueType VT = Node->getValueType(0); 525 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 526 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 527 "fcopysign expansion only supported for f32 and f64"); 528 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 529 530 // First get the sign bit of second operand. 531 SDOperand Mask1 = (SrcVT == MVT::f64) 532 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 533 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 534 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 535 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 536 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 537 // Shift right or sign-extend it if the two operands have different types. 538 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 539 if (SizeDiff > 0) { 540 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 541 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 542 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 543 } else if (SizeDiff < 0) 544 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 545 546 // Clear the sign bit of first operand. 547 SDOperand Mask2 = (VT == MVT::f64) 548 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 549 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 550 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 551 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 552 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 553 554 // Or the value with the sign bit. 555 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 556 return Result; 557} 558 559/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 560static 561SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 562 TargetLowering &TLI) { 563 SDOperand Chain = ST->getChain(); 564 SDOperand Ptr = ST->getBasePtr(); 565 SDOperand Val = ST->getValue(); 566 MVT::ValueType VT = Val.getValueType(); 567 int Alignment = ST->getAlignment(); 568 int SVOffset = ST->getSrcValueOffset(); 569 if (MVT::isFloatingPoint(ST->getStoredVT())) { 570 // Expand to a bitconvert of the value to the integer type of the 571 // same size, then a (misaligned) int store. 572 MVT::ValueType intVT; 573 if (VT==MVT::f64) 574 intVT = MVT::i64; 575 else if (VT==MVT::f32) 576 intVT = MVT::i32; 577 else 578 assert(0 && "Unaligned load of unsupported floating point type"); 579 580 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 581 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 582 SVOffset, ST->isVolatile(), Alignment); 583 } 584 assert(MVT::isInteger(ST->getStoredVT()) && 585 "Unaligned store of unknown type."); 586 // Get the half-size VT 587 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1; 588 int NumBits = MVT::getSizeInBits(NewStoredVT); 589 int IncrementSize = NumBits / 8; 590 591 // Divide the stored value in two parts. 592 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 593 SDOperand Lo = Val; 594 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 595 596 // Store the two parts 597 SDOperand Store1, Store2; 598 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 599 ST->getSrcValue(), SVOffset, NewStoredVT, 600 ST->isVolatile(), Alignment); 601 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 602 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 603 Alignment = MinAlign(Alignment, IncrementSize); 604 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 605 ST->getSrcValue(), SVOffset + IncrementSize, 606 NewStoredVT, ST->isVolatile(), Alignment); 607 608 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 609} 610 611/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 612static 613SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 614 TargetLowering &TLI) { 615 int SVOffset = LD->getSrcValueOffset(); 616 SDOperand Chain = LD->getChain(); 617 SDOperand Ptr = LD->getBasePtr(); 618 MVT::ValueType VT = LD->getValueType(0); 619 MVT::ValueType LoadedVT = LD->getLoadedVT(); 620 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) { 621 // Expand to a (misaligned) integer load of the same size, 622 // then bitconvert to floating point. 623 MVT::ValueType intVT; 624 if (LoadedVT == MVT::f64) 625 intVT = MVT::i64; 626 else if (LoadedVT == MVT::f32) 627 intVT = MVT::i32; 628 else 629 assert(0 && "Unaligned load of unsupported floating point type"); 630 631 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 632 SVOffset, LD->isVolatile(), 633 LD->getAlignment()); 634 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 635 if (LoadedVT != VT) 636 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 637 638 SDOperand Ops[] = { Result, Chain }; 639 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 640 Ops, 2); 641 } 642 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) && 643 "Unaligned load of unsupported type."); 644 645 // Compute the new VT that is half the size of the old one. We either have an 646 // integer MVT or we have a vector MVT. 647 unsigned NumBits = MVT::getSizeInBits(LoadedVT); 648 MVT::ValueType NewLoadedVT; 649 if (!MVT::isVector(LoadedVT)) { 650 NewLoadedVT = MVT::getIntegerType(NumBits/2); 651 } else { 652 // FIXME: This is not right for <1 x anything> it is also not right for 653 // non-power-of-two vectors. 654 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT), 655 MVT::getVectorNumElements(LoadedVT)/2); 656 } 657 NumBits >>= 1; 658 659 unsigned Alignment = LD->getAlignment(); 660 unsigned IncrementSize = NumBits / 8; 661 ISD::LoadExtType HiExtType = LD->getExtensionType(); 662 663 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 664 if (HiExtType == ISD::NON_EXTLOAD) 665 HiExtType = ISD::ZEXTLOAD; 666 667 // Load the value in two parts 668 SDOperand Lo, Hi; 669 if (TLI.isLittleEndian()) { 670 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 671 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 672 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 673 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 674 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 675 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 676 MinAlign(Alignment, IncrementSize)); 677 } else { 678 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 679 NewLoadedVT,LD->isVolatile(), Alignment); 680 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 681 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 682 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 683 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 684 MinAlign(Alignment, IncrementSize)); 685 } 686 687 // aggregate the two parts 688 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 689 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 690 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 691 692 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 693 Hi.getValue(1)); 694 695 SDOperand Ops[] = { Result, TF }; 696 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 697} 698 699/// UnrollVectorOp - We know that the given vector has a legal type, however 700/// the operation it performs is not legal and is an operation that we have 701/// no way of lowering. "Unroll" the vector, splitting out the scalars and 702/// operating on each element individually. 703SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { 704 MVT::ValueType VT = Op.getValueType(); 705 assert(isTypeLegal(VT) && 706 "Caller should expand or promote operands that are not legal!"); 707 assert(Op.Val->getNumValues() == 1 && 708 "Can't unroll a vector with multiple results!"); 709 unsigned NE = MVT::getVectorNumElements(VT); 710 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 711 712 SmallVector<SDOperand, 8> Scalars; 713 SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); 714 for (unsigned i = 0; i != NE; ++i) { 715 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 716 SDOperand Operand = Op.getOperand(j); 717 MVT::ValueType OperandVT = Operand.getValueType(); 718 if (MVT::isVector(OperandVT)) { 719 // A vector operand; extract a single element. 720 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT); 721 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 722 OperandEltVT, 723 Operand, 724 DAG.getConstant(i, MVT::i32)); 725 } else { 726 // A scalar operand; just use it as is. 727 Operands[j] = Operand; 728 } 729 } 730 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 731 &Operands[0], Operands.size())); 732 } 733 734 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 735} 736 737/// GetFPLibCall - Return the right libcall for the given floating point type. 738static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT, 739 RTLIB::Libcall Call_F32, 740 RTLIB::Libcall Call_F64, 741 RTLIB::Libcall Call_F80, 742 RTLIB::Libcall Call_PPCF128) { 743 return 744 VT == MVT::f32 ? Call_F32 : 745 VT == MVT::f64 ? Call_F64 : 746 VT == MVT::f80 ? Call_F80 : 747 VT == MVT::ppcf128 ? Call_PPCF128 : 748 RTLIB::UNKNOWN_LIBCALL; 749} 750 751/// LegalizeOp - We know that the specified value has a legal type, and 752/// that its operands are legal. Now ensure that the operation itself 753/// is legal, recursively ensuring that the operands' operations remain 754/// legal. 755SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 756 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 757 return Op; 758 759 assert(isTypeLegal(Op.getValueType()) && 760 "Caller should expand or promote operands that are not legal!"); 761 SDNode *Node = Op.Val; 762 763 // If this operation defines any values that cannot be represented in a 764 // register on this target, make sure to expand or promote them. 765 if (Node->getNumValues() > 1) { 766 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 767 if (getTypeAction(Node->getValueType(i)) != Legal) { 768 HandleOp(Op.getValue(i)); 769 assert(LegalizedNodes.count(Op) && 770 "Handling didn't add legal operands!"); 771 return LegalizedNodes[Op]; 772 } 773 } 774 775 // Note that LegalizeOp may be reentered even from single-use nodes, which 776 // means that we always must cache transformed nodes. 777 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 778 if (I != LegalizedNodes.end()) return I->second; 779 780 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 781 SDOperand Result = Op; 782 bool isCustom = false; 783 784 switch (Node->getOpcode()) { 785 case ISD::FrameIndex: 786 case ISD::EntryToken: 787 case ISD::Register: 788 case ISD::BasicBlock: 789 case ISD::TargetFrameIndex: 790 case ISD::TargetJumpTable: 791 case ISD::TargetConstant: 792 case ISD::TargetConstantFP: 793 case ISD::TargetConstantPool: 794 case ISD::TargetGlobalAddress: 795 case ISD::TargetGlobalTLSAddress: 796 case ISD::TargetExternalSymbol: 797 case ISD::VALUETYPE: 798 case ISD::SRCVALUE: 799 case ISD::STRING: 800 case ISD::CONDCODE: 801 // Primitives must all be legal. 802 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 803 "This must be legal!"); 804 break; 805 default: 806 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 807 // If this is a target node, legalize it by legalizing the operands then 808 // passing it through. 809 SmallVector<SDOperand, 8> Ops; 810 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 811 Ops.push_back(LegalizeOp(Node->getOperand(i))); 812 813 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 814 815 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 816 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 817 return Result.getValue(Op.ResNo); 818 } 819 // Otherwise this is an unhandled builtin node. splat. 820#ifndef NDEBUG 821 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 822#endif 823 assert(0 && "Do not know how to legalize this operator!"); 824 abort(); 825 case ISD::GLOBAL_OFFSET_TABLE: 826 case ISD::GlobalAddress: 827 case ISD::GlobalTLSAddress: 828 case ISD::ExternalSymbol: 829 case ISD::ConstantPool: 830 case ISD::JumpTable: // Nothing to do. 831 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 832 default: assert(0 && "This action is not supported yet!"); 833 case TargetLowering::Custom: 834 Tmp1 = TLI.LowerOperation(Op, DAG); 835 if (Tmp1.Val) Result = Tmp1; 836 // FALLTHROUGH if the target doesn't want to lower this op after all. 837 case TargetLowering::Legal: 838 break; 839 } 840 break; 841 case ISD::FRAMEADDR: 842 case ISD::RETURNADDR: 843 // The only option for these nodes is to custom lower them. If the target 844 // does not custom lower them, then return zero. 845 Tmp1 = TLI.LowerOperation(Op, DAG); 846 if (Tmp1.Val) 847 Result = Tmp1; 848 else 849 Result = DAG.getConstant(0, TLI.getPointerTy()); 850 break; 851 case ISD::FRAME_TO_ARGS_OFFSET: { 852 MVT::ValueType VT = Node->getValueType(0); 853 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 854 default: assert(0 && "This action is not supported yet!"); 855 case TargetLowering::Custom: 856 Result = TLI.LowerOperation(Op, DAG); 857 if (Result.Val) break; 858 // Fall Thru 859 case TargetLowering::Legal: 860 Result = DAG.getConstant(0, VT); 861 break; 862 } 863 } 864 break; 865 case ISD::EXCEPTIONADDR: { 866 Tmp1 = LegalizeOp(Node->getOperand(0)); 867 MVT::ValueType VT = Node->getValueType(0); 868 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 869 default: assert(0 && "This action is not supported yet!"); 870 case TargetLowering::Expand: { 871 unsigned Reg = TLI.getExceptionAddressRegister(); 872 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 873 } 874 break; 875 case TargetLowering::Custom: 876 Result = TLI.LowerOperation(Op, DAG); 877 if (Result.Val) break; 878 // Fall Thru 879 case TargetLowering::Legal: { 880 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 881 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 882 Ops, 2); 883 break; 884 } 885 } 886 } 887 if (Result.Val->getNumValues() == 1) break; 888 889 assert(Result.Val->getNumValues() == 2 && 890 "Cannot return more than two values!"); 891 892 // Since we produced two values, make sure to remember that we 893 // legalized both of them. 894 Tmp1 = LegalizeOp(Result); 895 Tmp2 = LegalizeOp(Result.getValue(1)); 896 AddLegalizedOperand(Op.getValue(0), Tmp1); 897 AddLegalizedOperand(Op.getValue(1), Tmp2); 898 return Op.ResNo ? Tmp2 : Tmp1; 899 case ISD::EHSELECTION: { 900 Tmp1 = LegalizeOp(Node->getOperand(0)); 901 Tmp2 = LegalizeOp(Node->getOperand(1)); 902 MVT::ValueType VT = Node->getValueType(0); 903 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 904 default: assert(0 && "This action is not supported yet!"); 905 case TargetLowering::Expand: { 906 unsigned Reg = TLI.getExceptionSelectorRegister(); 907 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 908 } 909 break; 910 case TargetLowering::Custom: 911 Result = TLI.LowerOperation(Op, DAG); 912 if (Result.Val) break; 913 // Fall Thru 914 case TargetLowering::Legal: { 915 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 916 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 917 Ops, 2); 918 break; 919 } 920 } 921 } 922 if (Result.Val->getNumValues() == 1) break; 923 924 assert(Result.Val->getNumValues() == 2 && 925 "Cannot return more than two values!"); 926 927 // Since we produced two values, make sure to remember that we 928 // legalized both of them. 929 Tmp1 = LegalizeOp(Result); 930 Tmp2 = LegalizeOp(Result.getValue(1)); 931 AddLegalizedOperand(Op.getValue(0), Tmp1); 932 AddLegalizedOperand(Op.getValue(1), Tmp2); 933 return Op.ResNo ? Tmp2 : Tmp1; 934 case ISD::EH_RETURN: { 935 MVT::ValueType VT = Node->getValueType(0); 936 // The only "good" option for this node is to custom lower it. 937 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 938 default: assert(0 && "This action is not supported at all!"); 939 case TargetLowering::Custom: 940 Result = TLI.LowerOperation(Op, DAG); 941 if (Result.Val) break; 942 // Fall Thru 943 case TargetLowering::Legal: 944 // Target does not know, how to lower this, lower to noop 945 Result = LegalizeOp(Node->getOperand(0)); 946 break; 947 } 948 } 949 break; 950 case ISD::AssertSext: 951 case ISD::AssertZext: 952 Tmp1 = LegalizeOp(Node->getOperand(0)); 953 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 954 break; 955 case ISD::MERGE_VALUES: 956 // Legalize eliminates MERGE_VALUES nodes. 957 Result = Node->getOperand(Op.ResNo); 958 break; 959 case ISD::CopyFromReg: 960 Tmp1 = LegalizeOp(Node->getOperand(0)); 961 Result = Op.getValue(0); 962 if (Node->getNumValues() == 2) { 963 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 964 } else { 965 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 966 if (Node->getNumOperands() == 3) { 967 Tmp2 = LegalizeOp(Node->getOperand(2)); 968 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 969 } else { 970 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 971 } 972 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 973 } 974 // Since CopyFromReg produces two values, make sure to remember that we 975 // legalized both of them. 976 AddLegalizedOperand(Op.getValue(0), Result); 977 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 978 return Result.getValue(Op.ResNo); 979 case ISD::UNDEF: { 980 MVT::ValueType VT = Op.getValueType(); 981 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 982 default: assert(0 && "This action is not supported yet!"); 983 case TargetLowering::Expand: 984 if (MVT::isInteger(VT)) 985 Result = DAG.getConstant(0, VT); 986 else if (MVT::isFloatingPoint(VT)) 987 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)), 988 VT); 989 else 990 assert(0 && "Unknown value type!"); 991 break; 992 case TargetLowering::Legal: 993 break; 994 } 995 break; 996 } 997 998 case ISD::INTRINSIC_W_CHAIN: 999 case ISD::INTRINSIC_WO_CHAIN: 1000 case ISD::INTRINSIC_VOID: { 1001 SmallVector<SDOperand, 8> Ops; 1002 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1003 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1004 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1005 1006 // Allow the target to custom lower its intrinsics if it wants to. 1007 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1008 TargetLowering::Custom) { 1009 Tmp3 = TLI.LowerOperation(Result, DAG); 1010 if (Tmp3.Val) Result = Tmp3; 1011 } 1012 1013 if (Result.Val->getNumValues() == 1) break; 1014 1015 // Must have return value and chain result. 1016 assert(Result.Val->getNumValues() == 2 && 1017 "Cannot return more than two values!"); 1018 1019 // Since loads produce two values, make sure to remember that we 1020 // legalized both of them. 1021 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1022 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1023 return Result.getValue(Op.ResNo); 1024 } 1025 1026 case ISD::LOCATION: 1027 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 1028 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1029 1030 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 1031 case TargetLowering::Promote: 1032 default: assert(0 && "This action is not supported yet!"); 1033 case TargetLowering::Expand: { 1034 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1035 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1036 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 1037 1038 if (MMI && (useDEBUG_LOC || useLABEL)) { 1039 const std::string &FName = 1040 cast<StringSDNode>(Node->getOperand(3))->getValue(); 1041 const std::string &DirName = 1042 cast<StringSDNode>(Node->getOperand(4))->getValue(); 1043 unsigned SrcFile = MMI->RecordSource(DirName, FName); 1044 1045 SmallVector<SDOperand, 8> Ops; 1046 Ops.push_back(Tmp1); // chain 1047 SDOperand LineOp = Node->getOperand(1); 1048 SDOperand ColOp = Node->getOperand(2); 1049 1050 if (useDEBUG_LOC) { 1051 Ops.push_back(LineOp); // line # 1052 Ops.push_back(ColOp); // col # 1053 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 1054 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 1055 } else { 1056 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 1057 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 1058 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile); 1059 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 1060 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size()); 1061 } 1062 } else { 1063 Result = Tmp1; // chain 1064 } 1065 break; 1066 } 1067 case TargetLowering::Legal: 1068 if (Tmp1 != Node->getOperand(0) || 1069 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 1070 SmallVector<SDOperand, 8> Ops; 1071 Ops.push_back(Tmp1); 1072 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 1073 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1074 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1075 } else { 1076 // Otherwise promote them. 1077 Ops.push_back(PromoteOp(Node->getOperand(1))); 1078 Ops.push_back(PromoteOp(Node->getOperand(2))); 1079 } 1080 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1081 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1082 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1083 } 1084 break; 1085 } 1086 break; 1087 1088 case ISD::DEBUG_LOC: 1089 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1090 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1091 default: assert(0 && "This action is not supported yet!"); 1092 case TargetLowering::Legal: 1093 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1094 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1095 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1096 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1097 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1098 break; 1099 } 1100 break; 1101 1102 case ISD::LABEL: 1103 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!"); 1104 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 1105 default: assert(0 && "This action is not supported yet!"); 1106 case TargetLowering::Legal: 1107 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1108 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 1109 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1110 break; 1111 case TargetLowering::Expand: 1112 Result = LegalizeOp(Node->getOperand(0)); 1113 break; 1114 } 1115 break; 1116 1117 case ISD::Constant: { 1118 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1119 unsigned opAction = 1120 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1121 1122 // We know we don't need to expand constants here, constants only have one 1123 // value and we check that it is fine above. 1124 1125 if (opAction == TargetLowering::Custom) { 1126 Tmp1 = TLI.LowerOperation(Result, DAG); 1127 if (Tmp1.Val) 1128 Result = Tmp1; 1129 } 1130 break; 1131 } 1132 case ISD::ConstantFP: { 1133 // Spill FP immediates to the constant pool if the target cannot directly 1134 // codegen them. Targets often have some immediate values that can be 1135 // efficiently generated into an FP register without a load. We explicitly 1136 // leave these constants as ConstantFP nodes for the target to deal with. 1137 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1138 1139 // Check to see if this FP immediate is already legal. 1140 bool isLegal = false; 1141 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1142 E = TLI.legal_fpimm_end(); I != E; ++I) 1143 if (CFP->isExactlyValue(*I)) { 1144 isLegal = true; 1145 break; 1146 } 1147 1148 // If this is a legal constant, turn it into a TargetConstantFP node. 1149 if (isLegal) { 1150 Result = DAG.getTargetConstantFP(CFP->getValueAPF(), 1151 CFP->getValueType(0)); 1152 break; 1153 } 1154 1155 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1156 default: assert(0 && "This action is not supported yet!"); 1157 case TargetLowering::Custom: 1158 Tmp3 = TLI.LowerOperation(Result, DAG); 1159 if (Tmp3.Val) { 1160 Result = Tmp3; 1161 break; 1162 } 1163 // FALLTHROUGH 1164 case TargetLowering::Expand: 1165 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1166 } 1167 break; 1168 } 1169 case ISD::TokenFactor: 1170 if (Node->getNumOperands() == 2) { 1171 Tmp1 = LegalizeOp(Node->getOperand(0)); 1172 Tmp2 = LegalizeOp(Node->getOperand(1)); 1173 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1174 } else if (Node->getNumOperands() == 3) { 1175 Tmp1 = LegalizeOp(Node->getOperand(0)); 1176 Tmp2 = LegalizeOp(Node->getOperand(1)); 1177 Tmp3 = LegalizeOp(Node->getOperand(2)); 1178 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1179 } else { 1180 SmallVector<SDOperand, 8> Ops; 1181 // Legalize the operands. 1182 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1183 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1184 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1185 } 1186 break; 1187 1188 case ISD::FORMAL_ARGUMENTS: 1189 case ISD::CALL: 1190 // The only option for this is to custom lower it. 1191 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1192 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1193 1194 // The number of incoming and outgoing values should match; unless the final 1195 // outgoing value is a flag. 1196 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || 1197 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && 1198 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == 1199 MVT::Flag)) && 1200 "Lowering call/formal_arguments produced unexpected # results!"); 1201 1202 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1203 // remember that we legalized all of them, so it doesn't get relegalized. 1204 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1205 if (Tmp3.Val->getValueType(i) == MVT::Flag) 1206 continue; 1207 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1208 if (Op.ResNo == i) 1209 Tmp2 = Tmp1; 1210 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1211 } 1212 return Tmp2; 1213 case ISD::EXTRACT_SUBREG: { 1214 Tmp1 = LegalizeOp(Node->getOperand(0)); 1215 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1216 assert(idx && "Operand must be a constant"); 1217 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1218 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1219 } 1220 break; 1221 case ISD::INSERT_SUBREG: { 1222 Tmp1 = LegalizeOp(Node->getOperand(0)); 1223 Tmp2 = LegalizeOp(Node->getOperand(1)); 1224 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1225 assert(idx && "Operand must be a constant"); 1226 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1227 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1228 } 1229 break; 1230 case ISD::BUILD_VECTOR: 1231 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1232 default: assert(0 && "This action is not supported yet!"); 1233 case TargetLowering::Custom: 1234 Tmp3 = TLI.LowerOperation(Result, DAG); 1235 if (Tmp3.Val) { 1236 Result = Tmp3; 1237 break; 1238 } 1239 // FALLTHROUGH 1240 case TargetLowering::Expand: 1241 Result = ExpandBUILD_VECTOR(Result.Val); 1242 break; 1243 } 1244 break; 1245 case ISD::INSERT_VECTOR_ELT: 1246 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1247 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 1248 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1249 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1250 1251 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1252 Node->getValueType(0))) { 1253 default: assert(0 && "This action is not supported yet!"); 1254 case TargetLowering::Legal: 1255 break; 1256 case TargetLowering::Custom: 1257 Tmp4 = TLI.LowerOperation(Result, DAG); 1258 if (Tmp4.Val) { 1259 Result = Tmp4; 1260 break; 1261 } 1262 // FALLTHROUGH 1263 case TargetLowering::Expand: { 1264 // If the insert index is a constant, codegen this as a scalar_to_vector, 1265 // then a shuffle that inserts it into the right position in the vector. 1266 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1267 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1268 Tmp1.getValueType(), Tmp2); 1269 1270 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1271 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1272 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); 1273 1274 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 1275 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 1276 // the RHS. 1277 SmallVector<SDOperand, 8> ShufOps; 1278 for (unsigned i = 0; i != NumElts; ++i) { 1279 if (i != InsertPos->getValue()) 1280 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1281 else 1282 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1283 } 1284 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1285 &ShufOps[0], ShufOps.size()); 1286 1287 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1288 Tmp1, ScVec, ShufMask); 1289 Result = LegalizeOp(Result); 1290 break; 1291 } 1292 1293 // If the target doesn't support this, we have to spill the input vector 1294 // to a temporary stack slot, update the element, then reload it. This is 1295 // badness. We could also load the value into a vector register (either 1296 // with a "move to register" or "extload into register" instruction, then 1297 // permute it into place, if the idx is a constant and if the idx is 1298 // supported by the target. 1299 MVT::ValueType VT = Tmp1.getValueType(); 1300 MVT::ValueType EltVT = Tmp2.getValueType(); 1301 MVT::ValueType IdxVT = Tmp3.getValueType(); 1302 MVT::ValueType PtrVT = TLI.getPointerTy(); 1303 SDOperand StackPtr = DAG.CreateStackTemporary(VT); 1304 // Store the vector. 1305 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); 1306 1307 // Truncate or zero extend offset to target pointer type. 1308 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1309 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 1310 // Add the offset to the index. 1311 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 1312 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 1313 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 1314 // Store the scalar value. 1315 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); 1316 // Load the updated vector. 1317 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); 1318 break; 1319 } 1320 } 1321 break; 1322 case ISD::SCALAR_TO_VECTOR: 1323 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1324 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1325 break; 1326 } 1327 1328 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1329 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1330 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1331 Node->getValueType(0))) { 1332 default: assert(0 && "This action is not supported yet!"); 1333 case TargetLowering::Legal: 1334 break; 1335 case TargetLowering::Custom: 1336 Tmp3 = TLI.LowerOperation(Result, DAG); 1337 if (Tmp3.Val) { 1338 Result = Tmp3; 1339 break; 1340 } 1341 // FALLTHROUGH 1342 case TargetLowering::Expand: 1343 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1344 break; 1345 } 1346 break; 1347 case ISD::VECTOR_SHUFFLE: 1348 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1349 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1350 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1351 1352 // Allow targets to custom lower the SHUFFLEs they support. 1353 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1354 default: assert(0 && "Unknown operation action!"); 1355 case TargetLowering::Legal: 1356 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1357 "vector shuffle should not be created if not legal!"); 1358 break; 1359 case TargetLowering::Custom: 1360 Tmp3 = TLI.LowerOperation(Result, DAG); 1361 if (Tmp3.Val) { 1362 Result = Tmp3; 1363 break; 1364 } 1365 // FALLTHROUGH 1366 case TargetLowering::Expand: { 1367 MVT::ValueType VT = Node->getValueType(0); 1368 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1369 MVT::ValueType PtrVT = TLI.getPointerTy(); 1370 SDOperand Mask = Node->getOperand(2); 1371 unsigned NumElems = Mask.getNumOperands(); 1372 SmallVector<SDOperand,8> Ops; 1373 for (unsigned i = 0; i != NumElems; ++i) { 1374 SDOperand Arg = Mask.getOperand(i); 1375 if (Arg.getOpcode() == ISD::UNDEF) { 1376 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1377 } else { 1378 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1379 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1380 if (Idx < NumElems) 1381 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1382 DAG.getConstant(Idx, PtrVT))); 1383 else 1384 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1385 DAG.getConstant(Idx - NumElems, PtrVT))); 1386 } 1387 } 1388 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1389 break; 1390 } 1391 case TargetLowering::Promote: { 1392 // Change base type to a different vector type. 1393 MVT::ValueType OVT = Node->getValueType(0); 1394 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1395 1396 // Cast the two input vectors. 1397 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1398 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1399 1400 // Convert the shuffle mask to the right # elements. 1401 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1402 assert(Tmp3.Val && "Shuffle not legal?"); 1403 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1404 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1405 break; 1406 } 1407 } 1408 break; 1409 1410 case ISD::EXTRACT_VECTOR_ELT: 1411 Tmp1 = Node->getOperand(0); 1412 Tmp2 = LegalizeOp(Node->getOperand(1)); 1413 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1414 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1415 break; 1416 1417 case ISD::EXTRACT_SUBVECTOR: 1418 Tmp1 = Node->getOperand(0); 1419 Tmp2 = LegalizeOp(Node->getOperand(1)); 1420 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1421 Result = ExpandEXTRACT_SUBVECTOR(Result); 1422 break; 1423 1424 case ISD::CALLSEQ_START: { 1425 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1426 1427 // Recursively Legalize all of the inputs of the call end that do not lead 1428 // to this call start. This ensures that any libcalls that need be inserted 1429 // are inserted *before* the CALLSEQ_START. 1430 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1431 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1432 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1433 NodesLeadingTo); 1434 } 1435 1436 // Now that we legalized all of the inputs (which may have inserted 1437 // libcalls) create the new CALLSEQ_START node. 1438 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1439 1440 // Merge in the last call, to ensure that this call start after the last 1441 // call ended. 1442 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1443 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1444 Tmp1 = LegalizeOp(Tmp1); 1445 } 1446 1447 // Do not try to legalize the target-specific arguments (#1+). 1448 if (Tmp1 != Node->getOperand(0)) { 1449 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1450 Ops[0] = Tmp1; 1451 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1452 } 1453 1454 // Remember that the CALLSEQ_START is legalized. 1455 AddLegalizedOperand(Op.getValue(0), Result); 1456 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1457 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1458 1459 // Now that the callseq_start and all of the non-call nodes above this call 1460 // sequence have been legalized, legalize the call itself. During this 1461 // process, no libcalls can/will be inserted, guaranteeing that no calls 1462 // can overlap. 1463 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1464 SDOperand InCallSEQ = LastCALLSEQ_END; 1465 // Note that we are selecting this call! 1466 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1467 IsLegalizingCall = true; 1468 1469 // Legalize the call, starting from the CALLSEQ_END. 1470 LegalizeOp(LastCALLSEQ_END); 1471 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1472 return Result; 1473 } 1474 case ISD::CALLSEQ_END: 1475 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1476 // will cause this node to be legalized as well as handling libcalls right. 1477 if (LastCALLSEQ_END.Val != Node) { 1478 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1479 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1480 assert(I != LegalizedNodes.end() && 1481 "Legalizing the call start should have legalized this node!"); 1482 return I->second; 1483 } 1484 1485 // Otherwise, the call start has been legalized and everything is going 1486 // according to plan. Just legalize ourselves normally here. 1487 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1488 // Do not try to legalize the target-specific arguments (#1+), except for 1489 // an optional flag input. 1490 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1491 if (Tmp1 != Node->getOperand(0)) { 1492 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1493 Ops[0] = Tmp1; 1494 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1495 } 1496 } else { 1497 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1498 if (Tmp1 != Node->getOperand(0) || 1499 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1500 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1501 Ops[0] = Tmp1; 1502 Ops.back() = Tmp2; 1503 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1504 } 1505 } 1506 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1507 // This finishes up call legalization. 1508 IsLegalizingCall = false; 1509 1510 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1511 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1512 if (Node->getNumValues() == 2) 1513 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1514 return Result.getValue(Op.ResNo); 1515 case ISD::DYNAMIC_STACKALLOC: { 1516 MVT::ValueType VT = Node->getValueType(0); 1517 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1518 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1519 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1520 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1521 1522 Tmp1 = Result.getValue(0); 1523 Tmp2 = Result.getValue(1); 1524 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1525 default: assert(0 && "This action is not supported yet!"); 1526 case TargetLowering::Expand: { 1527 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1528 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1529 " not tell us which reg is the stack pointer!"); 1530 SDOperand Chain = Tmp1.getOperand(0); 1531 1532 // Chain the dynamic stack allocation so that it doesn't modify the stack 1533 // pointer when other instructions are using the stack. 1534 Chain = DAG.getCALLSEQ_START(Chain, 1535 DAG.getConstant(0, TLI.getPointerTy())); 1536 1537 SDOperand Size = Tmp2.getOperand(1); 1538 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1539 Chain = SP.getValue(1); 1540 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1541 unsigned StackAlign = 1542 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1543 if (Align > StackAlign) 1544 SP = DAG.getNode(ISD::AND, VT, SP, 1545 DAG.getConstant(-(uint64_t)Align, VT)); 1546 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1547 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1548 1549 Tmp2 = 1550 DAG.getCALLSEQ_END(Chain, 1551 DAG.getConstant(0, TLI.getPointerTy()), 1552 DAG.getConstant(0, TLI.getPointerTy()), 1553 SDOperand()); 1554 1555 Tmp1 = LegalizeOp(Tmp1); 1556 Tmp2 = LegalizeOp(Tmp2); 1557 break; 1558 } 1559 case TargetLowering::Custom: 1560 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1561 if (Tmp3.Val) { 1562 Tmp1 = LegalizeOp(Tmp3); 1563 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1564 } 1565 break; 1566 case TargetLowering::Legal: 1567 break; 1568 } 1569 // Since this op produce two values, make sure to remember that we 1570 // legalized both of them. 1571 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1572 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1573 return Op.ResNo ? Tmp2 : Tmp1; 1574 } 1575 case ISD::INLINEASM: { 1576 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1577 bool Changed = false; 1578 // Legalize all of the operands of the inline asm, in case they are nodes 1579 // that need to be expanded or something. Note we skip the asm string and 1580 // all of the TargetConstant flags. 1581 SDOperand Op = LegalizeOp(Ops[0]); 1582 Changed = Op != Ops[0]; 1583 Ops[0] = Op; 1584 1585 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1586 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1587 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1588 for (++i; NumVals; ++i, --NumVals) { 1589 SDOperand Op = LegalizeOp(Ops[i]); 1590 if (Op != Ops[i]) { 1591 Changed = true; 1592 Ops[i] = Op; 1593 } 1594 } 1595 } 1596 1597 if (HasInFlag) { 1598 Op = LegalizeOp(Ops.back()); 1599 Changed |= Op != Ops.back(); 1600 Ops.back() = Op; 1601 } 1602 1603 if (Changed) 1604 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1605 1606 // INLINE asm returns a chain and flag, make sure to add both to the map. 1607 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1608 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1609 return Result.getValue(Op.ResNo); 1610 } 1611 case ISD::BR: 1612 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1613 // Ensure that libcalls are emitted before a branch. 1614 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1615 Tmp1 = LegalizeOp(Tmp1); 1616 LastCALLSEQ_END = DAG.getEntryNode(); 1617 1618 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1619 break; 1620 case ISD::BRIND: 1621 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1622 // Ensure that libcalls are emitted before a branch. 1623 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1624 Tmp1 = LegalizeOp(Tmp1); 1625 LastCALLSEQ_END = DAG.getEntryNode(); 1626 1627 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1628 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1629 case Legal: 1630 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1631 break; 1632 } 1633 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1634 break; 1635 case ISD::BR_JT: 1636 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1637 // Ensure that libcalls are emitted before a branch. 1638 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1639 Tmp1 = LegalizeOp(Tmp1); 1640 LastCALLSEQ_END = DAG.getEntryNode(); 1641 1642 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1643 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1644 1645 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1646 default: assert(0 && "This action is not supported yet!"); 1647 case TargetLowering::Legal: break; 1648 case TargetLowering::Custom: 1649 Tmp1 = TLI.LowerOperation(Result, DAG); 1650 if (Tmp1.Val) Result = Tmp1; 1651 break; 1652 case TargetLowering::Expand: { 1653 SDOperand Chain = Result.getOperand(0); 1654 SDOperand Table = Result.getOperand(1); 1655 SDOperand Index = Result.getOperand(2); 1656 1657 MVT::ValueType PTy = TLI.getPointerTy(); 1658 MachineFunction &MF = DAG.getMachineFunction(); 1659 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1660 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1661 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1662 1663 SDOperand LD; 1664 switch (EntrySize) { 1665 default: assert(0 && "Size of jump table not supported yet."); break; 1666 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; 1667 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; 1668 } 1669 1670 Addr = LD; 1671 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1672 // For PIC, the sequence is: 1673 // BRIND(load(Jumptable + index) + RelocBase) 1674 // RelocBase can be JumpTable, GOT or some sort of global base. 1675 if (PTy != MVT::i32) 1676 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1677 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1678 TLI.getPICJumpTableRelocBase(Table, DAG)); 1679 } 1680 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1681 } 1682 } 1683 break; 1684 case ISD::BRCOND: 1685 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1686 // Ensure that libcalls are emitted before a return. 1687 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1688 Tmp1 = LegalizeOp(Tmp1); 1689 LastCALLSEQ_END = DAG.getEntryNode(); 1690 1691 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1692 case Expand: assert(0 && "It's impossible to expand bools"); 1693 case Legal: 1694 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1695 break; 1696 case Promote: 1697 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1698 1699 // The top bits of the promoted condition are not necessarily zero, ensure 1700 // that the value is properly zero extended. 1701 if (!DAG.MaskedValueIsZero(Tmp2, 1702 MVT::getIntVTBitMask(Tmp2.getValueType())^1)) 1703 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1704 break; 1705 } 1706 1707 // Basic block destination (Op#2) is always legal. 1708 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1709 1710 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1711 default: assert(0 && "This action is not supported yet!"); 1712 case TargetLowering::Legal: break; 1713 case TargetLowering::Custom: 1714 Tmp1 = TLI.LowerOperation(Result, DAG); 1715 if (Tmp1.Val) Result = Tmp1; 1716 break; 1717 case TargetLowering::Expand: 1718 // Expand brcond's setcc into its constituent parts and create a BR_CC 1719 // Node. 1720 if (Tmp2.getOpcode() == ISD::SETCC) { 1721 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1722 Tmp2.getOperand(0), Tmp2.getOperand(1), 1723 Node->getOperand(2)); 1724 } else { 1725 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1726 DAG.getCondCode(ISD::SETNE), Tmp2, 1727 DAG.getConstant(0, Tmp2.getValueType()), 1728 Node->getOperand(2)); 1729 } 1730 break; 1731 } 1732 break; 1733 case ISD::BR_CC: 1734 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1735 // Ensure that libcalls are emitted before a branch. 1736 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1737 Tmp1 = LegalizeOp(Tmp1); 1738 Tmp2 = Node->getOperand(2); // LHS 1739 Tmp3 = Node->getOperand(3); // RHS 1740 Tmp4 = Node->getOperand(1); // CC 1741 1742 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1743 LastCALLSEQ_END = DAG.getEntryNode(); 1744 1745 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1746 // the LHS is a legal SETCC itself. In this case, we need to compare 1747 // the result against zero to select between true and false values. 1748 if (Tmp3.Val == 0) { 1749 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1750 Tmp4 = DAG.getCondCode(ISD::SETNE); 1751 } 1752 1753 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1754 Node->getOperand(4)); 1755 1756 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1757 default: assert(0 && "Unexpected action for BR_CC!"); 1758 case TargetLowering::Legal: break; 1759 case TargetLowering::Custom: 1760 Tmp4 = TLI.LowerOperation(Result, DAG); 1761 if (Tmp4.Val) Result = Tmp4; 1762 break; 1763 } 1764 break; 1765 case ISD::LOAD: { 1766 LoadSDNode *LD = cast<LoadSDNode>(Node); 1767 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1768 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1769 1770 ISD::LoadExtType ExtType = LD->getExtensionType(); 1771 if (ExtType == ISD::NON_EXTLOAD) { 1772 MVT::ValueType VT = Node->getValueType(0); 1773 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1774 Tmp3 = Result.getValue(0); 1775 Tmp4 = Result.getValue(1); 1776 1777 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1778 default: assert(0 && "This action is not supported yet!"); 1779 case TargetLowering::Legal: 1780 // If this is an unaligned load and the target doesn't support it, 1781 // expand it. 1782 if (!TLI.allowsUnalignedMemoryAccesses()) { 1783 unsigned ABIAlignment = TLI.getTargetData()-> 1784 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1785 if (LD->getAlignment() < ABIAlignment){ 1786 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1787 TLI); 1788 Tmp3 = Result.getOperand(0); 1789 Tmp4 = Result.getOperand(1); 1790 Tmp3 = LegalizeOp(Tmp3); 1791 Tmp4 = LegalizeOp(Tmp4); 1792 } 1793 } 1794 break; 1795 case TargetLowering::Custom: 1796 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1797 if (Tmp1.Val) { 1798 Tmp3 = LegalizeOp(Tmp1); 1799 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1800 } 1801 break; 1802 case TargetLowering::Promote: { 1803 // Only promote a load of vector type to another. 1804 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1805 // Change base type to a different vector type. 1806 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1807 1808 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1809 LD->getSrcValueOffset(), 1810 LD->isVolatile(), LD->getAlignment()); 1811 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1812 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1813 break; 1814 } 1815 } 1816 // Since loads produce two values, make sure to remember that we 1817 // legalized both of them. 1818 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1819 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1820 return Op.ResNo ? Tmp4 : Tmp3; 1821 } else { 1822 MVT::ValueType SrcVT = LD->getLoadedVT(); 1823 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1824 default: assert(0 && "This action is not supported yet!"); 1825 case TargetLowering::Promote: 1826 assert(SrcVT == MVT::i1 && 1827 "Can only promote extending LOAD from i1 -> i8!"); 1828 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1829 LD->getSrcValue(), LD->getSrcValueOffset(), 1830 MVT::i8, LD->isVolatile(), LD->getAlignment()); 1831 Tmp1 = Result.getValue(0); 1832 Tmp2 = Result.getValue(1); 1833 break; 1834 case TargetLowering::Custom: 1835 isCustom = true; 1836 // FALLTHROUGH 1837 case TargetLowering::Legal: 1838 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1839 Tmp1 = Result.getValue(0); 1840 Tmp2 = Result.getValue(1); 1841 1842 if (isCustom) { 1843 Tmp3 = TLI.LowerOperation(Result, DAG); 1844 if (Tmp3.Val) { 1845 Tmp1 = LegalizeOp(Tmp3); 1846 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1847 } 1848 } else { 1849 // If this is an unaligned load and the target doesn't support it, 1850 // expand it. 1851 if (!TLI.allowsUnalignedMemoryAccesses()) { 1852 unsigned ABIAlignment = TLI.getTargetData()-> 1853 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1854 if (LD->getAlignment() < ABIAlignment){ 1855 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1856 TLI); 1857 Tmp1 = Result.getOperand(0); 1858 Tmp2 = Result.getOperand(1); 1859 Tmp1 = LegalizeOp(Tmp1); 1860 Tmp2 = LegalizeOp(Tmp2); 1861 } 1862 } 1863 } 1864 break; 1865 case TargetLowering::Expand: 1866 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1867 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1868 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 1869 LD->getSrcValueOffset(), 1870 LD->isVolatile(), LD->getAlignment()); 1871 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1872 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1873 Tmp2 = LegalizeOp(Load.getValue(1)); 1874 break; 1875 } 1876 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1877 // Turn the unsupported load into an EXTLOAD followed by an explicit 1878 // zero/sign extend inreg. 1879 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1880 Tmp1, Tmp2, LD->getSrcValue(), 1881 LD->getSrcValueOffset(), SrcVT, 1882 LD->isVolatile(), LD->getAlignment()); 1883 SDOperand ValRes; 1884 if (ExtType == ISD::SEXTLOAD) 1885 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1886 Result, DAG.getValueType(SrcVT)); 1887 else 1888 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1889 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1890 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1891 break; 1892 } 1893 // Since loads produce two values, make sure to remember that we legalized 1894 // both of them. 1895 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1896 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1897 return Op.ResNo ? Tmp2 : Tmp1; 1898 } 1899 } 1900 case ISD::EXTRACT_ELEMENT: { 1901 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1902 switch (getTypeAction(OpTy)) { 1903 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1904 case Legal: 1905 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1906 // 1 -> Hi 1907 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1908 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1909 TLI.getShiftAmountTy())); 1910 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1911 } else { 1912 // 0 -> Lo 1913 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1914 Node->getOperand(0)); 1915 } 1916 break; 1917 case Expand: 1918 // Get both the low and high parts. 1919 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1920 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1921 Result = Tmp2; // 1 -> Hi 1922 else 1923 Result = Tmp1; // 0 -> Lo 1924 break; 1925 } 1926 break; 1927 } 1928 1929 case ISD::CopyToReg: 1930 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1931 1932 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1933 "Register type must be legal!"); 1934 // Legalize the incoming value (must be a legal type). 1935 Tmp2 = LegalizeOp(Node->getOperand(2)); 1936 if (Node->getNumValues() == 1) { 1937 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1938 } else { 1939 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1940 if (Node->getNumOperands() == 4) { 1941 Tmp3 = LegalizeOp(Node->getOperand(3)); 1942 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1943 Tmp3); 1944 } else { 1945 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1946 } 1947 1948 // Since this produces two values, make sure to remember that we legalized 1949 // both of them. 1950 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1951 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1952 return Result; 1953 } 1954 break; 1955 1956 case ISD::RET: 1957 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1958 1959 // Ensure that libcalls are emitted before a return. 1960 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1961 Tmp1 = LegalizeOp(Tmp1); 1962 LastCALLSEQ_END = DAG.getEntryNode(); 1963 1964 switch (Node->getNumOperands()) { 1965 case 3: // ret val 1966 Tmp2 = Node->getOperand(1); 1967 Tmp3 = Node->getOperand(2); // Signness 1968 switch (getTypeAction(Tmp2.getValueType())) { 1969 case Legal: 1970 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1971 break; 1972 case Expand: 1973 if (!MVT::isVector(Tmp2.getValueType())) { 1974 SDOperand Lo, Hi; 1975 ExpandOp(Tmp2, Lo, Hi); 1976 1977 // Big endian systems want the hi reg first. 1978 if (!TLI.isLittleEndian()) 1979 std::swap(Lo, Hi); 1980 1981 if (Hi.Val) 1982 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1983 else 1984 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 1985 Result = LegalizeOp(Result); 1986 } else { 1987 SDNode *InVal = Tmp2.Val; 1988 int InIx = Tmp2.ResNo; 1989 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 1990 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 1991 1992 // Figure out if there is a simple type corresponding to this Vector 1993 // type. If so, convert to the vector type. 1994 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1995 if (TLI.isTypeLegal(TVT)) { 1996 // Turn this into a return of the vector type. 1997 Tmp2 = LegalizeOp(Tmp2); 1998 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1999 } else if (NumElems == 1) { 2000 // Turn this into a return of the scalar type. 2001 Tmp2 = ScalarizeVectorOp(Tmp2); 2002 Tmp2 = LegalizeOp(Tmp2); 2003 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2004 2005 // FIXME: Returns of gcc generic vectors smaller than a legal type 2006 // should be returned in integer registers! 2007 2008 // The scalarized value type may not be legal, e.g. it might require 2009 // promotion or expansion. Relegalize the return. 2010 Result = LegalizeOp(Result); 2011 } else { 2012 // FIXME: Returns of gcc generic vectors larger than a legal vector 2013 // type should be returned by reference! 2014 SDOperand Lo, Hi; 2015 SplitVectorOp(Tmp2, Lo, Hi); 2016 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2017 Result = LegalizeOp(Result); 2018 } 2019 } 2020 break; 2021 case Promote: 2022 Tmp2 = PromoteOp(Node->getOperand(1)); 2023 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2024 Result = LegalizeOp(Result); 2025 break; 2026 } 2027 break; 2028 case 1: // ret void 2029 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2030 break; 2031 default: { // ret <values> 2032 SmallVector<SDOperand, 8> NewValues; 2033 NewValues.push_back(Tmp1); 2034 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2035 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2036 case Legal: 2037 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2038 NewValues.push_back(Node->getOperand(i+1)); 2039 break; 2040 case Expand: { 2041 SDOperand Lo, Hi; 2042 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && 2043 "FIXME: TODO: implement returning non-legal vector types!"); 2044 ExpandOp(Node->getOperand(i), Lo, Hi); 2045 NewValues.push_back(Lo); 2046 NewValues.push_back(Node->getOperand(i+1)); 2047 if (Hi.Val) { 2048 NewValues.push_back(Hi); 2049 NewValues.push_back(Node->getOperand(i+1)); 2050 } 2051 break; 2052 } 2053 case Promote: 2054 assert(0 && "Can't promote multiple return value yet!"); 2055 } 2056 2057 if (NewValues.size() == Node->getNumOperands()) 2058 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2059 else 2060 Result = DAG.getNode(ISD::RET, MVT::Other, 2061 &NewValues[0], NewValues.size()); 2062 break; 2063 } 2064 } 2065 2066 if (Result.getOpcode() == ISD::RET) { 2067 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2068 default: assert(0 && "This action is not supported yet!"); 2069 case TargetLowering::Legal: break; 2070 case TargetLowering::Custom: 2071 Tmp1 = TLI.LowerOperation(Result, DAG); 2072 if (Tmp1.Val) Result = Tmp1; 2073 break; 2074 } 2075 } 2076 break; 2077 case ISD::STORE: { 2078 StoreSDNode *ST = cast<StoreSDNode>(Node); 2079 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2080 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2081 int SVOffset = ST->getSrcValueOffset(); 2082 unsigned Alignment = ST->getAlignment(); 2083 bool isVolatile = ST->isVolatile(); 2084 2085 if (!ST->isTruncatingStore()) { 2086 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2087 // FIXME: We shouldn't do this for TargetConstantFP's. 2088 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2089 // to phase ordering between legalized code and the dag combiner. This 2090 // probably means that we need to integrate dag combiner and legalizer 2091 // together. 2092 // We generally can't do this one for long doubles. 2093 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2094 if (CFP->getValueType(0) == MVT::f32 && 2095 getTypeAction(MVT::i32) == Legal) { 2096 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF(). 2097 convertToAPInt().getZExtValue(), 2098 MVT::i32); 2099 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2100 SVOffset, isVolatile, Alignment); 2101 break; 2102 } else if (CFP->getValueType(0) == MVT::f64) { 2103 // If this target supports 64-bit registers, do a single 64-bit store. 2104 if (getTypeAction(MVT::i64) == Legal) { 2105 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2106 getZExtValue(), MVT::i64); 2107 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2108 SVOffset, isVolatile, Alignment); 2109 break; 2110 } else if (getTypeAction(MVT::i32) == Legal) { 2111 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2112 // stores. If the target supports neither 32- nor 64-bits, this 2113 // xform is certainly not worth it. 2114 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue(); 2115 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32); 2116 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32); 2117 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 2118 2119 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2120 SVOffset, isVolatile, Alignment); 2121 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2122 DAG.getIntPtrConstant(4)); 2123 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2124 isVolatile, MinAlign(Alignment, 4U)); 2125 2126 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2127 break; 2128 } 2129 } 2130 } 2131 2132 switch (getTypeAction(ST->getStoredVT())) { 2133 case Legal: { 2134 Tmp3 = LegalizeOp(ST->getValue()); 2135 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2136 ST->getOffset()); 2137 2138 MVT::ValueType VT = Tmp3.getValueType(); 2139 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2140 default: assert(0 && "This action is not supported yet!"); 2141 case TargetLowering::Legal: 2142 // If this is an unaligned store and the target doesn't support it, 2143 // expand it. 2144 if (!TLI.allowsUnalignedMemoryAccesses()) { 2145 unsigned ABIAlignment = TLI.getTargetData()-> 2146 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2147 if (ST->getAlignment() < ABIAlignment) 2148 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2149 TLI); 2150 } 2151 break; 2152 case TargetLowering::Custom: 2153 Tmp1 = TLI.LowerOperation(Result, DAG); 2154 if (Tmp1.Val) Result = Tmp1; 2155 break; 2156 case TargetLowering::Promote: 2157 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 2158 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2159 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2160 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2161 ST->getSrcValue(), SVOffset, isVolatile, 2162 Alignment); 2163 break; 2164 } 2165 break; 2166 } 2167 case Promote: 2168 // Truncate the value and store the result. 2169 Tmp3 = PromoteOp(ST->getValue()); 2170 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2171 SVOffset, ST->getStoredVT(), 2172 isVolatile, Alignment); 2173 break; 2174 2175 case Expand: 2176 unsigned IncrementSize = 0; 2177 SDOperand Lo, Hi; 2178 2179 // If this is a vector type, then we have to calculate the increment as 2180 // the product of the element size in bytes, and the number of elements 2181 // in the high half of the vector. 2182 if (MVT::isVector(ST->getValue().getValueType())) { 2183 SDNode *InVal = ST->getValue().Val; 2184 int InIx = ST->getValue().ResNo; 2185 MVT::ValueType InVT = InVal->getValueType(InIx); 2186 unsigned NumElems = MVT::getVectorNumElements(InVT); 2187 MVT::ValueType EVT = MVT::getVectorElementType(InVT); 2188 2189 // Figure out if there is a simple type corresponding to this Vector 2190 // type. If so, convert to the vector type. 2191 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2192 if (TLI.isTypeLegal(TVT)) { 2193 // Turn this into a normal store of the vector type. 2194 Tmp3 = LegalizeOp(Node->getOperand(1)); 2195 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2196 SVOffset, isVolatile, Alignment); 2197 Result = LegalizeOp(Result); 2198 break; 2199 } else if (NumElems == 1) { 2200 // Turn this into a normal store of the scalar type. 2201 Tmp3 = ScalarizeVectorOp(Node->getOperand(1)); 2202 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2203 SVOffset, isVolatile, Alignment); 2204 // The scalarized value type may not be legal, e.g. it might require 2205 // promotion or expansion. Relegalize the scalar store. 2206 Result = LegalizeOp(Result); 2207 break; 2208 } else { 2209 SplitVectorOp(Node->getOperand(1), Lo, Hi); 2210 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) * 2211 MVT::getSizeInBits(EVT)/8; 2212 } 2213 } else { 2214 ExpandOp(Node->getOperand(1), Lo, Hi); 2215 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 2216 2217 if (!TLI.isLittleEndian()) 2218 std::swap(Lo, Hi); 2219 } 2220 2221 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2222 SVOffset, isVolatile, Alignment); 2223 2224 if (Hi.Val == NULL) { 2225 // Must be int <-> float one-to-one expansion. 2226 Result = Lo; 2227 break; 2228 } 2229 2230 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2231 DAG.getIntPtrConstant(IncrementSize)); 2232 assert(isTypeLegal(Tmp2.getValueType()) && 2233 "Pointers must be legal!"); 2234 SVOffset += IncrementSize; 2235 Alignment = MinAlign(Alignment, IncrementSize); 2236 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2237 SVOffset, isVolatile, Alignment); 2238 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2239 break; 2240 } 2241 } else { 2242 // Truncating store 2243 assert(isTypeLegal(ST->getValue().getValueType()) && 2244 "Cannot handle illegal TRUNCSTORE yet!"); 2245 Tmp3 = LegalizeOp(ST->getValue()); 2246 2247 // The only promote case we handle is TRUNCSTORE:i1 X into 2248 // -> TRUNCSTORE:i8 (and X, 1) 2249 if (ST->getStoredVT() == MVT::i1 && 2250 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) { 2251 // Promote the bool to a mask then store. 2252 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3, 2253 DAG.getConstant(1, Tmp3.getValueType())); 2254 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2255 SVOffset, MVT::i8, 2256 isVolatile, Alignment); 2257 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2258 Tmp2 != ST->getBasePtr()) { 2259 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2260 ST->getOffset()); 2261 } 2262 2263 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT(); 2264 switch (TLI.getStoreXAction(StVT)) { 2265 default: assert(0 && "This action is not supported yet!"); 2266 case TargetLowering::Legal: 2267 // If this is an unaligned store and the target doesn't support it, 2268 // expand it. 2269 if (!TLI.allowsUnalignedMemoryAccesses()) { 2270 unsigned ABIAlignment = TLI.getTargetData()-> 2271 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2272 if (ST->getAlignment() < ABIAlignment) 2273 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2274 TLI); 2275 } 2276 break; 2277 case TargetLowering::Custom: 2278 Tmp1 = TLI.LowerOperation(Result, DAG); 2279 if (Tmp1.Val) Result = Tmp1; 2280 break; 2281 } 2282 } 2283 break; 2284 } 2285 case ISD::PCMARKER: 2286 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2287 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2288 break; 2289 case ISD::STACKSAVE: 2290 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2291 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2292 Tmp1 = Result.getValue(0); 2293 Tmp2 = Result.getValue(1); 2294 2295 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2296 default: assert(0 && "This action is not supported yet!"); 2297 case TargetLowering::Legal: break; 2298 case TargetLowering::Custom: 2299 Tmp3 = TLI.LowerOperation(Result, DAG); 2300 if (Tmp3.Val) { 2301 Tmp1 = LegalizeOp(Tmp3); 2302 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2303 } 2304 break; 2305 case TargetLowering::Expand: 2306 // Expand to CopyFromReg if the target set 2307 // StackPointerRegisterToSaveRestore. 2308 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2309 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2310 Node->getValueType(0)); 2311 Tmp2 = Tmp1.getValue(1); 2312 } else { 2313 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2314 Tmp2 = Node->getOperand(0); 2315 } 2316 break; 2317 } 2318 2319 // Since stacksave produce two values, make sure to remember that we 2320 // legalized both of them. 2321 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2322 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2323 return Op.ResNo ? Tmp2 : Tmp1; 2324 2325 case ISD::STACKRESTORE: 2326 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2327 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2328 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2329 2330 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2331 default: assert(0 && "This action is not supported yet!"); 2332 case TargetLowering::Legal: break; 2333 case TargetLowering::Custom: 2334 Tmp1 = TLI.LowerOperation(Result, DAG); 2335 if (Tmp1.Val) Result = Tmp1; 2336 break; 2337 case TargetLowering::Expand: 2338 // Expand to CopyToReg if the target set 2339 // StackPointerRegisterToSaveRestore. 2340 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2341 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2342 } else { 2343 Result = Tmp1; 2344 } 2345 break; 2346 } 2347 break; 2348 2349 case ISD::READCYCLECOUNTER: 2350 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2351 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2352 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2353 Node->getValueType(0))) { 2354 default: assert(0 && "This action is not supported yet!"); 2355 case TargetLowering::Legal: 2356 Tmp1 = Result.getValue(0); 2357 Tmp2 = Result.getValue(1); 2358 break; 2359 case TargetLowering::Custom: 2360 Result = TLI.LowerOperation(Result, DAG); 2361 Tmp1 = LegalizeOp(Result.getValue(0)); 2362 Tmp2 = LegalizeOp(Result.getValue(1)); 2363 break; 2364 } 2365 2366 // Since rdcc produce two values, make sure to remember that we legalized 2367 // both of them. 2368 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2369 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2370 return Result; 2371 2372 case ISD::SELECT: 2373 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2374 case Expand: assert(0 && "It's impossible to expand bools"); 2375 case Legal: 2376 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2377 break; 2378 case Promote: 2379 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2380 // Make sure the condition is either zero or one. 2381 if (!DAG.MaskedValueIsZero(Tmp1, 2382 MVT::getIntVTBitMask(Tmp1.getValueType())^1)) 2383 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2384 break; 2385 } 2386 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2387 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2388 2389 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2390 2391 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2392 default: assert(0 && "This action is not supported yet!"); 2393 case TargetLowering::Legal: break; 2394 case TargetLowering::Custom: { 2395 Tmp1 = TLI.LowerOperation(Result, DAG); 2396 if (Tmp1.Val) Result = Tmp1; 2397 break; 2398 } 2399 case TargetLowering::Expand: 2400 if (Tmp1.getOpcode() == ISD::SETCC) { 2401 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2402 Tmp2, Tmp3, 2403 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2404 } else { 2405 Result = DAG.getSelectCC(Tmp1, 2406 DAG.getConstant(0, Tmp1.getValueType()), 2407 Tmp2, Tmp3, ISD::SETNE); 2408 } 2409 break; 2410 case TargetLowering::Promote: { 2411 MVT::ValueType NVT = 2412 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2413 unsigned ExtOp, TruncOp; 2414 if (MVT::isVector(Tmp2.getValueType())) { 2415 ExtOp = ISD::BIT_CONVERT; 2416 TruncOp = ISD::BIT_CONVERT; 2417 } else if (MVT::isInteger(Tmp2.getValueType())) { 2418 ExtOp = ISD::ANY_EXTEND; 2419 TruncOp = ISD::TRUNCATE; 2420 } else { 2421 ExtOp = ISD::FP_EXTEND; 2422 TruncOp = ISD::FP_ROUND; 2423 } 2424 // Promote each of the values to the new type. 2425 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2426 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2427 // Perform the larger operation, then round down. 2428 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2429 if (TruncOp != ISD::FP_ROUND) 2430 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2431 else 2432 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2433 DAG.getIntPtrConstant(0)); 2434 break; 2435 } 2436 } 2437 break; 2438 case ISD::SELECT_CC: { 2439 Tmp1 = Node->getOperand(0); // LHS 2440 Tmp2 = Node->getOperand(1); // RHS 2441 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2442 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2443 SDOperand CC = Node->getOperand(4); 2444 2445 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2446 2447 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2448 // the LHS is a legal SETCC itself. In this case, we need to compare 2449 // the result against zero to select between true and false values. 2450 if (Tmp2.Val == 0) { 2451 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2452 CC = DAG.getCondCode(ISD::SETNE); 2453 } 2454 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2455 2456 // Everything is legal, see if we should expand this op or something. 2457 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2458 default: assert(0 && "This action is not supported yet!"); 2459 case TargetLowering::Legal: break; 2460 case TargetLowering::Custom: 2461 Tmp1 = TLI.LowerOperation(Result, DAG); 2462 if (Tmp1.Val) Result = Tmp1; 2463 break; 2464 } 2465 break; 2466 } 2467 case ISD::SETCC: 2468 Tmp1 = Node->getOperand(0); 2469 Tmp2 = Node->getOperand(1); 2470 Tmp3 = Node->getOperand(2); 2471 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2472 2473 // If we had to Expand the SetCC operands into a SELECT node, then it may 2474 // not always be possible to return a true LHS & RHS. In this case, just 2475 // return the value we legalized, returned in the LHS 2476 if (Tmp2.Val == 0) { 2477 Result = Tmp1; 2478 break; 2479 } 2480 2481 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2482 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2483 case TargetLowering::Custom: 2484 isCustom = true; 2485 // FALLTHROUGH. 2486 case TargetLowering::Legal: 2487 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2488 if (isCustom) { 2489 Tmp4 = TLI.LowerOperation(Result, DAG); 2490 if (Tmp4.Val) Result = Tmp4; 2491 } 2492 break; 2493 case TargetLowering::Promote: { 2494 // First step, figure out the appropriate operation to use. 2495 // Allow SETCC to not be supported for all legal data types 2496 // Mostly this targets FP 2497 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2498 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2499 2500 // Scan for the appropriate larger type to use. 2501 while (1) { 2502 NewInTy = (MVT::ValueType)(NewInTy+1); 2503 2504 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2505 "Fell off of the edge of the integer world"); 2506 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2507 "Fell off of the edge of the floating point world"); 2508 2509 // If the target supports SETCC of this type, use it. 2510 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2511 break; 2512 } 2513 if (MVT::isInteger(NewInTy)) 2514 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2515 else { 2516 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2517 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2518 } 2519 Tmp1 = LegalizeOp(Tmp1); 2520 Tmp2 = LegalizeOp(Tmp2); 2521 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2522 Result = LegalizeOp(Result); 2523 break; 2524 } 2525 case TargetLowering::Expand: 2526 // Expand a setcc node into a select_cc of the same condition, lhs, and 2527 // rhs that selects between const 1 (true) and const 0 (false). 2528 MVT::ValueType VT = Node->getValueType(0); 2529 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2530 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2531 Tmp3); 2532 break; 2533 } 2534 break; 2535 case ISD::MEMSET: 2536 case ISD::MEMCPY: 2537 case ISD::MEMMOVE: { 2538 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2539 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2540 2541 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2542 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2543 case Expand: assert(0 && "Cannot expand a byte!"); 2544 case Legal: 2545 Tmp3 = LegalizeOp(Node->getOperand(2)); 2546 break; 2547 case Promote: 2548 Tmp3 = PromoteOp(Node->getOperand(2)); 2549 break; 2550 } 2551 } else { 2552 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2553 } 2554 2555 SDOperand Tmp4; 2556 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2557 case Expand: { 2558 // Length is too big, just take the lo-part of the length. 2559 SDOperand HiPart; 2560 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2561 break; 2562 } 2563 case Legal: 2564 Tmp4 = LegalizeOp(Node->getOperand(3)); 2565 break; 2566 case Promote: 2567 Tmp4 = PromoteOp(Node->getOperand(3)); 2568 break; 2569 } 2570 2571 SDOperand Tmp5; 2572 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2573 case Expand: assert(0 && "Cannot expand this yet!"); 2574 case Legal: 2575 Tmp5 = LegalizeOp(Node->getOperand(4)); 2576 break; 2577 case Promote: 2578 Tmp5 = PromoteOp(Node->getOperand(4)); 2579 break; 2580 } 2581 2582 SDOperand Tmp6; 2583 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool 2584 case Expand: assert(0 && "Cannot expand this yet!"); 2585 case Legal: 2586 Tmp6 = LegalizeOp(Node->getOperand(5)); 2587 break; 2588 case Promote: 2589 Tmp6 = PromoteOp(Node->getOperand(5)); 2590 break; 2591 } 2592 2593 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2594 default: assert(0 && "This action not implemented for this operation!"); 2595 case TargetLowering::Custom: 2596 isCustom = true; 2597 // FALLTHROUGH 2598 case TargetLowering::Legal: { 2599 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 }; 2600 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 2601 if (isCustom) { 2602 Tmp1 = TLI.LowerOperation(Result, DAG); 2603 if (Tmp1.Val) Result = Tmp1; 2604 } 2605 break; 2606 } 2607 case TargetLowering::Expand: { 2608 // Otherwise, the target does not support this operation. Lower the 2609 // operation to an explicit libcall as appropriate. 2610 MVT::ValueType IntPtr = TLI.getPointerTy(); 2611 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2612 TargetLowering::ArgListTy Args; 2613 TargetLowering::ArgListEntry Entry; 2614 2615 const char *FnName = 0; 2616 if (Node->getOpcode() == ISD::MEMSET) { 2617 Entry.Node = Tmp2; Entry.Ty = IntPtrTy; 2618 Args.push_back(Entry); 2619 // Extend the (previously legalized) ubyte argument to be an int value 2620 // for the call. 2621 if (Tmp3.getValueType() > MVT::i32) 2622 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2623 else 2624 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2625 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 2626 Args.push_back(Entry); 2627 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false; 2628 Args.push_back(Entry); 2629 2630 FnName = "memset"; 2631 } else if (Node->getOpcode() == ISD::MEMCPY || 2632 Node->getOpcode() == ISD::MEMMOVE) { 2633 Entry.Ty = IntPtrTy; 2634 Entry.Node = Tmp2; Args.push_back(Entry); 2635 Entry.Node = Tmp3; Args.push_back(Entry); 2636 Entry.Node = Tmp4; Args.push_back(Entry); 2637 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2638 } else { 2639 assert(0 && "Unknown op!"); 2640 } 2641 2642 std::pair<SDOperand,SDOperand> CallResult = 2643 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 2644 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2645 Result = CallResult.second; 2646 break; 2647 } 2648 } 2649 break; 2650 } 2651 2652 case ISD::SHL_PARTS: 2653 case ISD::SRA_PARTS: 2654 case ISD::SRL_PARTS: { 2655 SmallVector<SDOperand, 8> Ops; 2656 bool Changed = false; 2657 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2658 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2659 Changed |= Ops.back() != Node->getOperand(i); 2660 } 2661 if (Changed) 2662 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2663 2664 switch (TLI.getOperationAction(Node->getOpcode(), 2665 Node->getValueType(0))) { 2666 default: assert(0 && "This action is not supported yet!"); 2667 case TargetLowering::Legal: break; 2668 case TargetLowering::Custom: 2669 Tmp1 = TLI.LowerOperation(Result, DAG); 2670 if (Tmp1.Val) { 2671 SDOperand Tmp2, RetVal(0, 0); 2672 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2673 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2674 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2675 if (i == Op.ResNo) 2676 RetVal = Tmp2; 2677 } 2678 assert(RetVal.Val && "Illegal result number"); 2679 return RetVal; 2680 } 2681 break; 2682 } 2683 2684 // Since these produce multiple values, make sure to remember that we 2685 // legalized all of them. 2686 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2687 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2688 return Result.getValue(Op.ResNo); 2689 } 2690 2691 // Binary operators 2692 case ISD::ADD: 2693 case ISD::SUB: 2694 case ISD::MUL: 2695 case ISD::MULHS: 2696 case ISD::MULHU: 2697 case ISD::UDIV: 2698 case ISD::SDIV: 2699 case ISD::AND: 2700 case ISD::OR: 2701 case ISD::XOR: 2702 case ISD::SHL: 2703 case ISD::SRL: 2704 case ISD::SRA: 2705 case ISD::FADD: 2706 case ISD::FSUB: 2707 case ISD::FMUL: 2708 case ISD::FDIV: 2709 case ISD::FPOW: 2710 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2711 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2712 case Expand: assert(0 && "Not possible"); 2713 case Legal: 2714 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2715 break; 2716 case Promote: 2717 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2718 break; 2719 } 2720 2721 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2722 2723 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2724 default: assert(0 && "BinOp legalize operation not supported"); 2725 case TargetLowering::Legal: break; 2726 case TargetLowering::Custom: 2727 Tmp1 = TLI.LowerOperation(Result, DAG); 2728 if (Tmp1.Val) Result = Tmp1; 2729 break; 2730 case TargetLowering::Expand: { 2731 MVT::ValueType VT = Op.getValueType(); 2732 2733 // See if multiply or divide can be lowered using two-result operations. 2734 SDVTList VTs = DAG.getVTList(VT, VT); 2735 if (Node->getOpcode() == ISD::MUL) { 2736 // We just need the low half of the multiply; try both the signed 2737 // and unsigned forms. If the target supports both SMUL_LOHI and 2738 // UMUL_LOHI, form a preference by checking which forms of plain 2739 // MULH it supports. 2740 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2741 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2742 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2743 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2744 unsigned OpToUse = 0; 2745 if (HasSMUL_LOHI && !HasMULHS) { 2746 OpToUse = ISD::SMUL_LOHI; 2747 } else if (HasUMUL_LOHI && !HasMULHU) { 2748 OpToUse = ISD::UMUL_LOHI; 2749 } else if (HasSMUL_LOHI) { 2750 OpToUse = ISD::SMUL_LOHI; 2751 } else if (HasUMUL_LOHI) { 2752 OpToUse = ISD::UMUL_LOHI; 2753 } 2754 if (OpToUse) { 2755 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 2756 break; 2757 } 2758 } 2759 if (Node->getOpcode() == ISD::MULHS && 2760 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 2761 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 2762 break; 2763 } 2764 if (Node->getOpcode() == ISD::MULHU && 2765 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 2766 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 2767 break; 2768 } 2769 if (Node->getOpcode() == ISD::SDIV && 2770 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 2771 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 2772 break; 2773 } 2774 if (Node->getOpcode() == ISD::UDIV && 2775 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 2776 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 2777 break; 2778 } 2779 2780 // Check to see if we have a libcall for this operator. 2781 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2782 bool isSigned = false; 2783 switch (Node->getOpcode()) { 2784 case ISD::UDIV: 2785 case ISD::SDIV: 2786 if (VT == MVT::i32) { 2787 LC = Node->getOpcode() == ISD::UDIV 2788 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 2789 isSigned = Node->getOpcode() == ISD::SDIV; 2790 } 2791 break; 2792 case ISD::FPOW: 2793 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 2794 RTLIB::POW_PPCF128); 2795 break; 2796 default: break; 2797 } 2798 if (LC != RTLIB::UNKNOWN_LIBCALL) { 2799 SDOperand Dummy; 2800 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2801 break; 2802 } 2803 2804 assert(MVT::isVector(Node->getValueType(0)) && 2805 "Cannot expand this binary operator!"); 2806 // Expand the operation into a bunch of nasty scalar code. 2807 Result = LegalizeOp(UnrollVectorOp(Op)); 2808 break; 2809 } 2810 case TargetLowering::Promote: { 2811 switch (Node->getOpcode()) { 2812 default: assert(0 && "Do not know how to promote this BinOp!"); 2813 case ISD::AND: 2814 case ISD::OR: 2815 case ISD::XOR: { 2816 MVT::ValueType OVT = Node->getValueType(0); 2817 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2818 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2819 // Bit convert each of the values to the new type. 2820 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2821 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2822 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2823 // Bit convert the result back the original type. 2824 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2825 break; 2826 } 2827 } 2828 } 2829 } 2830 break; 2831 2832 case ISD::SMUL_LOHI: 2833 case ISD::UMUL_LOHI: 2834 case ISD::SDIVREM: 2835 case ISD::UDIVREM: 2836 // These nodes will only be produced by target-specific lowering, so 2837 // they shouldn't be here if they aren't legal. 2838 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 2839 "This must be legal!"); 2840 2841 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2842 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2843 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2844 break; 2845 2846 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2847 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2848 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2849 case Expand: assert(0 && "Not possible"); 2850 case Legal: 2851 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2852 break; 2853 case Promote: 2854 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2855 break; 2856 } 2857 2858 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2859 2860 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2861 default: assert(0 && "Operation not supported"); 2862 case TargetLowering::Custom: 2863 Tmp1 = TLI.LowerOperation(Result, DAG); 2864 if (Tmp1.Val) Result = Tmp1; 2865 break; 2866 case TargetLowering::Legal: break; 2867 case TargetLowering::Expand: { 2868 // If this target supports fabs/fneg natively and select is cheap, 2869 // do this efficiently. 2870 if (!TLI.isSelectExpensive() && 2871 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 2872 TargetLowering::Legal && 2873 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 2874 TargetLowering::Legal) { 2875 // Get the sign bit of the RHS. 2876 MVT::ValueType IVT = 2877 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2878 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2879 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2880 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2881 // Get the absolute value of the result. 2882 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2883 // Select between the nabs and abs value based on the sign bit of 2884 // the input. 2885 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2886 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2887 AbsVal), 2888 AbsVal); 2889 Result = LegalizeOp(Result); 2890 break; 2891 } 2892 2893 // Otherwise, do bitwise ops! 2894 MVT::ValueType NVT = 2895 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 2896 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 2897 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 2898 Result = LegalizeOp(Result); 2899 break; 2900 } 2901 } 2902 break; 2903 2904 case ISD::ADDC: 2905 case ISD::SUBC: 2906 Tmp1 = LegalizeOp(Node->getOperand(0)); 2907 Tmp2 = LegalizeOp(Node->getOperand(1)); 2908 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2909 // Since this produces two values, make sure to remember that we legalized 2910 // both of them. 2911 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2912 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2913 return Result; 2914 2915 case ISD::ADDE: 2916 case ISD::SUBE: 2917 Tmp1 = LegalizeOp(Node->getOperand(0)); 2918 Tmp2 = LegalizeOp(Node->getOperand(1)); 2919 Tmp3 = LegalizeOp(Node->getOperand(2)); 2920 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2921 // Since this produces two values, make sure to remember that we legalized 2922 // both of them. 2923 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2924 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2925 return Result; 2926 2927 case ISD::BUILD_PAIR: { 2928 MVT::ValueType PairTy = Node->getValueType(0); 2929 // TODO: handle the case where the Lo and Hi operands are not of legal type 2930 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2931 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2932 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2933 case TargetLowering::Promote: 2934 case TargetLowering::Custom: 2935 assert(0 && "Cannot promote/custom this yet!"); 2936 case TargetLowering::Legal: 2937 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2938 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2939 break; 2940 case TargetLowering::Expand: 2941 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2942 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2943 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2944 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2945 TLI.getShiftAmountTy())); 2946 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2947 break; 2948 } 2949 break; 2950 } 2951 2952 case ISD::UREM: 2953 case ISD::SREM: 2954 case ISD::FREM: 2955 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2956 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2957 2958 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2959 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2960 case TargetLowering::Custom: 2961 isCustom = true; 2962 // FALLTHROUGH 2963 case TargetLowering::Legal: 2964 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2965 if (isCustom) { 2966 Tmp1 = TLI.LowerOperation(Result, DAG); 2967 if (Tmp1.Val) Result = Tmp1; 2968 } 2969 break; 2970 case TargetLowering::Expand: { 2971 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2972 bool isSigned = DivOpc == ISD::SDIV; 2973 MVT::ValueType VT = Node->getValueType(0); 2974 2975 // See if remainder can be lowered using two-result operations. 2976 SDVTList VTs = DAG.getVTList(VT, VT); 2977 if (Node->getOpcode() == ISD::SREM && 2978 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 2979 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 2980 break; 2981 } 2982 if (Node->getOpcode() == ISD::UREM && 2983 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 2984 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 2985 break; 2986 } 2987 2988 if (MVT::isInteger(VT)) { 2989 if (TLI.getOperationAction(DivOpc, VT) == 2990 TargetLowering::Legal) { 2991 // X % Y -> X-X/Y*Y 2992 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 2993 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2994 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2995 } else if (MVT::isVector(VT)) { 2996 Result = LegalizeOp(UnrollVectorOp(Op)); 2997 } else { 2998 assert(VT == MVT::i32 && 2999 "Cannot expand this binary operator!"); 3000 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3001 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3002 SDOperand Dummy; 3003 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 3004 } 3005 } else { 3006 assert(MVT::isFloatingPoint(VT) && 3007 "remainder op must have integer or floating-point type"); 3008 if (MVT::isVector(VT)) { 3009 Result = LegalizeOp(UnrollVectorOp(Op)); 3010 } else { 3011 // Floating point mod -> fmod libcall. 3012 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3013 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3014 SDOperand Dummy; 3015 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3016 false/*sign irrelevant*/, Dummy); 3017 } 3018 } 3019 break; 3020 } 3021 } 3022 break; 3023 case ISD::VAARG: { 3024 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3025 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3026 3027 MVT::ValueType VT = Node->getValueType(0); 3028 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3029 default: assert(0 && "This action is not supported yet!"); 3030 case TargetLowering::Custom: 3031 isCustom = true; 3032 // FALLTHROUGH 3033 case TargetLowering::Legal: 3034 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3035 Result = Result.getValue(0); 3036 Tmp1 = Result.getValue(1); 3037 3038 if (isCustom) { 3039 Tmp2 = TLI.LowerOperation(Result, DAG); 3040 if (Tmp2.Val) { 3041 Result = LegalizeOp(Tmp2); 3042 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3043 } 3044 } 3045 break; 3046 case TargetLowering::Expand: { 3047 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 3048 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3049 SV->getValue(), SV->getOffset()); 3050 // Increment the pointer, VAList, to the next vaarg 3051 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3052 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3053 TLI.getPointerTy())); 3054 // Store the incremented VAList to the legalized pointer 3055 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 3056 SV->getOffset()); 3057 // Load the actual argument out of the pointer VAList 3058 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3059 Tmp1 = LegalizeOp(Result.getValue(1)); 3060 Result = LegalizeOp(Result); 3061 break; 3062 } 3063 } 3064 // Since VAARG produces two values, make sure to remember that we 3065 // legalized both of them. 3066 AddLegalizedOperand(SDOperand(Node, 0), Result); 3067 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3068 return Op.ResNo ? Tmp1 : Result; 3069 } 3070 3071 case ISD::VACOPY: 3072 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3073 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3074 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3075 3076 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3077 default: assert(0 && "This action is not supported yet!"); 3078 case TargetLowering::Custom: 3079 isCustom = true; 3080 // FALLTHROUGH 3081 case TargetLowering::Legal: 3082 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3083 Node->getOperand(3), Node->getOperand(4)); 3084 if (isCustom) { 3085 Tmp1 = TLI.LowerOperation(Result, DAG); 3086 if (Tmp1.Val) Result = Tmp1; 3087 } 3088 break; 3089 case TargetLowering::Expand: 3090 // This defaults to loading a pointer from the input and storing it to the 3091 // output, returning the chain. 3092 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); 3093 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); 3094 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), 3095 SVD->getOffset()); 3096 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), 3097 SVS->getOffset()); 3098 break; 3099 } 3100 break; 3101 3102 case ISD::VAEND: 3103 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3104 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3105 3106 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3107 default: assert(0 && "This action is not supported yet!"); 3108 case TargetLowering::Custom: 3109 isCustom = true; 3110 // FALLTHROUGH 3111 case TargetLowering::Legal: 3112 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3113 if (isCustom) { 3114 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3115 if (Tmp1.Val) Result = Tmp1; 3116 } 3117 break; 3118 case TargetLowering::Expand: 3119 Result = Tmp1; // Default to a no-op, return the chain 3120 break; 3121 } 3122 break; 3123 3124 case ISD::VASTART: 3125 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3126 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3127 3128 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3129 3130 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3131 default: assert(0 && "This action is not supported yet!"); 3132 case TargetLowering::Legal: break; 3133 case TargetLowering::Custom: 3134 Tmp1 = TLI.LowerOperation(Result, DAG); 3135 if (Tmp1.Val) Result = Tmp1; 3136 break; 3137 } 3138 break; 3139 3140 case ISD::ROTL: 3141 case ISD::ROTR: 3142 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3143 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3144 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3145 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3146 default: 3147 assert(0 && "ROTL/ROTR legalize operation not supported"); 3148 break; 3149 case TargetLowering::Legal: 3150 break; 3151 case TargetLowering::Custom: 3152 Tmp1 = TLI.LowerOperation(Result, DAG); 3153 if (Tmp1.Val) Result = Tmp1; 3154 break; 3155 case TargetLowering::Promote: 3156 assert(0 && "Do not know how to promote ROTL/ROTR"); 3157 break; 3158 case TargetLowering::Expand: 3159 assert(0 && "Do not know how to expand ROTL/ROTR"); 3160 break; 3161 } 3162 break; 3163 3164 case ISD::BSWAP: 3165 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3166 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3167 case TargetLowering::Custom: 3168 assert(0 && "Cannot custom legalize this yet!"); 3169 case TargetLowering::Legal: 3170 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3171 break; 3172 case TargetLowering::Promote: { 3173 MVT::ValueType OVT = Tmp1.getValueType(); 3174 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3175 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); 3176 3177 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3178 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3179 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3180 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3181 break; 3182 } 3183 case TargetLowering::Expand: 3184 Result = ExpandBSWAP(Tmp1); 3185 break; 3186 } 3187 break; 3188 3189 case ISD::CTPOP: 3190 case ISD::CTTZ: 3191 case ISD::CTLZ: 3192 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3193 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3194 case TargetLowering::Custom: 3195 case TargetLowering::Legal: 3196 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3197 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3198 TargetLowering::Custom) { 3199 Tmp1 = TLI.LowerOperation(Result, DAG); 3200 if (Tmp1.Val) { 3201 Result = Tmp1; 3202 } 3203 } 3204 break; 3205 case TargetLowering::Promote: { 3206 MVT::ValueType OVT = Tmp1.getValueType(); 3207 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3208 3209 // Zero extend the argument. 3210 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3211 // Perform the larger operation, then subtract if needed. 3212 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3213 switch (Node->getOpcode()) { 3214 case ISD::CTPOP: 3215 Result = Tmp1; 3216 break; 3217 case ISD::CTTZ: 3218 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3219 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3220 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 3221 ISD::SETEQ); 3222 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3223 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); 3224 break; 3225 case ISD::CTLZ: 3226 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3227 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3228 DAG.getConstant(MVT::getSizeInBits(NVT) - 3229 MVT::getSizeInBits(OVT), NVT)); 3230 break; 3231 } 3232 break; 3233 } 3234 case TargetLowering::Expand: 3235 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3236 break; 3237 } 3238 break; 3239 3240 // Unary operators 3241 case ISD::FABS: 3242 case ISD::FNEG: 3243 case ISD::FSQRT: 3244 case ISD::FSIN: 3245 case ISD::FCOS: 3246 Tmp1 = LegalizeOp(Node->getOperand(0)); 3247 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3248 case TargetLowering::Promote: 3249 case TargetLowering::Custom: 3250 isCustom = true; 3251 // FALLTHROUGH 3252 case TargetLowering::Legal: 3253 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3254 if (isCustom) { 3255 Tmp1 = TLI.LowerOperation(Result, DAG); 3256 if (Tmp1.Val) Result = Tmp1; 3257 } 3258 break; 3259 case TargetLowering::Expand: 3260 switch (Node->getOpcode()) { 3261 default: assert(0 && "Unreachable!"); 3262 case ISD::FNEG: 3263 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3264 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3265 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3266 break; 3267 case ISD::FABS: { 3268 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3269 MVT::ValueType VT = Node->getValueType(0); 3270 Tmp2 = DAG.getConstantFP(0.0, VT); 3271 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 3272 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3273 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3274 break; 3275 } 3276 case ISD::FSQRT: 3277 case ISD::FSIN: 3278 case ISD::FCOS: { 3279 MVT::ValueType VT = Node->getValueType(0); 3280 3281 // Expand unsupported unary vector operators by unrolling them. 3282 if (MVT::isVector(VT)) { 3283 Result = LegalizeOp(UnrollVectorOp(Op)); 3284 break; 3285 } 3286 3287 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3288 switch(Node->getOpcode()) { 3289 case ISD::FSQRT: 3290 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3291 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3292 break; 3293 case ISD::FSIN: 3294 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3295 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3296 break; 3297 case ISD::FCOS: 3298 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3299 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3300 break; 3301 default: assert(0 && "Unreachable!"); 3302 } 3303 SDOperand Dummy; 3304 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3305 false/*sign irrelevant*/, Dummy); 3306 break; 3307 } 3308 } 3309 break; 3310 } 3311 break; 3312 case ISD::FPOWI: { 3313 MVT::ValueType VT = Node->getValueType(0); 3314 3315 // Expand unsupported unary vector operators by unrolling them. 3316 if (MVT::isVector(VT)) { 3317 Result = LegalizeOp(UnrollVectorOp(Op)); 3318 break; 3319 } 3320 3321 // We always lower FPOWI into a libcall. No target support for it yet. 3322 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3323 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3324 SDOperand Dummy; 3325 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3326 false/*sign irrelevant*/, Dummy); 3327 break; 3328 } 3329 case ISD::BIT_CONVERT: 3330 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3331 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3332 Node->getValueType(0)); 3333 } else if (MVT::isVector(Op.getOperand(0).getValueType())) { 3334 // The input has to be a vector type, we have to either scalarize it, pack 3335 // it, or convert it based on whether the input vector type is legal. 3336 SDNode *InVal = Node->getOperand(0).Val; 3337 int InIx = Node->getOperand(0).ResNo; 3338 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 3339 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 3340 3341 // Figure out if there is a simple type corresponding to this Vector 3342 // type. If so, convert to the vector type. 3343 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3344 if (TLI.isTypeLegal(TVT)) { 3345 // Turn this into a bit convert of the vector input. 3346 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3347 LegalizeOp(Node->getOperand(0))); 3348 break; 3349 } else if (NumElems == 1) { 3350 // Turn this into a bit convert of the scalar input. 3351 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3352 ScalarizeVectorOp(Node->getOperand(0))); 3353 break; 3354 } else { 3355 // FIXME: UNIMP! Store then reload 3356 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3357 } 3358 } else { 3359 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3360 Node->getOperand(0).getValueType())) { 3361 default: assert(0 && "Unknown operation action!"); 3362 case TargetLowering::Expand: 3363 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3364 Node->getValueType(0)); 3365 break; 3366 case TargetLowering::Legal: 3367 Tmp1 = LegalizeOp(Node->getOperand(0)); 3368 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3369 break; 3370 } 3371 } 3372 break; 3373 3374 // Conversion operators. The source and destination have different types. 3375 case ISD::SINT_TO_FP: 3376 case ISD::UINT_TO_FP: { 3377 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3378 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3379 case Legal: 3380 switch (TLI.getOperationAction(Node->getOpcode(), 3381 Node->getOperand(0).getValueType())) { 3382 default: assert(0 && "Unknown operation action!"); 3383 case TargetLowering::Custom: 3384 isCustom = true; 3385 // FALLTHROUGH 3386 case TargetLowering::Legal: 3387 Tmp1 = LegalizeOp(Node->getOperand(0)); 3388 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3389 if (isCustom) { 3390 Tmp1 = TLI.LowerOperation(Result, DAG); 3391 if (Tmp1.Val) Result = Tmp1; 3392 } 3393 break; 3394 case TargetLowering::Expand: 3395 Result = ExpandLegalINT_TO_FP(isSigned, 3396 LegalizeOp(Node->getOperand(0)), 3397 Node->getValueType(0)); 3398 break; 3399 case TargetLowering::Promote: 3400 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3401 Node->getValueType(0), 3402 isSigned); 3403 break; 3404 } 3405 break; 3406 case Expand: 3407 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3408 Node->getValueType(0), Node->getOperand(0)); 3409 break; 3410 case Promote: 3411 Tmp1 = PromoteOp(Node->getOperand(0)); 3412 if (isSigned) { 3413 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3414 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3415 } else { 3416 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3417 Node->getOperand(0).getValueType()); 3418 } 3419 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3420 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3421 break; 3422 } 3423 break; 3424 } 3425 case ISD::TRUNCATE: 3426 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3427 case Legal: 3428 Tmp1 = LegalizeOp(Node->getOperand(0)); 3429 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3430 break; 3431 case Expand: 3432 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3433 3434 // Since the result is legal, we should just be able to truncate the low 3435 // part of the source. 3436 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3437 break; 3438 case Promote: 3439 Result = PromoteOp(Node->getOperand(0)); 3440 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3441 break; 3442 } 3443 break; 3444 3445 case ISD::FP_TO_SINT: 3446 case ISD::FP_TO_UINT: 3447 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3448 case Legal: 3449 Tmp1 = LegalizeOp(Node->getOperand(0)); 3450 3451 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3452 default: assert(0 && "Unknown operation action!"); 3453 case TargetLowering::Custom: 3454 isCustom = true; 3455 // FALLTHROUGH 3456 case TargetLowering::Legal: 3457 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3458 if (isCustom) { 3459 Tmp1 = TLI.LowerOperation(Result, DAG); 3460 if (Tmp1.Val) Result = Tmp1; 3461 } 3462 break; 3463 case TargetLowering::Promote: 3464 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3465 Node->getOpcode() == ISD::FP_TO_SINT); 3466 break; 3467 case TargetLowering::Expand: 3468 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3469 SDOperand True, False; 3470 MVT::ValueType VT = Node->getOperand(0).getValueType(); 3471 MVT::ValueType NVT = Node->getValueType(0); 3472 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1; 3473 const uint64_t zero[] = {0, 0}; 3474 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero)); 3475 uint64_t x = 1ULL << ShiftAmt; 3476 (void)apf.convertFromZeroExtendedInteger 3477 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven); 3478 Tmp2 = DAG.getConstantFP(apf, VT); 3479 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 3480 Node->getOperand(0), Tmp2, ISD::SETLT); 3481 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3482 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3483 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3484 Tmp2)); 3485 False = DAG.getNode(ISD::XOR, NVT, False, 3486 DAG.getConstant(1ULL << ShiftAmt, NVT)); 3487 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3488 break; 3489 } else { 3490 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3491 } 3492 break; 3493 } 3494 break; 3495 case Expand: { 3496 MVT::ValueType VT = Op.getValueType(); 3497 MVT::ValueType OVT = Node->getOperand(0).getValueType(); 3498 // Convert ppcf128 to i32 3499 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3500 if (Node->getOpcode() == ISD::FP_TO_SINT) { 3501 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 3502 Node->getOperand(0), DAG.getValueType(MVT::f64)); 3503 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 3504 DAG.getIntPtrConstant(1)); 3505 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 3506 } else { 3507 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3508 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3509 Tmp2 = DAG.getConstantFP(apf, OVT); 3510 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3511 // FIXME: generated code sucks. 3512 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3513 DAG.getNode(ISD::ADD, MVT::i32, 3514 DAG.getNode(ISD::FP_TO_SINT, VT, 3515 DAG.getNode(ISD::FSUB, OVT, 3516 Node->getOperand(0), Tmp2)), 3517 DAG.getConstant(0x80000000, MVT::i32)), 3518 DAG.getNode(ISD::FP_TO_SINT, VT, 3519 Node->getOperand(0)), 3520 DAG.getCondCode(ISD::SETGE)); 3521 } 3522 break; 3523 } 3524 // Convert f32 / f64 to i32 / i64. 3525 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3526 switch (Node->getOpcode()) { 3527 case ISD::FP_TO_SINT: { 3528 if (OVT == MVT::f32) 3529 LC = (VT == MVT::i32) 3530 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3531 else if (OVT == MVT::f64) 3532 LC = (VT == MVT::i32) 3533 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3534 else if (OVT == MVT::f80) { 3535 assert(VT == MVT::i64); 3536 LC = RTLIB::FPTOSINT_F80_I64; 3537 } 3538 else if (OVT == MVT::ppcf128) { 3539 assert(VT == MVT::i64); 3540 LC = RTLIB::FPTOSINT_PPCF128_I64; 3541 } 3542 break; 3543 } 3544 case ISD::FP_TO_UINT: { 3545 if (OVT == MVT::f32) 3546 LC = (VT == MVT::i32) 3547 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3548 else if (OVT == MVT::f64) 3549 LC = (VT == MVT::i32) 3550 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3551 else if (OVT == MVT::f80) { 3552 LC = (VT == MVT::i32) 3553 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64; 3554 } 3555 else if (OVT == MVT::ppcf128) { 3556 assert(VT == MVT::i64); 3557 LC = RTLIB::FPTOUINT_PPCF128_I64; 3558 } 3559 break; 3560 } 3561 default: assert(0 && "Unreachable!"); 3562 } 3563 SDOperand Dummy; 3564 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3565 false/*sign irrelevant*/, Dummy); 3566 break; 3567 } 3568 case Promote: 3569 Tmp1 = PromoteOp(Node->getOperand(0)); 3570 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3571 Result = LegalizeOp(Result); 3572 break; 3573 } 3574 break; 3575 3576 case ISD::FP_EXTEND: { 3577 MVT::ValueType DstVT = Op.getValueType(); 3578 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 3579 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3580 // The only other way we can lower this is to turn it into a STORE, 3581 // LOAD pair, targetting a temporary location (a stack slot). 3582 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 3583 break; 3584 } 3585 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3586 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3587 case Legal: 3588 Tmp1 = LegalizeOp(Node->getOperand(0)); 3589 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3590 break; 3591 case Promote: 3592 Tmp1 = PromoteOp(Node->getOperand(0)); 3593 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 3594 break; 3595 } 3596 break; 3597 } 3598 case ISD::FP_ROUND: { 3599 MVT::ValueType DstVT = Op.getValueType(); 3600 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 3601 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3602 if (SrcVT == MVT::ppcf128) { 3603 SDOperand Lo, Hi; 3604 ExpandOp(Node->getOperand(0), Lo, Hi); 3605 // Round it the rest of the way (e.g. to f32) if needed. 3606 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Hi, Op.getOperand(1)); 3607 break; 3608 } 3609 // The only other way we can lower this is to turn it into a STORE, 3610 // LOAD pair, targetting a temporary location (a stack slot). 3611 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 3612 break; 3613 } 3614 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3615 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3616 case Legal: 3617 Tmp1 = LegalizeOp(Node->getOperand(0)); 3618 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3619 break; 3620 case Promote: 3621 Tmp1 = PromoteOp(Node->getOperand(0)); 3622 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 3623 Node->getOperand(1)); 3624 break; 3625 } 3626 break; 3627 } 3628 case ISD::ANY_EXTEND: 3629 case ISD::ZERO_EXTEND: 3630 case ISD::SIGN_EXTEND: 3631 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3632 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3633 case Legal: 3634 Tmp1 = LegalizeOp(Node->getOperand(0)); 3635 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3636 break; 3637 case Promote: 3638 switch (Node->getOpcode()) { 3639 case ISD::ANY_EXTEND: 3640 Tmp1 = PromoteOp(Node->getOperand(0)); 3641 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3642 break; 3643 case ISD::ZERO_EXTEND: 3644 Result = PromoteOp(Node->getOperand(0)); 3645 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3646 Result = DAG.getZeroExtendInReg(Result, 3647 Node->getOperand(0).getValueType()); 3648 break; 3649 case ISD::SIGN_EXTEND: 3650 Result = PromoteOp(Node->getOperand(0)); 3651 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3652 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3653 Result, 3654 DAG.getValueType(Node->getOperand(0).getValueType())); 3655 break; 3656 } 3657 } 3658 break; 3659 case ISD::FP_ROUND_INREG: 3660 case ISD::SIGN_EXTEND_INREG: { 3661 Tmp1 = LegalizeOp(Node->getOperand(0)); 3662 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3663 3664 // If this operation is not supported, convert it to a shl/shr or load/store 3665 // pair. 3666 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3667 default: assert(0 && "This action not supported for this op yet!"); 3668 case TargetLowering::Legal: 3669 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3670 break; 3671 case TargetLowering::Expand: 3672 // If this is an integer extend and shifts are supported, do that. 3673 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3674 // NOTE: we could fall back on load/store here too for targets without 3675 // SAR. However, it is doubtful that any exist. 3676 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3677 MVT::getSizeInBits(ExtraVT); 3678 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3679 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3680 Node->getOperand(0), ShiftCst); 3681 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3682 Result, ShiftCst); 3683 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3684 // The only way we can lower this is to turn it into a TRUNCSTORE, 3685 // EXTLOAD pair, targetting a temporary location (a stack slot). 3686 3687 // NOTE: there is a choice here between constantly creating new stack 3688 // slots and always reusing the same one. We currently always create 3689 // new ones, as reuse may inhibit scheduling. 3690 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 3691 Node->getValueType(0)); 3692 } else { 3693 assert(0 && "Unknown op"); 3694 } 3695 break; 3696 } 3697 break; 3698 } 3699 case ISD::TRAMPOLINE: { 3700 SDOperand Ops[6]; 3701 for (unsigned i = 0; i != 6; ++i) 3702 Ops[i] = LegalizeOp(Node->getOperand(i)); 3703 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3704 // The only option for this node is to custom lower it. 3705 Result = TLI.LowerOperation(Result, DAG); 3706 assert(Result.Val && "Should always custom lower!"); 3707 3708 // Since trampoline produces two values, make sure to remember that we 3709 // legalized both of them. 3710 Tmp1 = LegalizeOp(Result.getValue(1)); 3711 Result = LegalizeOp(Result); 3712 AddLegalizedOperand(SDOperand(Node, 0), Result); 3713 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3714 return Op.ResNo ? Tmp1 : Result; 3715 } 3716 case ISD::FLT_ROUNDS: { 3717 MVT::ValueType VT = Node->getValueType(0); 3718 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3719 default: assert(0 && "This action not supported for this op yet!"); 3720 case TargetLowering::Custom: 3721 Result = TLI.LowerOperation(Op, DAG); 3722 if (Result.Val) break; 3723 // Fall Thru 3724 case TargetLowering::Legal: 3725 // If this operation is not supported, lower it to constant 1 3726 Result = DAG.getConstant(1, VT); 3727 break; 3728 } 3729 } 3730 case ISD::TRAP: { 3731 MVT::ValueType VT = Node->getValueType(0); 3732 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3733 default: assert(0 && "This action not supported for this op yet!"); 3734 case TargetLowering::Legal: 3735 Tmp1 = LegalizeOp(Node->getOperand(0)); 3736 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3737 break; 3738 case TargetLowering::Custom: 3739 Result = TLI.LowerOperation(Op, DAG); 3740 if (Result.Val) break; 3741 // Fall Thru 3742 case TargetLowering::Expand: 3743 // If this operation is not supported, lower it to 'abort()' call 3744 Tmp1 = LegalizeOp(Node->getOperand(0)); 3745 TargetLowering::ArgListTy Args; 3746 std::pair<SDOperand,SDOperand> CallResult = 3747 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 3748 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 3749 Args, DAG); 3750 Result = CallResult.second; 3751 break; 3752 } 3753 break; 3754 } 3755 } 3756 3757 assert(Result.getValueType() == Op.getValueType() && 3758 "Bad legalization!"); 3759 3760 // Make sure that the generated code is itself legal. 3761 if (Result != Op) 3762 Result = LegalizeOp(Result); 3763 3764 // Note that LegalizeOp may be reentered even from single-use nodes, which 3765 // means that we always must cache transformed nodes. 3766 AddLegalizedOperand(Op, Result); 3767 return Result; 3768} 3769 3770/// PromoteOp - Given an operation that produces a value in an invalid type, 3771/// promote it to compute the value into a larger type. The produced value will 3772/// have the correct bits for the low portion of the register, but no guarantee 3773/// is made about the top bits: it may be zero, sign-extended, or garbage. 3774SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 3775 MVT::ValueType VT = Op.getValueType(); 3776 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3777 assert(getTypeAction(VT) == Promote && 3778 "Caller should expand or legalize operands that are not promotable!"); 3779 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 3780 "Cannot promote to smaller type!"); 3781 3782 SDOperand Tmp1, Tmp2, Tmp3; 3783 SDOperand Result; 3784 SDNode *Node = Op.Val; 3785 3786 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 3787 if (I != PromotedNodes.end()) return I->second; 3788 3789 switch (Node->getOpcode()) { 3790 case ISD::CopyFromReg: 3791 assert(0 && "CopyFromReg must be legal!"); 3792 default: 3793#ifndef NDEBUG 3794 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 3795#endif 3796 assert(0 && "Do not know how to promote this operator!"); 3797 abort(); 3798 case ISD::UNDEF: 3799 Result = DAG.getNode(ISD::UNDEF, NVT); 3800 break; 3801 case ISD::Constant: 3802 if (VT != MVT::i1) 3803 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 3804 else 3805 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 3806 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 3807 break; 3808 case ISD::ConstantFP: 3809 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 3810 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 3811 break; 3812 3813 case ISD::SETCC: 3814 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 3815 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 3816 Node->getOperand(1), Node->getOperand(2)); 3817 break; 3818 3819 case ISD::TRUNCATE: 3820 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3821 case Legal: 3822 Result = LegalizeOp(Node->getOperand(0)); 3823 assert(Result.getValueType() >= NVT && 3824 "This truncation doesn't make sense!"); 3825 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 3826 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 3827 break; 3828 case Promote: 3829 // The truncation is not required, because we don't guarantee anything 3830 // about high bits anyway. 3831 Result = PromoteOp(Node->getOperand(0)); 3832 break; 3833 case Expand: 3834 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3835 // Truncate the low part of the expanded value to the result type 3836 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 3837 } 3838 break; 3839 case ISD::SIGN_EXTEND: 3840 case ISD::ZERO_EXTEND: 3841 case ISD::ANY_EXTEND: 3842 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3843 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 3844 case Legal: 3845 // Input is legal? Just do extend all the way to the larger type. 3846 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3847 break; 3848 case Promote: 3849 // Promote the reg if it's smaller. 3850 Result = PromoteOp(Node->getOperand(0)); 3851 // The high bits are not guaranteed to be anything. Insert an extend. 3852 if (Node->getOpcode() == ISD::SIGN_EXTEND) 3853 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3854 DAG.getValueType(Node->getOperand(0).getValueType())); 3855 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 3856 Result = DAG.getZeroExtendInReg(Result, 3857 Node->getOperand(0).getValueType()); 3858 break; 3859 } 3860 break; 3861 case ISD::BIT_CONVERT: 3862 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3863 Node->getValueType(0)); 3864 Result = PromoteOp(Result); 3865 break; 3866 3867 case ISD::FP_EXTEND: 3868 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 3869 case ISD::FP_ROUND: 3870 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3871 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 3872 case Promote: assert(0 && "Unreachable with 2 FP types!"); 3873 case Legal: 3874 if (Node->getConstantOperandVal(1) == 0) { 3875 // Input is legal? Do an FP_ROUND_INREG. 3876 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 3877 DAG.getValueType(VT)); 3878 } else { 3879 // Just remove the truncate, it isn't affecting the value. 3880 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 3881 Node->getOperand(1)); 3882 } 3883 break; 3884 } 3885 break; 3886 case ISD::SINT_TO_FP: 3887 case ISD::UINT_TO_FP: 3888 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3889 case Legal: 3890 // No extra round required here. 3891 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3892 break; 3893 3894 case Promote: 3895 Result = PromoteOp(Node->getOperand(0)); 3896 if (Node->getOpcode() == ISD::SINT_TO_FP) 3897 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3898 Result, 3899 DAG.getValueType(Node->getOperand(0).getValueType())); 3900 else 3901 Result = DAG.getZeroExtendInReg(Result, 3902 Node->getOperand(0).getValueType()); 3903 // No extra round required here. 3904 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3905 break; 3906 case Expand: 3907 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3908 Node->getOperand(0)); 3909 // Round if we cannot tolerate excess precision. 3910 if (NoExcessFPPrecision) 3911 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3912 DAG.getValueType(VT)); 3913 break; 3914 } 3915 break; 3916 3917 case ISD::SIGN_EXTEND_INREG: 3918 Result = PromoteOp(Node->getOperand(0)); 3919 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3920 Node->getOperand(1)); 3921 break; 3922 case ISD::FP_TO_SINT: 3923 case ISD::FP_TO_UINT: 3924 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3925 case Legal: 3926 case Expand: 3927 Tmp1 = Node->getOperand(0); 3928 break; 3929 case Promote: 3930 // The input result is prerounded, so we don't have to do anything 3931 // special. 3932 Tmp1 = PromoteOp(Node->getOperand(0)); 3933 break; 3934 } 3935 // If we're promoting a UINT to a larger size, check to see if the new node 3936 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3937 // we can use that instead. This allows us to generate better code for 3938 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3939 // legal, such as PowerPC. 3940 if (Node->getOpcode() == ISD::FP_TO_UINT && 3941 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3942 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3943 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3944 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3945 } else { 3946 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3947 } 3948 break; 3949 3950 case ISD::FABS: 3951 case ISD::FNEG: 3952 Tmp1 = PromoteOp(Node->getOperand(0)); 3953 assert(Tmp1.getValueType() == NVT); 3954 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3955 // NOTE: we do not have to do any extra rounding here for 3956 // NoExcessFPPrecision, because we know the input will have the appropriate 3957 // precision, and these operations don't modify precision at all. 3958 break; 3959 3960 case ISD::FSQRT: 3961 case ISD::FSIN: 3962 case ISD::FCOS: 3963 Tmp1 = PromoteOp(Node->getOperand(0)); 3964 assert(Tmp1.getValueType() == NVT); 3965 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3966 if (NoExcessFPPrecision) 3967 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3968 DAG.getValueType(VT)); 3969 break; 3970 3971 case ISD::FPOWI: { 3972 // Promote f32 powi to f64 powi. Note that this could insert a libcall 3973 // directly as well, which may be better. 3974 Tmp1 = PromoteOp(Node->getOperand(0)); 3975 assert(Tmp1.getValueType() == NVT); 3976 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 3977 if (NoExcessFPPrecision) 3978 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3979 DAG.getValueType(VT)); 3980 break; 3981 } 3982 3983 case ISD::AND: 3984 case ISD::OR: 3985 case ISD::XOR: 3986 case ISD::ADD: 3987 case ISD::SUB: 3988 case ISD::MUL: 3989 // The input may have strange things in the top bits of the registers, but 3990 // these operations don't care. They may have weird bits going out, but 3991 // that too is okay if they are integer operations. 3992 Tmp1 = PromoteOp(Node->getOperand(0)); 3993 Tmp2 = PromoteOp(Node->getOperand(1)); 3994 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3995 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3996 break; 3997 case ISD::FADD: 3998 case ISD::FSUB: 3999 case ISD::FMUL: 4000 Tmp1 = PromoteOp(Node->getOperand(0)); 4001 Tmp2 = PromoteOp(Node->getOperand(1)); 4002 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4003 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4004 4005 // Floating point operations will give excess precision that we may not be 4006 // able to tolerate. If we DO allow excess precision, just leave it, 4007 // otherwise excise it. 4008 // FIXME: Why would we need to round FP ops more than integer ones? 4009 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4010 if (NoExcessFPPrecision) 4011 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4012 DAG.getValueType(VT)); 4013 break; 4014 4015 case ISD::SDIV: 4016 case ISD::SREM: 4017 // These operators require that their input be sign extended. 4018 Tmp1 = PromoteOp(Node->getOperand(0)); 4019 Tmp2 = PromoteOp(Node->getOperand(1)); 4020 if (MVT::isInteger(NVT)) { 4021 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4022 DAG.getValueType(VT)); 4023 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4024 DAG.getValueType(VT)); 4025 } 4026 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4027 4028 // Perform FP_ROUND: this is probably overly pessimistic. 4029 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 4030 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4031 DAG.getValueType(VT)); 4032 break; 4033 case ISD::FDIV: 4034 case ISD::FREM: 4035 case ISD::FCOPYSIGN: 4036 // These operators require that their input be fp extended. 4037 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4038 case Expand: assert(0 && "not implemented"); 4039 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4040 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4041 } 4042 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4043 case Expand: assert(0 && "not implemented"); 4044 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4045 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4046 } 4047 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4048 4049 // Perform FP_ROUND: this is probably overly pessimistic. 4050 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4051 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4052 DAG.getValueType(VT)); 4053 break; 4054 4055 case ISD::UDIV: 4056 case ISD::UREM: 4057 // These operators require that their input be zero extended. 4058 Tmp1 = PromoteOp(Node->getOperand(0)); 4059 Tmp2 = PromoteOp(Node->getOperand(1)); 4060 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 4061 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4062 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4063 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4064 break; 4065 4066 case ISD::SHL: 4067 Tmp1 = PromoteOp(Node->getOperand(0)); 4068 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4069 break; 4070 case ISD::SRA: 4071 // The input value must be properly sign extended. 4072 Tmp1 = PromoteOp(Node->getOperand(0)); 4073 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4074 DAG.getValueType(VT)); 4075 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4076 break; 4077 case ISD::SRL: 4078 // The input value must be properly zero extended. 4079 Tmp1 = PromoteOp(Node->getOperand(0)); 4080 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4081 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4082 break; 4083 4084 case ISD::VAARG: 4085 Tmp1 = Node->getOperand(0); // Get the chain. 4086 Tmp2 = Node->getOperand(1); // Get the pointer. 4087 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4088 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4089 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 4090 } else { 4091 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 4092 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 4093 SV->getValue(), SV->getOffset()); 4094 // Increment the pointer, VAList, to the next vaarg 4095 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4096 DAG.getConstant(MVT::getSizeInBits(VT)/8, 4097 TLI.getPointerTy())); 4098 // Store the incremented VAList to the legalized pointer 4099 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 4100 SV->getOffset()); 4101 // Load the actual argument out of the pointer VAList 4102 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4103 } 4104 // Remember that we legalized the chain. 4105 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4106 break; 4107 4108 case ISD::LOAD: { 4109 LoadSDNode *LD = cast<LoadSDNode>(Node); 4110 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4111 ? ISD::EXTLOAD : LD->getExtensionType(); 4112 Result = DAG.getExtLoad(ExtType, NVT, 4113 LD->getChain(), LD->getBasePtr(), 4114 LD->getSrcValue(), LD->getSrcValueOffset(), 4115 LD->getLoadedVT(), 4116 LD->isVolatile(), 4117 LD->getAlignment()); 4118 // Remember that we legalized the chain. 4119 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4120 break; 4121 } 4122 case ISD::SELECT: 4123 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4124 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4125 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 4126 break; 4127 case ISD::SELECT_CC: 4128 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4129 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4130 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4131 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4132 break; 4133 case ISD::BSWAP: 4134 Tmp1 = Node->getOperand(0); 4135 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4136 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4137 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4138 DAG.getConstant(MVT::getSizeInBits(NVT) - 4139 MVT::getSizeInBits(VT), 4140 TLI.getShiftAmountTy())); 4141 break; 4142 case ISD::CTPOP: 4143 case ISD::CTTZ: 4144 case ISD::CTLZ: 4145 // Zero extend the argument 4146 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4147 // Perform the larger operation, then subtract if needed. 4148 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4149 switch(Node->getOpcode()) { 4150 case ISD::CTPOP: 4151 Result = Tmp1; 4152 break; 4153 case ISD::CTTZ: 4154 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4155 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 4156 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 4157 ISD::SETEQ); 4158 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4159 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); 4160 break; 4161 case ISD::CTLZ: 4162 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4163 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4164 DAG.getConstant(MVT::getSizeInBits(NVT) - 4165 MVT::getSizeInBits(VT), NVT)); 4166 break; 4167 } 4168 break; 4169 case ISD::EXTRACT_SUBVECTOR: 4170 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4171 break; 4172 case ISD::EXTRACT_VECTOR_ELT: 4173 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4174 break; 4175 } 4176 4177 assert(Result.Val && "Didn't set a result!"); 4178 4179 // Make sure the result is itself legal. 4180 Result = LegalizeOp(Result); 4181 4182 // Remember that we promoted this! 4183 AddPromotedOperand(Op, Result); 4184 return Result; 4185} 4186 4187/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4188/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4189/// based on the vector type. The return type of this matches the element type 4190/// of the vector, which may not be legal for the target. 4191SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 4192 // We know that operand #0 is the Vec vector. If the index is a constant 4193 // or if the invec is a supported hardware type, we can use it. Otherwise, 4194 // lower to a store then an indexed load. 4195 SDOperand Vec = Op.getOperand(0); 4196 SDOperand Idx = Op.getOperand(1); 4197 4198 MVT::ValueType TVT = Vec.getValueType(); 4199 unsigned NumElems = MVT::getVectorNumElements(TVT); 4200 4201 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4202 default: assert(0 && "This action is not supported yet!"); 4203 case TargetLowering::Custom: { 4204 Vec = LegalizeOp(Vec); 4205 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4206 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 4207 if (Tmp3.Val) 4208 return Tmp3; 4209 break; 4210 } 4211 case TargetLowering::Legal: 4212 if (isTypeLegal(TVT)) { 4213 Vec = LegalizeOp(Vec); 4214 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4215 return Op; 4216 } 4217 break; 4218 case TargetLowering::Expand: 4219 break; 4220 } 4221 4222 if (NumElems == 1) { 4223 // This must be an access of the only element. Return it. 4224 Op = ScalarizeVectorOp(Vec); 4225 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4226 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4227 SDOperand Lo, Hi; 4228 SplitVectorOp(Vec, Lo, Hi); 4229 if (CIdx->getValue() < NumElems/2) { 4230 Vec = Lo; 4231 } else { 4232 Vec = Hi; 4233 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, 4234 Idx.getValueType()); 4235 } 4236 4237 // It's now an extract from the appropriate high or low part. Recurse. 4238 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4239 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4240 } else { 4241 // Store the value to a temporary stack slot, then LOAD the scalar 4242 // element back out. 4243 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4244 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4245 4246 // Add the offset to the index. 4247 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 4248 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4249 DAG.getConstant(EltSize, Idx.getValueType())); 4250 4251 if (MVT::getSizeInBits(Idx.getValueType()) > 4252 MVT::getSizeInBits(TLI.getPointerTy())) 4253 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4254 else 4255 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4256 4257 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4258 4259 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4260 } 4261 return Op; 4262} 4263 4264/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4265/// we assume the operation can be split if it is not already legal. 4266SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 4267 // We know that operand #0 is the Vec vector. For now we assume the index 4268 // is a constant and that the extracted result is a supported hardware type. 4269 SDOperand Vec = Op.getOperand(0); 4270 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 4271 4272 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); 4273 4274 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { 4275 // This must be an access of the desired vector length. Return it. 4276 return Vec; 4277 } 4278 4279 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4280 SDOperand Lo, Hi; 4281 SplitVectorOp(Vec, Lo, Hi); 4282 if (CIdx->getValue() < NumElems/2) { 4283 Vec = Lo; 4284 } else { 4285 Vec = Hi; 4286 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4287 } 4288 4289 // It's now an extract from the appropriate high or low part. Recurse. 4290 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4291 return ExpandEXTRACT_SUBVECTOR(Op); 4292} 4293 4294/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4295/// with condition CC on the current target. This usually involves legalizing 4296/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4297/// there may be no choice but to create a new SetCC node to represent the 4298/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4299/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 4300void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 4301 SDOperand &RHS, 4302 SDOperand &CC) { 4303 SDOperand Tmp1, Tmp2, Tmp3, Result; 4304 4305 switch (getTypeAction(LHS.getValueType())) { 4306 case Legal: 4307 Tmp1 = LegalizeOp(LHS); // LHS 4308 Tmp2 = LegalizeOp(RHS); // RHS 4309 break; 4310 case Promote: 4311 Tmp1 = PromoteOp(LHS); // LHS 4312 Tmp2 = PromoteOp(RHS); // RHS 4313 4314 // If this is an FP compare, the operands have already been extended. 4315 if (MVT::isInteger(LHS.getValueType())) { 4316 MVT::ValueType VT = LHS.getValueType(); 4317 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4318 4319 // Otherwise, we have to insert explicit sign or zero extends. Note 4320 // that we could insert sign extends for ALL conditions, but zero extend 4321 // is cheaper on many machines (an AND instead of two shifts), so prefer 4322 // it. 4323 switch (cast<CondCodeSDNode>(CC)->get()) { 4324 default: assert(0 && "Unknown integer comparison!"); 4325 case ISD::SETEQ: 4326 case ISD::SETNE: 4327 case ISD::SETUGE: 4328 case ISD::SETUGT: 4329 case ISD::SETULE: 4330 case ISD::SETULT: 4331 // ALL of these operations will work if we either sign or zero extend 4332 // the operands (including the unsigned comparisons!). Zero extend is 4333 // usually a simpler/cheaper operation, so prefer it. 4334 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4335 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4336 break; 4337 case ISD::SETGE: 4338 case ISD::SETGT: 4339 case ISD::SETLT: 4340 case ISD::SETLE: 4341 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4342 DAG.getValueType(VT)); 4343 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4344 DAG.getValueType(VT)); 4345 break; 4346 } 4347 } 4348 break; 4349 case Expand: { 4350 MVT::ValueType VT = LHS.getValueType(); 4351 if (VT == MVT::f32 || VT == MVT::f64) { 4352 // Expand into one or more soft-fp libcall(s). 4353 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 4354 switch (cast<CondCodeSDNode>(CC)->get()) { 4355 case ISD::SETEQ: 4356 case ISD::SETOEQ: 4357 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4358 break; 4359 case ISD::SETNE: 4360 case ISD::SETUNE: 4361 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4362 break; 4363 case ISD::SETGE: 4364 case ISD::SETOGE: 4365 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4366 break; 4367 case ISD::SETLT: 4368 case ISD::SETOLT: 4369 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4370 break; 4371 case ISD::SETLE: 4372 case ISD::SETOLE: 4373 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4374 break; 4375 case ISD::SETGT: 4376 case ISD::SETOGT: 4377 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4378 break; 4379 case ISD::SETUO: 4380 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4381 break; 4382 case ISD::SETO: 4383 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4384 break; 4385 default: 4386 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4387 switch (cast<CondCodeSDNode>(CC)->get()) { 4388 case ISD::SETONE: 4389 // SETONE = SETOLT | SETOGT 4390 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4391 // Fallthrough 4392 case ISD::SETUGT: 4393 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4394 break; 4395 case ISD::SETUGE: 4396 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4397 break; 4398 case ISD::SETULT: 4399 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4400 break; 4401 case ISD::SETULE: 4402 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4403 break; 4404 case ISD::SETUEQ: 4405 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4406 break; 4407 default: assert(0 && "Unsupported FP setcc!"); 4408 } 4409 } 4410 4411 SDOperand Dummy; 4412 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 4413 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4414 false /*sign irrelevant*/, Dummy); 4415 Tmp2 = DAG.getConstant(0, MVT::i32); 4416 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4417 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4418 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); 4419 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 4420 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4421 false /*sign irrelevant*/, Dummy); 4422 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, 4423 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4424 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4425 Tmp2 = SDOperand(); 4426 } 4427 LHS = Tmp1; 4428 RHS = Tmp2; 4429 return; 4430 } 4431 4432 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4433 ExpandOp(LHS, LHSLo, LHSHi); 4434 ExpandOp(RHS, RHSLo, RHSHi); 4435 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4436 4437 if (VT==MVT::ppcf128) { 4438 // FIXME: This generated code sucks. We want to generate 4439 // FCMP crN, hi1, hi2 4440 // BNE crN, L: 4441 // FCMP crN, lo1, lo2 4442 // The following can be improved, but not that much. 4443 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4444 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode); 4445 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4446 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE); 4447 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode); 4448 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4449 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4450 Tmp2 = SDOperand(); 4451 break; 4452 } 4453 4454 switch (CCCode) { 4455 case ISD::SETEQ: 4456 case ISD::SETNE: 4457 if (RHSLo == RHSHi) 4458 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4459 if (RHSCST->isAllOnesValue()) { 4460 // Comparison to -1. 4461 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4462 Tmp2 = RHSLo; 4463 break; 4464 } 4465 4466 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4467 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4468 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4469 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4470 break; 4471 default: 4472 // If this is a comparison of the sign bit, just look at the top part. 4473 // X > -1, x < 0 4474 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4475 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4476 CST->getValue() == 0) || // X < 0 4477 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4478 CST->isAllOnesValue())) { // X > -1 4479 Tmp1 = LHSHi; 4480 Tmp2 = RHSHi; 4481 break; 4482 } 4483 4484 // FIXME: This generated code sucks. 4485 ISD::CondCode LowCC; 4486 switch (CCCode) { 4487 default: assert(0 && "Unknown integer setcc!"); 4488 case ISD::SETLT: 4489 case ISD::SETULT: LowCC = ISD::SETULT; break; 4490 case ISD::SETGT: 4491 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4492 case ISD::SETLE: 4493 case ISD::SETULE: LowCC = ISD::SETULE; break; 4494 case ISD::SETGE: 4495 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4496 } 4497 4498 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4499 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4500 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4501 4502 // NOTE: on targets without efficient SELECT of bools, we can always use 4503 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4504 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4505 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, 4506 false, DagCombineInfo); 4507 if (!Tmp1.Val) 4508 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 4509 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4510 CCCode, false, DagCombineInfo); 4511 if (!Tmp2.Val) 4512 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC); 4513 4514 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4515 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4516 if ((Tmp1C && Tmp1C->getValue() == 0) || 4517 (Tmp2C && Tmp2C->getValue() == 0 && 4518 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4519 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4520 (Tmp2C && Tmp2C->getValue() == 1 && 4521 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4522 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4523 // low part is known false, returns high part. 4524 // For LE / GE, if high part is known false, ignore the low part. 4525 // For LT / GT, if high part is known true, ignore the low part. 4526 Tmp1 = Tmp2; 4527 Tmp2 = SDOperand(); 4528 } else { 4529 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4530 ISD::SETEQ, false, DagCombineInfo); 4531 if (!Result.Val) 4532 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4533 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4534 Result, Tmp1, Tmp2)); 4535 Tmp1 = Result; 4536 Tmp2 = SDOperand(); 4537 } 4538 } 4539 } 4540 } 4541 LHS = Tmp1; 4542 RHS = Tmp2; 4543} 4544 4545/// EmitStackConvert - Emit a store/load combination to the stack. This stores 4546/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 4547/// a load from the stack slot to DestVT, extending it if needed. 4548/// The resultant code need not be legal. 4549SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, 4550 MVT::ValueType SlotVT, 4551 MVT::ValueType DestVT) { 4552 // Create the stack frame object. 4553 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); 4554 4555 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType()); 4556 unsigned SlotSize = MVT::getSizeInBits(SlotVT); 4557 unsigned DestSize = MVT::getSizeInBits(DestVT); 4558 4559 // Emit a store to the stack slot. Use a truncstore if the input value is 4560 // later than DestVT. 4561 SDOperand Store; 4562 if (SrcSize > SlotSize) 4563 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0,SlotVT); 4564 else { 4565 assert(SrcSize == SlotSize && "Invalid store"); 4566 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); 4567 } 4568 4569 // Result is a load from the stack slot. 4570 if (SlotSize == DestSize) 4571 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4572 4573 assert(SlotSize < DestSize && "Unknown extension!"); 4574 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT); 4575} 4576 4577SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4578 // Create a vector sized/aligned stack slot, store the value to element #0, 4579 // then load the whole vector back out. 4580 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4581 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4582 NULL, 0); 4583 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); 4584} 4585 4586 4587/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4588/// support the operation, but do support the resultant vector type. 4589SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4590 4591 // If the only non-undef value is the low element, turn this into a 4592 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4593 unsigned NumElems = Node->getNumOperands(); 4594 bool isOnlyLowElement = true; 4595 SDOperand SplatValue = Node->getOperand(0); 4596 std::map<SDOperand, std::vector<unsigned> > Values; 4597 Values[SplatValue].push_back(0); 4598 bool isConstant = true; 4599 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4600 SplatValue.getOpcode() != ISD::UNDEF) 4601 isConstant = false; 4602 4603 for (unsigned i = 1; i < NumElems; ++i) { 4604 SDOperand V = Node->getOperand(i); 4605 Values[V].push_back(i); 4606 if (V.getOpcode() != ISD::UNDEF) 4607 isOnlyLowElement = false; 4608 if (SplatValue != V) 4609 SplatValue = SDOperand(0,0); 4610 4611 // If this isn't a constant element or an undef, we can't use a constant 4612 // pool load. 4613 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4614 V.getOpcode() != ISD::UNDEF) 4615 isConstant = false; 4616 } 4617 4618 if (isOnlyLowElement) { 4619 // If the low element is an undef too, then this whole things is an undef. 4620 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4621 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4622 // Otherwise, turn this into a scalar_to_vector node. 4623 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4624 Node->getOperand(0)); 4625 } 4626 4627 // If all elements are constants, create a load from the constant pool. 4628 if (isConstant) { 4629 MVT::ValueType VT = Node->getValueType(0); 4630 const Type *OpNTy = 4631 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 4632 std::vector<Constant*> CV; 4633 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4634 if (ConstantFPSDNode *V = 4635 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4636 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF())); 4637 } else if (ConstantSDNode *V = 4638 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4639 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 4640 } else { 4641 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4642 CV.push_back(UndefValue::get(OpNTy)); 4643 } 4644 } 4645 Constant *CP = ConstantVector::get(CV); 4646 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4647 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 4648 } 4649 4650 if (SplatValue.Val) { // Splat of one value? 4651 // Build the shuffle constant vector: <0, 0, 0, 0> 4652 MVT::ValueType MaskVT = 4653 MVT::getIntVectorWithNumElements(NumElems); 4654 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); 4655 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4656 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4657 &ZeroVec[0], ZeroVec.size()); 4658 4659 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4660 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 4661 // Get the splatted value into the low element of a vector register. 4662 SDOperand LowValVec = 4663 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 4664 4665 // Return shuffle(LowValVec, undef, <0,0,0,0>) 4666 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 4667 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 4668 SplatMask); 4669 } 4670 } 4671 4672 // If there are only two unique elements, we may be able to turn this into a 4673 // vector shuffle. 4674 if (Values.size() == 2) { 4675 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 4676 MVT::ValueType MaskVT = 4677 MVT::getIntVectorWithNumElements(NumElems); 4678 std::vector<SDOperand> MaskVec(NumElems); 4679 unsigned i = 0; 4680 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4681 E = Values.end(); I != E; ++I) { 4682 for (std::vector<unsigned>::iterator II = I->second.begin(), 4683 EE = I->second.end(); II != EE; ++II) 4684 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT)); 4685 i += NumElems; 4686 } 4687 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4688 &MaskVec[0], MaskVec.size()); 4689 4690 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4691 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 4692 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 4693 SmallVector<SDOperand, 8> Ops; 4694 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4695 E = Values.end(); I != E; ++I) { 4696 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4697 I->first); 4698 Ops.push_back(Op); 4699 } 4700 Ops.push_back(ShuffleMask); 4701 4702 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 4703 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 4704 &Ops[0], Ops.size()); 4705 } 4706 } 4707 4708 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 4709 // aligned object on the stack, store each element into it, then load 4710 // the result as a vector. 4711 MVT::ValueType VT = Node->getValueType(0); 4712 // Create the stack frame object. 4713 SDOperand FIPtr = DAG.CreateStackTemporary(VT); 4714 4715 // Emit a store of each element to the stack slot. 4716 SmallVector<SDOperand, 8> Stores; 4717 unsigned TypeByteSize = 4718 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 4719 // Store (in the right endianness) the elements to memory. 4720 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4721 // Ignore undef elements. 4722 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4723 4724 unsigned Offset = TypeByteSize*i; 4725 4726 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 4727 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 4728 4729 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 4730 NULL, 0)); 4731 } 4732 4733 SDOperand StoreChain; 4734 if (!Stores.empty()) // Not all undef elements? 4735 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4736 &Stores[0], Stores.size()); 4737 else 4738 StoreChain = DAG.getEntryNode(); 4739 4740 // Result is a load from the stack slot. 4741 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 4742} 4743 4744void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 4745 SDOperand Op, SDOperand Amt, 4746 SDOperand &Lo, SDOperand &Hi) { 4747 // Expand the subcomponents. 4748 SDOperand LHSL, LHSH; 4749 ExpandOp(Op, LHSL, LHSH); 4750 4751 SDOperand Ops[] = { LHSL, LHSH, Amt }; 4752 MVT::ValueType VT = LHSL.getValueType(); 4753 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 4754 Hi = Lo.getValue(1); 4755} 4756 4757 4758/// ExpandShift - Try to find a clever way to expand this shift operation out to 4759/// smaller elements. If we can't find a way that is more efficient than a 4760/// libcall on this target, return false. Otherwise, return true with the 4761/// low-parts expanded into Lo and Hi. 4762bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 4763 SDOperand &Lo, SDOperand &Hi) { 4764 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 4765 "This is not a shift!"); 4766 4767 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 4768 SDOperand ShAmt = LegalizeOp(Amt); 4769 MVT::ValueType ShTy = ShAmt.getValueType(); 4770 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 4771 unsigned NVTBits = MVT::getSizeInBits(NVT); 4772 4773 // Handle the case when Amt is an immediate. 4774 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 4775 unsigned Cst = CN->getValue(); 4776 // Expand the incoming operand to be shifted, so that we have its parts 4777 SDOperand InL, InH; 4778 ExpandOp(Op, InL, InH); 4779 switch(Opc) { 4780 case ISD::SHL: 4781 if (Cst > VTBits) { 4782 Lo = DAG.getConstant(0, NVT); 4783 Hi = DAG.getConstant(0, NVT); 4784 } else if (Cst > NVTBits) { 4785 Lo = DAG.getConstant(0, NVT); 4786 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 4787 } else if (Cst == NVTBits) { 4788 Lo = DAG.getConstant(0, NVT); 4789 Hi = InL; 4790 } else { 4791 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 4792 Hi = DAG.getNode(ISD::OR, NVT, 4793 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 4794 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 4795 } 4796 return true; 4797 case ISD::SRL: 4798 if (Cst > VTBits) { 4799 Lo = DAG.getConstant(0, NVT); 4800 Hi = DAG.getConstant(0, NVT); 4801 } else if (Cst > NVTBits) { 4802 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 4803 Hi = DAG.getConstant(0, NVT); 4804 } else if (Cst == NVTBits) { 4805 Lo = InH; 4806 Hi = DAG.getConstant(0, NVT); 4807 } else { 4808 Lo = DAG.getNode(ISD::OR, NVT, 4809 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4810 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4811 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 4812 } 4813 return true; 4814 case ISD::SRA: 4815 if (Cst > VTBits) { 4816 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 4817 DAG.getConstant(NVTBits-1, ShTy)); 4818 } else if (Cst > NVTBits) { 4819 Lo = DAG.getNode(ISD::SRA, NVT, InH, 4820 DAG.getConstant(Cst-NVTBits, ShTy)); 4821 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4822 DAG.getConstant(NVTBits-1, ShTy)); 4823 } else if (Cst == NVTBits) { 4824 Lo = InH; 4825 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4826 DAG.getConstant(NVTBits-1, ShTy)); 4827 } else { 4828 Lo = DAG.getNode(ISD::OR, NVT, 4829 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4830 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4831 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 4832 } 4833 return true; 4834 } 4835 } 4836 4837 // Okay, the shift amount isn't constant. However, if we can tell that it is 4838 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 4839 uint64_t Mask = NVTBits, KnownZero, KnownOne; 4840 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 4841 4842 // If we know that the high bit of the shift amount is one, then we can do 4843 // this as a couple of simple shifts. 4844 if (KnownOne & Mask) { 4845 // Mask out the high bit, which we know is set. 4846 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 4847 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4848 4849 // Expand the incoming operand to be shifted, so that we have its parts 4850 SDOperand InL, InH; 4851 ExpandOp(Op, InL, InH); 4852 switch(Opc) { 4853 case ISD::SHL: 4854 Lo = DAG.getConstant(0, NVT); // Low part is zero. 4855 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 4856 return true; 4857 case ISD::SRL: 4858 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 4859 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 4860 return true; 4861 case ISD::SRA: 4862 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 4863 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4864 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 4865 return true; 4866 } 4867 } 4868 4869 // If we know that the high bit of the shift amount is zero, then we can do 4870 // this as a couple of simple shifts. 4871 if (KnownZero & Mask) { 4872 // Compute 32-amt. 4873 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 4874 DAG.getConstant(NVTBits, Amt.getValueType()), 4875 Amt); 4876 4877 // Expand the incoming operand to be shifted, so that we have its parts 4878 SDOperand InL, InH; 4879 ExpandOp(Op, InL, InH); 4880 switch(Opc) { 4881 case ISD::SHL: 4882 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 4883 Hi = DAG.getNode(ISD::OR, NVT, 4884 DAG.getNode(ISD::SHL, NVT, InH, Amt), 4885 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 4886 return true; 4887 case ISD::SRL: 4888 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 4889 Lo = DAG.getNode(ISD::OR, NVT, 4890 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4891 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4892 return true; 4893 case ISD::SRA: 4894 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 4895 Lo = DAG.getNode(ISD::OR, NVT, 4896 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4897 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4898 return true; 4899 } 4900 } 4901 4902 return false; 4903} 4904 4905 4906// ExpandLibCall - Expand a node into a call to a libcall. If the result value 4907// does not fit into a register, return the lo part and set the hi part to the 4908// by-reg argument. If it does fit into a single register, return the result 4909// and leave the Hi part unset. 4910SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 4911 bool isSigned, SDOperand &Hi) { 4912 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 4913 // The input chain to this libcall is the entry node of the function. 4914 // Legalizing the call will automatically add the previous call to the 4915 // dependence. 4916 SDOperand InChain = DAG.getEntryNode(); 4917 4918 TargetLowering::ArgListTy Args; 4919 TargetLowering::ArgListEntry Entry; 4920 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4921 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 4922 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 4923 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 4924 Entry.isSExt = isSigned; 4925 Args.push_back(Entry); 4926 } 4927 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 4928 4929 // Splice the libcall in wherever FindInputOutputChains tells us to. 4930 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 4931 std::pair<SDOperand,SDOperand> CallInfo = 4932 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false, 4933 Callee, Args, DAG); 4934 4935 // Legalize the call sequence, starting with the chain. This will advance 4936 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 4937 // was added by LowerCallTo (guaranteeing proper serialization of calls). 4938 LegalizeOp(CallInfo.second); 4939 SDOperand Result; 4940 switch (getTypeAction(CallInfo.first.getValueType())) { 4941 default: assert(0 && "Unknown thing"); 4942 case Legal: 4943 Result = CallInfo.first; 4944 break; 4945 case Expand: 4946 ExpandOp(CallInfo.first, Result, Hi); 4947 break; 4948 } 4949 return Result; 4950} 4951 4952 4953/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 4954/// 4955SDOperand SelectionDAGLegalize:: 4956ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 4957 assert(getTypeAction(Source.getValueType()) == Expand && 4958 "This is not an expansion!"); 4959 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 4960 4961 if (!isSigned) { 4962 assert(Source.getValueType() == MVT::i64 && 4963 "This only works for 64-bit -> FP"); 4964 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 4965 // incoming integer is set. To handle this, we dynamically test to see if 4966 // it is set, and, if so, add a fudge factor. 4967 SDOperand Lo, Hi; 4968 ExpandOp(Source, Lo, Hi); 4969 4970 // If this is unsigned, and not supported, first perform the conversion to 4971 // signed, then adjust the result if the sign bit is set. 4972 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 4973 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 4974 4975 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 4976 DAG.getConstant(0, Hi.getValueType()), 4977 ISD::SETLT); 4978 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 4979 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4980 SignSet, Four, Zero); 4981 uint64_t FF = 0x5f800000ULL; 4982 if (TLI.isLittleEndian()) FF <<= 32; 4983 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4984 4985 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4986 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4987 SDOperand FudgeInReg; 4988 if (DestTy == MVT::f32) 4989 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4990 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) 4991 // FIXME: Avoid the extend by construction the right constantpool? 4992 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 4993 CPIdx, NULL, 0, MVT::f32); 4994 else 4995 assert(0 && "Unexpected conversion"); 4996 4997 MVT::ValueType SCVT = SignedConv.getValueType(); 4998 if (SCVT != DestTy) { 4999 // Destination type needs to be expanded as well. The FADD now we are 5000 // constructing will be expanded into a libcall. 5001 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { 5002 assert(SCVT == MVT::i32 && DestTy == MVT::f64); 5003 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, 5004 SignedConv, SignedConv.getValue(1)); 5005 } 5006 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5007 } 5008 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5009 } 5010 5011 // Check to see if the target has a custom way to lower this. If so, use it. 5012 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 5013 default: assert(0 && "This action not implemented for this operation!"); 5014 case TargetLowering::Legal: 5015 case TargetLowering::Expand: 5016 break; // This case is handled below. 5017 case TargetLowering::Custom: { 5018 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5019 Source), DAG); 5020 if (NV.Val) 5021 return LegalizeOp(NV); 5022 break; // The target decided this was legal after all 5023 } 5024 } 5025 5026 // Expand the source, then glue it back together for the call. We must expand 5027 // the source in case it is shared (this pass of legalize must traverse it). 5028 SDOperand SrcLo, SrcHi; 5029 ExpandOp(Source, SrcLo, SrcHi); 5030 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 5031 5032 RTLIB::Libcall LC; 5033 if (DestTy == MVT::f32) 5034 LC = RTLIB::SINTTOFP_I64_F32; 5035 else { 5036 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 5037 LC = RTLIB::SINTTOFP_I64_F64; 5038 } 5039 5040 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 5041 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5042 SDOperand UnusedHiPart; 5043 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 5044 UnusedHiPart); 5045} 5046 5047/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5048/// INT_TO_FP operation of the specified operand when the target requests that 5049/// we expand it. At this point, we know that the result and operand types are 5050/// legal for the target. 5051SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5052 SDOperand Op0, 5053 MVT::ValueType DestVT) { 5054 if (Op0.getValueType() == MVT::i32) { 5055 // simple 32-bit [signed|unsigned] integer to float/double expansion 5056 5057 // Get the stack frame index of a 8 byte buffer. 5058 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64); 5059 5060 // word offset constant for Hi/Lo address computation 5061 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5062 // set up Hi and Lo (into buffer) address based on endian 5063 SDOperand Hi = StackSlot; 5064 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5065 if (TLI.isLittleEndian()) 5066 std::swap(Hi, Lo); 5067 5068 // if signed map to unsigned space 5069 SDOperand Op0Mapped; 5070 if (isSigned) { 5071 // constant used to invert sign bit (signed to unsigned mapping) 5072 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5073 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5074 } else { 5075 Op0Mapped = Op0; 5076 } 5077 // store the lo of the constructed double - based on integer input 5078 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 5079 Op0Mapped, Lo, NULL, 0); 5080 // initial hi portion of constructed double 5081 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5082 // store the hi of the constructed double - biased exponent 5083 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5084 // load the constructed double 5085 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5086 // FP constant to bias correct the final result 5087 SDOperand Bias = DAG.getConstantFP(isSigned ? 5088 BitsToDouble(0x4330000080000000ULL) 5089 : BitsToDouble(0x4330000000000000ULL), 5090 MVT::f64); 5091 // subtract the bias 5092 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5093 // final result 5094 SDOperand Result; 5095 // handle final rounding 5096 if (DestVT == MVT::f64) { 5097 // do nothing 5098 Result = Sub; 5099 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) { 5100 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 5101 DAG.getIntPtrConstant(0)); 5102 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) { 5103 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5104 } 5105 return Result; 5106 } 5107 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5108 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5109 5110 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 5111 DAG.getConstant(0, Op0.getValueType()), 5112 ISD::SETLT); 5113 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5114 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5115 SignSet, Four, Zero); 5116 5117 // If the sign bit of the integer is set, the large number will be treated 5118 // as a negative number. To counteract this, the dynamic code adds an 5119 // offset depending on the data type. 5120 uint64_t FF; 5121 switch (Op0.getValueType()) { 5122 default: assert(0 && "Unsupported integer type!"); 5123 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5124 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5125 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5126 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5127 } 5128 if (TLI.isLittleEndian()) FF <<= 32; 5129 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5130 5131 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5132 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5133 SDOperand FudgeInReg; 5134 if (DestVT == MVT::f32) 5135 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 5136 else { 5137 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5138 DAG.getEntryNode(), CPIdx, 5139 NULL, 0, MVT::f32)); 5140 } 5141 5142 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5143} 5144 5145/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5146/// *INT_TO_FP operation of the specified operand when the target requests that 5147/// we promote it. At this point, we know that the result and operand types are 5148/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5149/// operation that takes a larger input. 5150SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 5151 MVT::ValueType DestVT, 5152 bool isSigned) { 5153 // First step, figure out the appropriate *INT_TO_FP operation to use. 5154 MVT::ValueType NewInTy = LegalOp.getValueType(); 5155 5156 unsigned OpToUse = 0; 5157 5158 // Scan for the appropriate larger type to use. 5159 while (1) { 5160 NewInTy = (MVT::ValueType)(NewInTy+1); 5161 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 5162 5163 // If the target supports SINT_TO_FP of this type, use it. 5164 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5165 default: break; 5166 case TargetLowering::Legal: 5167 if (!TLI.isTypeLegal(NewInTy)) 5168 break; // Can't use this datatype. 5169 // FALL THROUGH. 5170 case TargetLowering::Custom: 5171 OpToUse = ISD::SINT_TO_FP; 5172 break; 5173 } 5174 if (OpToUse) break; 5175 if (isSigned) continue; 5176 5177 // If the target supports UINT_TO_FP of this type, use it. 5178 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5179 default: break; 5180 case TargetLowering::Legal: 5181 if (!TLI.isTypeLegal(NewInTy)) 5182 break; // Can't use this datatype. 5183 // FALL THROUGH. 5184 case TargetLowering::Custom: 5185 OpToUse = ISD::UINT_TO_FP; 5186 break; 5187 } 5188 if (OpToUse) break; 5189 5190 // Otherwise, try a larger type. 5191 } 5192 5193 // Okay, we found the operation and type to use. Zero extend our input to the 5194 // desired type then run the operation on it. 5195 return DAG.getNode(OpToUse, DestVT, 5196 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5197 NewInTy, LegalOp)); 5198} 5199 5200/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5201/// FP_TO_*INT operation of the specified operand when the target requests that 5202/// we promote it. At this point, we know that the result and operand types are 5203/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5204/// operation that returns a larger result. 5205SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 5206 MVT::ValueType DestVT, 5207 bool isSigned) { 5208 // First step, figure out the appropriate FP_TO*INT operation to use. 5209 MVT::ValueType NewOutTy = DestVT; 5210 5211 unsigned OpToUse = 0; 5212 5213 // Scan for the appropriate larger type to use. 5214 while (1) { 5215 NewOutTy = (MVT::ValueType)(NewOutTy+1); 5216 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 5217 5218 // If the target supports FP_TO_SINT returning this type, use it. 5219 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5220 default: break; 5221 case TargetLowering::Legal: 5222 if (!TLI.isTypeLegal(NewOutTy)) 5223 break; // Can't use this datatype. 5224 // FALL THROUGH. 5225 case TargetLowering::Custom: 5226 OpToUse = ISD::FP_TO_SINT; 5227 break; 5228 } 5229 if (OpToUse) break; 5230 5231 // If the target supports FP_TO_UINT of this type, use it. 5232 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5233 default: break; 5234 case TargetLowering::Legal: 5235 if (!TLI.isTypeLegal(NewOutTy)) 5236 break; // Can't use this datatype. 5237 // FALL THROUGH. 5238 case TargetLowering::Custom: 5239 OpToUse = ISD::FP_TO_UINT; 5240 break; 5241 } 5242 if (OpToUse) break; 5243 5244 // Otherwise, try a larger type. 5245 } 5246 5247 5248 // Okay, we found the operation and type to use. 5249 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5250 5251 // If the operation produces an invalid type, it must be custom lowered. Use 5252 // the target lowering hooks to expand it. Just keep the low part of the 5253 // expanded operation, we know that we're truncating anyway. 5254 if (getTypeAction(NewOutTy) == Expand) { 5255 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0); 5256 assert(Operation.Val && "Didn't return anything"); 5257 } 5258 5259 // Truncate the result of the extended FP_TO_*INT operation to the desired 5260 // size. 5261 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5262} 5263 5264/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5265/// 5266SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 5267 MVT::ValueType VT = Op.getValueType(); 5268 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 5269 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5270 switch (VT) { 5271 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5272 case MVT::i16: 5273 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5274 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5275 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5276 case MVT::i32: 5277 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5278 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5279 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5280 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5281 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5282 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5283 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5284 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5285 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5286 case MVT::i64: 5287 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5288 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5289 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5290 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5291 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5292 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5293 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5294 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5295 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5296 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5297 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5298 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5299 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5300 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5301 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5302 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5303 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5304 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5305 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5306 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5307 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5308 } 5309} 5310 5311/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5312/// 5313SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 5314 switch (Opc) { 5315 default: assert(0 && "Cannot expand this yet!"); 5316 case ISD::CTPOP: { 5317 static const uint64_t mask[6] = { 5318 0x5555555555555555ULL, 0x3333333333333333ULL, 5319 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5320 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5321 }; 5322 MVT::ValueType VT = Op.getValueType(); 5323 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5324 unsigned len = MVT::getSizeInBits(VT); 5325 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5326 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5327 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 5328 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5329 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5330 DAG.getNode(ISD::AND, VT, 5331 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5332 } 5333 return Op; 5334 } 5335 case ISD::CTLZ: { 5336 // for now, we do this: 5337 // x = x | (x >> 1); 5338 // x = x | (x >> 2); 5339 // ... 5340 // x = x | (x >>16); 5341 // x = x | (x >>32); // for 64-bit input 5342 // return popcount(~x); 5343 // 5344 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5345 MVT::ValueType VT = Op.getValueType(); 5346 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5347 unsigned len = MVT::getSizeInBits(VT); 5348 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5349 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5350 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5351 } 5352 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5353 return DAG.getNode(ISD::CTPOP, VT, Op); 5354 } 5355 case ISD::CTTZ: { 5356 // for now, we use: { return popcount(~x & (x - 1)); } 5357 // unless the target has ctlz but not ctpop, in which case we use: 5358 // { return 32 - nlz(~x & (x-1)); } 5359 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5360 MVT::ValueType VT = Op.getValueType(); 5361 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 5362 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 5363 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5364 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5365 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5366 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5367 TLI.isOperationLegal(ISD::CTLZ, VT)) 5368 return DAG.getNode(ISD::SUB, VT, 5369 DAG.getConstant(MVT::getSizeInBits(VT), VT), 5370 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5371 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5372 } 5373 } 5374} 5375 5376/// ExpandOp - Expand the specified SDOperand into its two component pieces 5377/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5378/// LegalizeNodes map is filled in for any results that are not expanded, the 5379/// ExpandedNodes map is filled in for any results that are expanded, and the 5380/// Lo/Hi values are returned. 5381void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 5382 MVT::ValueType VT = Op.getValueType(); 5383 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 5384 SDNode *Node = Op.Val; 5385 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5386 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 5387 MVT::isVector(VT)) && 5388 "Cannot expand to FP value or to larger int value!"); 5389 5390 // See if we already expanded it. 5391 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5392 = ExpandedNodes.find(Op); 5393 if (I != ExpandedNodes.end()) { 5394 Lo = I->second.first; 5395 Hi = I->second.second; 5396 return; 5397 } 5398 5399 switch (Node->getOpcode()) { 5400 case ISD::CopyFromReg: 5401 assert(0 && "CopyFromReg must be legal!"); 5402 case ISD::FP_ROUND_INREG: 5403 if (VT == MVT::ppcf128 && 5404 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5405 TargetLowering::Custom) { 5406 SDOperand SrcLo, SrcHi, Src; 5407 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5408 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5409 SDOperand Result = TLI.LowerOperation( 5410 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5411 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5412 Lo = Result.Val->getOperand(0); 5413 Hi = Result.Val->getOperand(1); 5414 break; 5415 } 5416 // fall through 5417 default: 5418#ifndef NDEBUG 5419 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5420#endif 5421 assert(0 && "Do not know how to expand this operator!"); 5422 abort(); 5423 case ISD::EXTRACT_VECTOR_ELT: 5424 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5425 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5426 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5427 return ExpandOp(Lo, Lo, Hi); 5428 case ISD::UNDEF: 5429 NVT = TLI.getTypeToExpandTo(VT); 5430 Lo = DAG.getNode(ISD::UNDEF, NVT); 5431 Hi = DAG.getNode(ISD::UNDEF, NVT); 5432 break; 5433 case ISD::Constant: { 5434 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 5435 Lo = DAG.getConstant(Cst, NVT); 5436 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 5437 break; 5438 } 5439 case ISD::ConstantFP: { 5440 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5441 if (CFP->getValueType(0) == MVT::ppcf128) { 5442 APInt api = CFP->getValueAPF().convertToAPInt(); 5443 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5444 MVT::f64); 5445 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5446 MVT::f64); 5447 break; 5448 } 5449 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5450 if (getTypeAction(Lo.getValueType()) == Expand) 5451 ExpandOp(Lo, Lo, Hi); 5452 break; 5453 } 5454 case ISD::BUILD_PAIR: 5455 // Return the operands. 5456 Lo = Node->getOperand(0); 5457 Hi = Node->getOperand(1); 5458 break; 5459 5460 case ISD::MERGE_VALUES: 5461 if (Node->getNumValues() == 1) { 5462 ExpandOp(Op.getOperand(0), Lo, Hi); 5463 break; 5464 } 5465 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5466 assert(Op.ResNo == 0 && Node->getNumValues() == 2 && 5467 Op.getValue(1).getValueType() == MVT::Other && 5468 "unhandled MERGE_VALUES"); 5469 ExpandOp(Op.getOperand(0), Lo, Hi); 5470 // Remember that we legalized the chain. 5471 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5472 break; 5473 5474 case ISD::SIGN_EXTEND_INREG: 5475 ExpandOp(Node->getOperand(0), Lo, Hi); 5476 // sext_inreg the low part if needed. 5477 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5478 5479 // The high part gets the sign extension from the lo-part. This handles 5480 // things like sextinreg V:i64 from i8. 5481 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5482 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 5483 TLI.getShiftAmountTy())); 5484 break; 5485 5486 case ISD::BSWAP: { 5487 ExpandOp(Node->getOperand(0), Lo, Hi); 5488 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5489 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5490 Lo = TempLo; 5491 break; 5492 } 5493 5494 case ISD::CTPOP: 5495 ExpandOp(Node->getOperand(0), Lo, Hi); 5496 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5497 DAG.getNode(ISD::CTPOP, NVT, Lo), 5498 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5499 Hi = DAG.getConstant(0, NVT); 5500 break; 5501 5502 case ISD::CTLZ: { 5503 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5504 ExpandOp(Node->getOperand(0), Lo, Hi); 5505 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5506 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5507 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 5508 ISD::SETNE); 5509 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5510 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5511 5512 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5513 Hi = DAG.getConstant(0, NVT); 5514 break; 5515 } 5516 5517 case ISD::CTTZ: { 5518 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5519 ExpandOp(Node->getOperand(0), Lo, Hi); 5520 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5521 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5522 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 5523 ISD::SETNE); 5524 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5525 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5526 5527 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5528 Hi = DAG.getConstant(0, NVT); 5529 break; 5530 } 5531 5532 case ISD::VAARG: { 5533 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5534 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5535 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5536 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5537 5538 // Remember that we legalized the chain. 5539 Hi = LegalizeOp(Hi); 5540 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5541 if (!TLI.isLittleEndian()) 5542 std::swap(Lo, Hi); 5543 break; 5544 } 5545 5546 case ISD::LOAD: { 5547 LoadSDNode *LD = cast<LoadSDNode>(Node); 5548 SDOperand Ch = LD->getChain(); // Legalize the chain. 5549 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5550 ISD::LoadExtType ExtType = LD->getExtensionType(); 5551 int SVOffset = LD->getSrcValueOffset(); 5552 unsigned Alignment = LD->getAlignment(); 5553 bool isVolatile = LD->isVolatile(); 5554 5555 if (ExtType == ISD::NON_EXTLOAD) { 5556 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5557 isVolatile, Alignment); 5558 if (VT == MVT::f32 || VT == MVT::f64) { 5559 // f32->i32 or f64->i64 one to one expansion. 5560 // Remember that we legalized the chain. 5561 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5562 // Recursively expand the new load. 5563 if (getTypeAction(NVT) == Expand) 5564 ExpandOp(Lo, Lo, Hi); 5565 break; 5566 } 5567 5568 // Increment the pointer to the other half. 5569 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 5570 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5571 DAG.getIntPtrConstant(IncrementSize)); 5572 SVOffset += IncrementSize; 5573 Alignment = MinAlign(Alignment, IncrementSize); 5574 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5575 isVolatile, Alignment); 5576 5577 // Build a factor node to remember that this load is independent of the 5578 // other one. 5579 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5580 Hi.getValue(1)); 5581 5582 // Remember that we legalized the chain. 5583 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5584 if (!TLI.isLittleEndian()) 5585 std::swap(Lo, Hi); 5586 } else { 5587 MVT::ValueType EVT = LD->getLoadedVT(); 5588 5589 if ((VT == MVT::f64 && EVT == MVT::f32) || 5590 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 5591 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5592 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5593 SVOffset, isVolatile, Alignment); 5594 // Remember that we legalized the chain. 5595 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 5596 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 5597 break; 5598 } 5599 5600 if (EVT == NVT) 5601 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 5602 SVOffset, isVolatile, Alignment); 5603 else 5604 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 5605 SVOffset, EVT, isVolatile, 5606 Alignment); 5607 5608 // Remember that we legalized the chain. 5609 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5610 5611 if (ExtType == ISD::SEXTLOAD) { 5612 // The high part is obtained by SRA'ing all but one of the bits of the 5613 // lo part. 5614 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5615 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5616 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5617 } else if (ExtType == ISD::ZEXTLOAD) { 5618 // The high part is just a zero. 5619 Hi = DAG.getConstant(0, NVT); 5620 } else /* if (ExtType == ISD::EXTLOAD) */ { 5621 // The high part is undefined. 5622 Hi = DAG.getNode(ISD::UNDEF, NVT); 5623 } 5624 } 5625 break; 5626 } 5627 case ISD::AND: 5628 case ISD::OR: 5629 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 5630 SDOperand LL, LH, RL, RH; 5631 ExpandOp(Node->getOperand(0), LL, LH); 5632 ExpandOp(Node->getOperand(1), RL, RH); 5633 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 5634 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 5635 break; 5636 } 5637 case ISD::SELECT: { 5638 SDOperand LL, LH, RL, RH; 5639 ExpandOp(Node->getOperand(1), LL, LH); 5640 ExpandOp(Node->getOperand(2), RL, RH); 5641 if (getTypeAction(NVT) == Expand) 5642 NVT = TLI.getTypeToExpandTo(NVT); 5643 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 5644 if (VT != MVT::f32) 5645 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 5646 break; 5647 } 5648 case ISD::SELECT_CC: { 5649 SDOperand TL, TH, FL, FH; 5650 ExpandOp(Node->getOperand(2), TL, TH); 5651 ExpandOp(Node->getOperand(3), FL, FH); 5652 if (getTypeAction(NVT) == Expand) 5653 NVT = TLI.getTypeToExpandTo(NVT); 5654 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5655 Node->getOperand(1), TL, FL, Node->getOperand(4)); 5656 if (VT != MVT::f32) 5657 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5658 Node->getOperand(1), TH, FH, Node->getOperand(4)); 5659 break; 5660 } 5661 case ISD::ANY_EXTEND: 5662 // The low part is any extension of the input (which degenerates to a copy). 5663 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 5664 // The high part is undefined. 5665 Hi = DAG.getNode(ISD::UNDEF, NVT); 5666 break; 5667 case ISD::SIGN_EXTEND: { 5668 // The low part is just a sign extension of the input (which degenerates to 5669 // a copy). 5670 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 5671 5672 // The high part is obtained by SRA'ing all but one of the bits of the lo 5673 // part. 5674 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5675 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5676 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5677 break; 5678 } 5679 case ISD::ZERO_EXTEND: 5680 // The low part is just a zero extension of the input (which degenerates to 5681 // a copy). 5682 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 5683 5684 // The high part is just a zero. 5685 Hi = DAG.getConstant(0, NVT); 5686 break; 5687 5688 case ISD::TRUNCATE: { 5689 // The input value must be larger than this value. Expand *it*. 5690 SDOperand NewLo; 5691 ExpandOp(Node->getOperand(0), NewLo, Hi); 5692 5693 // The low part is now either the right size, or it is closer. If not the 5694 // right size, make an illegal truncate so we recursively expand it. 5695 if (NewLo.getValueType() != Node->getValueType(0)) 5696 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 5697 ExpandOp(NewLo, Lo, Hi); 5698 break; 5699 } 5700 5701 case ISD::BIT_CONVERT: { 5702 SDOperand Tmp; 5703 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 5704 // If the target wants to, allow it to lower this itself. 5705 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5706 case Expand: assert(0 && "cannot expand FP!"); 5707 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 5708 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 5709 } 5710 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 5711 } 5712 5713 // f32 / f64 must be expanded to i32 / i64. 5714 if (VT == MVT::f32 || VT == MVT::f64) { 5715 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5716 if (getTypeAction(NVT) == Expand) 5717 ExpandOp(Lo, Lo, Hi); 5718 break; 5719 } 5720 5721 // If source operand will be expanded to the same type as VT, i.e. 5722 // i64 <- f64, i32 <- f32, expand the source operand instead. 5723 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 5724 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 5725 ExpandOp(Node->getOperand(0), Lo, Hi); 5726 break; 5727 } 5728 5729 // Turn this into a load/store pair by default. 5730 if (Tmp.Val == 0) 5731 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 5732 5733 ExpandOp(Tmp, Lo, Hi); 5734 break; 5735 } 5736 5737 case ISD::READCYCLECOUNTER: { 5738 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 5739 TargetLowering::Custom && 5740 "Must custom expand ReadCycleCounter"); 5741 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 5742 assert(Tmp.Val && "Node must be custom expanded!"); 5743 ExpandOp(Tmp.getValue(0), Lo, Hi); 5744 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 5745 LegalizeOp(Tmp.getValue(1))); 5746 break; 5747 } 5748 5749 // These operators cannot be expanded directly, emit them as calls to 5750 // library functions. 5751 case ISD::FP_TO_SINT: { 5752 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 5753 SDOperand Op; 5754 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5755 case Expand: assert(0 && "cannot expand FP!"); 5756 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5757 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5758 } 5759 5760 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 5761 5762 // Now that the custom expander is done, expand the result, which is still 5763 // VT. 5764 if (Op.Val) { 5765 ExpandOp(Op, Lo, Hi); 5766 break; 5767 } 5768 } 5769 5770 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5771 if (Node->getOperand(0).getValueType() == MVT::f32) 5772 LC = RTLIB::FPTOSINT_F32_I64; 5773 else if (Node->getOperand(0).getValueType() == MVT::f64) 5774 LC = RTLIB::FPTOSINT_F64_I64; 5775 else if (Node->getOperand(0).getValueType() == MVT::f80) 5776 LC = RTLIB::FPTOSINT_F80_I64; 5777 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 5778 LC = RTLIB::FPTOSINT_PPCF128_I64; 5779 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5780 false/*sign irrelevant*/, Hi); 5781 break; 5782 } 5783 5784 case ISD::FP_TO_UINT: { 5785 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 5786 SDOperand Op; 5787 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5788 case Expand: assert(0 && "cannot expand FP!"); 5789 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5790 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5791 } 5792 5793 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 5794 5795 // Now that the custom expander is done, expand the result. 5796 if (Op.Val) { 5797 ExpandOp(Op, Lo, Hi); 5798 break; 5799 } 5800 } 5801 5802 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5803 if (Node->getOperand(0).getValueType() == MVT::f32) 5804 LC = RTLIB::FPTOUINT_F32_I64; 5805 else if (Node->getOperand(0).getValueType() == MVT::f64) 5806 LC = RTLIB::FPTOUINT_F64_I64; 5807 else if (Node->getOperand(0).getValueType() == MVT::f80) 5808 LC = RTLIB::FPTOUINT_F80_I64; 5809 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 5810 LC = RTLIB::FPTOUINT_PPCF128_I64; 5811 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5812 false/*sign irrelevant*/, Hi); 5813 break; 5814 } 5815 5816 case ISD::SHL: { 5817 // If the target wants custom lowering, do so. 5818 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5819 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 5820 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 5821 Op = TLI.LowerOperation(Op, DAG); 5822 if (Op.Val) { 5823 // Now that the custom expander is done, expand the result, which is 5824 // still VT. 5825 ExpandOp(Op, Lo, Hi); 5826 break; 5827 } 5828 } 5829 5830 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 5831 // this X << 1 as X+X. 5832 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 5833 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 5834 TLI.isOperationLegal(ISD::ADDE, NVT)) { 5835 SDOperand LoOps[2], HiOps[3]; 5836 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 5837 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 5838 LoOps[1] = LoOps[0]; 5839 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5840 5841 HiOps[1] = HiOps[0]; 5842 HiOps[2] = Lo.getValue(1); 5843 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5844 break; 5845 } 5846 } 5847 5848 // If we can emit an efficient shift operation, do so now. 5849 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5850 break; 5851 5852 // If this target supports SHL_PARTS, use it. 5853 TargetLowering::LegalizeAction Action = 5854 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 5855 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5856 Action == TargetLowering::Custom) { 5857 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5858 break; 5859 } 5860 5861 // Otherwise, emit a libcall. 5862 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 5863 false/*left shift=unsigned*/, Hi); 5864 break; 5865 } 5866 5867 case ISD::SRA: { 5868 // If the target wants custom lowering, do so. 5869 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5870 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 5871 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 5872 Op = TLI.LowerOperation(Op, DAG); 5873 if (Op.Val) { 5874 // Now that the custom expander is done, expand the result, which is 5875 // still VT. 5876 ExpandOp(Op, Lo, Hi); 5877 break; 5878 } 5879 } 5880 5881 // If we can emit an efficient shift operation, do so now. 5882 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5883 break; 5884 5885 // If this target supports SRA_PARTS, use it. 5886 TargetLowering::LegalizeAction Action = 5887 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 5888 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5889 Action == TargetLowering::Custom) { 5890 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5891 break; 5892 } 5893 5894 // Otherwise, emit a libcall. 5895 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 5896 true/*ashr is signed*/, Hi); 5897 break; 5898 } 5899 5900 case ISD::SRL: { 5901 // If the target wants custom lowering, do so. 5902 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5903 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 5904 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 5905 Op = TLI.LowerOperation(Op, DAG); 5906 if (Op.Val) { 5907 // Now that the custom expander is done, expand the result, which is 5908 // still VT. 5909 ExpandOp(Op, Lo, Hi); 5910 break; 5911 } 5912 } 5913 5914 // If we can emit an efficient shift operation, do so now. 5915 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5916 break; 5917 5918 // If this target supports SRL_PARTS, use it. 5919 TargetLowering::LegalizeAction Action = 5920 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 5921 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5922 Action == TargetLowering::Custom) { 5923 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5924 break; 5925 } 5926 5927 // Otherwise, emit a libcall. 5928 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 5929 false/*lshr is unsigned*/, Hi); 5930 break; 5931 } 5932 5933 case ISD::ADD: 5934 case ISD::SUB: { 5935 // If the target wants to custom expand this, let them. 5936 if (TLI.getOperationAction(Node->getOpcode(), VT) == 5937 TargetLowering::Custom) { 5938 Op = TLI.LowerOperation(Op, DAG); 5939 if (Op.Val) { 5940 ExpandOp(Op, Lo, Hi); 5941 break; 5942 } 5943 } 5944 5945 // Expand the subcomponents. 5946 SDOperand LHSL, LHSH, RHSL, RHSH; 5947 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5948 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5949 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5950 SDOperand LoOps[2], HiOps[3]; 5951 LoOps[0] = LHSL; 5952 LoOps[1] = RHSL; 5953 HiOps[0] = LHSH; 5954 HiOps[1] = RHSH; 5955 if (Node->getOpcode() == ISD::ADD) { 5956 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5957 HiOps[2] = Lo.getValue(1); 5958 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5959 } else { 5960 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5961 HiOps[2] = Lo.getValue(1); 5962 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5963 } 5964 break; 5965 } 5966 5967 case ISD::ADDC: 5968 case ISD::SUBC: { 5969 // Expand the subcomponents. 5970 SDOperand LHSL, LHSH, RHSL, RHSH; 5971 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5972 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5973 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5974 SDOperand LoOps[2] = { LHSL, RHSL }; 5975 SDOperand HiOps[3] = { LHSH, RHSH }; 5976 5977 if (Node->getOpcode() == ISD::ADDC) { 5978 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5979 HiOps[2] = Lo.getValue(1); 5980 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5981 } else { 5982 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5983 HiOps[2] = Lo.getValue(1); 5984 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5985 } 5986 // Remember that we legalized the flag. 5987 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5988 break; 5989 } 5990 case ISD::ADDE: 5991 case ISD::SUBE: { 5992 // Expand the subcomponents. 5993 SDOperand LHSL, LHSH, RHSL, RHSH; 5994 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5995 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5996 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5997 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 5998 SDOperand HiOps[3] = { LHSH, RHSH }; 5999 6000 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 6001 HiOps[2] = Lo.getValue(1); 6002 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 6003 6004 // Remember that we legalized the flag. 6005 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6006 break; 6007 } 6008 case ISD::MUL: { 6009 // If the target wants to custom expand this, let them. 6010 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 6011 SDOperand New = TLI.LowerOperation(Op, DAG); 6012 if (New.Val) { 6013 ExpandOp(New, Lo, Hi); 6014 break; 6015 } 6016 } 6017 6018 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 6019 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 6020 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 6021 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 6022 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 6023 SDOperand LL, LH, RL, RH; 6024 ExpandOp(Node->getOperand(0), LL, LH); 6025 ExpandOp(Node->getOperand(1), RL, RH); 6026 unsigned BitSize = MVT::getSizeInBits(RH.getValueType()); 6027 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 6028 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 6029 // FIXME: generalize this to handle other bit sizes 6030 if (LHSSB == 32 && RHSSB == 32 && 6031 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) && 6032 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) { 6033 // The inputs are both zero-extended. 6034 if (HasUMUL_LOHI) { 6035 // We can emit a umul_lohi. 6036 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6037 Hi = SDOperand(Lo.Val, 1); 6038 break; 6039 } 6040 if (HasMULHU) { 6041 // We can emit a mulhu+mul. 6042 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6043 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6044 break; 6045 } 6046 } 6047 if (LHSSB > BitSize && RHSSB > BitSize) { 6048 // The input values are both sign-extended. 6049 if (HasSMUL_LOHI) { 6050 // We can emit a smul_lohi. 6051 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6052 Hi = SDOperand(Lo.Val, 1); 6053 break; 6054 } 6055 if (HasMULHS) { 6056 // We can emit a mulhs+mul. 6057 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6058 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6059 break; 6060 } 6061 } 6062 if (HasUMUL_LOHI) { 6063 // Lo,Hi = umul LHS, RHS. 6064 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6065 DAG.getVTList(NVT, NVT), LL, RL); 6066 Lo = UMulLOHI; 6067 Hi = UMulLOHI.getValue(1); 6068 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6069 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6070 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6071 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6072 break; 6073 } 6074 if (HasMULHU) { 6075 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6076 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6077 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6078 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6079 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6080 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6081 break; 6082 } 6083 } 6084 6085 // If nothing else, we can make a libcall. 6086 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 6087 false/*sign irrelevant*/, Hi); 6088 break; 6089 } 6090 case ISD::SDIV: 6091 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 6092 break; 6093 case ISD::UDIV: 6094 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 6095 break; 6096 case ISD::SREM: 6097 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 6098 break; 6099 case ISD::UREM: 6100 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 6101 break; 6102 6103 case ISD::FADD: 6104 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32, 6105 RTLIB::ADD_F64, 6106 RTLIB::ADD_F80, 6107 RTLIB::ADD_PPCF128)), 6108 Node, false, Hi); 6109 break; 6110 case ISD::FSUB: 6111 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32, 6112 RTLIB::SUB_F64, 6113 RTLIB::SUB_F80, 6114 RTLIB::SUB_PPCF128)), 6115 Node, false, Hi); 6116 break; 6117 case ISD::FMUL: 6118 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32, 6119 RTLIB::MUL_F64, 6120 RTLIB::MUL_F80, 6121 RTLIB::MUL_PPCF128)), 6122 Node, false, Hi); 6123 break; 6124 case ISD::FDIV: 6125 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32, 6126 RTLIB::DIV_F64, 6127 RTLIB::DIV_F80, 6128 RTLIB::DIV_PPCF128)), 6129 Node, false, Hi); 6130 break; 6131 case ISD::FP_EXTEND: 6132 if (VT == MVT::ppcf128) { 6133 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6134 Node->getOperand(0).getValueType()==MVT::f64); 6135 const uint64_t zero = 0; 6136 if (Node->getOperand(0).getValueType()==MVT::f32) 6137 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6138 else 6139 Hi = Node->getOperand(0); 6140 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6141 break; 6142 } 6143 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 6144 break; 6145 case ISD::FP_ROUND: 6146 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 6147 break; 6148 case ISD::FPOWI: 6149 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32, 6150 RTLIB::POWI_F64, 6151 RTLIB::POWI_F80, 6152 RTLIB::POWI_PPCF128)), 6153 Node, false, Hi); 6154 break; 6155 case ISD::FSQRT: 6156 case ISD::FSIN: 6157 case ISD::FCOS: { 6158 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6159 switch(Node->getOpcode()) { 6160 case ISD::FSQRT: 6161 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 6162 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 6163 break; 6164 case ISD::FSIN: 6165 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 6166 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 6167 break; 6168 case ISD::FCOS: 6169 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 6170 RTLIB::COS_F80, RTLIB::COS_PPCF128); 6171 break; 6172 default: assert(0 && "Unreachable!"); 6173 } 6174 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 6175 break; 6176 } 6177 case ISD::FABS: { 6178 if (VT == MVT::ppcf128) { 6179 SDOperand Tmp; 6180 ExpandOp(Node->getOperand(0), Lo, Tmp); 6181 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6182 // lo = hi==fabs(hi) ? lo : -lo; 6183 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6184 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6185 DAG.getCondCode(ISD::SETEQ)); 6186 break; 6187 } 6188 SDOperand Mask = (VT == MVT::f64) 6189 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6190 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6191 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6192 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6193 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6194 if (getTypeAction(NVT) == Expand) 6195 ExpandOp(Lo, Lo, Hi); 6196 break; 6197 } 6198 case ISD::FNEG: { 6199 if (VT == MVT::ppcf128) { 6200 ExpandOp(Node->getOperand(0), Lo, Hi); 6201 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6202 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6203 break; 6204 } 6205 SDOperand Mask = (VT == MVT::f64) 6206 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6207 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6208 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6209 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6210 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6211 if (getTypeAction(NVT) == Expand) 6212 ExpandOp(Lo, Lo, Hi); 6213 break; 6214 } 6215 case ISD::FCOPYSIGN: { 6216 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6217 if (getTypeAction(NVT) == Expand) 6218 ExpandOp(Lo, Lo, Hi); 6219 break; 6220 } 6221 case ISD::SINT_TO_FP: 6222 case ISD::UINT_TO_FP: { 6223 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6224 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 6225 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) { 6226 static uint64_t zero = 0; 6227 if (isSigned) { 6228 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6229 Node->getOperand(0))); 6230 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6231 } else { 6232 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6233 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6234 Node->getOperand(0))); 6235 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6236 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6237 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6238 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6239 DAG.getConstant(0, MVT::i32), 6240 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6241 DAG.getConstantFP( 6242 APFloat(APInt(128, 2, TwoE32)), 6243 MVT::ppcf128)), 6244 Hi, 6245 DAG.getCondCode(ISD::SETLT)), 6246 Lo, Hi); 6247 } 6248 break; 6249 } 6250 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6251 // si64->ppcf128 done by libcall, below 6252 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6253 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6254 Lo, Hi); 6255 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6256 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6257 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6258 DAG.getConstant(0, MVT::i64), 6259 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6260 DAG.getConstantFP( 6261 APFloat(APInt(128, 2, TwoE64)), 6262 MVT::ppcf128)), 6263 Hi, 6264 DAG.getCondCode(ISD::SETLT)), 6265 Lo, Hi); 6266 break; 6267 } 6268 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6269 if (Node->getOperand(0).getValueType() == MVT::i64) { 6270 if (VT == MVT::f32) 6271 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; 6272 else if (VT == MVT::f64) 6273 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; 6274 else if (VT == MVT::f80) { 6275 assert(isSigned); 6276 LC = RTLIB::SINTTOFP_I64_F80; 6277 } 6278 else if (VT == MVT::ppcf128) { 6279 assert(isSigned); 6280 LC = RTLIB::SINTTOFP_I64_PPCF128; 6281 } 6282 } else { 6283 if (VT == MVT::f32) 6284 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 6285 else 6286 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 6287 } 6288 6289 // Promote the operand if needed. 6290 if (getTypeAction(SrcVT) == Promote) { 6291 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 6292 Tmp = isSigned 6293 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6294 DAG.getValueType(SrcVT)) 6295 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6296 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6297 } 6298 6299 const char *LibCall = TLI.getLibcallName(LC); 6300 if (LibCall) 6301 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi); 6302 else { 6303 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6304 Node->getOperand(0)); 6305 if (getTypeAction(Lo.getValueType()) == Expand) 6306 ExpandOp(Lo, Lo, Hi); 6307 } 6308 break; 6309 } 6310 } 6311 6312 // Make sure the resultant values have been legalized themselves, unless this 6313 // is a type that requires multi-step expansion. 6314 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6315 Lo = LegalizeOp(Lo); 6316 if (Hi.Val) 6317 // Don't legalize the high part if it is expanded to a single node. 6318 Hi = LegalizeOp(Hi); 6319 } 6320 6321 // Remember in a map if the values will be reused later. 6322 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 6323 assert(isNew && "Value already expanded?!?"); 6324} 6325 6326/// SplitVectorOp - Given an operand of vector type, break it down into 6327/// two smaller values, still of vector type. 6328void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 6329 SDOperand &Hi) { 6330 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); 6331 SDNode *Node = Op.Val; 6332 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType()); 6333 assert(NumElements > 1 && "Cannot split a single element vector!"); 6334 6335 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType()); 6336 6337 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6338 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6339 6340 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo); 6341 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi); 6342 6343 // See if we already split it. 6344 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 6345 = SplitNodes.find(Op); 6346 if (I != SplitNodes.end()) { 6347 Lo = I->second.first; 6348 Hi = I->second.second; 6349 return; 6350 } 6351 6352 switch (Node->getOpcode()) { 6353 default: 6354#ifndef NDEBUG 6355 Node->dump(&DAG); 6356#endif 6357 assert(0 && "Unhandled operation in SplitVectorOp!"); 6358 case ISD::UNDEF: 6359 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6360 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6361 break; 6362 case ISD::BUILD_PAIR: 6363 Lo = Node->getOperand(0); 6364 Hi = Node->getOperand(1); 6365 break; 6366 case ISD::INSERT_VECTOR_ELT: { 6367 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6368 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 6369 SDOperand ScalarOp = Node->getOperand(1); 6370 if (Index < NewNumElts_Lo) 6371 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6372 DAG.getConstant(Index, TLI.getPointerTy())); 6373 else 6374 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6375 DAG.getConstant(Index - NewNumElts_Lo, 6376 TLI.getPointerTy())); 6377 break; 6378 } 6379 case ISD::VECTOR_SHUFFLE: { 6380 // Build the low part. 6381 SDOperand Mask = Node->getOperand(2); 6382 SmallVector<SDOperand, 8> Ops; 6383 MVT::ValueType PtrVT = TLI.getPointerTy(); 6384 6385 // Insert all of the elements from the input that are needed. We use 6386 // buildvector of extractelement here because the input vectors will have 6387 // to be legalized, so this makes the code simpler. 6388 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 6389 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 6390 SDOperand InVec = Node->getOperand(0); 6391 if (Idx >= NumElements) { 6392 InVec = Node->getOperand(1); 6393 Idx -= NumElements; 6394 } 6395 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6396 DAG.getConstant(Idx, PtrVT))); 6397 } 6398 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6399 Ops.clear(); 6400 6401 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 6402 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 6403 SDOperand InVec = Node->getOperand(0); 6404 if (Idx >= NumElements) { 6405 InVec = Node->getOperand(1); 6406 Idx -= NumElements; 6407 } 6408 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6409 DAG.getConstant(Idx, PtrVT))); 6410 } 6411 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6412 break; 6413 } 6414 case ISD::BUILD_VECTOR: { 6415 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6416 Node->op_begin()+NewNumElts_Lo); 6417 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 6418 6419 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 6420 Node->op_end()); 6421 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 6422 break; 6423 } 6424 case ISD::CONCAT_VECTORS: { 6425 // FIXME: Handle non-power-of-two vectors? 6426 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6427 if (NewNumSubvectors == 1) { 6428 Lo = Node->getOperand(0); 6429 Hi = Node->getOperand(1); 6430 } else { 6431 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6432 Node->op_begin()+NewNumSubvectors); 6433 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 6434 6435 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6436 Node->op_end()); 6437 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 6438 } 6439 break; 6440 } 6441 case ISD::SELECT: { 6442 SDOperand Cond = Node->getOperand(0); 6443 6444 SDOperand LL, LH, RL, RH; 6445 SplitVectorOp(Node->getOperand(1), LL, LH); 6446 SplitVectorOp(Node->getOperand(2), RL, RH); 6447 6448 if (MVT::isVector(Cond.getValueType())) { 6449 // Handle a vector merge. 6450 SDOperand CL, CH; 6451 SplitVectorOp(Cond, CL, CH); 6452 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 6453 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 6454 } else { 6455 // Handle a simple select with vector operands. 6456 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 6457 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 6458 } 6459 break; 6460 } 6461 case ISD::ADD: 6462 case ISD::SUB: 6463 case ISD::MUL: 6464 case ISD::FADD: 6465 case ISD::FSUB: 6466 case ISD::FMUL: 6467 case ISD::SDIV: 6468 case ISD::UDIV: 6469 case ISD::FDIV: 6470 case ISD::FPOW: 6471 case ISD::AND: 6472 case ISD::OR: 6473 case ISD::XOR: 6474 case ISD::UREM: 6475 case ISD::SREM: 6476 case ISD::FREM: { 6477 SDOperand LL, LH, RL, RH; 6478 SplitVectorOp(Node->getOperand(0), LL, LH); 6479 SplitVectorOp(Node->getOperand(1), RL, RH); 6480 6481 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 6482 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 6483 break; 6484 } 6485 case ISD::FPOWI: { 6486 SDOperand L, H; 6487 SplitVectorOp(Node->getOperand(0), L, H); 6488 6489 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 6490 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 6491 break; 6492 } 6493 case ISD::CTTZ: 6494 case ISD::CTLZ: 6495 case ISD::CTPOP: 6496 case ISD::FNEG: 6497 case ISD::FABS: 6498 case ISD::FSQRT: 6499 case ISD::FSIN: 6500 case ISD::FCOS: 6501 case ISD::FP_TO_SINT: 6502 case ISD::FP_TO_UINT: 6503 case ISD::SINT_TO_FP: 6504 case ISD::UINT_TO_FP: { 6505 SDOperand L, H; 6506 SplitVectorOp(Node->getOperand(0), L, H); 6507 6508 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 6509 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 6510 break; 6511 } 6512 case ISD::LOAD: { 6513 LoadSDNode *LD = cast<LoadSDNode>(Node); 6514 SDOperand Ch = LD->getChain(); 6515 SDOperand Ptr = LD->getBasePtr(); 6516 const Value *SV = LD->getSrcValue(); 6517 int SVOffset = LD->getSrcValueOffset(); 6518 unsigned Alignment = LD->getAlignment(); 6519 bool isVolatile = LD->isVolatile(); 6520 6521 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6522 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8; 6523 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6524 DAG.getIntPtrConstant(IncrementSize)); 6525 SVOffset += IncrementSize; 6526 Alignment = MinAlign(Alignment, IncrementSize); 6527 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6528 6529 // Build a factor node to remember that this load is independent of the 6530 // other one. 6531 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6532 Hi.getValue(1)); 6533 6534 // Remember that we legalized the chain. 6535 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6536 break; 6537 } 6538 case ISD::BIT_CONVERT: { 6539 // We know the result is a vector. The input may be either a vector or a 6540 // scalar value. 6541 SDOperand InOp = Node->getOperand(0); 6542 if (!MVT::isVector(InOp.getValueType()) || 6543 MVT::getVectorNumElements(InOp.getValueType()) == 1) { 6544 // The input is a scalar or single-element vector. 6545 // Lower to a store/load so that it can be split. 6546 // FIXME: this could be improved probably. 6547 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); 6548 6549 SDOperand St = DAG.getStore(DAG.getEntryNode(), 6550 InOp, Ptr, NULL, 0); 6551 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0); 6552 } 6553 // Split the vector and convert each of the pieces now. 6554 SplitVectorOp(InOp, Lo, Hi); 6555 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 6556 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 6557 break; 6558 } 6559 } 6560 6561 // Remember in a map if the values will be reused later. 6562 bool isNew = 6563 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 6564 assert(isNew && "Value already split?!?"); 6565} 6566 6567 6568/// ScalarizeVectorOp - Given an operand of single-element vector type 6569/// (e.g. v1f32), convert it into the equivalent operation that returns a 6570/// scalar (e.g. f32) value. 6571SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 6572 assert(MVT::isVector(Op.getValueType()) && 6573 "Bad ScalarizeVectorOp invocation!"); 6574 SDNode *Node = Op.Val; 6575 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); 6576 assert(MVT::getVectorNumElements(Op.getValueType()) == 1); 6577 6578 // See if we already scalarized it. 6579 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 6580 if (I != ScalarizedNodes.end()) return I->second; 6581 6582 SDOperand Result; 6583 switch (Node->getOpcode()) { 6584 default: 6585#ifndef NDEBUG 6586 Node->dump(&DAG); cerr << "\n"; 6587#endif 6588 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 6589 case ISD::ADD: 6590 case ISD::FADD: 6591 case ISD::SUB: 6592 case ISD::FSUB: 6593 case ISD::MUL: 6594 case ISD::FMUL: 6595 case ISD::SDIV: 6596 case ISD::UDIV: 6597 case ISD::FDIV: 6598 case ISD::SREM: 6599 case ISD::UREM: 6600 case ISD::FREM: 6601 case ISD::FPOW: 6602 case ISD::AND: 6603 case ISD::OR: 6604 case ISD::XOR: 6605 Result = DAG.getNode(Node->getOpcode(), 6606 NewVT, 6607 ScalarizeVectorOp(Node->getOperand(0)), 6608 ScalarizeVectorOp(Node->getOperand(1))); 6609 break; 6610 case ISD::FNEG: 6611 case ISD::FABS: 6612 case ISD::FSQRT: 6613 case ISD::FSIN: 6614 case ISD::FCOS: 6615 Result = DAG.getNode(Node->getOpcode(), 6616 NewVT, 6617 ScalarizeVectorOp(Node->getOperand(0))); 6618 break; 6619 case ISD::FPOWI: 6620 Result = DAG.getNode(Node->getOpcode(), 6621 NewVT, 6622 ScalarizeVectorOp(Node->getOperand(0)), 6623 Node->getOperand(1)); 6624 break; 6625 case ISD::LOAD: { 6626 LoadSDNode *LD = cast<LoadSDNode>(Node); 6627 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 6628 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 6629 6630 const Value *SV = LD->getSrcValue(); 6631 int SVOffset = LD->getSrcValueOffset(); 6632 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 6633 LD->isVolatile(), LD->getAlignment()); 6634 6635 // Remember that we legalized the chain. 6636 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 6637 break; 6638 } 6639 case ISD::BUILD_VECTOR: 6640 Result = Node->getOperand(0); 6641 break; 6642 case ISD::INSERT_VECTOR_ELT: 6643 // Returning the inserted scalar element. 6644 Result = Node->getOperand(1); 6645 break; 6646 case ISD::CONCAT_VECTORS: 6647 assert(Node->getOperand(0).getValueType() == NewVT && 6648 "Concat of non-legal vectors not yet supported!"); 6649 Result = Node->getOperand(0); 6650 break; 6651 case ISD::VECTOR_SHUFFLE: { 6652 // Figure out if the scalar is the LHS or RHS and return it. 6653 SDOperand EltNum = Node->getOperand(2).getOperand(0); 6654 if (cast<ConstantSDNode>(EltNum)->getValue()) 6655 Result = ScalarizeVectorOp(Node->getOperand(1)); 6656 else 6657 Result = ScalarizeVectorOp(Node->getOperand(0)); 6658 break; 6659 } 6660 case ISD::EXTRACT_SUBVECTOR: 6661 Result = Node->getOperand(0); 6662 assert(Result.getValueType() == NewVT); 6663 break; 6664 case ISD::BIT_CONVERT: 6665 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 6666 break; 6667 case ISD::SELECT: 6668 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 6669 ScalarizeVectorOp(Op.getOperand(1)), 6670 ScalarizeVectorOp(Op.getOperand(2))); 6671 break; 6672 } 6673 6674 if (TLI.isTypeLegal(NewVT)) 6675 Result = LegalizeOp(Result); 6676 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 6677 assert(isNew && "Value already scalarized?"); 6678 return Result; 6679} 6680 6681 6682// SelectionDAG::Legalize - This is the entry point for the file. 6683// 6684void SelectionDAG::Legalize() { 6685 if (ViewLegalizeDAGs) viewGraph(); 6686 6687 /// run - This is the main entry point to this class. 6688 /// 6689 SelectionDAGLegalize(*this).LegalizeDAG(); 6690} 6691 6692