LegalizeDAG.cpp revision 5fbb5d2459a5410590f285250faa604576308a93
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 /// LegalizeAction - This enum indicates what action we should take for each 45 /// value type the can occur in the program. 46 enum LegalizeAction { 47 Legal, // The target natively supports this value type. 48 Promote, // This should be promoted to the next larger type. 49 Expand, // This integer type should be broken into smaller pieces. 50 }; 51 52 /// ValueTypeActions - This is a bitvector that contains two bits for each 53 /// value type, where the two bits correspond to the LegalizeAction enum. 54 /// This can be queried with "getTypeAction(VT)". 55 unsigned ValueTypeActions; 56 57 /// NeedsAnotherIteration - This is set when we expand a large integer 58 /// operation into smaller integer operations, but the smaller operations are 59 /// not set. This occurs only rarely in practice, for targets that don't have 60 /// 32-bit or larger integer registers. 61 bool NeedsAnotherIteration; 62 63 /// LegalizedNodes - For nodes that are of legal width, and that have more 64 /// than one use, this map indicates what regularized operand to use. This 65 /// allows us to avoid legalizing the same thing more than once. 66 std::map<SDOperand, SDOperand> LegalizedNodes; 67 68 /// PromotedNodes - For nodes that are below legal width, and that have more 69 /// than one use, this map indicates what promoted value to use. This allows 70 /// us to avoid promoting the same thing more than once. 71 std::map<SDOperand, SDOperand> PromotedNodes; 72 73 /// ExpandedNodes - For nodes that need to be expanded, and which have more 74 /// than one use, this map indicates which which operands are the expanded 75 /// version of the input. This allows us to avoid expanding the same node 76 /// more than once. 77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 78 79 void AddLegalizedOperand(SDOperand From, SDOperand To) { 80 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second; 81 assert(isNew && "Got into the map somehow?"); 82 } 83 void AddPromotedOperand(SDOperand From, SDOperand To) { 84 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 85 assert(isNew && "Got into the map somehow?"); 86 } 87 88public: 89 90 SelectionDAGLegalize(SelectionDAG &DAG); 91 92 /// Run - While there is still lowering to do, perform a pass over the DAG. 93 /// Most regularization can be done in a single pass, but targets that require 94 /// large values to be split into registers multiple times (e.g. i64 -> 4x 95 /// i16) require iteration for these values (the first iteration will demote 96 /// to i32, the second will demote to i16). 97 void Run() { 98 do { 99 NeedsAnotherIteration = false; 100 LegalizeDAG(); 101 } while (NeedsAnotherIteration); 102 } 103 104 /// getTypeAction - Return how we should legalize values of this type, either 105 /// it is already legal or we need to expand it into multiple registers of 106 /// smaller integer type, or we need to promote it to a larger type. 107 LegalizeAction getTypeAction(MVT::ValueType VT) const { 108 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 109 } 110 111 /// isTypeLegal - Return true if this type is legal on this target. 112 /// 113 bool isTypeLegal(MVT::ValueType VT) const { 114 return getTypeAction(VT) == Legal; 115 } 116 117private: 118 void LegalizeDAG(); 119 120 SDOperand LegalizeOp(SDOperand O); 121 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 122 SDOperand PromoteOp(SDOperand O); 123 124 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 125 SDOperand &Hi); 126 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 127 SDOperand Source); 128 129 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 130 SDOperand LegalOp, 131 MVT::ValueType DestVT); 132 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 133 bool isSigned); 134 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 135 bool isSigned); 136 137 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 138 SDOperand &Lo, SDOperand &Hi); 139 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 140 SDOperand &Lo, SDOperand &Hi); 141 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 142 SDOperand &Lo, SDOperand &Hi); 143 144 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 145 146 SDOperand getIntPtrConstant(uint64_t Val) { 147 return DAG.getConstant(Val, TLI.getPointerTy()); 148 } 149}; 150} 151 152static unsigned scalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 153 switch (VecOp) { 154 default: assert(0 && "Don't know how to scalarize this opcode!"); 155 break; 156 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 157 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 158 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 159 } 160} 161 162SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 163 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 164 ValueTypeActions(TLI.getValueTypeActions()) { 165 assert(MVT::LAST_VALUETYPE <= 16 && 166 "Too many value types for ValueTypeActions to hold!"); 167} 168 169/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 170/// INT_TO_FP operation of the specified operand when the target requests that 171/// we expand it. At this point, we know that the result and operand types are 172/// legal for the target. 173SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 174 SDOperand Op0, 175 MVT::ValueType DestVT) { 176 if (Op0.getValueType() == MVT::i32) { 177 // simple 32-bit [signed|unsigned] integer to float/double expansion 178 179 // get the stack frame index of a 8 byte buffer 180 MachineFunction &MF = DAG.getMachineFunction(); 181 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 182 // get address of 8 byte buffer 183 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 184 // word offset constant for Hi/Lo address computation 185 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 186 // set up Hi and Lo (into buffer) address based on endian 187 SDOperand Hi, Lo; 188 if (TLI.isLittleEndian()) { 189 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 190 Lo = StackSlot; 191 } else { 192 Hi = StackSlot; 193 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 194 } 195 // if signed map to unsigned space 196 SDOperand Op0Mapped; 197 if (isSigned) { 198 // constant used to invert sign bit (signed to unsigned mapping) 199 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 200 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 201 } else { 202 Op0Mapped = Op0; 203 } 204 // store the lo of the constructed double - based on integer input 205 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 206 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 207 // initial hi portion of constructed double 208 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 209 // store the hi of the constructed double - biased exponent 210 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 211 InitialHi, Hi, DAG.getSrcValue(NULL)); 212 // load the constructed double 213 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 214 DAG.getSrcValue(NULL)); 215 // FP constant to bias correct the final result 216 SDOperand Bias = DAG.getConstantFP(isSigned ? 217 BitsToDouble(0x4330000080000000ULL) 218 : BitsToDouble(0x4330000000000000ULL), 219 MVT::f64); 220 // subtract the bias 221 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 222 // final result 223 SDOperand Result; 224 // handle final rounding 225 if (DestVT == MVT::f64) { 226 // do nothing 227 Result = Sub; 228 } else { 229 // if f32 then cast to f32 230 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 231 } 232 NeedsAnotherIteration = true; 233 return Result; 234 } 235 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 236 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 237 238 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 239 DAG.getConstant(0, Op0.getValueType()), 240 ISD::SETLT); 241 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 242 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 243 SignSet, Four, Zero); 244 245 // If the sign bit of the integer is set, the large number will be treated 246 // as a negative number. To counteract this, the dynamic code adds an 247 // offset depending on the data type. 248 uint64_t FF; 249 switch (Op0.getValueType()) { 250 default: assert(0 && "Unsupported integer type!"); 251 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 252 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 253 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 254 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 255 } 256 if (TLI.isLittleEndian()) FF <<= 32; 257 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 258 259 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 260 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 261 SDOperand FudgeInReg; 262 if (DestVT == MVT::f32) 263 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 264 DAG.getSrcValue(NULL)); 265 else { 266 assert(DestVT == MVT::f64 && "Unexpected conversion"); 267 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 268 DAG.getEntryNode(), CPIdx, 269 DAG.getSrcValue(NULL), MVT::f32)); 270 } 271 272 NeedsAnotherIteration = true; 273 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 274} 275 276/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 277/// *INT_TO_FP operation of the specified operand when the target requests that 278/// we promote it. At this point, we know that the result and operand types are 279/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 280/// operation that takes a larger input. 281SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 282 MVT::ValueType DestVT, 283 bool isSigned) { 284 // First step, figure out the appropriate *INT_TO_FP operation to use. 285 MVT::ValueType NewInTy = LegalOp.getValueType(); 286 287 unsigned OpToUse = 0; 288 289 // Scan for the appropriate larger type to use. 290 while (1) { 291 NewInTy = (MVT::ValueType)(NewInTy+1); 292 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 293 294 // If the target supports SINT_TO_FP of this type, use it. 295 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 296 default: break; 297 case TargetLowering::Legal: 298 if (!TLI.isTypeLegal(NewInTy)) 299 break; // Can't use this datatype. 300 // FALL THROUGH. 301 case TargetLowering::Custom: 302 OpToUse = ISD::SINT_TO_FP; 303 break; 304 } 305 if (OpToUse) break; 306 if (isSigned) continue; 307 308 // If the target supports UINT_TO_FP of this type, use it. 309 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 310 default: break; 311 case TargetLowering::Legal: 312 if (!TLI.isTypeLegal(NewInTy)) 313 break; // Can't use this datatype. 314 // FALL THROUGH. 315 case TargetLowering::Custom: 316 OpToUse = ISD::UINT_TO_FP; 317 break; 318 } 319 if (OpToUse) break; 320 321 // Otherwise, try a larger type. 322 } 323 324 // Make sure to legalize any nodes we create here in the next pass. 325 NeedsAnotherIteration = true; 326 327 // Okay, we found the operation and type to use. Zero extend our input to the 328 // desired type then run the operation on it. 329 return DAG.getNode(OpToUse, DestVT, 330 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 331 NewInTy, LegalOp)); 332} 333 334/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 335/// FP_TO_*INT operation of the specified operand when the target requests that 336/// we promote it. At this point, we know that the result and operand types are 337/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 338/// operation that returns a larger result. 339SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 340 MVT::ValueType DestVT, 341 bool isSigned) { 342 // First step, figure out the appropriate FP_TO*INT operation to use. 343 MVT::ValueType NewOutTy = DestVT; 344 345 unsigned OpToUse = 0; 346 347 // Scan for the appropriate larger type to use. 348 while (1) { 349 NewOutTy = (MVT::ValueType)(NewOutTy+1); 350 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 351 352 // If the target supports FP_TO_SINT returning this type, use it. 353 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 354 default: break; 355 case TargetLowering::Legal: 356 if (!TLI.isTypeLegal(NewOutTy)) 357 break; // Can't use this datatype. 358 // FALL THROUGH. 359 case TargetLowering::Custom: 360 OpToUse = ISD::FP_TO_SINT; 361 break; 362 } 363 if (OpToUse) break; 364 365 // If the target supports FP_TO_UINT of this type, use it. 366 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 367 default: break; 368 case TargetLowering::Legal: 369 if (!TLI.isTypeLegal(NewOutTy)) 370 break; // Can't use this datatype. 371 // FALL THROUGH. 372 case TargetLowering::Custom: 373 OpToUse = ISD::FP_TO_UINT; 374 break; 375 } 376 if (OpToUse) break; 377 378 // Otherwise, try a larger type. 379 } 380 381 // Make sure to legalize any nodes we create here in the next pass. 382 NeedsAnotherIteration = true; 383 384 // Okay, we found the operation and type to use. Truncate the result of the 385 // extended FP_TO_*INT operation to the desired size. 386 return DAG.getNode(ISD::TRUNCATE, DestVT, 387 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 388} 389 390/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 391/// not been visited yet and if all of its operands have already been visited. 392static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 393 std::map<SDNode*, unsigned> &Visited) { 394 if (++Visited[N] != N->getNumOperands()) 395 return; // Haven't visited all operands yet 396 397 Order.push_back(N); 398 399 if (N->hasOneUse()) { // Tail recurse in common case. 400 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 401 return; 402 } 403 404 // Now that we have N in, add anything that uses it if all of their operands 405 // are now done. 406 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 407 ComputeTopDownOrdering(*UI, Order, Visited); 408} 409 410 411void SelectionDAGLegalize::LegalizeDAG() { 412 // The legalize process is inherently a bottom-up recursive process (users 413 // legalize their uses before themselves). Given infinite stack space, we 414 // could just start legalizing on the root and traverse the whole graph. In 415 // practice however, this causes us to run out of stack space on large basic 416 // blocks. To avoid this problem, compute an ordering of the nodes where each 417 // node is only legalized after all of its operands are legalized. 418 std::map<SDNode*, unsigned> Visited; 419 std::vector<SDNode*> Order; 420 421 // Compute ordering from all of the leaves in the graphs, those (like the 422 // entry node) that have no operands. 423 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 424 E = DAG.allnodes_end(); I != E; ++I) { 425 if (I->getNumOperands() == 0) { 426 Visited[I] = 0 - 1U; 427 ComputeTopDownOrdering(I, Order, Visited); 428 } 429 } 430 431 assert(Order.size() == Visited.size() && 432 Order.size() == 433 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 434 "Error: DAG is cyclic!"); 435 Visited.clear(); 436 437 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 438 SDNode *N = Order[i]; 439 switch (getTypeAction(N->getValueType(0))) { 440 default: assert(0 && "Bad type action!"); 441 case Legal: 442 LegalizeOp(SDOperand(N, 0)); 443 break; 444 case Promote: 445 PromoteOp(SDOperand(N, 0)); 446 break; 447 case Expand: { 448 SDOperand X, Y; 449 ExpandOp(SDOperand(N, 0), X, Y); 450 break; 451 } 452 } 453 } 454 455 // Finally, it's possible the root changed. Get the new root. 456 SDOperand OldRoot = DAG.getRoot(); 457 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 458 DAG.setRoot(LegalizedNodes[OldRoot]); 459 460 ExpandedNodes.clear(); 461 LegalizedNodes.clear(); 462 PromotedNodes.clear(); 463 464 // Remove dead nodes now. 465 DAG.RemoveDeadNodes(OldRoot.Val); 466} 467 468SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 469 assert(isTypeLegal(Op.getValueType()) && 470 "Caller should expand or promote operands that are not legal!"); 471 SDNode *Node = Op.Val; 472 473 // If this operation defines any values that cannot be represented in a 474 // register on this target, make sure to expand or promote them. 475 if (Node->getNumValues() > 1) { 476 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 477 switch (getTypeAction(Node->getValueType(i))) { 478 case Legal: break; // Nothing to do. 479 case Expand: { 480 SDOperand T1, T2; 481 ExpandOp(Op.getValue(i), T1, T2); 482 assert(LegalizedNodes.count(Op) && 483 "Expansion didn't add legal operands!"); 484 return LegalizedNodes[Op]; 485 } 486 case Promote: 487 PromoteOp(Op.getValue(i)); 488 assert(LegalizedNodes.count(Op) && 489 "Expansion didn't add legal operands!"); 490 return LegalizedNodes[Op]; 491 } 492 } 493 494 // Note that LegalizeOp may be reentered even from single-use nodes, which 495 // means that we always must cache transformed nodes. 496 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 497 if (I != LegalizedNodes.end()) return I->second; 498 499 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 500 501 SDOperand Result = Op; 502 503 switch (Node->getOpcode()) { 504 default: 505 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 506 // If this is a target node, legalize it by legalizing the operands then 507 // passing it through. 508 std::vector<SDOperand> Ops; 509 bool Changed = false; 510 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 511 Ops.push_back(LegalizeOp(Node->getOperand(i))); 512 Changed = Changed || Node->getOperand(i) != Ops.back(); 513 } 514 if (Changed) 515 if (Node->getNumValues() == 1) 516 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 517 else { 518 std::vector<MVT::ValueType> VTs(Node->value_begin(), 519 Node->value_end()); 520 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 521 } 522 523 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 524 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 525 return Result.getValue(Op.ResNo); 526 } 527 // Otherwise this is an unhandled builtin node. splat. 528 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 529 assert(0 && "Do not know how to legalize this operator!"); 530 abort(); 531 case ISD::EntryToken: 532 case ISD::FrameIndex: 533 case ISD::TargetFrameIndex: 534 case ISD::Register: 535 case ISD::TargetConstant: 536 case ISD::GlobalAddress: 537 case ISD::TargetGlobalAddress: 538 case ISD::ExternalSymbol: 539 case ISD::ConstantPool: // Nothing to do. 540 case ISD::BasicBlock: 541 case ISD::CONDCODE: 542 case ISD::VALUETYPE: 543 case ISD::SRCVALUE: 544 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 545 default: assert(0 && "This action is not supported yet!"); 546 case TargetLowering::Custom: { 547 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 548 if (Tmp.Val) { 549 Result = LegalizeOp(Tmp); 550 break; 551 } 552 } // FALLTHROUGH if the target doesn't want to lower this op after all. 553 case TargetLowering::Legal: 554 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!"); 555 break; 556 } 557 break; 558 case ISD::AssertSext: 559 case ISD::AssertZext: 560 Tmp1 = LegalizeOp(Node->getOperand(0)); 561 if (Tmp1 != Node->getOperand(0)) 562 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 563 Node->getOperand(1)); 564 break; 565 case ISD::CopyFromReg: 566 Tmp1 = LegalizeOp(Node->getOperand(0)); 567 if (Tmp1 != Node->getOperand(0)) 568 Result = DAG.getCopyFromReg(Tmp1, 569 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 570 Node->getValueType(0)); 571 else 572 Result = Op.getValue(0); 573 574 // Since CopyFromReg produces two values, make sure to remember that we 575 // legalized both of them. 576 AddLegalizedOperand(Op.getValue(0), Result); 577 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 578 return Result.getValue(Op.ResNo); 579 case ISD::ImplicitDef: 580 Tmp1 = LegalizeOp(Node->getOperand(0)); 581 if (Tmp1 != Node->getOperand(0)) 582 Result = DAG.getNode(ISD::ImplicitDef, MVT::Other, 583 Tmp1, Node->getOperand(1)); 584 break; 585 case ISD::UNDEF: { 586 MVT::ValueType VT = Op.getValueType(); 587 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 588 default: assert(0 && "This action is not supported yet!"); 589 case TargetLowering::Expand: 590 case TargetLowering::Promote: 591 if (MVT::isInteger(VT)) 592 Result = DAG.getConstant(0, VT); 593 else if (MVT::isFloatingPoint(VT)) 594 Result = DAG.getConstantFP(0, VT); 595 else 596 assert(0 && "Unknown value type!"); 597 break; 598 case TargetLowering::Legal: 599 break; 600 } 601 break; 602 } 603 case ISD::Constant: 604 // We know we don't need to expand constants here, constants only have one 605 // value and we check that it is fine above. 606 607 // FIXME: Maybe we should handle things like targets that don't support full 608 // 32-bit immediates? 609 break; 610 case ISD::ConstantFP: { 611 // Spill FP immediates to the constant pool if the target cannot directly 612 // codegen them. Targets often have some immediate values that can be 613 // efficiently generated into an FP register without a load. We explicitly 614 // leave these constants as ConstantFP nodes for the target to deal with. 615 616 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 617 618 // Check to see if this FP immediate is already legal. 619 bool isLegal = false; 620 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 621 E = TLI.legal_fpimm_end(); I != E; ++I) 622 if (CFP->isExactlyValue(*I)) { 623 isLegal = true; 624 break; 625 } 626 627 if (!isLegal) { 628 // Otherwise we need to spill the constant to memory. 629 bool Extend = false; 630 631 // If a FP immediate is precise when represented as a float, we put it 632 // into the constant pool as a float, even if it's is statically typed 633 // as a double. 634 MVT::ValueType VT = CFP->getValueType(0); 635 bool isDouble = VT == MVT::f64; 636 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 637 Type::FloatTy, CFP->getValue()); 638 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 639 // Only do this if the target has a native EXTLOAD instruction from 640 // f32. 641 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 642 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 643 VT = MVT::f32; 644 Extend = true; 645 } 646 647 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 648 if (Extend) { 649 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 650 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 651 } else { 652 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 653 DAG.getSrcValue(NULL)); 654 } 655 } 656 break; 657 } 658 case ISD::TokenFactor: 659 if (Node->getNumOperands() == 2) { 660 bool Changed = false; 661 SDOperand Op0 = LegalizeOp(Node->getOperand(0)); 662 SDOperand Op1 = LegalizeOp(Node->getOperand(1)); 663 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1)) 664 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1); 665 } else { 666 std::vector<SDOperand> Ops; 667 bool Changed = false; 668 // Legalize the operands. 669 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 670 SDOperand Op = Node->getOperand(i); 671 Ops.push_back(LegalizeOp(Op)); 672 Changed |= Ops[i] != Op; 673 } 674 if (Changed) 675 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 676 } 677 break; 678 679 case ISD::CALLSEQ_START: 680 case ISD::CALLSEQ_END: 681 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 682 // Do not try to legalize the target-specific arguments (#1+) 683 Tmp2 = Node->getOperand(0); 684 if (Tmp1 != Tmp2) 685 Node->setAdjCallChain(Tmp1); 686 687 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These 688 // nodes are treated specially and are mutated in place. This makes the dag 689 // legalization process more efficient and also makes libcall insertion 690 // easier. 691 break; 692 case ISD::DYNAMIC_STACKALLOC: 693 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 694 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 695 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 696 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 697 Tmp3 != Node->getOperand(2)) { 698 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 699 std::vector<SDOperand> Ops; 700 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 701 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 702 } else 703 Result = Op.getValue(0); 704 705 // Since this op produces two values, make sure to remember that we 706 // legalized both of them. 707 AddLegalizedOperand(SDOperand(Node, 0), Result); 708 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 709 return Result.getValue(Op.ResNo); 710 711 case ISD::TAILCALL: 712 case ISD::CALL: { 713 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 714 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 715 716 bool Changed = false; 717 std::vector<SDOperand> Ops; 718 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 719 Ops.push_back(LegalizeOp(Node->getOperand(i))); 720 Changed |= Ops.back() != Node->getOperand(i); 721 } 722 723 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 724 std::vector<MVT::ValueType> RetTyVTs; 725 RetTyVTs.reserve(Node->getNumValues()); 726 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 727 RetTyVTs.push_back(Node->getValueType(i)); 728 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 729 Node->getOpcode() == ISD::TAILCALL), 0); 730 } else { 731 Result = Result.getValue(0); 732 } 733 // Since calls produce multiple values, make sure to remember that we 734 // legalized all of them. 735 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 736 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 737 return Result.getValue(Op.ResNo); 738 } 739 case ISD::BR: 740 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 741 if (Tmp1 != Node->getOperand(0)) 742 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 743 break; 744 745 case ISD::BRCOND: 746 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 747 748 switch (getTypeAction(Node->getOperand(1).getValueType())) { 749 case Expand: assert(0 && "It's impossible to expand bools"); 750 case Legal: 751 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 752 break; 753 case Promote: 754 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 755 break; 756 } 757 758 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 759 default: assert(0 && "This action is not supported yet!"); 760 case TargetLowering::Expand: 761 // Expand brcond's setcc into its constituent parts and create a BR_CC 762 // Node. 763 if (Tmp2.getOpcode() == ISD::SETCC) { 764 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 765 Tmp2.getOperand(0), Tmp2.getOperand(1), 766 Node->getOperand(2)); 767 } else { 768 // Make sure the condition is either zero or one. It may have been 769 // promoted from something else. 770 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 771 772 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 773 DAG.getCondCode(ISD::SETNE), Tmp2, 774 DAG.getConstant(0, Tmp2.getValueType()), 775 Node->getOperand(2)); 776 } 777 break; 778 case TargetLowering::Legal: 779 // Basic block destination (Op#2) is always legal. 780 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 781 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 782 Node->getOperand(2)); 783 break; 784 } 785 break; 786 case ISD::BR_CC: 787 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 788 789 if (isTypeLegal(Node->getOperand(2).getValueType())) { 790 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 791 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 792 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 793 Tmp3 != Node->getOperand(3)) { 794 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 795 Tmp2, Tmp3, Node->getOperand(4)); 796 } 797 break; 798 } else { 799 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 800 Node->getOperand(2), // LHS 801 Node->getOperand(3), // RHS 802 Node->getOperand(1))); 803 // If we get a SETCC back from legalizing the SETCC node we just 804 // created, then use its LHS, RHS, and CC directly in creating a new 805 // node. Otherwise, select between the true and false value based on 806 // comparing the result of the legalized with zero. 807 if (Tmp2.getOpcode() == ISD::SETCC) { 808 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 809 Tmp2.getOperand(0), Tmp2.getOperand(1), 810 Node->getOperand(4)); 811 } else { 812 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 813 DAG.getCondCode(ISD::SETNE), 814 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 815 Node->getOperand(4)); 816 } 817 } 818 break; 819 case ISD::BRCONDTWOWAY: 820 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 821 switch (getTypeAction(Node->getOperand(1).getValueType())) { 822 case Expand: assert(0 && "It's impossible to expand bools"); 823 case Legal: 824 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 825 break; 826 case Promote: 827 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 828 break; 829 } 830 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 831 // pair. 832 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 833 case TargetLowering::Promote: 834 default: assert(0 && "This action is not supported yet!"); 835 case TargetLowering::Legal: 836 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 837 std::vector<SDOperand> Ops; 838 Ops.push_back(Tmp1); 839 Ops.push_back(Tmp2); 840 Ops.push_back(Node->getOperand(2)); 841 Ops.push_back(Node->getOperand(3)); 842 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 843 } 844 break; 845 case TargetLowering::Expand: 846 // If BRTWOWAY_CC is legal for this target, then simply expand this node 847 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 848 // BRCOND/BR pair. 849 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 850 if (Tmp2.getOpcode() == ISD::SETCC) { 851 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 852 Tmp2.getOperand(0), Tmp2.getOperand(1), 853 Node->getOperand(2), Node->getOperand(3)); 854 } else { 855 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 856 DAG.getConstant(0, Tmp2.getValueType()), 857 Node->getOperand(2), Node->getOperand(3)); 858 } 859 } else { 860 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 861 Node->getOperand(2)); 862 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 863 } 864 break; 865 } 866 break; 867 case ISD::BRTWOWAY_CC: 868 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 869 if (isTypeLegal(Node->getOperand(2).getValueType())) { 870 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 871 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 872 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 873 Tmp3 != Node->getOperand(3)) { 874 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3, 875 Node->getOperand(4), Node->getOperand(5)); 876 } 877 break; 878 } else { 879 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 880 Node->getOperand(2), // LHS 881 Node->getOperand(3), // RHS 882 Node->getOperand(1))); 883 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 884 // pair. 885 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 886 default: assert(0 && "This action is not supported yet!"); 887 case TargetLowering::Legal: 888 // If we get a SETCC back from legalizing the SETCC node we just 889 // created, then use its LHS, RHS, and CC directly in creating a new 890 // node. Otherwise, select between the true and false value based on 891 // comparing the result of the legalized with zero. 892 if (Tmp2.getOpcode() == ISD::SETCC) { 893 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 894 Tmp2.getOperand(0), Tmp2.getOperand(1), 895 Node->getOperand(4), Node->getOperand(5)); 896 } else { 897 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 898 DAG.getConstant(0, Tmp2.getValueType()), 899 Node->getOperand(4), Node->getOperand(5)); 900 } 901 break; 902 case TargetLowering::Expand: 903 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 904 Node->getOperand(4)); 905 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 906 break; 907 } 908 } 909 break; 910 case ISD::LOAD: 911 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 912 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 913 914 if (Tmp1 != Node->getOperand(0) || 915 Tmp2 != Node->getOperand(1)) 916 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, 917 Node->getOperand(2)); 918 else 919 Result = SDOperand(Node, 0); 920 921 // Since loads produce two values, make sure to remember that we legalized 922 // both of them. 923 AddLegalizedOperand(SDOperand(Node, 0), Result); 924 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 925 return Result.getValue(Op.ResNo); 926 927 case ISD::VLOAD: 928 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 929 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 930 931 // If we just have one element, scalarize the result. Otherwise, check to 932 // see if we support this operation on this type at this width. If not, 933 // split the vector in half and try again. 934 if (1 == cast<ConstantSDNode>(Node->getOperand(2))->getValue()) { 935 MVT::ValueType SVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 936 Result = LegalizeOp(DAG.getLoad(SVT, Tmp1, Tmp2, Node->getOperand(4))); 937 } else { 938 assert(0 && "Expand case for vectors unimplemented"); 939 } 940 941 // Since loads produce two values, make sure to remember that we legalized 942 // both of them. 943 AddLegalizedOperand(SDOperand(Node, 0), Result); 944 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 945 return Result.getValue(Op.ResNo); 946 947 case ISD::EXTLOAD: 948 case ISD::SEXTLOAD: 949 case ISD::ZEXTLOAD: { 950 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 951 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 952 953 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 954 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 955 default: assert(0 && "This action is not supported yet!"); 956 case TargetLowering::Promote: 957 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 958 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 959 Tmp1, Tmp2, Node->getOperand(2), MVT::i8); 960 // Since loads produce two values, make sure to remember that we legalized 961 // both of them. 962 AddLegalizedOperand(SDOperand(Node, 0), Result); 963 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 964 return Result.getValue(Op.ResNo); 965 966 case TargetLowering::Legal: 967 if (Tmp1 != Node->getOperand(0) || 968 Tmp2 != Node->getOperand(1)) 969 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 970 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 971 else 972 Result = SDOperand(Node, 0); 973 974 // Since loads produce two values, make sure to remember that we legalized 975 // both of them. 976 AddLegalizedOperand(SDOperand(Node, 0), Result); 977 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 978 return Result.getValue(Op.ResNo); 979 case TargetLowering::Expand: 980 //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 981 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 982 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 983 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 984 if (Op.ResNo) 985 return Load.getValue(1); 986 return Result; 987 } 988 assert(Node->getOpcode() != ISD::EXTLOAD && 989 "EXTLOAD should always be supported!"); 990 // Turn the unsupported load into an EXTLOAD followed by an explicit 991 // zero/sign extend inreg. 992 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 993 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 994 SDOperand ValRes; 995 if (Node->getOpcode() == ISD::SEXTLOAD) 996 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 997 Result, DAG.getValueType(SrcVT)); 998 else 999 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1000 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 1001 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1002 if (Op.ResNo) 1003 return Result.getValue(1); 1004 return ValRes; 1005 } 1006 assert(0 && "Unreachable"); 1007 } 1008 case ISD::EXTRACT_ELEMENT: { 1009 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1010 switch (getTypeAction(OpTy)) { 1011 default: 1012 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1013 break; 1014 case Legal: 1015 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1016 // 1 -> Hi 1017 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1018 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1019 TLI.getShiftAmountTy())); 1020 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1021 } else { 1022 // 0 -> Lo 1023 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1024 Node->getOperand(0)); 1025 } 1026 Result = LegalizeOp(Result); 1027 break; 1028 case Expand: 1029 // Get both the low and high parts. 1030 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1031 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1032 Result = Tmp2; // 1 -> Hi 1033 else 1034 Result = Tmp1; // 0 -> Lo 1035 break; 1036 } 1037 break; 1038 } 1039 1040 case ISD::CopyToReg: 1041 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1042 1043 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1044 "Register type must be legal!"); 1045 // Legalize the incoming value (must be legal). 1046 Tmp2 = LegalizeOp(Node->getOperand(2)); 1047 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2)) 1048 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1, 1049 Node->getOperand(1), Tmp2); 1050 break; 1051 1052 case ISD::RET: 1053 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1054 switch (Node->getNumOperands()) { 1055 case 2: // ret val 1056 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1057 case Legal: 1058 Tmp2 = LegalizeOp(Node->getOperand(1)); 1059 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1060 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1061 break; 1062 case Expand: { 1063 SDOperand Lo, Hi; 1064 ExpandOp(Node->getOperand(1), Lo, Hi); 1065 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1066 break; 1067 } 1068 case Promote: 1069 Tmp2 = PromoteOp(Node->getOperand(1)); 1070 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1071 break; 1072 } 1073 break; 1074 case 1: // ret void 1075 if (Tmp1 != Node->getOperand(0)) 1076 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 1077 break; 1078 default: { // ret <values> 1079 std::vector<SDOperand> NewValues; 1080 NewValues.push_back(Tmp1); 1081 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1082 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1083 case Legal: 1084 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1085 break; 1086 case Expand: { 1087 SDOperand Lo, Hi; 1088 ExpandOp(Node->getOperand(i), Lo, Hi); 1089 NewValues.push_back(Lo); 1090 NewValues.push_back(Hi); 1091 break; 1092 } 1093 case Promote: 1094 assert(0 && "Can't promote multiple return value yet!"); 1095 } 1096 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1097 break; 1098 } 1099 } 1100 break; 1101 case ISD::STORE: 1102 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1103 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1104 1105 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1106 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1107 if (CFP->getValueType(0) == MVT::f32) { 1108 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1109 DAG.getConstant(FloatToBits(CFP->getValue()), 1110 MVT::i32), 1111 Tmp2, 1112 Node->getOperand(3)); 1113 } else { 1114 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1115 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1116 DAG.getConstant(DoubleToBits(CFP->getValue()), 1117 MVT::i64), 1118 Tmp2, 1119 Node->getOperand(3)); 1120 } 1121 Node = Result.Val; 1122 } 1123 1124 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1125 case Legal: { 1126 SDOperand Val = LegalizeOp(Node->getOperand(1)); 1127 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 1128 Tmp2 != Node->getOperand(2)) 1129 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, 1130 Node->getOperand(3)); 1131 break; 1132 } 1133 case Promote: 1134 // Truncate the value and store the result. 1135 Tmp3 = PromoteOp(Node->getOperand(1)); 1136 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1137 Node->getOperand(3), 1138 DAG.getValueType(Node->getOperand(1).getValueType())); 1139 break; 1140 1141 case Expand: 1142 SDOperand Lo, Hi; 1143 ExpandOp(Node->getOperand(1), Lo, Hi); 1144 1145 if (!TLI.isLittleEndian()) 1146 std::swap(Lo, Hi); 1147 1148 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1149 Node->getOperand(3)); 1150 unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1151 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1152 getIntPtrConstant(IncrementSize)); 1153 assert(isTypeLegal(Tmp2.getValueType()) && 1154 "Pointers must be legal!"); 1155 //Again, claiming both parts of the store came form the same Instr 1156 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1157 Node->getOperand(3)); 1158 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1159 break; 1160 } 1161 break; 1162 case ISD::PCMARKER: 1163 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1164 if (Tmp1 != Node->getOperand(0)) 1165 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 1166 break; 1167 case ISD::READCYCLECOUNTER: 1168 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1169 if (Tmp1 != Node->getOperand(0)) 1170 Result = DAG.getNode(ISD::READCYCLECOUNTER, MVT::i64, Tmp1); 1171 break; 1172 case ISD::TRUNCSTORE: 1173 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1174 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1175 1176 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1177 case Legal: 1178 Tmp2 = LegalizeOp(Node->getOperand(1)); 1179 1180 // The only promote case we handle is TRUNCSTORE:i1 X into 1181 // -> TRUNCSTORE:i8 (and X, 1) 1182 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1183 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1184 TargetLowering::Promote) { 1185 // Promote the bool to a mask then store. 1186 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1187 DAG.getConstant(1, Tmp2.getValueType())); 1188 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1189 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1190 1191 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1192 Tmp3 != Node->getOperand(2)) { 1193 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1194 Node->getOperand(3), Node->getOperand(4)); 1195 } 1196 break; 1197 case Promote: 1198 case Expand: 1199 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 1200 } 1201 break; 1202 case ISD::SELECT: 1203 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1204 case Expand: assert(0 && "It's impossible to expand bools"); 1205 case Legal: 1206 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1207 break; 1208 case Promote: 1209 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1210 break; 1211 } 1212 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1213 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1214 1215 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1216 default: assert(0 && "This action is not supported yet!"); 1217 case TargetLowering::Expand: 1218 if (Tmp1.getOpcode() == ISD::SETCC) { 1219 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1220 Tmp2, Tmp3, 1221 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1222 } else { 1223 // Make sure the condition is either zero or one. It may have been 1224 // promoted from something else. 1225 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1226 Result = DAG.getSelectCC(Tmp1, 1227 DAG.getConstant(0, Tmp1.getValueType()), 1228 Tmp2, Tmp3, ISD::SETNE); 1229 } 1230 break; 1231 case TargetLowering::Legal: 1232 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1233 Tmp3 != Node->getOperand(2)) 1234 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 1235 Tmp1, Tmp2, Tmp3); 1236 break; 1237 case TargetLowering::Promote: { 1238 MVT::ValueType NVT = 1239 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1240 unsigned ExtOp, TruncOp; 1241 if (MVT::isInteger(Tmp2.getValueType())) { 1242 ExtOp = ISD::ANY_EXTEND; 1243 TruncOp = ISD::TRUNCATE; 1244 } else { 1245 ExtOp = ISD::FP_EXTEND; 1246 TruncOp = ISD::FP_ROUND; 1247 } 1248 // Promote each of the values to the new type. 1249 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1250 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1251 // Perform the larger operation, then round down. 1252 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1253 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1254 break; 1255 } 1256 } 1257 break; 1258 case ISD::SELECT_CC: 1259 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1260 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1261 1262 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1263 // Everything is legal, see if we should expand this op or something. 1264 switch (TLI.getOperationAction(ISD::SELECT_CC, 1265 Node->getOperand(0).getValueType())) { 1266 default: assert(0 && "This action is not supported yet!"); 1267 case TargetLowering::Custom: { 1268 SDOperand Tmp = 1269 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), 1270 Node->getOperand(0), 1271 Node->getOperand(1), Tmp3, Tmp4, 1272 Node->getOperand(4)), DAG); 1273 if (Tmp.Val) { 1274 Result = LegalizeOp(Tmp); 1275 break; 1276 } 1277 } // FALLTHROUGH if the target can't lower this operation after all. 1278 case TargetLowering::Legal: 1279 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1280 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1281 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1282 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { 1283 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2, 1284 Tmp3, Tmp4, Node->getOperand(4)); 1285 } 1286 break; 1287 } 1288 break; 1289 } else { 1290 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1291 Node->getOperand(0), // LHS 1292 Node->getOperand(1), // RHS 1293 Node->getOperand(4))); 1294 // If we get a SETCC back from legalizing the SETCC node we just 1295 // created, then use its LHS, RHS, and CC directly in creating a new 1296 // node. Otherwise, select between the true and false value based on 1297 // comparing the result of the legalized with zero. 1298 if (Tmp1.getOpcode() == ISD::SETCC) { 1299 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1300 Tmp1.getOperand(0), Tmp1.getOperand(1), 1301 Tmp3, Tmp4, Tmp1.getOperand(2)); 1302 } else { 1303 Result = DAG.getSelectCC(Tmp1, 1304 DAG.getConstant(0, Tmp1.getValueType()), 1305 Tmp3, Tmp4, ISD::SETNE); 1306 } 1307 } 1308 break; 1309 case ISD::SETCC: 1310 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1311 case Legal: 1312 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1313 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1314 break; 1315 case Promote: 1316 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1317 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1318 1319 // If this is an FP compare, the operands have already been extended. 1320 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1321 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1322 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1323 1324 // Otherwise, we have to insert explicit sign or zero extends. Note 1325 // that we could insert sign extends for ALL conditions, but zero extend 1326 // is cheaper on many machines (an AND instead of two shifts), so prefer 1327 // it. 1328 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1329 default: assert(0 && "Unknown integer comparison!"); 1330 case ISD::SETEQ: 1331 case ISD::SETNE: 1332 case ISD::SETUGE: 1333 case ISD::SETUGT: 1334 case ISD::SETULE: 1335 case ISD::SETULT: 1336 // ALL of these operations will work if we either sign or zero extend 1337 // the operands (including the unsigned comparisons!). Zero extend is 1338 // usually a simpler/cheaper operation, so prefer it. 1339 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1340 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1341 break; 1342 case ISD::SETGE: 1343 case ISD::SETGT: 1344 case ISD::SETLT: 1345 case ISD::SETLE: 1346 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1347 DAG.getValueType(VT)); 1348 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1349 DAG.getValueType(VT)); 1350 break; 1351 } 1352 } 1353 break; 1354 case Expand: 1355 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1356 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1357 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1358 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1359 case ISD::SETEQ: 1360 case ISD::SETNE: 1361 if (RHSLo == RHSHi) 1362 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1363 if (RHSCST->isAllOnesValue()) { 1364 // Comparison to -1. 1365 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1366 Tmp2 = RHSLo; 1367 break; 1368 } 1369 1370 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1371 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1372 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1373 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1374 break; 1375 default: 1376 // If this is a comparison of the sign bit, just look at the top part. 1377 // X > -1, x < 0 1378 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1379 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1380 CST->getValue() == 0) || // X < 0 1381 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1382 (CST->isAllOnesValue()))) { // X > -1 1383 Tmp1 = LHSHi; 1384 Tmp2 = RHSHi; 1385 break; 1386 } 1387 1388 // FIXME: This generated code sucks. 1389 ISD::CondCode LowCC; 1390 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1391 default: assert(0 && "Unknown integer setcc!"); 1392 case ISD::SETLT: 1393 case ISD::SETULT: LowCC = ISD::SETULT; break; 1394 case ISD::SETGT: 1395 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1396 case ISD::SETLE: 1397 case ISD::SETULE: LowCC = ISD::SETULE; break; 1398 case ISD::SETGE: 1399 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1400 } 1401 1402 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1403 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1404 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1405 1406 // NOTE: on targets without efficient SELECT of bools, we can always use 1407 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1408 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1409 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1410 Node->getOperand(2)); 1411 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1412 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1413 Result, Tmp1, Tmp2)); 1414 return Result; 1415 } 1416 } 1417 1418 switch(TLI.getOperationAction(ISD::SETCC, Node->getOperand(0).getValueType())) { 1419 default: 1420 assert(0 && "Cannot handle this action for SETCC yet!"); 1421 break; 1422 case TargetLowering::Promote: 1423 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1424 Node->getOperand(2)); 1425 break; 1426 case TargetLowering::Legal: 1427 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1428 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1429 Node->getOperand(2)); 1430 break; 1431 case TargetLowering::Expand: 1432 // Expand a setcc node into a select_cc of the same condition, lhs, and 1433 // rhs that selects between const 1 (true) and const 0 (false). 1434 MVT::ValueType VT = Node->getValueType(0); 1435 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1436 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1437 Node->getOperand(2)); 1438 Result = LegalizeOp(Result); 1439 break; 1440 } 1441 break; 1442 1443 case ISD::MEMSET: 1444 case ISD::MEMCPY: 1445 case ISD::MEMMOVE: { 1446 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1447 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1448 1449 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1450 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1451 case Expand: assert(0 && "Cannot expand a byte!"); 1452 case Legal: 1453 Tmp3 = LegalizeOp(Node->getOperand(2)); 1454 break; 1455 case Promote: 1456 Tmp3 = PromoteOp(Node->getOperand(2)); 1457 break; 1458 } 1459 } else { 1460 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1461 } 1462 1463 SDOperand Tmp4; 1464 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1465 case Expand: { 1466 // Length is too big, just take the lo-part of the length. 1467 SDOperand HiPart; 1468 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1469 break; 1470 } 1471 case Legal: 1472 Tmp4 = LegalizeOp(Node->getOperand(3)); 1473 break; 1474 case Promote: 1475 Tmp4 = PromoteOp(Node->getOperand(3)); 1476 break; 1477 } 1478 1479 SDOperand Tmp5; 1480 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1481 case Expand: assert(0 && "Cannot expand this yet!"); 1482 case Legal: 1483 Tmp5 = LegalizeOp(Node->getOperand(4)); 1484 break; 1485 case Promote: 1486 Tmp5 = PromoteOp(Node->getOperand(4)); 1487 break; 1488 } 1489 1490 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1491 default: assert(0 && "This action not implemented for this operation!"); 1492 case TargetLowering::Custom: { 1493 SDOperand Tmp = 1494 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 1495 Tmp2, Tmp3, Tmp4, Tmp5), DAG); 1496 if (Tmp.Val) { 1497 Result = LegalizeOp(Tmp); 1498 break; 1499 } 1500 // FALLTHROUGH if the target thinks it is legal. 1501 } 1502 case TargetLowering::Legal: 1503 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1504 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 1505 Tmp5 != Node->getOperand(4)) { 1506 std::vector<SDOperand> Ops; 1507 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 1508 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 1509 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 1510 } 1511 break; 1512 case TargetLowering::Expand: { 1513 // Otherwise, the target does not support this operation. Lower the 1514 // operation to an explicit libcall as appropriate. 1515 MVT::ValueType IntPtr = TLI.getPointerTy(); 1516 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1517 std::vector<std::pair<SDOperand, const Type*> > Args; 1518 1519 const char *FnName = 0; 1520 if (Node->getOpcode() == ISD::MEMSET) { 1521 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1522 // Extend the ubyte argument to be an int value for the call. 1523 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1524 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1525 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1526 1527 FnName = "memset"; 1528 } else if (Node->getOpcode() == ISD::MEMCPY || 1529 Node->getOpcode() == ISD::MEMMOVE) { 1530 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1531 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1532 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1533 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1534 } else { 1535 assert(0 && "Unknown op!"); 1536 } 1537 1538 std::pair<SDOperand,SDOperand> CallResult = 1539 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1540 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1541 Result = CallResult.second; 1542 NeedsAnotherIteration = true; 1543 break; 1544 } 1545 } 1546 break; 1547 } 1548 1549 case ISD::READPORT: 1550 Tmp1 = LegalizeOp(Node->getOperand(0)); 1551 Tmp2 = LegalizeOp(Node->getOperand(1)); 1552 1553 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1554 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1555 std::vector<SDOperand> Ops; 1556 Ops.push_back(Tmp1); 1557 Ops.push_back(Tmp2); 1558 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1559 } else 1560 Result = SDOperand(Node, 0); 1561 // Since these produce two values, make sure to remember that we legalized 1562 // both of them. 1563 AddLegalizedOperand(SDOperand(Node, 0), Result); 1564 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1565 return Result.getValue(Op.ResNo); 1566 case ISD::WRITEPORT: 1567 Tmp1 = LegalizeOp(Node->getOperand(0)); 1568 Tmp2 = LegalizeOp(Node->getOperand(1)); 1569 Tmp3 = LegalizeOp(Node->getOperand(2)); 1570 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1571 Tmp3 != Node->getOperand(2)) 1572 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1573 break; 1574 1575 case ISD::READIO: 1576 Tmp1 = LegalizeOp(Node->getOperand(0)); 1577 Tmp2 = LegalizeOp(Node->getOperand(1)); 1578 1579 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1580 case TargetLowering::Custom: 1581 default: assert(0 && "This action not implemented for this operation!"); 1582 case TargetLowering::Legal: 1583 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1584 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1585 std::vector<SDOperand> Ops; 1586 Ops.push_back(Tmp1); 1587 Ops.push_back(Tmp2); 1588 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1589 } else 1590 Result = SDOperand(Node, 0); 1591 break; 1592 case TargetLowering::Expand: 1593 // Replace this with a load from memory. 1594 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 1595 Node->getOperand(1), DAG.getSrcValue(NULL)); 1596 Result = LegalizeOp(Result); 1597 break; 1598 } 1599 1600 // Since these produce two values, make sure to remember that we legalized 1601 // both of them. 1602 AddLegalizedOperand(SDOperand(Node, 0), Result); 1603 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1604 return Result.getValue(Op.ResNo); 1605 1606 case ISD::WRITEIO: 1607 Tmp1 = LegalizeOp(Node->getOperand(0)); 1608 Tmp2 = LegalizeOp(Node->getOperand(1)); 1609 Tmp3 = LegalizeOp(Node->getOperand(2)); 1610 1611 switch (TLI.getOperationAction(Node->getOpcode(), 1612 Node->getOperand(1).getValueType())) { 1613 case TargetLowering::Custom: 1614 default: assert(0 && "This action not implemented for this operation!"); 1615 case TargetLowering::Legal: 1616 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1617 Tmp3 != Node->getOperand(2)) 1618 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1619 break; 1620 case TargetLowering::Expand: 1621 // Replace this with a store to memory. 1622 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 1623 Node->getOperand(1), Node->getOperand(2), 1624 DAG.getSrcValue(NULL)); 1625 Result = LegalizeOp(Result); 1626 break; 1627 } 1628 break; 1629 1630 case ISD::ADD_PARTS: 1631 case ISD::SUB_PARTS: 1632 case ISD::SHL_PARTS: 1633 case ISD::SRA_PARTS: 1634 case ISD::SRL_PARTS: { 1635 std::vector<SDOperand> Ops; 1636 bool Changed = false; 1637 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1638 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1639 Changed |= Ops.back() != Node->getOperand(i); 1640 } 1641 if (Changed) { 1642 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1643 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 1644 } 1645 1646 // Since these produce multiple values, make sure to remember that we 1647 // legalized all of them. 1648 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1649 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1650 return Result.getValue(Op.ResNo); 1651 } 1652 1653 // Binary operators 1654 case ISD::ADD: 1655 case ISD::SUB: 1656 case ISD::MUL: 1657 case ISD::MULHS: 1658 case ISD::MULHU: 1659 case ISD::UDIV: 1660 case ISD::SDIV: 1661 case ISD::AND: 1662 case ISD::OR: 1663 case ISD::XOR: 1664 case ISD::SHL: 1665 case ISD::SRL: 1666 case ISD::SRA: 1667 case ISD::FADD: 1668 case ISD::FSUB: 1669 case ISD::FMUL: 1670 case ISD::FDIV: 1671 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1672 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1673 case Expand: assert(0 && "Not possible"); 1674 case Legal: 1675 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 1676 break; 1677 case Promote: 1678 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 1679 break; 1680 } 1681 if (Tmp1 != Node->getOperand(0) || 1682 Tmp2 != Node->getOperand(1)) 1683 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 1684 break; 1685 1686 // Vector binary operators 1687 case ISD::VADD: 1688 case ISD::VSUB: 1689 case ISD::VMUL: { 1690 Tmp1 = Node->getOperand(0); // Element Count 1691 Tmp2 = Node->getOperand(1); // Element Type 1692 1693 // If we just have one element, scalarize the result. Otherwise, check to 1694 // see if we support this operation on this type at this width. If not, 1695 // split the vector in half and try again. 1696 if (1 == cast<ConstantSDNode>(Tmp1)->getValue()) { 1697 MVT::ValueType SVT = cast<VTSDNode>(Tmp2)->getVT(); 1698 1699 Result = DAG.getNode(scalarizedOpcode(Node->getOpcode(), SVT), SVT, 1700 LegalizeOp(Node->getOperand(2)), 1701 LegalizeOp(Node->getOperand(3))); 1702 } else { 1703 assert(0 && "Expand case for vectors unimplemented"); 1704 } 1705 break; 1706 } 1707 1708 case ISD::BUILD_PAIR: { 1709 MVT::ValueType PairTy = Node->getValueType(0); 1710 // TODO: handle the case where the Lo and Hi operands are not of legal type 1711 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 1712 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 1713 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 1714 case TargetLowering::Legal: 1715 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1716 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 1717 break; 1718 case TargetLowering::Promote: 1719 case TargetLowering::Custom: 1720 assert(0 && "Cannot promote/custom this yet!"); 1721 case TargetLowering::Expand: 1722 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 1723 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 1724 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 1725 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 1726 TLI.getShiftAmountTy())); 1727 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2)); 1728 break; 1729 } 1730 break; 1731 } 1732 1733 case ISD::UREM: 1734 case ISD::SREM: 1735 case ISD::FREM: 1736 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1737 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1738 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1739 case TargetLowering::Legal: 1740 if (Tmp1 != Node->getOperand(0) || 1741 Tmp2 != Node->getOperand(1)) 1742 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 1743 Tmp2); 1744 break; 1745 case TargetLowering::Promote: 1746 case TargetLowering::Custom: 1747 assert(0 && "Cannot promote/custom handle this yet!"); 1748 case TargetLowering::Expand: 1749 if (MVT::isInteger(Node->getValueType(0))) { 1750 MVT::ValueType VT = Node->getValueType(0); 1751 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 1752 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 1753 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 1754 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 1755 } else { 1756 // Floating point mod -> fmod libcall. 1757 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 1758 SDOperand Dummy; 1759 Result = ExpandLibCall(FnName, Node, Dummy); 1760 } 1761 break; 1762 } 1763 break; 1764 1765 case ISD::CTPOP: 1766 case ISD::CTTZ: 1767 case ISD::CTLZ: 1768 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 1769 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1770 case TargetLowering::Legal: 1771 if (Tmp1 != Node->getOperand(0)) 1772 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1773 break; 1774 case TargetLowering::Promote: { 1775 MVT::ValueType OVT = Tmp1.getValueType(); 1776 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1777 1778 // Zero extend the argument. 1779 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1780 // Perform the larger operation, then subtract if needed. 1781 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1782 switch(Node->getOpcode()) 1783 { 1784 case ISD::CTPOP: 1785 Result = Tmp1; 1786 break; 1787 case ISD::CTTZ: 1788 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 1789 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 1790 DAG.getConstant(getSizeInBits(NVT), NVT), 1791 ISD::SETEQ); 1792 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 1793 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 1794 break; 1795 case ISD::CTLZ: 1796 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 1797 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 1798 DAG.getConstant(getSizeInBits(NVT) - 1799 getSizeInBits(OVT), NVT)); 1800 break; 1801 } 1802 break; 1803 } 1804 case TargetLowering::Custom: 1805 assert(0 && "Cannot custom handle this yet!"); 1806 case TargetLowering::Expand: 1807 switch(Node->getOpcode()) 1808 { 1809 case ISD::CTPOP: { 1810 static const uint64_t mask[6] = { 1811 0x5555555555555555ULL, 0x3333333333333333ULL, 1812 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 1813 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 1814 }; 1815 MVT::ValueType VT = Tmp1.getValueType(); 1816 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1817 unsigned len = getSizeInBits(VT); 1818 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1819 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 1820 Tmp2 = DAG.getConstant(mask[i], VT); 1821 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1822 Tmp1 = DAG.getNode(ISD::ADD, VT, 1823 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), 1824 DAG.getNode(ISD::AND, VT, 1825 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), 1826 Tmp2)); 1827 } 1828 Result = Tmp1; 1829 break; 1830 } 1831 case ISD::CTLZ: { 1832 /* for now, we do this: 1833 x = x | (x >> 1); 1834 x = x | (x >> 2); 1835 ... 1836 x = x | (x >>16); 1837 x = x | (x >>32); // for 64-bit input 1838 return popcount(~x); 1839 1840 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ 1841 MVT::ValueType VT = Tmp1.getValueType(); 1842 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1843 unsigned len = getSizeInBits(VT); 1844 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1845 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1846 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, 1847 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); 1848 } 1849 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); 1850 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1851 break; 1852 } 1853 case ISD::CTTZ: { 1854 // for now, we use: { return popcount(~x & (x - 1)); } 1855 // unless the target has ctlz but not ctpop, in which case we use: 1856 // { return 32 - nlz(~x & (x-1)); } 1857 // see also http://www.hackersdelight.org/HDcode/ntz.cc 1858 MVT::ValueType VT = Tmp1.getValueType(); 1859 Tmp2 = DAG.getConstant(~0ULL, VT); 1860 Tmp3 = DAG.getNode(ISD::AND, VT, 1861 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), 1862 DAG.getNode(ISD::SUB, VT, Tmp1, 1863 DAG.getConstant(1, VT))); 1864 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead 1865 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 1866 TLI.isOperationLegal(ISD::CTLZ, VT)) { 1867 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, 1868 DAG.getConstant(getSizeInBits(VT), VT), 1869 DAG.getNode(ISD::CTLZ, VT, Tmp3))); 1870 } else { 1871 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1872 } 1873 break; 1874 } 1875 default: 1876 assert(0 && "Cannot expand this yet!"); 1877 break; 1878 } 1879 break; 1880 } 1881 break; 1882 1883 // Unary operators 1884 case ISD::FABS: 1885 case ISD::FNEG: 1886 case ISD::FSQRT: 1887 case ISD::FSIN: 1888 case ISD::FCOS: 1889 Tmp1 = LegalizeOp(Node->getOperand(0)); 1890 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1891 case TargetLowering::Legal: 1892 if (Tmp1 != Node->getOperand(0)) 1893 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1894 break; 1895 case TargetLowering::Promote: 1896 case TargetLowering::Custom: 1897 assert(0 && "Cannot promote/custom handle this yet!"); 1898 case TargetLowering::Expand: 1899 switch(Node->getOpcode()) { 1900 case ISD::FNEG: { 1901 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 1902 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 1903 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0), 1904 Tmp2, Tmp1)); 1905 break; 1906 } 1907 case ISD::FABS: { 1908 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 1909 MVT::ValueType VT = Node->getValueType(0); 1910 Tmp2 = DAG.getConstantFP(0.0, VT); 1911 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 1912 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 1913 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 1914 Result = LegalizeOp(Result); 1915 break; 1916 } 1917 case ISD::FSQRT: 1918 case ISD::FSIN: 1919 case ISD::FCOS: { 1920 MVT::ValueType VT = Node->getValueType(0); 1921 const char *FnName = 0; 1922 switch(Node->getOpcode()) { 1923 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 1924 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 1925 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 1926 default: assert(0 && "Unreachable!"); 1927 } 1928 SDOperand Dummy; 1929 Result = ExpandLibCall(FnName, Node, Dummy); 1930 break; 1931 } 1932 default: 1933 assert(0 && "Unreachable!"); 1934 } 1935 break; 1936 } 1937 break; 1938 1939 // Conversion operators. The source and destination have different types. 1940 case ISD::SINT_TO_FP: 1941 case ISD::UINT_TO_FP: { 1942 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 1943 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1944 case Legal: 1945 switch (TLI.getOperationAction(Node->getOpcode(), 1946 Node->getOperand(0).getValueType())) { 1947 default: assert(0 && "Unknown operation action!"); 1948 case TargetLowering::Expand: 1949 Result = ExpandLegalINT_TO_FP(isSigned, 1950 LegalizeOp(Node->getOperand(0)), 1951 Node->getValueType(0)); 1952 AddLegalizedOperand(Op, Result); 1953 return Result; 1954 case TargetLowering::Promote: 1955 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 1956 Node->getValueType(0), 1957 isSigned); 1958 AddLegalizedOperand(Op, Result); 1959 return Result; 1960 case TargetLowering::Legal: 1961 break; 1962 } 1963 1964 Tmp1 = LegalizeOp(Node->getOperand(0)); 1965 if (Tmp1 != Node->getOperand(0)) 1966 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1967 break; 1968 case Expand: 1969 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 1970 Node->getValueType(0), Node->getOperand(0)); 1971 break; 1972 case Promote: 1973 if (isSigned) { 1974 Result = PromoteOp(Node->getOperand(0)); 1975 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1976 Result, DAG.getValueType(Node->getOperand(0).getValueType())); 1977 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 1978 } else { 1979 Result = PromoteOp(Node->getOperand(0)); 1980 Result = DAG.getZeroExtendInReg(Result, 1981 Node->getOperand(0).getValueType()); 1982 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 1983 } 1984 break; 1985 } 1986 break; 1987 } 1988 case ISD::TRUNCATE: 1989 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1990 case Legal: 1991 Tmp1 = LegalizeOp(Node->getOperand(0)); 1992 if (Tmp1 != Node->getOperand(0)) 1993 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1994 break; 1995 case Expand: 1996 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1997 1998 // Since the result is legal, we should just be able to truncate the low 1999 // part of the source. 2000 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2001 break; 2002 case Promote: 2003 Result = PromoteOp(Node->getOperand(0)); 2004 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2005 break; 2006 } 2007 break; 2008 2009 case ISD::FP_TO_SINT: 2010 case ISD::FP_TO_UINT: 2011 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2012 case Legal: 2013 Tmp1 = LegalizeOp(Node->getOperand(0)); 2014 2015 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2016 default: assert(0 && "Unknown operation action!"); 2017 case TargetLowering::Expand: 2018 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2019 SDOperand True, False; 2020 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2021 MVT::ValueType NVT = Node->getValueType(0); 2022 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2023 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2024 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2025 Node->getOperand(0), Tmp2, ISD::SETLT); 2026 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2027 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2028 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2029 Tmp2)); 2030 False = DAG.getNode(ISD::XOR, NVT, False, 2031 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2032 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False)); 2033 return Result; 2034 } else { 2035 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2036 } 2037 break; 2038 case TargetLowering::Promote: 2039 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2040 Node->getOpcode() == ISD::FP_TO_SINT); 2041 AddLegalizedOperand(Op, Result); 2042 return Result; 2043 case TargetLowering::Custom: { 2044 SDOperand Tmp = 2045 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2046 Tmp = TLI.LowerOperation(Tmp, DAG); 2047 if (Tmp.Val) { 2048 AddLegalizedOperand(Op, Tmp); 2049 NeedsAnotherIteration = true; 2050 return Tmp; 2051 } else { 2052 // The target thinks this is legal afterall. 2053 break; 2054 } 2055 } 2056 case TargetLowering::Legal: 2057 break; 2058 } 2059 2060 if (Tmp1 != Node->getOperand(0)) 2061 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2062 break; 2063 case Expand: 2064 assert(0 && "Shouldn't need to expand other operators here!"); 2065 case Promote: 2066 Result = PromoteOp(Node->getOperand(0)); 2067 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2068 break; 2069 } 2070 break; 2071 2072 case ISD::ANY_EXTEND: 2073 case ISD::ZERO_EXTEND: 2074 case ISD::SIGN_EXTEND: 2075 case ISD::FP_EXTEND: 2076 case ISD::FP_ROUND: 2077 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2078 case Legal: 2079 Tmp1 = LegalizeOp(Node->getOperand(0)); 2080 if (Tmp1 != Node->getOperand(0)) 2081 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2082 break; 2083 case Expand: 2084 assert(0 && "Shouldn't need to expand other operators here!"); 2085 2086 case Promote: 2087 switch (Node->getOpcode()) { 2088 case ISD::ANY_EXTEND: 2089 Result = PromoteOp(Node->getOperand(0)); 2090 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2091 break; 2092 case ISD::ZERO_EXTEND: 2093 Result = PromoteOp(Node->getOperand(0)); 2094 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2095 Result = DAG.getZeroExtendInReg(Result, 2096 Node->getOperand(0).getValueType()); 2097 break; 2098 case ISD::SIGN_EXTEND: 2099 Result = PromoteOp(Node->getOperand(0)); 2100 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2101 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2102 Result, 2103 DAG.getValueType(Node->getOperand(0).getValueType())); 2104 break; 2105 case ISD::FP_EXTEND: 2106 Result = PromoteOp(Node->getOperand(0)); 2107 if (Result.getValueType() != Op.getValueType()) 2108 // Dynamically dead while we have only 2 FP types. 2109 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2110 break; 2111 case ISD::FP_ROUND: 2112 Result = PromoteOp(Node->getOperand(0)); 2113 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2114 break; 2115 } 2116 } 2117 break; 2118 case ISD::FP_ROUND_INREG: 2119 case ISD::SIGN_EXTEND_INREG: { 2120 Tmp1 = LegalizeOp(Node->getOperand(0)); 2121 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2122 2123 // If this operation is not supported, convert it to a shl/shr or load/store 2124 // pair. 2125 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2126 default: assert(0 && "This action not supported for this op yet!"); 2127 case TargetLowering::Legal: 2128 if (Tmp1 != Node->getOperand(0)) 2129 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2130 DAG.getValueType(ExtraVT)); 2131 break; 2132 case TargetLowering::Expand: 2133 // If this is an integer extend and shifts are supported, do that. 2134 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2135 // NOTE: we could fall back on load/store here too for targets without 2136 // SAR. However, it is doubtful that any exist. 2137 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2138 MVT::getSizeInBits(ExtraVT); 2139 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2140 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2141 Node->getOperand(0), ShiftCst); 2142 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2143 Result, ShiftCst); 2144 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2145 // The only way we can lower this is to turn it into a STORETRUNC, 2146 // EXTLOAD pair, targetting a temporary location (a stack slot). 2147 2148 // NOTE: there is a choice here between constantly creating new stack 2149 // slots and always reusing the same one. We currently always create 2150 // new ones, as reuse may inhibit scheduling. 2151 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2152 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2153 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2154 MachineFunction &MF = DAG.getMachineFunction(); 2155 int SSFI = 2156 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2157 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2158 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2159 Node->getOperand(0), StackSlot, 2160 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2161 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2162 Result, StackSlot, DAG.getSrcValue(NULL), 2163 ExtraVT); 2164 } else { 2165 assert(0 && "Unknown op"); 2166 } 2167 Result = LegalizeOp(Result); 2168 break; 2169 } 2170 break; 2171 } 2172 } 2173 2174 // Note that LegalizeOp may be reentered even from single-use nodes, which 2175 // means that we always must cache transformed nodes. 2176 AddLegalizedOperand(Op, Result); 2177 return Result; 2178} 2179 2180/// PromoteOp - Given an operation that produces a value in an invalid type, 2181/// promote it to compute the value into a larger type. The produced value will 2182/// have the correct bits for the low portion of the register, but no guarantee 2183/// is made about the top bits: it may be zero, sign-extended, or garbage. 2184SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2185 MVT::ValueType VT = Op.getValueType(); 2186 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2187 assert(getTypeAction(VT) == Promote && 2188 "Caller should expand or legalize operands that are not promotable!"); 2189 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2190 "Cannot promote to smaller type!"); 2191 2192 SDOperand Tmp1, Tmp2, Tmp3; 2193 2194 SDOperand Result; 2195 SDNode *Node = Op.Val; 2196 2197 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2198 if (I != PromotedNodes.end()) return I->second; 2199 2200 // Promotion needs an optimization step to clean up after it, and is not 2201 // careful to avoid operations the target does not support. Make sure that 2202 // all generated operations are legalized in the next iteration. 2203 NeedsAnotherIteration = true; 2204 2205 switch (Node->getOpcode()) { 2206 case ISD::CopyFromReg: 2207 assert(0 && "CopyFromReg must be legal!"); 2208 default: 2209 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2210 assert(0 && "Do not know how to promote this operator!"); 2211 abort(); 2212 case ISD::UNDEF: 2213 Result = DAG.getNode(ISD::UNDEF, NVT); 2214 break; 2215 case ISD::Constant: 2216 if (VT != MVT::i1) 2217 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2218 else 2219 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2220 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2221 break; 2222 case ISD::ConstantFP: 2223 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2224 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2225 break; 2226 2227 case ISD::SETCC: 2228 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2229 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2230 Node->getOperand(1), Node->getOperand(2)); 2231 Result = LegalizeOp(Result); 2232 break; 2233 2234 case ISD::TRUNCATE: 2235 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2236 case Legal: 2237 Result = LegalizeOp(Node->getOperand(0)); 2238 assert(Result.getValueType() >= NVT && 2239 "This truncation doesn't make sense!"); 2240 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2241 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2242 break; 2243 case Promote: 2244 // The truncation is not required, because we don't guarantee anything 2245 // about high bits anyway. 2246 Result = PromoteOp(Node->getOperand(0)); 2247 break; 2248 case Expand: 2249 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2250 // Truncate the low part of the expanded value to the result type 2251 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2252 } 2253 break; 2254 case ISD::SIGN_EXTEND: 2255 case ISD::ZERO_EXTEND: 2256 case ISD::ANY_EXTEND: 2257 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2258 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2259 case Legal: 2260 // Input is legal? Just do extend all the way to the larger type. 2261 Result = LegalizeOp(Node->getOperand(0)); 2262 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2263 break; 2264 case Promote: 2265 // Promote the reg if it's smaller. 2266 Result = PromoteOp(Node->getOperand(0)); 2267 // The high bits are not guaranteed to be anything. Insert an extend. 2268 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2269 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2270 DAG.getValueType(Node->getOperand(0).getValueType())); 2271 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2272 Result = DAG.getZeroExtendInReg(Result, 2273 Node->getOperand(0).getValueType()); 2274 break; 2275 } 2276 break; 2277 2278 case ISD::FP_EXTEND: 2279 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2280 case ISD::FP_ROUND: 2281 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2282 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2283 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2284 case Legal: 2285 // Input is legal? Do an FP_ROUND_INREG. 2286 Result = LegalizeOp(Node->getOperand(0)); 2287 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2288 DAG.getValueType(VT)); 2289 break; 2290 } 2291 break; 2292 2293 case ISD::SINT_TO_FP: 2294 case ISD::UINT_TO_FP: 2295 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2296 case Legal: 2297 Result = LegalizeOp(Node->getOperand(0)); 2298 // No extra round required here. 2299 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2300 break; 2301 2302 case Promote: 2303 Result = PromoteOp(Node->getOperand(0)); 2304 if (Node->getOpcode() == ISD::SINT_TO_FP) 2305 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2306 Result, 2307 DAG.getValueType(Node->getOperand(0).getValueType())); 2308 else 2309 Result = DAG.getZeroExtendInReg(Result, 2310 Node->getOperand(0).getValueType()); 2311 // No extra round required here. 2312 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2313 break; 2314 case Expand: 2315 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2316 Node->getOperand(0)); 2317 // Round if we cannot tolerate excess precision. 2318 if (NoExcessFPPrecision) 2319 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2320 DAG.getValueType(VT)); 2321 break; 2322 } 2323 break; 2324 2325 case ISD::FP_TO_SINT: 2326 case ISD::FP_TO_UINT: 2327 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2328 case Legal: 2329 Tmp1 = LegalizeOp(Node->getOperand(0)); 2330 break; 2331 case Promote: 2332 // The input result is prerounded, so we don't have to do anything 2333 // special. 2334 Tmp1 = PromoteOp(Node->getOperand(0)); 2335 break; 2336 case Expand: 2337 assert(0 && "not implemented"); 2338 } 2339 // If we're promoting a UINT to a larger size, check to see if the new node 2340 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2341 // we can use that instead. This allows us to generate better code for 2342 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2343 // legal, such as PowerPC. 2344 if (Node->getOpcode() == ISD::FP_TO_UINT && 2345 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2346 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2347 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2348 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2349 } else { 2350 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2351 } 2352 break; 2353 2354 case ISD::FABS: 2355 case ISD::FNEG: 2356 Tmp1 = PromoteOp(Node->getOperand(0)); 2357 assert(Tmp1.getValueType() == NVT); 2358 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2359 // NOTE: we do not have to do any extra rounding here for 2360 // NoExcessFPPrecision, because we know the input will have the appropriate 2361 // precision, and these operations don't modify precision at all. 2362 break; 2363 2364 case ISD::FSQRT: 2365 case ISD::FSIN: 2366 case ISD::FCOS: 2367 Tmp1 = PromoteOp(Node->getOperand(0)); 2368 assert(Tmp1.getValueType() == NVT); 2369 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2370 if(NoExcessFPPrecision) 2371 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2372 DAG.getValueType(VT)); 2373 break; 2374 2375 case ISD::AND: 2376 case ISD::OR: 2377 case ISD::XOR: 2378 case ISD::ADD: 2379 case ISD::SUB: 2380 case ISD::MUL: 2381 // The input may have strange things in the top bits of the registers, but 2382 // these operations don't care. They may have weird bits going out, but 2383 // that too is okay if they are integer operations. 2384 Tmp1 = PromoteOp(Node->getOperand(0)); 2385 Tmp2 = PromoteOp(Node->getOperand(1)); 2386 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2387 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2388 break; 2389 case ISD::FADD: 2390 case ISD::FSUB: 2391 case ISD::FMUL: 2392 // The input may have strange things in the top bits of the registers, but 2393 // these operations don't care. 2394 Tmp1 = PromoteOp(Node->getOperand(0)); 2395 Tmp2 = PromoteOp(Node->getOperand(1)); 2396 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2397 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2398 2399 // Floating point operations will give excess precision that we may not be 2400 // able to tolerate. If we DO allow excess precision, just leave it, 2401 // otherwise excise it. 2402 // FIXME: Why would we need to round FP ops more than integer ones? 2403 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 2404 if (NoExcessFPPrecision) 2405 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2406 DAG.getValueType(VT)); 2407 break; 2408 2409 case ISD::SDIV: 2410 case ISD::SREM: 2411 // These operators require that their input be sign extended. 2412 Tmp1 = PromoteOp(Node->getOperand(0)); 2413 Tmp2 = PromoteOp(Node->getOperand(1)); 2414 if (MVT::isInteger(NVT)) { 2415 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2416 DAG.getValueType(VT)); 2417 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 2418 DAG.getValueType(VT)); 2419 } 2420 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2421 2422 // Perform FP_ROUND: this is probably overly pessimistic. 2423 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2424 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2425 DAG.getValueType(VT)); 2426 break; 2427 case ISD::FDIV: 2428 case ISD::FREM: 2429 // These operators require that their input be fp extended. 2430 Tmp1 = PromoteOp(Node->getOperand(0)); 2431 Tmp2 = PromoteOp(Node->getOperand(1)); 2432 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2433 2434 // Perform FP_ROUND: this is probably overly pessimistic. 2435 if (NoExcessFPPrecision) 2436 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2437 DAG.getValueType(VT)); 2438 break; 2439 2440 case ISD::UDIV: 2441 case ISD::UREM: 2442 // These operators require that their input be zero extended. 2443 Tmp1 = PromoteOp(Node->getOperand(0)); 2444 Tmp2 = PromoteOp(Node->getOperand(1)); 2445 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 2446 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2447 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 2448 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2449 break; 2450 2451 case ISD::SHL: 2452 Tmp1 = PromoteOp(Node->getOperand(0)); 2453 Tmp2 = LegalizeOp(Node->getOperand(1)); 2454 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 2455 break; 2456 case ISD::SRA: 2457 // The input value must be properly sign extended. 2458 Tmp1 = PromoteOp(Node->getOperand(0)); 2459 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2460 DAG.getValueType(VT)); 2461 Tmp2 = LegalizeOp(Node->getOperand(1)); 2462 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 2463 break; 2464 case ISD::SRL: 2465 // The input value must be properly zero extended. 2466 Tmp1 = PromoteOp(Node->getOperand(0)); 2467 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2468 Tmp2 = LegalizeOp(Node->getOperand(1)); 2469 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 2470 break; 2471 case ISD::LOAD: 2472 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2473 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2474 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2, 2475 Node->getOperand(2), VT); 2476 // Remember that we legalized the chain. 2477 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2478 break; 2479 case ISD::SEXTLOAD: 2480 case ISD::ZEXTLOAD: 2481 case ISD::EXTLOAD: 2482 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2483 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2484 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2, 2485 Node->getOperand(2), 2486 cast<VTSDNode>(Node->getOperand(3))->getVT()); 2487 // Remember that we legalized the chain. 2488 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2489 break; 2490 case ISD::SELECT: 2491 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2492 case Expand: assert(0 && "It's impossible to expand bools"); 2493 case Legal: 2494 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 2495 break; 2496 case Promote: 2497 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2498 break; 2499 } 2500 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 2501 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 2502 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 2503 break; 2504 case ISD::SELECT_CC: 2505 Tmp2 = PromoteOp(Node->getOperand(2)); // True 2506 Tmp3 = PromoteOp(Node->getOperand(3)); // False 2507 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 2508 Node->getOperand(1), Tmp2, Tmp3, 2509 Node->getOperand(4)); 2510 break; 2511 case ISD::TAILCALL: 2512 case ISD::CALL: { 2513 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2514 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 2515 2516 std::vector<SDOperand> Ops; 2517 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 2518 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2519 2520 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 2521 "Can only promote single result calls"); 2522 std::vector<MVT::ValueType> RetTyVTs; 2523 RetTyVTs.reserve(2); 2524 RetTyVTs.push_back(NVT); 2525 RetTyVTs.push_back(MVT::Other); 2526 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 2527 Node->getOpcode() == ISD::TAILCALL); 2528 Result = SDOperand(NC, 0); 2529 2530 // Insert the new chain mapping. 2531 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2532 break; 2533 } 2534 case ISD::CTPOP: 2535 case ISD::CTTZ: 2536 case ISD::CTLZ: 2537 Tmp1 = Node->getOperand(0); 2538 //Zero extend the argument 2539 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2540 // Perform the larger operation, then subtract if needed. 2541 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2542 switch(Node->getOpcode()) 2543 { 2544 case ISD::CTPOP: 2545 Result = Tmp1; 2546 break; 2547 case ISD::CTTZ: 2548 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2549 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2550 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 2551 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2552 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); 2553 break; 2554 case ISD::CTLZ: 2555 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2556 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2557 DAG.getConstant(getSizeInBits(NVT) - 2558 getSizeInBits(VT), NVT)); 2559 break; 2560 } 2561 break; 2562 } 2563 2564 assert(Result.Val && "Didn't set a result!"); 2565 AddPromotedOperand(Op, Result); 2566 return Result; 2567} 2568 2569/// ExpandAddSub - Find a clever way to expand this add operation into 2570/// subcomponents. 2571void SelectionDAGLegalize:: 2572ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 2573 SDOperand &Lo, SDOperand &Hi) { 2574 // Expand the subcomponents. 2575 SDOperand LHSL, LHSH, RHSL, RHSH; 2576 ExpandOp(LHS, LHSL, LHSH); 2577 ExpandOp(RHS, RHSL, RHSH); 2578 2579 std::vector<SDOperand> Ops; 2580 Ops.push_back(LHSL); 2581 Ops.push_back(LHSH); 2582 Ops.push_back(RHSL); 2583 Ops.push_back(RHSH); 2584 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2585 Lo = DAG.getNode(NodeOp, VTs, Ops); 2586 Hi = Lo.getValue(1); 2587} 2588 2589void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 2590 SDOperand Op, SDOperand Amt, 2591 SDOperand &Lo, SDOperand &Hi) { 2592 // Expand the subcomponents. 2593 SDOperand LHSL, LHSH; 2594 ExpandOp(Op, LHSL, LHSH); 2595 2596 std::vector<SDOperand> Ops; 2597 Ops.push_back(LHSL); 2598 Ops.push_back(LHSH); 2599 Ops.push_back(Amt); 2600 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2601 Lo = DAG.getNode(NodeOp, VTs, Ops); 2602 Hi = Lo.getValue(1); 2603} 2604 2605 2606/// ExpandShift - Try to find a clever way to expand this shift operation out to 2607/// smaller elements. If we can't find a way that is more efficient than a 2608/// libcall on this target, return false. Otherwise, return true with the 2609/// low-parts expanded into Lo and Hi. 2610bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 2611 SDOperand &Lo, SDOperand &Hi) { 2612 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 2613 "This is not a shift!"); 2614 2615 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 2616 SDOperand ShAmt = LegalizeOp(Amt); 2617 MVT::ValueType ShTy = ShAmt.getValueType(); 2618 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 2619 unsigned NVTBits = MVT::getSizeInBits(NVT); 2620 2621 // Handle the case when Amt is an immediate. Other cases are currently broken 2622 // and are disabled. 2623 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 2624 unsigned Cst = CN->getValue(); 2625 // Expand the incoming operand to be shifted, so that we have its parts 2626 SDOperand InL, InH; 2627 ExpandOp(Op, InL, InH); 2628 switch(Opc) { 2629 case ISD::SHL: 2630 if (Cst > VTBits) { 2631 Lo = DAG.getConstant(0, NVT); 2632 Hi = DAG.getConstant(0, NVT); 2633 } else if (Cst > NVTBits) { 2634 Lo = DAG.getConstant(0, NVT); 2635 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 2636 } else if (Cst == NVTBits) { 2637 Lo = DAG.getConstant(0, NVT); 2638 Hi = InL; 2639 } else { 2640 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 2641 Hi = DAG.getNode(ISD::OR, NVT, 2642 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 2643 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 2644 } 2645 return true; 2646 case ISD::SRL: 2647 if (Cst > VTBits) { 2648 Lo = DAG.getConstant(0, NVT); 2649 Hi = DAG.getConstant(0, NVT); 2650 } else if (Cst > NVTBits) { 2651 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 2652 Hi = DAG.getConstant(0, NVT); 2653 } else if (Cst == NVTBits) { 2654 Lo = InH; 2655 Hi = DAG.getConstant(0, NVT); 2656 } else { 2657 Lo = DAG.getNode(ISD::OR, NVT, 2658 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2659 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2660 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 2661 } 2662 return true; 2663 case ISD::SRA: 2664 if (Cst > VTBits) { 2665 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 2666 DAG.getConstant(NVTBits-1, ShTy)); 2667 } else if (Cst > NVTBits) { 2668 Lo = DAG.getNode(ISD::SRA, NVT, InH, 2669 DAG.getConstant(Cst-NVTBits, ShTy)); 2670 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2671 DAG.getConstant(NVTBits-1, ShTy)); 2672 } else if (Cst == NVTBits) { 2673 Lo = InH; 2674 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2675 DAG.getConstant(NVTBits-1, ShTy)); 2676 } else { 2677 Lo = DAG.getNode(ISD::OR, NVT, 2678 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2679 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2680 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 2681 } 2682 return true; 2683 } 2684 } 2685 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 2686 // so disable it for now. Currently targets are handling this via SHL_PARTS 2687 // and friends. 2688 return false; 2689 2690 // If we have an efficient select operation (or if the selects will all fold 2691 // away), lower to some complex code, otherwise just emit the libcall. 2692 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt)) 2693 return false; 2694 2695 SDOperand InL, InH; 2696 ExpandOp(Op, InL, InH); 2697 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 2698 DAG.getConstant(NVTBits, ShTy), ShAmt); 2699 2700 // Compare the unmasked shift amount against 32. 2701 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt, 2702 DAG.getConstant(NVTBits, ShTy), ISD::SETGE); 2703 2704 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 2705 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 2706 DAG.getConstant(NVTBits-1, ShTy)); 2707 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 2708 DAG.getConstant(NVTBits-1, ShTy)); 2709 } 2710 2711 if (Opc == ISD::SHL) { 2712 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 2713 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 2714 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 2715 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 2716 2717 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2718 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 2719 } else { 2720 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 2721 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt, 2722 DAG.getConstant(32, ShTy), 2723 ISD::SETEQ), 2724 DAG.getConstant(0, NVT), 2725 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 2726 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 2727 HiLoPart, 2728 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 2729 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 2730 2731 SDOperand HiPart; 2732 if (Opc == ISD::SRA) 2733 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 2734 DAG.getConstant(NVTBits-1, ShTy)); 2735 else 2736 HiPart = DAG.getConstant(0, NVT); 2737 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2738 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 2739 } 2740 return true; 2741} 2742 2743/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 2744/// NodeDepth) node that is an CallSeqStart operation and occurs later than 2745/// Found. 2746static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) { 2747 if (Node->getNodeDepth() <= Found->getNodeDepth()) return; 2748 2749 // If we found an CALLSEQ_START, we already know this node occurs later 2750 // than the Found node. Just remember this node and return. 2751 if (Node->getOpcode() == ISD::CALLSEQ_START) { 2752 Found = Node; 2753 return; 2754 } 2755 2756 // Otherwise, scan the operands of Node to see if any of them is a call. 2757 assert(Node->getNumOperands() != 0 && 2758 "All leaves should have depth equal to the entry node!"); 2759 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 2760 FindLatestCallSeqStart(Node->getOperand(i).Val, Found); 2761 2762 // Tail recurse for the last iteration. 2763 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 2764 Found); 2765} 2766 2767 2768/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 2769/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 2770/// than Found. 2771static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 2772 std::set<SDNode*> &Visited) { 2773 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 2774 !Visited.insert(Node).second) return; 2775 2776 // If we found an CALLSEQ_END, we already know this node occurs earlier 2777 // than the Found node. Just remember this node and return. 2778 if (Node->getOpcode() == ISD::CALLSEQ_END) { 2779 Found = Node; 2780 return; 2781 } 2782 2783 // Otherwise, scan the operands of Node to see if any of them is a call. 2784 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 2785 if (UI == E) return; 2786 for (--E; UI != E; ++UI) 2787 FindEarliestCallSeqEnd(*UI, Found, Visited); 2788 2789 // Tail recurse for the last iteration. 2790 FindEarliestCallSeqEnd(*UI, Found, Visited); 2791} 2792 2793/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 2794/// find the CALLSEQ_END node that terminates the call sequence. 2795static SDNode *FindCallSeqEnd(SDNode *Node) { 2796 if (Node->getOpcode() == ISD::CALLSEQ_END) 2797 return Node; 2798 if (Node->use_empty()) 2799 return 0; // No CallSeqEnd 2800 2801 SDOperand TheChain(Node, Node->getNumValues()-1); 2802 if (TheChain.getValueType() != MVT::Other) 2803 TheChain = SDOperand(Node, 0); 2804 if (TheChain.getValueType() != MVT::Other) 2805 return 0; 2806 2807 for (SDNode::use_iterator UI = Node->use_begin(), 2808 E = Node->use_end(); UI != E; ++UI) { 2809 2810 // Make sure to only follow users of our token chain. 2811 SDNode *User = *UI; 2812 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 2813 if (User->getOperand(i) == TheChain) 2814 if (SDNode *Result = FindCallSeqEnd(User)) 2815 return Result; 2816 } 2817 return 0; 2818} 2819 2820/// FindCallSeqStart - Given a chained node that is part of a call sequence, 2821/// find the CALLSEQ_START node that initiates the call sequence. 2822static SDNode *FindCallSeqStart(SDNode *Node) { 2823 assert(Node && "Didn't find callseq_start for a call??"); 2824 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 2825 2826 assert(Node->getOperand(0).getValueType() == MVT::Other && 2827 "Node doesn't have a token chain argument!"); 2828 return FindCallSeqStart(Node->getOperand(0).Val); 2829} 2830 2831 2832/// FindInputOutputChains - If we are replacing an operation with a call we need 2833/// to find the call that occurs before and the call that occurs after it to 2834/// properly serialize the calls in the block. The returned operand is the 2835/// input chain value for the new call (e.g. the entry node or the previous 2836/// call), and OutChain is set to be the chain node to update to point to the 2837/// end of the call chain. 2838static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 2839 SDOperand Entry) { 2840 SDNode *LatestCallSeqStart = Entry.Val; 2841 SDNode *LatestCallSeqEnd = 0; 2842 FindLatestCallSeqStart(OpNode, LatestCallSeqStart); 2843 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 2844 2845 // It is possible that no ISD::CALLSEQ_START was found because there is no 2846 // previous call in the function. LatestCallStackDown may in that case be 2847 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 2848 // unless LatestCallStackDown is an CALLSEQ_START. 2849 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) { 2850 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 2851 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n"; 2852 } else { 2853 LatestCallSeqEnd = Entry.Val; 2854 } 2855 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 2856 2857 // Finally, find the first call that this must come before, first we find the 2858 // CallSeqEnd that ends the call. 2859 OutChain = 0; 2860 std::set<SDNode*> Visited; 2861 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 2862 2863 // If we found one, translate from the adj up to the callseq_start. 2864 if (OutChain) 2865 OutChain = FindCallSeqStart(OutChain); 2866 2867 return SDOperand(LatestCallSeqEnd, 0); 2868} 2869 2870/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 2871void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 2872 SDNode *OutChain) { 2873 // Nothing to splice it into? 2874 if (OutChain == 0) return; 2875 2876 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 2877 //OutChain->dump(); 2878 2879 // Form a token factor node merging the old inval and the new inval. 2880 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 2881 OutChain->getOperand(0)); 2882 // Change the node to refer to the new token. 2883 OutChain->setAdjCallChain(InToken); 2884} 2885 2886 2887// ExpandLibCall - Expand a node into a call to a libcall. If the result value 2888// does not fit into a register, return the lo part and set the hi part to the 2889// by-reg argument. If it does fit into a single register, return the result 2890// and leave the Hi part unset. 2891SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 2892 SDOperand &Hi) { 2893 SDNode *OutChain; 2894 SDOperand InChain = FindInputOutputChains(Node, OutChain, 2895 DAG.getEntryNode()); 2896 if (InChain.Val == 0) 2897 InChain = DAG.getEntryNode(); 2898 2899 TargetLowering::ArgListTy Args; 2900 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2901 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 2902 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 2903 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 2904 } 2905 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 2906 2907 // Splice the libcall in wherever FindInputOutputChains tells us to. 2908 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 2909 std::pair<SDOperand,SDOperand> CallInfo = 2910 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 2911 Callee, Args, DAG); 2912 2913 SDOperand Result; 2914 switch (getTypeAction(CallInfo.first.getValueType())) { 2915 default: assert(0 && "Unknown thing"); 2916 case Legal: 2917 Result = CallInfo.first; 2918 break; 2919 case Promote: 2920 assert(0 && "Cannot promote this yet!"); 2921 case Expand: 2922 ExpandOp(CallInfo.first, Result, Hi); 2923 CallInfo.second = LegalizeOp(CallInfo.second); 2924 break; 2925 } 2926 2927 SpliceCallInto(CallInfo.second, OutChain); 2928 NeedsAnotherIteration = true; 2929 return Result; 2930} 2931 2932 2933/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 2934/// destination type is legal. 2935SDOperand SelectionDAGLegalize:: 2936ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 2937 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 2938 assert(getTypeAction(Source.getValueType()) == Expand && 2939 "This is not an expansion!"); 2940 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 2941 2942 if (!isSigned) { 2943 assert(Source.getValueType() == MVT::i64 && 2944 "This only works for 64-bit -> FP"); 2945 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 2946 // incoming integer is set. To handle this, we dynamically test to see if 2947 // it is set, and, if so, add a fudge factor. 2948 SDOperand Lo, Hi; 2949 ExpandOp(Source, Lo, Hi); 2950 2951 // If this is unsigned, and not supported, first perform the conversion to 2952 // signed, then adjust the result if the sign bit is set. 2953 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 2954 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 2955 2956 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 2957 DAG.getConstant(0, Hi.getValueType()), 2958 ISD::SETLT); 2959 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 2960 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 2961 SignSet, Four, Zero); 2962 uint64_t FF = 0x5f800000ULL; 2963 if (TLI.isLittleEndian()) FF <<= 32; 2964 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 2965 2966 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2967 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 2968 SDOperand FudgeInReg; 2969 if (DestTy == MVT::f32) 2970 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 2971 DAG.getSrcValue(NULL)); 2972 else { 2973 assert(DestTy == MVT::f64 && "Unexpected conversion"); 2974 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 2975 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 2976 } 2977 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 2978 } 2979 2980 // Check to see if the target has a custom way to lower this. If so, use it. 2981 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 2982 default: assert(0 && "This action not implemented for this operation!"); 2983 case TargetLowering::Legal: 2984 case TargetLowering::Expand: 2985 break; // This case is handled below. 2986 case TargetLowering::Custom: { 2987 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 2988 Source), DAG); 2989 if (NV.Val) 2990 return LegalizeOp(NV); 2991 break; // The target decided this was legal after all 2992 } 2993 } 2994 2995 // Expand the source, then glue it back together for the call. We must expand 2996 // the source in case it is shared (this pass of legalize must traverse it). 2997 SDOperand SrcLo, SrcHi; 2998 ExpandOp(Source, SrcLo, SrcHi); 2999 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3000 3001 SDNode *OutChain = 0; 3002 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 3003 DAG.getEntryNode()); 3004 const char *FnName = 0; 3005 if (DestTy == MVT::f32) 3006 FnName = "__floatdisf"; 3007 else { 3008 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3009 FnName = "__floatdidf"; 3010 } 3011 3012 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 3013 3014 TargetLowering::ArgListTy Args; 3015 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 3016 3017 Args.push_back(std::make_pair(Source, ArgTy)); 3018 3019 // We don't care about token chains for libcalls. We just use the entry 3020 // node as our input and ignore the output chain. This allows us to place 3021 // calls wherever we need them to satisfy data dependences. 3022 const Type *RetTy = MVT::getTypeForValueType(DestTy); 3023 3024 std::pair<SDOperand,SDOperand> CallResult = 3025 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 3026 Callee, Args, DAG); 3027 3028 SpliceCallInto(CallResult.second, OutChain); 3029 return CallResult.first; 3030} 3031 3032 3033 3034/// ExpandOp - Expand the specified SDOperand into its two component pieces 3035/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 3036/// LegalizeNodes map is filled in for any results that are not expanded, the 3037/// ExpandedNodes map is filled in for any results that are expanded, and the 3038/// Lo/Hi values are returned. 3039void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 3040 MVT::ValueType VT = Op.getValueType(); 3041 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3042 SDNode *Node = Op.Val; 3043 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 3044 assert(MVT::isInteger(VT) && "Cannot expand FP values!"); 3045 assert(MVT::isInteger(NVT) && NVT < VT && 3046 "Cannot expand to FP value or to larger int value!"); 3047 3048 // See if we already expanded it. 3049 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 3050 = ExpandedNodes.find(Op); 3051 if (I != ExpandedNodes.end()) { 3052 Lo = I->second.first; 3053 Hi = I->second.second; 3054 return; 3055 } 3056 3057 // Expanding to multiple registers needs to perform an optimization step, and 3058 // is not careful to avoid operations the target does not support. Make sure 3059 // that all generated operations are legalized in the next iteration. 3060 NeedsAnotherIteration = true; 3061 3062 switch (Node->getOpcode()) { 3063 case ISD::CopyFromReg: 3064 assert(0 && "CopyFromReg must be legal!"); 3065 default: 3066 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 3067 assert(0 && "Do not know how to expand this operator!"); 3068 abort(); 3069 case ISD::UNDEF: 3070 Lo = DAG.getNode(ISD::UNDEF, NVT); 3071 Hi = DAG.getNode(ISD::UNDEF, NVT); 3072 break; 3073 case ISD::Constant: { 3074 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 3075 Lo = DAG.getConstant(Cst, NVT); 3076 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 3077 break; 3078 } 3079 3080 case ISD::BUILD_PAIR: 3081 // Legalize both operands. FIXME: in the future we should handle the case 3082 // where the two elements are not legal. 3083 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 3084 Lo = LegalizeOp(Node->getOperand(0)); 3085 Hi = LegalizeOp(Node->getOperand(1)); 3086 break; 3087 3088 case ISD::CTPOP: 3089 ExpandOp(Node->getOperand(0), Lo, Hi); 3090 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 3091 DAG.getNode(ISD::CTPOP, NVT, Lo), 3092 DAG.getNode(ISD::CTPOP, NVT, Hi)); 3093 Hi = DAG.getConstant(0, NVT); 3094 break; 3095 3096 case ISD::CTLZ: { 3097 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 3098 ExpandOp(Node->getOperand(0), Lo, Hi); 3099 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3100 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 3101 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 3102 ISD::SETNE); 3103 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 3104 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 3105 3106 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 3107 Hi = DAG.getConstant(0, NVT); 3108 break; 3109 } 3110 3111 case ISD::CTTZ: { 3112 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 3113 ExpandOp(Node->getOperand(0), Lo, Hi); 3114 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3115 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 3116 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 3117 ISD::SETNE); 3118 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 3119 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 3120 3121 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 3122 Hi = DAG.getConstant(0, NVT); 3123 break; 3124 } 3125 3126 case ISD::LOAD: { 3127 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3128 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3129 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3130 3131 // Increment the pointer to the other half. 3132 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 3133 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3134 getIntPtrConstant(IncrementSize)); 3135 //Is this safe? declaring that the two parts of the split load 3136 //are from the same instruction? 3137 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3138 3139 // Build a factor node to remember that this load is independent of the 3140 // other one. 3141 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3142 Hi.getValue(1)); 3143 3144 // Remember that we legalized the chain. 3145 AddLegalizedOperand(Op.getValue(1), TF); 3146 if (!TLI.isLittleEndian()) 3147 std::swap(Lo, Hi); 3148 break; 3149 } 3150 case ISD::TAILCALL: 3151 case ISD::CALL: { 3152 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3153 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 3154 3155 bool Changed = false; 3156 std::vector<SDOperand> Ops; 3157 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 3158 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3159 Changed |= Ops.back() != Node->getOperand(i); 3160 } 3161 3162 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 3163 "Can only expand a call once so far, not i64 -> i16!"); 3164 3165 std::vector<MVT::ValueType> RetTyVTs; 3166 RetTyVTs.reserve(3); 3167 RetTyVTs.push_back(NVT); 3168 RetTyVTs.push_back(NVT); 3169 RetTyVTs.push_back(MVT::Other); 3170 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops, 3171 Node->getOpcode() == ISD::TAILCALL); 3172 Lo = SDOperand(NC, 0); 3173 Hi = SDOperand(NC, 1); 3174 3175 // Insert the new chain mapping. 3176 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 3177 break; 3178 } 3179 case ISD::AND: 3180 case ISD::OR: 3181 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 3182 SDOperand LL, LH, RL, RH; 3183 ExpandOp(Node->getOperand(0), LL, LH); 3184 ExpandOp(Node->getOperand(1), RL, RH); 3185 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 3186 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 3187 break; 3188 } 3189 case ISD::SELECT: { 3190 SDOperand C, LL, LH, RL, RH; 3191 3192 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3193 case Expand: assert(0 && "It's impossible to expand bools"); 3194 case Legal: 3195 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 3196 break; 3197 case Promote: 3198 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 3199 break; 3200 } 3201 ExpandOp(Node->getOperand(1), LL, LH); 3202 ExpandOp(Node->getOperand(2), RL, RH); 3203 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 3204 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 3205 break; 3206 } 3207 case ISD::SELECT_CC: { 3208 SDOperand TL, TH, FL, FH; 3209 ExpandOp(Node->getOperand(2), TL, TH); 3210 ExpandOp(Node->getOperand(3), FL, FH); 3211 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3212 Node->getOperand(1), TL, FL, Node->getOperand(4)); 3213 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3214 Node->getOperand(1), TH, FH, Node->getOperand(4)); 3215 Lo = LegalizeOp(Lo); 3216 Hi = LegalizeOp(Hi); 3217 break; 3218 } 3219 case ISD::SEXTLOAD: { 3220 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3221 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3222 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3223 3224 if (EVT == NVT) 3225 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3226 else 3227 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3228 EVT); 3229 3230 // Remember that we legalized the chain. 3231 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3232 3233 // The high part is obtained by SRA'ing all but one of the bits of the lo 3234 // part. 3235 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3236 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3237 TLI.getShiftAmountTy())); 3238 Lo = LegalizeOp(Lo); 3239 Hi = LegalizeOp(Hi); 3240 break; 3241 } 3242 case ISD::ZEXTLOAD: { 3243 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3244 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3245 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3246 3247 if (EVT == NVT) 3248 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3249 else 3250 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3251 EVT); 3252 3253 // Remember that we legalized the chain. 3254 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3255 3256 // The high part is just a zero. 3257 Hi = LegalizeOp(DAG.getConstant(0, NVT)); 3258 Lo = LegalizeOp(Lo); 3259 break; 3260 } 3261 case ISD::EXTLOAD: { 3262 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3263 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3264 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3265 3266 if (EVT == NVT) 3267 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3268 else 3269 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3270 EVT); 3271 3272 // Remember that we legalized the chain. 3273 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3274 3275 // The high part is undefined. 3276 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT)); 3277 Lo = LegalizeOp(Lo); 3278 break; 3279 } 3280 case ISD::ANY_EXTEND: { 3281 SDOperand In; 3282 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3283 case Expand: assert(0 && "expand-expand not implemented yet!"); 3284 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3285 case Promote: 3286 In = PromoteOp(Node->getOperand(0)); 3287 break; 3288 } 3289 3290 // The low part is any extension of the input (which degenerates to a copy). 3291 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In); 3292 // The high part is undefined. 3293 Hi = DAG.getNode(ISD::UNDEF, NVT); 3294 break; 3295 } 3296 case ISD::SIGN_EXTEND: { 3297 SDOperand In; 3298 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3299 case Expand: assert(0 && "expand-expand not implemented yet!"); 3300 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3301 case Promote: 3302 In = PromoteOp(Node->getOperand(0)); 3303 // Emit the appropriate sign_extend_inreg to get the value we want. 3304 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 3305 DAG.getValueType(Node->getOperand(0).getValueType())); 3306 break; 3307 } 3308 3309 // The low part is just a sign extension of the input (which degenerates to 3310 // a copy). 3311 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 3312 3313 // The high part is obtained by SRA'ing all but one of the bits of the lo 3314 // part. 3315 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3316 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3317 TLI.getShiftAmountTy())); 3318 break; 3319 } 3320 case ISD::ZERO_EXTEND: { 3321 SDOperand In; 3322 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3323 case Expand: assert(0 && "expand-expand not implemented yet!"); 3324 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3325 case Promote: 3326 In = PromoteOp(Node->getOperand(0)); 3327 // Emit the appropriate zero_extend_inreg to get the value we want. 3328 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType()); 3329 break; 3330 } 3331 3332 // The low part is just a zero extension of the input (which degenerates to 3333 // a copy). 3334 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 3335 3336 // The high part is just a zero. 3337 Hi = DAG.getConstant(0, NVT); 3338 break; 3339 } 3340 // These operators cannot be expanded directly, emit them as calls to 3341 // library functions. 3342 case ISD::FP_TO_SINT: 3343 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 3344 SDOperand Op; 3345 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3346 case Expand: assert(0 && "cannot expand FP!"); 3347 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3348 case Promote: Op = PromoteOp(Node->getOperand(0)); break; 3349 } 3350 3351 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 3352 3353 // Now that the custom expander is done, expand the result, which is still 3354 // VT. 3355 if (Op.Val) { 3356 ExpandOp(Op, Lo, Hi); 3357 break; 3358 } 3359 } 3360 3361 if (Node->getOperand(0).getValueType() == MVT::f32) 3362 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 3363 else 3364 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 3365 break; 3366 3367 case ISD::FP_TO_UINT: 3368 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 3369 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, 3370 LegalizeOp(Node->getOperand(0))); 3371 // Now that the custom expander is done, expand the result, which is still 3372 // VT. 3373 Op = TLI.LowerOperation(Op, DAG); 3374 if (Op.Val) { 3375 ExpandOp(Op, Lo, Hi); 3376 break; 3377 } 3378 } 3379 3380 if (Node->getOperand(0).getValueType() == MVT::f32) 3381 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 3382 else 3383 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 3384 break; 3385 3386 case ISD::SHL: 3387 // If the target wants custom lowering, do so. 3388 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 3389 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), 3390 LegalizeOp(Node->getOperand(1))); 3391 Op = TLI.LowerOperation(Op, DAG); 3392 if (Op.Val) { 3393 // Now that the custom expander is done, expand the result, which is 3394 // still VT. 3395 ExpandOp(Op, Lo, Hi); 3396 break; 3397 } 3398 } 3399 3400 // If we can emit an efficient shift operation, do so now. 3401 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3402 break; 3403 3404 // If this target supports SHL_PARTS, use it. 3405 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) { 3406 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 3407 Lo, Hi); 3408 break; 3409 } 3410 3411 // Otherwise, emit a libcall. 3412 Lo = ExpandLibCall("__ashldi3", Node, Hi); 3413 break; 3414 3415 case ISD::SRA: 3416 // If the target wants custom lowering, do so. 3417 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 3418 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), 3419 LegalizeOp(Node->getOperand(1))); 3420 Op = TLI.LowerOperation(Op, DAG); 3421 if (Op.Val) { 3422 // Now that the custom expander is done, expand the result, which is 3423 // still VT. 3424 ExpandOp(Op, Lo, Hi); 3425 break; 3426 } 3427 } 3428 3429 // If we can emit an efficient shift operation, do so now. 3430 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3431 break; 3432 3433 // If this target supports SRA_PARTS, use it. 3434 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) { 3435 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 3436 Lo, Hi); 3437 break; 3438 } 3439 3440 // Otherwise, emit a libcall. 3441 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 3442 break; 3443 case ISD::SRL: 3444 // If the target wants custom lowering, do so. 3445 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 3446 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), 3447 LegalizeOp(Node->getOperand(1))); 3448 Op = TLI.LowerOperation(Op, DAG); 3449 if (Op.Val) { 3450 // Now that the custom expander is done, expand the result, which is 3451 // still VT. 3452 ExpandOp(Op, Lo, Hi); 3453 break; 3454 } 3455 } 3456 3457 // If we can emit an efficient shift operation, do so now. 3458 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3459 break; 3460 3461 // If this target supports SRL_PARTS, use it. 3462 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) { 3463 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 3464 Lo, Hi); 3465 break; 3466 } 3467 3468 // Otherwise, emit a libcall. 3469 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 3470 break; 3471 3472 case ISD::ADD: 3473 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 3474 Lo, Hi); 3475 break; 3476 case ISD::SUB: 3477 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 3478 Lo, Hi); 3479 break; 3480 case ISD::MUL: { 3481 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 3482 SDOperand LL, LH, RL, RH; 3483 ExpandOp(Node->getOperand(0), LL, LH); 3484 ExpandOp(Node->getOperand(1), RL, RH); 3485 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 3486 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 3487 // extended the sign bit of the low half through the upper half, and if so 3488 // emit a MULHS instead of the alternate sequence that is valid for any 3489 // i64 x i64 multiply. 3490 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 3491 // is RH an extension of the sign bit of RL? 3492 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 3493 RH.getOperand(1).getOpcode() == ISD::Constant && 3494 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 3495 // is LH an extension of the sign bit of LL? 3496 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 3497 LH.getOperand(1).getOpcode() == ISD::Constant && 3498 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 3499 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 3500 } else { 3501 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 3502 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 3503 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 3504 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 3505 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 3506 } 3507 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 3508 } else { 3509 Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 3510 } 3511 break; 3512 } 3513 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 3514 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 3515 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 3516 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 3517 } 3518 3519 // Remember in a map if the values will be reused later. 3520 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 3521 std::make_pair(Lo, Hi))).second; 3522 assert(isNew && "Value already expanded?!?"); 3523} 3524 3525 3526// SelectionDAG::Legalize - This is the entry point for the file. 3527// 3528void SelectionDAG::Legalize() { 3529 /// run - This is the main entry point to this class. 3530 /// 3531 SelectionDAGLegalize(*this).Run(); 3532} 3533 3534