LegalizeDAG.cpp revision 6862dbc446f2f633f6f4905d07a3bafd96741da2
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 enum LegalizeAction { 45 Legal, // The target natively supports this operation. 46 Promote, // This operation should be executed in a larger type. 47 Expand, // Try to expand this to other ops, otherwise use a libcall. 48 }; 49 50 /// ValueTypeActions - This is a bitvector that contains two bits for each 51 /// value type, where the two bits correspond to the LegalizeAction enum. 52 /// This can be queried with "getTypeAction(VT)". 53 TargetLowering::ValueTypeActionImpl ValueTypeActions; 54 55 /// LegalizedNodes - For nodes that are of legal width, and that have more 56 /// than one use, this map indicates what regularized operand to use. This 57 /// allows us to avoid legalizing the same thing more than once. 58 std::map<SDOperand, SDOperand> LegalizedNodes; 59 60 /// PromotedNodes - For nodes that are below legal width, and that have more 61 /// than one use, this map indicates what promoted value to use. This allows 62 /// us to avoid promoting the same thing more than once. 63 std::map<SDOperand, SDOperand> PromotedNodes; 64 65 /// ExpandedNodes - For nodes that need to be expanded, and which have more 66 /// than one use, this map indicates which which operands are the expanded 67 /// version of the input. This allows us to avoid expanding the same node 68 /// more than once. 69 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 70 71 void AddLegalizedOperand(SDOperand From, SDOperand To) { 72 LegalizedNodes.insert(std::make_pair(From, To)); 73 // If someone requests legalization of the new node, return itself. 74 if (From != To) 75 LegalizedNodes.insert(std::make_pair(To, To)); 76 } 77 void AddPromotedOperand(SDOperand From, SDOperand To) { 78 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 79 assert(isNew && "Got into the map somehow?"); 80 // If someone requests legalization of the new node, return itself. 81 LegalizedNodes.insert(std::make_pair(To, To)); 82 } 83 84public: 85 86 SelectionDAGLegalize(SelectionDAG &DAG); 87 88 /// getTypeAction - Return how we should legalize values of this type, either 89 /// it is already legal or we need to expand it into multiple registers of 90 /// smaller integer type, or we need to promote it to a larger type. 91 LegalizeAction getTypeAction(MVT::ValueType VT) const { 92 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 93 } 94 95 /// isTypeLegal - Return true if this type is legal on this target. 96 /// 97 bool isTypeLegal(MVT::ValueType VT) const { 98 return getTypeAction(VT) == Legal; 99 } 100 101 void LegalizeDAG(); 102 103private: 104 105 SDOperand LegalizeOp(SDOperand O); 106 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 107 SDOperand PromoteOp(SDOperand O); 108 109 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 110 SDOperand &Hi); 111 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 112 SDOperand Source); 113 114 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 115 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 116 SDOperand LegalOp, 117 MVT::ValueType DestVT); 118 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 119 bool isSigned); 120 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 121 bool isSigned); 122 123 SDOperand ExpandBSWAP(SDOperand Op); 124 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 125 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 126 SDOperand &Lo, SDOperand &Hi); 127 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 128 SDOperand &Lo, SDOperand &Hi); 129 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 130 131 SDOperand getIntPtrConstant(uint64_t Val) { 132 return DAG.getConstant(Val, TLI.getPointerTy()); 133 } 134}; 135} 136 137static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 138 switch (VecOp) { 139 default: assert(0 && "Don't know how to scalarize this opcode!"); 140 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 141 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 142 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 143 } 144} 145 146SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 147 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 148 ValueTypeActions(TLI.getValueTypeActions()) { 149 assert(MVT::LAST_VALUETYPE <= 32 && 150 "Too many value types for ValueTypeActions to hold!"); 151} 152 153/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 154/// not been visited yet and if all of its operands have already been visited. 155static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 156 std::map<SDNode*, unsigned> &Visited) { 157 if (++Visited[N] != N->getNumOperands()) 158 return; // Haven't visited all operands yet 159 160 Order.push_back(N); 161 162 if (N->hasOneUse()) { // Tail recurse in common case. 163 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 164 return; 165 } 166 167 // Now that we have N in, add anything that uses it if all of their operands 168 // are now done. 169 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 170 ComputeTopDownOrdering(*UI, Order, Visited); 171} 172 173 174void SelectionDAGLegalize::LegalizeDAG() { 175 // The legalize process is inherently a bottom-up recursive process (users 176 // legalize their uses before themselves). Given infinite stack space, we 177 // could just start legalizing on the root and traverse the whole graph. In 178 // practice however, this causes us to run out of stack space on large basic 179 // blocks. To avoid this problem, compute an ordering of the nodes where each 180 // node is only legalized after all of its operands are legalized. 181 std::map<SDNode*, unsigned> Visited; 182 std::vector<SDNode*> Order; 183 184 // Compute ordering from all of the leaves in the graphs, those (like the 185 // entry node) that have no operands. 186 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 187 E = DAG.allnodes_end(); I != E; ++I) { 188 if (I->getNumOperands() == 0) { 189 Visited[I] = 0 - 1U; 190 ComputeTopDownOrdering(I, Order, Visited); 191 } 192 } 193 194 assert(Order.size() == Visited.size() && 195 Order.size() == 196 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 197 "Error: DAG is cyclic!"); 198 Visited.clear(); 199 200 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 201 SDNode *N = Order[i]; 202 switch (getTypeAction(N->getValueType(0))) { 203 default: assert(0 && "Bad type action!"); 204 case Legal: 205 LegalizeOp(SDOperand(N, 0)); 206 break; 207 case Promote: 208 PromoteOp(SDOperand(N, 0)); 209 break; 210 case Expand: { 211 SDOperand X, Y; 212 ExpandOp(SDOperand(N, 0), X, Y); 213 break; 214 } 215 } 216 } 217 218 // Finally, it's possible the root changed. Get the new root. 219 SDOperand OldRoot = DAG.getRoot(); 220 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 221 DAG.setRoot(LegalizedNodes[OldRoot]); 222 223 ExpandedNodes.clear(); 224 LegalizedNodes.clear(); 225 PromotedNodes.clear(); 226 227 // Remove dead nodes now. 228 DAG.RemoveDeadNodes(OldRoot.Val); 229} 230 231SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 232 assert(isTypeLegal(Op.getValueType()) && 233 "Caller should expand or promote operands that are not legal!"); 234 SDNode *Node = Op.Val; 235 236 // If this operation defines any values that cannot be represented in a 237 // register on this target, make sure to expand or promote them. 238 if (Node->getNumValues() > 1) { 239 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 240 switch (getTypeAction(Node->getValueType(i))) { 241 case Legal: break; // Nothing to do. 242 case Expand: { 243 SDOperand T1, T2; 244 ExpandOp(Op.getValue(i), T1, T2); 245 assert(LegalizedNodes.count(Op) && 246 "Expansion didn't add legal operands!"); 247 return LegalizedNodes[Op]; 248 } 249 case Promote: 250 PromoteOp(Op.getValue(i)); 251 assert(LegalizedNodes.count(Op) && 252 "Promotion didn't add legal operands!"); 253 return LegalizedNodes[Op]; 254 } 255 } 256 257 // Note that LegalizeOp may be reentered even from single-use nodes, which 258 // means that we always must cache transformed nodes. 259 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 260 if (I != LegalizedNodes.end()) return I->second; 261 262 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 263 SDOperand Result = Op; 264 bool isCustom = false; 265 266 switch (Node->getOpcode()) { 267 case ISD::FrameIndex: 268 case ISD::EntryToken: 269 case ISD::Register: 270 case ISD::BasicBlock: 271 case ISD::TargetFrameIndex: 272 case ISD::TargetConstant: 273 case ISD::TargetConstantFP: 274 case ISD::TargetConstantVec: 275 case ISD::TargetConstantPool: 276 case ISD::TargetGlobalAddress: 277 case ISD::TargetExternalSymbol: 278 case ISD::VALUETYPE: 279 case ISD::SRCVALUE: 280 case ISD::STRING: 281 case ISD::CONDCODE: 282 // Primitives must all be legal. 283 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 284 "This must be legal!"); 285 break; 286 default: 287 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 288 // If this is a target node, legalize it by legalizing the operands then 289 // passing it through. 290 std::vector<SDOperand> Ops; 291 bool Changed = false; 292 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 293 Ops.push_back(LegalizeOp(Node->getOperand(i))); 294 Changed = Changed || Node->getOperand(i) != Ops.back(); 295 } 296 if (Changed) 297 if (Node->getNumValues() == 1) 298 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 299 else { 300 std::vector<MVT::ValueType> VTs(Node->value_begin(), 301 Node->value_end()); 302 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 303 } 304 305 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 306 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 307 return Result.getValue(Op.ResNo); 308 } 309 // Otherwise this is an unhandled builtin node. splat. 310 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 311 assert(0 && "Do not know how to legalize this operator!"); 312 abort(); 313 case ISD::GlobalAddress: 314 case ISD::ExternalSymbol: 315 case ISD::ConstantPool: // Nothing to do. 316 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 317 default: assert(0 && "This action is not supported yet!"); 318 case TargetLowering::Custom: 319 Tmp1 = TLI.LowerOperation(Op, DAG); 320 if (Tmp1.Val) Result = Tmp1; 321 // FALLTHROUGH if the target doesn't want to lower this op after all. 322 case TargetLowering::Legal: 323 break; 324 } 325 break; 326 case ISD::AssertSext: 327 case ISD::AssertZext: 328 Tmp1 = LegalizeOp(Node->getOperand(0)); 329 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 330 break; 331 case ISD::MERGE_VALUES: 332 // Legalize eliminates MERGE_VALUES nodes. 333 Result = Node->getOperand(Op.ResNo); 334 break; 335 case ISD::CopyFromReg: 336 Tmp1 = LegalizeOp(Node->getOperand(0)); 337 Result = Op.getValue(0); 338 if (Node->getNumValues() == 2) { 339 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 340 } else { 341 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 342 if (Node->getNumOperands() == 3) { 343 Tmp2 = LegalizeOp(Node->getOperand(2)); 344 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 345 } else { 346 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 347 } 348 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 349 } 350 // Since CopyFromReg produces two values, make sure to remember that we 351 // legalized both of them. 352 AddLegalizedOperand(Op.getValue(0), Result); 353 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 354 return Result.getValue(Op.ResNo); 355 case ISD::UNDEF: { 356 MVT::ValueType VT = Op.getValueType(); 357 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 358 default: assert(0 && "This action is not supported yet!"); 359 case TargetLowering::Expand: 360 if (MVT::isInteger(VT)) 361 Result = DAG.getConstant(0, VT); 362 else if (MVT::isFloatingPoint(VT)) 363 Result = DAG.getConstantFP(0, VT); 364 else 365 assert(0 && "Unknown value type!"); 366 break; 367 case TargetLowering::Legal: 368 break; 369 } 370 break; 371 } 372 373 case ISD::LOCATION: 374 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 375 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 376 377 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 378 case TargetLowering::Promote: 379 default: assert(0 && "This action is not supported yet!"); 380 case TargetLowering::Expand: { 381 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 382 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 383 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other); 384 385 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) { 386 const std::string &FName = 387 cast<StringSDNode>(Node->getOperand(3))->getValue(); 388 const std::string &DirName = 389 cast<StringSDNode>(Node->getOperand(4))->getValue(); 390 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName); 391 392 std::vector<SDOperand> Ops; 393 Ops.push_back(Tmp1); // chain 394 SDOperand LineOp = Node->getOperand(1); 395 SDOperand ColOp = Node->getOperand(2); 396 397 if (useDEBUG_LOC) { 398 Ops.push_back(LineOp); // line # 399 Ops.push_back(ColOp); // col # 400 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 401 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops); 402 } else { 403 unsigned Line = dyn_cast<ConstantSDNode>(LineOp)->getValue(); 404 unsigned Col = dyn_cast<ConstantSDNode>(ColOp)->getValue(); 405 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile); 406 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 407 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops); 408 } 409 } else { 410 Result = Tmp1; // chain 411 } 412 break; 413 } 414 case TargetLowering::Legal: 415 if (Tmp1 != Node->getOperand(0) || 416 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 417 std::vector<SDOperand> Ops; 418 Ops.push_back(Tmp1); 419 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 420 Ops.push_back(Node->getOperand(1)); // line # must be legal. 421 Ops.push_back(Node->getOperand(2)); // col # must be legal. 422 } else { 423 // Otherwise promote them. 424 Ops.push_back(PromoteOp(Node->getOperand(1))); 425 Ops.push_back(PromoteOp(Node->getOperand(2))); 426 } 427 Ops.push_back(Node->getOperand(3)); // filename must be legal. 428 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 429 Result = DAG.UpdateNodeOperands(Result, Ops); 430 } 431 break; 432 } 433 break; 434 435 case ISD::DEBUG_LOC: 436 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 437 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 438 default: assert(0 && "This action is not supported yet!"); 439 case TargetLowering::Legal: 440 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 441 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 442 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 443 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 444 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 445 break; 446 } 447 break; 448 449 case ISD::DEBUG_LABEL: 450 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!"); 451 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) { 452 default: assert(0 && "This action is not supported yet!"); 453 case TargetLowering::Legal: 454 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 455 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 456 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 457 break; 458 } 459 break; 460 461 case ISD::Constant: 462 // We know we don't need to expand constants here, constants only have one 463 // value and we check that it is fine above. 464 465 // FIXME: Maybe we should handle things like targets that don't support full 466 // 32-bit immediates? 467 break; 468 case ISD::ConstantFP: { 469 // Spill FP immediates to the constant pool if the target cannot directly 470 // codegen them. Targets often have some immediate values that can be 471 // efficiently generated into an FP register without a load. We explicitly 472 // leave these constants as ConstantFP nodes for the target to deal with. 473 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 474 475 // Check to see if this FP immediate is already legal. 476 bool isLegal = false; 477 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 478 E = TLI.legal_fpimm_end(); I != E; ++I) 479 if (CFP->isExactlyValue(*I)) { 480 isLegal = true; 481 break; 482 } 483 484 // If this is a legal constant, turn it into a TargetConstantFP node. 485 if (isLegal) { 486 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0)); 487 break; 488 } 489 490 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 491 default: assert(0 && "This action is not supported yet!"); 492 case TargetLowering::Custom: 493 Tmp3 = TLI.LowerOperation(Result, DAG); 494 if (Tmp3.Val) { 495 Result = Tmp3; 496 break; 497 } 498 // FALLTHROUGH 499 case TargetLowering::Expand: 500 // Otherwise we need to spill the constant to memory. 501 bool Extend = false; 502 503 // If a FP immediate is precise when represented as a float and if the 504 // target can do an extending load from float to double, we put it into 505 // the constant pool as a float, even if it's is statically typed as a 506 // double. 507 MVT::ValueType VT = CFP->getValueType(0); 508 bool isDouble = VT == MVT::f64; 509 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 510 Type::FloatTy, CFP->getValue()); 511 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 512 // Only do this if the target has a native EXTLOAD instruction from 513 // f32. 514 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 515 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 516 VT = MVT::f32; 517 Extend = true; 518 } 519 520 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 521 if (Extend) { 522 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 523 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 524 } else { 525 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 526 DAG.getSrcValue(NULL)); 527 } 528 } 529 break; 530 } 531 case ISD::ConstantVec: 532 switch (TLI.getOperationAction(ISD::ConstantVec, Node->getValueType(0))) { 533 default: assert(0 && "This action is not supported yet!"); 534 case TargetLowering::Custom: 535 Tmp3 = TLI.LowerOperation(Result, DAG); 536 if (Tmp3.Val) { 537 Result = Tmp3; 538 break; 539 } 540 // FALLTHROUGH 541 case TargetLowering::Expand: 542 // We assume that vector constants are not legal, and will be immediately 543 // spilled to the constant pool. 544 // 545 // Create a ConstantPacked, and put it in the constant pool. 546 MVT::ValueType VT = Node->getValueType(0); 547 const Type *OpNTy = 548 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 549 std::vector<Constant*> CV; 550 if (MVT::isFloatingPoint(VT)) { 551 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 552 double V = cast<ConstantFPSDNode>(Node->getOperand(i))->getValue(); 553 CV.push_back(ConstantFP::get(OpNTy, V)); 554 } 555 } else { 556 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 557 uint64_t V = cast<ConstantSDNode>(Node->getOperand(i))->getValue(); 558 CV.push_back(ConstantUInt::get(OpNTy, V)); 559 } 560 } 561 Constant *CP = ConstantPacked::get(CV); 562 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 563 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 564 DAG.getSrcValue(NULL)); 565 break; 566 } 567 break; 568 case ISD::TokenFactor: 569 if (Node->getNumOperands() == 2) { 570 Tmp1 = LegalizeOp(Node->getOperand(0)); 571 Tmp2 = LegalizeOp(Node->getOperand(1)); 572 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 573 } else if (Node->getNumOperands() == 3) { 574 Tmp1 = LegalizeOp(Node->getOperand(0)); 575 Tmp2 = LegalizeOp(Node->getOperand(1)); 576 Tmp3 = LegalizeOp(Node->getOperand(2)); 577 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 578 } else { 579 std::vector<SDOperand> Ops; 580 // Legalize the operands. 581 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 582 Ops.push_back(LegalizeOp(Node->getOperand(i))); 583 Result = DAG.UpdateNodeOperands(Result, Ops); 584 } 585 break; 586 587 case ISD::CALLSEQ_START: 588 case ISD::CALLSEQ_END: 589 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 590 // Do not try to legalize the target-specific arguments (#1+), except for 591 // an optional flag input. 592 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 593 if (Tmp1 != Node->getOperand(0)) { 594 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 595 Ops[0] = Tmp1; 596 Result = DAG.UpdateNodeOperands(Result, Ops); 597 } 598 } else { 599 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 600 if (Tmp1 != Node->getOperand(0) || 601 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 602 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 603 Ops[0] = Tmp1; 604 Ops.back() = Tmp2; 605 Result = DAG.UpdateNodeOperands(Result, Ops); 606 } 607 } 608 break; 609 case ISD::DYNAMIC_STACKALLOC: { 610 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 611 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 612 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 613 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 614 615 Tmp1 = Result.getValue(0); 616 Tmp2 = Result.getValue(1); 617 switch (TLI.getOperationAction(Node->getOpcode(), 618 Node->getValueType(0))) { 619 default: assert(0 && "This action is not supported yet!"); 620 case TargetLowering::Expand: { 621 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 622 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 623 " not tell us which reg is the stack pointer!"); 624 SDOperand Chain = Tmp1.getOperand(0); 625 SDOperand Size = Tmp2.getOperand(1); 626 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0)); 627 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value 628 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain 629 Tmp1 = LegalizeOp(Tmp1); 630 Tmp2 = LegalizeOp(Tmp2); 631 break; 632 } 633 case TargetLowering::Custom: 634 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 635 if (Tmp3.Val) { 636 Tmp1 = LegalizeOp(Tmp3); 637 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 638 } 639 break; 640 case TargetLowering::Legal: 641 break; 642 } 643 // Since this op produce two values, make sure to remember that we 644 // legalized both of them. 645 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 646 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 647 return Op.ResNo ? Tmp2 : Tmp1; 648 } 649 case ISD::INLINEASM: 650 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize Chain. 651 Tmp2 = Node->getOperand(Node->getNumOperands()-1); 652 if (Tmp2.getValueType() == MVT::Flag) // Legalize Flag if it exists. 653 Tmp2 = Tmp3 = SDOperand(0, 0); 654 else 655 Tmp3 = LegalizeOp(Tmp2); 656 657 if (Tmp1 != Node->getOperand(0) || Tmp2 != Tmp3) { 658 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 659 Ops[0] = Tmp1; 660 if (Tmp3.Val) Ops.back() = Tmp3; 661 Result = DAG.UpdateNodeOperands(Result, Ops); 662 } 663 664 // INLINE asm returns a chain and flag, make sure to add both to the map. 665 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 666 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 667 return Result.getValue(Op.ResNo); 668 case ISD::BR: 669 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 670 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 671 break; 672 673 case ISD::BRCOND: 674 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 675 676 switch (getTypeAction(Node->getOperand(1).getValueType())) { 677 case Expand: assert(0 && "It's impossible to expand bools"); 678 case Legal: 679 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 680 break; 681 case Promote: 682 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 683 break; 684 } 685 686 // Basic block destination (Op#2) is always legal. 687 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 688 689 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 690 default: assert(0 && "This action is not supported yet!"); 691 case TargetLowering::Legal: break; 692 case TargetLowering::Custom: 693 Tmp1 = TLI.LowerOperation(Result, DAG); 694 if (Tmp1.Val) Result = Tmp1; 695 break; 696 case TargetLowering::Expand: 697 // Expand brcond's setcc into its constituent parts and create a BR_CC 698 // Node. 699 if (Tmp2.getOpcode() == ISD::SETCC) { 700 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 701 Tmp2.getOperand(0), Tmp2.getOperand(1), 702 Node->getOperand(2)); 703 } else { 704 // Make sure the condition is either zero or one. It may have been 705 // promoted from something else. 706 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 707 708 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 709 DAG.getCondCode(ISD::SETNE), Tmp2, 710 DAG.getConstant(0, Tmp2.getValueType()), 711 Node->getOperand(2)); 712 } 713 break; 714 } 715 break; 716 case ISD::BR_CC: 717 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 718 if (!isTypeLegal(Node->getOperand(2).getValueType())) { 719 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 720 Node->getOperand(2), // LHS 721 Node->getOperand(3), // RHS 722 Node->getOperand(1))); 723 // If we get a SETCC back from legalizing the SETCC node we just 724 // created, then use its LHS, RHS, and CC directly in creating a new 725 // node. Otherwise, select between the true and false value based on 726 // comparing the result of the legalized with zero. 727 if (Tmp2.getOpcode() == ISD::SETCC) { 728 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 729 Tmp2.getOperand(0), Tmp2.getOperand(1), 730 Node->getOperand(4)); 731 } else { 732 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 733 DAG.getCondCode(ISD::SETNE), 734 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 735 Node->getOperand(4)); 736 } 737 break; 738 } 739 740 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 741 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 742 743 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 744 Tmp3, Node->getOperand(4)); 745 746 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 747 default: assert(0 && "Unexpected action for BR_CC!"); 748 case TargetLowering::Legal: break; 749 case TargetLowering::Custom: 750 Tmp4 = TLI.LowerOperation(Result, DAG); 751 if (Tmp4.Val) Result = Tmp4; 752 break; 753 } 754 break; 755 case ISD::BRCONDTWOWAY: 756 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 757 switch (getTypeAction(Node->getOperand(1).getValueType())) { 758 case Expand: assert(0 && "It's impossible to expand bools"); 759 case Legal: 760 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 761 break; 762 case Promote: 763 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 764 break; 765 } 766 767 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 768 // pair. 769 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 770 case TargetLowering::Promote: 771 default: assert(0 && "This action is not supported yet!"); 772 case TargetLowering::Legal: 773 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), 774 Node->getOperand(3)); 775 break; 776 case TargetLowering::Expand: 777 // If BRTWOWAY_CC is legal for this target, then simply expand this node 778 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 779 // BRCOND/BR pair. 780 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 781 if (Tmp2.getOpcode() == ISD::SETCC) { 782 Tmp3 = Tmp2.getOperand(0); 783 Tmp4 = Tmp2.getOperand(1); 784 Tmp2 = Tmp2.getOperand(2); 785 } else { 786 Tmp3 = Tmp2; 787 Tmp4 = DAG.getConstant(0, Tmp2.getValueType()); 788 Tmp2 = DAG.getCondCode(ISD::SETNE); 789 } 790 std::vector<SDOperand> Ops; 791 Ops.push_back(Tmp1); 792 Ops.push_back(Tmp2); 793 Ops.push_back(Tmp3); 794 Ops.push_back(Tmp4); 795 Ops.push_back(Node->getOperand(2)); 796 Ops.push_back(Node->getOperand(3)); 797 Result = DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); 798 } else { 799 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 800 Node->getOperand(2)); 801 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 802 } 803 break; 804 } 805 break; 806 case ISD::BRTWOWAY_CC: 807 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 808 if (isTypeLegal(Node->getOperand(2).getValueType())) { 809 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 810 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 811 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 812 Tmp3 != Node->getOperand(3)) { 813 std::vector<SDOperand> Ops; 814 Ops.push_back(Tmp1); 815 Ops.push_back(Node->getOperand(1)); 816 Ops.push_back(Tmp2); 817 Ops.push_back(Tmp3); 818 Ops.push_back(Node->getOperand(4)); 819 Ops.push_back(Node->getOperand(5)); 820 Result = DAG.UpdateNodeOperands(Result, Ops); 821 } 822 break; 823 } else { 824 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 825 Node->getOperand(2), // LHS 826 Node->getOperand(3), // RHS 827 Node->getOperand(1))); 828 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 829 // pair. 830 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 831 default: assert(0 && "This action is not supported yet!"); 832 case TargetLowering::Legal: { 833 // If we get a SETCC back from legalizing the SETCC node we just 834 // created, then use its LHS, RHS, and CC directly in creating a new 835 // node. Otherwise, select between the true and false value based on 836 // comparing the result of the legalized with zero. 837 std::vector<SDOperand> Ops; 838 Ops.push_back(Tmp1); 839 if (Tmp2.getOpcode() == ISD::SETCC) { 840 Ops.push_back(Tmp2.getOperand(2)); 841 Ops.push_back(Tmp2.getOperand(0)); 842 Ops.push_back(Tmp2.getOperand(1)); 843 } else { 844 Ops.push_back(DAG.getCondCode(ISD::SETNE)); 845 Ops.push_back(Tmp2); 846 Ops.push_back(DAG.getConstant(0, Tmp2.getValueType())); 847 } 848 Ops.push_back(Node->getOperand(4)); 849 Ops.push_back(Node->getOperand(5)); 850 Result = DAG.UpdateNodeOperands(Result, Ops); 851 break; 852 } 853 case TargetLowering::Expand: 854 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 855 Node->getOperand(4)); 856 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 857 break; 858 } 859 } 860 break; 861 case ISD::LOAD: { 862 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 863 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 864 865 MVT::ValueType VT = Node->getValueType(0); 866 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 867 Tmp2 = Result.getValue(0); 868 Tmp3 = Result.getValue(1); 869 870 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 871 default: assert(0 && "This action is not supported yet!"); 872 case TargetLowering::Legal: break; 873 case TargetLowering::Custom: 874 Tmp1 = TLI.LowerOperation(Tmp2, DAG); 875 if (Tmp1.Val) { 876 Tmp2 = LegalizeOp(Tmp1); 877 Tmp3 = LegalizeOp(Tmp1.getValue(1)); 878 } 879 break; 880 } 881 // Since loads produce two values, make sure to remember that we 882 // legalized both of them. 883 AddLegalizedOperand(SDOperand(Node, 0), Tmp2); 884 AddLegalizedOperand(SDOperand(Node, 1), Tmp3); 885 return Op.ResNo ? Tmp3 : Tmp2; 886 } 887 case ISD::EXTLOAD: 888 case ISD::SEXTLOAD: 889 case ISD::ZEXTLOAD: { 890 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 891 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 892 893 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 894 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 895 default: assert(0 && "This action is not supported yet!"); 896 case TargetLowering::Promote: 897 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 898 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), 899 DAG.getValueType(MVT::i8)); 900 Tmp1 = Result.getValue(0); 901 Tmp2 = Result.getValue(1); 902 break; 903 case TargetLowering::Custom: 904 isCustom = true; 905 // FALLTHROUGH 906 case TargetLowering::Legal: 907 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), 908 Node->getOperand(3)); 909 Tmp1 = Result.getValue(0); 910 Tmp2 = Result.getValue(1); 911 912 if (isCustom) { 913 Tmp3 = TLI.LowerOperation(Tmp3, DAG); 914 if (Tmp3.Val) { 915 Tmp1 = LegalizeOp(Tmp3); 916 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 917 } 918 } 919 break; 920 case TargetLowering::Expand: 921 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 922 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 923 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 924 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 925 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 926 Tmp2 = LegalizeOp(Load.getValue(1)); 927 break; 928 } 929 assert(Node->getOpcode() != ISD::EXTLOAD && 930 "EXTLOAD should always be supported!"); 931 // Turn the unsupported load into an EXTLOAD followed by an explicit 932 // zero/sign extend inreg. 933 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 934 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 935 SDOperand ValRes; 936 if (Node->getOpcode() == ISD::SEXTLOAD) 937 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 938 Result, DAG.getValueType(SrcVT)); 939 else 940 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 941 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 942 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 943 break; 944 } 945 // Since loads produce two values, make sure to remember that we legalized 946 // both of them. 947 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 948 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 949 return Op.ResNo ? Tmp2 : Tmp1; 950 } 951 case ISD::EXTRACT_ELEMENT: { 952 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 953 switch (getTypeAction(OpTy)) { 954 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 955 case Legal: 956 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 957 // 1 -> Hi 958 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 959 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 960 TLI.getShiftAmountTy())); 961 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 962 } else { 963 // 0 -> Lo 964 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 965 Node->getOperand(0)); 966 } 967 break; 968 case Expand: 969 // Get both the low and high parts. 970 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 971 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 972 Result = Tmp2; // 1 -> Hi 973 else 974 Result = Tmp1; // 0 -> Lo 975 break; 976 } 977 break; 978 } 979 980 case ISD::CopyToReg: 981 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 982 983 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 984 "Register type must be legal!"); 985 // Legalize the incoming value (must be a legal type). 986 Tmp2 = LegalizeOp(Node->getOperand(2)); 987 if (Node->getNumValues() == 1) { 988 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 989 } else { 990 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 991 if (Node->getNumOperands() == 4) { 992 Tmp3 = LegalizeOp(Node->getOperand(3)); 993 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 994 Tmp3); 995 } else { 996 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 997 } 998 999 // Since this produces two values, make sure to remember that we legalized 1000 // both of them. 1001 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1002 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1003 return Result; 1004 } 1005 break; 1006 1007 case ISD::RET: 1008 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1009 switch (Node->getNumOperands()) { 1010 case 2: // ret val 1011 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1012 case Legal: 1013 Tmp2 = LegalizeOp(Node->getOperand(1)); 1014 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1015 break; 1016 case Expand: { 1017 SDOperand Lo, Hi; 1018 ExpandOp(Node->getOperand(1), Lo, Hi); 1019 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1020 break; 1021 } 1022 case Promote: 1023 Tmp2 = PromoteOp(Node->getOperand(1)); 1024 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1025 Result = LegalizeOp(Result); 1026 break; 1027 } 1028 break; 1029 case 1: // ret void 1030 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1031 break; 1032 default: { // ret <values> 1033 std::vector<SDOperand> NewValues; 1034 NewValues.push_back(Tmp1); 1035 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1036 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1037 case Legal: 1038 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1039 break; 1040 case Expand: { 1041 SDOperand Lo, Hi; 1042 ExpandOp(Node->getOperand(i), Lo, Hi); 1043 NewValues.push_back(Lo); 1044 NewValues.push_back(Hi); 1045 break; 1046 } 1047 case Promote: 1048 assert(0 && "Can't promote multiple return value yet!"); 1049 } 1050 1051 if (NewValues.size() == Node->getNumOperands()) 1052 Result = DAG.UpdateNodeOperands(Result, NewValues); 1053 else 1054 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1055 break; 1056 } 1057 } 1058 1059 if (Result.getOpcode() == ISD::RET) { 1060 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 1061 default: assert(0 && "This action is not supported yet!"); 1062 case TargetLowering::Legal: break; 1063 case TargetLowering::Custom: 1064 Tmp1 = TLI.LowerOperation(Result, DAG); 1065 if (Tmp1.Val) Result = Tmp1; 1066 break; 1067 } 1068 } 1069 break; 1070 case ISD::STORE: { 1071 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1072 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1073 1074 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1075 // FIXME: We shouldn't do this for TargetConstantFP's. 1076 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1077 if (CFP->getValueType(0) == MVT::f32) { 1078 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 1079 } else { 1080 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1081 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 1082 } 1083 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1084 Node->getOperand(3)); 1085 break; 1086 } 1087 1088 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1089 case Legal: { 1090 Tmp3 = LegalizeOp(Node->getOperand(1)); 1091 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1092 Node->getOperand(3)); 1093 1094 MVT::ValueType VT = Tmp3.getValueType(); 1095 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1096 default: assert(0 && "This action is not supported yet!"); 1097 case TargetLowering::Legal: break; 1098 case TargetLowering::Custom: 1099 Tmp1 = TLI.LowerOperation(Result, DAG); 1100 if (Tmp1.Val) Result = Tmp1; 1101 break; 1102 } 1103 break; 1104 } 1105 case Promote: 1106 // Truncate the value and store the result. 1107 Tmp3 = PromoteOp(Node->getOperand(1)); 1108 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1109 Node->getOperand(3), 1110 DAG.getValueType(Node->getOperand(1).getValueType())); 1111 break; 1112 1113 case Expand: 1114 SDOperand Lo, Hi; 1115 ExpandOp(Node->getOperand(1), Lo, Hi); 1116 1117 if (!TLI.isLittleEndian()) 1118 std::swap(Lo, Hi); 1119 1120 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1121 Node->getOperand(3)); 1122 // If this is a vector type, then we have to calculate the increment as 1123 // the product of the element size in bytes, and the number of elements 1124 // in the high half of the vector. 1125 unsigned IncrementSize; 1126 if (MVT::Vector == Hi.getValueType()) { 1127 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue(); 1128 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT(); 1129 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8; 1130 } else { 1131 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1132 } 1133 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1134 getIntPtrConstant(IncrementSize)); 1135 assert(isTypeLegal(Tmp2.getValueType()) && 1136 "Pointers must be legal!"); 1137 // FIXME: This sets the srcvalue of both halves to be the same, which is 1138 // wrong. 1139 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1140 Node->getOperand(3)); 1141 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1142 break; 1143 } 1144 break; 1145 } 1146 case ISD::PCMARKER: 1147 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1148 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1149 break; 1150 case ISD::STACKSAVE: 1151 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1152 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1153 Tmp1 = Result.getValue(0); 1154 Tmp2 = Result.getValue(1); 1155 1156 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 1157 default: assert(0 && "This action is not supported yet!"); 1158 case TargetLowering::Legal: break; 1159 case TargetLowering::Custom: 1160 Tmp3 = TLI.LowerOperation(Result, DAG); 1161 if (Tmp3.Val) { 1162 Tmp1 = LegalizeOp(Tmp3); 1163 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1164 } 1165 break; 1166 case TargetLowering::Expand: 1167 // Expand to CopyFromReg if the target set 1168 // StackPointerRegisterToSaveRestore. 1169 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1170 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 1171 Node->getValueType(0)); 1172 Tmp2 = Tmp1.getValue(1); 1173 } else { 1174 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 1175 Tmp2 = Node->getOperand(0); 1176 } 1177 break; 1178 } 1179 1180 // Since stacksave produce two values, make sure to remember that we 1181 // legalized both of them. 1182 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1183 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1184 return Op.ResNo ? Tmp2 : Tmp1; 1185 1186 case ISD::STACKRESTORE: 1187 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1188 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1189 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1190 1191 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 1192 default: assert(0 && "This action is not supported yet!"); 1193 case TargetLowering::Legal: break; 1194 case TargetLowering::Custom: 1195 Tmp1 = TLI.LowerOperation(Result, DAG); 1196 if (Tmp1.Val) Result = Tmp1; 1197 break; 1198 case TargetLowering::Expand: 1199 // Expand to CopyToReg if the target set 1200 // StackPointerRegisterToSaveRestore. 1201 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1202 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 1203 } else { 1204 Result = Tmp1; 1205 } 1206 break; 1207 } 1208 break; 1209 1210 case ISD::READCYCLECOUNTER: 1211 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1212 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1213 1214 // Since rdcc produce two values, make sure to remember that we legalized 1215 // both of them. 1216 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1217 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1218 return Result; 1219 1220 case ISD::TRUNCSTORE: { 1221 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1222 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1223 1224 assert(isTypeLegal(Node->getOperand(1).getValueType()) && 1225 "Cannot handle illegal TRUNCSTORE yet!"); 1226 Tmp2 = LegalizeOp(Node->getOperand(1)); 1227 1228 // The only promote case we handle is TRUNCSTORE:i1 X into 1229 // -> TRUNCSTORE:i8 (and X, 1) 1230 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1231 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1232 TargetLowering::Promote) { 1233 // Promote the bool to a mask then store. 1234 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1235 DAG.getConstant(1, Tmp2.getValueType())); 1236 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1237 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1238 1239 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1240 Tmp3 != Node->getOperand(2)) { 1241 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 1242 Node->getOperand(3), Node->getOperand(4)); 1243 } 1244 1245 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT(); 1246 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) { 1247 default: assert(0 && "This action is not supported yet!"); 1248 case TargetLowering::Legal: break; 1249 case TargetLowering::Custom: 1250 Tmp1 = TLI.LowerOperation(Result, DAG); 1251 if (Tmp1.Val) Result = Tmp1; 1252 break; 1253 } 1254 break; 1255 } 1256 case ISD::SELECT: 1257 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1258 case Expand: assert(0 && "It's impossible to expand bools"); 1259 case Legal: 1260 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1261 break; 1262 case Promote: 1263 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1264 break; 1265 } 1266 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1267 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1268 1269 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1270 1271 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1272 default: assert(0 && "This action is not supported yet!"); 1273 case TargetLowering::Legal: break; 1274 case TargetLowering::Custom: { 1275 Tmp1 = TLI.LowerOperation(Result, DAG); 1276 if (Tmp1.Val) Result = Tmp1; 1277 break; 1278 } 1279 case TargetLowering::Expand: 1280 if (Tmp1.getOpcode() == ISD::SETCC) { 1281 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1282 Tmp2, Tmp3, 1283 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1284 } else { 1285 // Make sure the condition is either zero or one. It may have been 1286 // promoted from something else. 1287 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1288 Result = DAG.getSelectCC(Tmp1, 1289 DAG.getConstant(0, Tmp1.getValueType()), 1290 Tmp2, Tmp3, ISD::SETNE); 1291 } 1292 break; 1293 case TargetLowering::Promote: { 1294 MVT::ValueType NVT = 1295 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1296 unsigned ExtOp, TruncOp; 1297 if (MVT::isInteger(Tmp2.getValueType())) { 1298 ExtOp = ISD::ANY_EXTEND; 1299 TruncOp = ISD::TRUNCATE; 1300 } else { 1301 ExtOp = ISD::FP_EXTEND; 1302 TruncOp = ISD::FP_ROUND; 1303 } 1304 // Promote each of the values to the new type. 1305 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1306 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1307 // Perform the larger operation, then round down. 1308 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1309 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1310 break; 1311 } 1312 } 1313 break; 1314 case ISD::SELECT_CC: 1315 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1316 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1317 1318 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1319 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1320 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1321 1322 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, 1323 Node->getOperand(4)); 1324 1325 // Everything is legal, see if we should expand this op or something. 1326 switch (TLI.getOperationAction(ISD::SELECT_CC, 1327 Node->getOperand(0).getValueType())) { 1328 default: assert(0 && "This action is not supported yet!"); 1329 case TargetLowering::Legal: break; 1330 case TargetLowering::Custom: 1331 Tmp1 = TLI.LowerOperation(Result, DAG); 1332 if (Tmp1.Val) Result = Tmp1; 1333 break; 1334 } 1335 break; 1336 } else { 1337 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1338 Node->getOperand(0), // LHS 1339 Node->getOperand(1), // RHS 1340 Node->getOperand(4))); 1341 // If we get a SETCC back from legalizing the SETCC node we just 1342 // created, then use its LHS, RHS, and CC directly in creating a new 1343 // node. Otherwise, select between the true and false value based on 1344 // comparing the result of the legalized with zero. 1345 if (Tmp1.getOpcode() == ISD::SETCC) { 1346 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1347 Tmp1.getOperand(0), Tmp1.getOperand(1), 1348 Tmp3, Tmp4, Tmp1.getOperand(2)); 1349 } else { 1350 Result = DAG.getSelectCC(Tmp1, 1351 DAG.getConstant(0, Tmp1.getValueType()), 1352 Tmp3, Tmp4, ISD::SETNE); 1353 } 1354 } 1355 break; 1356 case ISD::SETCC: 1357 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1358 case Legal: 1359 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1360 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1361 break; 1362 case Promote: 1363 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1364 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1365 1366 // If this is an FP compare, the operands have already been extended. 1367 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1368 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1369 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1370 1371 // Otherwise, we have to insert explicit sign or zero extends. Note 1372 // that we could insert sign extends for ALL conditions, but zero extend 1373 // is cheaper on many machines (an AND instead of two shifts), so prefer 1374 // it. 1375 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1376 default: assert(0 && "Unknown integer comparison!"); 1377 case ISD::SETEQ: 1378 case ISD::SETNE: 1379 case ISD::SETUGE: 1380 case ISD::SETUGT: 1381 case ISD::SETULE: 1382 case ISD::SETULT: 1383 // ALL of these operations will work if we either sign or zero extend 1384 // the operands (including the unsigned comparisons!). Zero extend is 1385 // usually a simpler/cheaper operation, so prefer it. 1386 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1387 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1388 break; 1389 case ISD::SETGE: 1390 case ISD::SETGT: 1391 case ISD::SETLT: 1392 case ISD::SETLE: 1393 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1394 DAG.getValueType(VT)); 1395 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1396 DAG.getValueType(VT)); 1397 break; 1398 } 1399 } 1400 break; 1401 case Expand: 1402 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1403 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1404 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1405 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1406 case ISD::SETEQ: 1407 case ISD::SETNE: 1408 if (RHSLo == RHSHi) 1409 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1410 if (RHSCST->isAllOnesValue()) { 1411 // Comparison to -1. 1412 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1413 Tmp2 = RHSLo; 1414 break; 1415 } 1416 1417 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1418 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1419 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1420 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1421 break; 1422 default: 1423 // If this is a comparison of the sign bit, just look at the top part. 1424 // X > -1, x < 0 1425 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1426 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1427 CST->getValue() == 0) || // X < 0 1428 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1429 (CST->isAllOnesValue()))) { // X > -1 1430 Tmp1 = LHSHi; 1431 Tmp2 = RHSHi; 1432 break; 1433 } 1434 1435 // FIXME: This generated code sucks. 1436 ISD::CondCode LowCC; 1437 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1438 default: assert(0 && "Unknown integer setcc!"); 1439 case ISD::SETLT: 1440 case ISD::SETULT: LowCC = ISD::SETULT; break; 1441 case ISD::SETGT: 1442 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1443 case ISD::SETLE: 1444 case ISD::SETULE: LowCC = ISD::SETULE; break; 1445 case ISD::SETGE: 1446 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1447 } 1448 1449 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1450 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1451 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1452 1453 // NOTE: on targets without efficient SELECT of bools, we can always use 1454 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1455 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1456 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1457 Node->getOperand(2)); 1458 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1459 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1460 Result, Tmp1, Tmp2)); 1461 AddLegalizedOperand(SDOperand(Node, 0), Result); 1462 return Result; 1463 } 1464 } 1465 1466 switch (TLI.getOperationAction(ISD::SETCC, 1467 Node->getOperand(0).getValueType())) { 1468 default: assert(0 && "Cannot handle this action for SETCC yet!"); 1469 case TargetLowering::Custom: 1470 isCustom = true; 1471 // FALLTHROUGH. 1472 case TargetLowering::Legal: 1473 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1474 if (isCustom) { 1475 Tmp3 = TLI.LowerOperation(Result, DAG); 1476 if (Tmp3.Val) Result = Tmp3; 1477 } 1478 break; 1479 case TargetLowering::Promote: { 1480 // First step, figure out the appropriate operation to use. 1481 // Allow SETCC to not be supported for all legal data types 1482 // Mostly this targets FP 1483 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 1484 MVT::ValueType OldVT = NewInTy; 1485 1486 // Scan for the appropriate larger type to use. 1487 while (1) { 1488 NewInTy = (MVT::ValueType)(NewInTy+1); 1489 1490 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 1491 "Fell off of the edge of the integer world"); 1492 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 1493 "Fell off of the edge of the floating point world"); 1494 1495 // If the target supports SETCC of this type, use it. 1496 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 1497 break; 1498 } 1499 if (MVT::isInteger(NewInTy)) 1500 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1501 else { 1502 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 1503 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 1504 } 1505 Tmp1 = LegalizeOp(Tmp1); 1506 Tmp2 = LegalizeOp(Tmp2); 1507 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1508 Result = LegalizeOp(Result); 1509 break; 1510 } 1511 case TargetLowering::Expand: 1512 // Expand a setcc node into a select_cc of the same condition, lhs, and 1513 // rhs that selects between const 1 (true) and const 0 (false). 1514 MVT::ValueType VT = Node->getValueType(0); 1515 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1516 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1517 Node->getOperand(2)); 1518 break; 1519 } 1520 break; 1521 case ISD::MEMSET: 1522 case ISD::MEMCPY: 1523 case ISD::MEMMOVE: { 1524 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1525 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1526 1527 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1528 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1529 case Expand: assert(0 && "Cannot expand a byte!"); 1530 case Legal: 1531 Tmp3 = LegalizeOp(Node->getOperand(2)); 1532 break; 1533 case Promote: 1534 Tmp3 = PromoteOp(Node->getOperand(2)); 1535 break; 1536 } 1537 } else { 1538 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1539 } 1540 1541 SDOperand Tmp4; 1542 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1543 case Expand: { 1544 // Length is too big, just take the lo-part of the length. 1545 SDOperand HiPart; 1546 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1547 break; 1548 } 1549 case Legal: 1550 Tmp4 = LegalizeOp(Node->getOperand(3)); 1551 break; 1552 case Promote: 1553 Tmp4 = PromoteOp(Node->getOperand(3)); 1554 break; 1555 } 1556 1557 SDOperand Tmp5; 1558 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1559 case Expand: assert(0 && "Cannot expand this yet!"); 1560 case Legal: 1561 Tmp5 = LegalizeOp(Node->getOperand(4)); 1562 break; 1563 case Promote: 1564 Tmp5 = PromoteOp(Node->getOperand(4)); 1565 break; 1566 } 1567 1568 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1569 default: assert(0 && "This action not implemented for this operation!"); 1570 case TargetLowering::Custom: 1571 isCustom = true; 1572 // FALLTHROUGH 1573 case TargetLowering::Legal: 1574 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 1575 if (isCustom) { 1576 Tmp1 = TLI.LowerOperation(Result, DAG); 1577 if (Tmp1.Val) Result = Tmp1; 1578 } 1579 break; 1580 case TargetLowering::Expand: { 1581 // Otherwise, the target does not support this operation. Lower the 1582 // operation to an explicit libcall as appropriate. 1583 MVT::ValueType IntPtr = TLI.getPointerTy(); 1584 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1585 std::vector<std::pair<SDOperand, const Type*> > Args; 1586 1587 const char *FnName = 0; 1588 if (Node->getOpcode() == ISD::MEMSET) { 1589 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1590 // Extend the ubyte argument to be an int value for the call. 1591 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1592 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1593 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1594 1595 FnName = "memset"; 1596 } else if (Node->getOpcode() == ISD::MEMCPY || 1597 Node->getOpcode() == ISD::MEMMOVE) { 1598 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1599 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1600 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1601 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1602 } else { 1603 assert(0 && "Unknown op!"); 1604 } 1605 1606 std::pair<SDOperand,SDOperand> CallResult = 1607 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1608 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1609 Result = CallResult.second; 1610 break; 1611 } 1612 } 1613 break; 1614 } 1615 1616 case ISD::READPORT: 1617 Tmp1 = LegalizeOp(Node->getOperand(0)); 1618 Tmp2 = LegalizeOp(Node->getOperand(1)); 1619 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1620 1621 // Since these produce two values, make sure to remember that we legalized 1622 // both of them. 1623 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1624 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1625 return Result; 1626 case ISD::WRITEPORT: 1627 Tmp1 = LegalizeOp(Node->getOperand(0)); 1628 Tmp2 = LegalizeOp(Node->getOperand(1)); 1629 Tmp3 = LegalizeOp(Node->getOperand(2)); 1630 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1631 break; 1632 1633 case ISD::READIO: 1634 Tmp1 = LegalizeOp(Node->getOperand(0)); 1635 Tmp2 = LegalizeOp(Node->getOperand(1)); 1636 1637 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1638 case TargetLowering::Custom: 1639 default: assert(0 && "This action not implemented for this operation!"); 1640 case TargetLowering::Legal: 1641 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1642 break; 1643 case TargetLowering::Expand: 1644 // Replace this with a load from memory. 1645 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 1646 Node->getOperand(1), DAG.getSrcValue(NULL)); 1647 Result = LegalizeOp(Result); 1648 break; 1649 } 1650 1651 // Since these produce two values, make sure to remember that we legalized 1652 // both of them. 1653 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1654 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1655 return Result.getValue(Op.ResNo); 1656 1657 case ISD::WRITEIO: 1658 Tmp1 = LegalizeOp(Node->getOperand(0)); 1659 Tmp2 = LegalizeOp(Node->getOperand(1)); 1660 Tmp3 = LegalizeOp(Node->getOperand(2)); 1661 1662 switch (TLI.getOperationAction(Node->getOpcode(), 1663 Node->getOperand(1).getValueType())) { 1664 case TargetLowering::Custom: 1665 default: assert(0 && "This action not implemented for this operation!"); 1666 case TargetLowering::Legal: 1667 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1668 break; 1669 case TargetLowering::Expand: 1670 // Replace this with a store to memory. 1671 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 1672 Node->getOperand(1), Node->getOperand(2), 1673 DAG.getSrcValue(NULL)); 1674 break; 1675 } 1676 break; 1677 1678 case ISD::ADD_PARTS: 1679 case ISD::SUB_PARTS: 1680 case ISD::SHL_PARTS: 1681 case ISD::SRA_PARTS: 1682 case ISD::SRL_PARTS: { 1683 std::vector<SDOperand> Ops; 1684 bool Changed = false; 1685 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1686 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1687 Changed |= Ops.back() != Node->getOperand(i); 1688 } 1689 if (Changed) 1690 Result = DAG.UpdateNodeOperands(Result, Ops); 1691 1692 switch (TLI.getOperationAction(Node->getOpcode(), 1693 Node->getValueType(0))) { 1694 default: assert(0 && "This action is not supported yet!"); 1695 case TargetLowering::Legal: break; 1696 case TargetLowering::Custom: 1697 Tmp1 = TLI.LowerOperation(Result, DAG); 1698 if (Tmp1.Val) { 1699 SDOperand Tmp2, RetVal(0, 0); 1700 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 1701 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 1702 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 1703 if (i == Op.ResNo) 1704 RetVal = Tmp2; 1705 } 1706 assert(RetVal.Val && "Illegal result number"); 1707 return RetVal; 1708 } 1709 break; 1710 } 1711 1712 // Since these produce multiple values, make sure to remember that we 1713 // legalized all of them. 1714 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1715 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1716 return Result.getValue(Op.ResNo); 1717 } 1718 1719 // Binary operators 1720 case ISD::ADD: 1721 case ISD::SUB: 1722 case ISD::MUL: 1723 case ISD::MULHS: 1724 case ISD::MULHU: 1725 case ISD::UDIV: 1726 case ISD::SDIV: 1727 case ISD::AND: 1728 case ISD::OR: 1729 case ISD::XOR: 1730 case ISD::SHL: 1731 case ISD::SRL: 1732 case ISD::SRA: 1733 case ISD::FADD: 1734 case ISD::FSUB: 1735 case ISD::FMUL: 1736 case ISD::FDIV: 1737 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1738 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1739 case Expand: assert(0 && "Not possible"); 1740 case Legal: 1741 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 1742 break; 1743 case Promote: 1744 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 1745 break; 1746 } 1747 1748 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1749 1750 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1751 default: assert(0 && "Operation not supported"); 1752 case TargetLowering::Legal: break; 1753 case TargetLowering::Custom: 1754 Tmp1 = TLI.LowerOperation(Result, DAG); 1755 if (Tmp1.Val) Result = Tmp1; 1756 break; 1757 } 1758 break; 1759 1760 case ISD::BUILD_PAIR: { 1761 MVT::ValueType PairTy = Node->getValueType(0); 1762 // TODO: handle the case where the Lo and Hi operands are not of legal type 1763 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 1764 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 1765 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 1766 case TargetLowering::Promote: 1767 case TargetLowering::Custom: 1768 assert(0 && "Cannot promote/custom this yet!"); 1769 case TargetLowering::Legal: 1770 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1771 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 1772 break; 1773 case TargetLowering::Expand: 1774 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 1775 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 1776 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 1777 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 1778 TLI.getShiftAmountTy())); 1779 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 1780 break; 1781 } 1782 break; 1783 } 1784 1785 case ISD::UREM: 1786 case ISD::SREM: 1787 case ISD::FREM: 1788 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1789 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1790 1791 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1792 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 1793 case TargetLowering::Custom: 1794 isCustom = true; 1795 // FALLTHROUGH 1796 case TargetLowering::Legal: 1797 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1798 if (isCustom) { 1799 Tmp1 = TLI.LowerOperation(Result, DAG); 1800 if (Tmp1.Val) Result = Tmp1; 1801 } 1802 break; 1803 case TargetLowering::Expand: 1804 if (MVT::isInteger(Node->getValueType(0))) { 1805 // X % Y -> X-X/Y*Y 1806 MVT::ValueType VT = Node->getValueType(0); 1807 unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV; 1808 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 1809 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 1810 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 1811 } else { 1812 // Floating point mod -> fmod libcall. 1813 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 1814 SDOperand Dummy; 1815 Result = ExpandLibCall(FnName, Node, Dummy); 1816 } 1817 break; 1818 } 1819 break; 1820 case ISD::VAARG: { 1821 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1822 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1823 1824 MVT::ValueType VT = Node->getValueType(0); 1825 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1826 default: assert(0 && "This action is not supported yet!"); 1827 case TargetLowering::Custom: 1828 isCustom = true; 1829 // FALLTHROUGH 1830 case TargetLowering::Legal: 1831 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1832 Result = Result.getValue(0); 1833 Tmp1 = Result.getValue(1); 1834 1835 if (isCustom) { 1836 Tmp2 = TLI.LowerOperation(Result, DAG); 1837 if (Tmp2.Val) { 1838 Result = LegalizeOp(Tmp2); 1839 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 1840 } 1841 } 1842 break; 1843 case TargetLowering::Expand: { 1844 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 1845 Node->getOperand(2)); 1846 // Increment the pointer, VAList, to the next vaarg 1847 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 1848 DAG.getConstant(MVT::getSizeInBits(VT)/8, 1849 TLI.getPointerTy())); 1850 // Store the incremented VAList to the legalized pointer 1851 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2, 1852 Node->getOperand(2)); 1853 // Load the actual argument out of the pointer VAList 1854 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0)); 1855 Tmp1 = LegalizeOp(Result.getValue(1)); 1856 Result = LegalizeOp(Result); 1857 break; 1858 } 1859 } 1860 // Since VAARG produces two values, make sure to remember that we 1861 // legalized both of them. 1862 AddLegalizedOperand(SDOperand(Node, 0), Result); 1863 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 1864 return Op.ResNo ? Tmp1 : Result; 1865 } 1866 1867 case ISD::VACOPY: 1868 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1869 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 1870 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 1871 1872 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 1873 default: assert(0 && "This action is not supported yet!"); 1874 case TargetLowering::Custom: 1875 isCustom = true; 1876 // FALLTHROUGH 1877 case TargetLowering::Legal: 1878 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 1879 Node->getOperand(3), Node->getOperand(4)); 1880 if (isCustom) { 1881 Tmp1 = TLI.LowerOperation(Result, DAG); 1882 if (Tmp1.Val) Result = Tmp1; 1883 } 1884 break; 1885 case TargetLowering::Expand: 1886 // This defaults to loading a pointer from the input and storing it to the 1887 // output, returning the chain. 1888 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3)); 1889 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2, 1890 Node->getOperand(4)); 1891 break; 1892 } 1893 break; 1894 1895 case ISD::VAEND: 1896 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1897 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1898 1899 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 1900 default: assert(0 && "This action is not supported yet!"); 1901 case TargetLowering::Custom: 1902 isCustom = true; 1903 // FALLTHROUGH 1904 case TargetLowering::Legal: 1905 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1906 if (isCustom) { 1907 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 1908 if (Tmp1.Val) Result = Tmp1; 1909 } 1910 break; 1911 case TargetLowering::Expand: 1912 Result = Tmp1; // Default to a no-op, return the chain 1913 break; 1914 } 1915 break; 1916 1917 case ISD::VASTART: 1918 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1919 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1920 1921 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1922 1923 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 1924 default: assert(0 && "This action is not supported yet!"); 1925 case TargetLowering::Legal: break; 1926 case TargetLowering::Custom: 1927 Tmp1 = TLI.LowerOperation(Result, DAG); 1928 if (Tmp1.Val) Result = Tmp1; 1929 break; 1930 } 1931 break; 1932 1933 case ISD::ROTL: 1934 case ISD::ROTR: 1935 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1936 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1937 1938 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 1939 "Cannot handle this yet!"); 1940 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1941 break; 1942 1943 case ISD::BSWAP: 1944 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 1945 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1946 case TargetLowering::Custom: 1947 assert(0 && "Cannot custom legalize this yet!"); 1948 case TargetLowering::Legal: 1949 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1950 break; 1951 case TargetLowering::Promote: { 1952 MVT::ValueType OVT = Tmp1.getValueType(); 1953 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1954 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT); 1955 1956 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1957 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 1958 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 1959 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 1960 break; 1961 } 1962 case TargetLowering::Expand: 1963 Result = ExpandBSWAP(Tmp1); 1964 break; 1965 } 1966 break; 1967 1968 case ISD::CTPOP: 1969 case ISD::CTTZ: 1970 case ISD::CTLZ: 1971 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 1972 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1973 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!"); 1974 case TargetLowering::Legal: 1975 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1976 break; 1977 case TargetLowering::Promote: { 1978 MVT::ValueType OVT = Tmp1.getValueType(); 1979 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1980 1981 // Zero extend the argument. 1982 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1983 // Perform the larger operation, then subtract if needed. 1984 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1985 switch (Node->getOpcode()) { 1986 case ISD::CTPOP: 1987 Result = Tmp1; 1988 break; 1989 case ISD::CTTZ: 1990 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 1991 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 1992 DAG.getConstant(getSizeInBits(NVT), NVT), 1993 ISD::SETEQ); 1994 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 1995 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 1996 break; 1997 case ISD::CTLZ: 1998 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 1999 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2000 DAG.getConstant(getSizeInBits(NVT) - 2001 getSizeInBits(OVT), NVT)); 2002 break; 2003 } 2004 break; 2005 } 2006 case TargetLowering::Expand: 2007 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 2008 break; 2009 } 2010 break; 2011 2012 // Unary operators 2013 case ISD::FABS: 2014 case ISD::FNEG: 2015 case ISD::FSQRT: 2016 case ISD::FSIN: 2017 case ISD::FCOS: 2018 Tmp1 = LegalizeOp(Node->getOperand(0)); 2019 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2020 case TargetLowering::Promote: 2021 case TargetLowering::Custom: 2022 assert(0 && "Cannot promote/custom handle this yet!"); 2023 case TargetLowering::Legal: 2024 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2025 break; 2026 case TargetLowering::Expand: 2027 switch (Node->getOpcode()) { 2028 default: assert(0 && "Unreachable!"); 2029 case ISD::FNEG: 2030 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2031 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2032 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 2033 break; 2034 case ISD::FABS: { 2035 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2036 MVT::ValueType VT = Node->getValueType(0); 2037 Tmp2 = DAG.getConstantFP(0.0, VT); 2038 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2039 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2040 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2041 break; 2042 } 2043 case ISD::FSQRT: 2044 case ISD::FSIN: 2045 case ISD::FCOS: { 2046 MVT::ValueType VT = Node->getValueType(0); 2047 const char *FnName = 0; 2048 switch(Node->getOpcode()) { 2049 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 2050 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 2051 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 2052 default: assert(0 && "Unreachable!"); 2053 } 2054 SDOperand Dummy; 2055 Result = ExpandLibCall(FnName, Node, Dummy); 2056 break; 2057 } 2058 } 2059 break; 2060 } 2061 break; 2062 2063 case ISD::BIT_CONVERT: 2064 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 2065 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2066 } else { 2067 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 2068 Node->getOperand(0).getValueType())) { 2069 default: assert(0 && "Unknown operation action!"); 2070 case TargetLowering::Expand: 2071 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2072 break; 2073 case TargetLowering::Legal: 2074 Tmp1 = LegalizeOp(Node->getOperand(0)); 2075 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2076 break; 2077 } 2078 } 2079 break; 2080 // Conversion operators. The source and destination have different types. 2081 case ISD::SINT_TO_FP: 2082 case ISD::UINT_TO_FP: { 2083 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2084 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2085 case Legal: 2086 switch (TLI.getOperationAction(Node->getOpcode(), 2087 Node->getOperand(0).getValueType())) { 2088 default: assert(0 && "Unknown operation action!"); 2089 case TargetLowering::Custom: 2090 isCustom = true; 2091 // FALLTHROUGH 2092 case TargetLowering::Legal: 2093 Tmp1 = LegalizeOp(Node->getOperand(0)); 2094 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2095 if (isCustom) { 2096 Tmp1 = TLI.LowerOperation(Result, DAG); 2097 if (Tmp1.Val) Result = Tmp1; 2098 } 2099 break; 2100 case TargetLowering::Expand: 2101 Result = ExpandLegalINT_TO_FP(isSigned, 2102 LegalizeOp(Node->getOperand(0)), 2103 Node->getValueType(0)); 2104 break; 2105 case TargetLowering::Promote: 2106 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2107 Node->getValueType(0), 2108 isSigned); 2109 break; 2110 } 2111 break; 2112 case Expand: 2113 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2114 Node->getValueType(0), Node->getOperand(0)); 2115 break; 2116 case Promote: 2117 Tmp1 = PromoteOp(Node->getOperand(0)); 2118 if (isSigned) { 2119 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 2120 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 2121 } else { 2122 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 2123 Node->getOperand(0).getValueType()); 2124 } 2125 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2126 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 2127 break; 2128 } 2129 break; 2130 } 2131 case ISD::TRUNCATE: 2132 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2133 case Legal: 2134 Tmp1 = LegalizeOp(Node->getOperand(0)); 2135 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2136 break; 2137 case Expand: 2138 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2139 2140 // Since the result is legal, we should just be able to truncate the low 2141 // part of the source. 2142 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2143 break; 2144 case Promote: 2145 Result = PromoteOp(Node->getOperand(0)); 2146 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2147 break; 2148 } 2149 break; 2150 2151 case ISD::FP_TO_SINT: 2152 case ISD::FP_TO_UINT: 2153 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2154 case Legal: 2155 Tmp1 = LegalizeOp(Node->getOperand(0)); 2156 2157 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2158 default: assert(0 && "Unknown operation action!"); 2159 case TargetLowering::Custom: 2160 isCustom = true; 2161 // FALLTHROUGH 2162 case TargetLowering::Legal: 2163 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2164 if (isCustom) { 2165 Tmp1 = TLI.LowerOperation(Result, DAG); 2166 if (Tmp1.Val) Result = Tmp1; 2167 } 2168 break; 2169 case TargetLowering::Promote: 2170 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2171 Node->getOpcode() == ISD::FP_TO_SINT); 2172 break; 2173 case TargetLowering::Expand: 2174 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2175 SDOperand True, False; 2176 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2177 MVT::ValueType NVT = Node->getValueType(0); 2178 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2179 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2180 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2181 Node->getOperand(0), Tmp2, ISD::SETLT); 2182 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2183 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2184 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2185 Tmp2)); 2186 False = DAG.getNode(ISD::XOR, NVT, False, 2187 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2188 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 2189 break; 2190 } else { 2191 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2192 } 2193 break; 2194 } 2195 break; 2196 case Expand: 2197 assert(0 && "Shouldn't need to expand other operators here!"); 2198 case Promote: 2199 Tmp1 = PromoteOp(Node->getOperand(0)); 2200 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 2201 Result = LegalizeOp(Result); 2202 break; 2203 } 2204 break; 2205 2206 case ISD::ANY_EXTEND: 2207 case ISD::ZERO_EXTEND: 2208 case ISD::SIGN_EXTEND: 2209 case ISD::FP_EXTEND: 2210 case ISD::FP_ROUND: 2211 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2212 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 2213 case Legal: 2214 Tmp1 = LegalizeOp(Node->getOperand(0)); 2215 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2216 break; 2217 case Promote: 2218 switch (Node->getOpcode()) { 2219 case ISD::ANY_EXTEND: 2220 Tmp1 = PromoteOp(Node->getOperand(0)); 2221 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 2222 break; 2223 case ISD::ZERO_EXTEND: 2224 Result = PromoteOp(Node->getOperand(0)); 2225 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2226 Result = DAG.getZeroExtendInReg(Result, 2227 Node->getOperand(0).getValueType()); 2228 break; 2229 case ISD::SIGN_EXTEND: 2230 Result = PromoteOp(Node->getOperand(0)); 2231 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2232 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2233 Result, 2234 DAG.getValueType(Node->getOperand(0).getValueType())); 2235 break; 2236 case ISD::FP_EXTEND: 2237 Result = PromoteOp(Node->getOperand(0)); 2238 if (Result.getValueType() != Op.getValueType()) 2239 // Dynamically dead while we have only 2 FP types. 2240 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2241 break; 2242 case ISD::FP_ROUND: 2243 Result = PromoteOp(Node->getOperand(0)); 2244 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2245 break; 2246 } 2247 } 2248 break; 2249 case ISD::FP_ROUND_INREG: 2250 case ISD::SIGN_EXTEND_INREG: { 2251 Tmp1 = LegalizeOp(Node->getOperand(0)); 2252 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2253 2254 // If this operation is not supported, convert it to a shl/shr or load/store 2255 // pair. 2256 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2257 default: assert(0 && "This action not supported for this op yet!"); 2258 case TargetLowering::Legal: 2259 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2260 break; 2261 case TargetLowering::Expand: 2262 // If this is an integer extend and shifts are supported, do that. 2263 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2264 // NOTE: we could fall back on load/store here too for targets without 2265 // SAR. However, it is doubtful that any exist. 2266 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2267 MVT::getSizeInBits(ExtraVT); 2268 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2269 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2270 Node->getOperand(0), ShiftCst); 2271 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2272 Result, ShiftCst); 2273 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2274 // The only way we can lower this is to turn it into a STORETRUNC, 2275 // EXTLOAD pair, targetting a temporary location (a stack slot). 2276 2277 // NOTE: there is a choice here between constantly creating new stack 2278 // slots and always reusing the same one. We currently always create 2279 // new ones, as reuse may inhibit scheduling. 2280 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2281 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2282 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2283 MachineFunction &MF = DAG.getMachineFunction(); 2284 int SSFI = 2285 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2286 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2287 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2288 Node->getOperand(0), StackSlot, 2289 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2290 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2291 Result, StackSlot, DAG.getSrcValue(NULL), 2292 ExtraVT); 2293 } else { 2294 assert(0 && "Unknown op"); 2295 } 2296 break; 2297 } 2298 break; 2299 } 2300 } 2301 2302 // Make sure that the generated code is itself legal. 2303 if (Result != Op) 2304 Result = LegalizeOp(Result); 2305 2306 // Note that LegalizeOp may be reentered even from single-use nodes, which 2307 // means that we always must cache transformed nodes. 2308 AddLegalizedOperand(Op, Result); 2309 return Result; 2310} 2311 2312/// PromoteOp - Given an operation that produces a value in an invalid type, 2313/// promote it to compute the value into a larger type. The produced value will 2314/// have the correct bits for the low portion of the register, but no guarantee 2315/// is made about the top bits: it may be zero, sign-extended, or garbage. 2316SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2317 MVT::ValueType VT = Op.getValueType(); 2318 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2319 assert(getTypeAction(VT) == Promote && 2320 "Caller should expand or legalize operands that are not promotable!"); 2321 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2322 "Cannot promote to smaller type!"); 2323 2324 SDOperand Tmp1, Tmp2, Tmp3; 2325 SDOperand Result; 2326 SDNode *Node = Op.Val; 2327 2328 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2329 if (I != PromotedNodes.end()) return I->second; 2330 2331 switch (Node->getOpcode()) { 2332 case ISD::CopyFromReg: 2333 assert(0 && "CopyFromReg must be legal!"); 2334 default: 2335 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2336 assert(0 && "Do not know how to promote this operator!"); 2337 abort(); 2338 case ISD::UNDEF: 2339 Result = DAG.getNode(ISD::UNDEF, NVT); 2340 break; 2341 case ISD::Constant: 2342 if (VT != MVT::i1) 2343 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2344 else 2345 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2346 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2347 break; 2348 case ISD::ConstantFP: 2349 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2350 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2351 break; 2352 2353 case ISD::SETCC: 2354 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2355 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2356 Node->getOperand(1), Node->getOperand(2)); 2357 break; 2358 2359 case ISD::TRUNCATE: 2360 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2361 case Legal: 2362 Result = LegalizeOp(Node->getOperand(0)); 2363 assert(Result.getValueType() >= NVT && 2364 "This truncation doesn't make sense!"); 2365 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2366 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2367 break; 2368 case Promote: 2369 // The truncation is not required, because we don't guarantee anything 2370 // about high bits anyway. 2371 Result = PromoteOp(Node->getOperand(0)); 2372 break; 2373 case Expand: 2374 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2375 // Truncate the low part of the expanded value to the result type 2376 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2377 } 2378 break; 2379 case ISD::SIGN_EXTEND: 2380 case ISD::ZERO_EXTEND: 2381 case ISD::ANY_EXTEND: 2382 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2383 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2384 case Legal: 2385 // Input is legal? Just do extend all the way to the larger type. 2386 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 2387 break; 2388 case Promote: 2389 // Promote the reg if it's smaller. 2390 Result = PromoteOp(Node->getOperand(0)); 2391 // The high bits are not guaranteed to be anything. Insert an extend. 2392 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2393 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2394 DAG.getValueType(Node->getOperand(0).getValueType())); 2395 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2396 Result = DAG.getZeroExtendInReg(Result, 2397 Node->getOperand(0).getValueType()); 2398 break; 2399 } 2400 break; 2401 case ISD::BIT_CONVERT: 2402 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2403 Result = PromoteOp(Result); 2404 break; 2405 2406 case ISD::FP_EXTEND: 2407 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2408 case ISD::FP_ROUND: 2409 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2410 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2411 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2412 case Legal: 2413 // Input is legal? Do an FP_ROUND_INREG. 2414 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 2415 DAG.getValueType(VT)); 2416 break; 2417 } 2418 break; 2419 2420 case ISD::SINT_TO_FP: 2421 case ISD::UINT_TO_FP: 2422 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2423 case Legal: 2424 // No extra round required here. 2425 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 2426 break; 2427 2428 case Promote: 2429 Result = PromoteOp(Node->getOperand(0)); 2430 if (Node->getOpcode() == ISD::SINT_TO_FP) 2431 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2432 Result, 2433 DAG.getValueType(Node->getOperand(0).getValueType())); 2434 else 2435 Result = DAG.getZeroExtendInReg(Result, 2436 Node->getOperand(0).getValueType()); 2437 // No extra round required here. 2438 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2439 break; 2440 case Expand: 2441 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2442 Node->getOperand(0)); 2443 // Round if we cannot tolerate excess precision. 2444 if (NoExcessFPPrecision) 2445 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2446 DAG.getValueType(VT)); 2447 break; 2448 } 2449 break; 2450 2451 case ISD::SIGN_EXTEND_INREG: 2452 Result = PromoteOp(Node->getOperand(0)); 2453 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2454 Node->getOperand(1)); 2455 break; 2456 case ISD::FP_TO_SINT: 2457 case ISD::FP_TO_UINT: 2458 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2459 case Legal: 2460 Tmp1 = Node->getOperand(0); 2461 break; 2462 case Promote: 2463 // The input result is prerounded, so we don't have to do anything 2464 // special. 2465 Tmp1 = PromoteOp(Node->getOperand(0)); 2466 break; 2467 case Expand: 2468 assert(0 && "not implemented"); 2469 } 2470 // If we're promoting a UINT to a larger size, check to see if the new node 2471 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2472 // we can use that instead. This allows us to generate better code for 2473 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2474 // legal, such as PowerPC. 2475 if (Node->getOpcode() == ISD::FP_TO_UINT && 2476 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2477 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2478 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2479 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2480 } else { 2481 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2482 } 2483 break; 2484 2485 case ISD::FABS: 2486 case ISD::FNEG: 2487 Tmp1 = PromoteOp(Node->getOperand(0)); 2488 assert(Tmp1.getValueType() == NVT); 2489 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2490 // NOTE: we do not have to do any extra rounding here for 2491 // NoExcessFPPrecision, because we know the input will have the appropriate 2492 // precision, and these operations don't modify precision at all. 2493 break; 2494 2495 case ISD::FSQRT: 2496 case ISD::FSIN: 2497 case ISD::FCOS: 2498 Tmp1 = PromoteOp(Node->getOperand(0)); 2499 assert(Tmp1.getValueType() == NVT); 2500 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2501 if (NoExcessFPPrecision) 2502 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2503 DAG.getValueType(VT)); 2504 break; 2505 2506 case ISD::AND: 2507 case ISD::OR: 2508 case ISD::XOR: 2509 case ISD::ADD: 2510 case ISD::SUB: 2511 case ISD::MUL: 2512 // The input may have strange things in the top bits of the registers, but 2513 // these operations don't care. They may have weird bits going out, but 2514 // that too is okay if they are integer operations. 2515 Tmp1 = PromoteOp(Node->getOperand(0)); 2516 Tmp2 = PromoteOp(Node->getOperand(1)); 2517 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2518 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2519 break; 2520 case ISD::FADD: 2521 case ISD::FSUB: 2522 case ISD::FMUL: 2523 Tmp1 = PromoteOp(Node->getOperand(0)); 2524 Tmp2 = PromoteOp(Node->getOperand(1)); 2525 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2526 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2527 2528 // Floating point operations will give excess precision that we may not be 2529 // able to tolerate. If we DO allow excess precision, just leave it, 2530 // otherwise excise it. 2531 // FIXME: Why would we need to round FP ops more than integer ones? 2532 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 2533 if (NoExcessFPPrecision) 2534 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2535 DAG.getValueType(VT)); 2536 break; 2537 2538 case ISD::SDIV: 2539 case ISD::SREM: 2540 // These operators require that their input be sign extended. 2541 Tmp1 = PromoteOp(Node->getOperand(0)); 2542 Tmp2 = PromoteOp(Node->getOperand(1)); 2543 if (MVT::isInteger(NVT)) { 2544 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2545 DAG.getValueType(VT)); 2546 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 2547 DAG.getValueType(VT)); 2548 } 2549 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2550 2551 // Perform FP_ROUND: this is probably overly pessimistic. 2552 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2553 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2554 DAG.getValueType(VT)); 2555 break; 2556 case ISD::FDIV: 2557 case ISD::FREM: 2558 // These operators require that their input be fp extended. 2559 Tmp1 = PromoteOp(Node->getOperand(0)); 2560 Tmp2 = PromoteOp(Node->getOperand(1)); 2561 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2562 2563 // Perform FP_ROUND: this is probably overly pessimistic. 2564 if (NoExcessFPPrecision) 2565 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2566 DAG.getValueType(VT)); 2567 break; 2568 2569 case ISD::UDIV: 2570 case ISD::UREM: 2571 // These operators require that their input be zero extended. 2572 Tmp1 = PromoteOp(Node->getOperand(0)); 2573 Tmp2 = PromoteOp(Node->getOperand(1)); 2574 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 2575 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2576 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 2577 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2578 break; 2579 2580 case ISD::SHL: 2581 Tmp1 = PromoteOp(Node->getOperand(0)); 2582 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 2583 break; 2584 case ISD::SRA: 2585 // The input value must be properly sign extended. 2586 Tmp1 = PromoteOp(Node->getOperand(0)); 2587 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2588 DAG.getValueType(VT)); 2589 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 2590 break; 2591 case ISD::SRL: 2592 // The input value must be properly zero extended. 2593 Tmp1 = PromoteOp(Node->getOperand(0)); 2594 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2595 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 2596 break; 2597 2598 case ISD::VAARG: 2599 Tmp1 = Node->getOperand(0); // Get the chain. 2600 Tmp2 = Node->getOperand(1); // Get the pointer. 2601 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 2602 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 2603 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 2604 } else { 2605 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2606 Node->getOperand(2)); 2607 // Increment the pointer, VAList, to the next vaarg 2608 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2609 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2610 TLI.getPointerTy())); 2611 // Store the incremented VAList to the legalized pointer 2612 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2, 2613 Node->getOperand(2)); 2614 // Load the actual argument out of the pointer VAList 2615 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, 2616 DAG.getSrcValue(0), VT); 2617 } 2618 // Remember that we legalized the chain. 2619 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 2620 break; 2621 2622 case ISD::LOAD: 2623 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0), 2624 Node->getOperand(1), Node->getOperand(2), VT); 2625 // Remember that we legalized the chain. 2626 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 2627 break; 2628 case ISD::SEXTLOAD: 2629 case ISD::ZEXTLOAD: 2630 case ISD::EXTLOAD: 2631 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0), 2632 Node->getOperand(1), Node->getOperand(2), 2633 cast<VTSDNode>(Node->getOperand(3))->getVT()); 2634 // Remember that we legalized the chain. 2635 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 2636 break; 2637 case ISD::SELECT: 2638 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 2639 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 2640 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 2641 break; 2642 case ISD::SELECT_CC: 2643 Tmp2 = PromoteOp(Node->getOperand(2)); // True 2644 Tmp3 = PromoteOp(Node->getOperand(3)); // False 2645 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 2646 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 2647 break; 2648 case ISD::BSWAP: 2649 Tmp1 = Node->getOperand(0); 2650 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2651 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 2652 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 2653 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT), 2654 TLI.getShiftAmountTy())); 2655 break; 2656 case ISD::CTPOP: 2657 case ISD::CTTZ: 2658 case ISD::CTLZ: 2659 // Zero extend the argument 2660 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 2661 // Perform the larger operation, then subtract if needed. 2662 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2663 switch(Node->getOpcode()) { 2664 case ISD::CTPOP: 2665 Result = Tmp1; 2666 break; 2667 case ISD::CTTZ: 2668 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2669 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2670 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 2671 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2672 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1); 2673 break; 2674 case ISD::CTLZ: 2675 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2676 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2677 DAG.getConstant(getSizeInBits(NVT) - 2678 getSizeInBits(VT), NVT)); 2679 break; 2680 } 2681 break; 2682 } 2683 2684 assert(Result.Val && "Didn't set a result!"); 2685 2686 // Make sure the result is itself legal. 2687 Result = LegalizeOp(Result); 2688 2689 // Remember that we promoted this! 2690 AddPromotedOperand(Op, Result); 2691 return Result; 2692} 2693 2694/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 2695/// The resultant code need not be legal. Note that SrcOp is the input operand 2696/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 2697SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 2698 SDOperand SrcOp) { 2699 // Create the stack frame object. 2700 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2701 unsigned ByteSize = MVT::getSizeInBits(DestVT)/8; 2702 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize); 2703 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 2704 2705 // Emit a store to the stack slot. 2706 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 2707 SrcOp, FIPtr, DAG.getSrcValue(NULL)); 2708 // Result is a load from the stack slot. 2709 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0)); 2710} 2711 2712void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 2713 SDOperand Op, SDOperand Amt, 2714 SDOperand &Lo, SDOperand &Hi) { 2715 // Expand the subcomponents. 2716 SDOperand LHSL, LHSH; 2717 ExpandOp(Op, LHSL, LHSH); 2718 2719 std::vector<SDOperand> Ops; 2720 Ops.push_back(LHSL); 2721 Ops.push_back(LHSH); 2722 Ops.push_back(Amt); 2723 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2724 Lo = DAG.getNode(NodeOp, VTs, Ops); 2725 Hi = Lo.getValue(1); 2726} 2727 2728 2729/// ExpandShift - Try to find a clever way to expand this shift operation out to 2730/// smaller elements. If we can't find a way that is more efficient than a 2731/// libcall on this target, return false. Otherwise, return true with the 2732/// low-parts expanded into Lo and Hi. 2733bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 2734 SDOperand &Lo, SDOperand &Hi) { 2735 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 2736 "This is not a shift!"); 2737 2738 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 2739 SDOperand ShAmt = LegalizeOp(Amt); 2740 MVT::ValueType ShTy = ShAmt.getValueType(); 2741 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 2742 unsigned NVTBits = MVT::getSizeInBits(NVT); 2743 2744 // Handle the case when Amt is an immediate. Other cases are currently broken 2745 // and are disabled. 2746 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 2747 unsigned Cst = CN->getValue(); 2748 // Expand the incoming operand to be shifted, so that we have its parts 2749 SDOperand InL, InH; 2750 ExpandOp(Op, InL, InH); 2751 switch(Opc) { 2752 case ISD::SHL: 2753 if (Cst > VTBits) { 2754 Lo = DAG.getConstant(0, NVT); 2755 Hi = DAG.getConstant(0, NVT); 2756 } else if (Cst > NVTBits) { 2757 Lo = DAG.getConstant(0, NVT); 2758 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 2759 } else if (Cst == NVTBits) { 2760 Lo = DAG.getConstant(0, NVT); 2761 Hi = InL; 2762 } else { 2763 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 2764 Hi = DAG.getNode(ISD::OR, NVT, 2765 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 2766 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 2767 } 2768 return true; 2769 case ISD::SRL: 2770 if (Cst > VTBits) { 2771 Lo = DAG.getConstant(0, NVT); 2772 Hi = DAG.getConstant(0, NVT); 2773 } else if (Cst > NVTBits) { 2774 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 2775 Hi = DAG.getConstant(0, NVT); 2776 } else if (Cst == NVTBits) { 2777 Lo = InH; 2778 Hi = DAG.getConstant(0, NVT); 2779 } else { 2780 Lo = DAG.getNode(ISD::OR, NVT, 2781 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2782 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2783 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 2784 } 2785 return true; 2786 case ISD::SRA: 2787 if (Cst > VTBits) { 2788 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 2789 DAG.getConstant(NVTBits-1, ShTy)); 2790 } else if (Cst > NVTBits) { 2791 Lo = DAG.getNode(ISD::SRA, NVT, InH, 2792 DAG.getConstant(Cst-NVTBits, ShTy)); 2793 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2794 DAG.getConstant(NVTBits-1, ShTy)); 2795 } else if (Cst == NVTBits) { 2796 Lo = InH; 2797 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2798 DAG.getConstant(NVTBits-1, ShTy)); 2799 } else { 2800 Lo = DAG.getNode(ISD::OR, NVT, 2801 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2802 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2803 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 2804 } 2805 return true; 2806 } 2807 } 2808 return false; 2809} 2810 2811/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 2812/// NodeDepth) node that is an CallSeqStart operation and occurs later than 2813/// Found. 2814static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found, 2815 std::set<SDNode*> &Visited) { 2816 if (Node->getNodeDepth() <= Found->getNodeDepth() || 2817 !Visited.insert(Node).second) return; 2818 2819 // If we found an CALLSEQ_START, we already know this node occurs later 2820 // than the Found node. Just remember this node and return. 2821 if (Node->getOpcode() == ISD::CALLSEQ_START) { 2822 Found = Node; 2823 return; 2824 } 2825 2826 // Otherwise, scan the operands of Node to see if any of them is a call. 2827 assert(Node->getNumOperands() != 0 && 2828 "All leaves should have depth equal to the entry node!"); 2829 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 2830 FindLatestCallSeqStart(Node->getOperand(i).Val, Found, Visited); 2831 2832 // Tail recurse for the last iteration. 2833 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 2834 Found, Visited); 2835} 2836 2837 2838/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 2839/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 2840/// than Found. 2841static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 2842 std::set<SDNode*> &Visited) { 2843 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 2844 !Visited.insert(Node).second) return; 2845 2846 // If we found an CALLSEQ_END, we already know this node occurs earlier 2847 // than the Found node. Just remember this node and return. 2848 if (Node->getOpcode() == ISD::CALLSEQ_END) { 2849 Found = Node; 2850 return; 2851 } 2852 2853 // Otherwise, scan the operands of Node to see if any of them is a call. 2854 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 2855 if (UI == E) return; 2856 for (--E; UI != E; ++UI) 2857 FindEarliestCallSeqEnd(*UI, Found, Visited); 2858 2859 // Tail recurse for the last iteration. 2860 FindEarliestCallSeqEnd(*UI, Found, Visited); 2861} 2862 2863/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 2864/// find the CALLSEQ_END node that terminates the call sequence. 2865static SDNode *FindCallSeqEnd(SDNode *Node) { 2866 if (Node->getOpcode() == ISD::CALLSEQ_END) 2867 return Node; 2868 if (Node->use_empty()) 2869 return 0; // No CallSeqEnd 2870 2871 // The chain is usually at the end. 2872 SDOperand TheChain(Node, Node->getNumValues()-1); 2873 if (TheChain.getValueType() != MVT::Other) { 2874 // Sometimes it's at the beginning. 2875 TheChain = SDOperand(Node, 0); 2876 if (TheChain.getValueType() != MVT::Other) { 2877 // Otherwise, hunt for it. 2878 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 2879 if (Node->getValueType(i) == MVT::Other) { 2880 TheChain = SDOperand(Node, i); 2881 break; 2882 } 2883 2884 // Otherwise, we walked into a node without a chain. 2885 if (TheChain.getValueType() != MVT::Other) 2886 return 0; 2887 } 2888 } 2889 2890 for (SDNode::use_iterator UI = Node->use_begin(), 2891 E = Node->use_end(); UI != E; ++UI) { 2892 2893 // Make sure to only follow users of our token chain. 2894 SDNode *User = *UI; 2895 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 2896 if (User->getOperand(i) == TheChain) 2897 if (SDNode *Result = FindCallSeqEnd(User)) 2898 return Result; 2899 } 2900 return 0; 2901} 2902 2903/// FindCallSeqStart - Given a chained node that is part of a call sequence, 2904/// find the CALLSEQ_START node that initiates the call sequence. 2905static SDNode *FindCallSeqStart(SDNode *Node) { 2906 assert(Node && "Didn't find callseq_start for a call??"); 2907 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 2908 2909 assert(Node->getOperand(0).getValueType() == MVT::Other && 2910 "Node doesn't have a token chain argument!"); 2911 return FindCallSeqStart(Node->getOperand(0).Val); 2912} 2913 2914 2915/// FindInputOutputChains - If we are replacing an operation with a call we need 2916/// to find the call that occurs before and the call that occurs after it to 2917/// properly serialize the calls in the block. The returned operand is the 2918/// input chain value for the new call (e.g. the entry node or the previous 2919/// call), and OutChain is set to be the chain node to update to point to the 2920/// end of the call chain. 2921static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 2922 SDOperand Entry) { 2923 SDNode *LatestCallSeqStart = Entry.Val; 2924 SDNode *LatestCallSeqEnd = 0; 2925 std::set<SDNode*> Visited; 2926 FindLatestCallSeqStart(OpNode, LatestCallSeqStart, Visited); 2927 Visited.clear(); 2928 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 2929 2930 // It is possible that no ISD::CALLSEQ_START was found because there is no 2931 // previous call in the function. LatestCallStackDown may in that case be 2932 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 2933 // unless LatestCallStackDown is an CALLSEQ_START. 2934 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) { 2935 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 2936 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n"; 2937 } else { 2938 LatestCallSeqEnd = Entry.Val; 2939 } 2940 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 2941 2942 // Finally, find the first call that this must come before, first we find the 2943 // CallSeqEnd that ends the call. 2944 OutChain = 0; 2945 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 2946 Visited.clear(); 2947 2948 // If we found one, translate from the adj up to the callseq_start. 2949 if (OutChain) 2950 OutChain = FindCallSeqStart(OutChain); 2951 2952 return SDOperand(LatestCallSeqEnd, 0); 2953} 2954 2955/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 2956void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 2957 SDNode *OutChain) { 2958 // Nothing to splice it into? 2959 if (OutChain == 0) return; 2960 2961 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 2962 //OutChain->dump(); 2963 2964 // Form a token factor node merging the old inval and the new inval. 2965 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 2966 OutChain->getOperand(0)); 2967 // Change the node to refer to the new token. 2968 std::vector<SDOperand> Ops(OutChain->op_begin(), OutChain->op_end()); 2969 Ops[0] = InToken; 2970 SDOperand Res = DAG.UpdateNodeOperands(SDOperand(OutChain, 0), Ops); 2971 assert(Res.Val == OutChain && "Didn't update in place!"); 2972} 2973 2974 2975// ExpandLibCall - Expand a node into a call to a libcall. If the result value 2976// does not fit into a register, return the lo part and set the hi part to the 2977// by-reg argument. If it does fit into a single register, return the result 2978// and leave the Hi part unset. 2979SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 2980 SDOperand &Hi) { 2981 SDNode *OutChain; 2982 SDOperand InChain = FindInputOutputChains(Node, OutChain, 2983 DAG.getEntryNode()); 2984 if (InChain.Val == 0) 2985 InChain = DAG.getEntryNode(); 2986 2987 TargetLowering::ArgListTy Args; 2988 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2989 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 2990 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 2991 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 2992 } 2993 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 2994 2995 // Splice the libcall in wherever FindInputOutputChains tells us to. 2996 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 2997 std::pair<SDOperand,SDOperand> CallInfo = 2998 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 2999 Callee, Args, DAG); 3000 3001 SDOperand Result; 3002 switch (getTypeAction(CallInfo.first.getValueType())) { 3003 default: assert(0 && "Unknown thing"); 3004 case Legal: 3005 Result = CallInfo.first; 3006 break; 3007 case Expand: 3008 ExpandOp(CallInfo.first, Result, Hi); 3009 break; 3010 } 3011 3012 CallInfo.second = LegalizeOp(CallInfo.second); 3013 SpliceCallInto(CallInfo.second, OutChain); 3014 return Result; 3015} 3016 3017 3018/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 3019/// destination type is legal. 3020SDOperand SelectionDAGLegalize:: 3021ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 3022 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 3023 assert(getTypeAction(Source.getValueType()) == Expand && 3024 "This is not an expansion!"); 3025 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 3026 3027 if (!isSigned) { 3028 assert(Source.getValueType() == MVT::i64 && 3029 "This only works for 64-bit -> FP"); 3030 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 3031 // incoming integer is set. To handle this, we dynamically test to see if 3032 // it is set, and, if so, add a fudge factor. 3033 SDOperand Lo, Hi; 3034 ExpandOp(Source, Lo, Hi); 3035 3036 // If this is unsigned, and not supported, first perform the conversion to 3037 // signed, then adjust the result if the sign bit is set. 3038 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 3039 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 3040 3041 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 3042 DAG.getConstant(0, Hi.getValueType()), 3043 ISD::SETLT); 3044 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3045 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3046 SignSet, Four, Zero); 3047 uint64_t FF = 0x5f800000ULL; 3048 if (TLI.isLittleEndian()) FF <<= 32; 3049 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3050 3051 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3052 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3053 SDOperand FudgeInReg; 3054 if (DestTy == MVT::f32) 3055 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3056 DAG.getSrcValue(NULL)); 3057 else { 3058 assert(DestTy == MVT::f64 && "Unexpected conversion"); 3059 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 3060 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 3061 } 3062 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 3063 } 3064 3065 // Check to see if the target has a custom way to lower this. If so, use it. 3066 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 3067 default: assert(0 && "This action not implemented for this operation!"); 3068 case TargetLowering::Legal: 3069 case TargetLowering::Expand: 3070 break; // This case is handled below. 3071 case TargetLowering::Custom: { 3072 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 3073 Source), DAG); 3074 if (NV.Val) 3075 return LegalizeOp(NV); 3076 break; // The target decided this was legal after all 3077 } 3078 } 3079 3080 // Expand the source, then glue it back together for the call. We must expand 3081 // the source in case it is shared (this pass of legalize must traverse it). 3082 SDOperand SrcLo, SrcHi; 3083 ExpandOp(Source, SrcLo, SrcHi); 3084 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3085 3086 SDNode *OutChain = 0; 3087 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 3088 DAG.getEntryNode()); 3089 const char *FnName = 0; 3090 if (DestTy == MVT::f32) 3091 FnName = "__floatdisf"; 3092 else { 3093 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3094 FnName = "__floatdidf"; 3095 } 3096 3097 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 3098 3099 TargetLowering::ArgListTy Args; 3100 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 3101 3102 Args.push_back(std::make_pair(Source, ArgTy)); 3103 3104 // We don't care about token chains for libcalls. We just use the entry 3105 // node as our input and ignore the output chain. This allows us to place 3106 // calls wherever we need them to satisfy data dependences. 3107 const Type *RetTy = MVT::getTypeForValueType(DestTy); 3108 3109 std::pair<SDOperand,SDOperand> CallResult = 3110 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 3111 Callee, Args, DAG); 3112 3113 SpliceCallInto(CallResult.second, OutChain); 3114 return CallResult.first; 3115} 3116 3117/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 3118/// INT_TO_FP operation of the specified operand when the target requests that 3119/// we expand it. At this point, we know that the result and operand types are 3120/// legal for the target. 3121SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 3122 SDOperand Op0, 3123 MVT::ValueType DestVT) { 3124 if (Op0.getValueType() == MVT::i32) { 3125 // simple 32-bit [signed|unsigned] integer to float/double expansion 3126 3127 // get the stack frame index of a 8 byte buffer 3128 MachineFunction &MF = DAG.getMachineFunction(); 3129 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 3130 // get address of 8 byte buffer 3131 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3132 // word offset constant for Hi/Lo address computation 3133 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 3134 // set up Hi and Lo (into buffer) address based on endian 3135 SDOperand Hi, Lo; 3136 if (TLI.isLittleEndian()) { 3137 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 3138 Lo = StackSlot; 3139 } else { 3140 Hi = StackSlot; 3141 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 3142 } 3143 // if signed map to unsigned space 3144 SDOperand Op0Mapped; 3145 if (isSigned) { 3146 // constant used to invert sign bit (signed to unsigned mapping) 3147 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 3148 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 3149 } else { 3150 Op0Mapped = Op0; 3151 } 3152 // store the lo of the constructed double - based on integer input 3153 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3154 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 3155 // initial hi portion of constructed double 3156 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 3157 // store the hi of the constructed double - biased exponent 3158 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 3159 InitialHi, Hi, DAG.getSrcValue(NULL)); 3160 // load the constructed double 3161 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 3162 DAG.getSrcValue(NULL)); 3163 // FP constant to bias correct the final result 3164 SDOperand Bias = DAG.getConstantFP(isSigned ? 3165 BitsToDouble(0x4330000080000000ULL) 3166 : BitsToDouble(0x4330000000000000ULL), 3167 MVT::f64); 3168 // subtract the bias 3169 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 3170 // final result 3171 SDOperand Result; 3172 // handle final rounding 3173 if (DestVT == MVT::f64) { 3174 // do nothing 3175 Result = Sub; 3176 } else { 3177 // if f32 then cast to f32 3178 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 3179 } 3180 return Result; 3181 } 3182 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 3183 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 3184 3185 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 3186 DAG.getConstant(0, Op0.getValueType()), 3187 ISD::SETLT); 3188 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3189 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3190 SignSet, Four, Zero); 3191 3192 // If the sign bit of the integer is set, the large number will be treated 3193 // as a negative number. To counteract this, the dynamic code adds an 3194 // offset depending on the data type. 3195 uint64_t FF; 3196 switch (Op0.getValueType()) { 3197 default: assert(0 && "Unsupported integer type!"); 3198 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 3199 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 3200 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 3201 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 3202 } 3203 if (TLI.isLittleEndian()) FF <<= 32; 3204 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3205 3206 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3207 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3208 SDOperand FudgeInReg; 3209 if (DestVT == MVT::f32) 3210 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3211 DAG.getSrcValue(NULL)); 3212 else { 3213 assert(DestVT == MVT::f64 && "Unexpected conversion"); 3214 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 3215 DAG.getEntryNode(), CPIdx, 3216 DAG.getSrcValue(NULL), MVT::f32)); 3217 } 3218 3219 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 3220} 3221 3222/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 3223/// *INT_TO_FP operation of the specified operand when the target requests that 3224/// we promote it. At this point, we know that the result and operand types are 3225/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 3226/// operation that takes a larger input. 3227SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 3228 MVT::ValueType DestVT, 3229 bool isSigned) { 3230 // First step, figure out the appropriate *INT_TO_FP operation to use. 3231 MVT::ValueType NewInTy = LegalOp.getValueType(); 3232 3233 unsigned OpToUse = 0; 3234 3235 // Scan for the appropriate larger type to use. 3236 while (1) { 3237 NewInTy = (MVT::ValueType)(NewInTy+1); 3238 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 3239 3240 // If the target supports SINT_TO_FP of this type, use it. 3241 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 3242 default: break; 3243 case TargetLowering::Legal: 3244 if (!TLI.isTypeLegal(NewInTy)) 3245 break; // Can't use this datatype. 3246 // FALL THROUGH. 3247 case TargetLowering::Custom: 3248 OpToUse = ISD::SINT_TO_FP; 3249 break; 3250 } 3251 if (OpToUse) break; 3252 if (isSigned) continue; 3253 3254 // If the target supports UINT_TO_FP of this type, use it. 3255 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 3256 default: break; 3257 case TargetLowering::Legal: 3258 if (!TLI.isTypeLegal(NewInTy)) 3259 break; // Can't use this datatype. 3260 // FALL THROUGH. 3261 case TargetLowering::Custom: 3262 OpToUse = ISD::UINT_TO_FP; 3263 break; 3264 } 3265 if (OpToUse) break; 3266 3267 // Otherwise, try a larger type. 3268 } 3269 3270 // Okay, we found the operation and type to use. Zero extend our input to the 3271 // desired type then run the operation on it. 3272 return DAG.getNode(OpToUse, DestVT, 3273 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 3274 NewInTy, LegalOp)); 3275} 3276 3277/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 3278/// FP_TO_*INT operation of the specified operand when the target requests that 3279/// we promote it. At this point, we know that the result and operand types are 3280/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 3281/// operation that returns a larger result. 3282SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 3283 MVT::ValueType DestVT, 3284 bool isSigned) { 3285 // First step, figure out the appropriate FP_TO*INT operation to use. 3286 MVT::ValueType NewOutTy = DestVT; 3287 3288 unsigned OpToUse = 0; 3289 3290 // Scan for the appropriate larger type to use. 3291 while (1) { 3292 NewOutTy = (MVT::ValueType)(NewOutTy+1); 3293 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 3294 3295 // If the target supports FP_TO_SINT returning this type, use it. 3296 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 3297 default: break; 3298 case TargetLowering::Legal: 3299 if (!TLI.isTypeLegal(NewOutTy)) 3300 break; // Can't use this datatype. 3301 // FALL THROUGH. 3302 case TargetLowering::Custom: 3303 OpToUse = ISD::FP_TO_SINT; 3304 break; 3305 } 3306 if (OpToUse) break; 3307 3308 // If the target supports FP_TO_UINT of this type, use it. 3309 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 3310 default: break; 3311 case TargetLowering::Legal: 3312 if (!TLI.isTypeLegal(NewOutTy)) 3313 break; // Can't use this datatype. 3314 // FALL THROUGH. 3315 case TargetLowering::Custom: 3316 OpToUse = ISD::FP_TO_UINT; 3317 break; 3318 } 3319 if (OpToUse) break; 3320 3321 // Otherwise, try a larger type. 3322 } 3323 3324 // Okay, we found the operation and type to use. Truncate the result of the 3325 // extended FP_TO_*INT operation to the desired size. 3326 return DAG.getNode(ISD::TRUNCATE, DestVT, 3327 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 3328} 3329 3330/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 3331/// 3332SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 3333 MVT::ValueType VT = Op.getValueType(); 3334 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 3335 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 3336 switch (VT) { 3337 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 3338 case MVT::i16: 3339 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 3340 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 3341 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 3342 case MVT::i32: 3343 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 3344 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 3345 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 3346 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 3347 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 3348 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 3349 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 3350 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 3351 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 3352 case MVT::i64: 3353 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 3354 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 3355 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 3356 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 3357 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 3358 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 3359 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 3360 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 3361 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 3362 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 3363 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 3364 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 3365 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 3366 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 3367 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 3368 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 3369 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 3370 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 3371 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 3372 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 3373 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 3374 } 3375} 3376 3377/// ExpandBitCount - Expand the specified bitcount instruction into operations. 3378/// 3379SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 3380 switch (Opc) { 3381 default: assert(0 && "Cannot expand this yet!"); 3382 case ISD::CTPOP: { 3383 static const uint64_t mask[6] = { 3384 0x5555555555555555ULL, 0x3333333333333333ULL, 3385 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 3386 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 3387 }; 3388 MVT::ValueType VT = Op.getValueType(); 3389 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 3390 unsigned len = getSizeInBits(VT); 3391 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 3392 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 3393 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 3394 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 3395 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 3396 DAG.getNode(ISD::AND, VT, 3397 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 3398 } 3399 return Op; 3400 } 3401 case ISD::CTLZ: { 3402 // for now, we do this: 3403 // x = x | (x >> 1); 3404 // x = x | (x >> 2); 3405 // ... 3406 // x = x | (x >>16); 3407 // x = x | (x >>32); // for 64-bit input 3408 // return popcount(~x); 3409 // 3410 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 3411 MVT::ValueType VT = Op.getValueType(); 3412 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 3413 unsigned len = getSizeInBits(VT); 3414 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 3415 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 3416 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 3417 } 3418 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 3419 return DAG.getNode(ISD::CTPOP, VT, Op); 3420 } 3421 case ISD::CTTZ: { 3422 // for now, we use: { return popcount(~x & (x - 1)); } 3423 // unless the target has ctlz but not ctpop, in which case we use: 3424 // { return 32 - nlz(~x & (x-1)); } 3425 // see also http://www.hackersdelight.org/HDcode/ntz.cc 3426 MVT::ValueType VT = Op.getValueType(); 3427 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 3428 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 3429 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 3430 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 3431 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 3432 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 3433 TLI.isOperationLegal(ISD::CTLZ, VT)) 3434 return DAG.getNode(ISD::SUB, VT, 3435 DAG.getConstant(getSizeInBits(VT), VT), 3436 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 3437 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 3438 } 3439 } 3440} 3441 3442 3443/// ExpandOp - Expand the specified SDOperand into its two component pieces 3444/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 3445/// LegalizeNodes map is filled in for any results that are not expanded, the 3446/// ExpandedNodes map is filled in for any results that are expanded, and the 3447/// Lo/Hi values are returned. 3448void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 3449 MVT::ValueType VT = Op.getValueType(); 3450 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3451 SDNode *Node = Op.Val; 3452 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 3453 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 3454 "Cannot expand FP values!"); 3455 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 3456 "Cannot expand to FP value or to larger int value!"); 3457 3458 // See if we already expanded it. 3459 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 3460 = ExpandedNodes.find(Op); 3461 if (I != ExpandedNodes.end()) { 3462 Lo = I->second.first; 3463 Hi = I->second.second; 3464 return; 3465 } 3466 3467 switch (Node->getOpcode()) { 3468 case ISD::CopyFromReg: 3469 assert(0 && "CopyFromReg must be legal!"); 3470 default: 3471 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 3472 assert(0 && "Do not know how to expand this operator!"); 3473 abort(); 3474 case ISD::UNDEF: 3475 Lo = DAG.getNode(ISD::UNDEF, NVT); 3476 Hi = DAG.getNode(ISD::UNDEF, NVT); 3477 break; 3478 case ISD::Constant: { 3479 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 3480 Lo = DAG.getConstant(Cst, NVT); 3481 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 3482 break; 3483 } 3484 case ISD::ConstantVec: { 3485 unsigned NumElements = Node->getNumOperands(); 3486 // If we only have two elements left in the constant vector, just break it 3487 // apart into the two scalar constants it contains. Otherwise, bisect the 3488 // ConstantVec, and return each half as a new ConstantVec. 3489 // FIXME: this is hard coded as big endian, it may have to change to support 3490 // SSE and Alpha MVI 3491 if (NumElements == 2) { 3492 Hi = Node->getOperand(0); 3493 Lo = Node->getOperand(1); 3494 } else { 3495 NumElements /= 2; 3496 std::vector<SDOperand> LoOps, HiOps; 3497 for (unsigned I = 0, E = NumElements; I < E; ++I) { 3498 HiOps.push_back(Node->getOperand(I)); 3499 LoOps.push_back(Node->getOperand(I+NumElements)); 3500 } 3501 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps); 3502 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps); 3503 } 3504 break; 3505 } 3506 3507 case ISD::BUILD_PAIR: 3508 // Return the operands. 3509 Lo = Node->getOperand(0); 3510 Hi = Node->getOperand(1); 3511 break; 3512 3513 case ISD::SIGN_EXTEND_INREG: 3514 ExpandOp(Node->getOperand(0), Lo, Hi); 3515 // Sign extend the lo-part. 3516 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 3517 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 3518 TLI.getShiftAmountTy())); 3519 // sext_inreg the low part if needed. 3520 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 3521 break; 3522 3523 case ISD::BSWAP: { 3524 ExpandOp(Node->getOperand(0), Lo, Hi); 3525 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 3526 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 3527 Lo = TempLo; 3528 break; 3529 } 3530 3531 case ISD::CTPOP: 3532 ExpandOp(Node->getOperand(0), Lo, Hi); 3533 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 3534 DAG.getNode(ISD::CTPOP, NVT, Lo), 3535 DAG.getNode(ISD::CTPOP, NVT, Hi)); 3536 Hi = DAG.getConstant(0, NVT); 3537 break; 3538 3539 case ISD::CTLZ: { 3540 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 3541 ExpandOp(Node->getOperand(0), Lo, Hi); 3542 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3543 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 3544 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 3545 ISD::SETNE); 3546 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 3547 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 3548 3549 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 3550 Hi = DAG.getConstant(0, NVT); 3551 break; 3552 } 3553 3554 case ISD::CTTZ: { 3555 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 3556 ExpandOp(Node->getOperand(0), Lo, Hi); 3557 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3558 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 3559 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 3560 ISD::SETNE); 3561 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 3562 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 3563 3564 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 3565 Hi = DAG.getConstant(0, NVT); 3566 break; 3567 } 3568 3569 case ISD::VAARG: { 3570 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 3571 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 3572 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 3573 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 3574 3575 // Remember that we legalized the chain. 3576 Hi = LegalizeOp(Hi); 3577 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 3578 if (!TLI.isLittleEndian()) 3579 std::swap(Lo, Hi); 3580 break; 3581 } 3582 3583 case ISD::LOAD: { 3584 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 3585 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 3586 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3587 3588 // Increment the pointer to the other half. 3589 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 3590 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3591 getIntPtrConstant(IncrementSize)); 3592 // FIXME: This creates a bogus srcvalue! 3593 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3594 3595 // Build a factor node to remember that this load is independent of the 3596 // other one. 3597 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3598 Hi.getValue(1)); 3599 3600 // Remember that we legalized the chain. 3601 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 3602 if (!TLI.isLittleEndian()) 3603 std::swap(Lo, Hi); 3604 break; 3605 } 3606 case ISD::VLOAD: { 3607 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 3608 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 3609 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3610 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3611 3612 // If we only have two elements, turn into a pair of scalar loads. 3613 // FIXME: handle case where a vector of two elements is fine, such as 3614 // 2 x double on SSE2. 3615 if (NumElements == 2) { 3616 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3617 // Increment the pointer to the other half. 3618 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8; 3619 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3620 getIntPtrConstant(IncrementSize)); 3621 // FIXME: This creates a bogus srcvalue! 3622 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3623 } else { 3624 NumElements /= 2; // Split the vector in half 3625 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3626 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8; 3627 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3628 getIntPtrConstant(IncrementSize)); 3629 // FIXME: This creates a bogus srcvalue! 3630 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3631 } 3632 3633 // Build a factor node to remember that this load is independent of the 3634 // other one. 3635 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3636 Hi.getValue(1)); 3637 3638 // Remember that we legalized the chain. 3639 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 3640 if (!TLI.isLittleEndian()) 3641 std::swap(Lo, Hi); 3642 break; 3643 } 3644 case ISD::VADD: 3645 case ISD::VSUB: 3646 case ISD::VMUL: { 3647 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3648 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3649 SDOperand LL, LH, RL, RH; 3650 3651 ExpandOp(Node->getOperand(0), LL, LH); 3652 ExpandOp(Node->getOperand(1), RL, RH); 3653 3654 // If we only have two elements, turn into a pair of scalar loads. 3655 // FIXME: handle case where a vector of two elements is fine, such as 3656 // 2 x double on SSE2. 3657 if (NumElements == 2) { 3658 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT); 3659 Lo = DAG.getNode(Opc, EVT, LL, RL); 3660 Hi = DAG.getNode(Opc, EVT, LH, RH); 3661 } else { 3662 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2), 3663 LL.getOperand(3)); 3664 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2), 3665 LH.getOperand(3)); 3666 } 3667 break; 3668 } 3669 case ISD::AND: 3670 case ISD::OR: 3671 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 3672 SDOperand LL, LH, RL, RH; 3673 ExpandOp(Node->getOperand(0), LL, LH); 3674 ExpandOp(Node->getOperand(1), RL, RH); 3675 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 3676 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 3677 break; 3678 } 3679 case ISD::SELECT: { 3680 SDOperand LL, LH, RL, RH; 3681 ExpandOp(Node->getOperand(1), LL, LH); 3682 ExpandOp(Node->getOperand(2), RL, RH); 3683 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 3684 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 3685 break; 3686 } 3687 case ISD::SELECT_CC: { 3688 SDOperand TL, TH, FL, FH; 3689 ExpandOp(Node->getOperand(2), TL, TH); 3690 ExpandOp(Node->getOperand(3), FL, FH); 3691 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3692 Node->getOperand(1), TL, FL, Node->getOperand(4)); 3693 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3694 Node->getOperand(1), TH, FH, Node->getOperand(4)); 3695 break; 3696 } 3697 case ISD::SEXTLOAD: { 3698 SDOperand Chain = Node->getOperand(0); 3699 SDOperand Ptr = Node->getOperand(1); 3700 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3701 3702 if (EVT == NVT) 3703 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3704 else 3705 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3706 EVT); 3707 3708 // Remember that we legalized the chain. 3709 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 3710 3711 // The high part is obtained by SRA'ing all but one of the bits of the lo 3712 // part. 3713 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3714 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3715 TLI.getShiftAmountTy())); 3716 break; 3717 } 3718 case ISD::ZEXTLOAD: { 3719 SDOperand Chain = Node->getOperand(0); 3720 SDOperand Ptr = Node->getOperand(1); 3721 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3722 3723 if (EVT == NVT) 3724 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3725 else 3726 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3727 EVT); 3728 3729 // Remember that we legalized the chain. 3730 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 3731 3732 // The high part is just a zero. 3733 Hi = DAG.getConstant(0, NVT); 3734 break; 3735 } 3736 case ISD::EXTLOAD: { 3737 SDOperand Chain = Node->getOperand(0); 3738 SDOperand Ptr = Node->getOperand(1); 3739 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3740 3741 if (EVT == NVT) 3742 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3743 else 3744 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3745 EVT); 3746 3747 // Remember that we legalized the chain. 3748 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 3749 3750 // The high part is undefined. 3751 Hi = DAG.getNode(ISD::UNDEF, NVT); 3752 break; 3753 } 3754 case ISD::ANY_EXTEND: 3755 // The low part is any extension of the input (which degenerates to a copy). 3756 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 3757 // The high part is undefined. 3758 Hi = DAG.getNode(ISD::UNDEF, NVT); 3759 break; 3760 case ISD::SIGN_EXTEND: { 3761 // The low part is just a sign extension of the input (which degenerates to 3762 // a copy). 3763 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 3764 3765 // The high part is obtained by SRA'ing all but one of the bits of the lo 3766 // part. 3767 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3768 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 3769 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 3770 break; 3771 } 3772 case ISD::ZERO_EXTEND: 3773 // The low part is just a zero extension of the input (which degenerates to 3774 // a copy). 3775 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 3776 3777 // The high part is just a zero. 3778 Hi = DAG.getConstant(0, NVT); 3779 break; 3780 3781 case ISD::BIT_CONVERT: { 3782 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0), 3783 Node->getOperand(0)); 3784 ExpandOp(Tmp, Lo, Hi); 3785 break; 3786 } 3787 3788 case ISD::READCYCLECOUNTER: 3789 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 3790 TargetLowering::Custom && 3791 "Must custom expand ReadCycleCounter"); 3792 Lo = TLI.LowerOperation(Op, DAG); 3793 assert(Lo.Val && "Node must be custom expanded!"); 3794 Hi = Lo.getValue(1); 3795 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 3796 LegalizeOp(Lo.getValue(2))); 3797 break; 3798 3799 // These operators cannot be expanded directly, emit them as calls to 3800 // library functions. 3801 case ISD::FP_TO_SINT: 3802 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 3803 SDOperand Op; 3804 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3805 case Expand: assert(0 && "cannot expand FP!"); 3806 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3807 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 3808 } 3809 3810 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 3811 3812 // Now that the custom expander is done, expand the result, which is still 3813 // VT. 3814 if (Op.Val) { 3815 ExpandOp(Op, Lo, Hi); 3816 break; 3817 } 3818 } 3819 3820 if (Node->getOperand(0).getValueType() == MVT::f32) 3821 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 3822 else 3823 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 3824 break; 3825 3826 case ISD::FP_TO_UINT: 3827 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 3828 SDOperand Op; 3829 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3830 case Expand: assert(0 && "cannot expand FP!"); 3831 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3832 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 3833 } 3834 3835 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 3836 3837 // Now that the custom expander is done, expand the result. 3838 if (Op.Val) { 3839 ExpandOp(Op, Lo, Hi); 3840 break; 3841 } 3842 } 3843 3844 if (Node->getOperand(0).getValueType() == MVT::f32) 3845 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 3846 else 3847 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 3848 break; 3849 3850 case ISD::SHL: { 3851 // If the target wants custom lowering, do so. 3852 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 3853 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 3854 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 3855 Op = TLI.LowerOperation(Op, DAG); 3856 if (Op.Val) { 3857 // Now that the custom expander is done, expand the result, which is 3858 // still VT. 3859 ExpandOp(Op, Lo, Hi); 3860 break; 3861 } 3862 } 3863 3864 // If we can emit an efficient shift operation, do so now. 3865 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 3866 break; 3867 3868 // If this target supports SHL_PARTS, use it. 3869 TargetLowering::LegalizeAction Action = 3870 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 3871 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 3872 Action == TargetLowering::Custom) { 3873 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 3874 break; 3875 } 3876 3877 // Otherwise, emit a libcall. 3878 Lo = ExpandLibCall("__ashldi3", Node, Hi); 3879 break; 3880 } 3881 3882 case ISD::SRA: { 3883 // If the target wants custom lowering, do so. 3884 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 3885 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 3886 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 3887 Op = TLI.LowerOperation(Op, DAG); 3888 if (Op.Val) { 3889 // Now that the custom expander is done, expand the result, which is 3890 // still VT. 3891 ExpandOp(Op, Lo, Hi); 3892 break; 3893 } 3894 } 3895 3896 // If we can emit an efficient shift operation, do so now. 3897 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 3898 break; 3899 3900 // If this target supports SRA_PARTS, use it. 3901 TargetLowering::LegalizeAction Action = 3902 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 3903 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 3904 Action == TargetLowering::Custom) { 3905 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 3906 break; 3907 } 3908 3909 // Otherwise, emit a libcall. 3910 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 3911 break; 3912 } 3913 3914 case ISD::SRL: { 3915 // If the target wants custom lowering, do so. 3916 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 3917 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 3918 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 3919 Op = TLI.LowerOperation(Op, DAG); 3920 if (Op.Val) { 3921 // Now that the custom expander is done, expand the result, which is 3922 // still VT. 3923 ExpandOp(Op, Lo, Hi); 3924 break; 3925 } 3926 } 3927 3928 // If we can emit an efficient shift operation, do so now. 3929 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 3930 break; 3931 3932 // If this target supports SRL_PARTS, use it. 3933 TargetLowering::LegalizeAction Action = 3934 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 3935 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 3936 Action == TargetLowering::Custom) { 3937 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 3938 break; 3939 } 3940 3941 // Otherwise, emit a libcall. 3942 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 3943 break; 3944 } 3945 3946 case ISD::ADD: 3947 case ISD::SUB: { 3948 // If the target wants to custom expand this, let them. 3949 if (TLI.getOperationAction(Node->getOpcode(), VT) == 3950 TargetLowering::Custom) { 3951 Op = TLI.LowerOperation(Op, DAG); 3952 if (Op.Val) { 3953 ExpandOp(Op, Lo, Hi); 3954 break; 3955 } 3956 } 3957 3958 // Expand the subcomponents. 3959 SDOperand LHSL, LHSH, RHSL, RHSH; 3960 ExpandOp(Node->getOperand(0), LHSL, LHSH); 3961 ExpandOp(Node->getOperand(1), RHSL, RHSH); 3962 3963 std::vector<SDOperand> Ops; 3964 Ops.push_back(LHSL); 3965 Ops.push_back(LHSH); 3966 Ops.push_back(RHSL); 3967 Ops.push_back(RHSH); 3968 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 3969 unsigned Opc = 3970 Node->getOpcode() == ISD::ADD ? ISD::ADD_PARTS : ISD::SUB_PARTS; 3971 Lo = DAG.getNode(Opc, VTs, Ops); 3972 Hi = Lo.getValue(1); 3973 break; 3974 } 3975 case ISD::MUL: { 3976 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 3977 SDOperand LL, LH, RL, RH; 3978 ExpandOp(Node->getOperand(0), LL, LH); 3979 ExpandOp(Node->getOperand(1), RL, RH); 3980 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 3981 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 3982 // extended the sign bit of the low half through the upper half, and if so 3983 // emit a MULHS instead of the alternate sequence that is valid for any 3984 // i64 x i64 multiply. 3985 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 3986 // is RH an extension of the sign bit of RL? 3987 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 3988 RH.getOperand(1).getOpcode() == ISD::Constant && 3989 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 3990 // is LH an extension of the sign bit of LL? 3991 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 3992 LH.getOperand(1).getOpcode() == ISD::Constant && 3993 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 3994 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 3995 } else { 3996 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 3997 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 3998 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 3999 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 4000 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 4001 } 4002 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 4003 } else { 4004 Lo = ExpandLibCall("__muldi3" , Node, Hi); 4005 } 4006 break; 4007 } 4008 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 4009 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 4010 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 4011 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 4012 } 4013 4014 // Make sure the resultant values have been legalized themselves, unless this 4015 // is a type that requires multi-step expansion. 4016 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 4017 Lo = LegalizeOp(Lo); 4018 Hi = LegalizeOp(Hi); 4019 } 4020 4021 // Remember in a map if the values will be reused later. 4022 bool isNew = 4023 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 4024 assert(isNew && "Value already expanded?!?"); 4025} 4026 4027 4028// SelectionDAG::Legalize - This is the entry point for the file. 4029// 4030void SelectionDAG::Legalize() { 4031 /// run - This is the main entry point to this class. 4032 /// 4033 SelectionDAGLegalize(*this).LegalizeDAG(); 4034} 4035 4036