LegalizeDAG.cpp revision 6a648614e88586e85a36ceb5c1d3b84e4f55b458
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 /// LegalizeAction - This enum indicates what action we should take for each 45 /// value type the can occur in the program. 46 enum LegalizeAction { 47 Legal, // The target natively supports this value type. 48 Promote, // This should be promoted to the next larger type. 49 Expand, // This integer type should be broken into smaller pieces. 50 }; 51 52 /// ValueTypeActions - This is a bitvector that contains two bits for each 53 /// value type, where the two bits correspond to the LegalizeAction enum. 54 /// This can be queried with "getTypeAction(VT)". 55 unsigned long long ValueTypeActions; 56 57 /// NeedsAnotherIteration - This is set when we expand a large integer 58 /// operation into smaller integer operations, but the smaller operations are 59 /// not set. This occurs only rarely in practice, for targets that don't have 60 /// 32-bit or larger integer registers. 61 bool NeedsAnotherIteration; 62 63 /// LegalizedNodes - For nodes that are of legal width, and that have more 64 /// than one use, this map indicates what regularized operand to use. This 65 /// allows us to avoid legalizing the same thing more than once. 66 std::map<SDOperand, SDOperand> LegalizedNodes; 67 68 /// PromotedNodes - For nodes that are below legal width, and that have more 69 /// than one use, this map indicates what promoted value to use. This allows 70 /// us to avoid promoting the same thing more than once. 71 std::map<SDOperand, SDOperand> PromotedNodes; 72 73 /// ExpandedNodes - For nodes that need to be expanded, and which have more 74 /// than one use, this map indicates which which operands are the expanded 75 /// version of the input. This allows us to avoid expanding the same node 76 /// more than once. 77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 78 79 void AddLegalizedOperand(SDOperand From, SDOperand To) { 80 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second; 81 assert(isNew && "Got into the map somehow?"); 82 } 83 void AddPromotedOperand(SDOperand From, SDOperand To) { 84 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 85 assert(isNew && "Got into the map somehow?"); 86 } 87 88public: 89 90 SelectionDAGLegalize(SelectionDAG &DAG); 91 92 /// Run - While there is still lowering to do, perform a pass over the DAG. 93 /// Most regularization can be done in a single pass, but targets that require 94 /// large values to be split into registers multiple times (e.g. i64 -> 4x 95 /// i16) require iteration for these values (the first iteration will demote 96 /// to i32, the second will demote to i16). 97 void Run() { 98 do { 99 NeedsAnotherIteration = false; 100 LegalizeDAG(); 101 } while (NeedsAnotherIteration); 102 } 103 104 /// getTypeAction - Return how we should legalize values of this type, either 105 /// it is already legal or we need to expand it into multiple registers of 106 /// smaller integer type, or we need to promote it to a larger type. 107 LegalizeAction getTypeAction(MVT::ValueType VT) const { 108 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 109 } 110 111 /// isTypeLegal - Return true if this type is legal on this target. 112 /// 113 bool isTypeLegal(MVT::ValueType VT) const { 114 return getTypeAction(VT) == Legal; 115 } 116 117private: 118 void LegalizeDAG(); 119 120 SDOperand LegalizeOp(SDOperand O); 121 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 122 SDOperand PromoteOp(SDOperand O); 123 124 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 125 SDOperand &Hi); 126 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 127 SDOperand Source); 128 129 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 130 SDOperand LegalOp, 131 MVT::ValueType DestVT); 132 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 133 bool isSigned); 134 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 135 bool isSigned); 136 137 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 138 SDOperand &Lo, SDOperand &Hi); 139 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 140 SDOperand &Lo, SDOperand &Hi); 141 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 142 SDOperand &Lo, SDOperand &Hi); 143 144 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 145 146 SDOperand getIntPtrConstant(uint64_t Val) { 147 return DAG.getConstant(Val, TLI.getPointerTy()); 148 } 149}; 150} 151 152static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 153 switch (VecOp) { 154 default: assert(0 && "Don't know how to scalarize this opcode!"); 155 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 156 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 157 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 158 } 159} 160 161SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 162 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 163 ValueTypeActions(TLI.getValueTypeActions()) { 164 assert(MVT::LAST_VALUETYPE <= 32 && 165 "Too many value types for ValueTypeActions to hold!"); 166} 167 168/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 169/// INT_TO_FP operation of the specified operand when the target requests that 170/// we expand it. At this point, we know that the result and operand types are 171/// legal for the target. 172SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 173 SDOperand Op0, 174 MVT::ValueType DestVT) { 175 if (Op0.getValueType() == MVT::i32) { 176 // simple 32-bit [signed|unsigned] integer to float/double expansion 177 178 // get the stack frame index of a 8 byte buffer 179 MachineFunction &MF = DAG.getMachineFunction(); 180 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 181 // get address of 8 byte buffer 182 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 183 // word offset constant for Hi/Lo address computation 184 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 185 // set up Hi and Lo (into buffer) address based on endian 186 SDOperand Hi, Lo; 187 if (TLI.isLittleEndian()) { 188 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 189 Lo = StackSlot; 190 } else { 191 Hi = StackSlot; 192 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 193 } 194 // if signed map to unsigned space 195 SDOperand Op0Mapped; 196 if (isSigned) { 197 // constant used to invert sign bit (signed to unsigned mapping) 198 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 199 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 200 } else { 201 Op0Mapped = Op0; 202 } 203 // store the lo of the constructed double - based on integer input 204 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 205 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 206 // initial hi portion of constructed double 207 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 208 // store the hi of the constructed double - biased exponent 209 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 210 InitialHi, Hi, DAG.getSrcValue(NULL)); 211 // load the constructed double 212 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 213 DAG.getSrcValue(NULL)); 214 // FP constant to bias correct the final result 215 SDOperand Bias = DAG.getConstantFP(isSigned ? 216 BitsToDouble(0x4330000080000000ULL) 217 : BitsToDouble(0x4330000000000000ULL), 218 MVT::f64); 219 // subtract the bias 220 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 221 // final result 222 SDOperand Result; 223 // handle final rounding 224 if (DestVT == MVT::f64) { 225 // do nothing 226 Result = Sub; 227 } else { 228 // if f32 then cast to f32 229 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 230 } 231 NeedsAnotherIteration = true; 232 return Result; 233 } 234 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 235 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 236 237 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 238 DAG.getConstant(0, Op0.getValueType()), 239 ISD::SETLT); 240 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 241 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 242 SignSet, Four, Zero); 243 244 // If the sign bit of the integer is set, the large number will be treated 245 // as a negative number. To counteract this, the dynamic code adds an 246 // offset depending on the data type. 247 uint64_t FF; 248 switch (Op0.getValueType()) { 249 default: assert(0 && "Unsupported integer type!"); 250 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 251 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 252 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 253 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 254 } 255 if (TLI.isLittleEndian()) FF <<= 32; 256 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 257 258 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 259 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 260 SDOperand FudgeInReg; 261 if (DestVT == MVT::f32) 262 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 263 DAG.getSrcValue(NULL)); 264 else { 265 assert(DestVT == MVT::f64 && "Unexpected conversion"); 266 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 267 DAG.getEntryNode(), CPIdx, 268 DAG.getSrcValue(NULL), MVT::f32)); 269 } 270 271 NeedsAnotherIteration = true; 272 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 273} 274 275/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 276/// *INT_TO_FP operation of the specified operand when the target requests that 277/// we promote it. At this point, we know that the result and operand types are 278/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 279/// operation that takes a larger input. 280SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 281 MVT::ValueType DestVT, 282 bool isSigned) { 283 // First step, figure out the appropriate *INT_TO_FP operation to use. 284 MVT::ValueType NewInTy = LegalOp.getValueType(); 285 286 unsigned OpToUse = 0; 287 288 // Scan for the appropriate larger type to use. 289 while (1) { 290 NewInTy = (MVT::ValueType)(NewInTy+1); 291 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 292 293 // If the target supports SINT_TO_FP of this type, use it. 294 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 295 default: break; 296 case TargetLowering::Legal: 297 if (!TLI.isTypeLegal(NewInTy)) 298 break; // Can't use this datatype. 299 // FALL THROUGH. 300 case TargetLowering::Custom: 301 OpToUse = ISD::SINT_TO_FP; 302 break; 303 } 304 if (OpToUse) break; 305 if (isSigned) continue; 306 307 // If the target supports UINT_TO_FP of this type, use it. 308 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 309 default: break; 310 case TargetLowering::Legal: 311 if (!TLI.isTypeLegal(NewInTy)) 312 break; // Can't use this datatype. 313 // FALL THROUGH. 314 case TargetLowering::Custom: 315 OpToUse = ISD::UINT_TO_FP; 316 break; 317 } 318 if (OpToUse) break; 319 320 // Otherwise, try a larger type. 321 } 322 323 // Make sure to legalize any nodes we create here in the next pass. 324 NeedsAnotherIteration = true; 325 326 // Okay, we found the operation and type to use. Zero extend our input to the 327 // desired type then run the operation on it. 328 return DAG.getNode(OpToUse, DestVT, 329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 330 NewInTy, LegalOp)); 331} 332 333/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 334/// FP_TO_*INT operation of the specified operand when the target requests that 335/// we promote it. At this point, we know that the result and operand types are 336/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 337/// operation that returns a larger result. 338SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 339 MVT::ValueType DestVT, 340 bool isSigned) { 341 // First step, figure out the appropriate FP_TO*INT operation to use. 342 MVT::ValueType NewOutTy = DestVT; 343 344 unsigned OpToUse = 0; 345 346 // Scan for the appropriate larger type to use. 347 while (1) { 348 NewOutTy = (MVT::ValueType)(NewOutTy+1); 349 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 350 351 // If the target supports FP_TO_SINT returning this type, use it. 352 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 353 default: break; 354 case TargetLowering::Legal: 355 if (!TLI.isTypeLegal(NewOutTy)) 356 break; // Can't use this datatype. 357 // FALL THROUGH. 358 case TargetLowering::Custom: 359 OpToUse = ISD::FP_TO_SINT; 360 break; 361 } 362 if (OpToUse) break; 363 364 // If the target supports FP_TO_UINT of this type, use it. 365 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 366 default: break; 367 case TargetLowering::Legal: 368 if (!TLI.isTypeLegal(NewOutTy)) 369 break; // Can't use this datatype. 370 // FALL THROUGH. 371 case TargetLowering::Custom: 372 OpToUse = ISD::FP_TO_UINT; 373 break; 374 } 375 if (OpToUse) break; 376 377 // Otherwise, try a larger type. 378 } 379 380 // Make sure to legalize any nodes we create here in the next pass. 381 NeedsAnotherIteration = true; 382 383 // Okay, we found the operation and type to use. Truncate the result of the 384 // extended FP_TO_*INT operation to the desired size. 385 return DAG.getNode(ISD::TRUNCATE, DestVT, 386 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 387} 388 389/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 390/// not been visited yet and if all of its operands have already been visited. 391static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 392 std::map<SDNode*, unsigned> &Visited) { 393 if (++Visited[N] != N->getNumOperands()) 394 return; // Haven't visited all operands yet 395 396 Order.push_back(N); 397 398 if (N->hasOneUse()) { // Tail recurse in common case. 399 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 400 return; 401 } 402 403 // Now that we have N in, add anything that uses it if all of their operands 404 // are now done. 405 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 406 ComputeTopDownOrdering(*UI, Order, Visited); 407} 408 409 410void SelectionDAGLegalize::LegalizeDAG() { 411 // The legalize process is inherently a bottom-up recursive process (users 412 // legalize their uses before themselves). Given infinite stack space, we 413 // could just start legalizing on the root and traverse the whole graph. In 414 // practice however, this causes us to run out of stack space on large basic 415 // blocks. To avoid this problem, compute an ordering of the nodes where each 416 // node is only legalized after all of its operands are legalized. 417 std::map<SDNode*, unsigned> Visited; 418 std::vector<SDNode*> Order; 419 420 // Compute ordering from all of the leaves in the graphs, those (like the 421 // entry node) that have no operands. 422 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 423 E = DAG.allnodes_end(); I != E; ++I) { 424 if (I->getNumOperands() == 0) { 425 Visited[I] = 0 - 1U; 426 ComputeTopDownOrdering(I, Order, Visited); 427 } 428 } 429 430 assert(Order.size() == Visited.size() && 431 Order.size() == 432 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 433 "Error: DAG is cyclic!"); 434 Visited.clear(); 435 436 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 437 SDNode *N = Order[i]; 438 switch (getTypeAction(N->getValueType(0))) { 439 default: assert(0 && "Bad type action!"); 440 case Legal: 441 LegalizeOp(SDOperand(N, 0)); 442 break; 443 case Promote: 444 PromoteOp(SDOperand(N, 0)); 445 break; 446 case Expand: { 447 SDOperand X, Y; 448 ExpandOp(SDOperand(N, 0), X, Y); 449 break; 450 } 451 } 452 } 453 454 // Finally, it's possible the root changed. Get the new root. 455 SDOperand OldRoot = DAG.getRoot(); 456 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 457 DAG.setRoot(LegalizedNodes[OldRoot]); 458 459 ExpandedNodes.clear(); 460 LegalizedNodes.clear(); 461 PromotedNodes.clear(); 462 463 // Remove dead nodes now. 464 DAG.RemoveDeadNodes(OldRoot.Val); 465} 466 467SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 468 assert(isTypeLegal(Op.getValueType()) && 469 "Caller should expand or promote operands that are not legal!"); 470 SDNode *Node = Op.Val; 471 472 // If this operation defines any values that cannot be represented in a 473 // register on this target, make sure to expand or promote them. 474 if (Node->getNumValues() > 1) { 475 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 476 switch (getTypeAction(Node->getValueType(i))) { 477 case Legal: break; // Nothing to do. 478 case Expand: { 479 SDOperand T1, T2; 480 ExpandOp(Op.getValue(i), T1, T2); 481 assert(LegalizedNodes.count(Op) && 482 "Expansion didn't add legal operands!"); 483 return LegalizedNodes[Op]; 484 } 485 case Promote: 486 PromoteOp(Op.getValue(i)); 487 assert(LegalizedNodes.count(Op) && 488 "Expansion didn't add legal operands!"); 489 return LegalizedNodes[Op]; 490 } 491 } 492 493 // Note that LegalizeOp may be reentered even from single-use nodes, which 494 // means that we always must cache transformed nodes. 495 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 496 if (I != LegalizedNodes.end()) return I->second; 497 498 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 499 500 SDOperand Result = Op; 501 502 switch (Node->getOpcode()) { 503 default: 504 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 505 // If this is a target node, legalize it by legalizing the operands then 506 // passing it through. 507 std::vector<SDOperand> Ops; 508 bool Changed = false; 509 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 510 Ops.push_back(LegalizeOp(Node->getOperand(i))); 511 Changed = Changed || Node->getOperand(i) != Ops.back(); 512 } 513 if (Changed) 514 if (Node->getNumValues() == 1) 515 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 516 else { 517 std::vector<MVT::ValueType> VTs(Node->value_begin(), 518 Node->value_end()); 519 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 520 } 521 522 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 523 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 524 return Result.getValue(Op.ResNo); 525 } 526 // Otherwise this is an unhandled builtin node. splat. 527 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 528 assert(0 && "Do not know how to legalize this operator!"); 529 abort(); 530 case ISD::EntryToken: 531 case ISD::FrameIndex: 532 case ISD::TargetFrameIndex: 533 case ISD::Register: 534 case ISD::TargetConstant: 535 case ISD::GlobalAddress: 536 case ISD::TargetGlobalAddress: 537 case ISD::ExternalSymbol: 538 case ISD::ConstantPool: // Nothing to do. 539 case ISD::BasicBlock: 540 case ISD::CONDCODE: 541 case ISD::VALUETYPE: 542 case ISD::SRCVALUE: 543 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 544 default: assert(0 && "This action is not supported yet!"); 545 case TargetLowering::Custom: { 546 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 547 if (Tmp.Val) { 548 Result = LegalizeOp(Tmp); 549 break; 550 } 551 } // FALLTHROUGH if the target doesn't want to lower this op after all. 552 case TargetLowering::Legal: 553 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!"); 554 break; 555 } 556 break; 557 case ISD::AssertSext: 558 case ISD::AssertZext: 559 Tmp1 = LegalizeOp(Node->getOperand(0)); 560 if (Tmp1 != Node->getOperand(0)) 561 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 562 Node->getOperand(1)); 563 break; 564 case ISD::MERGE_VALUES: 565 return LegalizeOp(Node->getOperand(Op.ResNo)); 566 case ISD::CopyFromReg: 567 Tmp1 = LegalizeOp(Node->getOperand(0)); 568 if (Tmp1 != Node->getOperand(0)) 569 Result = DAG.getCopyFromReg(Tmp1, 570 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 571 Node->getValueType(0)); 572 else 573 Result = Op.getValue(0); 574 575 // Since CopyFromReg produces two values, make sure to remember that we 576 // legalized both of them. 577 AddLegalizedOperand(Op.getValue(0), Result); 578 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 579 return Result.getValue(Op.ResNo); 580 case ISD::ImplicitDef: 581 Tmp1 = LegalizeOp(Node->getOperand(0)); 582 if (Tmp1 != Node->getOperand(0)) 583 Result = DAG.getNode(ISD::ImplicitDef, MVT::Other, 584 Tmp1, Node->getOperand(1)); 585 break; 586 case ISD::UNDEF: { 587 MVT::ValueType VT = Op.getValueType(); 588 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 589 default: assert(0 && "This action is not supported yet!"); 590 case TargetLowering::Expand: 591 case TargetLowering::Promote: 592 if (MVT::isInteger(VT)) 593 Result = DAG.getConstant(0, VT); 594 else if (MVT::isFloatingPoint(VT)) 595 Result = DAG.getConstantFP(0, VT); 596 else 597 assert(0 && "Unknown value type!"); 598 break; 599 case TargetLowering::Legal: 600 break; 601 } 602 break; 603 } 604 case ISD::Constant: 605 // We know we don't need to expand constants here, constants only have one 606 // value and we check that it is fine above. 607 608 // FIXME: Maybe we should handle things like targets that don't support full 609 // 32-bit immediates? 610 break; 611 case ISD::ConstantFP: { 612 // Spill FP immediates to the constant pool if the target cannot directly 613 // codegen them. Targets often have some immediate values that can be 614 // efficiently generated into an FP register without a load. We explicitly 615 // leave these constants as ConstantFP nodes for the target to deal with. 616 617 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 618 619 // Check to see if this FP immediate is already legal. 620 bool isLegal = false; 621 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 622 E = TLI.legal_fpimm_end(); I != E; ++I) 623 if (CFP->isExactlyValue(*I)) { 624 isLegal = true; 625 break; 626 } 627 628 if (!isLegal) { 629 // Otherwise we need to spill the constant to memory. 630 bool Extend = false; 631 632 // If a FP immediate is precise when represented as a float, we put it 633 // into the constant pool as a float, even if it's is statically typed 634 // as a double. 635 MVT::ValueType VT = CFP->getValueType(0); 636 bool isDouble = VT == MVT::f64; 637 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 638 Type::FloatTy, CFP->getValue()); 639 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 640 // Only do this if the target has a native EXTLOAD instruction from 641 // f32. 642 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 643 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 644 VT = MVT::f32; 645 Extend = true; 646 } 647 648 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 649 if (Extend) { 650 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 651 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 652 } else { 653 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 654 DAG.getSrcValue(NULL)); 655 } 656 } 657 break; 658 } 659 case ISD::TokenFactor: 660 if (Node->getNumOperands() == 2) { 661 bool Changed = false; 662 SDOperand Op0 = LegalizeOp(Node->getOperand(0)); 663 SDOperand Op1 = LegalizeOp(Node->getOperand(1)); 664 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1)) 665 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1); 666 } else { 667 std::vector<SDOperand> Ops; 668 bool Changed = false; 669 // Legalize the operands. 670 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 671 SDOperand Op = Node->getOperand(i); 672 Ops.push_back(LegalizeOp(Op)); 673 Changed |= Ops[i] != Op; 674 } 675 if (Changed) 676 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 677 } 678 break; 679 680 case ISD::CALLSEQ_START: 681 case ISD::CALLSEQ_END: 682 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 683 // Do not try to legalize the target-specific arguments (#1+) 684 Tmp2 = Node->getOperand(0); 685 if (Tmp1 != Tmp2) 686 Node->setAdjCallChain(Tmp1); 687 688 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These 689 // nodes are treated specially and are mutated in place. This makes the dag 690 // legalization process more efficient and also makes libcall insertion 691 // easier. 692 break; 693 case ISD::DYNAMIC_STACKALLOC: 694 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 695 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 696 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 697 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 698 Tmp3 != Node->getOperand(2)) { 699 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 700 std::vector<SDOperand> Ops; 701 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 702 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 703 } else 704 Result = Op.getValue(0); 705 706 // Since this op produces two values, make sure to remember that we 707 // legalized both of them. 708 AddLegalizedOperand(SDOperand(Node, 0), Result); 709 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 710 return Result.getValue(Op.ResNo); 711 712 case ISD::TAILCALL: 713 case ISD::CALL: { 714 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 715 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 716 717 bool Changed = false; 718 std::vector<SDOperand> Ops; 719 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 720 Ops.push_back(LegalizeOp(Node->getOperand(i))); 721 Changed |= Ops.back() != Node->getOperand(i); 722 } 723 724 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 725 std::vector<MVT::ValueType> RetTyVTs; 726 RetTyVTs.reserve(Node->getNumValues()); 727 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 728 RetTyVTs.push_back(Node->getValueType(i)); 729 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 730 Node->getOpcode() == ISD::TAILCALL), 0); 731 } else { 732 Result = Result.getValue(0); 733 } 734 // Since calls produce multiple values, make sure to remember that we 735 // legalized all of them. 736 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 737 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 738 return Result.getValue(Op.ResNo); 739 } 740 case ISD::BR: 741 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 742 if (Tmp1 != Node->getOperand(0)) 743 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 744 break; 745 746 case ISD::BRCOND: 747 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 748 749 switch (getTypeAction(Node->getOperand(1).getValueType())) { 750 case Expand: assert(0 && "It's impossible to expand bools"); 751 case Legal: 752 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 753 break; 754 case Promote: 755 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 756 break; 757 } 758 759 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 760 default: assert(0 && "This action is not supported yet!"); 761 case TargetLowering::Expand: 762 // Expand brcond's setcc into its constituent parts and create a BR_CC 763 // Node. 764 if (Tmp2.getOpcode() == ISD::SETCC) { 765 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 766 Tmp2.getOperand(0), Tmp2.getOperand(1), 767 Node->getOperand(2)); 768 } else { 769 // Make sure the condition is either zero or one. It may have been 770 // promoted from something else. 771 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 772 773 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 774 DAG.getCondCode(ISD::SETNE), Tmp2, 775 DAG.getConstant(0, Tmp2.getValueType()), 776 Node->getOperand(2)); 777 } 778 break; 779 case TargetLowering::Legal: 780 // Basic block destination (Op#2) is always legal. 781 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 782 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 783 Node->getOperand(2)); 784 break; 785 } 786 break; 787 case ISD::BR_CC: 788 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 789 790 if (isTypeLegal(Node->getOperand(2).getValueType())) { 791 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 792 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 793 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 794 Tmp3 != Node->getOperand(3)) { 795 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 796 Tmp2, Tmp3, Node->getOperand(4)); 797 } 798 break; 799 } else { 800 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 801 Node->getOperand(2), // LHS 802 Node->getOperand(3), // RHS 803 Node->getOperand(1))); 804 // If we get a SETCC back from legalizing the SETCC node we just 805 // created, then use its LHS, RHS, and CC directly in creating a new 806 // node. Otherwise, select between the true and false value based on 807 // comparing the result of the legalized with zero. 808 if (Tmp2.getOpcode() == ISD::SETCC) { 809 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 810 Tmp2.getOperand(0), Tmp2.getOperand(1), 811 Node->getOperand(4)); 812 } else { 813 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 814 DAG.getCondCode(ISD::SETNE), 815 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 816 Node->getOperand(4)); 817 } 818 } 819 break; 820 case ISD::BRCONDTWOWAY: 821 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 822 switch (getTypeAction(Node->getOperand(1).getValueType())) { 823 case Expand: assert(0 && "It's impossible to expand bools"); 824 case Legal: 825 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 826 break; 827 case Promote: 828 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 829 break; 830 } 831 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 832 // pair. 833 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 834 case TargetLowering::Promote: 835 default: assert(0 && "This action is not supported yet!"); 836 case TargetLowering::Legal: 837 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 838 std::vector<SDOperand> Ops; 839 Ops.push_back(Tmp1); 840 Ops.push_back(Tmp2); 841 Ops.push_back(Node->getOperand(2)); 842 Ops.push_back(Node->getOperand(3)); 843 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 844 } 845 break; 846 case TargetLowering::Expand: 847 // If BRTWOWAY_CC is legal for this target, then simply expand this node 848 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 849 // BRCOND/BR pair. 850 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 851 if (Tmp2.getOpcode() == ISD::SETCC) { 852 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 853 Tmp2.getOperand(0), Tmp2.getOperand(1), 854 Node->getOperand(2), Node->getOperand(3)); 855 } else { 856 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 857 DAG.getConstant(0, Tmp2.getValueType()), 858 Node->getOperand(2), Node->getOperand(3)); 859 } 860 } else { 861 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 862 Node->getOperand(2)); 863 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 864 } 865 break; 866 } 867 break; 868 case ISD::BRTWOWAY_CC: 869 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 870 if (isTypeLegal(Node->getOperand(2).getValueType())) { 871 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 872 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 873 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 874 Tmp3 != Node->getOperand(3)) { 875 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3, 876 Node->getOperand(4), Node->getOperand(5)); 877 } 878 break; 879 } else { 880 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 881 Node->getOperand(2), // LHS 882 Node->getOperand(3), // RHS 883 Node->getOperand(1))); 884 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 885 // pair. 886 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 887 default: assert(0 && "This action is not supported yet!"); 888 case TargetLowering::Legal: 889 // If we get a SETCC back from legalizing the SETCC node we just 890 // created, then use its LHS, RHS, and CC directly in creating a new 891 // node. Otherwise, select between the true and false value based on 892 // comparing the result of the legalized with zero. 893 if (Tmp2.getOpcode() == ISD::SETCC) { 894 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 895 Tmp2.getOperand(0), Tmp2.getOperand(1), 896 Node->getOperand(4), Node->getOperand(5)); 897 } else { 898 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 899 DAG.getConstant(0, Tmp2.getValueType()), 900 Node->getOperand(4), Node->getOperand(5)); 901 } 902 break; 903 case TargetLowering::Expand: 904 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 905 Node->getOperand(4)); 906 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 907 break; 908 } 909 } 910 break; 911 case ISD::LOAD: 912 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 913 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 914 915 if (Tmp1 != Node->getOperand(0) || 916 Tmp2 != Node->getOperand(1)) 917 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, 918 Node->getOperand(2)); 919 else 920 Result = SDOperand(Node, 0); 921 922 // Since loads produce two values, make sure to remember that we legalized 923 // both of them. 924 AddLegalizedOperand(SDOperand(Node, 0), Result); 925 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 926 return Result.getValue(Op.ResNo); 927 928 case ISD::EXTLOAD: 929 case ISD::SEXTLOAD: 930 case ISD::ZEXTLOAD: { 931 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 932 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 933 934 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 935 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 936 default: assert(0 && "This action is not supported yet!"); 937 case TargetLowering::Promote: 938 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 939 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 940 Tmp1, Tmp2, Node->getOperand(2), MVT::i8); 941 // Since loads produce two values, make sure to remember that we legalized 942 // both of them. 943 AddLegalizedOperand(SDOperand(Node, 0), Result); 944 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 945 return Result.getValue(Op.ResNo); 946 947 case TargetLowering::Legal: 948 if (Tmp1 != Node->getOperand(0) || 949 Tmp2 != Node->getOperand(1)) 950 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 951 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 952 else 953 Result = SDOperand(Node, 0); 954 955 // Since loads produce two values, make sure to remember that we legalized 956 // both of them. 957 AddLegalizedOperand(SDOperand(Node, 0), Result); 958 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 959 return Result.getValue(Op.ResNo); 960 case TargetLowering::Expand: 961 //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 962 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 963 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 964 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 965 if (Op.ResNo) 966 return Load.getValue(1); 967 return Result; 968 } 969 assert(Node->getOpcode() != ISD::EXTLOAD && 970 "EXTLOAD should always be supported!"); 971 // Turn the unsupported load into an EXTLOAD followed by an explicit 972 // zero/sign extend inreg. 973 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 974 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 975 SDOperand ValRes; 976 if (Node->getOpcode() == ISD::SEXTLOAD) 977 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 978 Result, DAG.getValueType(SrcVT)); 979 else 980 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 981 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 982 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 983 if (Op.ResNo) 984 return Result.getValue(1); 985 return ValRes; 986 } 987 assert(0 && "Unreachable"); 988 } 989 case ISD::EXTRACT_ELEMENT: { 990 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 991 switch (getTypeAction(OpTy)) { 992 default: 993 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 994 break; 995 case Legal: 996 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 997 // 1 -> Hi 998 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 999 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1000 TLI.getShiftAmountTy())); 1001 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1002 } else { 1003 // 0 -> Lo 1004 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1005 Node->getOperand(0)); 1006 } 1007 Result = LegalizeOp(Result); 1008 break; 1009 case Expand: 1010 // Get both the low and high parts. 1011 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1012 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1013 Result = Tmp2; // 1 -> Hi 1014 else 1015 Result = Tmp1; // 0 -> Lo 1016 break; 1017 } 1018 break; 1019 } 1020 1021 case ISD::CopyToReg: 1022 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1023 1024 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1025 "Register type must be legal!"); 1026 // Legalize the incoming value (must be legal). 1027 Tmp2 = LegalizeOp(Node->getOperand(2)); 1028 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2)) 1029 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1, 1030 Node->getOperand(1), Tmp2); 1031 break; 1032 1033 case ISD::RET: 1034 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1035 switch (Node->getNumOperands()) { 1036 case 2: // ret val 1037 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1038 case Legal: 1039 Tmp2 = LegalizeOp(Node->getOperand(1)); 1040 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1041 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1042 break; 1043 case Expand: { 1044 SDOperand Lo, Hi; 1045 ExpandOp(Node->getOperand(1), Lo, Hi); 1046 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1047 break; 1048 } 1049 case Promote: 1050 Tmp2 = PromoteOp(Node->getOperand(1)); 1051 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1052 break; 1053 } 1054 break; 1055 case 1: // ret void 1056 if (Tmp1 != Node->getOperand(0)) 1057 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 1058 break; 1059 default: { // ret <values> 1060 std::vector<SDOperand> NewValues; 1061 NewValues.push_back(Tmp1); 1062 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1063 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1064 case Legal: 1065 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1066 break; 1067 case Expand: { 1068 SDOperand Lo, Hi; 1069 ExpandOp(Node->getOperand(i), Lo, Hi); 1070 NewValues.push_back(Lo); 1071 NewValues.push_back(Hi); 1072 break; 1073 } 1074 case Promote: 1075 assert(0 && "Can't promote multiple return value yet!"); 1076 } 1077 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1078 break; 1079 } 1080 } 1081 break; 1082 case ISD::STORE: 1083 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1084 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1085 1086 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1087 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1088 if (CFP->getValueType(0) == MVT::f32) { 1089 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1090 DAG.getConstant(FloatToBits(CFP->getValue()), 1091 MVT::i32), 1092 Tmp2, 1093 Node->getOperand(3)); 1094 } else { 1095 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1096 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1097 DAG.getConstant(DoubleToBits(CFP->getValue()), 1098 MVT::i64), 1099 Tmp2, 1100 Node->getOperand(3)); 1101 } 1102 Node = Result.Val; 1103 } 1104 1105 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1106 case Legal: { 1107 SDOperand Val = LegalizeOp(Node->getOperand(1)); 1108 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 1109 Tmp2 != Node->getOperand(2)) 1110 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, 1111 Node->getOperand(3)); 1112 break; 1113 } 1114 case Promote: 1115 // Truncate the value and store the result. 1116 Tmp3 = PromoteOp(Node->getOperand(1)); 1117 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1118 Node->getOperand(3), 1119 DAG.getValueType(Node->getOperand(1).getValueType())); 1120 break; 1121 1122 case Expand: 1123 SDOperand Lo, Hi; 1124 unsigned IncrementSize; 1125 ExpandOp(Node->getOperand(1), Lo, Hi); 1126 1127 if (!TLI.isLittleEndian()) 1128 std::swap(Lo, Hi); 1129 1130 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1131 Node->getOperand(3)); 1132 // If this is a vector type, then we have to calculate the increment as 1133 // the product of the element size in bytes, and the number of elements 1134 // in the high half of the vector. 1135 if (MVT::Vector == Hi.getValueType()) { 1136 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue(); 1137 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT(); 1138 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8; 1139 } else { 1140 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1141 } 1142 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1143 getIntPtrConstant(IncrementSize)); 1144 assert(isTypeLegal(Tmp2.getValueType()) && 1145 "Pointers must be legal!"); 1146 //Again, claiming both parts of the store came form the same Instr 1147 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1148 Node->getOperand(3)); 1149 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1150 break; 1151 } 1152 break; 1153 case ISD::PCMARKER: 1154 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1155 if (Tmp1 != Node->getOperand(0)) 1156 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 1157 break; 1158 case ISD::READCYCLECOUNTER: 1159 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1160 if (Tmp1 != Node->getOperand(0)) 1161 Result = DAG.getNode(ISD::READCYCLECOUNTER, MVT::i64, Tmp1); 1162 break; 1163 1164 case ISD::TRUNCSTORE: 1165 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1166 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1167 1168 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1169 case Legal: 1170 Tmp2 = LegalizeOp(Node->getOperand(1)); 1171 1172 // The only promote case we handle is TRUNCSTORE:i1 X into 1173 // -> TRUNCSTORE:i8 (and X, 1) 1174 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1175 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1176 TargetLowering::Promote) { 1177 // Promote the bool to a mask then store. 1178 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1179 DAG.getConstant(1, Tmp2.getValueType())); 1180 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1181 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1182 1183 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1184 Tmp3 != Node->getOperand(2)) { 1185 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1186 Node->getOperand(3), Node->getOperand(4)); 1187 } 1188 break; 1189 case Promote: 1190 case Expand: 1191 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 1192 } 1193 break; 1194 case ISD::SELECT: 1195 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1196 case Expand: assert(0 && "It's impossible to expand bools"); 1197 case Legal: 1198 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1199 break; 1200 case Promote: 1201 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1202 break; 1203 } 1204 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1205 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1206 1207 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1208 default: assert(0 && "This action is not supported yet!"); 1209 case TargetLowering::Expand: 1210 if (Tmp1.getOpcode() == ISD::SETCC) { 1211 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1212 Tmp2, Tmp3, 1213 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1214 } else { 1215 // Make sure the condition is either zero or one. It may have been 1216 // promoted from something else. 1217 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1218 Result = DAG.getSelectCC(Tmp1, 1219 DAG.getConstant(0, Tmp1.getValueType()), 1220 Tmp2, Tmp3, ISD::SETNE); 1221 } 1222 break; 1223 case TargetLowering::Legal: 1224 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1225 Tmp3 != Node->getOperand(2)) 1226 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 1227 Tmp1, Tmp2, Tmp3); 1228 break; 1229 case TargetLowering::Promote: { 1230 MVT::ValueType NVT = 1231 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1232 unsigned ExtOp, TruncOp; 1233 if (MVT::isInteger(Tmp2.getValueType())) { 1234 ExtOp = ISD::ANY_EXTEND; 1235 TruncOp = ISD::TRUNCATE; 1236 } else { 1237 ExtOp = ISD::FP_EXTEND; 1238 TruncOp = ISD::FP_ROUND; 1239 } 1240 // Promote each of the values to the new type. 1241 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1242 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1243 // Perform the larger operation, then round down. 1244 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1245 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1246 break; 1247 } 1248 } 1249 break; 1250 case ISD::SELECT_CC: 1251 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1252 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1253 1254 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1255 // Everything is legal, see if we should expand this op or something. 1256 switch (TLI.getOperationAction(ISD::SELECT_CC, 1257 Node->getOperand(0).getValueType())) { 1258 default: assert(0 && "This action is not supported yet!"); 1259 case TargetLowering::Custom: { 1260 SDOperand Tmp = 1261 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), 1262 Node->getOperand(0), 1263 Node->getOperand(1), Tmp3, Tmp4, 1264 Node->getOperand(4)), DAG); 1265 if (Tmp.Val) { 1266 Result = LegalizeOp(Tmp); 1267 break; 1268 } 1269 } // FALLTHROUGH if the target can't lower this operation after all. 1270 case TargetLowering::Legal: 1271 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1272 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1273 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1274 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { 1275 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2, 1276 Tmp3, Tmp4, Node->getOperand(4)); 1277 } 1278 break; 1279 } 1280 break; 1281 } else { 1282 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1283 Node->getOperand(0), // LHS 1284 Node->getOperand(1), // RHS 1285 Node->getOperand(4))); 1286 // If we get a SETCC back from legalizing the SETCC node we just 1287 // created, then use its LHS, RHS, and CC directly in creating a new 1288 // node. Otherwise, select between the true and false value based on 1289 // comparing the result of the legalized with zero. 1290 if (Tmp1.getOpcode() == ISD::SETCC) { 1291 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1292 Tmp1.getOperand(0), Tmp1.getOperand(1), 1293 Tmp3, Tmp4, Tmp1.getOperand(2)); 1294 } else { 1295 Result = DAG.getSelectCC(Tmp1, 1296 DAG.getConstant(0, Tmp1.getValueType()), 1297 Tmp3, Tmp4, ISD::SETNE); 1298 } 1299 } 1300 break; 1301 case ISD::SETCC: 1302 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1303 case Legal: 1304 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1305 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1306 break; 1307 case Promote: 1308 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1309 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1310 1311 // If this is an FP compare, the operands have already been extended. 1312 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1313 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1314 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1315 1316 // Otherwise, we have to insert explicit sign or zero extends. Note 1317 // that we could insert sign extends for ALL conditions, but zero extend 1318 // is cheaper on many machines (an AND instead of two shifts), so prefer 1319 // it. 1320 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1321 default: assert(0 && "Unknown integer comparison!"); 1322 case ISD::SETEQ: 1323 case ISD::SETNE: 1324 case ISD::SETUGE: 1325 case ISD::SETUGT: 1326 case ISD::SETULE: 1327 case ISD::SETULT: 1328 // ALL of these operations will work if we either sign or zero extend 1329 // the operands (including the unsigned comparisons!). Zero extend is 1330 // usually a simpler/cheaper operation, so prefer it. 1331 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1332 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1333 break; 1334 case ISD::SETGE: 1335 case ISD::SETGT: 1336 case ISD::SETLT: 1337 case ISD::SETLE: 1338 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1339 DAG.getValueType(VT)); 1340 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1341 DAG.getValueType(VT)); 1342 break; 1343 } 1344 } 1345 break; 1346 case Expand: 1347 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1348 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1349 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1350 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1351 case ISD::SETEQ: 1352 case ISD::SETNE: 1353 if (RHSLo == RHSHi) 1354 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1355 if (RHSCST->isAllOnesValue()) { 1356 // Comparison to -1. 1357 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1358 Tmp2 = RHSLo; 1359 break; 1360 } 1361 1362 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1363 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1364 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1365 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1366 break; 1367 default: 1368 // If this is a comparison of the sign bit, just look at the top part. 1369 // X > -1, x < 0 1370 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1371 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1372 CST->getValue() == 0) || // X < 0 1373 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1374 (CST->isAllOnesValue()))) { // X > -1 1375 Tmp1 = LHSHi; 1376 Tmp2 = RHSHi; 1377 break; 1378 } 1379 1380 // FIXME: This generated code sucks. 1381 ISD::CondCode LowCC; 1382 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1383 default: assert(0 && "Unknown integer setcc!"); 1384 case ISD::SETLT: 1385 case ISD::SETULT: LowCC = ISD::SETULT; break; 1386 case ISD::SETGT: 1387 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1388 case ISD::SETLE: 1389 case ISD::SETULE: LowCC = ISD::SETULE; break; 1390 case ISD::SETGE: 1391 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1392 } 1393 1394 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1395 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1396 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1397 1398 // NOTE: on targets without efficient SELECT of bools, we can always use 1399 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1400 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1401 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1402 Node->getOperand(2)); 1403 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1404 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1405 Result, Tmp1, Tmp2)); 1406 return Result; 1407 } 1408 } 1409 1410 switch(TLI.getOperationAction(ISD::SETCC, Node->getOperand(0).getValueType())) { 1411 default: 1412 assert(0 && "Cannot handle this action for SETCC yet!"); 1413 break; 1414 case TargetLowering::Promote: 1415 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1416 Node->getOperand(2)); 1417 break; 1418 case TargetLowering::Legal: 1419 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1420 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1421 Node->getOperand(2)); 1422 break; 1423 case TargetLowering::Expand: 1424 // Expand a setcc node into a select_cc of the same condition, lhs, and 1425 // rhs that selects between const 1 (true) and const 0 (false). 1426 MVT::ValueType VT = Node->getValueType(0); 1427 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1428 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1429 Node->getOperand(2)); 1430 Result = LegalizeOp(Result); 1431 break; 1432 } 1433 break; 1434 1435 case ISD::MEMSET: 1436 case ISD::MEMCPY: 1437 case ISD::MEMMOVE: { 1438 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1439 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1440 1441 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1442 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1443 case Expand: assert(0 && "Cannot expand a byte!"); 1444 case Legal: 1445 Tmp3 = LegalizeOp(Node->getOperand(2)); 1446 break; 1447 case Promote: 1448 Tmp3 = PromoteOp(Node->getOperand(2)); 1449 break; 1450 } 1451 } else { 1452 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1453 } 1454 1455 SDOperand Tmp4; 1456 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1457 case Expand: { 1458 // Length is too big, just take the lo-part of the length. 1459 SDOperand HiPart; 1460 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1461 break; 1462 } 1463 case Legal: 1464 Tmp4 = LegalizeOp(Node->getOperand(3)); 1465 break; 1466 case Promote: 1467 Tmp4 = PromoteOp(Node->getOperand(3)); 1468 break; 1469 } 1470 1471 SDOperand Tmp5; 1472 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1473 case Expand: assert(0 && "Cannot expand this yet!"); 1474 case Legal: 1475 Tmp5 = LegalizeOp(Node->getOperand(4)); 1476 break; 1477 case Promote: 1478 Tmp5 = PromoteOp(Node->getOperand(4)); 1479 break; 1480 } 1481 1482 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1483 default: assert(0 && "This action not implemented for this operation!"); 1484 case TargetLowering::Custom: { 1485 SDOperand Tmp = 1486 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 1487 Tmp2, Tmp3, Tmp4, Tmp5), DAG); 1488 if (Tmp.Val) { 1489 Result = LegalizeOp(Tmp); 1490 break; 1491 } 1492 // FALLTHROUGH if the target thinks it is legal. 1493 } 1494 case TargetLowering::Legal: 1495 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1496 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 1497 Tmp5 != Node->getOperand(4)) { 1498 std::vector<SDOperand> Ops; 1499 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 1500 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 1501 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 1502 } 1503 break; 1504 case TargetLowering::Expand: { 1505 // Otherwise, the target does not support this operation. Lower the 1506 // operation to an explicit libcall as appropriate. 1507 MVT::ValueType IntPtr = TLI.getPointerTy(); 1508 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1509 std::vector<std::pair<SDOperand, const Type*> > Args; 1510 1511 const char *FnName = 0; 1512 if (Node->getOpcode() == ISD::MEMSET) { 1513 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1514 // Extend the ubyte argument to be an int value for the call. 1515 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1516 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1517 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1518 1519 FnName = "memset"; 1520 } else if (Node->getOpcode() == ISD::MEMCPY || 1521 Node->getOpcode() == ISD::MEMMOVE) { 1522 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1523 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1524 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1525 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1526 } else { 1527 assert(0 && "Unknown op!"); 1528 } 1529 1530 std::pair<SDOperand,SDOperand> CallResult = 1531 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1532 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1533 Result = CallResult.second; 1534 NeedsAnotherIteration = true; 1535 break; 1536 } 1537 } 1538 break; 1539 } 1540 1541 case ISD::READPORT: 1542 Tmp1 = LegalizeOp(Node->getOperand(0)); 1543 Tmp2 = LegalizeOp(Node->getOperand(1)); 1544 1545 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1546 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1547 std::vector<SDOperand> Ops; 1548 Ops.push_back(Tmp1); 1549 Ops.push_back(Tmp2); 1550 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1551 } else 1552 Result = SDOperand(Node, 0); 1553 // Since these produce two values, make sure to remember that we legalized 1554 // both of them. 1555 AddLegalizedOperand(SDOperand(Node, 0), Result); 1556 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1557 return Result.getValue(Op.ResNo); 1558 case ISD::WRITEPORT: 1559 Tmp1 = LegalizeOp(Node->getOperand(0)); 1560 Tmp2 = LegalizeOp(Node->getOperand(1)); 1561 Tmp3 = LegalizeOp(Node->getOperand(2)); 1562 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1563 Tmp3 != Node->getOperand(2)) 1564 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1565 break; 1566 1567 case ISD::READIO: 1568 Tmp1 = LegalizeOp(Node->getOperand(0)); 1569 Tmp2 = LegalizeOp(Node->getOperand(1)); 1570 1571 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1572 case TargetLowering::Custom: 1573 default: assert(0 && "This action not implemented for this operation!"); 1574 case TargetLowering::Legal: 1575 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1576 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1577 std::vector<SDOperand> Ops; 1578 Ops.push_back(Tmp1); 1579 Ops.push_back(Tmp2); 1580 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1581 } else 1582 Result = SDOperand(Node, 0); 1583 break; 1584 case TargetLowering::Expand: 1585 // Replace this with a load from memory. 1586 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 1587 Node->getOperand(1), DAG.getSrcValue(NULL)); 1588 Result = LegalizeOp(Result); 1589 break; 1590 } 1591 1592 // Since these produce two values, make sure to remember that we legalized 1593 // both of them. 1594 AddLegalizedOperand(SDOperand(Node, 0), Result); 1595 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1596 return Result.getValue(Op.ResNo); 1597 1598 case ISD::WRITEIO: 1599 Tmp1 = LegalizeOp(Node->getOperand(0)); 1600 Tmp2 = LegalizeOp(Node->getOperand(1)); 1601 Tmp3 = LegalizeOp(Node->getOperand(2)); 1602 1603 switch (TLI.getOperationAction(Node->getOpcode(), 1604 Node->getOperand(1).getValueType())) { 1605 case TargetLowering::Custom: 1606 default: assert(0 && "This action not implemented for this operation!"); 1607 case TargetLowering::Legal: 1608 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1609 Tmp3 != Node->getOperand(2)) 1610 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1611 break; 1612 case TargetLowering::Expand: 1613 // Replace this with a store to memory. 1614 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 1615 Node->getOperand(1), Node->getOperand(2), 1616 DAG.getSrcValue(NULL)); 1617 Result = LegalizeOp(Result); 1618 break; 1619 } 1620 break; 1621 1622 case ISD::ADD_PARTS: 1623 case ISD::SUB_PARTS: 1624 case ISD::SHL_PARTS: 1625 case ISD::SRA_PARTS: 1626 case ISD::SRL_PARTS: { 1627 std::vector<SDOperand> Ops; 1628 bool Changed = false; 1629 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1630 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1631 Changed |= Ops.back() != Node->getOperand(i); 1632 } 1633 if (Changed) { 1634 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1635 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 1636 } 1637 1638 // Since these produce multiple values, make sure to remember that we 1639 // legalized all of them. 1640 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1641 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1642 return Result.getValue(Op.ResNo); 1643 } 1644 1645 // Binary operators 1646 case ISD::ADD: 1647 case ISD::SUB: 1648 case ISD::MUL: 1649 case ISD::MULHS: 1650 case ISD::MULHU: 1651 case ISD::UDIV: 1652 case ISD::SDIV: 1653 case ISD::AND: 1654 case ISD::OR: 1655 case ISD::XOR: 1656 case ISD::SHL: 1657 case ISD::SRL: 1658 case ISD::SRA: 1659 case ISD::FADD: 1660 case ISD::FSUB: 1661 case ISD::FMUL: 1662 case ISD::FDIV: 1663 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1664 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1665 case Expand: assert(0 && "Not possible"); 1666 case Legal: 1667 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 1668 break; 1669 case Promote: 1670 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 1671 break; 1672 } 1673 if (Tmp1 != Node->getOperand(0) || 1674 Tmp2 != Node->getOperand(1)) 1675 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 1676 break; 1677 1678 case ISD::BUILD_PAIR: { 1679 MVT::ValueType PairTy = Node->getValueType(0); 1680 // TODO: handle the case where the Lo and Hi operands are not of legal type 1681 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 1682 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 1683 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 1684 case TargetLowering::Legal: 1685 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1686 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 1687 break; 1688 case TargetLowering::Promote: 1689 case TargetLowering::Custom: 1690 assert(0 && "Cannot promote/custom this yet!"); 1691 case TargetLowering::Expand: 1692 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 1693 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 1694 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 1695 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 1696 TLI.getShiftAmountTy())); 1697 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2)); 1698 break; 1699 } 1700 break; 1701 } 1702 1703 case ISD::UREM: 1704 case ISD::SREM: 1705 case ISD::FREM: 1706 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1707 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1708 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1709 case TargetLowering::Legal: 1710 if (Tmp1 != Node->getOperand(0) || 1711 Tmp2 != Node->getOperand(1)) 1712 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 1713 Tmp2); 1714 break; 1715 case TargetLowering::Promote: 1716 case TargetLowering::Custom: 1717 assert(0 && "Cannot promote/custom handle this yet!"); 1718 case TargetLowering::Expand: 1719 if (MVT::isInteger(Node->getValueType(0))) { 1720 MVT::ValueType VT = Node->getValueType(0); 1721 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 1722 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 1723 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 1724 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 1725 } else { 1726 // Floating point mod -> fmod libcall. 1727 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 1728 SDOperand Dummy; 1729 Result = ExpandLibCall(FnName, Node, Dummy); 1730 } 1731 break; 1732 } 1733 break; 1734 1735 case ISD::CTPOP: 1736 case ISD::CTTZ: 1737 case ISD::CTLZ: 1738 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 1739 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1740 case TargetLowering::Legal: 1741 if (Tmp1 != Node->getOperand(0)) 1742 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1743 break; 1744 case TargetLowering::Promote: { 1745 MVT::ValueType OVT = Tmp1.getValueType(); 1746 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1747 1748 // Zero extend the argument. 1749 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1750 // Perform the larger operation, then subtract if needed. 1751 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1752 switch(Node->getOpcode()) 1753 { 1754 case ISD::CTPOP: 1755 Result = Tmp1; 1756 break; 1757 case ISD::CTTZ: 1758 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 1759 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 1760 DAG.getConstant(getSizeInBits(NVT), NVT), 1761 ISD::SETEQ); 1762 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 1763 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 1764 break; 1765 case ISD::CTLZ: 1766 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 1767 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 1768 DAG.getConstant(getSizeInBits(NVT) - 1769 getSizeInBits(OVT), NVT)); 1770 break; 1771 } 1772 break; 1773 } 1774 case TargetLowering::Custom: 1775 assert(0 && "Cannot custom handle this yet!"); 1776 case TargetLowering::Expand: 1777 switch(Node->getOpcode()) 1778 { 1779 case ISD::CTPOP: { 1780 static const uint64_t mask[6] = { 1781 0x5555555555555555ULL, 0x3333333333333333ULL, 1782 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 1783 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 1784 }; 1785 MVT::ValueType VT = Tmp1.getValueType(); 1786 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1787 unsigned len = getSizeInBits(VT); 1788 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1789 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 1790 Tmp2 = DAG.getConstant(mask[i], VT); 1791 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1792 Tmp1 = DAG.getNode(ISD::ADD, VT, 1793 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), 1794 DAG.getNode(ISD::AND, VT, 1795 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), 1796 Tmp2)); 1797 } 1798 Result = Tmp1; 1799 break; 1800 } 1801 case ISD::CTLZ: { 1802 /* for now, we do this: 1803 x = x | (x >> 1); 1804 x = x | (x >> 2); 1805 ... 1806 x = x | (x >>16); 1807 x = x | (x >>32); // for 64-bit input 1808 return popcount(~x); 1809 1810 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ 1811 MVT::ValueType VT = Tmp1.getValueType(); 1812 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1813 unsigned len = getSizeInBits(VT); 1814 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1815 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1816 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, 1817 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); 1818 } 1819 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); 1820 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1821 break; 1822 } 1823 case ISD::CTTZ: { 1824 // for now, we use: { return popcount(~x & (x - 1)); } 1825 // unless the target has ctlz but not ctpop, in which case we use: 1826 // { return 32 - nlz(~x & (x-1)); } 1827 // see also http://www.hackersdelight.org/HDcode/ntz.cc 1828 MVT::ValueType VT = Tmp1.getValueType(); 1829 Tmp2 = DAG.getConstant(~0ULL, VT); 1830 Tmp3 = DAG.getNode(ISD::AND, VT, 1831 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), 1832 DAG.getNode(ISD::SUB, VT, Tmp1, 1833 DAG.getConstant(1, VT))); 1834 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead 1835 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 1836 TLI.isOperationLegal(ISD::CTLZ, VT)) { 1837 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, 1838 DAG.getConstant(getSizeInBits(VT), VT), 1839 DAG.getNode(ISD::CTLZ, VT, Tmp3))); 1840 } else { 1841 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1842 } 1843 break; 1844 } 1845 default: 1846 assert(0 && "Cannot expand this yet!"); 1847 break; 1848 } 1849 break; 1850 } 1851 break; 1852 1853 // Unary operators 1854 case ISD::FABS: 1855 case ISD::FNEG: 1856 case ISD::FSQRT: 1857 case ISD::FSIN: 1858 case ISD::FCOS: 1859 Tmp1 = LegalizeOp(Node->getOperand(0)); 1860 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1861 case TargetLowering::Legal: 1862 if (Tmp1 != Node->getOperand(0)) 1863 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1864 break; 1865 case TargetLowering::Promote: 1866 case TargetLowering::Custom: 1867 assert(0 && "Cannot promote/custom handle this yet!"); 1868 case TargetLowering::Expand: 1869 switch(Node->getOpcode()) { 1870 case ISD::FNEG: { 1871 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 1872 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 1873 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0), 1874 Tmp2, Tmp1)); 1875 break; 1876 } 1877 case ISD::FABS: { 1878 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 1879 MVT::ValueType VT = Node->getValueType(0); 1880 Tmp2 = DAG.getConstantFP(0.0, VT); 1881 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 1882 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 1883 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 1884 Result = LegalizeOp(Result); 1885 break; 1886 } 1887 case ISD::FSQRT: 1888 case ISD::FSIN: 1889 case ISD::FCOS: { 1890 MVT::ValueType VT = Node->getValueType(0); 1891 const char *FnName = 0; 1892 switch(Node->getOpcode()) { 1893 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 1894 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 1895 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 1896 default: assert(0 && "Unreachable!"); 1897 } 1898 SDOperand Dummy; 1899 Result = ExpandLibCall(FnName, Node, Dummy); 1900 break; 1901 } 1902 default: 1903 assert(0 && "Unreachable!"); 1904 } 1905 break; 1906 } 1907 break; 1908 1909 // Conversion operators. The source and destination have different types. 1910 case ISD::SINT_TO_FP: 1911 case ISD::UINT_TO_FP: { 1912 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 1913 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1914 case Legal: 1915 switch (TLI.getOperationAction(Node->getOpcode(), 1916 Node->getOperand(0).getValueType())) { 1917 default: assert(0 && "Unknown operation action!"); 1918 case TargetLowering::Expand: 1919 Result = ExpandLegalINT_TO_FP(isSigned, 1920 LegalizeOp(Node->getOperand(0)), 1921 Node->getValueType(0)); 1922 AddLegalizedOperand(Op, Result); 1923 return Result; 1924 case TargetLowering::Promote: 1925 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 1926 Node->getValueType(0), 1927 isSigned); 1928 AddLegalizedOperand(Op, Result); 1929 return Result; 1930 case TargetLowering::Legal: 1931 break; 1932 } 1933 1934 Tmp1 = LegalizeOp(Node->getOperand(0)); 1935 if (Tmp1 != Node->getOperand(0)) 1936 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1937 break; 1938 case Expand: 1939 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 1940 Node->getValueType(0), Node->getOperand(0)); 1941 break; 1942 case Promote: 1943 if (isSigned) { 1944 Result = PromoteOp(Node->getOperand(0)); 1945 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1946 Result, DAG.getValueType(Node->getOperand(0).getValueType())); 1947 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 1948 } else { 1949 Result = PromoteOp(Node->getOperand(0)); 1950 Result = DAG.getZeroExtendInReg(Result, 1951 Node->getOperand(0).getValueType()); 1952 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 1953 } 1954 break; 1955 } 1956 break; 1957 } 1958 case ISD::TRUNCATE: 1959 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1960 case Legal: 1961 Tmp1 = LegalizeOp(Node->getOperand(0)); 1962 if (Tmp1 != Node->getOperand(0)) 1963 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1964 break; 1965 case Expand: 1966 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1967 1968 // Since the result is legal, we should just be able to truncate the low 1969 // part of the source. 1970 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 1971 break; 1972 case Promote: 1973 Result = PromoteOp(Node->getOperand(0)); 1974 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 1975 break; 1976 } 1977 break; 1978 1979 case ISD::FP_TO_SINT: 1980 case ISD::FP_TO_UINT: 1981 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1982 case Legal: 1983 Tmp1 = LegalizeOp(Node->getOperand(0)); 1984 1985 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 1986 default: assert(0 && "Unknown operation action!"); 1987 case TargetLowering::Expand: 1988 if (Node->getOpcode() == ISD::FP_TO_UINT) { 1989 SDOperand True, False; 1990 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1991 MVT::ValueType NVT = Node->getValueType(0); 1992 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 1993 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 1994 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 1995 Node->getOperand(0), Tmp2, ISD::SETLT); 1996 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 1997 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 1998 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 1999 Tmp2)); 2000 False = DAG.getNode(ISD::XOR, NVT, False, 2001 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2002 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False)); 2003 return Result; 2004 } else { 2005 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2006 } 2007 break; 2008 case TargetLowering::Promote: 2009 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2010 Node->getOpcode() == ISD::FP_TO_SINT); 2011 AddLegalizedOperand(Op, Result); 2012 return Result; 2013 case TargetLowering::Custom: { 2014 SDOperand Tmp = 2015 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2016 Tmp = TLI.LowerOperation(Tmp, DAG); 2017 if (Tmp.Val) { 2018 AddLegalizedOperand(Op, Tmp); 2019 NeedsAnotherIteration = true; 2020 return Tmp; 2021 } else { 2022 // The target thinks this is legal afterall. 2023 break; 2024 } 2025 } 2026 case TargetLowering::Legal: 2027 break; 2028 } 2029 2030 if (Tmp1 != Node->getOperand(0)) 2031 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2032 break; 2033 case Expand: 2034 assert(0 && "Shouldn't need to expand other operators here!"); 2035 case Promote: 2036 Result = PromoteOp(Node->getOperand(0)); 2037 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2038 break; 2039 } 2040 break; 2041 2042 case ISD::ANY_EXTEND: 2043 case ISD::ZERO_EXTEND: 2044 case ISD::SIGN_EXTEND: 2045 case ISD::FP_EXTEND: 2046 case ISD::FP_ROUND: 2047 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2048 case Legal: 2049 Tmp1 = LegalizeOp(Node->getOperand(0)); 2050 if (Tmp1 != Node->getOperand(0)) 2051 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2052 break; 2053 case Expand: 2054 assert(0 && "Shouldn't need to expand other operators here!"); 2055 2056 case Promote: 2057 switch (Node->getOpcode()) { 2058 case ISD::ANY_EXTEND: 2059 Result = PromoteOp(Node->getOperand(0)); 2060 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2061 break; 2062 case ISD::ZERO_EXTEND: 2063 Result = PromoteOp(Node->getOperand(0)); 2064 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2065 Result = DAG.getZeroExtendInReg(Result, 2066 Node->getOperand(0).getValueType()); 2067 break; 2068 case ISD::SIGN_EXTEND: 2069 Result = PromoteOp(Node->getOperand(0)); 2070 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2071 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2072 Result, 2073 DAG.getValueType(Node->getOperand(0).getValueType())); 2074 break; 2075 case ISD::FP_EXTEND: 2076 Result = PromoteOp(Node->getOperand(0)); 2077 if (Result.getValueType() != Op.getValueType()) 2078 // Dynamically dead while we have only 2 FP types. 2079 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2080 break; 2081 case ISD::FP_ROUND: 2082 Result = PromoteOp(Node->getOperand(0)); 2083 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2084 break; 2085 } 2086 } 2087 break; 2088 case ISD::FP_ROUND_INREG: 2089 case ISD::SIGN_EXTEND_INREG: { 2090 Tmp1 = LegalizeOp(Node->getOperand(0)); 2091 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2092 2093 // If this operation is not supported, convert it to a shl/shr or load/store 2094 // pair. 2095 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2096 default: assert(0 && "This action not supported for this op yet!"); 2097 case TargetLowering::Legal: 2098 if (Tmp1 != Node->getOperand(0)) 2099 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2100 DAG.getValueType(ExtraVT)); 2101 break; 2102 case TargetLowering::Expand: 2103 // If this is an integer extend and shifts are supported, do that. 2104 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2105 // NOTE: we could fall back on load/store here too for targets without 2106 // SAR. However, it is doubtful that any exist. 2107 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2108 MVT::getSizeInBits(ExtraVT); 2109 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2110 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2111 Node->getOperand(0), ShiftCst); 2112 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2113 Result, ShiftCst); 2114 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2115 // The only way we can lower this is to turn it into a STORETRUNC, 2116 // EXTLOAD pair, targetting a temporary location (a stack slot). 2117 2118 // NOTE: there is a choice here between constantly creating new stack 2119 // slots and always reusing the same one. We currently always create 2120 // new ones, as reuse may inhibit scheduling. 2121 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2122 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2123 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2124 MachineFunction &MF = DAG.getMachineFunction(); 2125 int SSFI = 2126 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2127 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2128 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2129 Node->getOperand(0), StackSlot, 2130 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2131 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2132 Result, StackSlot, DAG.getSrcValue(NULL), 2133 ExtraVT); 2134 } else { 2135 assert(0 && "Unknown op"); 2136 } 2137 Result = LegalizeOp(Result); 2138 break; 2139 } 2140 break; 2141 } 2142 } 2143 2144 // Note that LegalizeOp may be reentered even from single-use nodes, which 2145 // means that we always must cache transformed nodes. 2146 AddLegalizedOperand(Op, Result); 2147 return Result; 2148} 2149 2150/// PromoteOp - Given an operation that produces a value in an invalid type, 2151/// promote it to compute the value into a larger type. The produced value will 2152/// have the correct bits for the low portion of the register, but no guarantee 2153/// is made about the top bits: it may be zero, sign-extended, or garbage. 2154SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2155 MVT::ValueType VT = Op.getValueType(); 2156 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2157 assert(getTypeAction(VT) == Promote && 2158 "Caller should expand or legalize operands that are not promotable!"); 2159 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2160 "Cannot promote to smaller type!"); 2161 2162 SDOperand Tmp1, Tmp2, Tmp3; 2163 2164 SDOperand Result; 2165 SDNode *Node = Op.Val; 2166 2167 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2168 if (I != PromotedNodes.end()) return I->second; 2169 2170 // Promotion needs an optimization step to clean up after it, and is not 2171 // careful to avoid operations the target does not support. Make sure that 2172 // all generated operations are legalized in the next iteration. 2173 NeedsAnotherIteration = true; 2174 2175 switch (Node->getOpcode()) { 2176 case ISD::CopyFromReg: 2177 assert(0 && "CopyFromReg must be legal!"); 2178 default: 2179 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2180 assert(0 && "Do not know how to promote this operator!"); 2181 abort(); 2182 case ISD::UNDEF: 2183 Result = DAG.getNode(ISD::UNDEF, NVT); 2184 break; 2185 case ISD::Constant: 2186 if (VT != MVT::i1) 2187 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2188 else 2189 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2190 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2191 break; 2192 case ISD::ConstantFP: 2193 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2194 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2195 break; 2196 2197 case ISD::SETCC: 2198 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2199 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2200 Node->getOperand(1), Node->getOperand(2)); 2201 Result = LegalizeOp(Result); 2202 break; 2203 2204 case ISD::TRUNCATE: 2205 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2206 case Legal: 2207 Result = LegalizeOp(Node->getOperand(0)); 2208 assert(Result.getValueType() >= NVT && 2209 "This truncation doesn't make sense!"); 2210 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2211 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2212 break; 2213 case Promote: 2214 // The truncation is not required, because we don't guarantee anything 2215 // about high bits anyway. 2216 Result = PromoteOp(Node->getOperand(0)); 2217 break; 2218 case Expand: 2219 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2220 // Truncate the low part of the expanded value to the result type 2221 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2222 } 2223 break; 2224 case ISD::SIGN_EXTEND: 2225 case ISD::ZERO_EXTEND: 2226 case ISD::ANY_EXTEND: 2227 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2228 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2229 case Legal: 2230 // Input is legal? Just do extend all the way to the larger type. 2231 Result = LegalizeOp(Node->getOperand(0)); 2232 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2233 break; 2234 case Promote: 2235 // Promote the reg if it's smaller. 2236 Result = PromoteOp(Node->getOperand(0)); 2237 // The high bits are not guaranteed to be anything. Insert an extend. 2238 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2239 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2240 DAG.getValueType(Node->getOperand(0).getValueType())); 2241 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2242 Result = DAG.getZeroExtendInReg(Result, 2243 Node->getOperand(0).getValueType()); 2244 break; 2245 } 2246 break; 2247 2248 case ISD::FP_EXTEND: 2249 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2250 case ISD::FP_ROUND: 2251 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2252 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2253 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2254 case Legal: 2255 // Input is legal? Do an FP_ROUND_INREG. 2256 Result = LegalizeOp(Node->getOperand(0)); 2257 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2258 DAG.getValueType(VT)); 2259 break; 2260 } 2261 break; 2262 2263 case ISD::SINT_TO_FP: 2264 case ISD::UINT_TO_FP: 2265 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2266 case Legal: 2267 Result = LegalizeOp(Node->getOperand(0)); 2268 // No extra round required here. 2269 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2270 break; 2271 2272 case Promote: 2273 Result = PromoteOp(Node->getOperand(0)); 2274 if (Node->getOpcode() == ISD::SINT_TO_FP) 2275 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2276 Result, 2277 DAG.getValueType(Node->getOperand(0).getValueType())); 2278 else 2279 Result = DAG.getZeroExtendInReg(Result, 2280 Node->getOperand(0).getValueType()); 2281 // No extra round required here. 2282 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2283 break; 2284 case Expand: 2285 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2286 Node->getOperand(0)); 2287 // Round if we cannot tolerate excess precision. 2288 if (NoExcessFPPrecision) 2289 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2290 DAG.getValueType(VT)); 2291 break; 2292 } 2293 break; 2294 2295 case ISD::FP_TO_SINT: 2296 case ISD::FP_TO_UINT: 2297 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2298 case Legal: 2299 Tmp1 = LegalizeOp(Node->getOperand(0)); 2300 break; 2301 case Promote: 2302 // The input result is prerounded, so we don't have to do anything 2303 // special. 2304 Tmp1 = PromoteOp(Node->getOperand(0)); 2305 break; 2306 case Expand: 2307 assert(0 && "not implemented"); 2308 } 2309 // If we're promoting a UINT to a larger size, check to see if the new node 2310 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2311 // we can use that instead. This allows us to generate better code for 2312 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2313 // legal, such as PowerPC. 2314 if (Node->getOpcode() == ISD::FP_TO_UINT && 2315 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2316 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2317 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2318 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2319 } else { 2320 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2321 } 2322 break; 2323 2324 case ISD::FABS: 2325 case ISD::FNEG: 2326 Tmp1 = PromoteOp(Node->getOperand(0)); 2327 assert(Tmp1.getValueType() == NVT); 2328 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2329 // NOTE: we do not have to do any extra rounding here for 2330 // NoExcessFPPrecision, because we know the input will have the appropriate 2331 // precision, and these operations don't modify precision at all. 2332 break; 2333 2334 case ISD::FSQRT: 2335 case ISD::FSIN: 2336 case ISD::FCOS: 2337 Tmp1 = PromoteOp(Node->getOperand(0)); 2338 assert(Tmp1.getValueType() == NVT); 2339 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2340 if(NoExcessFPPrecision) 2341 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2342 DAG.getValueType(VT)); 2343 break; 2344 2345 case ISD::AND: 2346 case ISD::OR: 2347 case ISD::XOR: 2348 case ISD::ADD: 2349 case ISD::SUB: 2350 case ISD::MUL: 2351 // The input may have strange things in the top bits of the registers, but 2352 // these operations don't care. They may have weird bits going out, but 2353 // that too is okay if they are integer operations. 2354 Tmp1 = PromoteOp(Node->getOperand(0)); 2355 Tmp2 = PromoteOp(Node->getOperand(1)); 2356 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2357 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2358 break; 2359 case ISD::FADD: 2360 case ISD::FSUB: 2361 case ISD::FMUL: 2362 // The input may have strange things in the top bits of the registers, but 2363 // these operations don't care. 2364 Tmp1 = PromoteOp(Node->getOperand(0)); 2365 Tmp2 = PromoteOp(Node->getOperand(1)); 2366 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2367 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2368 2369 // Floating point operations will give excess precision that we may not be 2370 // able to tolerate. If we DO allow excess precision, just leave it, 2371 // otherwise excise it. 2372 // FIXME: Why would we need to round FP ops more than integer ones? 2373 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 2374 if (NoExcessFPPrecision) 2375 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2376 DAG.getValueType(VT)); 2377 break; 2378 2379 case ISD::SDIV: 2380 case ISD::SREM: 2381 // These operators require that their input be sign extended. 2382 Tmp1 = PromoteOp(Node->getOperand(0)); 2383 Tmp2 = PromoteOp(Node->getOperand(1)); 2384 if (MVT::isInteger(NVT)) { 2385 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2386 DAG.getValueType(VT)); 2387 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 2388 DAG.getValueType(VT)); 2389 } 2390 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2391 2392 // Perform FP_ROUND: this is probably overly pessimistic. 2393 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2394 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2395 DAG.getValueType(VT)); 2396 break; 2397 case ISD::FDIV: 2398 case ISD::FREM: 2399 // These operators require that their input be fp extended. 2400 Tmp1 = PromoteOp(Node->getOperand(0)); 2401 Tmp2 = PromoteOp(Node->getOperand(1)); 2402 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2403 2404 // Perform FP_ROUND: this is probably overly pessimistic. 2405 if (NoExcessFPPrecision) 2406 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2407 DAG.getValueType(VT)); 2408 break; 2409 2410 case ISD::UDIV: 2411 case ISD::UREM: 2412 // These operators require that their input be zero extended. 2413 Tmp1 = PromoteOp(Node->getOperand(0)); 2414 Tmp2 = PromoteOp(Node->getOperand(1)); 2415 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 2416 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2417 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 2418 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2419 break; 2420 2421 case ISD::SHL: 2422 Tmp1 = PromoteOp(Node->getOperand(0)); 2423 Tmp2 = LegalizeOp(Node->getOperand(1)); 2424 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 2425 break; 2426 case ISD::SRA: 2427 // The input value must be properly sign extended. 2428 Tmp1 = PromoteOp(Node->getOperand(0)); 2429 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2430 DAG.getValueType(VT)); 2431 Tmp2 = LegalizeOp(Node->getOperand(1)); 2432 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 2433 break; 2434 case ISD::SRL: 2435 // The input value must be properly zero extended. 2436 Tmp1 = PromoteOp(Node->getOperand(0)); 2437 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2438 Tmp2 = LegalizeOp(Node->getOperand(1)); 2439 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 2440 break; 2441 case ISD::LOAD: 2442 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2443 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2444 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2, 2445 Node->getOperand(2), VT); 2446 // Remember that we legalized the chain. 2447 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2448 break; 2449 case ISD::SEXTLOAD: 2450 case ISD::ZEXTLOAD: 2451 case ISD::EXTLOAD: 2452 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2453 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2454 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2, 2455 Node->getOperand(2), 2456 cast<VTSDNode>(Node->getOperand(3))->getVT()); 2457 // Remember that we legalized the chain. 2458 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2459 break; 2460 case ISD::SELECT: 2461 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2462 case Expand: assert(0 && "It's impossible to expand bools"); 2463 case Legal: 2464 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 2465 break; 2466 case Promote: 2467 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2468 break; 2469 } 2470 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 2471 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 2472 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 2473 break; 2474 case ISD::SELECT_CC: 2475 Tmp2 = PromoteOp(Node->getOperand(2)); // True 2476 Tmp3 = PromoteOp(Node->getOperand(3)); // False 2477 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 2478 Node->getOperand(1), Tmp2, Tmp3, 2479 Node->getOperand(4)); 2480 break; 2481 case ISD::TAILCALL: 2482 case ISD::CALL: { 2483 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2484 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 2485 2486 std::vector<SDOperand> Ops; 2487 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 2488 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2489 2490 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 2491 "Can only promote single result calls"); 2492 std::vector<MVT::ValueType> RetTyVTs; 2493 RetTyVTs.reserve(2); 2494 RetTyVTs.push_back(NVT); 2495 RetTyVTs.push_back(MVT::Other); 2496 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 2497 Node->getOpcode() == ISD::TAILCALL); 2498 Result = SDOperand(NC, 0); 2499 2500 // Insert the new chain mapping. 2501 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2502 break; 2503 } 2504 case ISD::CTPOP: 2505 case ISD::CTTZ: 2506 case ISD::CTLZ: 2507 Tmp1 = Node->getOperand(0); 2508 //Zero extend the argument 2509 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2510 // Perform the larger operation, then subtract if needed. 2511 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2512 switch(Node->getOpcode()) 2513 { 2514 case ISD::CTPOP: 2515 Result = Tmp1; 2516 break; 2517 case ISD::CTTZ: 2518 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2519 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2520 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 2521 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2522 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); 2523 break; 2524 case ISD::CTLZ: 2525 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2526 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2527 DAG.getConstant(getSizeInBits(NVT) - 2528 getSizeInBits(VT), NVT)); 2529 break; 2530 } 2531 break; 2532 } 2533 2534 assert(Result.Val && "Didn't set a result!"); 2535 AddPromotedOperand(Op, Result); 2536 return Result; 2537} 2538 2539/// ExpandAddSub - Find a clever way to expand this add operation into 2540/// subcomponents. 2541void SelectionDAGLegalize:: 2542ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 2543 SDOperand &Lo, SDOperand &Hi) { 2544 // Expand the subcomponents. 2545 SDOperand LHSL, LHSH, RHSL, RHSH; 2546 ExpandOp(LHS, LHSL, LHSH); 2547 ExpandOp(RHS, RHSL, RHSH); 2548 2549 std::vector<SDOperand> Ops; 2550 Ops.push_back(LHSL); 2551 Ops.push_back(LHSH); 2552 Ops.push_back(RHSL); 2553 Ops.push_back(RHSH); 2554 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2555 Lo = DAG.getNode(NodeOp, VTs, Ops); 2556 Hi = Lo.getValue(1); 2557} 2558 2559void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 2560 SDOperand Op, SDOperand Amt, 2561 SDOperand &Lo, SDOperand &Hi) { 2562 // Expand the subcomponents. 2563 SDOperand LHSL, LHSH; 2564 ExpandOp(Op, LHSL, LHSH); 2565 2566 std::vector<SDOperand> Ops; 2567 Ops.push_back(LHSL); 2568 Ops.push_back(LHSH); 2569 Ops.push_back(Amt); 2570 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2571 Lo = DAG.getNode(NodeOp, VTs, Ops); 2572 Hi = Lo.getValue(1); 2573} 2574 2575 2576/// ExpandShift - Try to find a clever way to expand this shift operation out to 2577/// smaller elements. If we can't find a way that is more efficient than a 2578/// libcall on this target, return false. Otherwise, return true with the 2579/// low-parts expanded into Lo and Hi. 2580bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 2581 SDOperand &Lo, SDOperand &Hi) { 2582 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 2583 "This is not a shift!"); 2584 2585 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 2586 SDOperand ShAmt = LegalizeOp(Amt); 2587 MVT::ValueType ShTy = ShAmt.getValueType(); 2588 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 2589 unsigned NVTBits = MVT::getSizeInBits(NVT); 2590 2591 // Handle the case when Amt is an immediate. Other cases are currently broken 2592 // and are disabled. 2593 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 2594 unsigned Cst = CN->getValue(); 2595 // Expand the incoming operand to be shifted, so that we have its parts 2596 SDOperand InL, InH; 2597 ExpandOp(Op, InL, InH); 2598 switch(Opc) { 2599 case ISD::SHL: 2600 if (Cst > VTBits) { 2601 Lo = DAG.getConstant(0, NVT); 2602 Hi = DAG.getConstant(0, NVT); 2603 } else if (Cst > NVTBits) { 2604 Lo = DAG.getConstant(0, NVT); 2605 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 2606 } else if (Cst == NVTBits) { 2607 Lo = DAG.getConstant(0, NVT); 2608 Hi = InL; 2609 } else { 2610 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 2611 Hi = DAG.getNode(ISD::OR, NVT, 2612 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 2613 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 2614 } 2615 return true; 2616 case ISD::SRL: 2617 if (Cst > VTBits) { 2618 Lo = DAG.getConstant(0, NVT); 2619 Hi = DAG.getConstant(0, NVT); 2620 } else if (Cst > NVTBits) { 2621 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 2622 Hi = DAG.getConstant(0, NVT); 2623 } else if (Cst == NVTBits) { 2624 Lo = InH; 2625 Hi = DAG.getConstant(0, NVT); 2626 } else { 2627 Lo = DAG.getNode(ISD::OR, NVT, 2628 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2629 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2630 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 2631 } 2632 return true; 2633 case ISD::SRA: 2634 if (Cst > VTBits) { 2635 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 2636 DAG.getConstant(NVTBits-1, ShTy)); 2637 } else if (Cst > NVTBits) { 2638 Lo = DAG.getNode(ISD::SRA, NVT, InH, 2639 DAG.getConstant(Cst-NVTBits, ShTy)); 2640 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2641 DAG.getConstant(NVTBits-1, ShTy)); 2642 } else if (Cst == NVTBits) { 2643 Lo = InH; 2644 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2645 DAG.getConstant(NVTBits-1, ShTy)); 2646 } else { 2647 Lo = DAG.getNode(ISD::OR, NVT, 2648 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2649 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2650 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 2651 } 2652 return true; 2653 } 2654 } 2655 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 2656 // so disable it for now. Currently targets are handling this via SHL_PARTS 2657 // and friends. 2658 return false; 2659 2660 // If we have an efficient select operation (or if the selects will all fold 2661 // away), lower to some complex code, otherwise just emit the libcall. 2662 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt)) 2663 return false; 2664 2665 SDOperand InL, InH; 2666 ExpandOp(Op, InL, InH); 2667 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 2668 DAG.getConstant(NVTBits, ShTy), ShAmt); 2669 2670 // Compare the unmasked shift amount against 32. 2671 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt, 2672 DAG.getConstant(NVTBits, ShTy), ISD::SETGE); 2673 2674 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 2675 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 2676 DAG.getConstant(NVTBits-1, ShTy)); 2677 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 2678 DAG.getConstant(NVTBits-1, ShTy)); 2679 } 2680 2681 if (Opc == ISD::SHL) { 2682 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 2683 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 2684 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 2685 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 2686 2687 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2688 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 2689 } else { 2690 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 2691 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt, 2692 DAG.getConstant(32, ShTy), 2693 ISD::SETEQ), 2694 DAG.getConstant(0, NVT), 2695 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 2696 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 2697 HiLoPart, 2698 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 2699 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 2700 2701 SDOperand HiPart; 2702 if (Opc == ISD::SRA) 2703 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 2704 DAG.getConstant(NVTBits-1, ShTy)); 2705 else 2706 HiPart = DAG.getConstant(0, NVT); 2707 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2708 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 2709 } 2710 return true; 2711} 2712 2713/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 2714/// NodeDepth) node that is an CallSeqStart operation and occurs later than 2715/// Found. 2716static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) { 2717 if (Node->getNodeDepth() <= Found->getNodeDepth()) return; 2718 2719 // If we found an CALLSEQ_START, we already know this node occurs later 2720 // than the Found node. Just remember this node and return. 2721 if (Node->getOpcode() == ISD::CALLSEQ_START) { 2722 Found = Node; 2723 return; 2724 } 2725 2726 // Otherwise, scan the operands of Node to see if any of them is a call. 2727 assert(Node->getNumOperands() != 0 && 2728 "All leaves should have depth equal to the entry node!"); 2729 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 2730 FindLatestCallSeqStart(Node->getOperand(i).Val, Found); 2731 2732 // Tail recurse for the last iteration. 2733 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 2734 Found); 2735} 2736 2737 2738/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 2739/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 2740/// than Found. 2741static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 2742 std::set<SDNode*> &Visited) { 2743 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 2744 !Visited.insert(Node).second) return; 2745 2746 // If we found an CALLSEQ_END, we already know this node occurs earlier 2747 // than the Found node. Just remember this node and return. 2748 if (Node->getOpcode() == ISD::CALLSEQ_END) { 2749 Found = Node; 2750 return; 2751 } 2752 2753 // Otherwise, scan the operands of Node to see if any of them is a call. 2754 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 2755 if (UI == E) return; 2756 for (--E; UI != E; ++UI) 2757 FindEarliestCallSeqEnd(*UI, Found, Visited); 2758 2759 // Tail recurse for the last iteration. 2760 FindEarliestCallSeqEnd(*UI, Found, Visited); 2761} 2762 2763/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 2764/// find the CALLSEQ_END node that terminates the call sequence. 2765static SDNode *FindCallSeqEnd(SDNode *Node) { 2766 if (Node->getOpcode() == ISD::CALLSEQ_END) 2767 return Node; 2768 if (Node->use_empty()) 2769 return 0; // No CallSeqEnd 2770 2771 SDOperand TheChain(Node, Node->getNumValues()-1); 2772 if (TheChain.getValueType() != MVT::Other) 2773 TheChain = SDOperand(Node, 0); 2774 if (TheChain.getValueType() != MVT::Other) 2775 return 0; 2776 2777 for (SDNode::use_iterator UI = Node->use_begin(), 2778 E = Node->use_end(); UI != E; ++UI) { 2779 2780 // Make sure to only follow users of our token chain. 2781 SDNode *User = *UI; 2782 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 2783 if (User->getOperand(i) == TheChain) 2784 if (SDNode *Result = FindCallSeqEnd(User)) 2785 return Result; 2786 } 2787 return 0; 2788} 2789 2790/// FindCallSeqStart - Given a chained node that is part of a call sequence, 2791/// find the CALLSEQ_START node that initiates the call sequence. 2792static SDNode *FindCallSeqStart(SDNode *Node) { 2793 assert(Node && "Didn't find callseq_start for a call??"); 2794 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 2795 2796 assert(Node->getOperand(0).getValueType() == MVT::Other && 2797 "Node doesn't have a token chain argument!"); 2798 return FindCallSeqStart(Node->getOperand(0).Val); 2799} 2800 2801 2802/// FindInputOutputChains - If we are replacing an operation with a call we need 2803/// to find the call that occurs before and the call that occurs after it to 2804/// properly serialize the calls in the block. The returned operand is the 2805/// input chain value for the new call (e.g. the entry node or the previous 2806/// call), and OutChain is set to be the chain node to update to point to the 2807/// end of the call chain. 2808static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 2809 SDOperand Entry) { 2810 SDNode *LatestCallSeqStart = Entry.Val; 2811 SDNode *LatestCallSeqEnd = 0; 2812 FindLatestCallSeqStart(OpNode, LatestCallSeqStart); 2813 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 2814 2815 // It is possible that no ISD::CALLSEQ_START was found because there is no 2816 // previous call in the function. LatestCallStackDown may in that case be 2817 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 2818 // unless LatestCallStackDown is an CALLSEQ_START. 2819 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) { 2820 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 2821 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n"; 2822 } else { 2823 LatestCallSeqEnd = Entry.Val; 2824 } 2825 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 2826 2827 // Finally, find the first call that this must come before, first we find the 2828 // CallSeqEnd that ends the call. 2829 OutChain = 0; 2830 std::set<SDNode*> Visited; 2831 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 2832 2833 // If we found one, translate from the adj up to the callseq_start. 2834 if (OutChain) 2835 OutChain = FindCallSeqStart(OutChain); 2836 2837 return SDOperand(LatestCallSeqEnd, 0); 2838} 2839 2840/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 2841void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 2842 SDNode *OutChain) { 2843 // Nothing to splice it into? 2844 if (OutChain == 0) return; 2845 2846 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 2847 //OutChain->dump(); 2848 2849 // Form a token factor node merging the old inval and the new inval. 2850 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 2851 OutChain->getOperand(0)); 2852 // Change the node to refer to the new token. 2853 OutChain->setAdjCallChain(InToken); 2854} 2855 2856 2857// ExpandLibCall - Expand a node into a call to a libcall. If the result value 2858// does not fit into a register, return the lo part and set the hi part to the 2859// by-reg argument. If it does fit into a single register, return the result 2860// and leave the Hi part unset. 2861SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 2862 SDOperand &Hi) { 2863 SDNode *OutChain; 2864 SDOperand InChain = FindInputOutputChains(Node, OutChain, 2865 DAG.getEntryNode()); 2866 if (InChain.Val == 0) 2867 InChain = DAG.getEntryNode(); 2868 2869 TargetLowering::ArgListTy Args; 2870 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2871 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 2872 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 2873 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 2874 } 2875 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 2876 2877 // Splice the libcall in wherever FindInputOutputChains tells us to. 2878 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 2879 std::pair<SDOperand,SDOperand> CallInfo = 2880 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 2881 Callee, Args, DAG); 2882 2883 SDOperand Result; 2884 switch (getTypeAction(CallInfo.first.getValueType())) { 2885 default: assert(0 && "Unknown thing"); 2886 case Legal: 2887 Result = CallInfo.first; 2888 break; 2889 case Promote: 2890 assert(0 && "Cannot promote this yet!"); 2891 case Expand: 2892 ExpandOp(CallInfo.first, Result, Hi); 2893 CallInfo.second = LegalizeOp(CallInfo.second); 2894 break; 2895 } 2896 2897 SpliceCallInto(CallInfo.second, OutChain); 2898 NeedsAnotherIteration = true; 2899 return Result; 2900} 2901 2902 2903/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 2904/// destination type is legal. 2905SDOperand SelectionDAGLegalize:: 2906ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 2907 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 2908 assert(getTypeAction(Source.getValueType()) == Expand && 2909 "This is not an expansion!"); 2910 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 2911 2912 if (!isSigned) { 2913 assert(Source.getValueType() == MVT::i64 && 2914 "This only works for 64-bit -> FP"); 2915 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 2916 // incoming integer is set. To handle this, we dynamically test to see if 2917 // it is set, and, if so, add a fudge factor. 2918 SDOperand Lo, Hi; 2919 ExpandOp(Source, Lo, Hi); 2920 2921 // If this is unsigned, and not supported, first perform the conversion to 2922 // signed, then adjust the result if the sign bit is set. 2923 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 2924 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 2925 2926 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 2927 DAG.getConstant(0, Hi.getValueType()), 2928 ISD::SETLT); 2929 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 2930 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 2931 SignSet, Four, Zero); 2932 uint64_t FF = 0x5f800000ULL; 2933 if (TLI.isLittleEndian()) FF <<= 32; 2934 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 2935 2936 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2937 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 2938 SDOperand FudgeInReg; 2939 if (DestTy == MVT::f32) 2940 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 2941 DAG.getSrcValue(NULL)); 2942 else { 2943 assert(DestTy == MVT::f64 && "Unexpected conversion"); 2944 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 2945 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 2946 } 2947 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 2948 } 2949 2950 // Check to see if the target has a custom way to lower this. If so, use it. 2951 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 2952 default: assert(0 && "This action not implemented for this operation!"); 2953 case TargetLowering::Legal: 2954 case TargetLowering::Expand: 2955 break; // This case is handled below. 2956 case TargetLowering::Custom: { 2957 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 2958 Source), DAG); 2959 if (NV.Val) 2960 return LegalizeOp(NV); 2961 break; // The target decided this was legal after all 2962 } 2963 } 2964 2965 // Expand the source, then glue it back together for the call. We must expand 2966 // the source in case it is shared (this pass of legalize must traverse it). 2967 SDOperand SrcLo, SrcHi; 2968 ExpandOp(Source, SrcLo, SrcHi); 2969 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 2970 2971 SDNode *OutChain = 0; 2972 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 2973 DAG.getEntryNode()); 2974 const char *FnName = 0; 2975 if (DestTy == MVT::f32) 2976 FnName = "__floatdisf"; 2977 else { 2978 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 2979 FnName = "__floatdidf"; 2980 } 2981 2982 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 2983 2984 TargetLowering::ArgListTy Args; 2985 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 2986 2987 Args.push_back(std::make_pair(Source, ArgTy)); 2988 2989 // We don't care about token chains for libcalls. We just use the entry 2990 // node as our input and ignore the output chain. This allows us to place 2991 // calls wherever we need them to satisfy data dependences. 2992 const Type *RetTy = MVT::getTypeForValueType(DestTy); 2993 2994 std::pair<SDOperand,SDOperand> CallResult = 2995 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 2996 Callee, Args, DAG); 2997 2998 SpliceCallInto(CallResult.second, OutChain); 2999 return CallResult.first; 3000} 3001 3002 3003 3004/// ExpandOp - Expand the specified SDOperand into its two component pieces 3005/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 3006/// LegalizeNodes map is filled in for any results that are not expanded, the 3007/// ExpandedNodes map is filled in for any results that are expanded, and the 3008/// Lo/Hi values are returned. 3009void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 3010 MVT::ValueType VT = Op.getValueType(); 3011 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3012 SDNode *Node = Op.Val; 3013 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 3014 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 3015 "Cannot expand FP values!"); 3016 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 3017 "Cannot expand to FP value or to larger int value!"); 3018 3019 // See if we already expanded it. 3020 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 3021 = ExpandedNodes.find(Op); 3022 if (I != ExpandedNodes.end()) { 3023 Lo = I->second.first; 3024 Hi = I->second.second; 3025 return; 3026 } 3027 3028 // Expanding to multiple registers needs to perform an optimization step, and 3029 // is not careful to avoid operations the target does not support. Make sure 3030 // that all generated operations are legalized in the next iteration. 3031 NeedsAnotherIteration = true; 3032 3033 switch (Node->getOpcode()) { 3034 case ISD::CopyFromReg: 3035 assert(0 && "CopyFromReg must be legal!"); 3036 default: 3037 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 3038 assert(0 && "Do not know how to expand this operator!"); 3039 abort(); 3040 case ISD::UNDEF: 3041 Lo = DAG.getNode(ISD::UNDEF, NVT); 3042 Hi = DAG.getNode(ISD::UNDEF, NVT); 3043 break; 3044 case ISD::Constant: { 3045 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 3046 Lo = DAG.getConstant(Cst, NVT); 3047 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 3048 break; 3049 } 3050 3051 case ISD::BUILD_PAIR: 3052 // Legalize both operands. FIXME: in the future we should handle the case 3053 // where the two elements are not legal. 3054 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 3055 Lo = LegalizeOp(Node->getOperand(0)); 3056 Hi = LegalizeOp(Node->getOperand(1)); 3057 break; 3058 3059 case ISD::CTPOP: 3060 ExpandOp(Node->getOperand(0), Lo, Hi); 3061 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 3062 DAG.getNode(ISD::CTPOP, NVT, Lo), 3063 DAG.getNode(ISD::CTPOP, NVT, Hi)); 3064 Hi = DAG.getConstant(0, NVT); 3065 break; 3066 3067 case ISD::CTLZ: { 3068 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 3069 ExpandOp(Node->getOperand(0), Lo, Hi); 3070 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3071 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 3072 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 3073 ISD::SETNE); 3074 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 3075 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 3076 3077 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 3078 Hi = DAG.getConstant(0, NVT); 3079 break; 3080 } 3081 3082 case ISD::CTTZ: { 3083 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 3084 ExpandOp(Node->getOperand(0), Lo, Hi); 3085 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3086 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 3087 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 3088 ISD::SETNE); 3089 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 3090 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 3091 3092 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 3093 Hi = DAG.getConstant(0, NVT); 3094 break; 3095 } 3096 3097 case ISD::LOAD: { 3098 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3099 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3100 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3101 3102 // Increment the pointer to the other half. 3103 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 3104 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3105 getIntPtrConstant(IncrementSize)); 3106 //Is this safe? declaring that the two parts of the split load 3107 //are from the same instruction? 3108 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3109 3110 // Build a factor node to remember that this load is independent of the 3111 // other one. 3112 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3113 Hi.getValue(1)); 3114 3115 // Remember that we legalized the chain. 3116 AddLegalizedOperand(Op.getValue(1), TF); 3117 if (!TLI.isLittleEndian()) 3118 std::swap(Lo, Hi); 3119 break; 3120 } 3121 case ISD::VLOAD: { 3122 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3123 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3124 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3125 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3126 3127 // If we only have two elements, turn into a pair of scalar loads. 3128 // FIXME: handle case where a vector of two elements is fine, such as 3129 // 2 x double on SSE2. 3130 if (NumElements == 2) { 3131 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3132 // Increment the pointer to the other half. 3133 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8; 3134 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3135 getIntPtrConstant(IncrementSize)); 3136 //Is this safe? declaring that the two parts of the split load 3137 //are from the same instruction? 3138 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3139 } else { 3140 NumElements /= 2; // Split the vector in half 3141 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3142 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8; 3143 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3144 getIntPtrConstant(IncrementSize)); 3145 //Is this safe? declaring that the two parts of the split load 3146 //are from the same instruction? 3147 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3148 } 3149 3150 // Build a factor node to remember that this load is independent of the 3151 // other one. 3152 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3153 Hi.getValue(1)); 3154 3155 // Remember that we legalized the chain. 3156 AddLegalizedOperand(Op.getValue(1), TF); 3157 if (!TLI.isLittleEndian()) 3158 std::swap(Lo, Hi); 3159 break; 3160 } 3161 case ISD::VADD: 3162 case ISD::VSUB: 3163 case ISD::VMUL: { 3164 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3165 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3166 SDOperand LL, LH, RL, RH; 3167 3168 ExpandOp(Node->getOperand(0), LL, LH); 3169 ExpandOp(Node->getOperand(1), RL, RH); 3170 3171 // If we only have two elements, turn into a pair of scalar loads. 3172 // FIXME: handle case where a vector of two elements is fine, such as 3173 // 2 x double on SSE2. 3174 if (NumElements == 2) { 3175 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT); 3176 Lo = DAG.getNode(Opc, EVT, LL, RL); 3177 Hi = DAG.getNode(Opc, EVT, LH, RH); 3178 } else { 3179 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2), 3180 LL.getOperand(3)); 3181 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2), 3182 LH.getOperand(3)); 3183 } 3184 break; 3185 } 3186 case ISD::TAILCALL: 3187 case ISD::CALL: { 3188 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3189 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 3190 3191 bool Changed = false; 3192 std::vector<SDOperand> Ops; 3193 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 3194 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3195 Changed |= Ops.back() != Node->getOperand(i); 3196 } 3197 3198 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 3199 "Can only expand a call once so far, not i64 -> i16!"); 3200 3201 std::vector<MVT::ValueType> RetTyVTs; 3202 RetTyVTs.reserve(3); 3203 RetTyVTs.push_back(NVT); 3204 RetTyVTs.push_back(NVT); 3205 RetTyVTs.push_back(MVT::Other); 3206 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops, 3207 Node->getOpcode() == ISD::TAILCALL); 3208 Lo = SDOperand(NC, 0); 3209 Hi = SDOperand(NC, 1); 3210 3211 // Insert the new chain mapping. 3212 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 3213 break; 3214 } 3215 case ISD::AND: 3216 case ISD::OR: 3217 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 3218 SDOperand LL, LH, RL, RH; 3219 ExpandOp(Node->getOperand(0), LL, LH); 3220 ExpandOp(Node->getOperand(1), RL, RH); 3221 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 3222 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 3223 break; 3224 } 3225 case ISD::SELECT: { 3226 SDOperand C, LL, LH, RL, RH; 3227 3228 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3229 case Expand: assert(0 && "It's impossible to expand bools"); 3230 case Legal: 3231 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 3232 break; 3233 case Promote: 3234 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 3235 break; 3236 } 3237 ExpandOp(Node->getOperand(1), LL, LH); 3238 ExpandOp(Node->getOperand(2), RL, RH); 3239 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 3240 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 3241 break; 3242 } 3243 case ISD::SELECT_CC: { 3244 SDOperand TL, TH, FL, FH; 3245 ExpandOp(Node->getOperand(2), TL, TH); 3246 ExpandOp(Node->getOperand(3), FL, FH); 3247 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3248 Node->getOperand(1), TL, FL, Node->getOperand(4)); 3249 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3250 Node->getOperand(1), TH, FH, Node->getOperand(4)); 3251 Lo = LegalizeOp(Lo); 3252 Hi = LegalizeOp(Hi); 3253 break; 3254 } 3255 case ISD::SEXTLOAD: { 3256 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3257 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3258 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3259 3260 if (EVT == NVT) 3261 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3262 else 3263 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3264 EVT); 3265 3266 // Remember that we legalized the chain. 3267 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3268 3269 // The high part is obtained by SRA'ing all but one of the bits of the lo 3270 // part. 3271 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3272 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3273 TLI.getShiftAmountTy())); 3274 Lo = LegalizeOp(Lo); 3275 Hi = LegalizeOp(Hi); 3276 break; 3277 } 3278 case ISD::ZEXTLOAD: { 3279 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3280 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3281 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3282 3283 if (EVT == NVT) 3284 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3285 else 3286 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3287 EVT); 3288 3289 // Remember that we legalized the chain. 3290 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3291 3292 // The high part is just a zero. 3293 Hi = LegalizeOp(DAG.getConstant(0, NVT)); 3294 Lo = LegalizeOp(Lo); 3295 break; 3296 } 3297 case ISD::EXTLOAD: { 3298 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3299 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3300 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3301 3302 if (EVT == NVT) 3303 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3304 else 3305 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3306 EVT); 3307 3308 // Remember that we legalized the chain. 3309 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3310 3311 // The high part is undefined. 3312 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT)); 3313 Lo = LegalizeOp(Lo); 3314 break; 3315 } 3316 case ISD::ANY_EXTEND: { 3317 SDOperand In; 3318 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3319 case Expand: assert(0 && "expand-expand not implemented yet!"); 3320 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3321 case Promote: 3322 In = PromoteOp(Node->getOperand(0)); 3323 break; 3324 } 3325 3326 // The low part is any extension of the input (which degenerates to a copy). 3327 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In); 3328 // The high part is undefined. 3329 Hi = DAG.getNode(ISD::UNDEF, NVT); 3330 break; 3331 } 3332 case ISD::SIGN_EXTEND: { 3333 SDOperand In; 3334 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3335 case Expand: assert(0 && "expand-expand not implemented yet!"); 3336 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3337 case Promote: 3338 In = PromoteOp(Node->getOperand(0)); 3339 // Emit the appropriate sign_extend_inreg to get the value we want. 3340 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 3341 DAG.getValueType(Node->getOperand(0).getValueType())); 3342 break; 3343 } 3344 3345 // The low part is just a sign extension of the input (which degenerates to 3346 // a copy). 3347 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 3348 3349 // The high part is obtained by SRA'ing all but one of the bits of the lo 3350 // part. 3351 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3352 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3353 TLI.getShiftAmountTy())); 3354 break; 3355 } 3356 case ISD::ZERO_EXTEND: { 3357 SDOperand In; 3358 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3359 case Expand: assert(0 && "expand-expand not implemented yet!"); 3360 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3361 case Promote: 3362 In = PromoteOp(Node->getOperand(0)); 3363 // Emit the appropriate zero_extend_inreg to get the value we want. 3364 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType()); 3365 break; 3366 } 3367 3368 // The low part is just a zero extension of the input (which degenerates to 3369 // a copy). 3370 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 3371 3372 // The high part is just a zero. 3373 Hi = DAG.getConstant(0, NVT); 3374 break; 3375 } 3376 3377 case ISD::READCYCLECOUNTER: { 3378 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 3379 TargetLowering::Custom && 3380 "Must custom expand ReadCycleCounter"); 3381 SDOperand T = TLI.LowerOperation(Op, DAG); 3382 assert(T.Val && "Node must be custom expanded!"); 3383 Lo = LegalizeOp(T.getValue(0)); 3384 Hi = LegalizeOp(T.getValue(1)); 3385 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 3386 LegalizeOp(T.getValue(2))); 3387 break; 3388 } 3389 3390 // These operators cannot be expanded directly, emit them as calls to 3391 // library functions. 3392 case ISD::FP_TO_SINT: 3393 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 3394 SDOperand Op; 3395 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3396 case Expand: assert(0 && "cannot expand FP!"); 3397 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3398 case Promote: Op = PromoteOp(Node->getOperand(0)); break; 3399 } 3400 3401 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 3402 3403 // Now that the custom expander is done, expand the result, which is still 3404 // VT. 3405 if (Op.Val) { 3406 ExpandOp(Op, Lo, Hi); 3407 break; 3408 } 3409 } 3410 3411 if (Node->getOperand(0).getValueType() == MVT::f32) 3412 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 3413 else 3414 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 3415 break; 3416 3417 case ISD::FP_TO_UINT: 3418 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 3419 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, 3420 LegalizeOp(Node->getOperand(0))); 3421 // Now that the custom expander is done, expand the result, which is still 3422 // VT. 3423 Op = TLI.LowerOperation(Op, DAG); 3424 if (Op.Val) { 3425 ExpandOp(Op, Lo, Hi); 3426 break; 3427 } 3428 } 3429 3430 if (Node->getOperand(0).getValueType() == MVT::f32) 3431 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 3432 else 3433 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 3434 break; 3435 3436 case ISD::SHL: 3437 // If the target wants custom lowering, do so. 3438 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 3439 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), 3440 LegalizeOp(Node->getOperand(1))); 3441 Op = TLI.LowerOperation(Op, DAG); 3442 if (Op.Val) { 3443 // Now that the custom expander is done, expand the result, which is 3444 // still VT. 3445 ExpandOp(Op, Lo, Hi); 3446 break; 3447 } 3448 } 3449 3450 // If we can emit an efficient shift operation, do so now. 3451 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3452 break; 3453 3454 // If this target supports SHL_PARTS, use it. 3455 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) { 3456 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 3457 Lo, Hi); 3458 break; 3459 } 3460 3461 // Otherwise, emit a libcall. 3462 Lo = ExpandLibCall("__ashldi3", Node, Hi); 3463 break; 3464 3465 case ISD::SRA: 3466 // If the target wants custom lowering, do so. 3467 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 3468 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), 3469 LegalizeOp(Node->getOperand(1))); 3470 Op = TLI.LowerOperation(Op, DAG); 3471 if (Op.Val) { 3472 // Now that the custom expander is done, expand the result, which is 3473 // still VT. 3474 ExpandOp(Op, Lo, Hi); 3475 break; 3476 } 3477 } 3478 3479 // If we can emit an efficient shift operation, do so now. 3480 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3481 break; 3482 3483 // If this target supports SRA_PARTS, use it. 3484 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) { 3485 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 3486 Lo, Hi); 3487 break; 3488 } 3489 3490 // Otherwise, emit a libcall. 3491 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 3492 break; 3493 case ISD::SRL: 3494 // If the target wants custom lowering, do so. 3495 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 3496 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), 3497 LegalizeOp(Node->getOperand(1))); 3498 Op = TLI.LowerOperation(Op, DAG); 3499 if (Op.Val) { 3500 // Now that the custom expander is done, expand the result, which is 3501 // still VT. 3502 ExpandOp(Op, Lo, Hi); 3503 break; 3504 } 3505 } 3506 3507 // If we can emit an efficient shift operation, do so now. 3508 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3509 break; 3510 3511 // If this target supports SRL_PARTS, use it. 3512 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) { 3513 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 3514 Lo, Hi); 3515 break; 3516 } 3517 3518 // Otherwise, emit a libcall. 3519 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 3520 break; 3521 3522 case ISD::ADD: 3523 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 3524 Lo, Hi); 3525 break; 3526 case ISD::SUB: 3527 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 3528 Lo, Hi); 3529 break; 3530 case ISD::MUL: { 3531 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 3532 SDOperand LL, LH, RL, RH; 3533 ExpandOp(Node->getOperand(0), LL, LH); 3534 ExpandOp(Node->getOperand(1), RL, RH); 3535 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 3536 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 3537 // extended the sign bit of the low half through the upper half, and if so 3538 // emit a MULHS instead of the alternate sequence that is valid for any 3539 // i64 x i64 multiply. 3540 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 3541 // is RH an extension of the sign bit of RL? 3542 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 3543 RH.getOperand(1).getOpcode() == ISD::Constant && 3544 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 3545 // is LH an extension of the sign bit of LL? 3546 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 3547 LH.getOperand(1).getOpcode() == ISD::Constant && 3548 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 3549 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 3550 } else { 3551 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 3552 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 3553 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 3554 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 3555 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 3556 } 3557 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 3558 } else { 3559 Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 3560 } 3561 break; 3562 } 3563 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 3564 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 3565 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 3566 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 3567 } 3568 3569 // Remember in a map if the values will be reused later. 3570 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 3571 std::make_pair(Lo, Hi))).second; 3572 assert(isNew && "Value already expanded?!?"); 3573} 3574 3575 3576// SelectionDAG::Legalize - This is the entry point for the file. 3577// 3578void SelectionDAG::Legalize() { 3579 /// run - This is the main entry point to this class. 3580 /// 3581 SelectionDAGLegalize(*this).Run(); 3582} 3583 3584