LegalizeDAG.cpp revision 70814bc38435d61a8c7cc32f2375c09e21f12a8a
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 /// LegalizeAction - This enum indicates what action we should take for each 45 /// value type the can occur in the program. 46 enum LegalizeAction { 47 Legal, // The target natively supports this value type. 48 Promote, // This should be promoted to the next larger type. 49 Expand, // This integer type should be broken into smaller pieces. 50 }; 51 52 /// ValueTypeActions - This is a bitvector that contains two bits for each 53 /// value type, where the two bits correspond to the LegalizeAction enum. 54 /// This can be queried with "getTypeAction(VT)". 55 unsigned long long ValueTypeActions; 56 57 /// LegalizedNodes - For nodes that are of legal width, and that have more 58 /// than one use, this map indicates what regularized operand to use. This 59 /// allows us to avoid legalizing the same thing more than once. 60 std::map<SDOperand, SDOperand> LegalizedNodes; 61 62 /// PromotedNodes - For nodes that are below legal width, and that have more 63 /// than one use, this map indicates what promoted value to use. This allows 64 /// us to avoid promoting the same thing more than once. 65 std::map<SDOperand, SDOperand> PromotedNodes; 66 67 /// ExpandedNodes - For nodes that need to be expanded, and which have more 68 /// than one use, this map indicates which which operands are the expanded 69 /// version of the input. This allows us to avoid expanding the same node 70 /// more than once. 71 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 72 73 void AddLegalizedOperand(SDOperand From, SDOperand To) { 74 LegalizedNodes.insert(std::make_pair(From, To)); 75 // If someone requests legalization of the new node, return itself. 76 if (From != To) 77 LegalizedNodes.insert(std::make_pair(To, To)); 78 } 79 void AddPromotedOperand(SDOperand From, SDOperand To) { 80 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 81 assert(isNew && "Got into the map somehow?"); 82 // If someone requests legalization of the new node, return itself. 83 LegalizedNodes.insert(std::make_pair(To, To)); 84 } 85 86public: 87 88 SelectionDAGLegalize(SelectionDAG &DAG); 89 90 /// getTypeAction - Return how we should legalize values of this type, either 91 /// it is already legal or we need to expand it into multiple registers of 92 /// smaller integer type, or we need to promote it to a larger type. 93 LegalizeAction getTypeAction(MVT::ValueType VT) const { 94 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 95 } 96 97 /// isTypeLegal - Return true if this type is legal on this target. 98 /// 99 bool isTypeLegal(MVT::ValueType VT) const { 100 return getTypeAction(VT) == Legal; 101 } 102 103 void LegalizeDAG(); 104 105private: 106 107 SDOperand LegalizeOp(SDOperand O); 108 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 109 SDOperand PromoteOp(SDOperand O); 110 111 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 112 SDOperand &Hi); 113 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 114 SDOperand Source); 115 116 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 117 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 118 SDOperand LegalOp, 119 MVT::ValueType DestVT); 120 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 121 bool isSigned); 122 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 123 bool isSigned); 124 125 SDOperand ExpandBSWAP(SDOperand Op); 126 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 127 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 128 SDOperand &Lo, SDOperand &Hi); 129 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 130 SDOperand &Lo, SDOperand &Hi); 131 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 132 133 SDOperand getIntPtrConstant(uint64_t Val) { 134 return DAG.getConstant(Val, TLI.getPointerTy()); 135 } 136}; 137} 138 139static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 140 switch (VecOp) { 141 default: assert(0 && "Don't know how to scalarize this opcode!"); 142 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 143 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 144 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 145 } 146} 147 148SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 149 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 150 ValueTypeActions(TLI.getValueTypeActions()) { 151 assert(MVT::LAST_VALUETYPE <= 32 && 152 "Too many value types for ValueTypeActions to hold!"); 153} 154 155/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 156/// not been visited yet and if all of its operands have already been visited. 157static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 158 std::map<SDNode*, unsigned> &Visited) { 159 if (++Visited[N] != N->getNumOperands()) 160 return; // Haven't visited all operands yet 161 162 Order.push_back(N); 163 164 if (N->hasOneUse()) { // Tail recurse in common case. 165 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 166 return; 167 } 168 169 // Now that we have N in, add anything that uses it if all of their operands 170 // are now done. 171 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 172 ComputeTopDownOrdering(*UI, Order, Visited); 173} 174 175 176void SelectionDAGLegalize::LegalizeDAG() { 177 // The legalize process is inherently a bottom-up recursive process (users 178 // legalize their uses before themselves). Given infinite stack space, we 179 // could just start legalizing on the root and traverse the whole graph. In 180 // practice however, this causes us to run out of stack space on large basic 181 // blocks. To avoid this problem, compute an ordering of the nodes where each 182 // node is only legalized after all of its operands are legalized. 183 std::map<SDNode*, unsigned> Visited; 184 std::vector<SDNode*> Order; 185 186 // Compute ordering from all of the leaves in the graphs, those (like the 187 // entry node) that have no operands. 188 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 189 E = DAG.allnodes_end(); I != E; ++I) { 190 if (I->getNumOperands() == 0) { 191 Visited[I] = 0 - 1U; 192 ComputeTopDownOrdering(I, Order, Visited); 193 } 194 } 195 196 assert(Order.size() == Visited.size() && 197 Order.size() == 198 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 199 "Error: DAG is cyclic!"); 200 Visited.clear(); 201 202 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 203 SDNode *N = Order[i]; 204 switch (getTypeAction(N->getValueType(0))) { 205 default: assert(0 && "Bad type action!"); 206 case Legal: 207 LegalizeOp(SDOperand(N, 0)); 208 break; 209 case Promote: 210 PromoteOp(SDOperand(N, 0)); 211 break; 212 case Expand: { 213 SDOperand X, Y; 214 ExpandOp(SDOperand(N, 0), X, Y); 215 break; 216 } 217 } 218 } 219 220 // Finally, it's possible the root changed. Get the new root. 221 SDOperand OldRoot = DAG.getRoot(); 222 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 223 DAG.setRoot(LegalizedNodes[OldRoot]); 224 225 ExpandedNodes.clear(); 226 LegalizedNodes.clear(); 227 PromotedNodes.clear(); 228 229 // Remove dead nodes now. 230 DAG.RemoveDeadNodes(OldRoot.Val); 231} 232 233SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 234 assert(isTypeLegal(Op.getValueType()) && 235 "Caller should expand or promote operands that are not legal!"); 236 SDNode *Node = Op.Val; 237 238 // If this operation defines any values that cannot be represented in a 239 // register on this target, make sure to expand or promote them. 240 if (Node->getNumValues() > 1) { 241 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 242 switch (getTypeAction(Node->getValueType(i))) { 243 case Legal: break; // Nothing to do. 244 case Expand: { 245 SDOperand T1, T2; 246 ExpandOp(Op.getValue(i), T1, T2); 247 assert(LegalizedNodes.count(Op) && 248 "Expansion didn't add legal operands!"); 249 return LegalizedNodes[Op]; 250 } 251 case Promote: 252 PromoteOp(Op.getValue(i)); 253 assert(LegalizedNodes.count(Op) && 254 "Promotion didn't add legal operands!"); 255 return LegalizedNodes[Op]; 256 } 257 } 258 259 // Note that LegalizeOp may be reentered even from single-use nodes, which 260 // means that we always must cache transformed nodes. 261 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 262 if (I != LegalizedNodes.end()) return I->second; 263 264 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 265 SDOperand Result = Op; 266 bool isCustom = false; 267 268 switch (Node->getOpcode()) { 269 case ISD::FrameIndex: 270 case ISD::EntryToken: 271 case ISD::Register: 272 case ISD::BasicBlock: 273 case ISD::TargetFrameIndex: 274 case ISD::TargetConstant: 275 case ISD::TargetConstantFP: 276 case ISD::TargetConstantVec: 277 case ISD::TargetConstantPool: 278 case ISD::TargetGlobalAddress: 279 case ISD::TargetExternalSymbol: 280 case ISD::VALUETYPE: 281 case ISD::SRCVALUE: 282 case ISD::STRING: 283 case ISD::CONDCODE: 284 // Primitives must all be legal. 285 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 286 "This must be legal!"); 287 break; 288 default: 289 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 290 // If this is a target node, legalize it by legalizing the operands then 291 // passing it through. 292 std::vector<SDOperand> Ops; 293 bool Changed = false; 294 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 295 Ops.push_back(LegalizeOp(Node->getOperand(i))); 296 Changed = Changed || Node->getOperand(i) != Ops.back(); 297 } 298 if (Changed) 299 if (Node->getNumValues() == 1) 300 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 301 else { 302 std::vector<MVT::ValueType> VTs(Node->value_begin(), 303 Node->value_end()); 304 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 305 } 306 307 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 308 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 309 return Result.getValue(Op.ResNo); 310 } 311 // Otherwise this is an unhandled builtin node. splat. 312 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 313 assert(0 && "Do not know how to legalize this operator!"); 314 abort(); 315 case ISD::GlobalAddress: 316 case ISD::ExternalSymbol: 317 case ISD::ConstantPool: // Nothing to do. 318 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 319 default: assert(0 && "This action is not supported yet!"); 320 case TargetLowering::Custom: 321 Tmp1 = TLI.LowerOperation(Op, DAG); 322 if (Tmp1.Val) Result = Tmp1; 323 // FALLTHROUGH if the target doesn't want to lower this op after all. 324 case TargetLowering::Legal: 325 break; 326 } 327 break; 328 case ISD::AssertSext: 329 case ISD::AssertZext: 330 Tmp1 = LegalizeOp(Node->getOperand(0)); 331 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 332 break; 333 case ISD::MERGE_VALUES: 334 // Legalize eliminates MERGE_VALUES nodes. 335 Result = Node->getOperand(Op.ResNo); 336 break; 337 case ISD::CopyFromReg: 338 Tmp1 = LegalizeOp(Node->getOperand(0)); 339 Result = Op.getValue(0); 340 if (Node->getNumValues() == 2) { 341 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 342 } else { 343 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 344 if (Node->getNumOperands() == 3) { 345 Tmp2 = LegalizeOp(Node->getOperand(2)); 346 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 347 } else { 348 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 349 } 350 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 351 } 352 // Since CopyFromReg produces two values, make sure to remember that we 353 // legalized both of them. 354 AddLegalizedOperand(Op.getValue(0), Result); 355 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 356 return Result.getValue(Op.ResNo); 357 case ISD::UNDEF: { 358 MVT::ValueType VT = Op.getValueType(); 359 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 360 default: assert(0 && "This action is not supported yet!"); 361 case TargetLowering::Expand: 362 if (MVT::isInteger(VT)) 363 Result = DAG.getConstant(0, VT); 364 else if (MVT::isFloatingPoint(VT)) 365 Result = DAG.getConstantFP(0, VT); 366 else 367 assert(0 && "Unknown value type!"); 368 break; 369 case TargetLowering::Legal: 370 break; 371 } 372 break; 373 } 374 375 case ISD::LOCATION: 376 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 377 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 378 379 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 380 case TargetLowering::Promote: 381 default: assert(0 && "This action is not supported yet!"); 382 case TargetLowering::Expand: { 383 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 384 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 385 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other); 386 387 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) { 388 const std::string &FName = 389 cast<StringSDNode>(Node->getOperand(3))->getValue(); 390 const std::string &DirName = 391 cast<StringSDNode>(Node->getOperand(4))->getValue(); 392 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName); 393 394 std::vector<SDOperand> Ops; 395 Ops.push_back(Tmp1); // chain 396 SDOperand LineOp = Node->getOperand(1); 397 SDOperand ColOp = Node->getOperand(2); 398 399 if (useDEBUG_LOC) { 400 Ops.push_back(LineOp); // line # 401 Ops.push_back(ColOp); // col # 402 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 403 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops); 404 } else { 405 unsigned Line = dyn_cast<ConstantSDNode>(LineOp)->getValue(); 406 unsigned Col = dyn_cast<ConstantSDNode>(ColOp)->getValue(); 407 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile); 408 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 409 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops); 410 } 411 } else { 412 Result = Tmp1; // chain 413 } 414 break; 415 } 416 case TargetLowering::Legal: 417 if (Tmp1 != Node->getOperand(0) || 418 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 419 std::vector<SDOperand> Ops; 420 Ops.push_back(Tmp1); 421 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 422 Ops.push_back(Node->getOperand(1)); // line # must be legal. 423 Ops.push_back(Node->getOperand(2)); // col # must be legal. 424 } else { 425 // Otherwise promote them. 426 Ops.push_back(PromoteOp(Node->getOperand(1))); 427 Ops.push_back(PromoteOp(Node->getOperand(2))); 428 } 429 Ops.push_back(Node->getOperand(3)); // filename must be legal. 430 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 431 Result = DAG.UpdateNodeOperands(Result, Ops); 432 } 433 break; 434 } 435 break; 436 437 case ISD::DEBUG_LOC: 438 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 439 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 440 default: assert(0 && "This action is not supported yet!"); 441 case TargetLowering::Legal: 442 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 443 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 444 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 445 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 446 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 447 break; 448 } 449 break; 450 451 case ISD::DEBUG_LABEL: 452 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!"); 453 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) { 454 default: assert(0 && "This action is not supported yet!"); 455 case TargetLowering::Legal: 456 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 457 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 458 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 459 break; 460 } 461 break; 462 463 case ISD::Constant: 464 // We know we don't need to expand constants here, constants only have one 465 // value and we check that it is fine above. 466 467 // FIXME: Maybe we should handle things like targets that don't support full 468 // 32-bit immediates? 469 break; 470 case ISD::ConstantFP: { 471 // Spill FP immediates to the constant pool if the target cannot directly 472 // codegen them. Targets often have some immediate values that can be 473 // efficiently generated into an FP register without a load. We explicitly 474 // leave these constants as ConstantFP nodes for the target to deal with. 475 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 476 477 // Check to see if this FP immediate is already legal. 478 bool isLegal = false; 479 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 480 E = TLI.legal_fpimm_end(); I != E; ++I) 481 if (CFP->isExactlyValue(*I)) { 482 isLegal = true; 483 break; 484 } 485 486 // If this is a legal constant, turn it into a TargetConstantFP node. 487 if (isLegal) { 488 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0)); 489 break; 490 } 491 492 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 493 default: assert(0 && "This action is not supported yet!"); 494 case TargetLowering::Custom: 495 Tmp3 = TLI.LowerOperation(Result, DAG); 496 if (Tmp3.Val) { 497 Result = Tmp3; 498 break; 499 } 500 // FALLTHROUGH 501 case TargetLowering::Expand: 502 // Otherwise we need to spill the constant to memory. 503 bool Extend = false; 504 505 // If a FP immediate is precise when represented as a float and if the 506 // target can do an extending load from float to double, we put it into 507 // the constant pool as a float, even if it's is statically typed as a 508 // double. 509 MVT::ValueType VT = CFP->getValueType(0); 510 bool isDouble = VT == MVT::f64; 511 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 512 Type::FloatTy, CFP->getValue()); 513 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 514 // Only do this if the target has a native EXTLOAD instruction from 515 // f32. 516 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 517 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 518 VT = MVT::f32; 519 Extend = true; 520 } 521 522 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 523 if (Extend) { 524 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 525 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 526 } else { 527 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 528 DAG.getSrcValue(NULL)); 529 } 530 } 531 break; 532 } 533 case ISD::ConstantVec: 534 switch (TLI.getOperationAction(ISD::ConstantVec, Node->getValueType(0))) { 535 default: assert(0 && "This action is not supported yet!"); 536 case TargetLowering::Custom: 537 Tmp3 = TLI.LowerOperation(Result, DAG); 538 if (Tmp3.Val) { 539 Result = Tmp3; 540 break; 541 } 542 // FALLTHROUGH 543 case TargetLowering::Expand: 544 // We assume that vector constants are not legal, and will be immediately 545 // spilled to the constant pool. 546 // 547 // Create a ConstantPacked, and put it in the constant pool. 548 MVT::ValueType VT = Node->getValueType(0); 549 const Type *OpNTy = 550 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 551 std::vector<Constant*> CV; 552 if (MVT::isFloatingPoint(VT)) { 553 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 554 double V = cast<ConstantFPSDNode>(Node->getOperand(i))->getValue(); 555 CV.push_back(ConstantFP::get(OpNTy, V)); 556 } 557 } else { 558 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 559 uint64_t V = cast<ConstantSDNode>(Node->getOperand(i))->getValue(); 560 CV.push_back(ConstantUInt::get(OpNTy, V)); 561 } 562 } 563 Constant *CP = ConstantPacked::get(CV); 564 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 565 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 566 DAG.getSrcValue(NULL)); 567 break; 568 } 569 break; 570 case ISD::TokenFactor: 571 if (Node->getNumOperands() == 2) { 572 Tmp1 = LegalizeOp(Node->getOperand(0)); 573 Tmp2 = LegalizeOp(Node->getOperand(1)); 574 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 575 } else if (Node->getNumOperands() == 3) { 576 Tmp1 = LegalizeOp(Node->getOperand(0)); 577 Tmp2 = LegalizeOp(Node->getOperand(1)); 578 Tmp3 = LegalizeOp(Node->getOperand(2)); 579 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 580 } else { 581 std::vector<SDOperand> Ops; 582 // Legalize the operands. 583 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 584 Ops.push_back(LegalizeOp(Node->getOperand(i))); 585 Result = DAG.UpdateNodeOperands(Result, Ops); 586 } 587 break; 588 589 case ISD::CALLSEQ_START: 590 case ISD::CALLSEQ_END: 591 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 592 // Do not try to legalize the target-specific arguments (#1+), except for 593 // an optional flag input. 594 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 595 if (Tmp1 != Node->getOperand(0)) { 596 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 597 Ops[0] = Tmp1; 598 Result = DAG.UpdateNodeOperands(Result, Ops); 599 } 600 } else { 601 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 602 if (Tmp1 != Node->getOperand(0) || 603 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 604 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 605 Ops[0] = Tmp1; 606 Ops.back() = Tmp2; 607 Result = DAG.UpdateNodeOperands(Result, Ops); 608 } 609 } 610 break; 611 case ISD::DYNAMIC_STACKALLOC: { 612 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 613 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 614 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 615 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 616 617 Tmp1 = Result.getValue(0); 618 Tmp2 = Result.getValue(1); 619 switch (TLI.getOperationAction(Node->getOpcode(), 620 Node->getValueType(0))) { 621 default: assert(0 && "This action is not supported yet!"); 622 case TargetLowering::Expand: { 623 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 624 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 625 " not tell us which reg is the stack pointer!"); 626 SDOperand Chain = Tmp1.getOperand(0); 627 SDOperand Size = Tmp2.getOperand(1); 628 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0)); 629 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value 630 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain 631 Tmp1 = LegalizeOp(Tmp1); 632 Tmp2 = LegalizeOp(Tmp2); 633 break; 634 } 635 case TargetLowering::Custom: 636 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 637 if (Tmp3.Val) { 638 Tmp1 = LegalizeOp(Tmp3); 639 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 640 } 641 break; 642 case TargetLowering::Legal: 643 break; 644 } 645 // Since this op produce two values, make sure to remember that we 646 // legalized both of them. 647 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 648 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 649 return Op.ResNo ? Tmp2 : Tmp1; 650 } 651 case ISD::INLINEASM: 652 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize Chain. 653 Tmp2 = Node->getOperand(Node->getNumOperands()-1); 654 if (Tmp2.getValueType() == MVT::Flag) // Legalize Flag if it exists. 655 Tmp2 = Tmp3 = SDOperand(0, 0); 656 else 657 Tmp3 = LegalizeOp(Tmp2); 658 659 if (Tmp1 != Node->getOperand(0) || Tmp2 != Tmp3) { 660 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 661 Ops[0] = Tmp1; 662 if (Tmp3.Val) Ops.back() = Tmp3; 663 Result = DAG.UpdateNodeOperands(Result, Ops); 664 } 665 666 // INLINE asm returns a chain and flag, make sure to add both to the map. 667 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 668 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 669 return Result.getValue(Op.ResNo); 670 case ISD::BR: 671 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 672 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 673 break; 674 675 case ISD::BRCOND: 676 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 677 678 switch (getTypeAction(Node->getOperand(1).getValueType())) { 679 case Expand: assert(0 && "It's impossible to expand bools"); 680 case Legal: 681 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 682 break; 683 case Promote: 684 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 685 break; 686 } 687 688 // Basic block destination (Op#2) is always legal. 689 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 690 691 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 692 default: assert(0 && "This action is not supported yet!"); 693 case TargetLowering::Legal: break; 694 case TargetLowering::Custom: 695 Tmp1 = TLI.LowerOperation(Result, DAG); 696 if (Tmp1.Val) Result = Tmp1; 697 break; 698 case TargetLowering::Expand: 699 // Expand brcond's setcc into its constituent parts and create a BR_CC 700 // Node. 701 if (Tmp2.getOpcode() == ISD::SETCC) { 702 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 703 Tmp2.getOperand(0), Tmp2.getOperand(1), 704 Node->getOperand(2)); 705 } else { 706 // Make sure the condition is either zero or one. It may have been 707 // promoted from something else. 708 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 709 710 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 711 DAG.getCondCode(ISD::SETNE), Tmp2, 712 DAG.getConstant(0, Tmp2.getValueType()), 713 Node->getOperand(2)); 714 } 715 break; 716 } 717 break; 718 case ISD::BR_CC: 719 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 720 if (!isTypeLegal(Node->getOperand(2).getValueType())) { 721 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 722 Node->getOperand(2), // LHS 723 Node->getOperand(3), // RHS 724 Node->getOperand(1))); 725 // If we get a SETCC back from legalizing the SETCC node we just 726 // created, then use its LHS, RHS, and CC directly in creating a new 727 // node. Otherwise, select between the true and false value based on 728 // comparing the result of the legalized with zero. 729 if (Tmp2.getOpcode() == ISD::SETCC) { 730 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 731 Tmp2.getOperand(0), Tmp2.getOperand(1), 732 Node->getOperand(4)); 733 } else { 734 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 735 DAG.getCondCode(ISD::SETNE), 736 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 737 Node->getOperand(4)); 738 } 739 break; 740 } 741 742 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 743 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 744 745 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 746 Tmp3, Node->getOperand(4)); 747 748 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 749 default: assert(0 && "Unexpected action for BR_CC!"); 750 case TargetLowering::Legal: break; 751 case TargetLowering::Custom: 752 Tmp4 = TLI.LowerOperation(Result, DAG); 753 if (Tmp4.Val) Result = Tmp4; 754 break; 755 } 756 break; 757 case ISD::BRCONDTWOWAY: 758 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 759 switch (getTypeAction(Node->getOperand(1).getValueType())) { 760 case Expand: assert(0 && "It's impossible to expand bools"); 761 case Legal: 762 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 763 break; 764 case Promote: 765 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 766 break; 767 } 768 769 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 770 // pair. 771 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 772 case TargetLowering::Promote: 773 default: assert(0 && "This action is not supported yet!"); 774 case TargetLowering::Legal: 775 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), 776 Node->getOperand(3)); 777 break; 778 case TargetLowering::Expand: 779 // If BRTWOWAY_CC is legal for this target, then simply expand this node 780 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 781 // BRCOND/BR pair. 782 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 783 if (Tmp2.getOpcode() == ISD::SETCC) { 784 Tmp3 = Tmp2.getOperand(0); 785 Tmp4 = Tmp2.getOperand(1); 786 Tmp2 = Tmp2.getOperand(2); 787 } else { 788 Tmp3 = Tmp2; 789 Tmp4 = DAG.getConstant(0, Tmp2.getValueType()); 790 Tmp2 = DAG.getCondCode(ISD::SETNE); 791 } 792 std::vector<SDOperand> Ops; 793 Ops.push_back(Tmp1); 794 Ops.push_back(Tmp2); 795 Ops.push_back(Tmp3); 796 Ops.push_back(Tmp4); 797 Ops.push_back(Node->getOperand(2)); 798 Ops.push_back(Node->getOperand(3)); 799 Result = DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); 800 } else { 801 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 802 Node->getOperand(2)); 803 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 804 } 805 break; 806 } 807 break; 808 case ISD::BRTWOWAY_CC: 809 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 810 if (isTypeLegal(Node->getOperand(2).getValueType())) { 811 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 812 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 813 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 814 Tmp3 != Node->getOperand(3)) { 815 std::vector<SDOperand> Ops; 816 Ops.push_back(Tmp1); 817 Ops.push_back(Node->getOperand(1)); 818 Ops.push_back(Tmp2); 819 Ops.push_back(Tmp3); 820 Ops.push_back(Node->getOperand(4)); 821 Ops.push_back(Node->getOperand(5)); 822 Result = DAG.UpdateNodeOperands(Result, Ops); 823 } 824 break; 825 } else { 826 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 827 Node->getOperand(2), // LHS 828 Node->getOperand(3), // RHS 829 Node->getOperand(1))); 830 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 831 // pair. 832 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 833 default: assert(0 && "This action is not supported yet!"); 834 case TargetLowering::Legal: { 835 // If we get a SETCC back from legalizing the SETCC node we just 836 // created, then use its LHS, RHS, and CC directly in creating a new 837 // node. Otherwise, select between the true and false value based on 838 // comparing the result of the legalized with zero. 839 std::vector<SDOperand> Ops; 840 Ops.push_back(Tmp1); 841 if (Tmp2.getOpcode() == ISD::SETCC) { 842 Ops.push_back(Tmp2.getOperand(2)); 843 Ops.push_back(Tmp2.getOperand(0)); 844 Ops.push_back(Tmp2.getOperand(1)); 845 } else { 846 Ops.push_back(DAG.getCondCode(ISD::SETNE)); 847 Ops.push_back(Tmp2); 848 Ops.push_back(DAG.getConstant(0, Tmp2.getValueType())); 849 } 850 Ops.push_back(Node->getOperand(4)); 851 Ops.push_back(Node->getOperand(5)); 852 Result = DAG.UpdateNodeOperands(Result, Ops); 853 break; 854 } 855 case TargetLowering::Expand: 856 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 857 Node->getOperand(4)); 858 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 859 break; 860 } 861 } 862 break; 863 case ISD::LOAD: { 864 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 865 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 866 867 MVT::ValueType VT = Node->getValueType(0); 868 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 869 Tmp2 = Result.getValue(0); 870 Tmp3 = Result.getValue(1); 871 872 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 873 default: assert(0 && "This action is not supported yet!"); 874 case TargetLowering::Legal: break; 875 case TargetLowering::Custom: 876 Tmp1 = TLI.LowerOperation(Tmp2, DAG); 877 if (Tmp1.Val) { 878 Tmp2 = LegalizeOp(Tmp1); 879 Tmp3 = LegalizeOp(Tmp1.getValue(1)); 880 } 881 break; 882 } 883 // Since loads produce two values, make sure to remember that we 884 // legalized both of them. 885 AddLegalizedOperand(SDOperand(Node, 0), Tmp2); 886 AddLegalizedOperand(SDOperand(Node, 1), Tmp3); 887 return Op.ResNo ? Tmp3 : Tmp2; 888 } 889 case ISD::EXTLOAD: 890 case ISD::SEXTLOAD: 891 case ISD::ZEXTLOAD: { 892 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 893 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 894 895 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 896 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 897 default: assert(0 && "This action is not supported yet!"); 898 case TargetLowering::Promote: 899 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 900 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), 901 DAG.getValueType(MVT::i8)); 902 Tmp1 = Result.getValue(0); 903 Tmp2 = Result.getValue(1); 904 break; 905 case TargetLowering::Custom: 906 isCustom = true; 907 // FALLTHROUGH 908 case TargetLowering::Legal: 909 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), 910 Node->getOperand(3)); 911 Tmp1 = Result.getValue(0); 912 Tmp2 = Result.getValue(1); 913 914 if (isCustom) { 915 Tmp3 = TLI.LowerOperation(Tmp3, DAG); 916 if (Tmp3.Val) { 917 Tmp1 = LegalizeOp(Tmp3); 918 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 919 } 920 } 921 break; 922 case TargetLowering::Expand: 923 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 924 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 925 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 926 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 927 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 928 Tmp2 = LegalizeOp(Load.getValue(1)); 929 break; 930 } 931 assert(Node->getOpcode() != ISD::EXTLOAD && 932 "EXTLOAD should always be supported!"); 933 // Turn the unsupported load into an EXTLOAD followed by an explicit 934 // zero/sign extend inreg. 935 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 936 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 937 SDOperand ValRes; 938 if (Node->getOpcode() == ISD::SEXTLOAD) 939 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 940 Result, DAG.getValueType(SrcVT)); 941 else 942 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 943 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 944 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 945 break; 946 } 947 // Since loads produce two values, make sure to remember that we legalized 948 // both of them. 949 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 950 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 951 return Op.ResNo ? Tmp2 : Tmp1; 952 } 953 case ISD::EXTRACT_ELEMENT: { 954 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 955 switch (getTypeAction(OpTy)) { 956 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 957 case Legal: 958 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 959 // 1 -> Hi 960 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 961 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 962 TLI.getShiftAmountTy())); 963 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 964 } else { 965 // 0 -> Lo 966 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 967 Node->getOperand(0)); 968 } 969 break; 970 case Expand: 971 // Get both the low and high parts. 972 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 973 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 974 Result = Tmp2; // 1 -> Hi 975 else 976 Result = Tmp1; // 0 -> Lo 977 break; 978 } 979 break; 980 } 981 982 case ISD::CopyToReg: 983 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 984 985 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 986 "Register type must be legal!"); 987 // Legalize the incoming value (must be a legal type). 988 Tmp2 = LegalizeOp(Node->getOperand(2)); 989 if (Node->getNumValues() == 1) { 990 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 991 } else { 992 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 993 if (Node->getNumOperands() == 4) { 994 Tmp3 = LegalizeOp(Node->getOperand(3)); 995 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 996 Tmp3); 997 } else { 998 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 999 } 1000 1001 // Since this produces two values, make sure to remember that we legalized 1002 // both of them. 1003 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1004 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1005 return Result; 1006 } 1007 break; 1008 1009 case ISD::RET: 1010 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1011 switch (Node->getNumOperands()) { 1012 case 2: // ret val 1013 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1014 case Legal: 1015 Tmp2 = LegalizeOp(Node->getOperand(1)); 1016 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1017 break; 1018 case Expand: { 1019 SDOperand Lo, Hi; 1020 ExpandOp(Node->getOperand(1), Lo, Hi); 1021 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1022 break; 1023 } 1024 case Promote: 1025 Tmp2 = PromoteOp(Node->getOperand(1)); 1026 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1027 Result = LegalizeOp(Result); 1028 break; 1029 } 1030 break; 1031 case 1: // ret void 1032 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1033 break; 1034 default: { // ret <values> 1035 std::vector<SDOperand> NewValues; 1036 NewValues.push_back(Tmp1); 1037 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1038 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1039 case Legal: 1040 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1041 break; 1042 case Expand: { 1043 SDOperand Lo, Hi; 1044 ExpandOp(Node->getOperand(i), Lo, Hi); 1045 NewValues.push_back(Lo); 1046 NewValues.push_back(Hi); 1047 break; 1048 } 1049 case Promote: 1050 assert(0 && "Can't promote multiple return value yet!"); 1051 } 1052 1053 if (NewValues.size() == Node->getNumOperands()) 1054 Result = DAG.UpdateNodeOperands(Result, NewValues); 1055 else 1056 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1057 break; 1058 } 1059 } 1060 1061 switch (TLI.getOperationAction(Node->getOpcode(), 1062 Node->getValueType(0))) { 1063 default: assert(0 && "This action is not supported yet!"); 1064 case TargetLowering::Legal: break; 1065 case TargetLowering::Custom: 1066 Tmp1 = TLI.LowerOperation(Result, DAG); 1067 if (Tmp1.Val) Result = Tmp1; 1068 break; 1069 } 1070 break; 1071 case ISD::STORE: { 1072 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1073 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1074 1075 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1076 // FIXME: We shouldn't do this for TargetConstantFP's. 1077 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1078 if (CFP->getValueType(0) == MVT::f32) { 1079 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 1080 } else { 1081 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1082 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 1083 } 1084 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1085 Node->getOperand(3)); 1086 break; 1087 } 1088 1089 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1090 case Legal: { 1091 Tmp3 = LegalizeOp(Node->getOperand(1)); 1092 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1093 Node->getOperand(3)); 1094 1095 MVT::ValueType VT = Tmp3.getValueType(); 1096 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1097 default: assert(0 && "This action is not supported yet!"); 1098 case TargetLowering::Legal: break; 1099 case TargetLowering::Custom: 1100 Tmp1 = TLI.LowerOperation(Result, DAG); 1101 if (Tmp1.Val) Result = Tmp1; 1102 break; 1103 } 1104 break; 1105 } 1106 case Promote: 1107 // Truncate the value and store the result. 1108 Tmp3 = PromoteOp(Node->getOperand(1)); 1109 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1110 Node->getOperand(3), 1111 DAG.getValueType(Node->getOperand(1).getValueType())); 1112 break; 1113 1114 case Expand: 1115 SDOperand Lo, Hi; 1116 ExpandOp(Node->getOperand(1), Lo, Hi); 1117 1118 if (!TLI.isLittleEndian()) 1119 std::swap(Lo, Hi); 1120 1121 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1122 Node->getOperand(3)); 1123 // If this is a vector type, then we have to calculate the increment as 1124 // the product of the element size in bytes, and the number of elements 1125 // in the high half of the vector. 1126 unsigned IncrementSize; 1127 if (MVT::Vector == Hi.getValueType()) { 1128 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue(); 1129 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT(); 1130 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8; 1131 } else { 1132 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1133 } 1134 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1135 getIntPtrConstant(IncrementSize)); 1136 assert(isTypeLegal(Tmp2.getValueType()) && 1137 "Pointers must be legal!"); 1138 // FIXME: This sets the srcvalue of both halves to be the same, which is 1139 // wrong. 1140 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1141 Node->getOperand(3)); 1142 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1143 break; 1144 } 1145 break; 1146 } 1147 case ISD::PCMARKER: 1148 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1149 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1150 break; 1151 case ISD::STACKSAVE: 1152 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1153 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1154 Tmp1 = Result.getValue(0); 1155 Tmp2 = Result.getValue(1); 1156 1157 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 1158 default: assert(0 && "This action is not supported yet!"); 1159 case TargetLowering::Legal: break; 1160 case TargetLowering::Custom: 1161 Tmp3 = TLI.LowerOperation(Result, DAG); 1162 if (Tmp3.Val) { 1163 Tmp1 = LegalizeOp(Tmp3); 1164 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1165 } 1166 break; 1167 case TargetLowering::Expand: 1168 // Expand to CopyFromReg if the target set 1169 // StackPointerRegisterToSaveRestore. 1170 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1171 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 1172 Node->getValueType(0)); 1173 Tmp2 = Tmp1.getValue(1); 1174 } else { 1175 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 1176 Tmp2 = Node->getOperand(0); 1177 } 1178 break; 1179 } 1180 1181 // Since stacksave produce two values, make sure to remember that we 1182 // legalized both of them. 1183 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1184 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1185 return Op.ResNo ? Tmp2 : Tmp1; 1186 1187 case ISD::STACKRESTORE: 1188 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1189 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1190 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1191 1192 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 1193 default: assert(0 && "This action is not supported yet!"); 1194 case TargetLowering::Legal: break; 1195 case TargetLowering::Custom: 1196 Tmp1 = TLI.LowerOperation(Result, DAG); 1197 if (Tmp1.Val) Result = Tmp1; 1198 break; 1199 case TargetLowering::Expand: 1200 // Expand to CopyToReg if the target set 1201 // StackPointerRegisterToSaveRestore. 1202 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1203 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 1204 } else { 1205 Result = Tmp1; 1206 } 1207 break; 1208 } 1209 break; 1210 1211 case ISD::READCYCLECOUNTER: 1212 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1213 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1214 1215 // Since rdcc produce two values, make sure to remember that we legalized 1216 // both of them. 1217 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1218 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1219 return Result; 1220 1221 case ISD::TRUNCSTORE: { 1222 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1223 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1224 1225 assert(isTypeLegal(Node->getOperand(1).getValueType()) && 1226 "Cannot handle illegal TRUNCSTORE yet!"); 1227 Tmp2 = LegalizeOp(Node->getOperand(1)); 1228 1229 // The only promote case we handle is TRUNCSTORE:i1 X into 1230 // -> TRUNCSTORE:i8 (and X, 1) 1231 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1232 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1233 TargetLowering::Promote) { 1234 // Promote the bool to a mask then store. 1235 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1236 DAG.getConstant(1, Tmp2.getValueType())); 1237 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1238 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1239 1240 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1241 Tmp3 != Node->getOperand(2)) { 1242 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 1243 Node->getOperand(3), Node->getOperand(4)); 1244 } 1245 1246 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT(); 1247 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) { 1248 default: assert(0 && "This action is not supported yet!"); 1249 case TargetLowering::Legal: break; 1250 case TargetLowering::Custom: 1251 Tmp1 = TLI.LowerOperation(Result, DAG); 1252 if (Tmp1.Val) Result = Tmp1; 1253 break; 1254 } 1255 break; 1256 } 1257 case ISD::SELECT: 1258 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1259 case Expand: assert(0 && "It's impossible to expand bools"); 1260 case Legal: 1261 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1262 break; 1263 case Promote: 1264 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1265 break; 1266 } 1267 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1268 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1269 1270 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1271 1272 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1273 default: assert(0 && "This action is not supported yet!"); 1274 case TargetLowering::Legal: break; 1275 case TargetLowering::Custom: { 1276 Tmp1 = TLI.LowerOperation(Result, DAG); 1277 if (Tmp1.Val) Result = Tmp1; 1278 break; 1279 } 1280 case TargetLowering::Expand: 1281 if (Tmp1.getOpcode() == ISD::SETCC) { 1282 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1283 Tmp2, Tmp3, 1284 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1285 } else { 1286 // Make sure the condition is either zero or one. It may have been 1287 // promoted from something else. 1288 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1289 Result = DAG.getSelectCC(Tmp1, 1290 DAG.getConstant(0, Tmp1.getValueType()), 1291 Tmp2, Tmp3, ISD::SETNE); 1292 } 1293 break; 1294 case TargetLowering::Promote: { 1295 MVT::ValueType NVT = 1296 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1297 unsigned ExtOp, TruncOp; 1298 if (MVT::isInteger(Tmp2.getValueType())) { 1299 ExtOp = ISD::ANY_EXTEND; 1300 TruncOp = ISD::TRUNCATE; 1301 } else { 1302 ExtOp = ISD::FP_EXTEND; 1303 TruncOp = ISD::FP_ROUND; 1304 } 1305 // Promote each of the values to the new type. 1306 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1307 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1308 // Perform the larger operation, then round down. 1309 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1310 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1311 break; 1312 } 1313 } 1314 break; 1315 case ISD::SELECT_CC: 1316 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1317 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1318 1319 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1320 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1321 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1322 1323 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, 1324 Node->getOperand(4)); 1325 1326 // Everything is legal, see if we should expand this op or something. 1327 switch (TLI.getOperationAction(ISD::SELECT_CC, 1328 Node->getOperand(0).getValueType())) { 1329 default: assert(0 && "This action is not supported yet!"); 1330 case TargetLowering::Legal: break; 1331 case TargetLowering::Custom: 1332 Tmp1 = TLI.LowerOperation(Result, DAG); 1333 if (Tmp1.Val) Result = Tmp1; 1334 break; 1335 } 1336 break; 1337 } else { 1338 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1339 Node->getOperand(0), // LHS 1340 Node->getOperand(1), // RHS 1341 Node->getOperand(4))); 1342 // If we get a SETCC back from legalizing the SETCC node we just 1343 // created, then use its LHS, RHS, and CC directly in creating a new 1344 // node. Otherwise, select between the true and false value based on 1345 // comparing the result of the legalized with zero. 1346 if (Tmp1.getOpcode() == ISD::SETCC) { 1347 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1348 Tmp1.getOperand(0), Tmp1.getOperand(1), 1349 Tmp3, Tmp4, Tmp1.getOperand(2)); 1350 } else { 1351 Result = DAG.getSelectCC(Tmp1, 1352 DAG.getConstant(0, Tmp1.getValueType()), 1353 Tmp3, Tmp4, ISD::SETNE); 1354 } 1355 } 1356 break; 1357 case ISD::SETCC: 1358 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1359 case Legal: 1360 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1361 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1362 break; 1363 case Promote: 1364 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1365 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1366 1367 // If this is an FP compare, the operands have already been extended. 1368 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1369 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1370 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1371 1372 // Otherwise, we have to insert explicit sign or zero extends. Note 1373 // that we could insert sign extends for ALL conditions, but zero extend 1374 // is cheaper on many machines (an AND instead of two shifts), so prefer 1375 // it. 1376 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1377 default: assert(0 && "Unknown integer comparison!"); 1378 case ISD::SETEQ: 1379 case ISD::SETNE: 1380 case ISD::SETUGE: 1381 case ISD::SETUGT: 1382 case ISD::SETULE: 1383 case ISD::SETULT: 1384 // ALL of these operations will work if we either sign or zero extend 1385 // the operands (including the unsigned comparisons!). Zero extend is 1386 // usually a simpler/cheaper operation, so prefer it. 1387 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1388 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1389 break; 1390 case ISD::SETGE: 1391 case ISD::SETGT: 1392 case ISD::SETLT: 1393 case ISD::SETLE: 1394 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1395 DAG.getValueType(VT)); 1396 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1397 DAG.getValueType(VT)); 1398 break; 1399 } 1400 } 1401 break; 1402 case Expand: 1403 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1404 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1405 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1406 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1407 case ISD::SETEQ: 1408 case ISD::SETNE: 1409 if (RHSLo == RHSHi) 1410 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1411 if (RHSCST->isAllOnesValue()) { 1412 // Comparison to -1. 1413 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1414 Tmp2 = RHSLo; 1415 break; 1416 } 1417 1418 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1419 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1420 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1421 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1422 break; 1423 default: 1424 // If this is a comparison of the sign bit, just look at the top part. 1425 // X > -1, x < 0 1426 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1427 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1428 CST->getValue() == 0) || // X < 0 1429 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1430 (CST->isAllOnesValue()))) { // X > -1 1431 Tmp1 = LHSHi; 1432 Tmp2 = RHSHi; 1433 break; 1434 } 1435 1436 // FIXME: This generated code sucks. 1437 ISD::CondCode LowCC; 1438 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1439 default: assert(0 && "Unknown integer setcc!"); 1440 case ISD::SETLT: 1441 case ISD::SETULT: LowCC = ISD::SETULT; break; 1442 case ISD::SETGT: 1443 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1444 case ISD::SETLE: 1445 case ISD::SETULE: LowCC = ISD::SETULE; break; 1446 case ISD::SETGE: 1447 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1448 } 1449 1450 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1451 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1452 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1453 1454 // NOTE: on targets without efficient SELECT of bools, we can always use 1455 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1456 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1457 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1458 Node->getOperand(2)); 1459 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1460 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1461 Result, Tmp1, Tmp2)); 1462 AddLegalizedOperand(SDOperand(Node, 0), Result); 1463 return Result; 1464 } 1465 } 1466 1467 switch (TLI.getOperationAction(ISD::SETCC, 1468 Node->getOperand(0).getValueType())) { 1469 default: assert(0 && "Cannot handle this action for SETCC yet!"); 1470 case TargetLowering::Custom: 1471 isCustom = true; 1472 // FALLTHROUGH. 1473 case TargetLowering::Legal: 1474 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1475 if (isCustom) { 1476 Tmp3 = TLI.LowerOperation(Result, DAG); 1477 if (Tmp3.Val) Result = Tmp3; 1478 } 1479 break; 1480 case TargetLowering::Promote: { 1481 // First step, figure out the appropriate operation to use. 1482 // Allow SETCC to not be supported for all legal data types 1483 // Mostly this targets FP 1484 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 1485 MVT::ValueType OldVT = NewInTy; 1486 1487 // Scan for the appropriate larger type to use. 1488 while (1) { 1489 NewInTy = (MVT::ValueType)(NewInTy+1); 1490 1491 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 1492 "Fell off of the edge of the integer world"); 1493 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 1494 "Fell off of the edge of the floating point world"); 1495 1496 // If the target supports SETCC of this type, use it. 1497 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 1498 break; 1499 } 1500 if (MVT::isInteger(NewInTy)) 1501 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1502 else { 1503 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 1504 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 1505 } 1506 Tmp1 = LegalizeOp(Tmp1); 1507 Tmp2 = LegalizeOp(Tmp2); 1508 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1509 Result = LegalizeOp(Result); 1510 break; 1511 } 1512 case TargetLowering::Expand: 1513 // Expand a setcc node into a select_cc of the same condition, lhs, and 1514 // rhs that selects between const 1 (true) and const 0 (false). 1515 MVT::ValueType VT = Node->getValueType(0); 1516 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1517 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1518 Node->getOperand(2)); 1519 break; 1520 } 1521 break; 1522 case ISD::MEMSET: 1523 case ISD::MEMCPY: 1524 case ISD::MEMMOVE: { 1525 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1526 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1527 1528 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1529 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1530 case Expand: assert(0 && "Cannot expand a byte!"); 1531 case Legal: 1532 Tmp3 = LegalizeOp(Node->getOperand(2)); 1533 break; 1534 case Promote: 1535 Tmp3 = PromoteOp(Node->getOperand(2)); 1536 break; 1537 } 1538 } else { 1539 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1540 } 1541 1542 SDOperand Tmp4; 1543 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1544 case Expand: { 1545 // Length is too big, just take the lo-part of the length. 1546 SDOperand HiPart; 1547 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1548 break; 1549 } 1550 case Legal: 1551 Tmp4 = LegalizeOp(Node->getOperand(3)); 1552 break; 1553 case Promote: 1554 Tmp4 = PromoteOp(Node->getOperand(3)); 1555 break; 1556 } 1557 1558 SDOperand Tmp5; 1559 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1560 case Expand: assert(0 && "Cannot expand this yet!"); 1561 case Legal: 1562 Tmp5 = LegalizeOp(Node->getOperand(4)); 1563 break; 1564 case Promote: 1565 Tmp5 = PromoteOp(Node->getOperand(4)); 1566 break; 1567 } 1568 1569 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1570 default: assert(0 && "This action not implemented for this operation!"); 1571 case TargetLowering::Custom: 1572 isCustom = true; 1573 // FALLTHROUGH 1574 case TargetLowering::Legal: 1575 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 1576 if (isCustom) { 1577 Tmp1 = TLI.LowerOperation(Result, DAG); 1578 if (Tmp1.Val) Result = Tmp1; 1579 } 1580 break; 1581 case TargetLowering::Expand: { 1582 // Otherwise, the target does not support this operation. Lower the 1583 // operation to an explicit libcall as appropriate. 1584 MVT::ValueType IntPtr = TLI.getPointerTy(); 1585 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1586 std::vector<std::pair<SDOperand, const Type*> > Args; 1587 1588 const char *FnName = 0; 1589 if (Node->getOpcode() == ISD::MEMSET) { 1590 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1591 // Extend the ubyte argument to be an int value for the call. 1592 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1593 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1594 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1595 1596 FnName = "memset"; 1597 } else if (Node->getOpcode() == ISD::MEMCPY || 1598 Node->getOpcode() == ISD::MEMMOVE) { 1599 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1600 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1601 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1602 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1603 } else { 1604 assert(0 && "Unknown op!"); 1605 } 1606 1607 std::pair<SDOperand,SDOperand> CallResult = 1608 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1609 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1610 Result = CallResult.second; 1611 break; 1612 } 1613 } 1614 break; 1615 } 1616 1617 case ISD::READPORT: 1618 Tmp1 = LegalizeOp(Node->getOperand(0)); 1619 Tmp2 = LegalizeOp(Node->getOperand(1)); 1620 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1621 1622 // Since these produce two values, make sure to remember that we legalized 1623 // both of them. 1624 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1625 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1626 return Result; 1627 case ISD::WRITEPORT: 1628 Tmp1 = LegalizeOp(Node->getOperand(0)); 1629 Tmp2 = LegalizeOp(Node->getOperand(1)); 1630 Tmp3 = LegalizeOp(Node->getOperand(2)); 1631 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1632 break; 1633 1634 case ISD::READIO: 1635 Tmp1 = LegalizeOp(Node->getOperand(0)); 1636 Tmp2 = LegalizeOp(Node->getOperand(1)); 1637 1638 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1639 case TargetLowering::Custom: 1640 default: assert(0 && "This action not implemented for this operation!"); 1641 case TargetLowering::Legal: 1642 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1643 break; 1644 case TargetLowering::Expand: 1645 // Replace this with a load from memory. 1646 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 1647 Node->getOperand(1), DAG.getSrcValue(NULL)); 1648 Result = LegalizeOp(Result); 1649 break; 1650 } 1651 1652 // Since these produce two values, make sure to remember that we legalized 1653 // both of them. 1654 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1655 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1656 return Result.getValue(Op.ResNo); 1657 1658 case ISD::WRITEIO: 1659 Tmp1 = LegalizeOp(Node->getOperand(0)); 1660 Tmp2 = LegalizeOp(Node->getOperand(1)); 1661 Tmp3 = LegalizeOp(Node->getOperand(2)); 1662 1663 switch (TLI.getOperationAction(Node->getOpcode(), 1664 Node->getOperand(1).getValueType())) { 1665 case TargetLowering::Custom: 1666 default: assert(0 && "This action not implemented for this operation!"); 1667 case TargetLowering::Legal: 1668 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1669 break; 1670 case TargetLowering::Expand: 1671 // Replace this with a store to memory. 1672 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 1673 Node->getOperand(1), Node->getOperand(2), 1674 DAG.getSrcValue(NULL)); 1675 break; 1676 } 1677 break; 1678 1679 case ISD::ADD_PARTS: 1680 case ISD::SUB_PARTS: 1681 case ISD::SHL_PARTS: 1682 case ISD::SRA_PARTS: 1683 case ISD::SRL_PARTS: { 1684 std::vector<SDOperand> Ops; 1685 bool Changed = false; 1686 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1687 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1688 Changed |= Ops.back() != Node->getOperand(i); 1689 } 1690 if (Changed) 1691 Result = DAG.UpdateNodeOperands(Result, Ops); 1692 1693 switch (TLI.getOperationAction(Node->getOpcode(), 1694 Node->getValueType(0))) { 1695 default: assert(0 && "This action is not supported yet!"); 1696 case TargetLowering::Legal: break; 1697 case TargetLowering::Custom: 1698 Tmp1 = TLI.LowerOperation(Result, DAG); 1699 if (Tmp1.Val) { 1700 SDOperand Tmp2, RetVal(0, 0); 1701 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 1702 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 1703 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 1704 if (i == Op.ResNo) 1705 RetVal = Tmp2; 1706 } 1707 assert(RetVal.Val && "Illegal result number"); 1708 return RetVal; 1709 } 1710 break; 1711 } 1712 1713 // Since these produce multiple values, make sure to remember that we 1714 // legalized all of them. 1715 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1716 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1717 return Result.getValue(Op.ResNo); 1718 } 1719 1720 // Binary operators 1721 case ISD::ADD: 1722 case ISD::SUB: 1723 case ISD::MUL: 1724 case ISD::MULHS: 1725 case ISD::MULHU: 1726 case ISD::UDIV: 1727 case ISD::SDIV: 1728 case ISD::AND: 1729 case ISD::OR: 1730 case ISD::XOR: 1731 case ISD::SHL: 1732 case ISD::SRL: 1733 case ISD::SRA: 1734 case ISD::FADD: 1735 case ISD::FSUB: 1736 case ISD::FMUL: 1737 case ISD::FDIV: 1738 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1739 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1740 case Expand: assert(0 && "Not possible"); 1741 case Legal: 1742 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 1743 break; 1744 case Promote: 1745 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 1746 break; 1747 } 1748 1749 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1750 1751 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1752 default: assert(0 && "Operation not supported"); 1753 case TargetLowering::Legal: break; 1754 case TargetLowering::Custom: 1755 Tmp1 = TLI.LowerOperation(Result, DAG); 1756 if (Tmp1.Val) Result = Tmp1; 1757 break; 1758 } 1759 break; 1760 1761 case ISD::BUILD_PAIR: { 1762 MVT::ValueType PairTy = Node->getValueType(0); 1763 // TODO: handle the case where the Lo and Hi operands are not of legal type 1764 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 1765 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 1766 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 1767 case TargetLowering::Promote: 1768 case TargetLowering::Custom: 1769 assert(0 && "Cannot promote/custom this yet!"); 1770 case TargetLowering::Legal: 1771 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1772 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 1773 break; 1774 case TargetLowering::Expand: 1775 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 1776 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 1777 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 1778 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 1779 TLI.getShiftAmountTy())); 1780 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 1781 break; 1782 } 1783 break; 1784 } 1785 1786 case ISD::UREM: 1787 case ISD::SREM: 1788 case ISD::FREM: 1789 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1790 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1791 1792 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1793 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 1794 case TargetLowering::Custom: 1795 isCustom = true; 1796 // FALLTHROUGH 1797 case TargetLowering::Legal: 1798 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1799 if (isCustom) { 1800 Tmp1 = TLI.LowerOperation(Result, DAG); 1801 if (Tmp1.Val) Result = Tmp1; 1802 } 1803 break; 1804 case TargetLowering::Expand: 1805 if (MVT::isInteger(Node->getValueType(0))) { 1806 // X % Y -> X-X/Y*Y 1807 MVT::ValueType VT = Node->getValueType(0); 1808 unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV; 1809 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 1810 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 1811 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 1812 } else { 1813 // Floating point mod -> fmod libcall. 1814 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 1815 SDOperand Dummy; 1816 Result = ExpandLibCall(FnName, Node, Dummy); 1817 } 1818 break; 1819 } 1820 break; 1821 case ISD::VAARG: { 1822 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1823 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1824 1825 MVT::ValueType VT = Node->getValueType(0); 1826 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1827 default: assert(0 && "This action is not supported yet!"); 1828 case TargetLowering::Custom: 1829 isCustom = true; 1830 // FALLTHROUGH 1831 case TargetLowering::Legal: 1832 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1833 Result = Result.getValue(0); 1834 Tmp1 = Result.getValue(1); 1835 1836 if (isCustom) { 1837 Tmp2 = TLI.LowerOperation(Result, DAG); 1838 if (Tmp2.Val) { 1839 Result = LegalizeOp(Tmp2); 1840 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 1841 } 1842 } 1843 break; 1844 case TargetLowering::Expand: { 1845 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 1846 Node->getOperand(2)); 1847 // Increment the pointer, VAList, to the next vaarg 1848 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 1849 DAG.getConstant(MVT::getSizeInBits(VT)/8, 1850 TLI.getPointerTy())); 1851 // Store the incremented VAList to the legalized pointer 1852 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2, 1853 Node->getOperand(2)); 1854 // Load the actual argument out of the pointer VAList 1855 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0)); 1856 Tmp1 = LegalizeOp(Result.getValue(1)); 1857 Result = LegalizeOp(Result); 1858 break; 1859 } 1860 } 1861 // Since VAARG produces two values, make sure to remember that we 1862 // legalized both of them. 1863 AddLegalizedOperand(SDOperand(Node, 0), Result); 1864 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 1865 return Op.ResNo ? Tmp1 : Result; 1866 } 1867 1868 case ISD::VACOPY: 1869 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1870 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 1871 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 1872 1873 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 1874 default: assert(0 && "This action is not supported yet!"); 1875 case TargetLowering::Custom: 1876 isCustom = true; 1877 // FALLTHROUGH 1878 case TargetLowering::Legal: 1879 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 1880 Node->getOperand(3), Node->getOperand(4)); 1881 if (isCustom) { 1882 Tmp1 = TLI.LowerOperation(Result, DAG); 1883 if (Tmp1.Val) Result = Tmp1; 1884 } 1885 break; 1886 case TargetLowering::Expand: 1887 // This defaults to loading a pointer from the input and storing it to the 1888 // output, returning the chain. 1889 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3)); 1890 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2, 1891 Node->getOperand(4)); 1892 break; 1893 } 1894 break; 1895 1896 case ISD::VAEND: 1897 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1898 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1899 1900 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 1901 default: assert(0 && "This action is not supported yet!"); 1902 case TargetLowering::Custom: 1903 isCustom = true; 1904 // FALLTHROUGH 1905 case TargetLowering::Legal: 1906 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1907 if (isCustom) { 1908 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 1909 if (Tmp1.Val) Result = Tmp1; 1910 } 1911 break; 1912 case TargetLowering::Expand: 1913 Result = Tmp1; // Default to a no-op, return the chain 1914 break; 1915 } 1916 break; 1917 1918 case ISD::VASTART: 1919 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1920 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1921 1922 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1923 1924 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 1925 default: assert(0 && "This action is not supported yet!"); 1926 case TargetLowering::Legal: break; 1927 case TargetLowering::Custom: 1928 Tmp1 = TLI.LowerOperation(Result, DAG); 1929 if (Tmp1.Val) Result = Tmp1; 1930 break; 1931 } 1932 break; 1933 1934 case ISD::ROTL: 1935 case ISD::ROTR: 1936 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1937 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1938 1939 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 1940 "Cannot handle this yet!"); 1941 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1942 break; 1943 1944 case ISD::BSWAP: 1945 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 1946 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1947 case TargetLowering::Custom: 1948 assert(0 && "Cannot custom legalize this yet!"); 1949 case TargetLowering::Legal: 1950 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1951 break; 1952 case TargetLowering::Promote: { 1953 MVT::ValueType OVT = Tmp1.getValueType(); 1954 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1955 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT); 1956 1957 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1958 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 1959 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 1960 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 1961 break; 1962 } 1963 case TargetLowering::Expand: 1964 Result = ExpandBSWAP(Tmp1); 1965 break; 1966 } 1967 break; 1968 1969 case ISD::CTPOP: 1970 case ISD::CTTZ: 1971 case ISD::CTLZ: 1972 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 1973 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1974 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!"); 1975 case TargetLowering::Legal: 1976 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1977 break; 1978 case TargetLowering::Promote: { 1979 MVT::ValueType OVT = Tmp1.getValueType(); 1980 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1981 1982 // Zero extend the argument. 1983 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1984 // Perform the larger operation, then subtract if needed. 1985 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1986 switch (Node->getOpcode()) { 1987 case ISD::CTPOP: 1988 Result = Tmp1; 1989 break; 1990 case ISD::CTTZ: 1991 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 1992 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 1993 DAG.getConstant(getSizeInBits(NVT), NVT), 1994 ISD::SETEQ); 1995 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 1996 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 1997 break; 1998 case ISD::CTLZ: 1999 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2000 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2001 DAG.getConstant(getSizeInBits(NVT) - 2002 getSizeInBits(OVT), NVT)); 2003 break; 2004 } 2005 break; 2006 } 2007 case TargetLowering::Expand: 2008 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 2009 break; 2010 } 2011 break; 2012 2013 // Unary operators 2014 case ISD::FABS: 2015 case ISD::FNEG: 2016 case ISD::FSQRT: 2017 case ISD::FSIN: 2018 case ISD::FCOS: 2019 Tmp1 = LegalizeOp(Node->getOperand(0)); 2020 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2021 case TargetLowering::Promote: 2022 case TargetLowering::Custom: 2023 assert(0 && "Cannot promote/custom handle this yet!"); 2024 case TargetLowering::Legal: 2025 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2026 break; 2027 case TargetLowering::Expand: 2028 switch (Node->getOpcode()) { 2029 default: assert(0 && "Unreachable!"); 2030 case ISD::FNEG: 2031 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2032 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2033 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 2034 break; 2035 case ISD::FABS: { 2036 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2037 MVT::ValueType VT = Node->getValueType(0); 2038 Tmp2 = DAG.getConstantFP(0.0, VT); 2039 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2040 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2041 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2042 break; 2043 } 2044 case ISD::FSQRT: 2045 case ISD::FSIN: 2046 case ISD::FCOS: { 2047 MVT::ValueType VT = Node->getValueType(0); 2048 const char *FnName = 0; 2049 switch(Node->getOpcode()) { 2050 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 2051 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 2052 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 2053 default: assert(0 && "Unreachable!"); 2054 } 2055 SDOperand Dummy; 2056 Result = ExpandLibCall(FnName, Node, Dummy); 2057 break; 2058 } 2059 } 2060 break; 2061 } 2062 break; 2063 2064 case ISD::BIT_CONVERT: 2065 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 2066 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2067 } else { 2068 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 2069 Node->getOperand(0).getValueType())) { 2070 default: assert(0 && "Unknown operation action!"); 2071 case TargetLowering::Expand: 2072 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2073 break; 2074 case TargetLowering::Legal: 2075 Tmp1 = LegalizeOp(Node->getOperand(0)); 2076 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2077 break; 2078 } 2079 } 2080 break; 2081 // Conversion operators. The source and destination have different types. 2082 case ISD::SINT_TO_FP: 2083 case ISD::UINT_TO_FP: { 2084 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2085 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2086 case Legal: 2087 switch (TLI.getOperationAction(Node->getOpcode(), 2088 Node->getOperand(0).getValueType())) { 2089 default: assert(0 && "Unknown operation action!"); 2090 case TargetLowering::Custom: 2091 isCustom = true; 2092 // FALLTHROUGH 2093 case TargetLowering::Legal: 2094 Tmp1 = LegalizeOp(Node->getOperand(0)); 2095 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2096 if (isCustom) { 2097 Tmp1 = TLI.LowerOperation(Result, DAG); 2098 if (Tmp1.Val) Result = Tmp1; 2099 } 2100 break; 2101 case TargetLowering::Expand: 2102 Result = ExpandLegalINT_TO_FP(isSigned, 2103 LegalizeOp(Node->getOperand(0)), 2104 Node->getValueType(0)); 2105 break; 2106 case TargetLowering::Promote: 2107 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2108 Node->getValueType(0), 2109 isSigned); 2110 break; 2111 } 2112 break; 2113 case Expand: 2114 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2115 Node->getValueType(0), Node->getOperand(0)); 2116 break; 2117 case Promote: 2118 Tmp1 = PromoteOp(Node->getOperand(0)); 2119 if (isSigned) { 2120 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 2121 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 2122 } else { 2123 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 2124 Node->getOperand(0).getValueType()); 2125 } 2126 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2127 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 2128 break; 2129 } 2130 break; 2131 } 2132 case ISD::TRUNCATE: 2133 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2134 case Legal: 2135 Tmp1 = LegalizeOp(Node->getOperand(0)); 2136 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2137 break; 2138 case Expand: 2139 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2140 2141 // Since the result is legal, we should just be able to truncate the low 2142 // part of the source. 2143 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2144 break; 2145 case Promote: 2146 Result = PromoteOp(Node->getOperand(0)); 2147 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2148 break; 2149 } 2150 break; 2151 2152 case ISD::FP_TO_SINT: 2153 case ISD::FP_TO_UINT: 2154 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2155 case Legal: 2156 Tmp1 = LegalizeOp(Node->getOperand(0)); 2157 2158 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2159 default: assert(0 && "Unknown operation action!"); 2160 case TargetLowering::Custom: 2161 isCustom = true; 2162 // FALLTHROUGH 2163 case TargetLowering::Legal: 2164 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2165 if (isCustom) { 2166 Tmp1 = TLI.LowerOperation(Result, DAG); 2167 if (Tmp1.Val) Result = Tmp1; 2168 } 2169 break; 2170 case TargetLowering::Promote: 2171 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2172 Node->getOpcode() == ISD::FP_TO_SINT); 2173 break; 2174 case TargetLowering::Expand: 2175 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2176 SDOperand True, False; 2177 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2178 MVT::ValueType NVT = Node->getValueType(0); 2179 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2180 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2181 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2182 Node->getOperand(0), Tmp2, ISD::SETLT); 2183 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2184 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2185 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2186 Tmp2)); 2187 False = DAG.getNode(ISD::XOR, NVT, False, 2188 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2189 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 2190 break; 2191 } else { 2192 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2193 } 2194 break; 2195 } 2196 break; 2197 case Expand: 2198 assert(0 && "Shouldn't need to expand other operators here!"); 2199 case Promote: 2200 Tmp1 = PromoteOp(Node->getOperand(0)); 2201 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 2202 Result = LegalizeOp(Result); 2203 break; 2204 } 2205 break; 2206 2207 case ISD::ANY_EXTEND: 2208 case ISD::ZERO_EXTEND: 2209 case ISD::SIGN_EXTEND: 2210 case ISD::FP_EXTEND: 2211 case ISD::FP_ROUND: 2212 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2213 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 2214 case Legal: 2215 Tmp1 = LegalizeOp(Node->getOperand(0)); 2216 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2217 break; 2218 case Promote: 2219 switch (Node->getOpcode()) { 2220 case ISD::ANY_EXTEND: 2221 Tmp1 = PromoteOp(Node->getOperand(0)); 2222 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 2223 break; 2224 case ISD::ZERO_EXTEND: 2225 Result = PromoteOp(Node->getOperand(0)); 2226 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2227 Result = DAG.getZeroExtendInReg(Result, 2228 Node->getOperand(0).getValueType()); 2229 break; 2230 case ISD::SIGN_EXTEND: 2231 Result = PromoteOp(Node->getOperand(0)); 2232 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2233 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2234 Result, 2235 DAG.getValueType(Node->getOperand(0).getValueType())); 2236 break; 2237 case ISD::FP_EXTEND: 2238 Result = PromoteOp(Node->getOperand(0)); 2239 if (Result.getValueType() != Op.getValueType()) 2240 // Dynamically dead while we have only 2 FP types. 2241 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2242 break; 2243 case ISD::FP_ROUND: 2244 Result = PromoteOp(Node->getOperand(0)); 2245 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2246 break; 2247 } 2248 } 2249 break; 2250 case ISD::FP_ROUND_INREG: 2251 case ISD::SIGN_EXTEND_INREG: { 2252 Tmp1 = LegalizeOp(Node->getOperand(0)); 2253 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2254 2255 // If this operation is not supported, convert it to a shl/shr or load/store 2256 // pair. 2257 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2258 default: assert(0 && "This action not supported for this op yet!"); 2259 case TargetLowering::Legal: 2260 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2261 break; 2262 case TargetLowering::Expand: 2263 // If this is an integer extend and shifts are supported, do that. 2264 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2265 // NOTE: we could fall back on load/store here too for targets without 2266 // SAR. However, it is doubtful that any exist. 2267 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2268 MVT::getSizeInBits(ExtraVT); 2269 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2270 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2271 Node->getOperand(0), ShiftCst); 2272 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2273 Result, ShiftCst); 2274 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2275 // The only way we can lower this is to turn it into a STORETRUNC, 2276 // EXTLOAD pair, targetting a temporary location (a stack slot). 2277 2278 // NOTE: there is a choice here between constantly creating new stack 2279 // slots and always reusing the same one. We currently always create 2280 // new ones, as reuse may inhibit scheduling. 2281 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2282 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2283 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2284 MachineFunction &MF = DAG.getMachineFunction(); 2285 int SSFI = 2286 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2287 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2288 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2289 Node->getOperand(0), StackSlot, 2290 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2291 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2292 Result, StackSlot, DAG.getSrcValue(NULL), 2293 ExtraVT); 2294 } else { 2295 assert(0 && "Unknown op"); 2296 } 2297 break; 2298 } 2299 break; 2300 } 2301 } 2302 2303 // Make sure that the generated code is itself legal. 2304 if (Result != Op) 2305 Result = LegalizeOp(Result); 2306 2307 // Note that LegalizeOp may be reentered even from single-use nodes, which 2308 // means that we always must cache transformed nodes. 2309 AddLegalizedOperand(Op, Result); 2310 return Result; 2311} 2312 2313/// PromoteOp - Given an operation that produces a value in an invalid type, 2314/// promote it to compute the value into a larger type. The produced value will 2315/// have the correct bits for the low portion of the register, but no guarantee 2316/// is made about the top bits: it may be zero, sign-extended, or garbage. 2317SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2318 MVT::ValueType VT = Op.getValueType(); 2319 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2320 assert(getTypeAction(VT) == Promote && 2321 "Caller should expand or legalize operands that are not promotable!"); 2322 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2323 "Cannot promote to smaller type!"); 2324 2325 SDOperand Tmp1, Tmp2, Tmp3; 2326 SDOperand Result; 2327 SDNode *Node = Op.Val; 2328 2329 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2330 if (I != PromotedNodes.end()) return I->second; 2331 2332 switch (Node->getOpcode()) { 2333 case ISD::CopyFromReg: 2334 assert(0 && "CopyFromReg must be legal!"); 2335 default: 2336 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2337 assert(0 && "Do not know how to promote this operator!"); 2338 abort(); 2339 case ISD::UNDEF: 2340 Result = DAG.getNode(ISD::UNDEF, NVT); 2341 break; 2342 case ISD::Constant: 2343 if (VT != MVT::i1) 2344 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2345 else 2346 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2347 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2348 break; 2349 case ISD::ConstantFP: 2350 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2351 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2352 break; 2353 2354 case ISD::SETCC: 2355 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2356 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2357 Node->getOperand(1), Node->getOperand(2)); 2358 break; 2359 2360 case ISD::TRUNCATE: 2361 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2362 case Legal: 2363 Result = LegalizeOp(Node->getOperand(0)); 2364 assert(Result.getValueType() >= NVT && 2365 "This truncation doesn't make sense!"); 2366 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2367 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2368 break; 2369 case Promote: 2370 // The truncation is not required, because we don't guarantee anything 2371 // about high bits anyway. 2372 Result = PromoteOp(Node->getOperand(0)); 2373 break; 2374 case Expand: 2375 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2376 // Truncate the low part of the expanded value to the result type 2377 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2378 } 2379 break; 2380 case ISD::SIGN_EXTEND: 2381 case ISD::ZERO_EXTEND: 2382 case ISD::ANY_EXTEND: 2383 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2384 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2385 case Legal: 2386 // Input is legal? Just do extend all the way to the larger type. 2387 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 2388 break; 2389 case Promote: 2390 // Promote the reg if it's smaller. 2391 Result = PromoteOp(Node->getOperand(0)); 2392 // The high bits are not guaranteed to be anything. Insert an extend. 2393 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2394 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2395 DAG.getValueType(Node->getOperand(0).getValueType())); 2396 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2397 Result = DAG.getZeroExtendInReg(Result, 2398 Node->getOperand(0).getValueType()); 2399 break; 2400 } 2401 break; 2402 case ISD::BIT_CONVERT: 2403 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2404 Result = PromoteOp(Result); 2405 break; 2406 2407 case ISD::FP_EXTEND: 2408 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2409 case ISD::FP_ROUND: 2410 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2411 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2412 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2413 case Legal: 2414 // Input is legal? Do an FP_ROUND_INREG. 2415 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 2416 DAG.getValueType(VT)); 2417 break; 2418 } 2419 break; 2420 2421 case ISD::SINT_TO_FP: 2422 case ISD::UINT_TO_FP: 2423 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2424 case Legal: 2425 // No extra round required here. 2426 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 2427 break; 2428 2429 case Promote: 2430 Result = PromoteOp(Node->getOperand(0)); 2431 if (Node->getOpcode() == ISD::SINT_TO_FP) 2432 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2433 Result, 2434 DAG.getValueType(Node->getOperand(0).getValueType())); 2435 else 2436 Result = DAG.getZeroExtendInReg(Result, 2437 Node->getOperand(0).getValueType()); 2438 // No extra round required here. 2439 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2440 break; 2441 case Expand: 2442 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2443 Node->getOperand(0)); 2444 // Round if we cannot tolerate excess precision. 2445 if (NoExcessFPPrecision) 2446 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2447 DAG.getValueType(VT)); 2448 break; 2449 } 2450 break; 2451 2452 case ISD::SIGN_EXTEND_INREG: 2453 Result = PromoteOp(Node->getOperand(0)); 2454 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2455 Node->getOperand(1)); 2456 break; 2457 case ISD::FP_TO_SINT: 2458 case ISD::FP_TO_UINT: 2459 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2460 case Legal: 2461 Tmp1 = Node->getOperand(0); 2462 break; 2463 case Promote: 2464 // The input result is prerounded, so we don't have to do anything 2465 // special. 2466 Tmp1 = PromoteOp(Node->getOperand(0)); 2467 break; 2468 case Expand: 2469 assert(0 && "not implemented"); 2470 } 2471 // If we're promoting a UINT to a larger size, check to see if the new node 2472 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2473 // we can use that instead. This allows us to generate better code for 2474 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2475 // legal, such as PowerPC. 2476 if (Node->getOpcode() == ISD::FP_TO_UINT && 2477 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2478 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2479 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2480 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2481 } else { 2482 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2483 } 2484 break; 2485 2486 case ISD::FABS: 2487 case ISD::FNEG: 2488 Tmp1 = PromoteOp(Node->getOperand(0)); 2489 assert(Tmp1.getValueType() == NVT); 2490 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2491 // NOTE: we do not have to do any extra rounding here for 2492 // NoExcessFPPrecision, because we know the input will have the appropriate 2493 // precision, and these operations don't modify precision at all. 2494 break; 2495 2496 case ISD::FSQRT: 2497 case ISD::FSIN: 2498 case ISD::FCOS: 2499 Tmp1 = PromoteOp(Node->getOperand(0)); 2500 assert(Tmp1.getValueType() == NVT); 2501 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2502 if (NoExcessFPPrecision) 2503 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2504 DAG.getValueType(VT)); 2505 break; 2506 2507 case ISD::AND: 2508 case ISD::OR: 2509 case ISD::XOR: 2510 case ISD::ADD: 2511 case ISD::SUB: 2512 case ISD::MUL: 2513 // The input may have strange things in the top bits of the registers, but 2514 // these operations don't care. They may have weird bits going out, but 2515 // that too is okay if they are integer operations. 2516 Tmp1 = PromoteOp(Node->getOperand(0)); 2517 Tmp2 = PromoteOp(Node->getOperand(1)); 2518 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2519 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2520 break; 2521 case ISD::FADD: 2522 case ISD::FSUB: 2523 case ISD::FMUL: 2524 Tmp1 = PromoteOp(Node->getOperand(0)); 2525 Tmp2 = PromoteOp(Node->getOperand(1)); 2526 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2527 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2528 2529 // Floating point operations will give excess precision that we may not be 2530 // able to tolerate. If we DO allow excess precision, just leave it, 2531 // otherwise excise it. 2532 // FIXME: Why would we need to round FP ops more than integer ones? 2533 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 2534 if (NoExcessFPPrecision) 2535 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2536 DAG.getValueType(VT)); 2537 break; 2538 2539 case ISD::SDIV: 2540 case ISD::SREM: 2541 // These operators require that their input be sign extended. 2542 Tmp1 = PromoteOp(Node->getOperand(0)); 2543 Tmp2 = PromoteOp(Node->getOperand(1)); 2544 if (MVT::isInteger(NVT)) { 2545 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2546 DAG.getValueType(VT)); 2547 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 2548 DAG.getValueType(VT)); 2549 } 2550 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2551 2552 // Perform FP_ROUND: this is probably overly pessimistic. 2553 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2554 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2555 DAG.getValueType(VT)); 2556 break; 2557 case ISD::FDIV: 2558 case ISD::FREM: 2559 // These operators require that their input be fp extended. 2560 Tmp1 = PromoteOp(Node->getOperand(0)); 2561 Tmp2 = PromoteOp(Node->getOperand(1)); 2562 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2563 2564 // Perform FP_ROUND: this is probably overly pessimistic. 2565 if (NoExcessFPPrecision) 2566 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2567 DAG.getValueType(VT)); 2568 break; 2569 2570 case ISD::UDIV: 2571 case ISD::UREM: 2572 // These operators require that their input be zero extended. 2573 Tmp1 = PromoteOp(Node->getOperand(0)); 2574 Tmp2 = PromoteOp(Node->getOperand(1)); 2575 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 2576 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2577 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 2578 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2579 break; 2580 2581 case ISD::SHL: 2582 Tmp1 = PromoteOp(Node->getOperand(0)); 2583 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 2584 break; 2585 case ISD::SRA: 2586 // The input value must be properly sign extended. 2587 Tmp1 = PromoteOp(Node->getOperand(0)); 2588 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2589 DAG.getValueType(VT)); 2590 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 2591 break; 2592 case ISD::SRL: 2593 // The input value must be properly zero extended. 2594 Tmp1 = PromoteOp(Node->getOperand(0)); 2595 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2596 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 2597 break; 2598 2599 case ISD::VAARG: 2600 Tmp1 = Node->getOperand(0); // Get the chain. 2601 Tmp2 = Node->getOperand(1); // Get the pointer. 2602 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 2603 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 2604 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 2605 } else { 2606 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2607 Node->getOperand(2)); 2608 // Increment the pointer, VAList, to the next vaarg 2609 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2610 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2611 TLI.getPointerTy())); 2612 // Store the incremented VAList to the legalized pointer 2613 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2, 2614 Node->getOperand(2)); 2615 // Load the actual argument out of the pointer VAList 2616 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, 2617 DAG.getSrcValue(0), VT); 2618 } 2619 // Remember that we legalized the chain. 2620 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 2621 break; 2622 2623 case ISD::LOAD: 2624 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0), 2625 Node->getOperand(1), Node->getOperand(2), VT); 2626 // Remember that we legalized the chain. 2627 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 2628 break; 2629 case ISD::SEXTLOAD: 2630 case ISD::ZEXTLOAD: 2631 case ISD::EXTLOAD: 2632 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0), 2633 Node->getOperand(1), Node->getOperand(2), 2634 cast<VTSDNode>(Node->getOperand(3))->getVT()); 2635 // Remember that we legalized the chain. 2636 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 2637 break; 2638 case ISD::SELECT: 2639 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 2640 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 2641 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 2642 break; 2643 case ISD::SELECT_CC: 2644 Tmp2 = PromoteOp(Node->getOperand(2)); // True 2645 Tmp3 = PromoteOp(Node->getOperand(3)); // False 2646 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 2647 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 2648 break; 2649 case ISD::BSWAP: 2650 Tmp1 = Node->getOperand(0); 2651 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2652 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 2653 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 2654 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT), 2655 TLI.getShiftAmountTy())); 2656 break; 2657 case ISD::CTPOP: 2658 case ISD::CTTZ: 2659 case ISD::CTLZ: 2660 // Zero extend the argument 2661 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 2662 // Perform the larger operation, then subtract if needed. 2663 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2664 switch(Node->getOpcode()) { 2665 case ISD::CTPOP: 2666 Result = Tmp1; 2667 break; 2668 case ISD::CTTZ: 2669 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2670 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2671 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 2672 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2673 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1); 2674 break; 2675 case ISD::CTLZ: 2676 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2677 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2678 DAG.getConstant(getSizeInBits(NVT) - 2679 getSizeInBits(VT), NVT)); 2680 break; 2681 } 2682 break; 2683 } 2684 2685 assert(Result.Val && "Didn't set a result!"); 2686 2687 // Make sure the result is itself legal. 2688 Result = LegalizeOp(Result); 2689 2690 // Remember that we promoted this! 2691 AddPromotedOperand(Op, Result); 2692 return Result; 2693} 2694 2695/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 2696/// The resultant code need not be legal. Note that SrcOp is the input operand 2697/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 2698SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 2699 SDOperand SrcOp) { 2700 // Create the stack frame object. 2701 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2702 unsigned ByteSize = MVT::getSizeInBits(DestVT)/8; 2703 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize); 2704 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 2705 2706 // Emit a store to the stack slot. 2707 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 2708 SrcOp, FIPtr, DAG.getSrcValue(NULL)); 2709 // Result is a load from the stack slot. 2710 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0)); 2711} 2712 2713void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 2714 SDOperand Op, SDOperand Amt, 2715 SDOperand &Lo, SDOperand &Hi) { 2716 // Expand the subcomponents. 2717 SDOperand LHSL, LHSH; 2718 ExpandOp(Op, LHSL, LHSH); 2719 2720 std::vector<SDOperand> Ops; 2721 Ops.push_back(LHSL); 2722 Ops.push_back(LHSH); 2723 Ops.push_back(Amt); 2724 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2725 Lo = DAG.getNode(NodeOp, VTs, Ops); 2726 Hi = Lo.getValue(1); 2727} 2728 2729 2730/// ExpandShift - Try to find a clever way to expand this shift operation out to 2731/// smaller elements. If we can't find a way that is more efficient than a 2732/// libcall on this target, return false. Otherwise, return true with the 2733/// low-parts expanded into Lo and Hi. 2734bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 2735 SDOperand &Lo, SDOperand &Hi) { 2736 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 2737 "This is not a shift!"); 2738 2739 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 2740 SDOperand ShAmt = LegalizeOp(Amt); 2741 MVT::ValueType ShTy = ShAmt.getValueType(); 2742 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 2743 unsigned NVTBits = MVT::getSizeInBits(NVT); 2744 2745 // Handle the case when Amt is an immediate. Other cases are currently broken 2746 // and are disabled. 2747 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 2748 unsigned Cst = CN->getValue(); 2749 // Expand the incoming operand to be shifted, so that we have its parts 2750 SDOperand InL, InH; 2751 ExpandOp(Op, InL, InH); 2752 switch(Opc) { 2753 case ISD::SHL: 2754 if (Cst > VTBits) { 2755 Lo = DAG.getConstant(0, NVT); 2756 Hi = DAG.getConstant(0, NVT); 2757 } else if (Cst > NVTBits) { 2758 Lo = DAG.getConstant(0, NVT); 2759 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 2760 } else if (Cst == NVTBits) { 2761 Lo = DAG.getConstant(0, NVT); 2762 Hi = InL; 2763 } else { 2764 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 2765 Hi = DAG.getNode(ISD::OR, NVT, 2766 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 2767 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 2768 } 2769 return true; 2770 case ISD::SRL: 2771 if (Cst > VTBits) { 2772 Lo = DAG.getConstant(0, NVT); 2773 Hi = DAG.getConstant(0, NVT); 2774 } else if (Cst > NVTBits) { 2775 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 2776 Hi = DAG.getConstant(0, NVT); 2777 } else if (Cst == NVTBits) { 2778 Lo = InH; 2779 Hi = DAG.getConstant(0, NVT); 2780 } else { 2781 Lo = DAG.getNode(ISD::OR, NVT, 2782 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2783 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2784 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 2785 } 2786 return true; 2787 case ISD::SRA: 2788 if (Cst > VTBits) { 2789 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 2790 DAG.getConstant(NVTBits-1, ShTy)); 2791 } else if (Cst > NVTBits) { 2792 Lo = DAG.getNode(ISD::SRA, NVT, InH, 2793 DAG.getConstant(Cst-NVTBits, ShTy)); 2794 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2795 DAG.getConstant(NVTBits-1, ShTy)); 2796 } else if (Cst == NVTBits) { 2797 Lo = InH; 2798 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2799 DAG.getConstant(NVTBits-1, ShTy)); 2800 } else { 2801 Lo = DAG.getNode(ISD::OR, NVT, 2802 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2803 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2804 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 2805 } 2806 return true; 2807 } 2808 } 2809 return false; 2810} 2811 2812/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 2813/// NodeDepth) node that is an CallSeqStart operation and occurs later than 2814/// Found. 2815static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found, 2816 std::set<SDNode*> &Visited) { 2817 if (Node->getNodeDepth() <= Found->getNodeDepth() || 2818 !Visited.insert(Node).second) return; 2819 2820 // If we found an CALLSEQ_START, we already know this node occurs later 2821 // than the Found node. Just remember this node and return. 2822 if (Node->getOpcode() == ISD::CALLSEQ_START) { 2823 Found = Node; 2824 return; 2825 } 2826 2827 // Otherwise, scan the operands of Node to see if any of them is a call. 2828 assert(Node->getNumOperands() != 0 && 2829 "All leaves should have depth equal to the entry node!"); 2830 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 2831 FindLatestCallSeqStart(Node->getOperand(i).Val, Found, Visited); 2832 2833 // Tail recurse for the last iteration. 2834 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 2835 Found, Visited); 2836} 2837 2838 2839/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 2840/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 2841/// than Found. 2842static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 2843 std::set<SDNode*> &Visited) { 2844 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 2845 !Visited.insert(Node).second) return; 2846 2847 // If we found an CALLSEQ_END, we already know this node occurs earlier 2848 // than the Found node. Just remember this node and return. 2849 if (Node->getOpcode() == ISD::CALLSEQ_END) { 2850 Found = Node; 2851 return; 2852 } 2853 2854 // Otherwise, scan the operands of Node to see if any of them is a call. 2855 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 2856 if (UI == E) return; 2857 for (--E; UI != E; ++UI) 2858 FindEarliestCallSeqEnd(*UI, Found, Visited); 2859 2860 // Tail recurse for the last iteration. 2861 FindEarliestCallSeqEnd(*UI, Found, Visited); 2862} 2863 2864/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 2865/// find the CALLSEQ_END node that terminates the call sequence. 2866static SDNode *FindCallSeqEnd(SDNode *Node) { 2867 if (Node->getOpcode() == ISD::CALLSEQ_END) 2868 return Node; 2869 if (Node->use_empty()) 2870 return 0; // No CallSeqEnd 2871 2872 // The chain is usually at the end. 2873 SDOperand TheChain(Node, Node->getNumValues()-1); 2874 if (TheChain.getValueType() != MVT::Other) { 2875 // Sometimes it's at the beginning. 2876 TheChain = SDOperand(Node, 0); 2877 if (TheChain.getValueType() != MVT::Other) { 2878 // Otherwise, hunt for it. 2879 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 2880 if (Node->getValueType(i) == MVT::Other) { 2881 TheChain = SDOperand(Node, i); 2882 break; 2883 } 2884 2885 // Otherwise, we walked into a node without a chain. 2886 if (TheChain.getValueType() != MVT::Other) 2887 return 0; 2888 } 2889 } 2890 2891 for (SDNode::use_iterator UI = Node->use_begin(), 2892 E = Node->use_end(); UI != E; ++UI) { 2893 2894 // Make sure to only follow users of our token chain. 2895 SDNode *User = *UI; 2896 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 2897 if (User->getOperand(i) == TheChain) 2898 if (SDNode *Result = FindCallSeqEnd(User)) 2899 return Result; 2900 } 2901 return 0; 2902} 2903 2904/// FindCallSeqStart - Given a chained node that is part of a call sequence, 2905/// find the CALLSEQ_START node that initiates the call sequence. 2906static SDNode *FindCallSeqStart(SDNode *Node) { 2907 assert(Node && "Didn't find callseq_start for a call??"); 2908 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 2909 2910 assert(Node->getOperand(0).getValueType() == MVT::Other && 2911 "Node doesn't have a token chain argument!"); 2912 return FindCallSeqStart(Node->getOperand(0).Val); 2913} 2914 2915 2916/// FindInputOutputChains - If we are replacing an operation with a call we need 2917/// to find the call that occurs before and the call that occurs after it to 2918/// properly serialize the calls in the block. The returned operand is the 2919/// input chain value for the new call (e.g. the entry node or the previous 2920/// call), and OutChain is set to be the chain node to update to point to the 2921/// end of the call chain. 2922static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 2923 SDOperand Entry) { 2924 SDNode *LatestCallSeqStart = Entry.Val; 2925 SDNode *LatestCallSeqEnd = 0; 2926 std::set<SDNode*> Visited; 2927 FindLatestCallSeqStart(OpNode, LatestCallSeqStart, Visited); 2928 Visited.clear(); 2929 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 2930 2931 // It is possible that no ISD::CALLSEQ_START was found because there is no 2932 // previous call in the function. LatestCallStackDown may in that case be 2933 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 2934 // unless LatestCallStackDown is an CALLSEQ_START. 2935 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) { 2936 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 2937 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n"; 2938 } else { 2939 LatestCallSeqEnd = Entry.Val; 2940 } 2941 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 2942 2943 // Finally, find the first call that this must come before, first we find the 2944 // CallSeqEnd that ends the call. 2945 OutChain = 0; 2946 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 2947 Visited.clear(); 2948 2949 // If we found one, translate from the adj up to the callseq_start. 2950 if (OutChain) 2951 OutChain = FindCallSeqStart(OutChain); 2952 2953 return SDOperand(LatestCallSeqEnd, 0); 2954} 2955 2956/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 2957void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 2958 SDNode *OutChain) { 2959 // Nothing to splice it into? 2960 if (OutChain == 0) return; 2961 2962 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 2963 //OutChain->dump(); 2964 2965 // Form a token factor node merging the old inval and the new inval. 2966 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 2967 OutChain->getOperand(0)); 2968 // Change the node to refer to the new token. 2969 std::vector<SDOperand> Ops(OutChain->op_begin(), OutChain->op_end()); 2970 Ops[0] = InToken; 2971 SDOperand Res = DAG.UpdateNodeOperands(SDOperand(OutChain, 0), Ops); 2972 assert(Res.Val == OutChain && "Didn't update in place!"); 2973} 2974 2975 2976// ExpandLibCall - Expand a node into a call to a libcall. If the result value 2977// does not fit into a register, return the lo part and set the hi part to the 2978// by-reg argument. If it does fit into a single register, return the result 2979// and leave the Hi part unset. 2980SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 2981 SDOperand &Hi) { 2982 SDNode *OutChain; 2983 SDOperand InChain = FindInputOutputChains(Node, OutChain, 2984 DAG.getEntryNode()); 2985 if (InChain.Val == 0) 2986 InChain = DAG.getEntryNode(); 2987 2988 TargetLowering::ArgListTy Args; 2989 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2990 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 2991 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 2992 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 2993 } 2994 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 2995 2996 // Splice the libcall in wherever FindInputOutputChains tells us to. 2997 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 2998 std::pair<SDOperand,SDOperand> CallInfo = 2999 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 3000 Callee, Args, DAG); 3001 3002 SDOperand Result; 3003 switch (getTypeAction(CallInfo.first.getValueType())) { 3004 default: assert(0 && "Unknown thing"); 3005 case Legal: 3006 Result = CallInfo.first; 3007 break; 3008 case Expand: 3009 ExpandOp(CallInfo.first, Result, Hi); 3010 break; 3011 } 3012 3013 CallInfo.second = LegalizeOp(CallInfo.second); 3014 SpliceCallInto(CallInfo.second, OutChain); 3015 return Result; 3016} 3017 3018 3019/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 3020/// destination type is legal. 3021SDOperand SelectionDAGLegalize:: 3022ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 3023 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 3024 assert(getTypeAction(Source.getValueType()) == Expand && 3025 "This is not an expansion!"); 3026 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 3027 3028 if (!isSigned) { 3029 assert(Source.getValueType() == MVT::i64 && 3030 "This only works for 64-bit -> FP"); 3031 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 3032 // incoming integer is set. To handle this, we dynamically test to see if 3033 // it is set, and, if so, add a fudge factor. 3034 SDOperand Lo, Hi; 3035 ExpandOp(Source, Lo, Hi); 3036 3037 // If this is unsigned, and not supported, first perform the conversion to 3038 // signed, then adjust the result if the sign bit is set. 3039 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 3040 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 3041 3042 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 3043 DAG.getConstant(0, Hi.getValueType()), 3044 ISD::SETLT); 3045 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3046 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3047 SignSet, Four, Zero); 3048 uint64_t FF = 0x5f800000ULL; 3049 if (TLI.isLittleEndian()) FF <<= 32; 3050 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3051 3052 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3053 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3054 SDOperand FudgeInReg; 3055 if (DestTy == MVT::f32) 3056 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3057 DAG.getSrcValue(NULL)); 3058 else { 3059 assert(DestTy == MVT::f64 && "Unexpected conversion"); 3060 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 3061 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 3062 } 3063 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 3064 } 3065 3066 // Check to see if the target has a custom way to lower this. If so, use it. 3067 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 3068 default: assert(0 && "This action not implemented for this operation!"); 3069 case TargetLowering::Legal: 3070 case TargetLowering::Expand: 3071 break; // This case is handled below. 3072 case TargetLowering::Custom: { 3073 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 3074 Source), DAG); 3075 if (NV.Val) 3076 return LegalizeOp(NV); 3077 break; // The target decided this was legal after all 3078 } 3079 } 3080 3081 // Expand the source, then glue it back together for the call. We must expand 3082 // the source in case it is shared (this pass of legalize must traverse it). 3083 SDOperand SrcLo, SrcHi; 3084 ExpandOp(Source, SrcLo, SrcHi); 3085 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3086 3087 SDNode *OutChain = 0; 3088 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 3089 DAG.getEntryNode()); 3090 const char *FnName = 0; 3091 if (DestTy == MVT::f32) 3092 FnName = "__floatdisf"; 3093 else { 3094 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3095 FnName = "__floatdidf"; 3096 } 3097 3098 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 3099 3100 TargetLowering::ArgListTy Args; 3101 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 3102 3103 Args.push_back(std::make_pair(Source, ArgTy)); 3104 3105 // We don't care about token chains for libcalls. We just use the entry 3106 // node as our input and ignore the output chain. This allows us to place 3107 // calls wherever we need them to satisfy data dependences. 3108 const Type *RetTy = MVT::getTypeForValueType(DestTy); 3109 3110 std::pair<SDOperand,SDOperand> CallResult = 3111 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 3112 Callee, Args, DAG); 3113 3114 SpliceCallInto(CallResult.second, OutChain); 3115 return CallResult.first; 3116} 3117 3118/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 3119/// INT_TO_FP operation of the specified operand when the target requests that 3120/// we expand it. At this point, we know that the result and operand types are 3121/// legal for the target. 3122SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 3123 SDOperand Op0, 3124 MVT::ValueType DestVT) { 3125 if (Op0.getValueType() == MVT::i32) { 3126 // simple 32-bit [signed|unsigned] integer to float/double expansion 3127 3128 // get the stack frame index of a 8 byte buffer 3129 MachineFunction &MF = DAG.getMachineFunction(); 3130 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 3131 // get address of 8 byte buffer 3132 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3133 // word offset constant for Hi/Lo address computation 3134 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 3135 // set up Hi and Lo (into buffer) address based on endian 3136 SDOperand Hi, Lo; 3137 if (TLI.isLittleEndian()) { 3138 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 3139 Lo = StackSlot; 3140 } else { 3141 Hi = StackSlot; 3142 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 3143 } 3144 // if signed map to unsigned space 3145 SDOperand Op0Mapped; 3146 if (isSigned) { 3147 // constant used to invert sign bit (signed to unsigned mapping) 3148 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 3149 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 3150 } else { 3151 Op0Mapped = Op0; 3152 } 3153 // store the lo of the constructed double - based on integer input 3154 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3155 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 3156 // initial hi portion of constructed double 3157 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 3158 // store the hi of the constructed double - biased exponent 3159 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 3160 InitialHi, Hi, DAG.getSrcValue(NULL)); 3161 // load the constructed double 3162 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 3163 DAG.getSrcValue(NULL)); 3164 // FP constant to bias correct the final result 3165 SDOperand Bias = DAG.getConstantFP(isSigned ? 3166 BitsToDouble(0x4330000080000000ULL) 3167 : BitsToDouble(0x4330000000000000ULL), 3168 MVT::f64); 3169 // subtract the bias 3170 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 3171 // final result 3172 SDOperand Result; 3173 // handle final rounding 3174 if (DestVT == MVT::f64) { 3175 // do nothing 3176 Result = Sub; 3177 } else { 3178 // if f32 then cast to f32 3179 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 3180 } 3181 return Result; 3182 } 3183 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 3184 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 3185 3186 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 3187 DAG.getConstant(0, Op0.getValueType()), 3188 ISD::SETLT); 3189 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3190 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3191 SignSet, Four, Zero); 3192 3193 // If the sign bit of the integer is set, the large number will be treated 3194 // as a negative number. To counteract this, the dynamic code adds an 3195 // offset depending on the data type. 3196 uint64_t FF; 3197 switch (Op0.getValueType()) { 3198 default: assert(0 && "Unsupported integer type!"); 3199 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 3200 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 3201 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 3202 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 3203 } 3204 if (TLI.isLittleEndian()) FF <<= 32; 3205 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3206 3207 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3208 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3209 SDOperand FudgeInReg; 3210 if (DestVT == MVT::f32) 3211 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3212 DAG.getSrcValue(NULL)); 3213 else { 3214 assert(DestVT == MVT::f64 && "Unexpected conversion"); 3215 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 3216 DAG.getEntryNode(), CPIdx, 3217 DAG.getSrcValue(NULL), MVT::f32)); 3218 } 3219 3220 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 3221} 3222 3223/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 3224/// *INT_TO_FP operation of the specified operand when the target requests that 3225/// we promote it. At this point, we know that the result and operand types are 3226/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 3227/// operation that takes a larger input. 3228SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 3229 MVT::ValueType DestVT, 3230 bool isSigned) { 3231 // First step, figure out the appropriate *INT_TO_FP operation to use. 3232 MVT::ValueType NewInTy = LegalOp.getValueType(); 3233 3234 unsigned OpToUse = 0; 3235 3236 // Scan for the appropriate larger type to use. 3237 while (1) { 3238 NewInTy = (MVT::ValueType)(NewInTy+1); 3239 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 3240 3241 // If the target supports SINT_TO_FP of this type, use it. 3242 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 3243 default: break; 3244 case TargetLowering::Legal: 3245 if (!TLI.isTypeLegal(NewInTy)) 3246 break; // Can't use this datatype. 3247 // FALL THROUGH. 3248 case TargetLowering::Custom: 3249 OpToUse = ISD::SINT_TO_FP; 3250 break; 3251 } 3252 if (OpToUse) break; 3253 if (isSigned) continue; 3254 3255 // If the target supports UINT_TO_FP of this type, use it. 3256 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 3257 default: break; 3258 case TargetLowering::Legal: 3259 if (!TLI.isTypeLegal(NewInTy)) 3260 break; // Can't use this datatype. 3261 // FALL THROUGH. 3262 case TargetLowering::Custom: 3263 OpToUse = ISD::UINT_TO_FP; 3264 break; 3265 } 3266 if (OpToUse) break; 3267 3268 // Otherwise, try a larger type. 3269 } 3270 3271 // Okay, we found the operation and type to use. Zero extend our input to the 3272 // desired type then run the operation on it. 3273 return DAG.getNode(OpToUse, DestVT, 3274 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 3275 NewInTy, LegalOp)); 3276} 3277 3278/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 3279/// FP_TO_*INT operation of the specified operand when the target requests that 3280/// we promote it. At this point, we know that the result and operand types are 3281/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 3282/// operation that returns a larger result. 3283SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 3284 MVT::ValueType DestVT, 3285 bool isSigned) { 3286 // First step, figure out the appropriate FP_TO*INT operation to use. 3287 MVT::ValueType NewOutTy = DestVT; 3288 3289 unsigned OpToUse = 0; 3290 3291 // Scan for the appropriate larger type to use. 3292 while (1) { 3293 NewOutTy = (MVT::ValueType)(NewOutTy+1); 3294 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 3295 3296 // If the target supports FP_TO_SINT returning this type, use it. 3297 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 3298 default: break; 3299 case TargetLowering::Legal: 3300 if (!TLI.isTypeLegal(NewOutTy)) 3301 break; // Can't use this datatype. 3302 // FALL THROUGH. 3303 case TargetLowering::Custom: 3304 OpToUse = ISD::FP_TO_SINT; 3305 break; 3306 } 3307 if (OpToUse) break; 3308 3309 // If the target supports FP_TO_UINT of this type, use it. 3310 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 3311 default: break; 3312 case TargetLowering::Legal: 3313 if (!TLI.isTypeLegal(NewOutTy)) 3314 break; // Can't use this datatype. 3315 // FALL THROUGH. 3316 case TargetLowering::Custom: 3317 OpToUse = ISD::FP_TO_UINT; 3318 break; 3319 } 3320 if (OpToUse) break; 3321 3322 // Otherwise, try a larger type. 3323 } 3324 3325 // Okay, we found the operation and type to use. Truncate the result of the 3326 // extended FP_TO_*INT operation to the desired size. 3327 return DAG.getNode(ISD::TRUNCATE, DestVT, 3328 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 3329} 3330 3331/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 3332/// 3333SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 3334 MVT::ValueType VT = Op.getValueType(); 3335 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 3336 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 3337 switch (VT) { 3338 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 3339 case MVT::i16: 3340 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 3341 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 3342 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 3343 case MVT::i32: 3344 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 3345 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 3346 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 3347 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 3348 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 3349 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 3350 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 3351 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 3352 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 3353 case MVT::i64: 3354 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 3355 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 3356 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 3357 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 3358 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 3359 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 3360 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 3361 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 3362 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 3363 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 3364 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 3365 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 3366 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 3367 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 3368 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 3369 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 3370 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 3371 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 3372 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 3373 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 3374 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 3375 } 3376} 3377 3378/// ExpandBitCount - Expand the specified bitcount instruction into operations. 3379/// 3380SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 3381 switch (Opc) { 3382 default: assert(0 && "Cannot expand this yet!"); 3383 case ISD::CTPOP: { 3384 static const uint64_t mask[6] = { 3385 0x5555555555555555ULL, 0x3333333333333333ULL, 3386 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 3387 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 3388 }; 3389 MVT::ValueType VT = Op.getValueType(); 3390 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 3391 unsigned len = getSizeInBits(VT); 3392 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 3393 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 3394 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 3395 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 3396 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 3397 DAG.getNode(ISD::AND, VT, 3398 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 3399 } 3400 return Op; 3401 } 3402 case ISD::CTLZ: { 3403 // for now, we do this: 3404 // x = x | (x >> 1); 3405 // x = x | (x >> 2); 3406 // ... 3407 // x = x | (x >>16); 3408 // x = x | (x >>32); // for 64-bit input 3409 // return popcount(~x); 3410 // 3411 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 3412 MVT::ValueType VT = Op.getValueType(); 3413 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 3414 unsigned len = getSizeInBits(VT); 3415 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 3416 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 3417 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 3418 } 3419 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 3420 return DAG.getNode(ISD::CTPOP, VT, Op); 3421 } 3422 case ISD::CTTZ: { 3423 // for now, we use: { return popcount(~x & (x - 1)); } 3424 // unless the target has ctlz but not ctpop, in which case we use: 3425 // { return 32 - nlz(~x & (x-1)); } 3426 // see also http://www.hackersdelight.org/HDcode/ntz.cc 3427 MVT::ValueType VT = Op.getValueType(); 3428 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 3429 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 3430 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 3431 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 3432 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 3433 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 3434 TLI.isOperationLegal(ISD::CTLZ, VT)) 3435 return DAG.getNode(ISD::SUB, VT, 3436 DAG.getConstant(getSizeInBits(VT), VT), 3437 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 3438 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 3439 } 3440 } 3441} 3442 3443 3444/// ExpandOp - Expand the specified SDOperand into its two component pieces 3445/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 3446/// LegalizeNodes map is filled in for any results that are not expanded, the 3447/// ExpandedNodes map is filled in for any results that are expanded, and the 3448/// Lo/Hi values are returned. 3449void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 3450 MVT::ValueType VT = Op.getValueType(); 3451 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3452 SDNode *Node = Op.Val; 3453 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 3454 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 3455 "Cannot expand FP values!"); 3456 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 3457 "Cannot expand to FP value or to larger int value!"); 3458 3459 // See if we already expanded it. 3460 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 3461 = ExpandedNodes.find(Op); 3462 if (I != ExpandedNodes.end()) { 3463 Lo = I->second.first; 3464 Hi = I->second.second; 3465 return; 3466 } 3467 3468 switch (Node->getOpcode()) { 3469 case ISD::CopyFromReg: 3470 assert(0 && "CopyFromReg must be legal!"); 3471 default: 3472 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 3473 assert(0 && "Do not know how to expand this operator!"); 3474 abort(); 3475 case ISD::UNDEF: 3476 Lo = DAG.getNode(ISD::UNDEF, NVT); 3477 Hi = DAG.getNode(ISD::UNDEF, NVT); 3478 break; 3479 case ISD::Constant: { 3480 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 3481 Lo = DAG.getConstant(Cst, NVT); 3482 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 3483 break; 3484 } 3485 case ISD::ConstantVec: { 3486 unsigned NumElements = Node->getNumOperands(); 3487 // If we only have two elements left in the constant vector, just break it 3488 // apart into the two scalar constants it contains. Otherwise, bisect the 3489 // ConstantVec, and return each half as a new ConstantVec. 3490 // FIXME: this is hard coded as big endian, it may have to change to support 3491 // SSE and Alpha MVI 3492 if (NumElements == 2) { 3493 Hi = Node->getOperand(0); 3494 Lo = Node->getOperand(1); 3495 } else { 3496 NumElements /= 2; 3497 std::vector<SDOperand> LoOps, HiOps; 3498 for (unsigned I = 0, E = NumElements; I < E; ++I) { 3499 HiOps.push_back(Node->getOperand(I)); 3500 LoOps.push_back(Node->getOperand(I+NumElements)); 3501 } 3502 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps); 3503 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps); 3504 } 3505 break; 3506 } 3507 3508 case ISD::BUILD_PAIR: 3509 // Return the operands. 3510 Lo = Node->getOperand(0); 3511 Hi = Node->getOperand(1); 3512 break; 3513 3514 case ISD::SIGN_EXTEND_INREG: 3515 ExpandOp(Node->getOperand(0), Lo, Hi); 3516 // Sign extend the lo-part. 3517 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 3518 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 3519 TLI.getShiftAmountTy())); 3520 // sext_inreg the low part if needed. 3521 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 3522 break; 3523 3524 case ISD::BSWAP: { 3525 ExpandOp(Node->getOperand(0), Lo, Hi); 3526 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 3527 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 3528 Lo = TempLo; 3529 break; 3530 } 3531 3532 case ISD::CTPOP: 3533 ExpandOp(Node->getOperand(0), Lo, Hi); 3534 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 3535 DAG.getNode(ISD::CTPOP, NVT, Lo), 3536 DAG.getNode(ISD::CTPOP, NVT, Hi)); 3537 Hi = DAG.getConstant(0, NVT); 3538 break; 3539 3540 case ISD::CTLZ: { 3541 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 3542 ExpandOp(Node->getOperand(0), Lo, Hi); 3543 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3544 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 3545 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 3546 ISD::SETNE); 3547 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 3548 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 3549 3550 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 3551 Hi = DAG.getConstant(0, NVT); 3552 break; 3553 } 3554 3555 case ISD::CTTZ: { 3556 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 3557 ExpandOp(Node->getOperand(0), Lo, Hi); 3558 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3559 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 3560 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 3561 ISD::SETNE); 3562 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 3563 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 3564 3565 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 3566 Hi = DAG.getConstant(0, NVT); 3567 break; 3568 } 3569 3570 case ISD::VAARG: { 3571 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 3572 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 3573 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 3574 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 3575 3576 // Remember that we legalized the chain. 3577 Hi = LegalizeOp(Hi); 3578 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 3579 if (!TLI.isLittleEndian()) 3580 std::swap(Lo, Hi); 3581 break; 3582 } 3583 3584 case ISD::LOAD: { 3585 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 3586 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 3587 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3588 3589 // Increment the pointer to the other half. 3590 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 3591 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3592 getIntPtrConstant(IncrementSize)); 3593 // FIXME: This creates a bogus srcvalue! 3594 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3595 3596 // Build a factor node to remember that this load is independent of the 3597 // other one. 3598 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3599 Hi.getValue(1)); 3600 3601 // Remember that we legalized the chain. 3602 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 3603 if (!TLI.isLittleEndian()) 3604 std::swap(Lo, Hi); 3605 break; 3606 } 3607 case ISD::VLOAD: { 3608 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 3609 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 3610 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3611 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3612 3613 // If we only have two elements, turn into a pair of scalar loads. 3614 // FIXME: handle case where a vector of two elements is fine, such as 3615 // 2 x double on SSE2. 3616 if (NumElements == 2) { 3617 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3618 // Increment the pointer to the other half. 3619 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8; 3620 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3621 getIntPtrConstant(IncrementSize)); 3622 // FIXME: This creates a bogus srcvalue! 3623 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3624 } else { 3625 NumElements /= 2; // Split the vector in half 3626 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3627 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8; 3628 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3629 getIntPtrConstant(IncrementSize)); 3630 // FIXME: This creates a bogus srcvalue! 3631 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3632 } 3633 3634 // Build a factor node to remember that this load is independent of the 3635 // other one. 3636 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3637 Hi.getValue(1)); 3638 3639 // Remember that we legalized the chain. 3640 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 3641 if (!TLI.isLittleEndian()) 3642 std::swap(Lo, Hi); 3643 break; 3644 } 3645 case ISD::VADD: 3646 case ISD::VSUB: 3647 case ISD::VMUL: { 3648 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3649 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3650 SDOperand LL, LH, RL, RH; 3651 3652 ExpandOp(Node->getOperand(0), LL, LH); 3653 ExpandOp(Node->getOperand(1), RL, RH); 3654 3655 // If we only have two elements, turn into a pair of scalar loads. 3656 // FIXME: handle case where a vector of two elements is fine, such as 3657 // 2 x double on SSE2. 3658 if (NumElements == 2) { 3659 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT); 3660 Lo = DAG.getNode(Opc, EVT, LL, RL); 3661 Hi = DAG.getNode(Opc, EVT, LH, RH); 3662 } else { 3663 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2), 3664 LL.getOperand(3)); 3665 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2), 3666 LH.getOperand(3)); 3667 } 3668 break; 3669 } 3670 case ISD::AND: 3671 case ISD::OR: 3672 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 3673 SDOperand LL, LH, RL, RH; 3674 ExpandOp(Node->getOperand(0), LL, LH); 3675 ExpandOp(Node->getOperand(1), RL, RH); 3676 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 3677 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 3678 break; 3679 } 3680 case ISD::SELECT: { 3681 SDOperand LL, LH, RL, RH; 3682 ExpandOp(Node->getOperand(1), LL, LH); 3683 ExpandOp(Node->getOperand(2), RL, RH); 3684 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 3685 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 3686 break; 3687 } 3688 case ISD::SELECT_CC: { 3689 SDOperand TL, TH, FL, FH; 3690 ExpandOp(Node->getOperand(2), TL, TH); 3691 ExpandOp(Node->getOperand(3), FL, FH); 3692 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3693 Node->getOperand(1), TL, FL, Node->getOperand(4)); 3694 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3695 Node->getOperand(1), TH, FH, Node->getOperand(4)); 3696 break; 3697 } 3698 case ISD::SEXTLOAD: { 3699 SDOperand Chain = Node->getOperand(0); 3700 SDOperand Ptr = Node->getOperand(1); 3701 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3702 3703 if (EVT == NVT) 3704 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3705 else 3706 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3707 EVT); 3708 3709 // Remember that we legalized the chain. 3710 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 3711 3712 // The high part is obtained by SRA'ing all but one of the bits of the lo 3713 // part. 3714 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3715 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3716 TLI.getShiftAmountTy())); 3717 break; 3718 } 3719 case ISD::ZEXTLOAD: { 3720 SDOperand Chain = Node->getOperand(0); 3721 SDOperand Ptr = Node->getOperand(1); 3722 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3723 3724 if (EVT == NVT) 3725 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3726 else 3727 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3728 EVT); 3729 3730 // Remember that we legalized the chain. 3731 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 3732 3733 // The high part is just a zero. 3734 Hi = DAG.getConstant(0, NVT); 3735 break; 3736 } 3737 case ISD::EXTLOAD: { 3738 SDOperand Chain = Node->getOperand(0); 3739 SDOperand Ptr = Node->getOperand(1); 3740 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3741 3742 if (EVT == NVT) 3743 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3744 else 3745 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3746 EVT); 3747 3748 // Remember that we legalized the chain. 3749 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 3750 3751 // The high part is undefined. 3752 Hi = DAG.getNode(ISD::UNDEF, NVT); 3753 break; 3754 } 3755 case ISD::ANY_EXTEND: 3756 // The low part is any extension of the input (which degenerates to a copy). 3757 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 3758 // The high part is undefined. 3759 Hi = DAG.getNode(ISD::UNDEF, NVT); 3760 break; 3761 case ISD::SIGN_EXTEND: { 3762 // The low part is just a sign extension of the input (which degenerates to 3763 // a copy). 3764 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 3765 3766 // The high part is obtained by SRA'ing all but one of the bits of the lo 3767 // part. 3768 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3769 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 3770 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 3771 break; 3772 } 3773 case ISD::ZERO_EXTEND: 3774 // The low part is just a zero extension of the input (which degenerates to 3775 // a copy). 3776 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 3777 3778 // The high part is just a zero. 3779 Hi = DAG.getConstant(0, NVT); 3780 break; 3781 3782 case ISD::BIT_CONVERT: { 3783 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0), 3784 Node->getOperand(0)); 3785 ExpandOp(Tmp, Lo, Hi); 3786 break; 3787 } 3788 3789 case ISD::READCYCLECOUNTER: 3790 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 3791 TargetLowering::Custom && 3792 "Must custom expand ReadCycleCounter"); 3793 Lo = TLI.LowerOperation(Op, DAG); 3794 assert(Lo.Val && "Node must be custom expanded!"); 3795 Hi = Lo.getValue(1); 3796 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 3797 LegalizeOp(Lo.getValue(2))); 3798 break; 3799 3800 // These operators cannot be expanded directly, emit them as calls to 3801 // library functions. 3802 case ISD::FP_TO_SINT: 3803 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 3804 SDOperand Op; 3805 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3806 case Expand: assert(0 && "cannot expand FP!"); 3807 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3808 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 3809 } 3810 3811 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 3812 3813 // Now that the custom expander is done, expand the result, which is still 3814 // VT. 3815 if (Op.Val) { 3816 ExpandOp(Op, Lo, Hi); 3817 break; 3818 } 3819 } 3820 3821 if (Node->getOperand(0).getValueType() == MVT::f32) 3822 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 3823 else 3824 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 3825 break; 3826 3827 case ISD::FP_TO_UINT: 3828 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 3829 SDOperand Op; 3830 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3831 case Expand: assert(0 && "cannot expand FP!"); 3832 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3833 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 3834 } 3835 3836 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 3837 3838 // Now that the custom expander is done, expand the result. 3839 if (Op.Val) { 3840 ExpandOp(Op, Lo, Hi); 3841 break; 3842 } 3843 } 3844 3845 if (Node->getOperand(0).getValueType() == MVT::f32) 3846 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 3847 else 3848 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 3849 break; 3850 3851 case ISD::SHL: { 3852 // If the target wants custom lowering, do so. 3853 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 3854 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 3855 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 3856 Op = TLI.LowerOperation(Op, DAG); 3857 if (Op.Val) { 3858 // Now that the custom expander is done, expand the result, which is 3859 // still VT. 3860 ExpandOp(Op, Lo, Hi); 3861 break; 3862 } 3863 } 3864 3865 // If we can emit an efficient shift operation, do so now. 3866 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 3867 break; 3868 3869 // If this target supports SHL_PARTS, use it. 3870 TargetLowering::LegalizeAction Action = 3871 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 3872 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 3873 Action == TargetLowering::Custom) { 3874 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 3875 break; 3876 } 3877 3878 // Otherwise, emit a libcall. 3879 Lo = ExpandLibCall("__ashldi3", Node, Hi); 3880 break; 3881 } 3882 3883 case ISD::SRA: { 3884 // If the target wants custom lowering, do so. 3885 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 3886 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 3887 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 3888 Op = TLI.LowerOperation(Op, DAG); 3889 if (Op.Val) { 3890 // Now that the custom expander is done, expand the result, which is 3891 // still VT. 3892 ExpandOp(Op, Lo, Hi); 3893 break; 3894 } 3895 } 3896 3897 // If we can emit an efficient shift operation, do so now. 3898 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 3899 break; 3900 3901 // If this target supports SRA_PARTS, use it. 3902 TargetLowering::LegalizeAction Action = 3903 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 3904 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 3905 Action == TargetLowering::Custom) { 3906 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 3907 break; 3908 } 3909 3910 // Otherwise, emit a libcall. 3911 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 3912 break; 3913 } 3914 3915 case ISD::SRL: { 3916 // If the target wants custom lowering, do so. 3917 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 3918 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 3919 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 3920 Op = TLI.LowerOperation(Op, DAG); 3921 if (Op.Val) { 3922 // Now that the custom expander is done, expand the result, which is 3923 // still VT. 3924 ExpandOp(Op, Lo, Hi); 3925 break; 3926 } 3927 } 3928 3929 // If we can emit an efficient shift operation, do so now. 3930 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 3931 break; 3932 3933 // If this target supports SRL_PARTS, use it. 3934 TargetLowering::LegalizeAction Action = 3935 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 3936 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 3937 Action == TargetLowering::Custom) { 3938 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 3939 break; 3940 } 3941 3942 // Otherwise, emit a libcall. 3943 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 3944 break; 3945 } 3946 3947 case ISD::ADD: 3948 case ISD::SUB: { 3949 // If the target wants to custom expand this, let them. 3950 if (TLI.getOperationAction(Node->getOpcode(), VT) == 3951 TargetLowering::Custom) { 3952 Op = TLI.LowerOperation(Op, DAG); 3953 if (Op.Val) { 3954 ExpandOp(Op, Lo, Hi); 3955 break; 3956 } 3957 } 3958 3959 // Expand the subcomponents. 3960 SDOperand LHSL, LHSH, RHSL, RHSH; 3961 ExpandOp(Node->getOperand(0), LHSL, LHSH); 3962 ExpandOp(Node->getOperand(1), RHSL, RHSH); 3963 3964 std::vector<SDOperand> Ops; 3965 Ops.push_back(LHSL); 3966 Ops.push_back(LHSH); 3967 Ops.push_back(RHSL); 3968 Ops.push_back(RHSH); 3969 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 3970 unsigned Opc = 3971 Node->getOpcode() == ISD::ADD ? ISD::ADD_PARTS : ISD::SUB_PARTS; 3972 Lo = DAG.getNode(Opc, VTs, Ops); 3973 Hi = Lo.getValue(1); 3974 break; 3975 } 3976 case ISD::MUL: { 3977 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 3978 SDOperand LL, LH, RL, RH; 3979 ExpandOp(Node->getOperand(0), LL, LH); 3980 ExpandOp(Node->getOperand(1), RL, RH); 3981 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 3982 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 3983 // extended the sign bit of the low half through the upper half, and if so 3984 // emit a MULHS instead of the alternate sequence that is valid for any 3985 // i64 x i64 multiply. 3986 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 3987 // is RH an extension of the sign bit of RL? 3988 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 3989 RH.getOperand(1).getOpcode() == ISD::Constant && 3990 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 3991 // is LH an extension of the sign bit of LL? 3992 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 3993 LH.getOperand(1).getOpcode() == ISD::Constant && 3994 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 3995 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 3996 } else { 3997 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 3998 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 3999 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 4000 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 4001 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 4002 } 4003 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 4004 } else { 4005 Lo = ExpandLibCall("__muldi3" , Node, Hi); 4006 } 4007 break; 4008 } 4009 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 4010 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 4011 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 4012 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 4013 } 4014 4015 // Make sure the resultant values have been legalized themselves, unless this 4016 // is a type that requires multi-step expansion. 4017 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 4018 Lo = LegalizeOp(Lo); 4019 Hi = LegalizeOp(Hi); 4020 } 4021 4022 // Remember in a map if the values will be reused later. 4023 bool isNew = 4024 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 4025 assert(isNew && "Value already expanded?!?"); 4026} 4027 4028 4029// SelectionDAG::Legalize - This is the entry point for the file. 4030// 4031void SelectionDAG::Legalize() { 4032 /// run - This is the main entry point to this class. 4033 /// 4034 SelectionDAGLegalize(*this).LegalizeDAG(); 4035} 4036 4037