LegalizeDAG.cpp revision 7f042681764c6f8eae22781d8b4cb4c218a86b76
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetFrameInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/Target/TargetSubtarget.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Compiler.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/ADT/DenseMap.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/SmallPtrSet.h" 35#include <map> 36using namespace llvm; 37 38//===----------------------------------------------------------------------===// 39/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 40/// hacks on it until the target machine can handle it. This involves 41/// eliminating value sizes the machine cannot handle (promoting small sizes to 42/// large sizes or splitting up large values into small values) as well as 43/// eliminating operations the machine cannot handle. 44/// 45/// This code also does a small amount of optimization and recognition of idioms 46/// as part of its processing. For example, if a target does not support a 47/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 48/// will attempt merge setcc and brc instructions into brcc's. 49/// 50namespace { 51class VISIBILITY_HIDDEN SelectionDAGLegalize { 52 TargetLowering &TLI; 53 SelectionDAG &DAG; 54 55 // Libcall insertion helpers. 56 57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 58 /// legalized. We use this to ensure that calls are properly serialized 59 /// against each other, including inserted libcalls. 60 SDValue LastCALLSEQ_END; 61 62 /// IsLegalizingCall - This member is used *only* for purposes of providing 63 /// helpful assertions that a libcall isn't created while another call is 64 /// being legalized (which could lead to non-serialized call sequences). 65 bool IsLegalizingCall; 66 67 enum LegalizeAction { 68 Legal, // The target natively supports this operation. 69 Promote, // This operation should be executed in a larger type. 70 Expand // Try to expand this to other ops, otherwise use a libcall. 71 }; 72 73 /// ValueTypeActions - This is a bitvector that contains two bits for each 74 /// value type, where the two bits correspond to the LegalizeAction enum. 75 /// This can be queried with "getTypeAction(VT)". 76 TargetLowering::ValueTypeActionImpl ValueTypeActions; 77 78 /// LegalizedNodes - For nodes that are of legal width, and that have more 79 /// than one use, this map indicates what regularized operand to use. This 80 /// allows us to avoid legalizing the same thing more than once. 81 DenseMap<SDValue, SDValue> LegalizedNodes; 82 83 /// PromotedNodes - For nodes that are below legal width, and that have more 84 /// than one use, this map indicates what promoted value to use. This allows 85 /// us to avoid promoting the same thing more than once. 86 DenseMap<SDValue, SDValue> PromotedNodes; 87 88 /// ExpandedNodes - For nodes that need to be expanded this map indicates 89 /// which which operands are the expanded version of the input. This allows 90 /// us to avoid expanding the same node more than once. 91 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes; 92 93 /// SplitNodes - For vector nodes that need to be split, this map indicates 94 /// which which operands are the split version of the input. This allows us 95 /// to avoid splitting the same node more than once. 96 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes; 97 98 /// ScalarizedNodes - For nodes that need to be converted from vector types to 99 /// scalar types, this contains the mapping of ones we have already 100 /// processed to the result. 101 std::map<SDValue, SDValue> ScalarizedNodes; 102 103 void AddLegalizedOperand(SDValue From, SDValue To) { 104 LegalizedNodes.insert(std::make_pair(From, To)); 105 // If someone requests legalization of the new node, return itself. 106 if (From != To) 107 LegalizedNodes.insert(std::make_pair(To, To)); 108 } 109 void AddPromotedOperand(SDValue From, SDValue To) { 110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 111 assert(isNew && "Got into the map somehow?"); 112 // If someone requests legalization of the new node, return itself. 113 LegalizedNodes.insert(std::make_pair(To, To)); 114 } 115 116public: 117 explicit SelectionDAGLegalize(SelectionDAG &DAG); 118 119 /// getTypeAction - Return how we should legalize values of this type, either 120 /// it is already legal or we need to expand it into multiple registers of 121 /// smaller integer type, or we need to promote it to a larger type. 122 LegalizeAction getTypeAction(MVT VT) const { 123 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 124 } 125 126 /// isTypeLegal - Return true if this type is legal on this target. 127 /// 128 bool isTypeLegal(MVT VT) const { 129 return getTypeAction(VT) == Legal; 130 } 131 132 void LegalizeDAG(); 133 134private: 135 /// HandleOp - Legalize, Promote, or Expand the specified operand as 136 /// appropriate for its type. 137 void HandleOp(SDValue Op); 138 139 /// LegalizeOp - We know that the specified value has a legal type. 140 /// Recursively ensure that the operands have legal types, then return the 141 /// result. 142 SDValue LegalizeOp(SDValue O); 143 144 /// UnrollVectorOp - We know that the given vector has a legal type, however 145 /// the operation it performs is not legal and is an operation that we have 146 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 147 /// operating on each element individually. 148 SDValue UnrollVectorOp(SDValue O); 149 150 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 151 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 152 /// is necessary to spill the vector being inserted into to memory, perform 153 /// the insert there, and then read the result back. 154 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 155 SDValue Idx); 156 157 /// PromoteOp - Given an operation that produces a value in an invalid type, 158 /// promote it to compute the value into a larger type. The produced value 159 /// will have the correct bits for the low portion of the register, but no 160 /// guarantee is made about the top bits: it may be zero, sign-extended, or 161 /// garbage. 162 SDValue PromoteOp(SDValue O); 163 164 /// ExpandOp - Expand the specified SDValue into its two component pieces 165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 166 /// the LegalizedNodes map is filled in for any results that are not expanded, 167 /// the ExpandedNodes map is filled in for any results that are expanded, and 168 /// the Lo/Hi values are returned. This applies to integer types and Vector 169 /// types. 170 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi); 171 172 /// SplitVectorOp - Given an operand of vector type, break it down into 173 /// two smaller values. 174 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi); 175 176 /// ScalarizeVectorOp - Given an operand of single-element vector type 177 /// (e.g. v1f32), convert it into the equivalent operation that returns a 178 /// scalar (e.g. f32) value. 179 SDValue ScalarizeVectorOp(SDValue O); 180 181 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the 182 /// specified mask and type. Targets can specify exactly which masks they 183 /// support and the code generator is tasked with not creating illegal masks. 184 /// 185 /// Note that this will also return true for shuffles that are promoted to a 186 /// different type. 187 /// 188 /// If this is a legal shuffle, this method returns the (possibly promoted) 189 /// build_vector Mask. If it's not a legal shuffle, it returns null. 190 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const; 191 192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 194 195 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC); 196 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC); 197 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC) { 198 LegalizeSetCCOperands(LHS, RHS, CC); 199 LegalizeSetCCCondCode(VT, LHS, RHS, CC); 200 } 201 202 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, 203 SDValue &Hi); 204 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source); 205 206 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT); 207 SDValue ExpandBUILD_VECTOR(SDNode *Node); 208 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 209 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op); 210 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT); 211 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned); 212 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned); 213 214 SDValue ExpandBSWAP(SDValue Op); 215 SDValue ExpandBitCount(unsigned Opc, SDValue Op); 216 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt, 217 SDValue &Lo, SDValue &Hi); 218 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt, 219 SDValue &Lo, SDValue &Hi); 220 221 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op); 222 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op); 223}; 224} 225 226/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 227/// specified mask and type. Targets can specify exactly which masks they 228/// support and the code generator is tasked with not creating illegal masks. 229/// 230/// Note that this will also return true for shuffles that are promoted to a 231/// different type. 232SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const { 233 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 234 default: return 0; 235 case TargetLowering::Legal: 236 case TargetLowering::Custom: 237 break; 238 case TargetLowering::Promote: { 239 // If this is promoted to a different type, convert the shuffle mask and 240 // ask if it is legal in the promoted type! 241 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 242 MVT EltVT = NVT.getVectorElementType(); 243 244 // If we changed # elements, change the shuffle mask. 245 unsigned NumEltsGrowth = 246 NVT.getVectorNumElements() / VT.getVectorNumElements(); 247 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 248 if (NumEltsGrowth > 1) { 249 // Renumber the elements. 250 SmallVector<SDValue, 8> Ops; 251 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 252 SDValue InOp = Mask.getOperand(i); 253 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 254 if (InOp.getOpcode() == ISD::UNDEF) 255 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 256 else { 257 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue(); 258 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT)); 259 } 260 } 261 } 262 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 263 } 264 VT = NVT; 265 break; 266 } 267 } 268 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0; 269} 270 271SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 272 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 273 ValueTypeActions(TLI.getValueTypeActions()) { 274 assert(MVT::LAST_VALUETYPE <= 32 && 275 "Too many value types for ValueTypeActions to hold!"); 276} 277 278void SelectionDAGLegalize::LegalizeDAG() { 279 LastCALLSEQ_END = DAG.getEntryNode(); 280 IsLegalizingCall = false; 281 282 // The legalize process is inherently a bottom-up recursive process (users 283 // legalize their uses before themselves). Given infinite stack space, we 284 // could just start legalizing on the root and traverse the whole graph. In 285 // practice however, this causes us to run out of stack space on large basic 286 // blocks. To avoid this problem, compute an ordering of the nodes where each 287 // node is only legalized after all of its operands are legalized. 288 DAG.AssignTopologicalOrder(); 289 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 290 E = prior(DAG.allnodes_end()); I != next(E); ++I) 291 HandleOp(SDValue(I, 0)); 292 293 // Finally, it's possible the root changed. Get the new root. 294 SDValue OldRoot = DAG.getRoot(); 295 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 296 DAG.setRoot(LegalizedNodes[OldRoot]); 297 298 ExpandedNodes.clear(); 299 LegalizedNodes.clear(); 300 PromotedNodes.clear(); 301 SplitNodes.clear(); 302 ScalarizedNodes.clear(); 303 304 // Remove dead nodes now. 305 DAG.RemoveDeadNodes(); 306} 307 308 309/// FindCallEndFromCallStart - Given a chained node that is part of a call 310/// sequence, find the CALLSEQ_END node that terminates the call sequence. 311static SDNode *FindCallEndFromCallStart(SDNode *Node) { 312 if (Node->getOpcode() == ISD::CALLSEQ_END) 313 return Node; 314 if (Node->use_empty()) 315 return 0; // No CallSeqEnd 316 317 // The chain is usually at the end. 318 SDValue TheChain(Node, Node->getNumValues()-1); 319 if (TheChain.getValueType() != MVT::Other) { 320 // Sometimes it's at the beginning. 321 TheChain = SDValue(Node, 0); 322 if (TheChain.getValueType() != MVT::Other) { 323 // Otherwise, hunt for it. 324 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 325 if (Node->getValueType(i) == MVT::Other) { 326 TheChain = SDValue(Node, i); 327 break; 328 } 329 330 // Otherwise, we walked into a node without a chain. 331 if (TheChain.getValueType() != MVT::Other) 332 return 0; 333 } 334 } 335 336 for (SDNode::use_iterator UI = Node->use_begin(), 337 E = Node->use_end(); UI != E; ++UI) { 338 339 // Make sure to only follow users of our token chain. 340 SDNode *User = *UI; 341 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 342 if (User->getOperand(i) == TheChain) 343 if (SDNode *Result = FindCallEndFromCallStart(User)) 344 return Result; 345 } 346 return 0; 347} 348 349/// FindCallStartFromCallEnd - Given a chained node that is part of a call 350/// sequence, find the CALLSEQ_START node that initiates the call sequence. 351static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 352 assert(Node && "Didn't find callseq_start for a call??"); 353 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 354 355 assert(Node->getOperand(0).getValueType() == MVT::Other && 356 "Node doesn't have a token chain argument!"); 357 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 358} 359 360/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 361/// see if any uses can reach Dest. If no dest operands can get to dest, 362/// legalize them, legalize ourself, and return false, otherwise, return true. 363/// 364/// Keep track of the nodes we fine that actually do lead to Dest in 365/// NodesLeadingTo. This avoids retraversing them exponential number of times. 366/// 367bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 368 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 369 if (N == Dest) return true; // N certainly leads to Dest :) 370 371 // If we've already processed this node and it does lead to Dest, there is no 372 // need to reprocess it. 373 if (NodesLeadingTo.count(N)) return true; 374 375 // If the first result of this node has been already legalized, then it cannot 376 // reach N. 377 switch (getTypeAction(N->getValueType(0))) { 378 case Legal: 379 if (LegalizedNodes.count(SDValue(N, 0))) return false; 380 break; 381 case Promote: 382 if (PromotedNodes.count(SDValue(N, 0))) return false; 383 break; 384 case Expand: 385 if (ExpandedNodes.count(SDValue(N, 0))) return false; 386 break; 387 } 388 389 // Okay, this node has not already been legalized. Check and legalize all 390 // operands. If none lead to Dest, then we can legalize this node. 391 bool OperandsLeadToDest = false; 392 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 393 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 394 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 395 396 if (OperandsLeadToDest) { 397 NodesLeadingTo.insert(N); 398 return true; 399 } 400 401 // Okay, this node looks safe, legalize it and return false. 402 HandleOp(SDValue(N, 0)); 403 return false; 404} 405 406/// HandleOp - Legalize, Promote, or Expand the specified operand as 407/// appropriate for its type. 408void SelectionDAGLegalize::HandleOp(SDValue Op) { 409 MVT VT = Op.getValueType(); 410 switch (getTypeAction(VT)) { 411 default: assert(0 && "Bad type action!"); 412 case Legal: (void)LegalizeOp(Op); break; 413 case Promote: (void)PromoteOp(Op); break; 414 case Expand: 415 if (!VT.isVector()) { 416 // If this is an illegal scalar, expand it into its two component 417 // pieces. 418 SDValue X, Y; 419 if (Op.getOpcode() == ISD::TargetConstant) 420 break; // Allow illegal target nodes. 421 ExpandOp(Op, X, Y); 422 } else if (VT.getVectorNumElements() == 1) { 423 // If this is an illegal single element vector, convert it to a 424 // scalar operation. 425 (void)ScalarizeVectorOp(Op); 426 } else { 427 // Otherwise, this is an illegal multiple element vector. 428 // Split it in half and legalize both parts. 429 SDValue X, Y; 430 SplitVectorOp(Op, X, Y); 431 } 432 break; 433 } 434} 435 436/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 437/// a load from the constant pool. 438static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 439 SelectionDAG &DAG, TargetLowering &TLI) { 440 bool Extend = false; 441 442 // If a FP immediate is precise when represented as a float and if the 443 // target can do an extending load from float to double, we put it into 444 // the constant pool as a float, even if it's is statically typed as a 445 // double. This shrinks FP constants and canonicalizes them for targets where 446 // an FP extending load is the same cost as a normal load (such as on the x87 447 // fp stack or PPC FP unit). 448 MVT VT = CFP->getValueType(0); 449 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 450 if (!UseCP) { 451 if (VT!=MVT::f64 && VT!=MVT::f32) 452 assert(0 && "Invalid type expansion"); 453 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 454 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 455 } 456 457 MVT OrigVT = VT; 458 MVT SVT = VT; 459 while (SVT != MVT::f32) { 460 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 461 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 462 // Only do this if the target has a native EXTLOAD instruction from 463 // smaller type. 464 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 465 TLI.ShouldShrinkFPConstant(OrigVT)) { 466 const Type *SType = SVT.getTypeForMVT(); 467 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 468 VT = SVT; 469 Extend = true; 470 } 471 } 472 473 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 474 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 475 if (Extend) 476 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), 477 CPIdx, PseudoSourceValue::getConstantPool(), 478 0, VT, false, Alignment); 479 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, 480 PseudoSourceValue::getConstantPool(), 0, false, Alignment); 481} 482 483 484/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 485/// operations. 486static 487SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, 488 SelectionDAG &DAG, TargetLowering &TLI) { 489 MVT VT = Node->getValueType(0); 490 MVT SrcVT = Node->getOperand(1).getValueType(); 491 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 492 "fcopysign expansion only supported for f32 and f64"); 493 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 494 495 // First get the sign bit of second operand. 496 SDValue Mask1 = (SrcVT == MVT::f64) 497 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 498 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 499 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 500 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 501 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 502 // Shift right or sign-extend it if the two operands have different types. 503 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); 504 if (SizeDiff > 0) { 505 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 506 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 507 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 508 } else if (SizeDiff < 0) { 509 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit); 510 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit, 511 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy())); 512 } 513 514 // Clear the sign bit of first operand. 515 SDValue Mask2 = (VT == MVT::f64) 516 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 517 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 518 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 519 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 520 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 521 522 // Or the value with the sign bit. 523 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 524 return Result; 525} 526 527/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 528static 529SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 530 TargetLowering &TLI) { 531 SDValue Chain = ST->getChain(); 532 SDValue Ptr = ST->getBasePtr(); 533 SDValue Val = ST->getValue(); 534 MVT VT = Val.getValueType(); 535 int Alignment = ST->getAlignment(); 536 int SVOffset = ST->getSrcValueOffset(); 537 if (ST->getMemoryVT().isFloatingPoint() || 538 ST->getMemoryVT().isVector()) { 539 // Expand to a bitconvert of the value to the integer type of the 540 // same size, then a (misaligned) int store. 541 MVT intVT; 542 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128) 543 intVT = MVT::i128; 544 else if (VT.is64BitVector() || VT==MVT::f64) 545 intVT = MVT::i64; 546 else if (VT==MVT::f32) 547 intVT = MVT::i32; 548 else 549 assert(0 && "Unaligned store of unsupported type"); 550 551 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 552 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 553 SVOffset, ST->isVolatile(), Alignment); 554 } 555 assert(ST->getMemoryVT().isInteger() && 556 !ST->getMemoryVT().isVector() && 557 "Unaligned store of unknown type."); 558 // Get the half-size VT 559 MVT NewStoredVT = 560 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 561 int NumBits = NewStoredVT.getSizeInBits(); 562 int IncrementSize = NumBits / 8; 563 564 // Divide the stored value in two parts. 565 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 566 SDValue Lo = Val; 567 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 568 569 // Store the two parts 570 SDValue Store1, Store2; 571 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 572 ST->getSrcValue(), SVOffset, NewStoredVT, 573 ST->isVolatile(), Alignment); 574 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 575 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 576 Alignment = MinAlign(Alignment, IncrementSize); 577 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 578 ST->getSrcValue(), SVOffset + IncrementSize, 579 NewStoredVT, ST->isVolatile(), Alignment); 580 581 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 582} 583 584/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 585static 586SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 587 TargetLowering &TLI) { 588 int SVOffset = LD->getSrcValueOffset(); 589 SDValue Chain = LD->getChain(); 590 SDValue Ptr = LD->getBasePtr(); 591 MVT VT = LD->getValueType(0); 592 MVT LoadedVT = LD->getMemoryVT(); 593 if (VT.isFloatingPoint() || VT.isVector()) { 594 // Expand to a (misaligned) integer load of the same size, 595 // then bitconvert to floating point or vector. 596 MVT intVT; 597 if (LoadedVT.is128BitVector() || 598 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128) 599 intVT = MVT::i128; 600 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64) 601 intVT = MVT::i64; 602 else if (LoadedVT == MVT::f32) 603 intVT = MVT::i32; 604 else 605 assert(0 && "Unaligned load of unsupported type"); 606 607 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 608 SVOffset, LD->isVolatile(), 609 LD->getAlignment()); 610 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 611 if (VT.isFloatingPoint() && LoadedVT != VT) 612 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 613 614 SDValue Ops[] = { Result, Chain }; 615 return DAG.getMergeValues(Ops, 2); 616 } 617 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 618 "Unaligned load of unsupported type."); 619 620 // Compute the new VT that is half the size of the old one. This is an 621 // integer MVT. 622 unsigned NumBits = LoadedVT.getSizeInBits(); 623 MVT NewLoadedVT; 624 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 625 NumBits >>= 1; 626 627 unsigned Alignment = LD->getAlignment(); 628 unsigned IncrementSize = NumBits / 8; 629 ISD::LoadExtType HiExtType = LD->getExtensionType(); 630 631 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 632 if (HiExtType == ISD::NON_EXTLOAD) 633 HiExtType = ISD::ZEXTLOAD; 634 635 // Load the value in two parts 636 SDValue Lo, Hi; 637 if (TLI.isLittleEndian()) { 638 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 639 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 640 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 641 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 642 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 643 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 644 MinAlign(Alignment, IncrementSize)); 645 } else { 646 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 647 NewLoadedVT,LD->isVolatile(), Alignment); 648 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 649 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 650 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 651 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 652 MinAlign(Alignment, IncrementSize)); 653 } 654 655 // aggregate the two parts 656 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 657 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 658 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 659 660 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 661 Hi.getValue(1)); 662 663 SDValue Ops[] = { Result, TF }; 664 return DAG.getMergeValues(Ops, 2); 665} 666 667/// UnrollVectorOp - We know that the given vector has a legal type, however 668/// the operation it performs is not legal and is an operation that we have 669/// no way of lowering. "Unroll" the vector, splitting out the scalars and 670/// operating on each element individually. 671SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) { 672 MVT VT = Op.getValueType(); 673 assert(isTypeLegal(VT) && 674 "Caller should expand or promote operands that are not legal!"); 675 assert(Op.getNode()->getNumValues() == 1 && 676 "Can't unroll a vector with multiple results!"); 677 unsigned NE = VT.getVectorNumElements(); 678 MVT EltVT = VT.getVectorElementType(); 679 680 SmallVector<SDValue, 8> Scalars; 681 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 682 for (unsigned i = 0; i != NE; ++i) { 683 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 684 SDValue Operand = Op.getOperand(j); 685 MVT OperandVT = Operand.getValueType(); 686 if (OperandVT.isVector()) { 687 // A vector operand; extract a single element. 688 MVT OperandEltVT = OperandVT.getVectorElementType(); 689 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 690 OperandEltVT, 691 Operand, 692 DAG.getConstant(i, MVT::i32)); 693 } else { 694 // A scalar operand; just use it as is. 695 Operands[j] = Operand; 696 } 697 } 698 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 699 &Operands[0], Operands.size())); 700 } 701 702 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 703} 704 705/// GetFPLibCall - Return the right libcall for the given floating point type. 706static RTLIB::Libcall GetFPLibCall(MVT VT, 707 RTLIB::Libcall Call_F32, 708 RTLIB::Libcall Call_F64, 709 RTLIB::Libcall Call_F80, 710 RTLIB::Libcall Call_PPCF128) { 711 return 712 VT == MVT::f32 ? Call_F32 : 713 VT == MVT::f64 ? Call_F64 : 714 VT == MVT::f80 ? Call_F80 : 715 VT == MVT::ppcf128 ? Call_PPCF128 : 716 RTLIB::UNKNOWN_LIBCALL; 717} 718 719/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 720/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 721/// is necessary to spill the vector being inserted into to memory, perform 722/// the insert there, and then read the result back. 723SDValue SelectionDAGLegalize:: 724PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) { 725 SDValue Tmp1 = Vec; 726 SDValue Tmp2 = Val; 727 SDValue Tmp3 = Idx; 728 729 // If the target doesn't support this, we have to spill the input vector 730 // to a temporary stack slot, update the element, then reload it. This is 731 // badness. We could also load the value into a vector register (either 732 // with a "move to register" or "extload into register" instruction, then 733 // permute it into place, if the idx is a constant and if the idx is 734 // supported by the target. 735 MVT VT = Tmp1.getValueType(); 736 MVT EltVT = VT.getVectorElementType(); 737 MVT IdxVT = Tmp3.getValueType(); 738 MVT PtrVT = TLI.getPointerTy(); 739 SDValue StackPtr = DAG.CreateStackTemporary(VT); 740 741 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 742 743 // Store the vector. 744 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, 745 PseudoSourceValue::getFixedStack(SPFI), 0); 746 747 // Truncate or zero extend offset to target pointer type. 748 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 749 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 750 // Add the offset to the index. 751 unsigned EltSize = EltVT.getSizeInBits()/8; 752 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 753 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 754 // Store the scalar value. 755 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, 756 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); 757 // Load the updated vector. 758 return DAG.getLoad(VT, Ch, StackPtr, 759 PseudoSourceValue::getFixedStack(SPFI), 0); 760} 761 762/// LegalizeOp - We know that the specified value has a legal type, and 763/// that its operands are legal. Now ensure that the operation itself 764/// is legal, recursively ensuring that the operands' operations remain 765/// legal. 766SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 767 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 768 return Op; 769 770 assert(isTypeLegal(Op.getValueType()) && 771 "Caller should expand or promote operands that are not legal!"); 772 SDNode *Node = Op.getNode(); 773 774 // If this operation defines any values that cannot be represented in a 775 // register on this target, make sure to expand or promote them. 776 if (Node->getNumValues() > 1) { 777 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 778 if (getTypeAction(Node->getValueType(i)) != Legal) { 779 HandleOp(Op.getValue(i)); 780 assert(LegalizedNodes.count(Op) && 781 "Handling didn't add legal operands!"); 782 return LegalizedNodes[Op]; 783 } 784 } 785 786 // Note that LegalizeOp may be reentered even from single-use nodes, which 787 // means that we always must cache transformed nodes. 788 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 789 if (I != LegalizedNodes.end()) return I->second; 790 791 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 792 SDValue Result = Op; 793 bool isCustom = false; 794 795 switch (Node->getOpcode()) { 796 case ISD::FrameIndex: 797 case ISD::EntryToken: 798 case ISD::Register: 799 case ISD::BasicBlock: 800 case ISD::TargetFrameIndex: 801 case ISD::TargetJumpTable: 802 case ISD::TargetConstant: 803 case ISD::TargetConstantFP: 804 case ISD::TargetConstantPool: 805 case ISD::TargetGlobalAddress: 806 case ISD::TargetGlobalTLSAddress: 807 case ISD::TargetExternalSymbol: 808 case ISD::VALUETYPE: 809 case ISD::SRCVALUE: 810 case ISD::MEMOPERAND: 811 case ISD::CONDCODE: 812 case ISD::ARG_FLAGS: 813 // Primitives must all be legal. 814 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 815 "This must be legal!"); 816 break; 817 default: 818 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 819 // If this is a target node, legalize it by legalizing the operands then 820 // passing it through. 821 SmallVector<SDValue, 8> Ops; 822 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 823 Ops.push_back(LegalizeOp(Node->getOperand(i))); 824 825 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 826 827 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 828 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 829 return Result.getValue(Op.getResNo()); 830 } 831 // Otherwise this is an unhandled builtin node. splat. 832#ifndef NDEBUG 833 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 834#endif 835 assert(0 && "Do not know how to legalize this operator!"); 836 abort(); 837 case ISD::GLOBAL_OFFSET_TABLE: 838 case ISD::GlobalAddress: 839 case ISD::GlobalTLSAddress: 840 case ISD::ExternalSymbol: 841 case ISD::ConstantPool: 842 case ISD::JumpTable: // Nothing to do. 843 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 844 default: assert(0 && "This action is not supported yet!"); 845 case TargetLowering::Custom: 846 Tmp1 = TLI.LowerOperation(Op, DAG); 847 if (Tmp1.getNode()) Result = Tmp1; 848 // FALLTHROUGH if the target doesn't want to lower this op after all. 849 case TargetLowering::Legal: 850 break; 851 } 852 break; 853 case ISD::FRAMEADDR: 854 case ISD::RETURNADDR: 855 // The only option for these nodes is to custom lower them. If the target 856 // does not custom lower them, then return zero. 857 Tmp1 = TLI.LowerOperation(Op, DAG); 858 if (Tmp1.getNode()) 859 Result = Tmp1; 860 else 861 Result = DAG.getConstant(0, TLI.getPointerTy()); 862 break; 863 case ISD::FRAME_TO_ARGS_OFFSET: { 864 MVT VT = Node->getValueType(0); 865 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 866 default: assert(0 && "This action is not supported yet!"); 867 case TargetLowering::Custom: 868 Result = TLI.LowerOperation(Op, DAG); 869 if (Result.getNode()) break; 870 // Fall Thru 871 case TargetLowering::Legal: 872 Result = DAG.getConstant(0, VT); 873 break; 874 } 875 } 876 break; 877 case ISD::EXCEPTIONADDR: { 878 Tmp1 = LegalizeOp(Node->getOperand(0)); 879 MVT VT = Node->getValueType(0); 880 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 881 default: assert(0 && "This action is not supported yet!"); 882 case TargetLowering::Expand: { 883 unsigned Reg = TLI.getExceptionAddressRegister(); 884 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 885 } 886 break; 887 case TargetLowering::Custom: 888 Result = TLI.LowerOperation(Op, DAG); 889 if (Result.getNode()) break; 890 // Fall Thru 891 case TargetLowering::Legal: { 892 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 893 Result = DAG.getMergeValues(Ops, 2); 894 break; 895 } 896 } 897 } 898 if (Result.getNode()->getNumValues() == 1) break; 899 900 assert(Result.getNode()->getNumValues() == 2 && 901 "Cannot return more than two values!"); 902 903 // Since we produced two values, make sure to remember that we 904 // legalized both of them. 905 Tmp1 = LegalizeOp(Result); 906 Tmp2 = LegalizeOp(Result.getValue(1)); 907 AddLegalizedOperand(Op.getValue(0), Tmp1); 908 AddLegalizedOperand(Op.getValue(1), Tmp2); 909 return Op.getResNo() ? Tmp2 : Tmp1; 910 case ISD::EHSELECTION: { 911 Tmp1 = LegalizeOp(Node->getOperand(0)); 912 Tmp2 = LegalizeOp(Node->getOperand(1)); 913 MVT VT = Node->getValueType(0); 914 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 915 default: assert(0 && "This action is not supported yet!"); 916 case TargetLowering::Expand: { 917 unsigned Reg = TLI.getExceptionSelectorRegister(); 918 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 919 } 920 break; 921 case TargetLowering::Custom: 922 Result = TLI.LowerOperation(Op, DAG); 923 if (Result.getNode()) break; 924 // Fall Thru 925 case TargetLowering::Legal: { 926 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 927 Result = DAG.getMergeValues(Ops, 2); 928 break; 929 } 930 } 931 } 932 if (Result.getNode()->getNumValues() == 1) break; 933 934 assert(Result.getNode()->getNumValues() == 2 && 935 "Cannot return more than two values!"); 936 937 // Since we produced two values, make sure to remember that we 938 // legalized both of them. 939 Tmp1 = LegalizeOp(Result); 940 Tmp2 = LegalizeOp(Result.getValue(1)); 941 AddLegalizedOperand(Op.getValue(0), Tmp1); 942 AddLegalizedOperand(Op.getValue(1), Tmp2); 943 return Op.getResNo() ? Tmp2 : Tmp1; 944 case ISD::EH_RETURN: { 945 MVT VT = Node->getValueType(0); 946 // The only "good" option for this node is to custom lower it. 947 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 948 default: assert(0 && "This action is not supported at all!"); 949 case TargetLowering::Custom: 950 Result = TLI.LowerOperation(Op, DAG); 951 if (Result.getNode()) break; 952 // Fall Thru 953 case TargetLowering::Legal: 954 // Target does not know, how to lower this, lower to noop 955 Result = LegalizeOp(Node->getOperand(0)); 956 break; 957 } 958 } 959 break; 960 case ISD::AssertSext: 961 case ISD::AssertZext: 962 Tmp1 = LegalizeOp(Node->getOperand(0)); 963 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 964 break; 965 case ISD::MERGE_VALUES: 966 // Legalize eliminates MERGE_VALUES nodes. 967 Result = Node->getOperand(Op.getResNo()); 968 break; 969 case ISD::CopyFromReg: 970 Tmp1 = LegalizeOp(Node->getOperand(0)); 971 Result = Op.getValue(0); 972 if (Node->getNumValues() == 2) { 973 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 974 } else { 975 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 976 if (Node->getNumOperands() == 3) { 977 Tmp2 = LegalizeOp(Node->getOperand(2)); 978 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 979 } else { 980 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 981 } 982 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 983 } 984 // Since CopyFromReg produces two values, make sure to remember that we 985 // legalized both of them. 986 AddLegalizedOperand(Op.getValue(0), Result); 987 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 988 return Result.getValue(Op.getResNo()); 989 case ISD::UNDEF: { 990 MVT VT = Op.getValueType(); 991 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 992 default: assert(0 && "This action is not supported yet!"); 993 case TargetLowering::Expand: 994 if (VT.isInteger()) 995 Result = DAG.getConstant(0, VT); 996 else if (VT.isFloatingPoint()) 997 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), 998 VT); 999 else 1000 assert(0 && "Unknown value type!"); 1001 break; 1002 case TargetLowering::Legal: 1003 break; 1004 } 1005 break; 1006 } 1007 1008 case ISD::INTRINSIC_W_CHAIN: 1009 case ISD::INTRINSIC_WO_CHAIN: 1010 case ISD::INTRINSIC_VOID: { 1011 SmallVector<SDValue, 8> Ops; 1012 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1013 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1014 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1015 1016 // Allow the target to custom lower its intrinsics if it wants to. 1017 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1018 TargetLowering::Custom) { 1019 Tmp3 = TLI.LowerOperation(Result, DAG); 1020 if (Tmp3.getNode()) Result = Tmp3; 1021 } 1022 1023 if (Result.getNode()->getNumValues() == 1) break; 1024 1025 // Must have return value and chain result. 1026 assert(Result.getNode()->getNumValues() == 2 && 1027 "Cannot return more than two values!"); 1028 1029 // Since loads produce two values, make sure to remember that we 1030 // legalized both of them. 1031 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1032 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1033 return Result.getValue(Op.getResNo()); 1034 } 1035 1036 case ISD::DBG_STOPPOINT: 1037 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!"); 1038 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1039 1040 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) { 1041 case TargetLowering::Promote: 1042 default: assert(0 && "This action is not supported yet!"); 1043 case TargetLowering::Expand: { 1044 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1045 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1046 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other); 1047 1048 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 1049 if (MMI && (useDEBUG_LOC || useLABEL)) { 1050 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit(); 1051 unsigned SrcFile = MMI->RecordSource(CompileUnit); 1052 1053 unsigned Line = DSP->getLine(); 1054 unsigned Col = DSP->getColumn(); 1055 1056 if (useDEBUG_LOC) { 1057 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32), 1058 DAG.getConstant(Col, MVT::i32), 1059 DAG.getConstant(SrcFile, MVT::i32) }; 1060 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4); 1061 } else { 1062 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); 1063 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID); 1064 } 1065 } else { 1066 Result = Tmp1; // chain 1067 } 1068 break; 1069 } 1070 case TargetLowering::Legal: { 1071 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1072 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1073 break; 1074 1075 SmallVector<SDValue, 8> Ops; 1076 Ops.push_back(Tmp1); 1077 if (Action == Legal) { 1078 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1079 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1080 } else { 1081 // Otherwise promote them. 1082 Ops.push_back(PromoteOp(Node->getOperand(1))); 1083 Ops.push_back(PromoteOp(Node->getOperand(2))); 1084 } 1085 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1086 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1087 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1088 break; 1089 } 1090 } 1091 break; 1092 1093 case ISD::DECLARE: 1094 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1095 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1096 default: assert(0 && "This action is not supported yet!"); 1097 case TargetLowering::Legal: 1098 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1099 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1100 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1102 break; 1103 case TargetLowering::Expand: 1104 Result = LegalizeOp(Node->getOperand(0)); 1105 break; 1106 } 1107 break; 1108 1109 case ISD::DEBUG_LOC: 1110 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1111 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1112 default: assert(0 && "This action is not supported yet!"); 1113 case TargetLowering::Legal: { 1114 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1115 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1116 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1117 break; 1118 if (Action == Legal) { 1119 Tmp2 = Node->getOperand(1); 1120 Tmp3 = Node->getOperand(2); 1121 Tmp4 = Node->getOperand(3); 1122 } else { 1123 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1124 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1125 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1126 } 1127 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1128 break; 1129 } 1130 } 1131 break; 1132 1133 case ISD::DBG_LABEL: 1134 case ISD::EH_LABEL: 1135 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!"); 1136 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1137 default: assert(0 && "This action is not supported yet!"); 1138 case TargetLowering::Legal: 1139 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1140 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1141 break; 1142 case TargetLowering::Expand: 1143 Result = LegalizeOp(Node->getOperand(0)); 1144 break; 1145 } 1146 break; 1147 1148 case ISD::PREFETCH: 1149 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1150 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1151 default: assert(0 && "This action is not supported yet!"); 1152 case TargetLowering::Legal: 1153 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1154 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1155 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1156 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1157 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1158 break; 1159 case TargetLowering::Expand: 1160 // It's a noop. 1161 Result = LegalizeOp(Node->getOperand(0)); 1162 break; 1163 } 1164 break; 1165 1166 case ISD::MEMBARRIER: { 1167 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1168 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1169 default: assert(0 && "This action is not supported yet!"); 1170 case TargetLowering::Legal: { 1171 SDValue Ops[6]; 1172 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1173 for (int x = 1; x < 6; ++x) { 1174 Ops[x] = Node->getOperand(x); 1175 if (!isTypeLegal(Ops[x].getValueType())) 1176 Ops[x] = PromoteOp(Ops[x]); 1177 } 1178 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1179 break; 1180 } 1181 case TargetLowering::Expand: 1182 //There is no libgcc call for this op 1183 Result = Node->getOperand(0); // Noop 1184 break; 1185 } 1186 break; 1187 } 1188 1189 case ISD::ATOMIC_CMP_SWAP_8: 1190 case ISD::ATOMIC_CMP_SWAP_16: 1191 case ISD::ATOMIC_CMP_SWAP_32: 1192 case ISD::ATOMIC_CMP_SWAP_64: { 1193 unsigned int num_operands = 4; 1194 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1195 SDValue Ops[4]; 1196 for (unsigned int x = 0; x < num_operands; ++x) 1197 Ops[x] = LegalizeOp(Node->getOperand(x)); 1198 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1199 1200 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1201 default: assert(0 && "This action is not supported yet!"); 1202 case TargetLowering::Custom: 1203 Result = TLI.LowerOperation(Result, DAG); 1204 break; 1205 case TargetLowering::Legal: 1206 break; 1207 } 1208 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1209 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1210 return Result.getValue(Op.getResNo()); 1211 } 1212 case ISD::ATOMIC_LOAD_ADD_8: 1213 case ISD::ATOMIC_LOAD_SUB_8: 1214 case ISD::ATOMIC_LOAD_AND_8: 1215 case ISD::ATOMIC_LOAD_OR_8: 1216 case ISD::ATOMIC_LOAD_XOR_8: 1217 case ISD::ATOMIC_LOAD_NAND_8: 1218 case ISD::ATOMIC_LOAD_MIN_8: 1219 case ISD::ATOMIC_LOAD_MAX_8: 1220 case ISD::ATOMIC_LOAD_UMIN_8: 1221 case ISD::ATOMIC_LOAD_UMAX_8: 1222 case ISD::ATOMIC_SWAP_8: 1223 case ISD::ATOMIC_LOAD_ADD_16: 1224 case ISD::ATOMIC_LOAD_SUB_16: 1225 case ISD::ATOMIC_LOAD_AND_16: 1226 case ISD::ATOMIC_LOAD_OR_16: 1227 case ISD::ATOMIC_LOAD_XOR_16: 1228 case ISD::ATOMIC_LOAD_NAND_16: 1229 case ISD::ATOMIC_LOAD_MIN_16: 1230 case ISD::ATOMIC_LOAD_MAX_16: 1231 case ISD::ATOMIC_LOAD_UMIN_16: 1232 case ISD::ATOMIC_LOAD_UMAX_16: 1233 case ISD::ATOMIC_SWAP_16: 1234 case ISD::ATOMIC_LOAD_ADD_32: 1235 case ISD::ATOMIC_LOAD_SUB_32: 1236 case ISD::ATOMIC_LOAD_AND_32: 1237 case ISD::ATOMIC_LOAD_OR_32: 1238 case ISD::ATOMIC_LOAD_XOR_32: 1239 case ISD::ATOMIC_LOAD_NAND_32: 1240 case ISD::ATOMIC_LOAD_MIN_32: 1241 case ISD::ATOMIC_LOAD_MAX_32: 1242 case ISD::ATOMIC_LOAD_UMIN_32: 1243 case ISD::ATOMIC_LOAD_UMAX_32: 1244 case ISD::ATOMIC_SWAP_32: 1245 case ISD::ATOMIC_LOAD_ADD_64: 1246 case ISD::ATOMIC_LOAD_SUB_64: 1247 case ISD::ATOMIC_LOAD_AND_64: 1248 case ISD::ATOMIC_LOAD_OR_64: 1249 case ISD::ATOMIC_LOAD_XOR_64: 1250 case ISD::ATOMIC_LOAD_NAND_64: 1251 case ISD::ATOMIC_LOAD_MIN_64: 1252 case ISD::ATOMIC_LOAD_MAX_64: 1253 case ISD::ATOMIC_LOAD_UMIN_64: 1254 case ISD::ATOMIC_LOAD_UMAX_64: 1255 case ISD::ATOMIC_SWAP_64: { 1256 unsigned int num_operands = 3; 1257 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1258 SDValue Ops[3]; 1259 for (unsigned int x = 0; x < num_operands; ++x) 1260 Ops[x] = LegalizeOp(Node->getOperand(x)); 1261 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1262 1263 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1264 default: assert(0 && "This action is not supported yet!"); 1265 case TargetLowering::Custom: 1266 Result = TLI.LowerOperation(Result, DAG); 1267 break; 1268 case TargetLowering::Legal: 1269 break; 1270 } 1271 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1272 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1273 return Result.getValue(Op.getResNo()); 1274 } 1275 case ISD::Constant: { 1276 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1277 unsigned opAction = 1278 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1279 1280 // We know we don't need to expand constants here, constants only have one 1281 // value and we check that it is fine above. 1282 1283 if (opAction == TargetLowering::Custom) { 1284 Tmp1 = TLI.LowerOperation(Result, DAG); 1285 if (Tmp1.getNode()) 1286 Result = Tmp1; 1287 } 1288 break; 1289 } 1290 case ISD::ConstantFP: { 1291 // Spill FP immediates to the constant pool if the target cannot directly 1292 // codegen them. Targets often have some immediate values that can be 1293 // efficiently generated into an FP register without a load. We explicitly 1294 // leave these constants as ConstantFP nodes for the target to deal with. 1295 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1296 1297 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1298 default: assert(0 && "This action is not supported yet!"); 1299 case TargetLowering::Legal: 1300 break; 1301 case TargetLowering::Custom: 1302 Tmp3 = TLI.LowerOperation(Result, DAG); 1303 if (Tmp3.getNode()) { 1304 Result = Tmp3; 1305 break; 1306 } 1307 // FALLTHROUGH 1308 case TargetLowering::Expand: { 1309 // Check to see if this FP immediate is already legal. 1310 bool isLegal = false; 1311 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1312 E = TLI.legal_fpimm_end(); I != E; ++I) { 1313 if (CFP->isExactlyValue(*I)) { 1314 isLegal = true; 1315 break; 1316 } 1317 } 1318 // If this is a legal constant, turn it into a TargetConstantFP node. 1319 if (isLegal) 1320 break; 1321 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1322 } 1323 } 1324 break; 1325 } 1326 case ISD::TokenFactor: 1327 if (Node->getNumOperands() == 2) { 1328 Tmp1 = LegalizeOp(Node->getOperand(0)); 1329 Tmp2 = LegalizeOp(Node->getOperand(1)); 1330 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1331 } else if (Node->getNumOperands() == 3) { 1332 Tmp1 = LegalizeOp(Node->getOperand(0)); 1333 Tmp2 = LegalizeOp(Node->getOperand(1)); 1334 Tmp3 = LegalizeOp(Node->getOperand(2)); 1335 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1336 } else { 1337 SmallVector<SDValue, 8> Ops; 1338 // Legalize the operands. 1339 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1340 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1341 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1342 } 1343 break; 1344 1345 case ISD::FORMAL_ARGUMENTS: 1346 case ISD::CALL: 1347 // The only option for this is to custom lower it. 1348 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1349 assert(Tmp3.getNode() && "Target didn't custom lower this node!"); 1350 // A call within a calling sequence must be legalized to something 1351 // other than the normal CALLSEQ_END. Violating this gets Legalize 1352 // into an infinite loop. 1353 assert ((!IsLegalizingCall || 1354 Node->getOpcode() != ISD::CALL || 1355 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) && 1356 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1357 1358 // The number of incoming and outgoing values should match; unless the final 1359 // outgoing value is a flag. 1360 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() || 1361 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 && 1362 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) == 1363 MVT::Flag)) && 1364 "Lowering call/formal_arguments produced unexpected # results!"); 1365 1366 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1367 // remember that we legalized all of them, so it doesn't get relegalized. 1368 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) { 1369 if (Tmp3.getNode()->getValueType(i) == MVT::Flag) 1370 continue; 1371 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1372 if (Op.getResNo() == i) 1373 Tmp2 = Tmp1; 1374 AddLegalizedOperand(SDValue(Node, i), Tmp1); 1375 } 1376 return Tmp2; 1377 case ISD::EXTRACT_SUBREG: { 1378 Tmp1 = LegalizeOp(Node->getOperand(0)); 1379 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1380 assert(idx && "Operand must be a constant"); 1381 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); 1382 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1383 } 1384 break; 1385 case ISD::INSERT_SUBREG: { 1386 Tmp1 = LegalizeOp(Node->getOperand(0)); 1387 Tmp2 = LegalizeOp(Node->getOperand(1)); 1388 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1389 assert(idx && "Operand must be a constant"); 1390 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); 1391 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1392 } 1393 break; 1394 case ISD::BUILD_VECTOR: 1395 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1396 default: assert(0 && "This action is not supported yet!"); 1397 case TargetLowering::Custom: 1398 Tmp3 = TLI.LowerOperation(Result, DAG); 1399 if (Tmp3.getNode()) { 1400 Result = Tmp3; 1401 break; 1402 } 1403 // FALLTHROUGH 1404 case TargetLowering::Expand: 1405 Result = ExpandBUILD_VECTOR(Result.getNode()); 1406 break; 1407 } 1408 break; 1409 case ISD::INSERT_VECTOR_ELT: 1410 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1411 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1412 1413 // The type of the value to insert may not be legal, even though the vector 1414 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1415 // here. 1416 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1417 default: assert(0 && "Cannot expand insert element operand"); 1418 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1419 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1420 } 1421 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1422 1423 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1424 Node->getValueType(0))) { 1425 default: assert(0 && "This action is not supported yet!"); 1426 case TargetLowering::Legal: 1427 break; 1428 case TargetLowering::Custom: 1429 Tmp4 = TLI.LowerOperation(Result, DAG); 1430 if (Tmp4.getNode()) { 1431 Result = Tmp4; 1432 break; 1433 } 1434 // FALLTHROUGH 1435 case TargetLowering::Expand: { 1436 // If the insert index is a constant, codegen this as a scalar_to_vector, 1437 // then a shuffle that inserts it into the right position in the vector. 1438 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1439 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1440 // match the element type of the vector being created. 1441 if (Tmp2.getValueType() == 1442 Op.getValueType().getVectorElementType()) { 1443 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1444 Tmp1.getValueType(), Tmp2); 1445 1446 unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); 1447 MVT ShufMaskVT = 1448 MVT::getIntVectorWithNumElements(NumElts); 1449 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType(); 1450 1451 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1452 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1453 // elt 0 of the RHS. 1454 SmallVector<SDValue, 8> ShufOps; 1455 for (unsigned i = 0; i != NumElts; ++i) { 1456 if (i != InsertPos->getZExtValue()) 1457 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1458 else 1459 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1460 } 1461 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1462 &ShufOps[0], ShufOps.size()); 1463 1464 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1465 Tmp1, ScVec, ShufMask); 1466 Result = LegalizeOp(Result); 1467 break; 1468 } 1469 } 1470 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3); 1471 break; 1472 } 1473 } 1474 break; 1475 case ISD::SCALAR_TO_VECTOR: 1476 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1477 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1478 break; 1479 } 1480 1481 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1482 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1483 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1484 Node->getValueType(0))) { 1485 default: assert(0 && "This action is not supported yet!"); 1486 case TargetLowering::Legal: 1487 break; 1488 case TargetLowering::Custom: 1489 Tmp3 = TLI.LowerOperation(Result, DAG); 1490 if (Tmp3.getNode()) { 1491 Result = Tmp3; 1492 break; 1493 } 1494 // FALLTHROUGH 1495 case TargetLowering::Expand: 1496 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1497 break; 1498 } 1499 break; 1500 case ISD::VECTOR_SHUFFLE: 1501 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1502 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1503 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1504 1505 // Allow targets to custom lower the SHUFFLEs they support. 1506 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1507 default: assert(0 && "Unknown operation action!"); 1508 case TargetLowering::Legal: 1509 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1510 "vector shuffle should not be created if not legal!"); 1511 break; 1512 case TargetLowering::Custom: 1513 Tmp3 = TLI.LowerOperation(Result, DAG); 1514 if (Tmp3.getNode()) { 1515 Result = Tmp3; 1516 break; 1517 } 1518 // FALLTHROUGH 1519 case TargetLowering::Expand: { 1520 MVT VT = Node->getValueType(0); 1521 MVT EltVT = VT.getVectorElementType(); 1522 MVT PtrVT = TLI.getPointerTy(); 1523 SDValue Mask = Node->getOperand(2); 1524 unsigned NumElems = Mask.getNumOperands(); 1525 SmallVector<SDValue,8> Ops; 1526 for (unsigned i = 0; i != NumElems; ++i) { 1527 SDValue Arg = Mask.getOperand(i); 1528 if (Arg.getOpcode() == ISD::UNDEF) { 1529 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1530 } else { 1531 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1532 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue(); 1533 if (Idx < NumElems) 1534 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1535 DAG.getConstant(Idx, PtrVT))); 1536 else 1537 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1538 DAG.getConstant(Idx - NumElems, PtrVT))); 1539 } 1540 } 1541 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1542 break; 1543 } 1544 case TargetLowering::Promote: { 1545 // Change base type to a different vector type. 1546 MVT OVT = Node->getValueType(0); 1547 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1548 1549 // Cast the two input vectors. 1550 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1551 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1552 1553 // Convert the shuffle mask to the right # elements. 1554 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1555 assert(Tmp3.getNode() && "Shuffle not legal?"); 1556 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1557 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1558 break; 1559 } 1560 } 1561 break; 1562 1563 case ISD::EXTRACT_VECTOR_ELT: 1564 Tmp1 = Node->getOperand(0); 1565 Tmp2 = LegalizeOp(Node->getOperand(1)); 1566 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1567 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1568 break; 1569 1570 case ISD::EXTRACT_SUBVECTOR: 1571 Tmp1 = Node->getOperand(0); 1572 Tmp2 = LegalizeOp(Node->getOperand(1)); 1573 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1574 Result = ExpandEXTRACT_SUBVECTOR(Result); 1575 break; 1576 1577 case ISD::CALLSEQ_START: { 1578 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1579 1580 // Recursively Legalize all of the inputs of the call end that do not lead 1581 // to this call start. This ensures that any libcalls that need be inserted 1582 // are inserted *before* the CALLSEQ_START. 1583 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1584 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1585 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1586 NodesLeadingTo); 1587 } 1588 1589 // Now that we legalized all of the inputs (which may have inserted 1590 // libcalls) create the new CALLSEQ_START node. 1591 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1592 1593 // Merge in the last call, to ensure that this call start after the last 1594 // call ended. 1595 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1596 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1597 Tmp1 = LegalizeOp(Tmp1); 1598 } 1599 1600 // Do not try to legalize the target-specific arguments (#1+). 1601 if (Tmp1 != Node->getOperand(0)) { 1602 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1603 Ops[0] = Tmp1; 1604 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1605 } 1606 1607 // Remember that the CALLSEQ_START is legalized. 1608 AddLegalizedOperand(Op.getValue(0), Result); 1609 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1610 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1611 1612 // Now that the callseq_start and all of the non-call nodes above this call 1613 // sequence have been legalized, legalize the call itself. During this 1614 // process, no libcalls can/will be inserted, guaranteeing that no calls 1615 // can overlap. 1616 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1617 // Note that we are selecting this call! 1618 LastCALLSEQ_END = SDValue(CallEnd, 0); 1619 IsLegalizingCall = true; 1620 1621 // Legalize the call, starting from the CALLSEQ_END. 1622 LegalizeOp(LastCALLSEQ_END); 1623 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1624 return Result; 1625 } 1626 case ISD::CALLSEQ_END: 1627 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1628 // will cause this node to be legalized as well as handling libcalls right. 1629 if (LastCALLSEQ_END.getNode() != Node) { 1630 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1631 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1632 assert(I != LegalizedNodes.end() && 1633 "Legalizing the call start should have legalized this node!"); 1634 return I->second; 1635 } 1636 1637 // Otherwise, the call start has been legalized and everything is going 1638 // according to plan. Just legalize ourselves normally here. 1639 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1640 // Do not try to legalize the target-specific arguments (#1+), except for 1641 // an optional flag input. 1642 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1643 if (Tmp1 != Node->getOperand(0)) { 1644 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1645 Ops[0] = Tmp1; 1646 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1647 } 1648 } else { 1649 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1650 if (Tmp1 != Node->getOperand(0) || 1651 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1652 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1653 Ops[0] = Tmp1; 1654 Ops.back() = Tmp2; 1655 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1656 } 1657 } 1658 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1659 // This finishes up call legalization. 1660 IsLegalizingCall = false; 1661 1662 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1663 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1664 if (Node->getNumValues() == 2) 1665 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1666 return Result.getValue(Op.getResNo()); 1667 case ISD::DYNAMIC_STACKALLOC: { 1668 MVT VT = Node->getValueType(0); 1669 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1670 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1671 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1672 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1673 1674 Tmp1 = Result.getValue(0); 1675 Tmp2 = Result.getValue(1); 1676 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1677 default: assert(0 && "This action is not supported yet!"); 1678 case TargetLowering::Expand: { 1679 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1680 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1681 " not tell us which reg is the stack pointer!"); 1682 SDValue Chain = Tmp1.getOperand(0); 1683 1684 // Chain the dynamic stack allocation so that it doesn't modify the stack 1685 // pointer when other instructions are using the stack. 1686 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1687 1688 SDValue Size = Tmp2.getOperand(1); 1689 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1690 Chain = SP.getValue(1); 1691 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1692 unsigned StackAlign = 1693 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1694 if (Align > StackAlign) 1695 SP = DAG.getNode(ISD::AND, VT, SP, 1696 DAG.getConstant(-(uint64_t)Align, VT)); 1697 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1698 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1699 1700 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1701 DAG.getIntPtrConstant(0, true), SDValue()); 1702 1703 Tmp1 = LegalizeOp(Tmp1); 1704 Tmp2 = LegalizeOp(Tmp2); 1705 break; 1706 } 1707 case TargetLowering::Custom: 1708 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1709 if (Tmp3.getNode()) { 1710 Tmp1 = LegalizeOp(Tmp3); 1711 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1712 } 1713 break; 1714 case TargetLowering::Legal: 1715 break; 1716 } 1717 // Since this op produce two values, make sure to remember that we 1718 // legalized both of them. 1719 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1720 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1721 return Op.getResNo() ? Tmp2 : Tmp1; 1722 } 1723 case ISD::INLINEASM: { 1724 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1725 bool Changed = false; 1726 // Legalize all of the operands of the inline asm, in case they are nodes 1727 // that need to be expanded or something. Note we skip the asm string and 1728 // all of the TargetConstant flags. 1729 SDValue Op = LegalizeOp(Ops[0]); 1730 Changed = Op != Ops[0]; 1731 Ops[0] = Op; 1732 1733 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1734 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1735 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3; 1736 for (++i; NumVals; ++i, --NumVals) { 1737 SDValue Op = LegalizeOp(Ops[i]); 1738 if (Op != Ops[i]) { 1739 Changed = true; 1740 Ops[i] = Op; 1741 } 1742 } 1743 } 1744 1745 if (HasInFlag) { 1746 Op = LegalizeOp(Ops.back()); 1747 Changed |= Op != Ops.back(); 1748 Ops.back() = Op; 1749 } 1750 1751 if (Changed) 1752 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1753 1754 // INLINE asm returns a chain and flag, make sure to add both to the map. 1755 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1756 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1757 return Result.getValue(Op.getResNo()); 1758 } 1759 case ISD::BR: 1760 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1761 // Ensure that libcalls are emitted before a branch. 1762 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1763 Tmp1 = LegalizeOp(Tmp1); 1764 LastCALLSEQ_END = DAG.getEntryNode(); 1765 1766 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1767 break; 1768 case ISD::BRIND: 1769 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1770 // Ensure that libcalls are emitted before a branch. 1771 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1772 Tmp1 = LegalizeOp(Tmp1); 1773 LastCALLSEQ_END = DAG.getEntryNode(); 1774 1775 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1776 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1777 case Legal: 1778 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1779 break; 1780 } 1781 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1782 break; 1783 case ISD::BR_JT: 1784 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1785 // Ensure that libcalls are emitted before a branch. 1786 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1787 Tmp1 = LegalizeOp(Tmp1); 1788 LastCALLSEQ_END = DAG.getEntryNode(); 1789 1790 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1791 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1792 1793 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1794 default: assert(0 && "This action is not supported yet!"); 1795 case TargetLowering::Legal: break; 1796 case TargetLowering::Custom: 1797 Tmp1 = TLI.LowerOperation(Result, DAG); 1798 if (Tmp1.getNode()) Result = Tmp1; 1799 break; 1800 case TargetLowering::Expand: { 1801 SDValue Chain = Result.getOperand(0); 1802 SDValue Table = Result.getOperand(1); 1803 SDValue Index = Result.getOperand(2); 1804 1805 MVT PTy = TLI.getPointerTy(); 1806 MachineFunction &MF = DAG.getMachineFunction(); 1807 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1808 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1809 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1810 1811 SDValue LD; 1812 switch (EntrySize) { 1813 default: assert(0 && "Size of jump table not supported yet."); break; 1814 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, 1815 PseudoSourceValue::getJumpTable(), 0); break; 1816 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, 1817 PseudoSourceValue::getJumpTable(), 0); break; 1818 } 1819 1820 Addr = LD; 1821 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1822 // For PIC, the sequence is: 1823 // BRIND(load(Jumptable + index) + RelocBase) 1824 // RelocBase can be JumpTable, GOT or some sort of global base. 1825 if (PTy != MVT::i32) 1826 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1827 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1828 TLI.getPICJumpTableRelocBase(Table, DAG)); 1829 } 1830 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1831 } 1832 } 1833 break; 1834 case ISD::BRCOND: 1835 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1836 // Ensure that libcalls are emitted before a return. 1837 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1838 Tmp1 = LegalizeOp(Tmp1); 1839 LastCALLSEQ_END = DAG.getEntryNode(); 1840 1841 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1842 case Expand: assert(0 && "It's impossible to expand bools"); 1843 case Legal: 1844 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1845 break; 1846 case Promote: { 1847 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1848 1849 // The top bits of the promoted condition are not necessarily zero, ensure 1850 // that the value is properly zero extended. 1851 unsigned BitWidth = Tmp2.getValueSizeInBits(); 1852 if (!DAG.MaskedValueIsZero(Tmp2, 1853 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 1854 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1855 break; 1856 } 1857 } 1858 1859 // Basic block destination (Op#2) is always legal. 1860 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1861 1862 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1863 default: assert(0 && "This action is not supported yet!"); 1864 case TargetLowering::Legal: break; 1865 case TargetLowering::Custom: 1866 Tmp1 = TLI.LowerOperation(Result, DAG); 1867 if (Tmp1.getNode()) Result = Tmp1; 1868 break; 1869 case TargetLowering::Expand: 1870 // Expand brcond's setcc into its constituent parts and create a BR_CC 1871 // Node. 1872 if (Tmp2.getOpcode() == ISD::SETCC) { 1873 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1874 Tmp2.getOperand(0), Tmp2.getOperand(1), 1875 Node->getOperand(2)); 1876 } else { 1877 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1878 DAG.getCondCode(ISD::SETNE), Tmp2, 1879 DAG.getConstant(0, Tmp2.getValueType()), 1880 Node->getOperand(2)); 1881 } 1882 break; 1883 } 1884 break; 1885 case ISD::BR_CC: 1886 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1887 // Ensure that libcalls are emitted before a branch. 1888 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1889 Tmp1 = LegalizeOp(Tmp1); 1890 Tmp2 = Node->getOperand(2); // LHS 1891 Tmp3 = Node->getOperand(3); // RHS 1892 Tmp4 = Node->getOperand(1); // CC 1893 1894 LegalizeSetCC(Node->getValueType(0), Tmp2, Tmp3, Tmp4); 1895 LastCALLSEQ_END = DAG.getEntryNode(); 1896 1897 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 1898 // the LHS is a legal SETCC itself. In this case, we need to compare 1899 // the result against zero to select between true and false values. 1900 if (Tmp3.getNode() == 0) { 1901 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1902 Tmp4 = DAG.getCondCode(ISD::SETNE); 1903 } 1904 1905 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1906 Node->getOperand(4)); 1907 1908 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1909 default: assert(0 && "Unexpected action for BR_CC!"); 1910 case TargetLowering::Legal: break; 1911 case TargetLowering::Custom: 1912 Tmp4 = TLI.LowerOperation(Result, DAG); 1913 if (Tmp4.getNode()) Result = Tmp4; 1914 break; 1915 } 1916 break; 1917 case ISD::LOAD: { 1918 LoadSDNode *LD = cast<LoadSDNode>(Node); 1919 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1920 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1921 1922 ISD::LoadExtType ExtType = LD->getExtensionType(); 1923 if (ExtType == ISD::NON_EXTLOAD) { 1924 MVT VT = Node->getValueType(0); 1925 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1926 Tmp3 = Result.getValue(0); 1927 Tmp4 = Result.getValue(1); 1928 1929 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1930 default: assert(0 && "This action is not supported yet!"); 1931 case TargetLowering::Legal: 1932 // If this is an unaligned load and the target doesn't support it, 1933 // expand it. 1934 if (!TLI.allowsUnalignedMemoryAccesses()) { 1935 unsigned ABIAlignment = TLI.getTargetData()-> 1936 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 1937 if (LD->getAlignment() < ABIAlignment){ 1938 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 1939 TLI); 1940 Tmp3 = Result.getOperand(0); 1941 Tmp4 = Result.getOperand(1); 1942 Tmp3 = LegalizeOp(Tmp3); 1943 Tmp4 = LegalizeOp(Tmp4); 1944 } 1945 } 1946 break; 1947 case TargetLowering::Custom: 1948 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1949 if (Tmp1.getNode()) { 1950 Tmp3 = LegalizeOp(Tmp1); 1951 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1952 } 1953 break; 1954 case TargetLowering::Promote: { 1955 // Only promote a load of vector type to another. 1956 assert(VT.isVector() && "Cannot promote this load!"); 1957 // Change base type to a different vector type. 1958 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1959 1960 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1961 LD->getSrcValueOffset(), 1962 LD->isVolatile(), LD->getAlignment()); 1963 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1964 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1965 break; 1966 } 1967 } 1968 // Since loads produce two values, make sure to remember that we 1969 // legalized both of them. 1970 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1971 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1972 return Op.getResNo() ? Tmp4 : Tmp3; 1973 } else { 1974 MVT SrcVT = LD->getMemoryVT(); 1975 unsigned SrcWidth = SrcVT.getSizeInBits(); 1976 int SVOffset = LD->getSrcValueOffset(); 1977 unsigned Alignment = LD->getAlignment(); 1978 bool isVolatile = LD->isVolatile(); 1979 1980 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1981 // Some targets pretend to have an i1 loading operation, and actually 1982 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1983 // bits are guaranteed to be zero; it helps the optimizers understand 1984 // that these bits are zero. It is also useful for EXTLOAD, since it 1985 // tells the optimizers that those bits are undefined. It would be 1986 // nice to have an effective generic way of getting these benefits... 1987 // Until such a way is found, don't insist on promoting i1 here. 1988 (SrcVT != MVT::i1 || 1989 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1990 // Promote to a byte-sized load if not loading an integral number of 1991 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1992 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1993 MVT NVT = MVT::getIntegerVT(NewWidth); 1994 SDValue Ch; 1995 1996 // The extra bits are guaranteed to be zero, since we stored them that 1997 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1998 1999 ISD::LoadExtType NewExtType = 2000 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 2001 2002 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), 2003 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 2004 NVT, isVolatile, Alignment); 2005 2006 Ch = Result.getValue(1); // The chain. 2007 2008 if (ExtType == ISD::SEXTLOAD) 2009 // Having the top bits zero doesn't help when sign extending. 2010 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2011 Result, DAG.getValueType(SrcVT)); 2012 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 2013 // All the top bits are guaranteed to be zero - inform the optimizers. 2014 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, 2015 DAG.getValueType(SrcVT)); 2016 2017 Tmp1 = LegalizeOp(Result); 2018 Tmp2 = LegalizeOp(Ch); 2019 } else if (SrcWidth & (SrcWidth - 1)) { 2020 // If not loading a power-of-2 number of bits, expand as two loads. 2021 assert(SrcVT.isExtended() && !SrcVT.isVector() && 2022 "Unsupported extload!"); 2023 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 2024 assert(RoundWidth < SrcWidth); 2025 unsigned ExtraWidth = SrcWidth - RoundWidth; 2026 assert(ExtraWidth < RoundWidth); 2027 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2028 "Load size not an integral number of bytes!"); 2029 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2030 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2031 SDValue Lo, Hi, Ch; 2032 unsigned IncrementSize; 2033 2034 if (TLI.isLittleEndian()) { 2035 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2036 // Load the bottom RoundWidth bits. 2037 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2038 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2039 Alignment); 2040 2041 // Load the remaining ExtraWidth bits. 2042 IncrementSize = RoundWidth / 8; 2043 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2044 DAG.getIntPtrConstant(IncrementSize)); 2045 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2046 LD->getSrcValue(), SVOffset + IncrementSize, 2047 ExtraVT, isVolatile, 2048 MinAlign(Alignment, IncrementSize)); 2049 2050 // Build a factor node to remember that this load is independent of the 2051 // other one. 2052 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2053 Hi.getValue(1)); 2054 2055 // Move the top bits to the right place. 2056 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2057 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2058 2059 // Join the hi and lo parts. 2060 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2061 } else { 2062 // Big endian - avoid unaligned loads. 2063 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2064 // Load the top RoundWidth bits. 2065 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2066 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2067 Alignment); 2068 2069 // Load the remaining ExtraWidth bits. 2070 IncrementSize = RoundWidth / 8; 2071 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2072 DAG.getIntPtrConstant(IncrementSize)); 2073 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2074 LD->getSrcValue(), SVOffset + IncrementSize, 2075 ExtraVT, isVolatile, 2076 MinAlign(Alignment, IncrementSize)); 2077 2078 // Build a factor node to remember that this load is independent of the 2079 // other one. 2080 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2081 Hi.getValue(1)); 2082 2083 // Move the top bits to the right place. 2084 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2085 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2086 2087 // Join the hi and lo parts. 2088 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2089 } 2090 2091 Tmp1 = LegalizeOp(Result); 2092 Tmp2 = LegalizeOp(Ch); 2093 } else { 2094 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 2095 default: assert(0 && "This action is not supported yet!"); 2096 case TargetLowering::Custom: 2097 isCustom = true; 2098 // FALLTHROUGH 2099 case TargetLowering::Legal: 2100 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2101 Tmp1 = Result.getValue(0); 2102 Tmp2 = Result.getValue(1); 2103 2104 if (isCustom) { 2105 Tmp3 = TLI.LowerOperation(Result, DAG); 2106 if (Tmp3.getNode()) { 2107 Tmp1 = LegalizeOp(Tmp3); 2108 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2109 } 2110 } else { 2111 // If this is an unaligned load and the target doesn't support it, 2112 // expand it. 2113 if (!TLI.allowsUnalignedMemoryAccesses()) { 2114 unsigned ABIAlignment = TLI.getTargetData()-> 2115 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2116 if (LD->getAlignment() < ABIAlignment){ 2117 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 2118 TLI); 2119 Tmp1 = Result.getOperand(0); 2120 Tmp2 = Result.getOperand(1); 2121 Tmp1 = LegalizeOp(Tmp1); 2122 Tmp2 = LegalizeOp(Tmp2); 2123 } 2124 } 2125 } 2126 break; 2127 case TargetLowering::Expand: 2128 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2129 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2130 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 2131 LD->getSrcValueOffset(), 2132 LD->isVolatile(), LD->getAlignment()); 2133 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 2134 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2135 Tmp2 = LegalizeOp(Load.getValue(1)); 2136 break; 2137 } 2138 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2139 // Turn the unsupported load into an EXTLOAD followed by an explicit 2140 // zero/sign extend inreg. 2141 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2142 Tmp1, Tmp2, LD->getSrcValue(), 2143 LD->getSrcValueOffset(), SrcVT, 2144 LD->isVolatile(), LD->getAlignment()); 2145 SDValue ValRes; 2146 if (ExtType == ISD::SEXTLOAD) 2147 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2148 Result, DAG.getValueType(SrcVT)); 2149 else 2150 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 2151 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2152 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2153 break; 2154 } 2155 } 2156 2157 // Since loads produce two values, make sure to remember that we legalized 2158 // both of them. 2159 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2160 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2161 return Op.getResNo() ? Tmp2 : Tmp1; 2162 } 2163 } 2164 case ISD::EXTRACT_ELEMENT: { 2165 MVT OpTy = Node->getOperand(0).getValueType(); 2166 switch (getTypeAction(OpTy)) { 2167 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2168 case Legal: 2169 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2170 // 1 -> Hi 2171 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 2172 DAG.getConstant(OpTy.getSizeInBits()/2, 2173 TLI.getShiftAmountTy())); 2174 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 2175 } else { 2176 // 0 -> Lo 2177 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 2178 Node->getOperand(0)); 2179 } 2180 break; 2181 case Expand: 2182 // Get both the low and high parts. 2183 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2184 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) 2185 Result = Tmp2; // 1 -> Hi 2186 else 2187 Result = Tmp1; // 0 -> Lo 2188 break; 2189 } 2190 break; 2191 } 2192 2193 case ISD::CopyToReg: 2194 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2195 2196 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2197 "Register type must be legal!"); 2198 // Legalize the incoming value (must be a legal type). 2199 Tmp2 = LegalizeOp(Node->getOperand(2)); 2200 if (Node->getNumValues() == 1) { 2201 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2202 } else { 2203 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2204 if (Node->getNumOperands() == 4) { 2205 Tmp3 = LegalizeOp(Node->getOperand(3)); 2206 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2207 Tmp3); 2208 } else { 2209 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2210 } 2211 2212 // Since this produces two values, make sure to remember that we legalized 2213 // both of them. 2214 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 2215 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 2216 return Result; 2217 } 2218 break; 2219 2220 case ISD::RET: 2221 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2222 2223 // Ensure that libcalls are emitted before a return. 2224 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2225 Tmp1 = LegalizeOp(Tmp1); 2226 LastCALLSEQ_END = DAG.getEntryNode(); 2227 2228 switch (Node->getNumOperands()) { 2229 case 3: // ret val 2230 Tmp2 = Node->getOperand(1); 2231 Tmp3 = Node->getOperand(2); // Signness 2232 switch (getTypeAction(Tmp2.getValueType())) { 2233 case Legal: 2234 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2235 break; 2236 case Expand: 2237 if (!Tmp2.getValueType().isVector()) { 2238 SDValue Lo, Hi; 2239 ExpandOp(Tmp2, Lo, Hi); 2240 2241 // Big endian systems want the hi reg first. 2242 if (TLI.isBigEndian()) 2243 std::swap(Lo, Hi); 2244 2245 if (Hi.getNode()) 2246 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2247 else 2248 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 2249 Result = LegalizeOp(Result); 2250 } else { 2251 SDNode *InVal = Tmp2.getNode(); 2252 int InIx = Tmp2.getResNo(); 2253 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 2254 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 2255 2256 // Figure out if there is a simple type corresponding to this Vector 2257 // type. If so, convert to the vector type. 2258 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2259 if (TLI.isTypeLegal(TVT)) { 2260 // Turn this into a return of the vector type. 2261 Tmp2 = LegalizeOp(Tmp2); 2262 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2263 } else if (NumElems == 1) { 2264 // Turn this into a return of the scalar type. 2265 Tmp2 = ScalarizeVectorOp(Tmp2); 2266 Tmp2 = LegalizeOp(Tmp2); 2267 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2268 2269 // FIXME: Returns of gcc generic vectors smaller than a legal type 2270 // should be returned in integer registers! 2271 2272 // The scalarized value type may not be legal, e.g. it might require 2273 // promotion or expansion. Relegalize the return. 2274 Result = LegalizeOp(Result); 2275 } else { 2276 // FIXME: Returns of gcc generic vectors larger than a legal vector 2277 // type should be returned by reference! 2278 SDValue Lo, Hi; 2279 SplitVectorOp(Tmp2, Lo, Hi); 2280 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2281 Result = LegalizeOp(Result); 2282 } 2283 } 2284 break; 2285 case Promote: 2286 Tmp2 = PromoteOp(Node->getOperand(1)); 2287 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2288 Result = LegalizeOp(Result); 2289 break; 2290 } 2291 break; 2292 case 1: // ret void 2293 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2294 break; 2295 default: { // ret <values> 2296 SmallVector<SDValue, 8> NewValues; 2297 NewValues.push_back(Tmp1); 2298 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2299 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2300 case Legal: 2301 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2302 NewValues.push_back(Node->getOperand(i+1)); 2303 break; 2304 case Expand: { 2305 SDValue Lo, Hi; 2306 assert(!Node->getOperand(i).getValueType().isExtended() && 2307 "FIXME: TODO: implement returning non-legal vector types!"); 2308 ExpandOp(Node->getOperand(i), Lo, Hi); 2309 NewValues.push_back(Lo); 2310 NewValues.push_back(Node->getOperand(i+1)); 2311 if (Hi.getNode()) { 2312 NewValues.push_back(Hi); 2313 NewValues.push_back(Node->getOperand(i+1)); 2314 } 2315 break; 2316 } 2317 case Promote: 2318 assert(0 && "Can't promote multiple return value yet!"); 2319 } 2320 2321 if (NewValues.size() == Node->getNumOperands()) 2322 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2323 else 2324 Result = DAG.getNode(ISD::RET, MVT::Other, 2325 &NewValues[0], NewValues.size()); 2326 break; 2327 } 2328 } 2329 2330 if (Result.getOpcode() == ISD::RET) { 2331 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2332 default: assert(0 && "This action is not supported yet!"); 2333 case TargetLowering::Legal: break; 2334 case TargetLowering::Custom: 2335 Tmp1 = TLI.LowerOperation(Result, DAG); 2336 if (Tmp1.getNode()) Result = Tmp1; 2337 break; 2338 } 2339 } 2340 break; 2341 case ISD::STORE: { 2342 StoreSDNode *ST = cast<StoreSDNode>(Node); 2343 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2344 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2345 int SVOffset = ST->getSrcValueOffset(); 2346 unsigned Alignment = ST->getAlignment(); 2347 bool isVolatile = ST->isVolatile(); 2348 2349 if (!ST->isTruncatingStore()) { 2350 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2351 // FIXME: We shouldn't do this for TargetConstantFP's. 2352 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2353 // to phase ordering between legalized code and the dag combiner. This 2354 // probably means that we need to integrate dag combiner and legalizer 2355 // together. 2356 // We generally can't do this one for long doubles. 2357 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2358 if (CFP->getValueType(0) == MVT::f32 && 2359 getTypeAction(MVT::i32) == Legal) { 2360 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2361 bitcastToAPInt().zextOrTrunc(32), 2362 MVT::i32); 2363 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2364 SVOffset, isVolatile, Alignment); 2365 break; 2366 } else if (CFP->getValueType(0) == MVT::f64) { 2367 // If this target supports 64-bit registers, do a single 64-bit store. 2368 if (getTypeAction(MVT::i64) == Legal) { 2369 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 2370 zextOrTrunc(64), MVT::i64); 2371 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2372 SVOffset, isVolatile, Alignment); 2373 break; 2374 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 2375 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2376 // stores. If the target supports neither 32- nor 64-bits, this 2377 // xform is certainly not worth it. 2378 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 2379 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2380 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2381 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2382 2383 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2384 SVOffset, isVolatile, Alignment); 2385 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2386 DAG.getIntPtrConstant(4)); 2387 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2388 isVolatile, MinAlign(Alignment, 4U)); 2389 2390 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2391 break; 2392 } 2393 } 2394 } 2395 2396 switch (getTypeAction(ST->getMemoryVT())) { 2397 case Legal: { 2398 Tmp3 = LegalizeOp(ST->getValue()); 2399 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2400 ST->getOffset()); 2401 2402 MVT VT = Tmp3.getValueType(); 2403 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2404 default: assert(0 && "This action is not supported yet!"); 2405 case TargetLowering::Legal: 2406 // If this is an unaligned store and the target doesn't support it, 2407 // expand it. 2408 if (!TLI.allowsUnalignedMemoryAccesses()) { 2409 unsigned ABIAlignment = TLI.getTargetData()-> 2410 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2411 if (ST->getAlignment() < ABIAlignment) 2412 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 2413 TLI); 2414 } 2415 break; 2416 case TargetLowering::Custom: 2417 Tmp1 = TLI.LowerOperation(Result, DAG); 2418 if (Tmp1.getNode()) Result = Tmp1; 2419 break; 2420 case TargetLowering::Promote: 2421 assert(VT.isVector() && "Unknown legal promote case!"); 2422 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2423 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2424 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2425 ST->getSrcValue(), SVOffset, isVolatile, 2426 Alignment); 2427 break; 2428 } 2429 break; 2430 } 2431 case Promote: 2432 // Truncate the value and store the result. 2433 Tmp3 = PromoteOp(ST->getValue()); 2434 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2435 SVOffset, ST->getMemoryVT(), 2436 isVolatile, Alignment); 2437 break; 2438 2439 case Expand: 2440 unsigned IncrementSize = 0; 2441 SDValue Lo, Hi; 2442 2443 // If this is a vector type, then we have to calculate the increment as 2444 // the product of the element size in bytes, and the number of elements 2445 // in the high half of the vector. 2446 if (ST->getValue().getValueType().isVector()) { 2447 SDNode *InVal = ST->getValue().getNode(); 2448 int InIx = ST->getValue().getResNo(); 2449 MVT InVT = InVal->getValueType(InIx); 2450 unsigned NumElems = InVT.getVectorNumElements(); 2451 MVT EVT = InVT.getVectorElementType(); 2452 2453 // Figure out if there is a simple type corresponding to this Vector 2454 // type. If so, convert to the vector type. 2455 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2456 if (TLI.isTypeLegal(TVT)) { 2457 // Turn this into a normal store of the vector type. 2458 Tmp3 = LegalizeOp(ST->getValue()); 2459 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2460 SVOffset, isVolatile, Alignment); 2461 Result = LegalizeOp(Result); 2462 break; 2463 } else if (NumElems == 1) { 2464 // Turn this into a normal store of the scalar type. 2465 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2466 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2467 SVOffset, isVolatile, Alignment); 2468 // The scalarized value type may not be legal, e.g. it might require 2469 // promotion or expansion. Relegalize the scalar store. 2470 Result = LegalizeOp(Result); 2471 break; 2472 } else { 2473 SplitVectorOp(ST->getValue(), Lo, Hi); 2474 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() * 2475 EVT.getSizeInBits()/8; 2476 } 2477 } else { 2478 ExpandOp(ST->getValue(), Lo, Hi); 2479 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0; 2480 2481 if (Hi.getNode() && TLI.isBigEndian()) 2482 std::swap(Lo, Hi); 2483 } 2484 2485 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2486 SVOffset, isVolatile, Alignment); 2487 2488 if (Hi.getNode() == NULL) { 2489 // Must be int <-> float one-to-one expansion. 2490 Result = Lo; 2491 break; 2492 } 2493 2494 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2495 DAG.getIntPtrConstant(IncrementSize)); 2496 assert(isTypeLegal(Tmp2.getValueType()) && 2497 "Pointers must be legal!"); 2498 SVOffset += IncrementSize; 2499 Alignment = MinAlign(Alignment, IncrementSize); 2500 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2501 SVOffset, isVolatile, Alignment); 2502 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2503 break; 2504 } 2505 } else { 2506 switch (getTypeAction(ST->getValue().getValueType())) { 2507 case Legal: 2508 Tmp3 = LegalizeOp(ST->getValue()); 2509 break; 2510 case Promote: 2511 // We can promote the value, the truncstore will still take care of it. 2512 Tmp3 = PromoteOp(ST->getValue()); 2513 break; 2514 case Expand: 2515 // Just store the low part. This may become a non-trunc store, so make 2516 // sure to use getTruncStore, not UpdateNodeOperands below. 2517 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2518 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2519 SVOffset, MVT::i8, isVolatile, Alignment); 2520 } 2521 2522 MVT StVT = ST->getMemoryVT(); 2523 unsigned StWidth = StVT.getSizeInBits(); 2524 2525 if (StWidth != StVT.getStoreSizeInBits()) { 2526 // Promote to a byte-sized store with upper bits zero if not 2527 // storing an integral number of bytes. For example, promote 2528 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2529 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 2530 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); 2531 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2532 SVOffset, NVT, isVolatile, Alignment); 2533 } else if (StWidth & (StWidth - 1)) { 2534 // If not storing a power-of-2 number of bits, expand as two stores. 2535 assert(StVT.isExtended() && !StVT.isVector() && 2536 "Unsupported truncstore!"); 2537 unsigned RoundWidth = 1 << Log2_32(StWidth); 2538 assert(RoundWidth < StWidth); 2539 unsigned ExtraWidth = StWidth - RoundWidth; 2540 assert(ExtraWidth < RoundWidth); 2541 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2542 "Store size not an integral number of bytes!"); 2543 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2544 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2545 SDValue Lo, Hi; 2546 unsigned IncrementSize; 2547 2548 if (TLI.isLittleEndian()) { 2549 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2550 // Store the bottom RoundWidth bits. 2551 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2552 SVOffset, RoundVT, 2553 isVolatile, Alignment); 2554 2555 // Store the remaining ExtraWidth bits. 2556 IncrementSize = RoundWidth / 8; 2557 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2558 DAG.getIntPtrConstant(IncrementSize)); 2559 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2560 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2561 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2562 SVOffset + IncrementSize, ExtraVT, isVolatile, 2563 MinAlign(Alignment, IncrementSize)); 2564 } else { 2565 // Big endian - avoid unaligned stores. 2566 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2567 // Store the top RoundWidth bits. 2568 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2569 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2570 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, 2571 RoundVT, isVolatile, Alignment); 2572 2573 // Store the remaining ExtraWidth bits. 2574 IncrementSize = RoundWidth / 8; 2575 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2576 DAG.getIntPtrConstant(IncrementSize)); 2577 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2578 SVOffset + IncrementSize, ExtraVT, isVolatile, 2579 MinAlign(Alignment, IncrementSize)); 2580 } 2581 2582 // The order of the stores doesn't matter. 2583 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2584 } else { 2585 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2586 Tmp2 != ST->getBasePtr()) 2587 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2588 ST->getOffset()); 2589 2590 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2591 default: assert(0 && "This action is not supported yet!"); 2592 case TargetLowering::Legal: 2593 // If this is an unaligned store and the target doesn't support it, 2594 // expand it. 2595 if (!TLI.allowsUnalignedMemoryAccesses()) { 2596 unsigned ABIAlignment = TLI.getTargetData()-> 2597 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2598 if (ST->getAlignment() < ABIAlignment) 2599 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 2600 TLI); 2601 } 2602 break; 2603 case TargetLowering::Custom: 2604 Result = TLI.LowerOperation(Result, DAG); 2605 break; 2606 case Expand: 2607 // TRUNCSTORE:i16 i32 -> STORE i16 2608 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2609 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); 2610 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, 2611 isVolatile, Alignment); 2612 break; 2613 } 2614 } 2615 } 2616 break; 2617 } 2618 case ISD::PCMARKER: 2619 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2620 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2621 break; 2622 case ISD::STACKSAVE: 2623 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2624 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2625 Tmp1 = Result.getValue(0); 2626 Tmp2 = Result.getValue(1); 2627 2628 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2629 default: assert(0 && "This action is not supported yet!"); 2630 case TargetLowering::Legal: break; 2631 case TargetLowering::Custom: 2632 Tmp3 = TLI.LowerOperation(Result, DAG); 2633 if (Tmp3.getNode()) { 2634 Tmp1 = LegalizeOp(Tmp3); 2635 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2636 } 2637 break; 2638 case TargetLowering::Expand: 2639 // Expand to CopyFromReg if the target set 2640 // StackPointerRegisterToSaveRestore. 2641 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2642 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2643 Node->getValueType(0)); 2644 Tmp2 = Tmp1.getValue(1); 2645 } else { 2646 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2647 Tmp2 = Node->getOperand(0); 2648 } 2649 break; 2650 } 2651 2652 // Since stacksave produce two values, make sure to remember that we 2653 // legalized both of them. 2654 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2655 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2656 return Op.getResNo() ? Tmp2 : Tmp1; 2657 2658 case ISD::STACKRESTORE: 2659 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2660 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2661 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2662 2663 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2664 default: assert(0 && "This action is not supported yet!"); 2665 case TargetLowering::Legal: break; 2666 case TargetLowering::Custom: 2667 Tmp1 = TLI.LowerOperation(Result, DAG); 2668 if (Tmp1.getNode()) Result = Tmp1; 2669 break; 2670 case TargetLowering::Expand: 2671 // Expand to CopyToReg if the target set 2672 // StackPointerRegisterToSaveRestore. 2673 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2674 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2675 } else { 2676 Result = Tmp1; 2677 } 2678 break; 2679 } 2680 break; 2681 2682 case ISD::READCYCLECOUNTER: 2683 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2684 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2685 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2686 Node->getValueType(0))) { 2687 default: assert(0 && "This action is not supported yet!"); 2688 case TargetLowering::Legal: 2689 Tmp1 = Result.getValue(0); 2690 Tmp2 = Result.getValue(1); 2691 break; 2692 case TargetLowering::Custom: 2693 Result = TLI.LowerOperation(Result, DAG); 2694 Tmp1 = LegalizeOp(Result.getValue(0)); 2695 Tmp2 = LegalizeOp(Result.getValue(1)); 2696 break; 2697 } 2698 2699 // Since rdcc produce two values, make sure to remember that we legalized 2700 // both of them. 2701 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2702 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2703 return Result; 2704 2705 case ISD::SELECT: 2706 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2707 case Expand: assert(0 && "It's impossible to expand bools"); 2708 case Legal: 2709 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2710 break; 2711 case Promote: { 2712 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2713 // Make sure the condition is either zero or one. 2714 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2715 if (!DAG.MaskedValueIsZero(Tmp1, 2716 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2717 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2718 break; 2719 } 2720 } 2721 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2722 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2723 2724 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2725 2726 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2727 default: assert(0 && "This action is not supported yet!"); 2728 case TargetLowering::Legal: break; 2729 case TargetLowering::Custom: { 2730 Tmp1 = TLI.LowerOperation(Result, DAG); 2731 if (Tmp1.getNode()) Result = Tmp1; 2732 break; 2733 } 2734 case TargetLowering::Expand: 2735 if (Tmp1.getOpcode() == ISD::SETCC) { 2736 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2737 Tmp2, Tmp3, 2738 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2739 } else { 2740 Result = DAG.getSelectCC(Tmp1, 2741 DAG.getConstant(0, Tmp1.getValueType()), 2742 Tmp2, Tmp3, ISD::SETNE); 2743 } 2744 break; 2745 case TargetLowering::Promote: { 2746 MVT NVT = 2747 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2748 unsigned ExtOp, TruncOp; 2749 if (Tmp2.getValueType().isVector()) { 2750 ExtOp = ISD::BIT_CONVERT; 2751 TruncOp = ISD::BIT_CONVERT; 2752 } else if (Tmp2.getValueType().isInteger()) { 2753 ExtOp = ISD::ANY_EXTEND; 2754 TruncOp = ISD::TRUNCATE; 2755 } else { 2756 ExtOp = ISD::FP_EXTEND; 2757 TruncOp = ISD::FP_ROUND; 2758 } 2759 // Promote each of the values to the new type. 2760 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2761 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2762 // Perform the larger operation, then round down. 2763 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2764 if (TruncOp != ISD::FP_ROUND) 2765 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2766 else 2767 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2768 DAG.getIntPtrConstant(0)); 2769 break; 2770 } 2771 } 2772 break; 2773 case ISD::SELECT_CC: { 2774 Tmp1 = Node->getOperand(0); // LHS 2775 Tmp2 = Node->getOperand(1); // RHS 2776 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2777 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2778 SDValue CC = Node->getOperand(4); 2779 2780 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, CC); 2781 2782 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 2783 // the LHS is a legal SETCC itself. In this case, we need to compare 2784 // the result against zero to select between true and false values. 2785 if (Tmp2.getNode() == 0) { 2786 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2787 CC = DAG.getCondCode(ISD::SETNE); 2788 } 2789 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2790 2791 // Everything is legal, see if we should expand this op or something. 2792 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2793 default: assert(0 && "This action is not supported yet!"); 2794 case TargetLowering::Legal: break; 2795 case TargetLowering::Custom: 2796 Tmp1 = TLI.LowerOperation(Result, DAG); 2797 if (Tmp1.getNode()) Result = Tmp1; 2798 break; 2799 } 2800 break; 2801 } 2802 case ISD::SETCC: 2803 Tmp1 = Node->getOperand(0); 2804 Tmp2 = Node->getOperand(1); 2805 Tmp3 = Node->getOperand(2); 2806 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3); 2807 2808 // If we had to Expand the SetCC operands into a SELECT node, then it may 2809 // not always be possible to return a true LHS & RHS. In this case, just 2810 // return the value we legalized, returned in the LHS 2811 if (Tmp2.getNode() == 0) { 2812 Result = Tmp1; 2813 break; 2814 } 2815 2816 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2817 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2818 case TargetLowering::Custom: 2819 isCustom = true; 2820 // FALLTHROUGH. 2821 case TargetLowering::Legal: 2822 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2823 if (isCustom) { 2824 Tmp4 = TLI.LowerOperation(Result, DAG); 2825 if (Tmp4.getNode()) Result = Tmp4; 2826 } 2827 break; 2828 case TargetLowering::Promote: { 2829 // First step, figure out the appropriate operation to use. 2830 // Allow SETCC to not be supported for all legal data types 2831 // Mostly this targets FP 2832 MVT NewInTy = Node->getOperand(0).getValueType(); 2833 MVT OldVT = NewInTy; OldVT = OldVT; 2834 2835 // Scan for the appropriate larger type to use. 2836 while (1) { 2837 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 2838 2839 assert(NewInTy.isInteger() == OldVT.isInteger() && 2840 "Fell off of the edge of the integer world"); 2841 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 2842 "Fell off of the edge of the floating point world"); 2843 2844 // If the target supports SETCC of this type, use it. 2845 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2846 break; 2847 } 2848 if (NewInTy.isInteger()) 2849 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2850 else { 2851 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2852 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2853 } 2854 Tmp1 = LegalizeOp(Tmp1); 2855 Tmp2 = LegalizeOp(Tmp2); 2856 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2857 Result = LegalizeOp(Result); 2858 break; 2859 } 2860 case TargetLowering::Expand: 2861 // Expand a setcc node into a select_cc of the same condition, lhs, and 2862 // rhs that selects between const 1 (true) and const 0 (false). 2863 MVT VT = Node->getValueType(0); 2864 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2865 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2866 Tmp3); 2867 break; 2868 } 2869 break; 2870 case ISD::VSETCC: { 2871 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2872 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2873 SDValue CC = Node->getOperand(2); 2874 2875 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC); 2876 2877 // Everything is legal, see if we should expand this op or something. 2878 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) { 2879 default: assert(0 && "This action is not supported yet!"); 2880 case TargetLowering::Legal: break; 2881 case TargetLowering::Custom: 2882 Tmp1 = TLI.LowerOperation(Result, DAG); 2883 if (Tmp1.getNode()) Result = Tmp1; 2884 break; 2885 } 2886 break; 2887 } 2888 2889 case ISD::SHL_PARTS: 2890 case ISD::SRA_PARTS: 2891 case ISD::SRL_PARTS: { 2892 SmallVector<SDValue, 8> Ops; 2893 bool Changed = false; 2894 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2895 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2896 Changed |= Ops.back() != Node->getOperand(i); 2897 } 2898 if (Changed) 2899 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2900 2901 switch (TLI.getOperationAction(Node->getOpcode(), 2902 Node->getValueType(0))) { 2903 default: assert(0 && "This action is not supported yet!"); 2904 case TargetLowering::Legal: break; 2905 case TargetLowering::Custom: 2906 Tmp1 = TLI.LowerOperation(Result, DAG); 2907 if (Tmp1.getNode()) { 2908 SDValue Tmp2, RetVal(0, 0); 2909 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2910 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2911 AddLegalizedOperand(SDValue(Node, i), Tmp2); 2912 if (i == Op.getResNo()) 2913 RetVal = Tmp2; 2914 } 2915 assert(RetVal.getNode() && "Illegal result number"); 2916 return RetVal; 2917 } 2918 break; 2919 } 2920 2921 // Since these produce multiple values, make sure to remember that we 2922 // legalized all of them. 2923 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2924 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i)); 2925 return Result.getValue(Op.getResNo()); 2926 } 2927 2928 // Binary operators 2929 case ISD::ADD: 2930 case ISD::SUB: 2931 case ISD::MUL: 2932 case ISD::MULHS: 2933 case ISD::MULHU: 2934 case ISD::UDIV: 2935 case ISD::SDIV: 2936 case ISD::AND: 2937 case ISD::OR: 2938 case ISD::XOR: 2939 case ISD::SHL: 2940 case ISD::SRL: 2941 case ISD::SRA: 2942 case ISD::FADD: 2943 case ISD::FSUB: 2944 case ISD::FMUL: 2945 case ISD::FDIV: 2946 case ISD::FPOW: 2947 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2948 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2949 case Expand: assert(0 && "Not possible"); 2950 case Legal: 2951 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2952 break; 2953 case Promote: 2954 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2955 break; 2956 } 2957 2958 if ((Node->getOpcode() == ISD::SHL || 2959 Node->getOpcode() == ISD::SRL || 2960 Node->getOpcode() == ISD::SRA) && 2961 !Node->getValueType(0).isVector()) { 2962 if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType())) 2963 Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2); 2964 else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType())) 2965 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2); 2966 } 2967 2968 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2969 2970 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2971 default: assert(0 && "BinOp legalize operation not supported"); 2972 case TargetLowering::Legal: break; 2973 case TargetLowering::Custom: 2974 Tmp1 = TLI.LowerOperation(Result, DAG); 2975 if (Tmp1.getNode()) { 2976 Result = Tmp1; 2977 break; 2978 } 2979 // Fall through if the custom lower can't deal with the operation 2980 case TargetLowering::Expand: { 2981 MVT VT = Op.getValueType(); 2982 2983 // See if multiply or divide can be lowered using two-result operations. 2984 SDVTList VTs = DAG.getVTList(VT, VT); 2985 if (Node->getOpcode() == ISD::MUL) { 2986 // We just need the low half of the multiply; try both the signed 2987 // and unsigned forms. If the target supports both SMUL_LOHI and 2988 // UMUL_LOHI, form a preference by checking which forms of plain 2989 // MULH it supports. 2990 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2991 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2992 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2993 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2994 unsigned OpToUse = 0; 2995 if (HasSMUL_LOHI && !HasMULHS) { 2996 OpToUse = ISD::SMUL_LOHI; 2997 } else if (HasUMUL_LOHI && !HasMULHU) { 2998 OpToUse = ISD::UMUL_LOHI; 2999 } else if (HasSMUL_LOHI) { 3000 OpToUse = ISD::SMUL_LOHI; 3001 } else if (HasUMUL_LOHI) { 3002 OpToUse = ISD::UMUL_LOHI; 3003 } 3004 if (OpToUse) { 3005 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0); 3006 break; 3007 } 3008 } 3009 if (Node->getOpcode() == ISD::MULHS && 3010 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 3011 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 3012 1); 3013 break; 3014 } 3015 if (Node->getOpcode() == ISD::MULHU && 3016 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 3017 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 3018 1); 3019 break; 3020 } 3021 if (Node->getOpcode() == ISD::SDIV && 3022 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3023 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 3024 0); 3025 break; 3026 } 3027 if (Node->getOpcode() == ISD::UDIV && 3028 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3029 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 3030 0); 3031 break; 3032 } 3033 3034 // Check to see if we have a libcall for this operator. 3035 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3036 bool isSigned = false; 3037 switch (Node->getOpcode()) { 3038 case ISD::UDIV: 3039 case ISD::SDIV: 3040 if (VT == MVT::i32) { 3041 LC = Node->getOpcode() == ISD::UDIV 3042 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3043 isSigned = Node->getOpcode() == ISD::SDIV; 3044 } 3045 break; 3046 case ISD::MUL: 3047 if (VT == MVT::i32) 3048 LC = RTLIB::MUL_I32; 3049 break; 3050 case ISD::FPOW: 3051 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3052 RTLIB::POW_PPCF128); 3053 break; 3054 default: break; 3055 } 3056 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3057 SDValue Dummy; 3058 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3059 break; 3060 } 3061 3062 assert(Node->getValueType(0).isVector() && 3063 "Cannot expand this binary operator!"); 3064 // Expand the operation into a bunch of nasty scalar code. 3065 Result = LegalizeOp(UnrollVectorOp(Op)); 3066 break; 3067 } 3068 case TargetLowering::Promote: { 3069 switch (Node->getOpcode()) { 3070 default: assert(0 && "Do not know how to promote this BinOp!"); 3071 case ISD::AND: 3072 case ISD::OR: 3073 case ISD::XOR: { 3074 MVT OVT = Node->getValueType(0); 3075 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3076 assert(OVT.isVector() && "Cannot promote this BinOp!"); 3077 // Bit convert each of the values to the new type. 3078 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 3079 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 3080 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3081 // Bit convert the result back the original type. 3082 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 3083 break; 3084 } 3085 } 3086 } 3087 } 3088 break; 3089 3090 case ISD::SMUL_LOHI: 3091 case ISD::UMUL_LOHI: 3092 case ISD::SDIVREM: 3093 case ISD::UDIVREM: 3094 // These nodes will only be produced by target-specific lowering, so 3095 // they shouldn't be here if they aren't legal. 3096 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3097 "This must be legal!"); 3098 3099 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3100 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3102 break; 3103 3104 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3105 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3106 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3107 case Expand: assert(0 && "Not possible"); 3108 case Legal: 3109 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3110 break; 3111 case Promote: 3112 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3113 break; 3114 } 3115 3116 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3117 3118 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3119 default: assert(0 && "Operation not supported"); 3120 case TargetLowering::Custom: 3121 Tmp1 = TLI.LowerOperation(Result, DAG); 3122 if (Tmp1.getNode()) Result = Tmp1; 3123 break; 3124 case TargetLowering::Legal: break; 3125 case TargetLowering::Expand: { 3126 // If this target supports fabs/fneg natively and select is cheap, 3127 // do this efficiently. 3128 if (!TLI.isSelectExpensive() && 3129 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3130 TargetLowering::Legal && 3131 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3132 TargetLowering::Legal) { 3133 // Get the sign bit of the RHS. 3134 MVT IVT = 3135 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3136 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 3137 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), 3138 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3139 // Get the absolute value of the result. 3140 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 3141 // Select between the nabs and abs value based on the sign bit of 3142 // the input. 3143 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 3144 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3145 AbsVal), 3146 AbsVal); 3147 Result = LegalizeOp(Result); 3148 break; 3149 } 3150 3151 // Otherwise, do bitwise ops! 3152 MVT NVT = 3153 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3154 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3155 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 3156 Result = LegalizeOp(Result); 3157 break; 3158 } 3159 } 3160 break; 3161 3162 case ISD::ADDC: 3163 case ISD::SUBC: 3164 Tmp1 = LegalizeOp(Node->getOperand(0)); 3165 Tmp2 = LegalizeOp(Node->getOperand(1)); 3166 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3167 // Since this produces two values, make sure to remember that we legalized 3168 // both of them. 3169 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 3170 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 3171 return Result; 3172 3173 case ISD::ADDE: 3174 case ISD::SUBE: 3175 Tmp1 = LegalizeOp(Node->getOperand(0)); 3176 Tmp2 = LegalizeOp(Node->getOperand(1)); 3177 Tmp3 = LegalizeOp(Node->getOperand(2)); 3178 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3179 // Since this produces two values, make sure to remember that we legalized 3180 // both of them. 3181 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 3182 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 3183 return Result; 3184 3185 case ISD::BUILD_PAIR: { 3186 MVT PairTy = Node->getValueType(0); 3187 // TODO: handle the case where the Lo and Hi operands are not of legal type 3188 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3189 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3190 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3191 case TargetLowering::Promote: 3192 case TargetLowering::Custom: 3193 assert(0 && "Cannot promote/custom this yet!"); 3194 case TargetLowering::Legal: 3195 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3196 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 3197 break; 3198 case TargetLowering::Expand: 3199 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 3200 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 3201 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 3202 DAG.getConstant(PairTy.getSizeInBits()/2, 3203 TLI.getShiftAmountTy())); 3204 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 3205 break; 3206 } 3207 break; 3208 } 3209 3210 case ISD::UREM: 3211 case ISD::SREM: 3212 case ISD::FREM: 3213 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3214 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3215 3216 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3217 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3218 case TargetLowering::Custom: 3219 isCustom = true; 3220 // FALLTHROUGH 3221 case TargetLowering::Legal: 3222 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3223 if (isCustom) { 3224 Tmp1 = TLI.LowerOperation(Result, DAG); 3225 if (Tmp1.getNode()) Result = Tmp1; 3226 } 3227 break; 3228 case TargetLowering::Expand: { 3229 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3230 bool isSigned = DivOpc == ISD::SDIV; 3231 MVT VT = Node->getValueType(0); 3232 3233 // See if remainder can be lowered using two-result operations. 3234 SDVTList VTs = DAG.getVTList(VT, VT); 3235 if (Node->getOpcode() == ISD::SREM && 3236 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3237 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1); 3238 break; 3239 } 3240 if (Node->getOpcode() == ISD::UREM && 3241 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3242 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1); 3243 break; 3244 } 3245 3246 if (VT.isInteger()) { 3247 if (TLI.getOperationAction(DivOpc, VT) == 3248 TargetLowering::Legal) { 3249 // X % Y -> X-X/Y*Y 3250 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3251 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3252 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3253 } else if (VT.isVector()) { 3254 Result = LegalizeOp(UnrollVectorOp(Op)); 3255 } else { 3256 assert(VT == MVT::i32 && 3257 "Cannot expand this binary operator!"); 3258 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3259 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3260 SDValue Dummy; 3261 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3262 } 3263 } else { 3264 assert(VT.isFloatingPoint() && 3265 "remainder op must have integer or floating-point type"); 3266 if (VT.isVector()) { 3267 Result = LegalizeOp(UnrollVectorOp(Op)); 3268 } else { 3269 // Floating point mod -> fmod libcall. 3270 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3271 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3272 SDValue Dummy; 3273 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3274 } 3275 } 3276 break; 3277 } 3278 } 3279 break; 3280 case ISD::VAARG: { 3281 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3282 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3283 3284 MVT VT = Node->getValueType(0); 3285 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3286 default: assert(0 && "This action is not supported yet!"); 3287 case TargetLowering::Custom: 3288 isCustom = true; 3289 // FALLTHROUGH 3290 case TargetLowering::Legal: 3291 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3292 Result = Result.getValue(0); 3293 Tmp1 = Result.getValue(1); 3294 3295 if (isCustom) { 3296 Tmp2 = TLI.LowerOperation(Result, DAG); 3297 if (Tmp2.getNode()) { 3298 Result = LegalizeOp(Tmp2); 3299 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3300 } 3301 } 3302 break; 3303 case TargetLowering::Expand: { 3304 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3305 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 3306 // Increment the pointer, VAList, to the next vaarg 3307 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3308 DAG.getConstant(VT.getSizeInBits()/8, 3309 TLI.getPointerTy())); 3310 // Store the incremented VAList to the legalized pointer 3311 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 3312 // Load the actual argument out of the pointer VAList 3313 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3314 Tmp1 = LegalizeOp(Result.getValue(1)); 3315 Result = LegalizeOp(Result); 3316 break; 3317 } 3318 } 3319 // Since VAARG produces two values, make sure to remember that we 3320 // legalized both of them. 3321 AddLegalizedOperand(SDValue(Node, 0), Result); 3322 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 3323 return Op.getResNo() ? Tmp1 : Result; 3324 } 3325 3326 case ISD::VACOPY: 3327 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3328 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3329 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3330 3331 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3332 default: assert(0 && "This action is not supported yet!"); 3333 case TargetLowering::Custom: 3334 isCustom = true; 3335 // FALLTHROUGH 3336 case TargetLowering::Legal: 3337 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3338 Node->getOperand(3), Node->getOperand(4)); 3339 if (isCustom) { 3340 Tmp1 = TLI.LowerOperation(Result, DAG); 3341 if (Tmp1.getNode()) Result = Tmp1; 3342 } 3343 break; 3344 case TargetLowering::Expand: 3345 // This defaults to loading a pointer from the input and storing it to the 3346 // output, returning the chain. 3347 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3348 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3349 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0); 3350 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0); 3351 break; 3352 } 3353 break; 3354 3355 case ISD::VAEND: 3356 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3357 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3358 3359 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3360 default: assert(0 && "This action is not supported yet!"); 3361 case TargetLowering::Custom: 3362 isCustom = true; 3363 // FALLTHROUGH 3364 case TargetLowering::Legal: 3365 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3366 if (isCustom) { 3367 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3368 if (Tmp1.getNode()) Result = Tmp1; 3369 } 3370 break; 3371 case TargetLowering::Expand: 3372 Result = Tmp1; // Default to a no-op, return the chain 3373 break; 3374 } 3375 break; 3376 3377 case ISD::VASTART: 3378 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3379 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3380 3381 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3382 3383 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3384 default: assert(0 && "This action is not supported yet!"); 3385 case TargetLowering::Legal: break; 3386 case TargetLowering::Custom: 3387 Tmp1 = TLI.LowerOperation(Result, DAG); 3388 if (Tmp1.getNode()) Result = Tmp1; 3389 break; 3390 } 3391 break; 3392 3393 case ISD::ROTL: 3394 case ISD::ROTR: 3395 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3396 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3397 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3398 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3399 default: 3400 assert(0 && "ROTL/ROTR legalize operation not supported"); 3401 break; 3402 case TargetLowering::Legal: 3403 break; 3404 case TargetLowering::Custom: 3405 Tmp1 = TLI.LowerOperation(Result, DAG); 3406 if (Tmp1.getNode()) Result = Tmp1; 3407 break; 3408 case TargetLowering::Promote: 3409 assert(0 && "Do not know how to promote ROTL/ROTR"); 3410 break; 3411 case TargetLowering::Expand: 3412 assert(0 && "Do not know how to expand ROTL/ROTR"); 3413 break; 3414 } 3415 break; 3416 3417 case ISD::BSWAP: 3418 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3419 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3420 case TargetLowering::Custom: 3421 assert(0 && "Cannot custom legalize this yet!"); 3422 case TargetLowering::Legal: 3423 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3424 break; 3425 case TargetLowering::Promote: { 3426 MVT OVT = Tmp1.getValueType(); 3427 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3428 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3429 3430 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3431 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3432 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3433 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3434 break; 3435 } 3436 case TargetLowering::Expand: 3437 Result = ExpandBSWAP(Tmp1); 3438 break; 3439 } 3440 break; 3441 3442 case ISD::CTPOP: 3443 case ISD::CTTZ: 3444 case ISD::CTLZ: 3445 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3446 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3447 case TargetLowering::Custom: 3448 case TargetLowering::Legal: 3449 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3450 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3451 TargetLowering::Custom) { 3452 Tmp1 = TLI.LowerOperation(Result, DAG); 3453 if (Tmp1.getNode()) { 3454 Result = Tmp1; 3455 } 3456 } 3457 break; 3458 case TargetLowering::Promote: { 3459 MVT OVT = Tmp1.getValueType(); 3460 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3461 3462 // Zero extend the argument. 3463 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3464 // Perform the larger operation, then subtract if needed. 3465 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3466 switch (Node->getOpcode()) { 3467 case ISD::CTPOP: 3468 Result = Tmp1; 3469 break; 3470 case ISD::CTTZ: 3471 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3472 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 3473 DAG.getConstant(NVT.getSizeInBits(), NVT), 3474 ISD::SETEQ); 3475 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3476 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3477 break; 3478 case ISD::CTLZ: 3479 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3480 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3481 DAG.getConstant(NVT.getSizeInBits() - 3482 OVT.getSizeInBits(), NVT)); 3483 break; 3484 } 3485 break; 3486 } 3487 case TargetLowering::Expand: 3488 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3489 break; 3490 } 3491 break; 3492 3493 // Unary operators 3494 case ISD::FABS: 3495 case ISD::FNEG: 3496 case ISD::FSQRT: 3497 case ISD::FSIN: 3498 case ISD::FCOS: 3499 case ISD::FLOG: 3500 case ISD::FLOG2: 3501 case ISD::FLOG10: 3502 case ISD::FEXP: 3503 case ISD::FEXP2: 3504 case ISD::FTRUNC: 3505 case ISD::FFLOOR: 3506 case ISD::FCEIL: 3507 case ISD::FRINT: 3508 case ISD::FNEARBYINT: 3509 Tmp1 = LegalizeOp(Node->getOperand(0)); 3510 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3511 case TargetLowering::Promote: 3512 case TargetLowering::Custom: 3513 isCustom = true; 3514 // FALLTHROUGH 3515 case TargetLowering::Legal: 3516 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3517 if (isCustom) { 3518 Tmp1 = TLI.LowerOperation(Result, DAG); 3519 if (Tmp1.getNode()) Result = Tmp1; 3520 } 3521 break; 3522 case TargetLowering::Expand: 3523 switch (Node->getOpcode()) { 3524 default: assert(0 && "Unreachable!"); 3525 case ISD::FNEG: 3526 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3527 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3528 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3529 break; 3530 case ISD::FABS: { 3531 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3532 MVT VT = Node->getValueType(0); 3533 Tmp2 = DAG.getConstantFP(0.0, VT); 3534 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 3535 ISD::SETUGT); 3536 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3537 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3538 break; 3539 } 3540 case ISD::FSQRT: 3541 case ISD::FSIN: 3542 case ISD::FCOS: 3543 case ISD::FLOG: 3544 case ISD::FLOG2: 3545 case ISD::FLOG10: 3546 case ISD::FEXP: 3547 case ISD::FEXP2: 3548 case ISD::FTRUNC: 3549 case ISD::FFLOOR: 3550 case ISD::FCEIL: 3551 case ISD::FRINT: 3552 case ISD::FNEARBYINT: { 3553 MVT VT = Node->getValueType(0); 3554 3555 // Expand unsupported unary vector operators by unrolling them. 3556 if (VT.isVector()) { 3557 Result = LegalizeOp(UnrollVectorOp(Op)); 3558 break; 3559 } 3560 3561 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3562 switch(Node->getOpcode()) { 3563 case ISD::FSQRT: 3564 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3565 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3566 break; 3567 case ISD::FSIN: 3568 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3569 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3570 break; 3571 case ISD::FCOS: 3572 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3573 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3574 break; 3575 case ISD::FLOG: 3576 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64, 3577 RTLIB::LOG_F80, RTLIB::LOG_PPCF128); 3578 break; 3579 case ISD::FLOG2: 3580 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 3581 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128); 3582 break; 3583 case ISD::FLOG10: 3584 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 3585 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128); 3586 break; 3587 case ISD::FEXP: 3588 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64, 3589 RTLIB::EXP_F80, RTLIB::EXP_PPCF128); 3590 break; 3591 case ISD::FEXP2: 3592 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 3593 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128); 3594 break; 3595 case ISD::FTRUNC: 3596 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 3597 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 3598 break; 3599 case ISD::FFLOOR: 3600 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 3601 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 3602 break; 3603 case ISD::FCEIL: 3604 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 3605 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 3606 break; 3607 case ISD::FRINT: 3608 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 3609 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 3610 break; 3611 case ISD::FNEARBYINT: 3612 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 3613 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 3614 break; 3615 break; 3616 default: assert(0 && "Unreachable!"); 3617 } 3618 SDValue Dummy; 3619 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3620 break; 3621 } 3622 } 3623 break; 3624 } 3625 break; 3626 case ISD::FPOWI: { 3627 MVT VT = Node->getValueType(0); 3628 3629 // Expand unsupported unary vector operators by unrolling them. 3630 if (VT.isVector()) { 3631 Result = LegalizeOp(UnrollVectorOp(Op)); 3632 break; 3633 } 3634 3635 // We always lower FPOWI into a libcall. No target support for it yet. 3636 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3637 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3638 SDValue Dummy; 3639 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3640 break; 3641 } 3642 case ISD::BIT_CONVERT: 3643 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3644 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3645 Node->getValueType(0)); 3646 } else if (Op.getOperand(0).getValueType().isVector()) { 3647 // The input has to be a vector type, we have to either scalarize it, pack 3648 // it, or convert it based on whether the input vector type is legal. 3649 SDNode *InVal = Node->getOperand(0).getNode(); 3650 int InIx = Node->getOperand(0).getResNo(); 3651 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 3652 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 3653 3654 // Figure out if there is a simple type corresponding to this Vector 3655 // type. If so, convert to the vector type. 3656 MVT TVT = MVT::getVectorVT(EVT, NumElems); 3657 if (TLI.isTypeLegal(TVT)) { 3658 // Turn this into a bit convert of the vector input. 3659 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3660 LegalizeOp(Node->getOperand(0))); 3661 break; 3662 } else if (NumElems == 1) { 3663 // Turn this into a bit convert of the scalar input. 3664 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3665 ScalarizeVectorOp(Node->getOperand(0))); 3666 break; 3667 } else { 3668 // FIXME: UNIMP! Store then reload 3669 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3670 } 3671 } else { 3672 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3673 Node->getOperand(0).getValueType())) { 3674 default: assert(0 && "Unknown operation action!"); 3675 case TargetLowering::Expand: 3676 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3677 Node->getValueType(0)); 3678 break; 3679 case TargetLowering::Legal: 3680 Tmp1 = LegalizeOp(Node->getOperand(0)); 3681 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3682 break; 3683 } 3684 } 3685 break; 3686 3687 // Conversion operators. The source and destination have different types. 3688 case ISD::SINT_TO_FP: 3689 case ISD::UINT_TO_FP: { 3690 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3691 Result = LegalizeINT_TO_FP(Result, isSigned, 3692 Node->getValueType(0), Node->getOperand(0)); 3693 break; 3694 } 3695 case ISD::TRUNCATE: 3696 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3697 case Legal: 3698 Tmp1 = LegalizeOp(Node->getOperand(0)); 3699 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3700 break; 3701 case Expand: 3702 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3703 3704 // Since the result is legal, we should just be able to truncate the low 3705 // part of the source. 3706 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3707 break; 3708 case Promote: 3709 Result = PromoteOp(Node->getOperand(0)); 3710 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3711 break; 3712 } 3713 break; 3714 3715 case ISD::FP_TO_SINT: 3716 case ISD::FP_TO_UINT: 3717 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3718 case Legal: 3719 Tmp1 = LegalizeOp(Node->getOperand(0)); 3720 3721 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3722 default: assert(0 && "Unknown operation action!"); 3723 case TargetLowering::Custom: 3724 isCustom = true; 3725 // FALLTHROUGH 3726 case TargetLowering::Legal: 3727 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3728 if (isCustom) { 3729 Tmp1 = TLI.LowerOperation(Result, DAG); 3730 if (Tmp1.getNode()) Result = Tmp1; 3731 } 3732 break; 3733 case TargetLowering::Promote: 3734 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3735 Node->getOpcode() == ISD::FP_TO_SINT); 3736 break; 3737 case TargetLowering::Expand: 3738 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3739 SDValue True, False; 3740 MVT VT = Node->getOperand(0).getValueType(); 3741 MVT NVT = Node->getValueType(0); 3742 const uint64_t zero[] = {0, 0}; 3743 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 3744 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 3745 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 3746 Tmp2 = DAG.getConstantFP(apf, VT); 3747 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)), 3748 Node->getOperand(0), Tmp2, ISD::SETLT); 3749 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3750 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3751 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3752 Tmp2)); 3753 False = DAG.getNode(ISD::XOR, NVT, False, 3754 DAG.getConstant(x, NVT)); 3755 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3756 break; 3757 } else { 3758 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3759 } 3760 break; 3761 } 3762 break; 3763 case Expand: { 3764 MVT VT = Op.getValueType(); 3765 MVT OVT = Node->getOperand(0).getValueType(); 3766 // Convert ppcf128 to i32 3767 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3768 if (Node->getOpcode() == ISD::FP_TO_SINT) { 3769 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 3770 Node->getOperand(0), DAG.getValueType(MVT::f64)); 3771 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 3772 DAG.getIntPtrConstant(1)); 3773 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 3774 } else { 3775 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3776 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3777 Tmp2 = DAG.getConstantFP(apf, OVT); 3778 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3779 // FIXME: generated code sucks. 3780 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3781 DAG.getNode(ISD::ADD, MVT::i32, 3782 DAG.getNode(ISD::FP_TO_SINT, VT, 3783 DAG.getNode(ISD::FSUB, OVT, 3784 Node->getOperand(0), Tmp2)), 3785 DAG.getConstant(0x80000000, MVT::i32)), 3786 DAG.getNode(ISD::FP_TO_SINT, VT, 3787 Node->getOperand(0)), 3788 DAG.getCondCode(ISD::SETGE)); 3789 } 3790 break; 3791 } 3792 // Convert f32 / f64 to i32 / i64 / i128. 3793 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ? 3794 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT); 3795 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!"); 3796 SDValue Dummy; 3797 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3798 break; 3799 } 3800 case Promote: 3801 Tmp1 = PromoteOp(Node->getOperand(0)); 3802 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3803 Result = LegalizeOp(Result); 3804 break; 3805 } 3806 break; 3807 3808 case ISD::FP_EXTEND: { 3809 MVT DstVT = Op.getValueType(); 3810 MVT SrcVT = Op.getOperand(0).getValueType(); 3811 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3812 // The only other way we can lower this is to turn it into a STORE, 3813 // LOAD pair, targetting a temporary location (a stack slot). 3814 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 3815 break; 3816 } 3817 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3818 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3819 case Legal: 3820 Tmp1 = LegalizeOp(Node->getOperand(0)); 3821 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3822 break; 3823 case Promote: 3824 Tmp1 = PromoteOp(Node->getOperand(0)); 3825 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 3826 break; 3827 } 3828 break; 3829 } 3830 case ISD::FP_ROUND: { 3831 MVT DstVT = Op.getValueType(); 3832 MVT SrcVT = Op.getOperand(0).getValueType(); 3833 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3834 if (SrcVT == MVT::ppcf128) { 3835 SDValue Lo; 3836 ExpandOp(Node->getOperand(0), Lo, Result); 3837 // Round it the rest of the way (e.g. to f32) if needed. 3838 if (DstVT!=MVT::f64) 3839 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 3840 break; 3841 } 3842 // The only other way we can lower this is to turn it into a STORE, 3843 // LOAD pair, targetting a temporary location (a stack slot). 3844 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 3845 break; 3846 } 3847 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3848 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3849 case Legal: 3850 Tmp1 = LegalizeOp(Node->getOperand(0)); 3851 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3852 break; 3853 case Promote: 3854 Tmp1 = PromoteOp(Node->getOperand(0)); 3855 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 3856 Node->getOperand(1)); 3857 break; 3858 } 3859 break; 3860 } 3861 case ISD::ANY_EXTEND: 3862 case ISD::ZERO_EXTEND: 3863 case ISD::SIGN_EXTEND: 3864 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3865 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3866 case Legal: 3867 Tmp1 = LegalizeOp(Node->getOperand(0)); 3868 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3869 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3870 TargetLowering::Custom) { 3871 Tmp1 = TLI.LowerOperation(Result, DAG); 3872 if (Tmp1.getNode()) Result = Tmp1; 3873 } 3874 break; 3875 case Promote: 3876 switch (Node->getOpcode()) { 3877 case ISD::ANY_EXTEND: 3878 Tmp1 = PromoteOp(Node->getOperand(0)); 3879 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3880 break; 3881 case ISD::ZERO_EXTEND: 3882 Result = PromoteOp(Node->getOperand(0)); 3883 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3884 Result = DAG.getZeroExtendInReg(Result, 3885 Node->getOperand(0).getValueType()); 3886 break; 3887 case ISD::SIGN_EXTEND: 3888 Result = PromoteOp(Node->getOperand(0)); 3889 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3890 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3891 Result, 3892 DAG.getValueType(Node->getOperand(0).getValueType())); 3893 break; 3894 } 3895 } 3896 break; 3897 case ISD::FP_ROUND_INREG: 3898 case ISD::SIGN_EXTEND_INREG: { 3899 Tmp1 = LegalizeOp(Node->getOperand(0)); 3900 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3901 3902 // If this operation is not supported, convert it to a shl/shr or load/store 3903 // pair. 3904 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3905 default: assert(0 && "This action not supported for this op yet!"); 3906 case TargetLowering::Legal: 3907 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3908 break; 3909 case TargetLowering::Expand: 3910 // If this is an integer extend and shifts are supported, do that. 3911 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3912 // NOTE: we could fall back on load/store here too for targets without 3913 // SAR. However, it is doubtful that any exist. 3914 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 3915 ExtraVT.getSizeInBits(); 3916 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3917 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3918 Node->getOperand(0), ShiftCst); 3919 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3920 Result, ShiftCst); 3921 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3922 // The only way we can lower this is to turn it into a TRUNCSTORE, 3923 // EXTLOAD pair, targetting a temporary location (a stack slot). 3924 3925 // NOTE: there is a choice here between constantly creating new stack 3926 // slots and always reusing the same one. We currently always create 3927 // new ones, as reuse may inhibit scheduling. 3928 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 3929 Node->getValueType(0)); 3930 } else { 3931 assert(0 && "Unknown op"); 3932 } 3933 break; 3934 } 3935 break; 3936 } 3937 case ISD::TRAMPOLINE: { 3938 SDValue Ops[6]; 3939 for (unsigned i = 0; i != 6; ++i) 3940 Ops[i] = LegalizeOp(Node->getOperand(i)); 3941 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3942 // The only option for this node is to custom lower it. 3943 Result = TLI.LowerOperation(Result, DAG); 3944 assert(Result.getNode() && "Should always custom lower!"); 3945 3946 // Since trampoline produces two values, make sure to remember that we 3947 // legalized both of them. 3948 Tmp1 = LegalizeOp(Result.getValue(1)); 3949 Result = LegalizeOp(Result); 3950 AddLegalizedOperand(SDValue(Node, 0), Result); 3951 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 3952 return Op.getResNo() ? Tmp1 : Result; 3953 } 3954 case ISD::FLT_ROUNDS_: { 3955 MVT VT = Node->getValueType(0); 3956 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3957 default: assert(0 && "This action not supported for this op yet!"); 3958 case TargetLowering::Custom: 3959 Result = TLI.LowerOperation(Op, DAG); 3960 if (Result.getNode()) break; 3961 // Fall Thru 3962 case TargetLowering::Legal: 3963 // If this operation is not supported, lower it to constant 1 3964 Result = DAG.getConstant(1, VT); 3965 break; 3966 } 3967 break; 3968 } 3969 case ISD::TRAP: { 3970 MVT VT = Node->getValueType(0); 3971 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3972 default: assert(0 && "This action not supported for this op yet!"); 3973 case TargetLowering::Legal: 3974 Tmp1 = LegalizeOp(Node->getOperand(0)); 3975 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3976 break; 3977 case TargetLowering::Custom: 3978 Result = TLI.LowerOperation(Op, DAG); 3979 if (Result.getNode()) break; 3980 // Fall Thru 3981 case TargetLowering::Expand: 3982 // If this operation is not supported, lower it to 'abort()' call 3983 Tmp1 = LegalizeOp(Node->getOperand(0)); 3984 TargetLowering::ArgListTy Args; 3985 std::pair<SDValue,SDValue> CallResult = 3986 TLI.LowerCallTo(Tmp1, Type::VoidTy, 3987 false, false, false, false, CallingConv::C, false, 3988 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 3989 Args, DAG); 3990 Result = CallResult.second; 3991 break; 3992 } 3993 break; 3994 } 3995 } 3996 3997 assert(Result.getValueType() == Op.getValueType() && 3998 "Bad legalization!"); 3999 4000 // Make sure that the generated code is itself legal. 4001 if (Result != Op) 4002 Result = LegalizeOp(Result); 4003 4004 // Note that LegalizeOp may be reentered even from single-use nodes, which 4005 // means that we always must cache transformed nodes. 4006 AddLegalizedOperand(Op, Result); 4007 return Result; 4008} 4009 4010/// PromoteOp - Given an operation that produces a value in an invalid type, 4011/// promote it to compute the value into a larger type. The produced value will 4012/// have the correct bits for the low portion of the register, but no guarantee 4013/// is made about the top bits: it may be zero, sign-extended, or garbage. 4014SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { 4015 MVT VT = Op.getValueType(); 4016 MVT NVT = TLI.getTypeToTransformTo(VT); 4017 assert(getTypeAction(VT) == Promote && 4018 "Caller should expand or legalize operands that are not promotable!"); 4019 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() && 4020 "Cannot promote to smaller type!"); 4021 4022 SDValue Tmp1, Tmp2, Tmp3; 4023 SDValue Result; 4024 SDNode *Node = Op.getNode(); 4025 4026 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op); 4027 if (I != PromotedNodes.end()) return I->second; 4028 4029 switch (Node->getOpcode()) { 4030 case ISD::CopyFromReg: 4031 assert(0 && "CopyFromReg must be legal!"); 4032 default: 4033#ifndef NDEBUG 4034 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4035#endif 4036 assert(0 && "Do not know how to promote this operator!"); 4037 abort(); 4038 case ISD::UNDEF: 4039 Result = DAG.getNode(ISD::UNDEF, NVT); 4040 break; 4041 case ISD::Constant: 4042 if (VT != MVT::i1) 4043 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 4044 else 4045 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 4046 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4047 break; 4048 case ISD::ConstantFP: 4049 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 4050 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4051 break; 4052 4053 case ISD::SETCC: 4054 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0))) 4055 && "SetCC type is not legal??"); 4056 Result = DAG.getNode(ISD::SETCC, 4057 TLI.getSetCCResultType(Node->getOperand(0)), 4058 Node->getOperand(0), Node->getOperand(1), 4059 Node->getOperand(2)); 4060 break; 4061 4062 case ISD::TRUNCATE: 4063 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4064 case Legal: 4065 Result = LegalizeOp(Node->getOperand(0)); 4066 assert(Result.getValueType().bitsGE(NVT) && 4067 "This truncation doesn't make sense!"); 4068 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT 4069 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 4070 break; 4071 case Promote: 4072 // The truncation is not required, because we don't guarantee anything 4073 // about high bits anyway. 4074 Result = PromoteOp(Node->getOperand(0)); 4075 break; 4076 case Expand: 4077 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4078 // Truncate the low part of the expanded value to the result type 4079 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 4080 } 4081 break; 4082 case ISD::SIGN_EXTEND: 4083 case ISD::ZERO_EXTEND: 4084 case ISD::ANY_EXTEND: 4085 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4086 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4087 case Legal: 4088 // Input is legal? Just do extend all the way to the larger type. 4089 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4090 break; 4091 case Promote: 4092 // Promote the reg if it's smaller. 4093 Result = PromoteOp(Node->getOperand(0)); 4094 // The high bits are not guaranteed to be anything. Insert an extend. 4095 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4096 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4097 DAG.getValueType(Node->getOperand(0).getValueType())); 4098 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4099 Result = DAG.getZeroExtendInReg(Result, 4100 Node->getOperand(0).getValueType()); 4101 break; 4102 } 4103 break; 4104 case ISD::BIT_CONVERT: 4105 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4106 Node->getValueType(0)); 4107 Result = PromoteOp(Result); 4108 break; 4109 4110 case ISD::FP_EXTEND: 4111 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4112 case ISD::FP_ROUND: 4113 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4114 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4115 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4116 case Legal: 4117 if (Node->getConstantOperandVal(1) == 0) { 4118 // Input is legal? Do an FP_ROUND_INREG. 4119 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 4120 DAG.getValueType(VT)); 4121 } else { 4122 // Just remove the truncate, it isn't affecting the value. 4123 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 4124 Node->getOperand(1)); 4125 } 4126 break; 4127 } 4128 break; 4129 case ISD::SINT_TO_FP: 4130 case ISD::UINT_TO_FP: 4131 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4132 case Legal: 4133 // No extra round required here. 4134 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4135 break; 4136 4137 case Promote: 4138 Result = PromoteOp(Node->getOperand(0)); 4139 if (Node->getOpcode() == ISD::SINT_TO_FP) 4140 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4141 Result, 4142 DAG.getValueType(Node->getOperand(0).getValueType())); 4143 else 4144 Result = DAG.getZeroExtendInReg(Result, 4145 Node->getOperand(0).getValueType()); 4146 // No extra round required here. 4147 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 4148 break; 4149 case Expand: 4150 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4151 Node->getOperand(0)); 4152 // Round if we cannot tolerate excess precision. 4153 if (NoExcessFPPrecision) 4154 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4155 DAG.getValueType(VT)); 4156 break; 4157 } 4158 break; 4159 4160 case ISD::SIGN_EXTEND_INREG: 4161 Result = PromoteOp(Node->getOperand(0)); 4162 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4163 Node->getOperand(1)); 4164 break; 4165 case ISD::FP_TO_SINT: 4166 case ISD::FP_TO_UINT: 4167 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4168 case Legal: 4169 case Expand: 4170 Tmp1 = Node->getOperand(0); 4171 break; 4172 case Promote: 4173 // The input result is prerounded, so we don't have to do anything 4174 // special. 4175 Tmp1 = PromoteOp(Node->getOperand(0)); 4176 break; 4177 } 4178 // If we're promoting a UINT to a larger size, check to see if the new node 4179 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4180 // we can use that instead. This allows us to generate better code for 4181 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4182 // legal, such as PowerPC. 4183 if (Node->getOpcode() == ISD::FP_TO_UINT && 4184 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 4185 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 4186 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4187 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 4188 } else { 4189 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4190 } 4191 break; 4192 4193 case ISD::FABS: 4194 case ISD::FNEG: 4195 Tmp1 = PromoteOp(Node->getOperand(0)); 4196 assert(Tmp1.getValueType() == NVT); 4197 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4198 // NOTE: we do not have to do any extra rounding here for 4199 // NoExcessFPPrecision, because we know the input will have the appropriate 4200 // precision, and these operations don't modify precision at all. 4201 break; 4202 4203 case ISD::FLOG: 4204 case ISD::FLOG2: 4205 case ISD::FLOG10: 4206 case ISD::FEXP: 4207 case ISD::FEXP2: 4208 case ISD::FSQRT: 4209 case ISD::FSIN: 4210 case ISD::FCOS: 4211 case ISD::FTRUNC: 4212 case ISD::FFLOOR: 4213 case ISD::FCEIL: 4214 case ISD::FRINT: 4215 case ISD::FNEARBYINT: 4216 Tmp1 = PromoteOp(Node->getOperand(0)); 4217 assert(Tmp1.getValueType() == NVT); 4218 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4219 if (NoExcessFPPrecision) 4220 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4221 DAG.getValueType(VT)); 4222 break; 4223 4224 case ISD::FPOW: 4225 case ISD::FPOWI: { 4226 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall 4227 // directly as well, which may be better. 4228 Tmp1 = PromoteOp(Node->getOperand(0)); 4229 Tmp2 = Node->getOperand(1); 4230 if (Node->getOpcode() == ISD::FPOW) 4231 Tmp2 = PromoteOp(Tmp2); 4232 assert(Tmp1.getValueType() == NVT); 4233 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4234 if (NoExcessFPPrecision) 4235 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4236 DAG.getValueType(VT)); 4237 break; 4238 } 4239 4240 case ISD::ATOMIC_CMP_SWAP_8: 4241 case ISD::ATOMIC_CMP_SWAP_16: 4242 case ISD::ATOMIC_CMP_SWAP_32: 4243 case ISD::ATOMIC_CMP_SWAP_64: { 4244 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4245 Tmp2 = PromoteOp(Node->getOperand(2)); 4246 Tmp3 = PromoteOp(Node->getOperand(3)); 4247 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 4248 AtomNode->getBasePtr(), Tmp2, Tmp3, 4249 AtomNode->getSrcValue(), 4250 AtomNode->getAlignment()); 4251 // Remember that we legalized the chain. 4252 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4253 break; 4254 } 4255 case ISD::ATOMIC_LOAD_ADD_8: 4256 case ISD::ATOMIC_LOAD_SUB_8: 4257 case ISD::ATOMIC_LOAD_AND_8: 4258 case ISD::ATOMIC_LOAD_OR_8: 4259 case ISD::ATOMIC_LOAD_XOR_8: 4260 case ISD::ATOMIC_LOAD_NAND_8: 4261 case ISD::ATOMIC_LOAD_MIN_8: 4262 case ISD::ATOMIC_LOAD_MAX_8: 4263 case ISD::ATOMIC_LOAD_UMIN_8: 4264 case ISD::ATOMIC_LOAD_UMAX_8: 4265 case ISD::ATOMIC_SWAP_8: 4266 case ISD::ATOMIC_LOAD_ADD_16: 4267 case ISD::ATOMIC_LOAD_SUB_16: 4268 case ISD::ATOMIC_LOAD_AND_16: 4269 case ISD::ATOMIC_LOAD_OR_16: 4270 case ISD::ATOMIC_LOAD_XOR_16: 4271 case ISD::ATOMIC_LOAD_NAND_16: 4272 case ISD::ATOMIC_LOAD_MIN_16: 4273 case ISD::ATOMIC_LOAD_MAX_16: 4274 case ISD::ATOMIC_LOAD_UMIN_16: 4275 case ISD::ATOMIC_LOAD_UMAX_16: 4276 case ISD::ATOMIC_SWAP_16: 4277 case ISD::ATOMIC_LOAD_ADD_32: 4278 case ISD::ATOMIC_LOAD_SUB_32: 4279 case ISD::ATOMIC_LOAD_AND_32: 4280 case ISD::ATOMIC_LOAD_OR_32: 4281 case ISD::ATOMIC_LOAD_XOR_32: 4282 case ISD::ATOMIC_LOAD_NAND_32: 4283 case ISD::ATOMIC_LOAD_MIN_32: 4284 case ISD::ATOMIC_LOAD_MAX_32: 4285 case ISD::ATOMIC_LOAD_UMIN_32: 4286 case ISD::ATOMIC_LOAD_UMAX_32: 4287 case ISD::ATOMIC_SWAP_32: 4288 case ISD::ATOMIC_LOAD_ADD_64: 4289 case ISD::ATOMIC_LOAD_SUB_64: 4290 case ISD::ATOMIC_LOAD_AND_64: 4291 case ISD::ATOMIC_LOAD_OR_64: 4292 case ISD::ATOMIC_LOAD_XOR_64: 4293 case ISD::ATOMIC_LOAD_NAND_64: 4294 case ISD::ATOMIC_LOAD_MIN_64: 4295 case ISD::ATOMIC_LOAD_MAX_64: 4296 case ISD::ATOMIC_LOAD_UMIN_64: 4297 case ISD::ATOMIC_LOAD_UMAX_64: 4298 case ISD::ATOMIC_SWAP_64: { 4299 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4300 Tmp2 = PromoteOp(Node->getOperand(2)); 4301 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 4302 AtomNode->getBasePtr(), Tmp2, 4303 AtomNode->getSrcValue(), 4304 AtomNode->getAlignment()); 4305 // Remember that we legalized the chain. 4306 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4307 break; 4308 } 4309 4310 case ISD::AND: 4311 case ISD::OR: 4312 case ISD::XOR: 4313 case ISD::ADD: 4314 case ISD::SUB: 4315 case ISD::MUL: 4316 // The input may have strange things in the top bits of the registers, but 4317 // these operations don't care. They may have weird bits going out, but 4318 // that too is okay if they are integer operations. 4319 Tmp1 = PromoteOp(Node->getOperand(0)); 4320 Tmp2 = PromoteOp(Node->getOperand(1)); 4321 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4322 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4323 break; 4324 case ISD::FADD: 4325 case ISD::FSUB: 4326 case ISD::FMUL: 4327 Tmp1 = PromoteOp(Node->getOperand(0)); 4328 Tmp2 = PromoteOp(Node->getOperand(1)); 4329 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4330 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4331 4332 // Floating point operations will give excess precision that we may not be 4333 // able to tolerate. If we DO allow excess precision, just leave it, 4334 // otherwise excise it. 4335 // FIXME: Why would we need to round FP ops more than integer ones? 4336 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4337 if (NoExcessFPPrecision) 4338 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4339 DAG.getValueType(VT)); 4340 break; 4341 4342 case ISD::SDIV: 4343 case ISD::SREM: 4344 // These operators require that their input be sign extended. 4345 Tmp1 = PromoteOp(Node->getOperand(0)); 4346 Tmp2 = PromoteOp(Node->getOperand(1)); 4347 if (NVT.isInteger()) { 4348 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4349 DAG.getValueType(VT)); 4350 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4351 DAG.getValueType(VT)); 4352 } 4353 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4354 4355 // Perform FP_ROUND: this is probably overly pessimistic. 4356 if (NVT.isFloatingPoint() && NoExcessFPPrecision) 4357 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4358 DAG.getValueType(VT)); 4359 break; 4360 case ISD::FDIV: 4361 case ISD::FREM: 4362 case ISD::FCOPYSIGN: 4363 // These operators require that their input be fp extended. 4364 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4365 case Expand: assert(0 && "not implemented"); 4366 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4367 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4368 } 4369 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4370 case Expand: assert(0 && "not implemented"); 4371 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4372 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4373 } 4374 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4375 4376 // Perform FP_ROUND: this is probably overly pessimistic. 4377 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4378 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4379 DAG.getValueType(VT)); 4380 break; 4381 4382 case ISD::UDIV: 4383 case ISD::UREM: 4384 // These operators require that their input be zero extended. 4385 Tmp1 = PromoteOp(Node->getOperand(0)); 4386 Tmp2 = PromoteOp(Node->getOperand(1)); 4387 assert(NVT.isInteger() && "Operators don't apply to FP!"); 4388 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4389 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4390 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4391 break; 4392 4393 case ISD::SHL: 4394 Tmp1 = PromoteOp(Node->getOperand(0)); 4395 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4396 break; 4397 case ISD::SRA: 4398 // The input value must be properly sign extended. 4399 Tmp1 = PromoteOp(Node->getOperand(0)); 4400 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4401 DAG.getValueType(VT)); 4402 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4403 break; 4404 case ISD::SRL: 4405 // The input value must be properly zero extended. 4406 Tmp1 = PromoteOp(Node->getOperand(0)); 4407 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4408 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4409 break; 4410 4411 case ISD::VAARG: 4412 Tmp1 = Node->getOperand(0); // Get the chain. 4413 Tmp2 = Node->getOperand(1); // Get the pointer. 4414 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4415 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4416 Result = TLI.LowerOperation(Tmp3, DAG); 4417 } else { 4418 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4419 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 4420 // Increment the pointer, VAList, to the next vaarg 4421 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4422 DAG.getConstant(VT.getSizeInBits()/8, 4423 TLI.getPointerTy())); 4424 // Store the incremented VAList to the legalized pointer 4425 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 4426 // Load the actual argument out of the pointer VAList 4427 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4428 } 4429 // Remember that we legalized the chain. 4430 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4431 break; 4432 4433 case ISD::LOAD: { 4434 LoadSDNode *LD = cast<LoadSDNode>(Node); 4435 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4436 ? ISD::EXTLOAD : LD->getExtensionType(); 4437 Result = DAG.getExtLoad(ExtType, NVT, 4438 LD->getChain(), LD->getBasePtr(), 4439 LD->getSrcValue(), LD->getSrcValueOffset(), 4440 LD->getMemoryVT(), 4441 LD->isVolatile(), 4442 LD->getAlignment()); 4443 // Remember that we legalized the chain. 4444 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4445 break; 4446 } 4447 case ISD::SELECT: { 4448 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4449 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4450 4451 MVT VT2 = Tmp2.getValueType(); 4452 assert(VT2 == Tmp3.getValueType() 4453 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); 4454 // Ensure that the resulting node is at least the same size as the operands' 4455 // value types, because we cannot assume that TLI.getSetCCValueType() is 4456 // constant. 4457 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3); 4458 break; 4459 } 4460 case ISD::SELECT_CC: 4461 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4462 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4463 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4464 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4465 break; 4466 case ISD::BSWAP: 4467 Tmp1 = Node->getOperand(0); 4468 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4469 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4470 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4471 DAG.getConstant(NVT.getSizeInBits() - 4472 VT.getSizeInBits(), 4473 TLI.getShiftAmountTy())); 4474 break; 4475 case ISD::CTPOP: 4476 case ISD::CTTZ: 4477 case ISD::CTLZ: 4478 // Zero extend the argument 4479 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4480 // Perform the larger operation, then subtract if needed. 4481 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4482 switch(Node->getOpcode()) { 4483 case ISD::CTPOP: 4484 Result = Tmp1; 4485 break; 4486 case ISD::CTTZ: 4487 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4488 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 4489 DAG.getConstant(NVT.getSizeInBits(), NVT), 4490 ISD::SETEQ); 4491 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4492 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); 4493 break; 4494 case ISD::CTLZ: 4495 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4496 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4497 DAG.getConstant(NVT.getSizeInBits() - 4498 VT.getSizeInBits(), NVT)); 4499 break; 4500 } 4501 break; 4502 case ISD::EXTRACT_SUBVECTOR: 4503 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4504 break; 4505 case ISD::EXTRACT_VECTOR_ELT: 4506 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4507 break; 4508 } 4509 4510 assert(Result.getNode() && "Didn't set a result!"); 4511 4512 // Make sure the result is itself legal. 4513 Result = LegalizeOp(Result); 4514 4515 // Remember that we promoted this! 4516 AddPromotedOperand(Op, Result); 4517 return Result; 4518} 4519 4520/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4521/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4522/// based on the vector type. The return type of this matches the element type 4523/// of the vector, which may not be legal for the target. 4524SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) { 4525 // We know that operand #0 is the Vec vector. If the index is a constant 4526 // or if the invec is a supported hardware type, we can use it. Otherwise, 4527 // lower to a store then an indexed load. 4528 SDValue Vec = Op.getOperand(0); 4529 SDValue Idx = Op.getOperand(1); 4530 4531 MVT TVT = Vec.getValueType(); 4532 unsigned NumElems = TVT.getVectorNumElements(); 4533 4534 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4535 default: assert(0 && "This action is not supported yet!"); 4536 case TargetLowering::Custom: { 4537 Vec = LegalizeOp(Vec); 4538 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4539 SDValue Tmp3 = TLI.LowerOperation(Op, DAG); 4540 if (Tmp3.getNode()) 4541 return Tmp3; 4542 break; 4543 } 4544 case TargetLowering::Legal: 4545 if (isTypeLegal(TVT)) { 4546 Vec = LegalizeOp(Vec); 4547 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4548 return Op; 4549 } 4550 break; 4551 case TargetLowering::Expand: 4552 break; 4553 } 4554 4555 if (NumElems == 1) { 4556 // This must be an access of the only element. Return it. 4557 Op = ScalarizeVectorOp(Vec); 4558 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4559 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 4560 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4561 SDValue Lo, Hi; 4562 SplitVectorOp(Vec, Lo, Hi); 4563 if (CIdx->getZExtValue() < NumLoElts) { 4564 Vec = Lo; 4565 } else { 4566 Vec = Hi; 4567 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts, 4568 Idx.getValueType()); 4569 } 4570 4571 // It's now an extract from the appropriate high or low part. Recurse. 4572 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4573 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4574 } else { 4575 // Store the value to a temporary stack slot, then LOAD the scalar 4576 // element back out. 4577 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4578 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4579 4580 // Add the offset to the index. 4581 unsigned EltSize = Op.getValueType().getSizeInBits()/8; 4582 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4583 DAG.getConstant(EltSize, Idx.getValueType())); 4584 4585 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 4586 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4587 else 4588 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4589 4590 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4591 4592 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4593 } 4594 return Op; 4595} 4596 4597/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4598/// we assume the operation can be split if it is not already legal. 4599SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) { 4600 // We know that operand #0 is the Vec vector. For now we assume the index 4601 // is a constant and that the extracted result is a supported hardware type. 4602 SDValue Vec = Op.getOperand(0); 4603 SDValue Idx = LegalizeOp(Op.getOperand(1)); 4604 4605 unsigned NumElems = Vec.getValueType().getVectorNumElements(); 4606 4607 if (NumElems == Op.getValueType().getVectorNumElements()) { 4608 // This must be an access of the desired vector length. Return it. 4609 return Vec; 4610 } 4611 4612 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4613 SDValue Lo, Hi; 4614 SplitVectorOp(Vec, Lo, Hi); 4615 if (CIdx->getZExtValue() < NumElems/2) { 4616 Vec = Lo; 4617 } else { 4618 Vec = Hi; 4619 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2, 4620 Idx.getValueType()); 4621 } 4622 4623 // It's now an extract from the appropriate high or low part. Recurse. 4624 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4625 return ExpandEXTRACT_SUBVECTOR(Op); 4626} 4627 4628/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4629/// with condition CC on the current target. This usually involves legalizing 4630/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4631/// there may be no choice but to create a new SetCC node to represent the 4632/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4633/// LHS, and the SDValue returned in RHS has a nil SDNode value. 4634void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS, 4635 SDValue &RHS, 4636 SDValue &CC) { 4637 SDValue Tmp1, Tmp2, Tmp3, Result; 4638 4639 switch (getTypeAction(LHS.getValueType())) { 4640 case Legal: 4641 Tmp1 = LegalizeOp(LHS); // LHS 4642 Tmp2 = LegalizeOp(RHS); // RHS 4643 break; 4644 case Promote: 4645 Tmp1 = PromoteOp(LHS); // LHS 4646 Tmp2 = PromoteOp(RHS); // RHS 4647 4648 // If this is an FP compare, the operands have already been extended. 4649 if (LHS.getValueType().isInteger()) { 4650 MVT VT = LHS.getValueType(); 4651 MVT NVT = TLI.getTypeToTransformTo(VT); 4652 4653 // Otherwise, we have to insert explicit sign or zero extends. Note 4654 // that we could insert sign extends for ALL conditions, but zero extend 4655 // is cheaper on many machines (an AND instead of two shifts), so prefer 4656 // it. 4657 switch (cast<CondCodeSDNode>(CC)->get()) { 4658 default: assert(0 && "Unknown integer comparison!"); 4659 case ISD::SETEQ: 4660 case ISD::SETNE: 4661 case ISD::SETUGE: 4662 case ISD::SETUGT: 4663 case ISD::SETULE: 4664 case ISD::SETULT: 4665 // ALL of these operations will work if we either sign or zero extend 4666 // the operands (including the unsigned comparisons!). Zero extend is 4667 // usually a simpler/cheaper operation, so prefer it. 4668 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4669 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4670 break; 4671 case ISD::SETGE: 4672 case ISD::SETGT: 4673 case ISD::SETLT: 4674 case ISD::SETLE: 4675 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4676 DAG.getValueType(VT)); 4677 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4678 DAG.getValueType(VT)); 4679 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes. 4680 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes. 4681 break; 4682 } 4683 } 4684 break; 4685 case Expand: { 4686 MVT VT = LHS.getValueType(); 4687 if (VT == MVT::f32 || VT == MVT::f64) { 4688 // Expand into one or more soft-fp libcall(s). 4689 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; 4690 switch (cast<CondCodeSDNode>(CC)->get()) { 4691 case ISD::SETEQ: 4692 case ISD::SETOEQ: 4693 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4694 break; 4695 case ISD::SETNE: 4696 case ISD::SETUNE: 4697 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4698 break; 4699 case ISD::SETGE: 4700 case ISD::SETOGE: 4701 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4702 break; 4703 case ISD::SETLT: 4704 case ISD::SETOLT: 4705 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4706 break; 4707 case ISD::SETLE: 4708 case ISD::SETOLE: 4709 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4710 break; 4711 case ISD::SETGT: 4712 case ISD::SETOGT: 4713 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4714 break; 4715 case ISD::SETUO: 4716 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4717 break; 4718 case ISD::SETO: 4719 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4720 break; 4721 default: 4722 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4723 switch (cast<CondCodeSDNode>(CC)->get()) { 4724 case ISD::SETONE: 4725 // SETONE = SETOLT | SETOGT 4726 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4727 // Fallthrough 4728 case ISD::SETUGT: 4729 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4730 break; 4731 case ISD::SETUGE: 4732 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4733 break; 4734 case ISD::SETULT: 4735 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4736 break; 4737 case ISD::SETULE: 4738 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4739 break; 4740 case ISD::SETUEQ: 4741 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4742 break; 4743 default: assert(0 && "Unsupported FP setcc!"); 4744 } 4745 } 4746 4747 SDValue Dummy; 4748 SDValue Ops[2] = { LHS, RHS }; 4749 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(), 4750 false /*sign irrelevant*/, Dummy); 4751 Tmp2 = DAG.getConstant(0, MVT::i32); 4752 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4753 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4754 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 4755 CC); 4756 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(), 4757 false /*sign irrelevant*/, Dummy); 4758 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2, 4759 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4760 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4761 Tmp2 = SDValue(); 4762 } 4763 LHS = LegalizeOp(Tmp1); 4764 RHS = Tmp2; 4765 return; 4766 } 4767 4768 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 4769 ExpandOp(LHS, LHSLo, LHSHi); 4770 ExpandOp(RHS, RHSLo, RHSHi); 4771 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4772 4773 if (VT==MVT::ppcf128) { 4774 // FIXME: This generated code sucks. We want to generate 4775 // FCMPU crN, hi1, hi2 4776 // BNE crN, L: 4777 // FCMPU crN, lo1, lo2 4778 // The following can be improved, but not that much. 4779 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4780 ISD::SETOEQ); 4781 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode); 4782 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4783 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4784 ISD::SETUNE); 4785 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode); 4786 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4787 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4788 Tmp2 = SDValue(); 4789 break; 4790 } 4791 4792 switch (CCCode) { 4793 case ISD::SETEQ: 4794 case ISD::SETNE: 4795 if (RHSLo == RHSHi) 4796 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4797 if (RHSCST->isAllOnesValue()) { 4798 // Comparison to -1. 4799 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4800 Tmp2 = RHSLo; 4801 break; 4802 } 4803 4804 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4805 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4806 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4807 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4808 break; 4809 default: 4810 // If this is a comparison of the sign bit, just look at the top part. 4811 // X > -1, x < 0 4812 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4813 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4814 CST->isNullValue()) || // X < 0 4815 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4816 CST->isAllOnesValue())) { // X > -1 4817 Tmp1 = LHSHi; 4818 Tmp2 = RHSHi; 4819 break; 4820 } 4821 4822 // FIXME: This generated code sucks. 4823 ISD::CondCode LowCC; 4824 switch (CCCode) { 4825 default: assert(0 && "Unknown integer setcc!"); 4826 case ISD::SETLT: 4827 case ISD::SETULT: LowCC = ISD::SETULT; break; 4828 case ISD::SETGT: 4829 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4830 case ISD::SETLE: 4831 case ISD::SETULE: LowCC = ISD::SETULE; break; 4832 case ISD::SETGE: 4833 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4834 } 4835 4836 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4837 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4838 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4839 4840 // NOTE: on targets without efficient SELECT of bools, we can always use 4841 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4842 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4843 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, 4844 LowCC, false, DagCombineInfo); 4845 if (!Tmp1.getNode()) 4846 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 4847 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4848 CCCode, false, DagCombineInfo); 4849 if (!Tmp2.getNode()) 4850 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, 4851 RHSHi,CC); 4852 4853 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 4854 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 4855 if ((Tmp1C && Tmp1C->isNullValue()) || 4856 (Tmp2C && Tmp2C->isNullValue() && 4857 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4858 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4859 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 4860 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4861 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4862 // low part is known false, returns high part. 4863 // For LE / GE, if high part is known false, ignore the low part. 4864 // For LT / GT, if high part is known true, ignore the low part. 4865 Tmp1 = Tmp2; 4866 Tmp2 = SDValue(); 4867 } else { 4868 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4869 ISD::SETEQ, false, DagCombineInfo); 4870 if (!Result.getNode()) 4871 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4872 ISD::SETEQ); 4873 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4874 Result, Tmp1, Tmp2)); 4875 Tmp1 = Result; 4876 Tmp2 = SDValue(); 4877 } 4878 } 4879 } 4880 } 4881 LHS = Tmp1; 4882 RHS = Tmp2; 4883} 4884 4885/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 4886/// condition code CC on the current target. This routine assumes LHS and rHS 4887/// have already been legalized by LegalizeSetCCOperands. It expands SETCC with 4888/// illegal condition code into AND / OR of multiple SETCC values. 4889void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, 4890 SDValue &LHS, SDValue &RHS, 4891 SDValue &CC) { 4892 MVT OpVT = LHS.getValueType(); 4893 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4894 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 4895 default: assert(0 && "Unknown condition code action!"); 4896 case TargetLowering::Legal: 4897 // Nothing to do. 4898 break; 4899 case TargetLowering::Expand: { 4900 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 4901 unsigned Opc = 0; 4902 switch (CCCode) { 4903 default: assert(0 && "Don't know how to expand this condition!"); abort(); 4904 case ISD::SETOEQ: CC1 = ISD::SETO; CC2 = ISD::SETEQ; Opc = ISD::AND; break; 4905 case ISD::SETOGT: CC1 = ISD::SETO; CC2 = ISD::SETGT; Opc = ISD::AND; break; 4906 case ISD::SETOGE: CC1 = ISD::SETO; CC2 = ISD::SETGE; Opc = ISD::AND; break; 4907 case ISD::SETOLT: CC1 = ISD::SETO; CC2 = ISD::SETLT; Opc = ISD::AND; break; 4908 case ISD::SETOLE: CC1 = ISD::SETO; CC2 = ISD::SETLE; Opc = ISD::AND; break; 4909 case ISD::SETONE: CC1 = ISD::SETO; CC2 = ISD::SETNE; Opc = ISD::AND; break; 4910 case ISD::SETUEQ: CC1 = ISD::SETUO; CC2 = ISD::SETEQ; Opc = ISD::OR; break; 4911 case ISD::SETUGT: CC1 = ISD::SETUO; CC2 = ISD::SETGT; Opc = ISD::OR; break; 4912 case ISD::SETUGE: CC1 = ISD::SETUO; CC2 = ISD::SETGE; Opc = ISD::OR; break; 4913 case ISD::SETULT: CC1 = ISD::SETUO; CC2 = ISD::SETLT; Opc = ISD::OR; break; 4914 case ISD::SETULE: CC1 = ISD::SETUO; CC2 = ISD::SETLE; Opc = ISD::OR; break; 4915 case ISD::SETUNE: CC1 = ISD::SETUO; CC2 = ISD::SETNE; Opc = ISD::OR; break; 4916 // FIXME: Implement more expansions. 4917 } 4918 4919 SDValue SetCC1 = DAG.getSetCC(VT, LHS, RHS, CC1); 4920 SDValue SetCC2 = DAG.getSetCC(VT, LHS, RHS, CC2); 4921 LHS = DAG.getNode(Opc, VT, SetCC1, SetCC2); 4922 RHS = SDValue(); 4923 CC = SDValue(); 4924 break; 4925 } 4926 } 4927} 4928 4929/// EmitStackConvert - Emit a store/load combination to the stack. This stores 4930/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 4931/// a load from the stack slot to DestVT, extending it if needed. 4932/// The resultant code need not be legal. 4933SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 4934 MVT SlotVT, 4935 MVT DestVT) { 4936 // Create the stack frame object. 4937 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment( 4938 SrcOp.getValueType().getTypeForMVT()); 4939 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 4940 4941 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 4942 int SPFI = StackPtrFI->getIndex(); 4943 4944 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 4945 unsigned SlotSize = SlotVT.getSizeInBits(); 4946 unsigned DestSize = DestVT.getSizeInBits(); 4947 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment( 4948 DestVT.getTypeForMVT()); 4949 4950 // Emit a store to the stack slot. Use a truncstore if the input value is 4951 // later than DestVT. 4952 SDValue Store; 4953 4954 if (SrcSize > SlotSize) 4955 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, 4956 PseudoSourceValue::getFixedStack(SPFI), 0, 4957 SlotVT, false, SrcAlign); 4958 else { 4959 assert(SrcSize == SlotSize && "Invalid store"); 4960 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, 4961 PseudoSourceValue::getFixedStack(SPFI), 0, 4962 false, SrcAlign); 4963 } 4964 4965 // Result is a load from the stack slot. 4966 if (SlotSize == DestSize) 4967 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign); 4968 4969 assert(SlotSize < DestSize && "Unknown extension!"); 4970 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT, 4971 false, DestAlign); 4972} 4973 4974SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4975 // Create a vector sized/aligned stack slot, store the value to element #0, 4976 // then load the whole vector back out. 4977 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4978 4979 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 4980 int SPFI = StackPtrFI->getIndex(); 4981 4982 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4983 PseudoSourceValue::getFixedStack(SPFI), 0); 4984 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, 4985 PseudoSourceValue::getFixedStack(SPFI), 0); 4986} 4987 4988 4989/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4990/// support the operation, but do support the resultant vector type. 4991SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4992 4993 // If the only non-undef value is the low element, turn this into a 4994 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4995 unsigned NumElems = Node->getNumOperands(); 4996 bool isOnlyLowElement = true; 4997 SDValue SplatValue = Node->getOperand(0); 4998 4999 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t> 5000 // and use a bitmask instead of a list of elements. 5001 std::map<SDValue, std::vector<unsigned> > Values; 5002 Values[SplatValue].push_back(0); 5003 bool isConstant = true; 5004 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 5005 SplatValue.getOpcode() != ISD::UNDEF) 5006 isConstant = false; 5007 5008 for (unsigned i = 1; i < NumElems; ++i) { 5009 SDValue V = Node->getOperand(i); 5010 Values[V].push_back(i); 5011 if (V.getOpcode() != ISD::UNDEF) 5012 isOnlyLowElement = false; 5013 if (SplatValue != V) 5014 SplatValue = SDValue(0,0); 5015 5016 // If this isn't a constant element or an undef, we can't use a constant 5017 // pool load. 5018 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 5019 V.getOpcode() != ISD::UNDEF) 5020 isConstant = false; 5021 } 5022 5023 if (isOnlyLowElement) { 5024 // If the low element is an undef too, then this whole things is an undef. 5025 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 5026 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 5027 // Otherwise, turn this into a scalar_to_vector node. 5028 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 5029 Node->getOperand(0)); 5030 } 5031 5032 // If all elements are constants, create a load from the constant pool. 5033 if (isConstant) { 5034 MVT VT = Node->getValueType(0); 5035 std::vector<Constant*> CV; 5036 for (unsigned i = 0, e = NumElems; i != e; ++i) { 5037 if (ConstantFPSDNode *V = 5038 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 5039 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 5040 } else if (ConstantSDNode *V = 5041 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 5042 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 5043 } else { 5044 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 5045 const Type *OpNTy = 5046 Node->getOperand(0).getValueType().getTypeForMVT(); 5047 CV.push_back(UndefValue::get(OpNTy)); 5048 } 5049 } 5050 Constant *CP = ConstantVector::get(CV); 5051 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 5052 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5053 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 5054 PseudoSourceValue::getConstantPool(), 0, 5055 false, Alignment); 5056 } 5057 5058 if (SplatValue.getNode()) { // Splat of one value? 5059 // Build the shuffle constant vector: <0, 0, 0, 0> 5060 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5061 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); 5062 std::vector<SDValue> ZeroVec(NumElems, Zero); 5063 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5064 &ZeroVec[0], ZeroVec.size()); 5065 5066 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 5067 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 5068 // Get the splatted value into the low element of a vector register. 5069 SDValue LowValVec = 5070 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 5071 5072 // Return shuffle(LowValVec, undef, <0,0,0,0>) 5073 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 5074 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 5075 SplatMask); 5076 } 5077 } 5078 5079 // If there are only two unique elements, we may be able to turn this into a 5080 // vector shuffle. 5081 if (Values.size() == 2) { 5082 // Get the two values in deterministic order. 5083 SDValue Val1 = Node->getOperand(1); 5084 SDValue Val2; 5085 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin(); 5086 if (MI->first != Val1) 5087 Val2 = MI->first; 5088 else 5089 Val2 = (++MI)->first; 5090 5091 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our 5092 // vector shuffle has the undef vector on the RHS. 5093 if (Val1.getOpcode() == ISD::UNDEF) 5094 std::swap(Val1, Val2); 5095 5096 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 5097 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5098 MVT MaskEltVT = MaskVT.getVectorElementType(); 5099 std::vector<SDValue> MaskVec(NumElems); 5100 5101 // Set elements of the shuffle mask for Val1. 5102 std::vector<unsigned> &Val1Elts = Values[Val1]; 5103 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 5104 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT); 5105 5106 // Set elements of the shuffle mask for Val2. 5107 std::vector<unsigned> &Val2Elts = Values[Val2]; 5108 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 5109 if (Val2.getOpcode() != ISD::UNDEF) 5110 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); 5111 else 5112 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); 5113 5114 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5115 &MaskVec[0], MaskVec.size()); 5116 5117 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 5118 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 5119 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 5120 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); 5121 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); 5122 SDValue Ops[] = { Val1, Val2, ShuffleMask }; 5123 5124 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 5125 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); 5126 } 5127 } 5128 5129 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5130 // aligned object on the stack, store each element into it, then load 5131 // the result as a vector. 5132 MVT VT = Node->getValueType(0); 5133 // Create the stack frame object. 5134 SDValue FIPtr = DAG.CreateStackTemporary(VT); 5135 5136 // Emit a store of each element to the stack slot. 5137 SmallVector<SDValue, 8> Stores; 5138 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8; 5139 // Store (in the right endianness) the elements to memory. 5140 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5141 // Ignore undef elements. 5142 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5143 5144 unsigned Offset = TypeByteSize*i; 5145 5146 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5147 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 5148 5149 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 5150 NULL, 0)); 5151 } 5152 5153 SDValue StoreChain; 5154 if (!Stores.empty()) // Not all undef elements? 5155 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5156 &Stores[0], Stores.size()); 5157 else 5158 StoreChain = DAG.getEntryNode(); 5159 5160 // Result is a load from the stack slot. 5161 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 5162} 5163 5164void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5165 SDValue Op, SDValue Amt, 5166 SDValue &Lo, SDValue &Hi) { 5167 // Expand the subcomponents. 5168 SDValue LHSL, LHSH; 5169 ExpandOp(Op, LHSL, LHSH); 5170 5171 SDValue Ops[] = { LHSL, LHSH, Amt }; 5172 MVT VT = LHSL.getValueType(); 5173 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5174 Hi = Lo.getValue(1); 5175} 5176 5177 5178/// ExpandShift - Try to find a clever way to expand this shift operation out to 5179/// smaller elements. If we can't find a way that is more efficient than a 5180/// libcall on this target, return false. Otherwise, return true with the 5181/// low-parts expanded into Lo and Hi. 5182bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, 5183 SDValue &Lo, SDValue &Hi) { 5184 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5185 "This is not a shift!"); 5186 5187 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5188 SDValue ShAmt = LegalizeOp(Amt); 5189 MVT ShTy = ShAmt.getValueType(); 5190 unsigned ShBits = ShTy.getSizeInBits(); 5191 unsigned VTBits = Op.getValueType().getSizeInBits(); 5192 unsigned NVTBits = NVT.getSizeInBits(); 5193 5194 // Handle the case when Amt is an immediate. 5195 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) { 5196 unsigned Cst = CN->getZExtValue(); 5197 // Expand the incoming operand to be shifted, so that we have its parts 5198 SDValue InL, InH; 5199 ExpandOp(Op, InL, InH); 5200 switch(Opc) { 5201 case ISD::SHL: 5202 if (Cst > VTBits) { 5203 Lo = DAG.getConstant(0, NVT); 5204 Hi = DAG.getConstant(0, NVT); 5205 } else if (Cst > NVTBits) { 5206 Lo = DAG.getConstant(0, NVT); 5207 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5208 } else if (Cst == NVTBits) { 5209 Lo = DAG.getConstant(0, NVT); 5210 Hi = InL; 5211 } else { 5212 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 5213 Hi = DAG.getNode(ISD::OR, NVT, 5214 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 5215 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 5216 } 5217 return true; 5218 case ISD::SRL: 5219 if (Cst > VTBits) { 5220 Lo = DAG.getConstant(0, NVT); 5221 Hi = DAG.getConstant(0, NVT); 5222 } else if (Cst > NVTBits) { 5223 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5224 Hi = DAG.getConstant(0, NVT); 5225 } else if (Cst == NVTBits) { 5226 Lo = InH; 5227 Hi = DAG.getConstant(0, NVT); 5228 } else { 5229 Lo = DAG.getNode(ISD::OR, NVT, 5230 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5231 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5232 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 5233 } 5234 return true; 5235 case ISD::SRA: 5236 if (Cst > VTBits) { 5237 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 5238 DAG.getConstant(NVTBits-1, ShTy)); 5239 } else if (Cst > NVTBits) { 5240 Lo = DAG.getNode(ISD::SRA, NVT, InH, 5241 DAG.getConstant(Cst-NVTBits, ShTy)); 5242 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5243 DAG.getConstant(NVTBits-1, ShTy)); 5244 } else if (Cst == NVTBits) { 5245 Lo = InH; 5246 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5247 DAG.getConstant(NVTBits-1, ShTy)); 5248 } else { 5249 Lo = DAG.getNode(ISD::OR, NVT, 5250 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5251 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5252 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 5253 } 5254 return true; 5255 } 5256 } 5257 5258 // Okay, the shift amount isn't constant. However, if we can tell that it is 5259 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5260 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5261 APInt KnownZero, KnownOne; 5262 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5263 5264 // If we know that if any of the high bits of the shift amount are one, then 5265 // we can do this as a couple of simple shifts. 5266 if (KnownOne.intersects(Mask)) { 5267 // Mask out the high bit, which we know is set. 5268 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 5269 DAG.getConstant(~Mask, Amt.getValueType())); 5270 5271 // Expand the incoming operand to be shifted, so that we have its parts 5272 SDValue InL, InH; 5273 ExpandOp(Op, InL, InH); 5274 switch(Opc) { 5275 case ISD::SHL: 5276 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5277 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 5278 return true; 5279 case ISD::SRL: 5280 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5281 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 5282 return true; 5283 case ISD::SRA: 5284 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 5285 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5286 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 5287 return true; 5288 } 5289 } 5290 5291 // If we know that the high bits of the shift amount are all zero, then we can 5292 // do this as a couple of simple shifts. 5293 if ((KnownZero & Mask) == Mask) { 5294 // Compute 32-amt. 5295 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 5296 DAG.getConstant(NVTBits, Amt.getValueType()), 5297 Amt); 5298 5299 // Expand the incoming operand to be shifted, so that we have its parts 5300 SDValue InL, InH; 5301 ExpandOp(Op, InL, InH); 5302 switch(Opc) { 5303 case ISD::SHL: 5304 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 5305 Hi = DAG.getNode(ISD::OR, NVT, 5306 DAG.getNode(ISD::SHL, NVT, InH, Amt), 5307 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 5308 return true; 5309 case ISD::SRL: 5310 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 5311 Lo = DAG.getNode(ISD::OR, NVT, 5312 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5313 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5314 return true; 5315 case ISD::SRA: 5316 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 5317 Lo = DAG.getNode(ISD::OR, NVT, 5318 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5319 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5320 return true; 5321 } 5322 } 5323 5324 return false; 5325} 5326 5327 5328// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5329// does not fit into a register, return the lo part and set the hi part to the 5330// by-reg argument. If it does fit into a single register, return the result 5331// and leave the Hi part unset. 5332SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 5333 bool isSigned, SDValue &Hi) { 5334 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5335 // The input chain to this libcall is the entry node of the function. 5336 // Legalizing the call will automatically add the previous call to the 5337 // dependence. 5338 SDValue InChain = DAG.getEntryNode(); 5339 5340 TargetLowering::ArgListTy Args; 5341 TargetLowering::ArgListEntry Entry; 5342 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5343 MVT ArgVT = Node->getOperand(i).getValueType(); 5344 const Type *ArgTy = ArgVT.getTypeForMVT(); 5345 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5346 Entry.isSExt = isSigned; 5347 Entry.isZExt = !isSigned; 5348 Args.push_back(Entry); 5349 } 5350 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 5351 TLI.getPointerTy()); 5352 5353 // Splice the libcall in wherever FindInputOutputChains tells us to. 5354 const Type *RetTy = Node->getValueType(0).getTypeForMVT(); 5355 std::pair<SDValue,SDValue> CallInfo = 5356 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 5357 CallingConv::C, false, Callee, Args, DAG); 5358 5359 // Legalize the call sequence, starting with the chain. This will advance 5360 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5361 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5362 LegalizeOp(CallInfo.second); 5363 SDValue Result; 5364 switch (getTypeAction(CallInfo.first.getValueType())) { 5365 default: assert(0 && "Unknown thing"); 5366 case Legal: 5367 Result = CallInfo.first; 5368 break; 5369 case Expand: 5370 ExpandOp(CallInfo.first, Result, Hi); 5371 break; 5372 } 5373 return Result; 5374} 5375 5376/// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation. 5377/// 5378SDValue SelectionDAGLegalize:: 5379LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) { 5380 bool isCustom = false; 5381 SDValue Tmp1; 5382 switch (getTypeAction(Op.getValueType())) { 5383 case Legal: 5384 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5385 Op.getValueType())) { 5386 default: assert(0 && "Unknown operation action!"); 5387 case TargetLowering::Custom: 5388 isCustom = true; 5389 // FALLTHROUGH 5390 case TargetLowering::Legal: 5391 Tmp1 = LegalizeOp(Op); 5392 if (Result.getNode()) 5393 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5394 else 5395 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5396 DestTy, Tmp1); 5397 if (isCustom) { 5398 Tmp1 = TLI.LowerOperation(Result, DAG); 5399 if (Tmp1.getNode()) Result = Tmp1; 5400 } 5401 break; 5402 case TargetLowering::Expand: 5403 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy); 5404 break; 5405 case TargetLowering::Promote: 5406 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned); 5407 break; 5408 } 5409 break; 5410 case Expand: 5411 Result = ExpandIntToFP(isSigned, DestTy, Op); 5412 break; 5413 case Promote: 5414 Tmp1 = PromoteOp(Op); 5415 if (isSigned) { 5416 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 5417 Tmp1, DAG.getValueType(Op.getValueType())); 5418 } else { 5419 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 5420 Op.getValueType()); 5421 } 5422 if (Result.getNode()) 5423 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5424 else 5425 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5426 DestTy, Tmp1); 5427 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 5428 break; 5429 } 5430 return Result; 5431} 5432 5433/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5434/// 5435SDValue SelectionDAGLegalize:: 5436ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) { 5437 MVT SourceVT = Source.getValueType(); 5438 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5439 5440 // Expand unsupported int-to-fp vector casts by unrolling them. 5441 if (DestTy.isVector()) { 5442 if (!ExpandSource) 5443 return LegalizeOp(UnrollVectorOp(Source)); 5444 MVT DestEltTy = DestTy.getVectorElementType(); 5445 if (DestTy.getVectorNumElements() == 1) { 5446 SDValue Scalar = ScalarizeVectorOp(Source); 5447 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned, 5448 DestEltTy, Scalar); 5449 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result); 5450 } 5451 SDValue Lo, Hi; 5452 SplitVectorOp(Source, Lo, Hi); 5453 MVT SplitDestTy = MVT::getVectorVT(DestEltTy, 5454 DestTy.getVectorNumElements() / 2); 5455 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo); 5456 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi); 5457 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult, 5458 HiResult)); 5459 } 5460 5461 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. 5462 if (!isSigned && SourceVT != MVT::i32) { 5463 // The integer value loaded will be incorrectly if the 'sign bit' of the 5464 // incoming integer is set. To handle this, we dynamically test to see if 5465 // it is set, and, if so, add a fudge factor. 5466 SDValue Hi; 5467 if (ExpandSource) { 5468 SDValue Lo; 5469 ExpandOp(Source, Lo, Hi); 5470 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi); 5471 } else { 5472 // The comparison for the sign bit will use the entire operand. 5473 Hi = Source; 5474 } 5475 5476 // If this is unsigned, and not supported, first perform the conversion to 5477 // signed, then adjust the result if the sign bit is set. 5478 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source); 5479 5480 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 5481 DAG.getConstant(0, Hi.getValueType()), 5482 ISD::SETLT); 5483 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5484 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5485 SignSet, Four, Zero); 5486 uint64_t FF = 0x5f800000ULL; 5487 if (TLI.isLittleEndian()) FF <<= 32; 5488 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5489 5490 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5491 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5492 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5493 Alignment = std::min(Alignment, 4u); 5494 SDValue FudgeInReg; 5495 if (DestTy == MVT::f32) 5496 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5497 PseudoSourceValue::getConstantPool(), 0, 5498 false, Alignment); 5499 else if (DestTy.bitsGT(MVT::f32)) 5500 // FIXME: Avoid the extend by construction the right constantpool? 5501 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5502 CPIdx, 5503 PseudoSourceValue::getConstantPool(), 0, 5504 MVT::f32, false, Alignment); 5505 else 5506 assert(0 && "Unexpected conversion"); 5507 5508 MVT SCVT = SignedConv.getValueType(); 5509 if (SCVT != DestTy) { 5510 // Destination type needs to be expanded as well. The FADD now we are 5511 // constructing will be expanded into a libcall. 5512 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { 5513 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); 5514 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, 5515 SignedConv, SignedConv.getValue(1)); 5516 } 5517 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5518 } 5519 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5520 } 5521 5522 // Check to see if the target has a custom way to lower this. If so, use it. 5523 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 5524 default: assert(0 && "This action not implemented for this operation!"); 5525 case TargetLowering::Legal: 5526 case TargetLowering::Expand: 5527 break; // This case is handled below. 5528 case TargetLowering::Custom: { 5529 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5530 Source), DAG); 5531 if (NV.getNode()) 5532 return LegalizeOp(NV); 5533 break; // The target decided this was legal after all 5534 } 5535 } 5536 5537 // Expand the source, then glue it back together for the call. We must expand 5538 // the source in case it is shared (this pass of legalize must traverse it). 5539 if (ExpandSource) { 5540 SDValue SrcLo, SrcHi; 5541 ExpandOp(Source, SrcLo, SrcHi); 5542 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); 5543 } 5544 5545 RTLIB::Libcall LC = isSigned ? 5546 RTLIB::getSINTTOFP(SourceVT, DestTy) : 5547 RTLIB::getUINTTOFP(SourceVT, DestTy); 5548 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type"); 5549 5550 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5551 SDValue HiPart; 5552 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart); 5553 if (Result.getValueType() != DestTy && HiPart.getNode()) 5554 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart); 5555 return Result; 5556} 5557 5558/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5559/// INT_TO_FP operation of the specified operand when the target requests that 5560/// we expand it. At this point, we know that the result and operand types are 5561/// legal for the target. 5562SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5563 SDValue Op0, 5564 MVT DestVT) { 5565 if (Op0.getValueType() == MVT::i32) { 5566 // simple 32-bit [signed|unsigned] integer to float/double expansion 5567 5568 // Get the stack frame index of a 8 byte buffer. 5569 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 5570 5571 // word offset constant for Hi/Lo address computation 5572 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5573 // set up Hi and Lo (into buffer) address based on endian 5574 SDValue Hi = StackSlot; 5575 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5576 if (TLI.isLittleEndian()) 5577 std::swap(Hi, Lo); 5578 5579 // if signed map to unsigned space 5580 SDValue Op0Mapped; 5581 if (isSigned) { 5582 // constant used to invert sign bit (signed to unsigned mapping) 5583 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5584 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5585 } else { 5586 Op0Mapped = Op0; 5587 } 5588 // store the lo of the constructed double - based on integer input 5589 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), 5590 Op0Mapped, Lo, NULL, 0); 5591 // initial hi portion of constructed double 5592 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5593 // store the hi of the constructed double - biased exponent 5594 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5595 // load the constructed double 5596 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5597 // FP constant to bias correct the final result 5598 SDValue Bias = DAG.getConstantFP(isSigned ? 5599 BitsToDouble(0x4330000080000000ULL) 5600 : BitsToDouble(0x4330000000000000ULL), 5601 MVT::f64); 5602 // subtract the bias 5603 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5604 // final result 5605 SDValue Result; 5606 // handle final rounding 5607 if (DestVT == MVT::f64) { 5608 // do nothing 5609 Result = Sub; 5610 } else if (DestVT.bitsLT(MVT::f64)) { 5611 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 5612 DAG.getIntPtrConstant(0)); 5613 } else if (DestVT.bitsGT(MVT::f64)) { 5614 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5615 } 5616 return Result; 5617 } 5618 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5619 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5620 5621 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0, 5622 DAG.getConstant(0, Op0.getValueType()), 5623 ISD::SETLT); 5624 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5625 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5626 SignSet, Four, Zero); 5627 5628 // If the sign bit of the integer is set, the large number will be treated 5629 // as a negative number. To counteract this, the dynamic code adds an 5630 // offset depending on the data type. 5631 uint64_t FF; 5632 switch (Op0.getValueType().getSimpleVT()) { 5633 default: assert(0 && "Unsupported integer type!"); 5634 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5635 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5636 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5637 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5638 } 5639 if (TLI.isLittleEndian()) FF <<= 32; 5640 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5641 5642 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5643 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5644 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5645 Alignment = std::min(Alignment, 4u); 5646 SDValue FudgeInReg; 5647 if (DestVT == MVT::f32) 5648 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5649 PseudoSourceValue::getConstantPool(), 0, 5650 false, Alignment); 5651 else { 5652 FudgeInReg = 5653 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5654 DAG.getEntryNode(), CPIdx, 5655 PseudoSourceValue::getConstantPool(), 0, 5656 MVT::f32, false, Alignment)); 5657 } 5658 5659 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5660} 5661 5662/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5663/// *INT_TO_FP operation of the specified operand when the target requests that 5664/// we promote it. At this point, we know that the result and operand types are 5665/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5666/// operation that takes a larger input. 5667SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 5668 MVT DestVT, 5669 bool isSigned) { 5670 // First step, figure out the appropriate *INT_TO_FP operation to use. 5671 MVT NewInTy = LegalOp.getValueType(); 5672 5673 unsigned OpToUse = 0; 5674 5675 // Scan for the appropriate larger type to use. 5676 while (1) { 5677 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 5678 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 5679 5680 // If the target supports SINT_TO_FP of this type, use it. 5681 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5682 default: break; 5683 case TargetLowering::Legal: 5684 if (!TLI.isTypeLegal(NewInTy)) 5685 break; // Can't use this datatype. 5686 // FALL THROUGH. 5687 case TargetLowering::Custom: 5688 OpToUse = ISD::SINT_TO_FP; 5689 break; 5690 } 5691 if (OpToUse) break; 5692 if (isSigned) continue; 5693 5694 // If the target supports UINT_TO_FP of this type, use it. 5695 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5696 default: break; 5697 case TargetLowering::Legal: 5698 if (!TLI.isTypeLegal(NewInTy)) 5699 break; // Can't use this datatype. 5700 // FALL THROUGH. 5701 case TargetLowering::Custom: 5702 OpToUse = ISD::UINT_TO_FP; 5703 break; 5704 } 5705 if (OpToUse) break; 5706 5707 // Otherwise, try a larger type. 5708 } 5709 5710 // Okay, we found the operation and type to use. Zero extend our input to the 5711 // desired type then run the operation on it. 5712 return DAG.getNode(OpToUse, DestVT, 5713 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5714 NewInTy, LegalOp)); 5715} 5716 5717/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5718/// FP_TO_*INT operation of the specified operand when the target requests that 5719/// we promote it. At this point, we know that the result and operand types are 5720/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5721/// operation that returns a larger result. 5722SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 5723 MVT DestVT, 5724 bool isSigned) { 5725 // First step, figure out the appropriate FP_TO*INT operation to use. 5726 MVT NewOutTy = DestVT; 5727 5728 unsigned OpToUse = 0; 5729 5730 // Scan for the appropriate larger type to use. 5731 while (1) { 5732 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 5733 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 5734 5735 // If the target supports FP_TO_SINT returning this type, use it. 5736 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5737 default: break; 5738 case TargetLowering::Legal: 5739 if (!TLI.isTypeLegal(NewOutTy)) 5740 break; // Can't use this datatype. 5741 // FALL THROUGH. 5742 case TargetLowering::Custom: 5743 OpToUse = ISD::FP_TO_SINT; 5744 break; 5745 } 5746 if (OpToUse) break; 5747 5748 // If the target supports FP_TO_UINT of this type, use it. 5749 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5750 default: break; 5751 case TargetLowering::Legal: 5752 if (!TLI.isTypeLegal(NewOutTy)) 5753 break; // Can't use this datatype. 5754 // FALL THROUGH. 5755 case TargetLowering::Custom: 5756 OpToUse = ISD::FP_TO_UINT; 5757 break; 5758 } 5759 if (OpToUse) break; 5760 5761 // Otherwise, try a larger type. 5762 } 5763 5764 5765 // Okay, we found the operation and type to use. 5766 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5767 5768 // If the operation produces an invalid type, it must be custom lowered. Use 5769 // the target lowering hooks to expand it. Just keep the low part of the 5770 // expanded operation, we know that we're truncating anyway. 5771 if (getTypeAction(NewOutTy) == Expand) { 5772 Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(), DAG), 0); 5773 assert(Operation.getNode() && "Didn't return anything"); 5774 } 5775 5776 // Truncate the result of the extended FP_TO_*INT operation to the desired 5777 // size. 5778 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5779} 5780 5781/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5782/// 5783SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) { 5784 MVT VT = Op.getValueType(); 5785 MVT SHVT = TLI.getShiftAmountTy(); 5786 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5787 switch (VT.getSimpleVT()) { 5788 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5789 case MVT::i16: 5790 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5791 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5792 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5793 case MVT::i32: 5794 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5795 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5796 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5797 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5798 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5799 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5800 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5801 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5802 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5803 case MVT::i64: 5804 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5805 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5806 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5807 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5808 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5809 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5810 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5811 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5812 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5813 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5814 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5815 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5816 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5817 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5818 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5819 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5820 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5821 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5822 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5823 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5824 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5825 } 5826} 5827 5828/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5829/// 5830SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) { 5831 switch (Opc) { 5832 default: assert(0 && "Cannot expand this yet!"); 5833 case ISD::CTPOP: { 5834 static const uint64_t mask[6] = { 5835 0x5555555555555555ULL, 0x3333333333333333ULL, 5836 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5837 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5838 }; 5839 MVT VT = Op.getValueType(); 5840 MVT ShVT = TLI.getShiftAmountTy(); 5841 unsigned len = VT.getSizeInBits(); 5842 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5843 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5844 SDValue Tmp2 = DAG.getConstant(mask[i], VT); 5845 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5846 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5847 DAG.getNode(ISD::AND, VT, 5848 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5849 } 5850 return Op; 5851 } 5852 case ISD::CTLZ: { 5853 // for now, we do this: 5854 // x = x | (x >> 1); 5855 // x = x | (x >> 2); 5856 // ... 5857 // x = x | (x >>16); 5858 // x = x | (x >>32); // for 64-bit input 5859 // return popcount(~x); 5860 // 5861 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5862 MVT VT = Op.getValueType(); 5863 MVT ShVT = TLI.getShiftAmountTy(); 5864 unsigned len = VT.getSizeInBits(); 5865 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5866 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5867 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5868 } 5869 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5870 return DAG.getNode(ISD::CTPOP, VT, Op); 5871 } 5872 case ISD::CTTZ: { 5873 // for now, we use: { return popcount(~x & (x - 1)); } 5874 // unless the target has ctlz but not ctpop, in which case we use: 5875 // { return 32 - nlz(~x & (x-1)); } 5876 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5877 MVT VT = Op.getValueType(); 5878 SDValue Tmp2 = DAG.getConstant(~0ULL, VT); 5879 SDValue Tmp3 = DAG.getNode(ISD::AND, VT, 5880 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5881 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5882 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5883 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5884 TLI.isOperationLegal(ISD::CTLZ, VT)) 5885 return DAG.getNode(ISD::SUB, VT, 5886 DAG.getConstant(VT.getSizeInBits(), VT), 5887 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5888 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5889 } 5890 } 5891} 5892 5893/// ExpandOp - Expand the specified SDValue into its two component pieces 5894/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5895/// LegalizedNodes map is filled in for any results that are not expanded, the 5896/// ExpandedNodes map is filled in for any results that are expanded, and the 5897/// Lo/Hi values are returned. 5898void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){ 5899 MVT VT = Op.getValueType(); 5900 MVT NVT = TLI.getTypeToTransformTo(VT); 5901 SDNode *Node = Op.getNode(); 5902 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5903 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() || 5904 VT.isVector()) && "Cannot expand to FP value or to larger int value!"); 5905 5906 // See if we already expanded it. 5907 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I 5908 = ExpandedNodes.find(Op); 5909 if (I != ExpandedNodes.end()) { 5910 Lo = I->second.first; 5911 Hi = I->second.second; 5912 return; 5913 } 5914 5915 switch (Node->getOpcode()) { 5916 case ISD::CopyFromReg: 5917 assert(0 && "CopyFromReg must be legal!"); 5918 case ISD::FP_ROUND_INREG: 5919 if (VT == MVT::ppcf128 && 5920 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5921 TargetLowering::Custom) { 5922 SDValue SrcLo, SrcHi, Src; 5923 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5924 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5925 SDValue Result = TLI.LowerOperation( 5926 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5927 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR); 5928 Lo = Result.getNode()->getOperand(0); 5929 Hi = Result.getNode()->getOperand(1); 5930 break; 5931 } 5932 // fall through 5933 default: 5934#ifndef NDEBUG 5935 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5936#endif 5937 assert(0 && "Do not know how to expand this operator!"); 5938 abort(); 5939 case ISD::EXTRACT_ELEMENT: 5940 ExpandOp(Node->getOperand(0), Lo, Hi); 5941 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) 5942 return ExpandOp(Hi, Lo, Hi); 5943 return ExpandOp(Lo, Lo, Hi); 5944 case ISD::EXTRACT_VECTOR_ELT: 5945 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5946 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5947 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5948 return ExpandOp(Lo, Lo, Hi); 5949 case ISD::UNDEF: 5950 Lo = DAG.getNode(ISD::UNDEF, NVT); 5951 Hi = DAG.getNode(ISD::UNDEF, NVT); 5952 break; 5953 case ISD::Constant: { 5954 unsigned NVTBits = NVT.getSizeInBits(); 5955 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 5956 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 5957 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 5958 break; 5959 } 5960 case ISD::ConstantFP: { 5961 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5962 if (CFP->getValueType(0) == MVT::ppcf128) { 5963 APInt api = CFP->getValueAPF().bitcastToAPInt(); 5964 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5965 MVT::f64); 5966 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5967 MVT::f64); 5968 break; 5969 } 5970 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5971 if (getTypeAction(Lo.getValueType()) == Expand) 5972 ExpandOp(Lo, Lo, Hi); 5973 break; 5974 } 5975 case ISD::BUILD_PAIR: 5976 // Return the operands. 5977 Lo = Node->getOperand(0); 5978 Hi = Node->getOperand(1); 5979 break; 5980 5981 case ISD::MERGE_VALUES: 5982 if (Node->getNumValues() == 1) { 5983 ExpandOp(Op.getOperand(0), Lo, Hi); 5984 break; 5985 } 5986 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5987 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 && 5988 Op.getValue(1).getValueType() == MVT::Other && 5989 "unhandled MERGE_VALUES"); 5990 ExpandOp(Op.getOperand(0), Lo, Hi); 5991 // Remember that we legalized the chain. 5992 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5993 break; 5994 5995 case ISD::SIGN_EXTEND_INREG: 5996 ExpandOp(Node->getOperand(0), Lo, Hi); 5997 // sext_inreg the low part if needed. 5998 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5999 6000 // The high part gets the sign extension from the lo-part. This handles 6001 // things like sextinreg V:i64 from i8. 6002 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6003 DAG.getConstant(NVT.getSizeInBits()-1, 6004 TLI.getShiftAmountTy())); 6005 break; 6006 6007 case ISD::BSWAP: { 6008 ExpandOp(Node->getOperand(0), Lo, Hi); 6009 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 6010 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 6011 Lo = TempLo; 6012 break; 6013 } 6014 6015 case ISD::CTPOP: 6016 ExpandOp(Node->getOperand(0), Lo, Hi); 6017 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 6018 DAG.getNode(ISD::CTPOP, NVT, Lo), 6019 DAG.getNode(ISD::CTPOP, NVT, Hi)); 6020 Hi = DAG.getConstant(0, NVT); 6021 break; 6022 6023 case ISD::CTLZ: { 6024 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 6025 ExpandOp(Node->getOperand(0), Lo, Hi); 6026 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 6027 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 6028 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC, 6029 ISD::SETNE); 6030 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 6031 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 6032 6033 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 6034 Hi = DAG.getConstant(0, NVT); 6035 break; 6036 } 6037 6038 case ISD::CTTZ: { 6039 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 6040 ExpandOp(Node->getOperand(0), Lo, Hi); 6041 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 6042 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 6043 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC, 6044 ISD::SETNE); 6045 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 6046 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 6047 6048 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 6049 Hi = DAG.getConstant(0, NVT); 6050 break; 6051 } 6052 6053 case ISD::VAARG: { 6054 SDValue Ch = Node->getOperand(0); // Legalize the chain. 6055 SDValue Ptr = Node->getOperand(1); // Legalize the pointer. 6056 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 6057 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 6058 6059 // Remember that we legalized the chain. 6060 Hi = LegalizeOp(Hi); 6061 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 6062 if (TLI.isBigEndian()) 6063 std::swap(Lo, Hi); 6064 break; 6065 } 6066 6067 case ISD::LOAD: { 6068 LoadSDNode *LD = cast<LoadSDNode>(Node); 6069 SDValue Ch = LD->getChain(); // Legalize the chain. 6070 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer. 6071 ISD::LoadExtType ExtType = LD->getExtensionType(); 6072 const Value *SV = LD->getSrcValue(); 6073 int SVOffset = LD->getSrcValueOffset(); 6074 unsigned Alignment = LD->getAlignment(); 6075 bool isVolatile = LD->isVolatile(); 6076 6077 if (ExtType == ISD::NON_EXTLOAD) { 6078 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset, 6079 isVolatile, Alignment); 6080 if (VT == MVT::f32 || VT == MVT::f64) { 6081 // f32->i32 or f64->i64 one to one expansion. 6082 // Remember that we legalized the chain. 6083 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 6084 // Recursively expand the new load. 6085 if (getTypeAction(NVT) == Expand) 6086 ExpandOp(Lo, Lo, Hi); 6087 break; 6088 } 6089 6090 // Increment the pointer to the other half. 6091 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; 6092 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6093 DAG.getIntPtrConstant(IncrementSize)); 6094 SVOffset += IncrementSize; 6095 Alignment = MinAlign(Alignment, IncrementSize); 6096 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset, 6097 isVolatile, Alignment); 6098 6099 // Build a factor node to remember that this load is independent of the 6100 // other one. 6101 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6102 Hi.getValue(1)); 6103 6104 // Remember that we legalized the chain. 6105 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6106 if (TLI.isBigEndian()) 6107 std::swap(Lo, Hi); 6108 } else { 6109 MVT EVT = LD->getMemoryVT(); 6110 6111 if ((VT == MVT::f64 && EVT == MVT::f32) || 6112 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 6113 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 6114 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV, 6115 SVOffset, isVolatile, Alignment); 6116 // Remember that we legalized the chain. 6117 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1))); 6118 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 6119 break; 6120 } 6121 6122 if (EVT == NVT) 6123 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, 6124 SVOffset, isVolatile, Alignment); 6125 else 6126 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV, 6127 SVOffset, EVT, isVolatile, 6128 Alignment); 6129 6130 // Remember that we legalized the chain. 6131 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 6132 6133 if (ExtType == ISD::SEXTLOAD) { 6134 // The high part is obtained by SRA'ing all but one of the bits of the 6135 // lo part. 6136 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6137 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6138 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6139 } else if (ExtType == ISD::ZEXTLOAD) { 6140 // The high part is just a zero. 6141 Hi = DAG.getConstant(0, NVT); 6142 } else /* if (ExtType == ISD::EXTLOAD) */ { 6143 // The high part is undefined. 6144 Hi = DAG.getNode(ISD::UNDEF, NVT); 6145 } 6146 } 6147 break; 6148 } 6149 case ISD::AND: 6150 case ISD::OR: 6151 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 6152 SDValue LL, LH, RL, RH; 6153 ExpandOp(Node->getOperand(0), LL, LH); 6154 ExpandOp(Node->getOperand(1), RL, RH); 6155 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 6156 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 6157 break; 6158 } 6159 case ISD::SELECT: { 6160 SDValue LL, LH, RL, RH; 6161 ExpandOp(Node->getOperand(1), LL, LH); 6162 ExpandOp(Node->getOperand(2), RL, RH); 6163 if (getTypeAction(NVT) == Expand) 6164 NVT = TLI.getTypeToExpandTo(NVT); 6165 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 6166 if (VT != MVT::f32) 6167 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 6168 break; 6169 } 6170 case ISD::SELECT_CC: { 6171 SDValue TL, TH, FL, FH; 6172 ExpandOp(Node->getOperand(2), TL, TH); 6173 ExpandOp(Node->getOperand(3), FL, FH); 6174 if (getTypeAction(NVT) == Expand) 6175 NVT = TLI.getTypeToExpandTo(NVT); 6176 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6177 Node->getOperand(1), TL, FL, Node->getOperand(4)); 6178 if (VT != MVT::f32) 6179 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6180 Node->getOperand(1), TH, FH, Node->getOperand(4)); 6181 break; 6182 } 6183 case ISD::ANY_EXTEND: 6184 // The low part is any extension of the input (which degenerates to a copy). 6185 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 6186 // The high part is undefined. 6187 Hi = DAG.getNode(ISD::UNDEF, NVT); 6188 break; 6189 case ISD::SIGN_EXTEND: { 6190 // The low part is just a sign extension of the input (which degenerates to 6191 // a copy). 6192 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 6193 6194 // The high part is obtained by SRA'ing all but one of the bits of the lo 6195 // part. 6196 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6197 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6198 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6199 break; 6200 } 6201 case ISD::ZERO_EXTEND: 6202 // The low part is just a zero extension of the input (which degenerates to 6203 // a copy). 6204 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 6205 6206 // The high part is just a zero. 6207 Hi = DAG.getConstant(0, NVT); 6208 break; 6209 6210 case ISD::TRUNCATE: { 6211 // The input value must be larger than this value. Expand *it*. 6212 SDValue NewLo; 6213 ExpandOp(Node->getOperand(0), NewLo, Hi); 6214 6215 // The low part is now either the right size, or it is closer. If not the 6216 // right size, make an illegal truncate so we recursively expand it. 6217 if (NewLo.getValueType() != Node->getValueType(0)) 6218 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 6219 ExpandOp(NewLo, Lo, Hi); 6220 break; 6221 } 6222 6223 case ISD::BIT_CONVERT: { 6224 SDValue Tmp; 6225 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6226 // If the target wants to, allow it to lower this itself. 6227 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6228 case Expand: assert(0 && "cannot expand FP!"); 6229 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6230 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6231 } 6232 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 6233 } 6234 6235 // f32 / f64 must be expanded to i32 / i64. 6236 if (VT == MVT::f32 || VT == MVT::f64) { 6237 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6238 if (getTypeAction(NVT) == Expand) 6239 ExpandOp(Lo, Lo, Hi); 6240 break; 6241 } 6242 6243 // If source operand will be expanded to the same type as VT, i.e. 6244 // i64 <- f64, i32 <- f32, expand the source operand instead. 6245 MVT VT0 = Node->getOperand(0).getValueType(); 6246 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6247 ExpandOp(Node->getOperand(0), Lo, Hi); 6248 break; 6249 } 6250 6251 // Turn this into a load/store pair by default. 6252 if (Tmp.getNode() == 0) 6253 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 6254 6255 ExpandOp(Tmp, Lo, Hi); 6256 break; 6257 } 6258 6259 case ISD::READCYCLECOUNTER: { 6260 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6261 TargetLowering::Custom && 6262 "Must custom expand ReadCycleCounter"); 6263 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6264 assert(Tmp.getNode() && "Node must be custom expanded!"); 6265 ExpandOp(Tmp.getValue(0), Lo, Hi); 6266 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6267 LegalizeOp(Tmp.getValue(1))); 6268 break; 6269 } 6270 6271 case ISD::ATOMIC_CMP_SWAP_64: { 6272 // This operation does not need a loop. 6273 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6274 assert(Tmp.getNode() && "Node must be custom expanded!"); 6275 ExpandOp(Tmp.getValue(0), Lo, Hi); 6276 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6277 LegalizeOp(Tmp.getValue(1))); 6278 break; 6279 } 6280 6281 case ISD::ATOMIC_LOAD_ADD_64: 6282 case ISD::ATOMIC_LOAD_SUB_64: 6283 case ISD::ATOMIC_LOAD_AND_64: 6284 case ISD::ATOMIC_LOAD_OR_64: 6285 case ISD::ATOMIC_LOAD_XOR_64: 6286 case ISD::ATOMIC_LOAD_NAND_64: 6287 case ISD::ATOMIC_SWAP_64: { 6288 // These operations require a loop to be generated. We can't do that yet, 6289 // so substitute a target-dependent pseudo and expand that later. 6290 SDValue In2Lo, In2Hi, In2; 6291 ExpandOp(Op.getOperand(2), In2Lo, In2Hi); 6292 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi); 6293 AtomicSDNode* Anode = cast<AtomicSDNode>(Node); 6294 SDValue Replace = 6295 DAG.getAtomic(Op.getOpcode(), Op.getOperand(0), Op.getOperand(1), In2, 6296 Anode->getSrcValue(), Anode->getAlignment()); 6297 SDValue Result = TLI.LowerOperation(Replace, DAG); 6298 ExpandOp(Result.getValue(0), Lo, Hi); 6299 // Remember that we legalized the chain. 6300 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1))); 6301 break; 6302 } 6303 6304 // These operators cannot be expanded directly, emit them as calls to 6305 // library functions. 6306 case ISD::FP_TO_SINT: { 6307 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6308 SDValue Op; 6309 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6310 case Expand: assert(0 && "cannot expand FP!"); 6311 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6312 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6313 } 6314 6315 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 6316 6317 // Now that the custom expander is done, expand the result, which is still 6318 // VT. 6319 if (Op.getNode()) { 6320 ExpandOp(Op, Lo, Hi); 6321 break; 6322 } 6323 } 6324 6325 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(), 6326 VT); 6327 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!"); 6328 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6329 break; 6330 } 6331 6332 case ISD::FP_TO_UINT: { 6333 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6334 SDValue Op; 6335 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6336 case Expand: assert(0 && "cannot expand FP!"); 6337 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6338 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6339 } 6340 6341 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 6342 6343 // Now that the custom expander is done, expand the result. 6344 if (Op.getNode()) { 6345 ExpandOp(Op, Lo, Hi); 6346 break; 6347 } 6348 } 6349 6350 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(), 6351 VT); 6352 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 6353 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6354 break; 6355 } 6356 6357 case ISD::SHL: { 6358 // If the target wants custom lowering, do so. 6359 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6360 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6361 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 6362 Op = TLI.LowerOperation(Op, DAG); 6363 if (Op.getNode()) { 6364 // Now that the custom expander is done, expand the result, which is 6365 // still VT. 6366 ExpandOp(Op, Lo, Hi); 6367 break; 6368 } 6369 } 6370 6371 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6372 // this X << 1 as X+X. 6373 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6374 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 6375 TLI.isOperationLegal(ISD::ADDE, NVT)) { 6376 SDValue LoOps[2], HiOps[3]; 6377 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6378 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6379 LoOps[1] = LoOps[0]; 6380 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6381 6382 HiOps[1] = HiOps[0]; 6383 HiOps[2] = Lo.getValue(1); 6384 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6385 break; 6386 } 6387 } 6388 6389 // If we can emit an efficient shift operation, do so now. 6390 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6391 break; 6392 6393 // If this target supports SHL_PARTS, use it. 6394 TargetLowering::LegalizeAction Action = 6395 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6396 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6397 Action == TargetLowering::Custom) { 6398 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6399 break; 6400 } 6401 6402 // Otherwise, emit a libcall. 6403 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi); 6404 break; 6405 } 6406 6407 case ISD::SRA: { 6408 // If the target wants custom lowering, do so. 6409 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6410 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6411 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6412 Op = TLI.LowerOperation(Op, DAG); 6413 if (Op.getNode()) { 6414 // Now that the custom expander is done, expand the result, which is 6415 // still VT. 6416 ExpandOp(Op, Lo, Hi); 6417 break; 6418 } 6419 } 6420 6421 // If we can emit an efficient shift operation, do so now. 6422 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6423 break; 6424 6425 // If this target supports SRA_PARTS, use it. 6426 TargetLowering::LegalizeAction Action = 6427 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6428 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6429 Action == TargetLowering::Custom) { 6430 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6431 break; 6432 } 6433 6434 // Otherwise, emit a libcall. 6435 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi); 6436 break; 6437 } 6438 6439 case ISD::SRL: { 6440 // If the target wants custom lowering, do so. 6441 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6442 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6443 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 6444 Op = TLI.LowerOperation(Op, DAG); 6445 if (Op.getNode()) { 6446 // Now that the custom expander is done, expand the result, which is 6447 // still VT. 6448 ExpandOp(Op, Lo, Hi); 6449 break; 6450 } 6451 } 6452 6453 // If we can emit an efficient shift operation, do so now. 6454 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6455 break; 6456 6457 // If this target supports SRL_PARTS, use it. 6458 TargetLowering::LegalizeAction Action = 6459 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6460 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6461 Action == TargetLowering::Custom) { 6462 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6463 break; 6464 } 6465 6466 // Otherwise, emit a libcall. 6467 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi); 6468 break; 6469 } 6470 6471 case ISD::ADD: 6472 case ISD::SUB: { 6473 // If the target wants to custom expand this, let them. 6474 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6475 TargetLowering::Custom) { 6476 SDValue Result = TLI.LowerOperation(Op, DAG); 6477 if (Result.getNode()) { 6478 ExpandOp(Result, Lo, Hi); 6479 break; 6480 } 6481 } 6482 // Expand the subcomponents. 6483 SDValue LHSL, LHSH, RHSL, RHSH; 6484 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6485 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6486 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6487 SDValue LoOps[2], HiOps[3]; 6488 LoOps[0] = LHSL; 6489 LoOps[1] = RHSL; 6490 HiOps[0] = LHSH; 6491 HiOps[1] = RHSH; 6492 6493 //cascaded check to see if any smaller size has a a carry flag. 6494 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC; 6495 bool hasCarry = false; 6496 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) { 6497 MVT AVT = MVT::getIntegerVT(BitSize); 6498 if (TLI.isOperationLegal(OpV, AVT)) { 6499 hasCarry = true; 6500 break; 6501 } 6502 } 6503 6504 if(hasCarry) { 6505 if (Node->getOpcode() == ISD::ADD) { 6506 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6507 HiOps[2] = Lo.getValue(1); 6508 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6509 } else { 6510 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6511 HiOps[2] = Lo.getValue(1); 6512 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6513 } 6514 break; 6515 } else { 6516 if (Node->getOpcode() == ISD::ADD) { 6517 Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2); 6518 Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2); 6519 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), 6520 Lo, LoOps[0], ISD::SETULT); 6521 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1, 6522 DAG.getConstant(1, NVT), 6523 DAG.getConstant(0, NVT)); 6524 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), 6525 Lo, LoOps[1], ISD::SETULT); 6526 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2, 6527 DAG.getConstant(1, NVT), 6528 Carry1); 6529 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2); 6530 } else { 6531 Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2); 6532 Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2); 6533 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT); 6534 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp, 6535 DAG.getConstant(1, NVT), 6536 DAG.getConstant(0, NVT)); 6537 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow); 6538 } 6539 break; 6540 } 6541 } 6542 6543 case ISD::ADDC: 6544 case ISD::SUBC: { 6545 // Expand the subcomponents. 6546 SDValue LHSL, LHSH, RHSL, RHSH; 6547 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6548 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6549 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6550 SDValue LoOps[2] = { LHSL, RHSL }; 6551 SDValue HiOps[3] = { LHSH, RHSH }; 6552 6553 if (Node->getOpcode() == ISD::ADDC) { 6554 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6555 HiOps[2] = Lo.getValue(1); 6556 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6557 } else { 6558 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6559 HiOps[2] = Lo.getValue(1); 6560 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6561 } 6562 // Remember that we legalized the flag. 6563 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6564 break; 6565 } 6566 case ISD::ADDE: 6567 case ISD::SUBE: { 6568 // Expand the subcomponents. 6569 SDValue LHSL, LHSH, RHSL, RHSH; 6570 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6571 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6572 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6573 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 6574 SDValue HiOps[3] = { LHSH, RHSH }; 6575 6576 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 6577 HiOps[2] = Lo.getValue(1); 6578 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 6579 6580 // Remember that we legalized the flag. 6581 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6582 break; 6583 } 6584 case ISD::MUL: { 6585 // If the target wants to custom expand this, let them. 6586 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 6587 SDValue New = TLI.LowerOperation(Op, DAG); 6588 if (New.getNode()) { 6589 ExpandOp(New, Lo, Hi); 6590 break; 6591 } 6592 } 6593 6594 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 6595 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 6596 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 6597 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 6598 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 6599 SDValue LL, LH, RL, RH; 6600 ExpandOp(Node->getOperand(0), LL, LH); 6601 ExpandOp(Node->getOperand(1), RL, RH); 6602 unsigned OuterBitSize = Op.getValueSizeInBits(); 6603 unsigned InnerBitSize = RH.getValueSizeInBits(); 6604 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 6605 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 6606 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 6607 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 6608 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 6609 // The inputs are both zero-extended. 6610 if (HasUMUL_LOHI) { 6611 // We can emit a umul_lohi. 6612 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6613 Hi = SDValue(Lo.getNode(), 1); 6614 break; 6615 } 6616 if (HasMULHU) { 6617 // We can emit a mulhu+mul. 6618 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6619 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6620 break; 6621 } 6622 } 6623 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 6624 // The input values are both sign-extended. 6625 if (HasSMUL_LOHI) { 6626 // We can emit a smul_lohi. 6627 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6628 Hi = SDValue(Lo.getNode(), 1); 6629 break; 6630 } 6631 if (HasMULHS) { 6632 // We can emit a mulhs+mul. 6633 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6634 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6635 break; 6636 } 6637 } 6638 if (HasUMUL_LOHI) { 6639 // Lo,Hi = umul LHS, RHS. 6640 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6641 DAG.getVTList(NVT, NVT), LL, RL); 6642 Lo = UMulLOHI; 6643 Hi = UMulLOHI.getValue(1); 6644 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6645 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6646 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6647 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6648 break; 6649 } 6650 if (HasMULHU) { 6651 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6652 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6653 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6654 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6655 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6656 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6657 break; 6658 } 6659 } 6660 6661 // If nothing else, we can make a libcall. 6662 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi); 6663 break; 6664 } 6665 case ISD::SDIV: 6666 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi); 6667 break; 6668 case ISD::UDIV: 6669 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi); 6670 break; 6671 case ISD::SREM: 6672 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi); 6673 break; 6674 case ISD::UREM: 6675 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi); 6676 break; 6677 6678 case ISD::FADD: 6679 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32, 6680 RTLIB::ADD_F64, 6681 RTLIB::ADD_F80, 6682 RTLIB::ADD_PPCF128), 6683 Node, false, Hi); 6684 break; 6685 case ISD::FSUB: 6686 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32, 6687 RTLIB::SUB_F64, 6688 RTLIB::SUB_F80, 6689 RTLIB::SUB_PPCF128), 6690 Node, false, Hi); 6691 break; 6692 case ISD::FMUL: 6693 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32, 6694 RTLIB::MUL_F64, 6695 RTLIB::MUL_F80, 6696 RTLIB::MUL_PPCF128), 6697 Node, false, Hi); 6698 break; 6699 case ISD::FDIV: 6700 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32, 6701 RTLIB::DIV_F64, 6702 RTLIB::DIV_F80, 6703 RTLIB::DIV_PPCF128), 6704 Node, false, Hi); 6705 break; 6706 case ISD::FP_EXTEND: { 6707 if (VT == MVT::ppcf128) { 6708 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6709 Node->getOperand(0).getValueType()==MVT::f64); 6710 const uint64_t zero = 0; 6711 if (Node->getOperand(0).getValueType()==MVT::f32) 6712 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6713 else 6714 Hi = Node->getOperand(0); 6715 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6716 break; 6717 } 6718 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT); 6719 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!"); 6720 Lo = ExpandLibCall(LC, Node, true, Hi); 6721 break; 6722 } 6723 case ISD::FP_ROUND: { 6724 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(), 6725 VT); 6726 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!"); 6727 Lo = ExpandLibCall(LC, Node, true, Hi); 6728 break; 6729 } 6730 case ISD::FSQRT: 6731 case ISD::FSIN: 6732 case ISD::FCOS: 6733 case ISD::FLOG: 6734 case ISD::FLOG2: 6735 case ISD::FLOG10: 6736 case ISD::FEXP: 6737 case ISD::FEXP2: 6738 case ISD::FTRUNC: 6739 case ISD::FFLOOR: 6740 case ISD::FCEIL: 6741 case ISD::FRINT: 6742 case ISD::FNEARBYINT: 6743 case ISD::FPOW: 6744 case ISD::FPOWI: { 6745 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6746 switch(Node->getOpcode()) { 6747 case ISD::FSQRT: 6748 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 6749 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 6750 break; 6751 case ISD::FSIN: 6752 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 6753 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 6754 break; 6755 case ISD::FCOS: 6756 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 6757 RTLIB::COS_F80, RTLIB::COS_PPCF128); 6758 break; 6759 case ISD::FLOG: 6760 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64, 6761 RTLIB::LOG_F80, RTLIB::LOG_PPCF128); 6762 break; 6763 case ISD::FLOG2: 6764 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 6765 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128); 6766 break; 6767 case ISD::FLOG10: 6768 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 6769 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128); 6770 break; 6771 case ISD::FEXP: 6772 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64, 6773 RTLIB::EXP_F80, RTLIB::EXP_PPCF128); 6774 break; 6775 case ISD::FEXP2: 6776 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 6777 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128); 6778 break; 6779 case ISD::FTRUNC: 6780 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 6781 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 6782 break; 6783 case ISD::FFLOOR: 6784 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 6785 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 6786 break; 6787 case ISD::FCEIL: 6788 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 6789 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 6790 break; 6791 case ISD::FRINT: 6792 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 6793 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 6794 break; 6795 case ISD::FNEARBYINT: 6796 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 6797 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 6798 break; 6799 case ISD::FPOW: 6800 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 6801 RTLIB::POW_PPCF128); 6802 break; 6803 case ISD::FPOWI: 6804 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80, 6805 RTLIB::POWI_PPCF128); 6806 break; 6807 default: assert(0 && "Unreachable!"); 6808 } 6809 Lo = ExpandLibCall(LC, Node, false, Hi); 6810 break; 6811 } 6812 case ISD::FABS: { 6813 if (VT == MVT::ppcf128) { 6814 SDValue Tmp; 6815 ExpandOp(Node->getOperand(0), Lo, Tmp); 6816 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6817 // lo = hi==fabs(hi) ? lo : -lo; 6818 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6819 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6820 DAG.getCondCode(ISD::SETEQ)); 6821 break; 6822 } 6823 SDValue Mask = (VT == MVT::f64) 6824 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6825 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6826 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6827 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6828 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6829 if (getTypeAction(NVT) == Expand) 6830 ExpandOp(Lo, Lo, Hi); 6831 break; 6832 } 6833 case ISD::FNEG: { 6834 if (VT == MVT::ppcf128) { 6835 ExpandOp(Node->getOperand(0), Lo, Hi); 6836 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6837 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6838 break; 6839 } 6840 SDValue Mask = (VT == MVT::f64) 6841 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6842 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6843 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6844 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6845 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6846 if (getTypeAction(NVT) == Expand) 6847 ExpandOp(Lo, Lo, Hi); 6848 break; 6849 } 6850 case ISD::FCOPYSIGN: { 6851 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6852 if (getTypeAction(NVT) == Expand) 6853 ExpandOp(Lo, Lo, Hi); 6854 break; 6855 } 6856 case ISD::SINT_TO_FP: 6857 case ISD::UINT_TO_FP: { 6858 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6859 MVT SrcVT = Node->getOperand(0).getValueType(); 6860 6861 // Promote the operand if needed. Do this before checking for 6862 // ppcf128 so conversions of i16 and i8 work. 6863 if (getTypeAction(SrcVT) == Promote) { 6864 SDValue Tmp = PromoteOp(Node->getOperand(0)); 6865 Tmp = isSigned 6866 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6867 DAG.getValueType(SrcVT)) 6868 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6869 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode(); 6870 SrcVT = Node->getOperand(0).getValueType(); 6871 } 6872 6873 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 6874 static const uint64_t zero = 0; 6875 if (isSigned) { 6876 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6877 Node->getOperand(0))); 6878 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6879 } else { 6880 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6881 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6882 Node->getOperand(0))); 6883 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6884 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6885 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6886 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6887 DAG.getConstant(0, MVT::i32), 6888 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6889 DAG.getConstantFP( 6890 APFloat(APInt(128, 2, TwoE32)), 6891 MVT::ppcf128)), 6892 Hi, 6893 DAG.getCondCode(ISD::SETLT)), 6894 Lo, Hi); 6895 } 6896 break; 6897 } 6898 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6899 // si64->ppcf128 done by libcall, below 6900 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6901 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6902 Lo, Hi); 6903 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6904 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6905 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6906 DAG.getConstant(0, MVT::i64), 6907 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6908 DAG.getConstantFP( 6909 APFloat(APInt(128, 2, TwoE64)), 6910 MVT::ppcf128)), 6911 Hi, 6912 DAG.getCondCode(ISD::SETLT)), 6913 Lo, Hi); 6914 break; 6915 } 6916 6917 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6918 Node->getOperand(0)); 6919 if (getTypeAction(Lo.getValueType()) == Expand) 6920 // float to i32 etc. can be 'expanded' to a single node. 6921 ExpandOp(Lo, Lo, Hi); 6922 break; 6923 } 6924 } 6925 6926 // Make sure the resultant values have been legalized themselves, unless this 6927 // is a type that requires multi-step expansion. 6928 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6929 Lo = LegalizeOp(Lo); 6930 if (Hi.getNode()) 6931 // Don't legalize the high part if it is expanded to a single node. 6932 Hi = LegalizeOp(Hi); 6933 } 6934 6935 // Remember in a map if the values will be reused later. 6936 bool isNew = 6937 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 6938 assert(isNew && "Value already expanded?!?"); 6939} 6940 6941/// SplitVectorOp - Given an operand of vector type, break it down into 6942/// two smaller values, still of vector type. 6943void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo, 6944 SDValue &Hi) { 6945 assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); 6946 SDNode *Node = Op.getNode(); 6947 unsigned NumElements = Op.getValueType().getVectorNumElements(); 6948 assert(NumElements > 1 && "Cannot split a single element vector!"); 6949 6950 MVT NewEltVT = Op.getValueType().getVectorElementType(); 6951 6952 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6953 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6954 6955 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); 6956 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); 6957 6958 // See if we already split it. 6959 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I 6960 = SplitNodes.find(Op); 6961 if (I != SplitNodes.end()) { 6962 Lo = I->second.first; 6963 Hi = I->second.second; 6964 return; 6965 } 6966 6967 switch (Node->getOpcode()) { 6968 default: 6969#ifndef NDEBUG 6970 Node->dump(&DAG); 6971#endif 6972 assert(0 && "Unhandled operation in SplitVectorOp!"); 6973 case ISD::UNDEF: 6974 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6975 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6976 break; 6977 case ISD::BUILD_PAIR: 6978 Lo = Node->getOperand(0); 6979 Hi = Node->getOperand(1); 6980 break; 6981 case ISD::INSERT_VECTOR_ELT: { 6982 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 6983 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6984 unsigned Index = Idx->getZExtValue(); 6985 SDValue ScalarOp = Node->getOperand(1); 6986 if (Index < NewNumElts_Lo) 6987 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6988 DAG.getIntPtrConstant(Index)); 6989 else 6990 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6991 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 6992 break; 6993 } 6994 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), 6995 Node->getOperand(1), 6996 Node->getOperand(2)); 6997 SplitVectorOp(Tmp, Lo, Hi); 6998 break; 6999 } 7000 case ISD::VECTOR_SHUFFLE: { 7001 // Build the low part. 7002 SDValue Mask = Node->getOperand(2); 7003 SmallVector<SDValue, 8> Ops; 7004 MVT PtrVT = TLI.getPointerTy(); 7005 7006 // Insert all of the elements from the input that are needed. We use 7007 // buildvector of extractelement here because the input vectors will have 7008 // to be legalized, so this makes the code simpler. 7009 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 7010 SDValue IdxNode = Mask.getOperand(i); 7011 if (IdxNode.getOpcode() == ISD::UNDEF) { 7012 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 7013 continue; 7014 } 7015 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue(); 7016 SDValue InVec = Node->getOperand(0); 7017 if (Idx >= NumElements) { 7018 InVec = Node->getOperand(1); 7019 Idx -= NumElements; 7020 } 7021 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 7022 DAG.getConstant(Idx, PtrVT))); 7023 } 7024 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 7025 Ops.clear(); 7026 7027 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 7028 SDValue IdxNode = Mask.getOperand(i); 7029 if (IdxNode.getOpcode() == ISD::UNDEF) { 7030 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 7031 continue; 7032 } 7033 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue(); 7034 SDValue InVec = Node->getOperand(0); 7035 if (Idx >= NumElements) { 7036 InVec = Node->getOperand(1); 7037 Idx -= NumElements; 7038 } 7039 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 7040 DAG.getConstant(Idx, PtrVT))); 7041 } 7042 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size()); 7043 break; 7044 } 7045 case ISD::BUILD_VECTOR: { 7046 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 7047 Node->op_begin()+NewNumElts_Lo); 7048 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 7049 7050 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 7051 Node->op_end()); 7052 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 7053 break; 7054 } 7055 case ISD::CONCAT_VECTORS: { 7056 // FIXME: Handle non-power-of-two vectors? 7057 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 7058 if (NewNumSubvectors == 1) { 7059 Lo = Node->getOperand(0); 7060 Hi = Node->getOperand(1); 7061 } else { 7062 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 7063 Node->op_begin()+NewNumSubvectors); 7064 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 7065 7066 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors, 7067 Node->op_end()); 7068 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 7069 } 7070 break; 7071 } 7072 case ISD::SELECT: { 7073 SDValue Cond = Node->getOperand(0); 7074 7075 SDValue LL, LH, RL, RH; 7076 SplitVectorOp(Node->getOperand(1), LL, LH); 7077 SplitVectorOp(Node->getOperand(2), RL, RH); 7078 7079 if (Cond.getValueType().isVector()) { 7080 // Handle a vector merge. 7081 SDValue CL, CH; 7082 SplitVectorOp(Cond, CL, CH); 7083 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 7084 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 7085 } else { 7086 // Handle a simple select with vector operands. 7087 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 7088 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 7089 } 7090 break; 7091 } 7092 case ISD::SELECT_CC: { 7093 SDValue CondLHS = Node->getOperand(0); 7094 SDValue CondRHS = Node->getOperand(1); 7095 SDValue CondCode = Node->getOperand(4); 7096 7097 SDValue LL, LH, RL, RH; 7098 SplitVectorOp(Node->getOperand(2), LL, LH); 7099 SplitVectorOp(Node->getOperand(3), RL, RH); 7100 7101 // Handle a simple select with vector operands. 7102 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS, 7103 LL, RL, CondCode); 7104 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS, 7105 LH, RH, CondCode); 7106 break; 7107 } 7108 case ISD::VSETCC: { 7109 SDValue LL, LH, RL, RH; 7110 SplitVectorOp(Node->getOperand(0), LL, LH); 7111 SplitVectorOp(Node->getOperand(1), RL, RH); 7112 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2)); 7113 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2)); 7114 break; 7115 } 7116 case ISD::ADD: 7117 case ISD::SUB: 7118 case ISD::MUL: 7119 case ISD::FADD: 7120 case ISD::FSUB: 7121 case ISD::FMUL: 7122 case ISD::SDIV: 7123 case ISD::UDIV: 7124 case ISD::FDIV: 7125 case ISD::FPOW: 7126 case ISD::AND: 7127 case ISD::OR: 7128 case ISD::XOR: 7129 case ISD::UREM: 7130 case ISD::SREM: 7131 case ISD::FREM: { 7132 SDValue LL, LH, RL, RH; 7133 SplitVectorOp(Node->getOperand(0), LL, LH); 7134 SplitVectorOp(Node->getOperand(1), RL, RH); 7135 7136 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 7137 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 7138 break; 7139 } 7140 case ISD::FP_ROUND: 7141 case ISD::FPOWI: { 7142 SDValue L, H; 7143 SplitVectorOp(Node->getOperand(0), L, H); 7144 7145 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 7146 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 7147 break; 7148 } 7149 case ISD::CTTZ: 7150 case ISD::CTLZ: 7151 case ISD::CTPOP: 7152 case ISD::FNEG: 7153 case ISD::FABS: 7154 case ISD::FSQRT: 7155 case ISD::FSIN: 7156 case ISD::FCOS: 7157 case ISD::FLOG: 7158 case ISD::FLOG2: 7159 case ISD::FLOG10: 7160 case ISD::FEXP: 7161 case ISD::FEXP2: 7162 case ISD::FP_TO_SINT: 7163 case ISD::FP_TO_UINT: 7164 case ISD::SINT_TO_FP: 7165 case ISD::UINT_TO_FP: 7166 case ISD::TRUNCATE: 7167 case ISD::ANY_EXTEND: 7168 case ISD::SIGN_EXTEND: 7169 case ISD::ZERO_EXTEND: 7170 case ISD::FP_EXTEND: { 7171 SDValue L, H; 7172 SplitVectorOp(Node->getOperand(0), L, H); 7173 7174 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 7175 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 7176 break; 7177 } 7178 case ISD::LOAD: { 7179 LoadSDNode *LD = cast<LoadSDNode>(Node); 7180 SDValue Ch = LD->getChain(); 7181 SDValue Ptr = LD->getBasePtr(); 7182 ISD::LoadExtType ExtType = LD->getExtensionType(); 7183 const Value *SV = LD->getSrcValue(); 7184 int SVOffset = LD->getSrcValueOffset(); 7185 MVT MemoryVT = LD->getMemoryVT(); 7186 unsigned Alignment = LD->getAlignment(); 7187 bool isVolatile = LD->isVolatile(); 7188 7189 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 7190 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); 7191 7192 MVT MemNewEltVT = MemoryVT.getVectorElementType(); 7193 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo); 7194 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi); 7195 7196 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, 7197 NewVT_Lo, Ch, Ptr, Offset, 7198 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment); 7199 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8; 7200 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 7201 DAG.getIntPtrConstant(IncrementSize)); 7202 SVOffset += IncrementSize; 7203 Alignment = MinAlign(Alignment, IncrementSize); 7204 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, 7205 NewVT_Hi, Ch, Ptr, Offset, 7206 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment); 7207 7208 // Build a factor node to remember that this load is independent of the 7209 // other one. 7210 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 7211 Hi.getValue(1)); 7212 7213 // Remember that we legalized the chain. 7214 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 7215 break; 7216 } 7217 case ISD::BIT_CONVERT: { 7218 // We know the result is a vector. The input may be either a vector or a 7219 // scalar value. 7220 SDValue InOp = Node->getOperand(0); 7221 if (!InOp.getValueType().isVector() || 7222 InOp.getValueType().getVectorNumElements() == 1) { 7223 // The input is a scalar or single-element vector. 7224 // Lower to a store/load so that it can be split. 7225 // FIXME: this could be improved probably. 7226 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment( 7227 Op.getValueType().getTypeForMVT()); 7228 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign); 7229 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex(); 7230 7231 SDValue St = DAG.getStore(DAG.getEntryNode(), 7232 InOp, Ptr, 7233 PseudoSourceValue::getFixedStack(FI), 0); 7234 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, 7235 PseudoSourceValue::getFixedStack(FI), 0); 7236 } 7237 // Split the vector and convert each of the pieces now. 7238 SplitVectorOp(InOp, Lo, Hi); 7239 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 7240 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 7241 break; 7242 } 7243 } 7244 7245 // Remember in a map if the values will be reused later. 7246 bool isNew = 7247 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7248 assert(isNew && "Value already split?!?"); 7249} 7250 7251 7252/// ScalarizeVectorOp - Given an operand of single-element vector type 7253/// (e.g. v1f32), convert it into the equivalent operation that returns a 7254/// scalar (e.g. f32) value. 7255SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) { 7256 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); 7257 SDNode *Node = Op.getNode(); 7258 MVT NewVT = Op.getValueType().getVectorElementType(); 7259 assert(Op.getValueType().getVectorNumElements() == 1); 7260 7261 // See if we already scalarized it. 7262 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op); 7263 if (I != ScalarizedNodes.end()) return I->second; 7264 7265 SDValue Result; 7266 switch (Node->getOpcode()) { 7267 default: 7268#ifndef NDEBUG 7269 Node->dump(&DAG); cerr << "\n"; 7270#endif 7271 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 7272 case ISD::ADD: 7273 case ISD::FADD: 7274 case ISD::SUB: 7275 case ISD::FSUB: 7276 case ISD::MUL: 7277 case ISD::FMUL: 7278 case ISD::SDIV: 7279 case ISD::UDIV: 7280 case ISD::FDIV: 7281 case ISD::SREM: 7282 case ISD::UREM: 7283 case ISD::FREM: 7284 case ISD::FPOW: 7285 case ISD::AND: 7286 case ISD::OR: 7287 case ISD::XOR: 7288 Result = DAG.getNode(Node->getOpcode(), 7289 NewVT, 7290 ScalarizeVectorOp(Node->getOperand(0)), 7291 ScalarizeVectorOp(Node->getOperand(1))); 7292 break; 7293 case ISD::FNEG: 7294 case ISD::FABS: 7295 case ISD::FSQRT: 7296 case ISD::FSIN: 7297 case ISD::FCOS: 7298 case ISD::FLOG: 7299 case ISD::FLOG2: 7300 case ISD::FLOG10: 7301 case ISD::FEXP: 7302 case ISD::FEXP2: 7303 case ISD::FP_TO_SINT: 7304 case ISD::FP_TO_UINT: 7305 case ISD::SINT_TO_FP: 7306 case ISD::UINT_TO_FP: 7307 case ISD::SIGN_EXTEND: 7308 case ISD::ZERO_EXTEND: 7309 case ISD::ANY_EXTEND: 7310 case ISD::TRUNCATE: 7311 case ISD::FP_EXTEND: 7312 Result = DAG.getNode(Node->getOpcode(), 7313 NewVT, 7314 ScalarizeVectorOp(Node->getOperand(0))); 7315 break; 7316 case ISD::FPOWI: 7317 case ISD::FP_ROUND: 7318 Result = DAG.getNode(Node->getOpcode(), 7319 NewVT, 7320 ScalarizeVectorOp(Node->getOperand(0)), 7321 Node->getOperand(1)); 7322 break; 7323 case ISD::LOAD: { 7324 LoadSDNode *LD = cast<LoadSDNode>(Node); 7325 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 7326 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 7327 ISD::LoadExtType ExtType = LD->getExtensionType(); 7328 const Value *SV = LD->getSrcValue(); 7329 int SVOffset = LD->getSrcValueOffset(); 7330 MVT MemoryVT = LD->getMemoryVT(); 7331 unsigned Alignment = LD->getAlignment(); 7332 bool isVolatile = LD->isVolatile(); 7333 7334 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 7335 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); 7336 7337 Result = DAG.getLoad(ISD::UNINDEXED, ExtType, 7338 NewVT, Ch, Ptr, Offset, SV, SVOffset, 7339 MemoryVT.getVectorElementType(), 7340 isVolatile, Alignment); 7341 7342 // Remember that we legalized the chain. 7343 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 7344 break; 7345 } 7346 case ISD::BUILD_VECTOR: 7347 Result = Node->getOperand(0); 7348 break; 7349 case ISD::INSERT_VECTOR_ELT: 7350 // Returning the inserted scalar element. 7351 Result = Node->getOperand(1); 7352 break; 7353 case ISD::CONCAT_VECTORS: 7354 assert(Node->getOperand(0).getValueType() == NewVT && 7355 "Concat of non-legal vectors not yet supported!"); 7356 Result = Node->getOperand(0); 7357 break; 7358 case ISD::VECTOR_SHUFFLE: { 7359 // Figure out if the scalar is the LHS or RHS and return it. 7360 SDValue EltNum = Node->getOperand(2).getOperand(0); 7361 if (cast<ConstantSDNode>(EltNum)->getZExtValue()) 7362 Result = ScalarizeVectorOp(Node->getOperand(1)); 7363 else 7364 Result = ScalarizeVectorOp(Node->getOperand(0)); 7365 break; 7366 } 7367 case ISD::EXTRACT_SUBVECTOR: 7368 Result = Node->getOperand(0); 7369 assert(Result.getValueType() == NewVT); 7370 break; 7371 case ISD::BIT_CONVERT: { 7372 SDValue Op0 = Op.getOperand(0); 7373 if (Op0.getValueType().getVectorNumElements() == 1) 7374 Op0 = ScalarizeVectorOp(Op0); 7375 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0); 7376 break; 7377 } 7378 case ISD::SELECT: 7379 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 7380 ScalarizeVectorOp(Op.getOperand(1)), 7381 ScalarizeVectorOp(Op.getOperand(2))); 7382 break; 7383 case ISD::SELECT_CC: 7384 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0), 7385 Node->getOperand(1), 7386 ScalarizeVectorOp(Op.getOperand(2)), 7387 ScalarizeVectorOp(Op.getOperand(3)), 7388 Node->getOperand(4)); 7389 break; 7390 case ISD::VSETCC: { 7391 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0)); 7392 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1)); 7393 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1, 7394 Op.getOperand(2)); 7395 Result = DAG.getNode(ISD::SELECT, NewVT, Result, 7396 DAG.getConstant(-1ULL, NewVT), 7397 DAG.getConstant(0ULL, NewVT)); 7398 break; 7399 } 7400 } 7401 7402 if (TLI.isTypeLegal(NewVT)) 7403 Result = LegalizeOp(Result); 7404 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7405 assert(isNew && "Value already scalarized?"); 7406 return Result; 7407} 7408 7409 7410// SelectionDAG::Legalize - This is the entry point for the file. 7411// 7412void SelectionDAG::Legalize() { 7413 /// run - This is the main entry point to this class. 7414 /// 7415 SelectionDAGLegalize(*this).LegalizeDAG(); 7416} 7417 7418