LegalizeDAG.cpp revision 8121504200287caf76a42be5548afc82b051a7fa
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetFrameInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/Target/TargetSubtarget.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Compiler.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/ADT/DenseMap.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/SmallPtrSet.h" 35#include <map> 36using namespace llvm; 37 38//===----------------------------------------------------------------------===// 39/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 40/// hacks on it until the target machine can handle it. This involves 41/// eliminating value sizes the machine cannot handle (promoting small sizes to 42/// large sizes or splitting up large values into small values) as well as 43/// eliminating operations the machine cannot handle. 44/// 45/// This code also does a small amount of optimization and recognition of idioms 46/// as part of its processing. For example, if a target does not support a 47/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 48/// will attempt merge setcc and brc instructions into brcc's. 49/// 50namespace { 51class VISIBILITY_HIDDEN SelectionDAGLegalize { 52 TargetLowering &TLI; 53 SelectionDAG &DAG; 54 bool TypesNeedLegalizing; 55 56 // Libcall insertion helpers. 57 58 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 59 /// legalized. We use this to ensure that calls are properly serialized 60 /// against each other, including inserted libcalls. 61 SDValue LastCALLSEQ_END; 62 63 /// IsLegalizingCall - This member is used *only* for purposes of providing 64 /// helpful assertions that a libcall isn't created while another call is 65 /// being legalized (which could lead to non-serialized call sequences). 66 bool IsLegalizingCall; 67 68 enum LegalizeAction { 69 Legal, // The target natively supports this operation. 70 Promote, // This operation should be executed in a larger type. 71 Expand // Try to expand this to other ops, otherwise use a libcall. 72 }; 73 74 /// ValueTypeActions - This is a bitvector that contains two bits for each 75 /// value type, where the two bits correspond to the LegalizeAction enum. 76 /// This can be queried with "getTypeAction(VT)". 77 TargetLowering::ValueTypeActionImpl ValueTypeActions; 78 79 /// LegalizedNodes - For nodes that are of legal width, and that have more 80 /// than one use, this map indicates what regularized operand to use. This 81 /// allows us to avoid legalizing the same thing more than once. 82 DenseMap<SDValue, SDValue> LegalizedNodes; 83 84 /// PromotedNodes - For nodes that are below legal width, and that have more 85 /// than one use, this map indicates what promoted value to use. This allows 86 /// us to avoid promoting the same thing more than once. 87 DenseMap<SDValue, SDValue> PromotedNodes; 88 89 /// ExpandedNodes - For nodes that need to be expanded this map indicates 90 /// which operands are the expanded version of the input. This allows 91 /// us to avoid expanding the same node more than once. 92 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes; 93 94 /// SplitNodes - For vector nodes that need to be split, this map indicates 95 /// which operands are the split version of the input. This allows us 96 /// to avoid splitting the same node more than once. 97 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes; 98 99 /// ScalarizedNodes - For nodes that need to be converted from vector types to 100 /// scalar types, this contains the mapping of ones we have already 101 /// processed to the result. 102 std::map<SDValue, SDValue> ScalarizedNodes; 103 104 /// WidenNodes - For nodes that need to be widened from one vector type to 105 /// another, this contains the mapping of those that we have already widen. 106 /// This allows us to avoid widening more than once. 107 std::map<SDValue, SDValue> WidenNodes; 108 109 void AddLegalizedOperand(SDValue From, SDValue To) { 110 LegalizedNodes.insert(std::make_pair(From, To)); 111 // If someone requests legalization of the new node, return itself. 112 if (From != To) 113 LegalizedNodes.insert(std::make_pair(To, To)); 114 } 115 void AddPromotedOperand(SDValue From, SDValue To) { 116 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 117 assert(isNew && "Got into the map somehow?"); 118 isNew = isNew; 119 // If someone requests legalization of the new node, return itself. 120 LegalizedNodes.insert(std::make_pair(To, To)); 121 } 122 void AddWidenedOperand(SDValue From, SDValue To) { 123 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second; 124 assert(isNew && "Got into the map somehow?"); 125 isNew = isNew; 126 // If someone requests legalization of the new node, return itself. 127 LegalizedNodes.insert(std::make_pair(To, To)); 128 } 129 130public: 131 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing); 132 133 /// getTypeAction - Return how we should legalize values of this type, either 134 /// it is already legal or we need to expand it into multiple registers of 135 /// smaller integer type, or we need to promote it to a larger type. 136 LegalizeAction getTypeAction(MVT VT) const { 137 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 138 } 139 140 /// isTypeLegal - Return true if this type is legal on this target. 141 /// 142 bool isTypeLegal(MVT VT) const { 143 return getTypeAction(VT) == Legal; 144 } 145 146 void LegalizeDAG(); 147 148private: 149 /// HandleOp - Legalize, Promote, or Expand the specified operand as 150 /// appropriate for its type. 151 void HandleOp(SDValue Op); 152 153 /// LegalizeOp - We know that the specified value has a legal type. 154 /// Recursively ensure that the operands have legal types, then return the 155 /// result. 156 SDValue LegalizeOp(SDValue O); 157 158 /// UnrollVectorOp - We know that the given vector has a legal type, however 159 /// the operation it performs is not legal and is an operation that we have 160 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 161 /// operating on each element individually. 162 SDValue UnrollVectorOp(SDValue O); 163 164 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 165 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 166 /// is necessary to spill the vector being inserted into to memory, perform 167 /// the insert there, and then read the result back. 168 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 169 SDValue Idx); 170 171 /// PromoteOp - Given an operation that produces a value in an invalid type, 172 /// promote it to compute the value into a larger type. The produced value 173 /// will have the correct bits for the low portion of the register, but no 174 /// guarantee is made about the top bits: it may be zero, sign-extended, or 175 /// garbage. 176 SDValue PromoteOp(SDValue O); 177 178 /// ExpandOp - Expand the specified SDValue into its two component pieces 179 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 180 /// the LegalizedNodes map is filled in for any results that are not expanded, 181 /// the ExpandedNodes map is filled in for any results that are expanded, and 182 /// the Lo/Hi values are returned. This applies to integer types and Vector 183 /// types. 184 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi); 185 186 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT 187 /// (e.g., v3i32 to v4i32). The produced value will have the correct value 188 /// for the existing elements but no guarantee is made about the new elements 189 /// at the end of the vector: it may be zero, ones, or garbage. This is useful 190 /// when we have an instruction operating on an illegal vector type and we 191 /// want to widen it to do the computation on a legal wider vector type. 192 SDValue WidenVectorOp(SDValue Op, MVT WidenVT); 193 194 /// SplitVectorOp - Given an operand of vector type, break it down into 195 /// two smaller values. 196 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi); 197 198 /// ScalarizeVectorOp - Given an operand of single-element vector type 199 /// (e.g. v1f32), convert it into the equivalent operation that returns a 200 /// scalar (e.g. f32) value. 201 SDValue ScalarizeVectorOp(SDValue O); 202 203 /// Useful 16 element vector type that is used to pass operands for widening. 204 typedef SmallVector<SDValue, 16> SDValueVector; 205 206 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if 207 /// the LdChain contains a single load and false if it contains a token 208 /// factor for multiple loads. It takes 209 /// Result: location to return the result 210 /// LdChain: location to return the load chain 211 /// Op: load operation to widen 212 /// NVT: widen vector result type we want for the load 213 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain, 214 SDValue Op, MVT NVT); 215 216 /// Helper genWidenVectorLoads - Helper function to generate a set of 217 /// loads to load a vector with a resulting wider type. It takes 218 /// LdChain: list of chains for the load we have generated 219 /// Chain: incoming chain for the ld vector 220 /// BasePtr: base pointer to load from 221 /// SV: memory disambiguation source value 222 /// SVOffset: memory disambiugation offset 223 /// Alignment: alignment of the memory 224 /// isVolatile: volatile load 225 /// LdWidth: width of memory that we want to load 226 /// ResType: the wider result result type for the resulting loaded vector 227 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain, 228 SDValue BasePtr, const Value *SV, 229 int SVOffset, unsigned Alignment, 230 bool isVolatile, unsigned LdWidth, 231 MVT ResType); 232 233 /// StoreWidenVectorOp - Stores a widen vector into non widen memory 234 /// location. It takes 235 /// ST: store node that we want to replace 236 /// Chain: incoming store chain 237 /// BasePtr: base address of where we want to store into 238 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain, 239 SDValue BasePtr); 240 241 /// Helper genWidenVectorStores - Helper function to generate a set of 242 /// stores to store a widen vector into non widen memory 243 // It takes 244 // StChain: list of chains for the stores we have generated 245 // Chain: incoming chain for the ld vector 246 // BasePtr: base pointer to load from 247 // SV: memory disambiguation source value 248 // SVOffset: memory disambiugation offset 249 // Alignment: alignment of the memory 250 // isVolatile: volatile lod 251 // ValOp: value to store 252 // StWidth: width of memory that we want to store 253 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain, 254 SDValue BasePtr, const Value *SV, 255 int SVOffset, unsigned Alignment, 256 bool isVolatile, SDValue ValOp, 257 unsigned StWidth); 258 259 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the 260 /// specified mask and type. Targets can specify exactly which masks they 261 /// support and the code generator is tasked with not creating illegal masks. 262 /// 263 /// Note that this will also return true for shuffles that are promoted to a 264 /// different type. 265 /// 266 /// If this is a legal shuffle, this method returns the (possibly promoted) 267 /// build_vector Mask. If it's not a legal shuffle, it returns null. 268 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const; 269 270 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 271 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 272 273 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC); 274 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC); 275 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC) { 276 LegalizeSetCCOperands(LHS, RHS, CC); 277 LegalizeSetCCCondCode(VT, LHS, RHS, CC); 278 } 279 280 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, 281 SDValue &Hi); 282 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source); 283 284 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT); 285 SDValue ExpandBUILD_VECTOR(SDNode *Node); 286 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 287 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op); 288 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT); 289 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned); 290 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned); 291 292 SDValue ExpandBSWAP(SDValue Op); 293 SDValue ExpandBitCount(unsigned Opc, SDValue Op); 294 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt, 295 SDValue &Lo, SDValue &Hi); 296 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt, 297 SDValue &Lo, SDValue &Hi); 298 299 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op); 300 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op); 301 302 // Returns the legalized (truncated or extended) shift amount. 303 SDValue LegalizeShiftAmount(SDValue ShiftAmt); 304}; 305} 306 307/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 308/// specified mask and type. Targets can specify exactly which masks they 309/// support and the code generator is tasked with not creating illegal masks. 310/// 311/// Note that this will also return true for shuffles that are promoted to a 312/// different type. 313SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const { 314 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 315 default: return 0; 316 case TargetLowering::Legal: 317 case TargetLowering::Custom: 318 break; 319 case TargetLowering::Promote: { 320 // If this is promoted to a different type, convert the shuffle mask and 321 // ask if it is legal in the promoted type! 322 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 323 MVT EltVT = NVT.getVectorElementType(); 324 325 // If we changed # elements, change the shuffle mask. 326 unsigned NumEltsGrowth = 327 NVT.getVectorNumElements() / VT.getVectorNumElements(); 328 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 329 if (NumEltsGrowth > 1) { 330 // Renumber the elements. 331 SmallVector<SDValue, 8> Ops; 332 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 333 SDValue InOp = Mask.getOperand(i); 334 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 335 if (InOp.getOpcode() == ISD::UNDEF) 336 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 337 else { 338 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue(); 339 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT)); 340 } 341 } 342 } 343 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 344 } 345 VT = NVT; 346 break; 347 } 348 } 349 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0; 350} 351 352SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, bool types) 353 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types), 354 ValueTypeActions(TLI.getValueTypeActions()) { 355 assert(MVT::LAST_VALUETYPE <= 32 && 356 "Too many value types for ValueTypeActions to hold!"); 357} 358 359void SelectionDAGLegalize::LegalizeDAG() { 360 LastCALLSEQ_END = DAG.getEntryNode(); 361 IsLegalizingCall = false; 362 363 // The legalize process is inherently a bottom-up recursive process (users 364 // legalize their uses before themselves). Given infinite stack space, we 365 // could just start legalizing on the root and traverse the whole graph. In 366 // practice however, this causes us to run out of stack space on large basic 367 // blocks. To avoid this problem, compute an ordering of the nodes where each 368 // node is only legalized after all of its operands are legalized. 369 DAG.AssignTopologicalOrder(); 370 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 371 E = prior(DAG.allnodes_end()); I != next(E); ++I) 372 HandleOp(SDValue(I, 0)); 373 374 // Finally, it's possible the root changed. Get the new root. 375 SDValue OldRoot = DAG.getRoot(); 376 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 377 DAG.setRoot(LegalizedNodes[OldRoot]); 378 379 ExpandedNodes.clear(); 380 LegalizedNodes.clear(); 381 PromotedNodes.clear(); 382 SplitNodes.clear(); 383 ScalarizedNodes.clear(); 384 WidenNodes.clear(); 385 386 // Remove dead nodes now. 387 DAG.RemoveDeadNodes(); 388} 389 390 391/// FindCallEndFromCallStart - Given a chained node that is part of a call 392/// sequence, find the CALLSEQ_END node that terminates the call sequence. 393static SDNode *FindCallEndFromCallStart(SDNode *Node) { 394 if (Node->getOpcode() == ISD::CALLSEQ_END) 395 return Node; 396 if (Node->use_empty()) 397 return 0; // No CallSeqEnd 398 399 // The chain is usually at the end. 400 SDValue TheChain(Node, Node->getNumValues()-1); 401 if (TheChain.getValueType() != MVT::Other) { 402 // Sometimes it's at the beginning. 403 TheChain = SDValue(Node, 0); 404 if (TheChain.getValueType() != MVT::Other) { 405 // Otherwise, hunt for it. 406 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 407 if (Node->getValueType(i) == MVT::Other) { 408 TheChain = SDValue(Node, i); 409 break; 410 } 411 412 // Otherwise, we walked into a node without a chain. 413 if (TheChain.getValueType() != MVT::Other) 414 return 0; 415 } 416 } 417 418 for (SDNode::use_iterator UI = Node->use_begin(), 419 E = Node->use_end(); UI != E; ++UI) { 420 421 // Make sure to only follow users of our token chain. 422 SDNode *User = *UI; 423 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 424 if (User->getOperand(i) == TheChain) 425 if (SDNode *Result = FindCallEndFromCallStart(User)) 426 return Result; 427 } 428 return 0; 429} 430 431/// FindCallStartFromCallEnd - Given a chained node that is part of a call 432/// sequence, find the CALLSEQ_START node that initiates the call sequence. 433static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 434 assert(Node && "Didn't find callseq_start for a call??"); 435 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 436 437 assert(Node->getOperand(0).getValueType() == MVT::Other && 438 "Node doesn't have a token chain argument!"); 439 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 440} 441 442/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 443/// see if any uses can reach Dest. If no dest operands can get to dest, 444/// legalize them, legalize ourself, and return false, otherwise, return true. 445/// 446/// Keep track of the nodes we fine that actually do lead to Dest in 447/// NodesLeadingTo. This avoids retraversing them exponential number of times. 448/// 449bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 450 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 451 if (N == Dest) return true; // N certainly leads to Dest :) 452 453 // If we've already processed this node and it does lead to Dest, there is no 454 // need to reprocess it. 455 if (NodesLeadingTo.count(N)) return true; 456 457 // If the first result of this node has been already legalized, then it cannot 458 // reach N. 459 switch (getTypeAction(N->getValueType(0))) { 460 case Legal: 461 if (LegalizedNodes.count(SDValue(N, 0))) return false; 462 break; 463 case Promote: 464 if (PromotedNodes.count(SDValue(N, 0))) return false; 465 break; 466 case Expand: 467 if (ExpandedNodes.count(SDValue(N, 0))) return false; 468 break; 469 } 470 471 // Okay, this node has not already been legalized. Check and legalize all 472 // operands. If none lead to Dest, then we can legalize this node. 473 bool OperandsLeadToDest = false; 474 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 475 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 476 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 477 478 if (OperandsLeadToDest) { 479 NodesLeadingTo.insert(N); 480 return true; 481 } 482 483 // Okay, this node looks safe, legalize it and return false. 484 HandleOp(SDValue(N, 0)); 485 return false; 486} 487 488/// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as 489/// appropriate for its type. 490void SelectionDAGLegalize::HandleOp(SDValue Op) { 491 MVT VT = Op.getValueType(); 492 // If the type legalizer was run then we should never see any illegal result 493 // types here except for target constants (the type legalizer does not touch 494 // those) or for build vector used as a mask for a vector shuffle. 495 // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957. 496 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal || 497 Op.getOpcode() == ISD::TargetConstant || 498 Op.getOpcode() == ISD::BUILD_VECTOR) && 499 "Illegal type introduced after type legalization?"); 500 switch (getTypeAction(VT)) { 501 default: assert(0 && "Bad type action!"); 502 case Legal: (void)LegalizeOp(Op); break; 503 case Promote: 504 if (!VT.isVector()) { 505 (void)PromoteOp(Op); 506 break; 507 } 508 else { 509 // See if we can widen otherwise use Expand to either scalarize or split 510 MVT WidenVT = TLI.getWidenVectorType(VT); 511 if (WidenVT != MVT::Other) { 512 (void) WidenVectorOp(Op, WidenVT); 513 break; 514 } 515 // else fall thru to expand since we can't widen the vector 516 } 517 case Expand: 518 if (!VT.isVector()) { 519 // If this is an illegal scalar, expand it into its two component 520 // pieces. 521 SDValue X, Y; 522 if (Op.getOpcode() == ISD::TargetConstant) 523 break; // Allow illegal target nodes. 524 ExpandOp(Op, X, Y); 525 } else if (VT.getVectorNumElements() == 1) { 526 // If this is an illegal single element vector, convert it to a 527 // scalar operation. 528 (void)ScalarizeVectorOp(Op); 529 } else { 530 // This is an illegal multiple element vector. 531 // Split it in half and legalize both parts. 532 SDValue X, Y; 533 SplitVectorOp(Op, X, Y); 534 } 535 break; 536 } 537} 538 539/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 540/// a load from the constant pool. 541static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 542 SelectionDAG &DAG, TargetLowering &TLI) { 543 bool Extend = false; 544 545 // If a FP immediate is precise when represented as a float and if the 546 // target can do an extending load from float to double, we put it into 547 // the constant pool as a float, even if it's is statically typed as a 548 // double. This shrinks FP constants and canonicalizes them for targets where 549 // an FP extending load is the same cost as a normal load (such as on the x87 550 // fp stack or PPC FP unit). 551 MVT VT = CFP->getValueType(0); 552 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 553 if (!UseCP) { 554 if (VT!=MVT::f64 && VT!=MVT::f32) 555 assert(0 && "Invalid type expansion"); 556 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 557 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 558 } 559 560 MVT OrigVT = VT; 561 MVT SVT = VT; 562 while (SVT != MVT::f32) { 563 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 564 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 565 // Only do this if the target has a native EXTLOAD instruction from 566 // smaller type. 567 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 568 TLI.ShouldShrinkFPConstant(OrigVT)) { 569 const Type *SType = SVT.getTypeForMVT(); 570 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 571 VT = SVT; 572 Extend = true; 573 } 574 } 575 576 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 577 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 578 if (Extend) 579 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), 580 CPIdx, PseudoSourceValue::getConstantPool(), 581 0, VT, false, Alignment); 582 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, 583 PseudoSourceValue::getConstantPool(), 0, false, Alignment); 584} 585 586 587/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 588/// operations. 589static 590SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, 591 SelectionDAG &DAG, TargetLowering &TLI) { 592 MVT VT = Node->getValueType(0); 593 MVT SrcVT = Node->getOperand(1).getValueType(); 594 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 595 "fcopysign expansion only supported for f32 and f64"); 596 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 597 598 // First get the sign bit of second operand. 599 SDValue Mask1 = (SrcVT == MVT::f64) 600 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 601 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 602 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 603 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 604 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 605 // Shift right or sign-extend it if the two operands have different types. 606 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); 607 if (SizeDiff > 0) { 608 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 609 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 610 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 611 } else if (SizeDiff < 0) { 612 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit); 613 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit, 614 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy())); 615 } 616 617 // Clear the sign bit of first operand. 618 SDValue Mask2 = (VT == MVT::f64) 619 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 620 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 621 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 622 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 623 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 624 625 // Or the value with the sign bit. 626 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 627 return Result; 628} 629 630/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 631static 632SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 633 TargetLowering &TLI) { 634 SDValue Chain = ST->getChain(); 635 SDValue Ptr = ST->getBasePtr(); 636 SDValue Val = ST->getValue(); 637 MVT VT = Val.getValueType(); 638 int Alignment = ST->getAlignment(); 639 int SVOffset = ST->getSrcValueOffset(); 640 if (ST->getMemoryVT().isFloatingPoint() || 641 ST->getMemoryVT().isVector()) { 642 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits()); 643 if (TLI.isTypeLegal(intVT)) { 644 // Expand to a bitconvert of the value to the integer type of the 645 // same size, then a (misaligned) int store. 646 // FIXME: Does not handle truncating floating point stores! 647 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 648 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 649 SVOffset, ST->isVolatile(), Alignment); 650 } else { 651 // Do a (aligned) store to a stack slot, then copy from the stack slot 652 // to the final destination using (unaligned) integer loads and stores. 653 MVT StoredVT = ST->getMemoryVT(); 654 MVT RegVT = 655 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits())); 656 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 657 unsigned RegBytes = RegVT.getSizeInBits() / 8; 658 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 659 660 // Make sure the stack slot is also aligned for the register type. 661 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 662 663 // Perform the original store, only redirected to the stack slot. 664 SDValue Store = DAG.getTruncStore(Chain, Val, StackPtr, NULL, 0,StoredVT); 665 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 666 SmallVector<SDValue, 8> Stores; 667 unsigned Offset = 0; 668 669 // Do all but one copies using the full register width. 670 for (unsigned i = 1; i < NumRegs; i++) { 671 // Load one integer register's worth from the stack slot. 672 SDValue Load = DAG.getLoad(RegVT, Store, StackPtr, NULL, 0); 673 // Store it to the final location. Remember the store. 674 Stores.push_back(DAG.getStore(Load.getValue(1), Load, Ptr, 675 ST->getSrcValue(), SVOffset + Offset, 676 ST->isVolatile(), 677 MinAlign(ST->getAlignment(), Offset))); 678 // Increment the pointers. 679 Offset += RegBytes; 680 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr, 681 Increment); 682 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment); 683 } 684 685 // The last store may be partial. Do a truncating store. On big-endian 686 // machines this requires an extending load from the stack slot to ensure 687 // that the bits are in the right place. 688 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset)); 689 690 // Load from the stack slot. 691 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Store, StackPtr, 692 NULL, 0, MemVT); 693 694 Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, Ptr, 695 ST->getSrcValue(), SVOffset + Offset, 696 MemVT, ST->isVolatile(), 697 MinAlign(ST->getAlignment(), Offset))); 698 // The order of the stores doesn't matter - say it with a TokenFactor. 699 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], 700 Stores.size()); 701 } 702 } 703 assert(ST->getMemoryVT().isInteger() && 704 !ST->getMemoryVT().isVector() && 705 "Unaligned store of unknown type."); 706 // Get the half-size VT 707 MVT NewStoredVT = 708 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 709 int NumBits = NewStoredVT.getSizeInBits(); 710 int IncrementSize = NumBits / 8; 711 712 // Divide the stored value in two parts. 713 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 714 SDValue Lo = Val; 715 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 716 717 // Store the two parts 718 SDValue Store1, Store2; 719 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 720 ST->getSrcValue(), SVOffset, NewStoredVT, 721 ST->isVolatile(), Alignment); 722 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 723 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 724 Alignment = MinAlign(Alignment, IncrementSize); 725 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 726 ST->getSrcValue(), SVOffset + IncrementSize, 727 NewStoredVT, ST->isVolatile(), Alignment); 728 729 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 730} 731 732/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 733static 734SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 735 TargetLowering &TLI) { 736 int SVOffset = LD->getSrcValueOffset(); 737 SDValue Chain = LD->getChain(); 738 SDValue Ptr = LD->getBasePtr(); 739 MVT VT = LD->getValueType(0); 740 MVT LoadedVT = LD->getMemoryVT(); 741 if (VT.isFloatingPoint() || VT.isVector()) { 742 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits()); 743 if (TLI.isTypeLegal(intVT)) { 744 // Expand to a (misaligned) integer load of the same size, 745 // then bitconvert to floating point or vector. 746 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 747 SVOffset, LD->isVolatile(), 748 LD->getAlignment()); 749 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 750 if (VT.isFloatingPoint() && LoadedVT != VT) 751 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 752 753 SDValue Ops[] = { Result, Chain }; 754 return DAG.getMergeValues(Ops, 2); 755 } else { 756 // Copy the value to a (aligned) stack slot using (unaligned) integer 757 // loads and stores, then do a (aligned) load from the stack slot. 758 MVT RegVT = TLI.getRegisterType(intVT); 759 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 760 unsigned RegBytes = RegVT.getSizeInBits() / 8; 761 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 762 763 // Make sure the stack slot is also aligned for the register type. 764 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 765 766 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 767 SmallVector<SDValue, 8> Stores; 768 SDValue StackPtr = StackBase; 769 unsigned Offset = 0; 770 771 // Do all but one copies using the full register width. 772 for (unsigned i = 1; i < NumRegs; i++) { 773 // Load one integer register's worth from the original location. 774 SDValue Load = DAG.getLoad(RegVT, Chain, Ptr, LD->getSrcValue(), 775 SVOffset + Offset, LD->isVolatile(), 776 MinAlign(LD->getAlignment(), Offset)); 777 // Follow the load with a store to the stack slot. Remember the store. 778 Stores.push_back(DAG.getStore(Load.getValue(1), Load, StackPtr, 779 NULL, 0)); 780 // Increment the pointers. 781 Offset += RegBytes; 782 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment); 783 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr, 784 Increment); 785 } 786 787 // The last copy may be partial. Do an extending load. 788 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset)); 789 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Chain, Ptr, 790 LD->getSrcValue(), SVOffset + Offset, 791 MemVT, LD->isVolatile(), 792 MinAlign(LD->getAlignment(), Offset)); 793 // Follow the load with a store to the stack slot. Remember the store. 794 // On big-endian machines this requires a truncating store to ensure 795 // that the bits end up in the right place. 796 Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, StackPtr, 797 NULL, 0, MemVT)); 798 799 // The order of the stores doesn't matter - say it with a TokenFactor. 800 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], 801 Stores.size()); 802 803 // Finally, perform the original load only redirected to the stack slot. 804 Load = DAG.getExtLoad(LD->getExtensionType(), VT, TF, StackBase, 805 NULL, 0, LoadedVT); 806 807 // Callers expect a MERGE_VALUES node. 808 SDValue Ops[] = { Load, TF }; 809 return DAG.getMergeValues(Ops, 2); 810 } 811 } 812 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 813 "Unaligned load of unsupported type."); 814 815 // Compute the new VT that is half the size of the old one. This is an 816 // integer MVT. 817 unsigned NumBits = LoadedVT.getSizeInBits(); 818 MVT NewLoadedVT; 819 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 820 NumBits >>= 1; 821 822 unsigned Alignment = LD->getAlignment(); 823 unsigned IncrementSize = NumBits / 8; 824 ISD::LoadExtType HiExtType = LD->getExtensionType(); 825 826 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 827 if (HiExtType == ISD::NON_EXTLOAD) 828 HiExtType = ISD::ZEXTLOAD; 829 830 // Load the value in two parts 831 SDValue Lo, Hi; 832 if (TLI.isLittleEndian()) { 833 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 834 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 835 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 836 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 837 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 838 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 839 MinAlign(Alignment, IncrementSize)); 840 } else { 841 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 842 NewLoadedVT,LD->isVolatile(), Alignment); 843 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 844 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 845 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 846 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 847 MinAlign(Alignment, IncrementSize)); 848 } 849 850 // aggregate the two parts 851 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 852 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 853 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 854 855 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 856 Hi.getValue(1)); 857 858 SDValue Ops[] = { Result, TF }; 859 return DAG.getMergeValues(Ops, 2); 860} 861 862/// UnrollVectorOp - We know that the given vector has a legal type, however 863/// the operation it performs is not legal and is an operation that we have 864/// no way of lowering. "Unroll" the vector, splitting out the scalars and 865/// operating on each element individually. 866SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) { 867 MVT VT = Op.getValueType(); 868 assert(isTypeLegal(VT) && 869 "Caller should expand or promote operands that are not legal!"); 870 assert(Op.getNode()->getNumValues() == 1 && 871 "Can't unroll a vector with multiple results!"); 872 unsigned NE = VT.getVectorNumElements(); 873 MVT EltVT = VT.getVectorElementType(); 874 875 SmallVector<SDValue, 8> Scalars; 876 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 877 for (unsigned i = 0; i != NE; ++i) { 878 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 879 SDValue Operand = Op.getOperand(j); 880 MVT OperandVT = Operand.getValueType(); 881 if (OperandVT.isVector()) { 882 // A vector operand; extract a single element. 883 MVT OperandEltVT = OperandVT.getVectorElementType(); 884 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 885 OperandEltVT, 886 Operand, 887 DAG.getConstant(i, MVT::i32)); 888 } else { 889 // A scalar operand; just use it as is. 890 Operands[j] = Operand; 891 } 892 } 893 894 switch (Op.getOpcode()) { 895 default: 896 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 897 &Operands[0], Operands.size())); 898 break; 899 case ISD::SHL: 900 case ISD::SRA: 901 case ISD::SRL: 902 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, Operands[0], 903 LegalizeShiftAmount(Operands[1]))); 904 break; 905 } 906 } 907 908 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 909} 910 911/// GetFPLibCall - Return the right libcall for the given floating point type. 912static RTLIB::Libcall GetFPLibCall(MVT VT, 913 RTLIB::Libcall Call_F32, 914 RTLIB::Libcall Call_F64, 915 RTLIB::Libcall Call_F80, 916 RTLIB::Libcall Call_PPCF128) { 917 return 918 VT == MVT::f32 ? Call_F32 : 919 VT == MVT::f64 ? Call_F64 : 920 VT == MVT::f80 ? Call_F80 : 921 VT == MVT::ppcf128 ? Call_PPCF128 : 922 RTLIB::UNKNOWN_LIBCALL; 923} 924 925/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 926/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 927/// is necessary to spill the vector being inserted into to memory, perform 928/// the insert there, and then read the result back. 929SDValue SelectionDAGLegalize:: 930PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) { 931 SDValue Tmp1 = Vec; 932 SDValue Tmp2 = Val; 933 SDValue Tmp3 = Idx; 934 935 // If the target doesn't support this, we have to spill the input vector 936 // to a temporary stack slot, update the element, then reload it. This is 937 // badness. We could also load the value into a vector register (either 938 // with a "move to register" or "extload into register" instruction, then 939 // permute it into place, if the idx is a constant and if the idx is 940 // supported by the target. 941 MVT VT = Tmp1.getValueType(); 942 MVT EltVT = VT.getVectorElementType(); 943 MVT IdxVT = Tmp3.getValueType(); 944 MVT PtrVT = TLI.getPointerTy(); 945 SDValue StackPtr = DAG.CreateStackTemporary(VT); 946 947 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 948 949 // Store the vector. 950 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, 951 PseudoSourceValue::getFixedStack(SPFI), 0); 952 953 // Truncate or zero extend offset to target pointer type. 954 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 955 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 956 // Add the offset to the index. 957 unsigned EltSize = EltVT.getSizeInBits()/8; 958 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 959 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 960 // Store the scalar value. 961 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, 962 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); 963 // Load the updated vector. 964 return DAG.getLoad(VT, Ch, StackPtr, 965 PseudoSourceValue::getFixedStack(SPFI), 0); 966} 967 968SDValue SelectionDAGLegalize::LegalizeShiftAmount(SDValue ShiftAmt) { 969 if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType())) 970 return DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt); 971 972 if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType())) 973 return DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt); 974 975 return ShiftAmt; 976} 977 978 979/// LegalizeOp - We know that the specified value has a legal type, and 980/// that its operands are legal. Now ensure that the operation itself 981/// is legal, recursively ensuring that the operands' operations remain 982/// legal. 983SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 984 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 985 return Op; 986 987 assert(isTypeLegal(Op.getValueType()) && 988 "Caller should expand or promote operands that are not legal!"); 989 SDNode *Node = Op.getNode(); 990 991 // If this operation defines any values that cannot be represented in a 992 // register on this target, make sure to expand or promote them. 993 if (Node->getNumValues() > 1) { 994 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 995 if (getTypeAction(Node->getValueType(i)) != Legal) { 996 HandleOp(Op.getValue(i)); 997 assert(LegalizedNodes.count(Op) && 998 "Handling didn't add legal operands!"); 999 return LegalizedNodes[Op]; 1000 } 1001 } 1002 1003 // Note that LegalizeOp may be reentered even from single-use nodes, which 1004 // means that we always must cache transformed nodes. 1005 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1006 if (I != LegalizedNodes.end()) return I->second; 1007 1008 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 1009 SDValue Result = Op; 1010 bool isCustom = false; 1011 1012 switch (Node->getOpcode()) { 1013 case ISD::FrameIndex: 1014 case ISD::EntryToken: 1015 case ISD::Register: 1016 case ISD::BasicBlock: 1017 case ISD::TargetFrameIndex: 1018 case ISD::TargetJumpTable: 1019 case ISD::TargetConstant: 1020 case ISD::TargetConstantFP: 1021 case ISD::TargetConstantPool: 1022 case ISD::TargetGlobalAddress: 1023 case ISD::TargetGlobalTLSAddress: 1024 case ISD::TargetExternalSymbol: 1025 case ISD::VALUETYPE: 1026 case ISD::SRCVALUE: 1027 case ISD::MEMOPERAND: 1028 case ISD::CONDCODE: 1029 case ISD::ARG_FLAGS: 1030 // Primitives must all be legal. 1031 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 1032 "This must be legal!"); 1033 break; 1034 default: 1035 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 1036 // If this is a target node, legalize it by legalizing the operands then 1037 // passing it through. 1038 SmallVector<SDValue, 8> Ops; 1039 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1040 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1041 1042 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 1043 1044 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1045 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 1046 return Result.getValue(Op.getResNo()); 1047 } 1048 // Otherwise this is an unhandled builtin node. splat. 1049#ifndef NDEBUG 1050 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 1051#endif 1052 assert(0 && "Do not know how to legalize this operator!"); 1053 abort(); 1054 case ISD::GLOBAL_OFFSET_TABLE: 1055 case ISD::GlobalAddress: 1056 case ISD::GlobalTLSAddress: 1057 case ISD::ExternalSymbol: 1058 case ISD::ConstantPool: 1059 case ISD::JumpTable: // Nothing to do. 1060 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1061 default: assert(0 && "This action is not supported yet!"); 1062 case TargetLowering::Custom: 1063 Tmp1 = TLI.LowerOperation(Op, DAG); 1064 if (Tmp1.getNode()) Result = Tmp1; 1065 // FALLTHROUGH if the target doesn't want to lower this op after all. 1066 case TargetLowering::Legal: 1067 break; 1068 } 1069 break; 1070 case ISD::FRAMEADDR: 1071 case ISD::RETURNADDR: 1072 // The only option for these nodes is to custom lower them. If the target 1073 // does not custom lower them, then return zero. 1074 Tmp1 = TLI.LowerOperation(Op, DAG); 1075 if (Tmp1.getNode()) 1076 Result = Tmp1; 1077 else 1078 Result = DAG.getConstant(0, TLI.getPointerTy()); 1079 break; 1080 case ISD::FRAME_TO_ARGS_OFFSET: { 1081 MVT VT = Node->getValueType(0); 1082 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1083 default: assert(0 && "This action is not supported yet!"); 1084 case TargetLowering::Custom: 1085 Result = TLI.LowerOperation(Op, DAG); 1086 if (Result.getNode()) break; 1087 // Fall Thru 1088 case TargetLowering::Legal: 1089 Result = DAG.getConstant(0, VT); 1090 break; 1091 } 1092 } 1093 break; 1094 case ISD::EXCEPTIONADDR: { 1095 Tmp1 = LegalizeOp(Node->getOperand(0)); 1096 MVT VT = Node->getValueType(0); 1097 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1098 default: assert(0 && "This action is not supported yet!"); 1099 case TargetLowering::Expand: { 1100 unsigned Reg = TLI.getExceptionAddressRegister(); 1101 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 1102 } 1103 break; 1104 case TargetLowering::Custom: 1105 Result = TLI.LowerOperation(Op, DAG); 1106 if (Result.getNode()) break; 1107 // Fall Thru 1108 case TargetLowering::Legal: { 1109 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 1110 Result = DAG.getMergeValues(Ops, 2); 1111 break; 1112 } 1113 } 1114 } 1115 if (Result.getNode()->getNumValues() == 1) break; 1116 1117 assert(Result.getNode()->getNumValues() == 2 && 1118 "Cannot return more than two values!"); 1119 1120 // Since we produced two values, make sure to remember that we 1121 // legalized both of them. 1122 Tmp1 = LegalizeOp(Result); 1123 Tmp2 = LegalizeOp(Result.getValue(1)); 1124 AddLegalizedOperand(Op.getValue(0), Tmp1); 1125 AddLegalizedOperand(Op.getValue(1), Tmp2); 1126 return Op.getResNo() ? Tmp2 : Tmp1; 1127 case ISD::EHSELECTION: { 1128 Tmp1 = LegalizeOp(Node->getOperand(0)); 1129 Tmp2 = LegalizeOp(Node->getOperand(1)); 1130 MVT VT = Node->getValueType(0); 1131 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1132 default: assert(0 && "This action is not supported yet!"); 1133 case TargetLowering::Expand: { 1134 unsigned Reg = TLI.getExceptionSelectorRegister(); 1135 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 1136 } 1137 break; 1138 case TargetLowering::Custom: 1139 Result = TLI.LowerOperation(Op, DAG); 1140 if (Result.getNode()) break; 1141 // Fall Thru 1142 case TargetLowering::Legal: { 1143 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 1144 Result = DAG.getMergeValues(Ops, 2); 1145 break; 1146 } 1147 } 1148 } 1149 if (Result.getNode()->getNumValues() == 1) break; 1150 1151 assert(Result.getNode()->getNumValues() == 2 && 1152 "Cannot return more than two values!"); 1153 1154 // Since we produced two values, make sure to remember that we 1155 // legalized both of them. 1156 Tmp1 = LegalizeOp(Result); 1157 Tmp2 = LegalizeOp(Result.getValue(1)); 1158 AddLegalizedOperand(Op.getValue(0), Tmp1); 1159 AddLegalizedOperand(Op.getValue(1), Tmp2); 1160 return Op.getResNo() ? Tmp2 : Tmp1; 1161 case ISD::EH_RETURN: { 1162 MVT VT = Node->getValueType(0); 1163 // The only "good" option for this node is to custom lower it. 1164 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1165 default: assert(0 && "This action is not supported at all!"); 1166 case TargetLowering::Custom: 1167 Result = TLI.LowerOperation(Op, DAG); 1168 if (Result.getNode()) break; 1169 // Fall Thru 1170 case TargetLowering::Legal: 1171 // Target does not know, how to lower this, lower to noop 1172 Result = LegalizeOp(Node->getOperand(0)); 1173 break; 1174 } 1175 } 1176 break; 1177 case ISD::AssertSext: 1178 case ISD::AssertZext: 1179 Tmp1 = LegalizeOp(Node->getOperand(0)); 1180 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1181 break; 1182 case ISD::MERGE_VALUES: 1183 // Legalize eliminates MERGE_VALUES nodes. 1184 Result = Node->getOperand(Op.getResNo()); 1185 break; 1186 case ISD::CopyFromReg: 1187 Tmp1 = LegalizeOp(Node->getOperand(0)); 1188 Result = Op.getValue(0); 1189 if (Node->getNumValues() == 2) { 1190 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1191 } else { 1192 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 1193 if (Node->getNumOperands() == 3) { 1194 Tmp2 = LegalizeOp(Node->getOperand(2)); 1195 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1196 } else { 1197 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1198 } 1199 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 1200 } 1201 // Since CopyFromReg produces two values, make sure to remember that we 1202 // legalized both of them. 1203 AddLegalizedOperand(Op.getValue(0), Result); 1204 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1205 return Result.getValue(Op.getResNo()); 1206 case ISD::UNDEF: { 1207 MVT VT = Op.getValueType(); 1208 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 1209 default: assert(0 && "This action is not supported yet!"); 1210 case TargetLowering::Expand: 1211 if (VT.isInteger()) 1212 Result = DAG.getConstant(0, VT); 1213 else if (VT.isFloatingPoint()) 1214 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), 1215 VT); 1216 else 1217 assert(0 && "Unknown value type!"); 1218 break; 1219 case TargetLowering::Legal: 1220 break; 1221 } 1222 break; 1223 } 1224 1225 case ISD::INTRINSIC_W_CHAIN: 1226 case ISD::INTRINSIC_WO_CHAIN: 1227 case ISD::INTRINSIC_VOID: { 1228 SmallVector<SDValue, 8> Ops; 1229 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1230 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1231 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1232 1233 // Allow the target to custom lower its intrinsics if it wants to. 1234 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1235 TargetLowering::Custom) { 1236 Tmp3 = TLI.LowerOperation(Result, DAG); 1237 if (Tmp3.getNode()) Result = Tmp3; 1238 } 1239 1240 if (Result.getNode()->getNumValues() == 1) break; 1241 1242 // Must have return value and chain result. 1243 assert(Result.getNode()->getNumValues() == 2 && 1244 "Cannot return more than two values!"); 1245 1246 // Since loads produce two values, make sure to remember that we 1247 // legalized both of them. 1248 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1249 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1250 return Result.getValue(Op.getResNo()); 1251 } 1252 1253 case ISD::DBG_STOPPOINT: 1254 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!"); 1255 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1256 1257 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) { 1258 case TargetLowering::Promote: 1259 default: assert(0 && "This action is not supported yet!"); 1260 case TargetLowering::Expand: { 1261 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1262 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1263 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other); 1264 1265 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 1266 if (MMI && (useDEBUG_LOC || useLABEL)) { 1267 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit(); 1268 unsigned SrcFile = MMI->RecordSource(CompileUnit); 1269 1270 unsigned Line = DSP->getLine(); 1271 unsigned Col = DSP->getColumn(); 1272 1273 if (useDEBUG_LOC) { 1274 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32), 1275 DAG.getConstant(Col, MVT::i32), 1276 DAG.getConstant(SrcFile, MVT::i32) }; 1277 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4); 1278 } else { 1279 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); 1280 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID); 1281 } 1282 } else { 1283 Result = Tmp1; // chain 1284 } 1285 break; 1286 } 1287 case TargetLowering::Legal: { 1288 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1289 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1290 break; 1291 1292 SmallVector<SDValue, 8> Ops; 1293 Ops.push_back(Tmp1); 1294 if (Action == Legal) { 1295 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1296 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1297 } else { 1298 // Otherwise promote them. 1299 Ops.push_back(PromoteOp(Node->getOperand(1))); 1300 Ops.push_back(PromoteOp(Node->getOperand(2))); 1301 } 1302 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1303 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1304 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1305 break; 1306 } 1307 } 1308 break; 1309 1310 case ISD::DECLARE: 1311 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1312 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1313 default: assert(0 && "This action is not supported yet!"); 1314 case TargetLowering::Legal: 1315 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1316 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1317 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1318 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1319 break; 1320 case TargetLowering::Expand: 1321 Result = LegalizeOp(Node->getOperand(0)); 1322 break; 1323 } 1324 break; 1325 1326 case ISD::DEBUG_LOC: 1327 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1328 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1329 default: assert(0 && "This action is not supported yet!"); 1330 case TargetLowering::Legal: { 1331 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1332 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1333 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1334 break; 1335 if (Action == Legal) { 1336 Tmp2 = Node->getOperand(1); 1337 Tmp3 = Node->getOperand(2); 1338 Tmp4 = Node->getOperand(3); 1339 } else { 1340 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1341 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1342 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1343 } 1344 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1345 break; 1346 } 1347 } 1348 break; 1349 1350 case ISD::DBG_LABEL: 1351 case ISD::EH_LABEL: 1352 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!"); 1353 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1354 default: assert(0 && "This action is not supported yet!"); 1355 case TargetLowering::Legal: 1356 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1357 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1358 break; 1359 case TargetLowering::Expand: 1360 Result = LegalizeOp(Node->getOperand(0)); 1361 break; 1362 } 1363 break; 1364 1365 case ISD::PREFETCH: 1366 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1367 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1368 default: assert(0 && "This action is not supported yet!"); 1369 case TargetLowering::Legal: 1370 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1371 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1372 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1373 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1374 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1375 break; 1376 case TargetLowering::Expand: 1377 // It's a noop. 1378 Result = LegalizeOp(Node->getOperand(0)); 1379 break; 1380 } 1381 break; 1382 1383 case ISD::MEMBARRIER: { 1384 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1385 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1386 default: assert(0 && "This action is not supported yet!"); 1387 case TargetLowering::Legal: { 1388 SDValue Ops[6]; 1389 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1390 for (int x = 1; x < 6; ++x) { 1391 Ops[x] = Node->getOperand(x); 1392 if (!isTypeLegal(Ops[x].getValueType())) 1393 Ops[x] = PromoteOp(Ops[x]); 1394 } 1395 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1396 break; 1397 } 1398 case TargetLowering::Expand: 1399 //There is no libgcc call for this op 1400 Result = Node->getOperand(0); // Noop 1401 break; 1402 } 1403 break; 1404 } 1405 1406 case ISD::ATOMIC_CMP_SWAP: { 1407 unsigned int num_operands = 4; 1408 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1409 SDValue Ops[4]; 1410 for (unsigned int x = 0; x < num_operands; ++x) 1411 Ops[x] = LegalizeOp(Node->getOperand(x)); 1412 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1413 1414 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1415 default: assert(0 && "This action is not supported yet!"); 1416 case TargetLowering::Custom: 1417 Result = TLI.LowerOperation(Result, DAG); 1418 break; 1419 case TargetLowering::Legal: 1420 break; 1421 } 1422 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1423 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1424 return Result.getValue(Op.getResNo()); 1425 } 1426 case ISD::ATOMIC_LOAD_ADD: 1427 case ISD::ATOMIC_LOAD_SUB: 1428 case ISD::ATOMIC_LOAD_AND: 1429 case ISD::ATOMIC_LOAD_OR: 1430 case ISD::ATOMIC_LOAD_XOR: 1431 case ISD::ATOMIC_LOAD_NAND: 1432 case ISD::ATOMIC_LOAD_MIN: 1433 case ISD::ATOMIC_LOAD_MAX: 1434 case ISD::ATOMIC_LOAD_UMIN: 1435 case ISD::ATOMIC_LOAD_UMAX: 1436 case ISD::ATOMIC_SWAP: { 1437 unsigned int num_operands = 3; 1438 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1439 SDValue Ops[3]; 1440 for (unsigned int x = 0; x < num_operands; ++x) 1441 Ops[x] = LegalizeOp(Node->getOperand(x)); 1442 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1443 1444 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1445 default: assert(0 && "This action is not supported yet!"); 1446 case TargetLowering::Custom: 1447 Result = TLI.LowerOperation(Result, DAG); 1448 break; 1449 case TargetLowering::Legal: 1450 break; 1451 } 1452 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1453 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1454 return Result.getValue(Op.getResNo()); 1455 } 1456 case ISD::Constant: { 1457 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1458 unsigned opAction = 1459 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1460 1461 // We know we don't need to expand constants here, constants only have one 1462 // value and we check that it is fine above. 1463 1464 if (opAction == TargetLowering::Custom) { 1465 Tmp1 = TLI.LowerOperation(Result, DAG); 1466 if (Tmp1.getNode()) 1467 Result = Tmp1; 1468 } 1469 break; 1470 } 1471 case ISD::ConstantFP: { 1472 // Spill FP immediates to the constant pool if the target cannot directly 1473 // codegen them. Targets often have some immediate values that can be 1474 // efficiently generated into an FP register without a load. We explicitly 1475 // leave these constants as ConstantFP nodes for the target to deal with. 1476 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1477 1478 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1479 default: assert(0 && "This action is not supported yet!"); 1480 case TargetLowering::Legal: 1481 break; 1482 case TargetLowering::Custom: 1483 Tmp3 = TLI.LowerOperation(Result, DAG); 1484 if (Tmp3.getNode()) { 1485 Result = Tmp3; 1486 break; 1487 } 1488 // FALLTHROUGH 1489 case TargetLowering::Expand: { 1490 // Check to see if this FP immediate is already legal. 1491 bool isLegal = false; 1492 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1493 E = TLI.legal_fpimm_end(); I != E; ++I) { 1494 if (CFP->isExactlyValue(*I)) { 1495 isLegal = true; 1496 break; 1497 } 1498 } 1499 // If this is a legal constant, turn it into a TargetConstantFP node. 1500 if (isLegal) 1501 break; 1502 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1503 } 1504 } 1505 break; 1506 } 1507 case ISD::TokenFactor: 1508 if (Node->getNumOperands() == 2) { 1509 Tmp1 = LegalizeOp(Node->getOperand(0)); 1510 Tmp2 = LegalizeOp(Node->getOperand(1)); 1511 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1512 } else if (Node->getNumOperands() == 3) { 1513 Tmp1 = LegalizeOp(Node->getOperand(0)); 1514 Tmp2 = LegalizeOp(Node->getOperand(1)); 1515 Tmp3 = LegalizeOp(Node->getOperand(2)); 1516 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1517 } else { 1518 SmallVector<SDValue, 8> Ops; 1519 // Legalize the operands. 1520 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1521 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1522 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1523 } 1524 break; 1525 1526 case ISD::FORMAL_ARGUMENTS: 1527 case ISD::CALL: 1528 // The only option for this is to custom lower it. 1529 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1530 assert(Tmp3.getNode() && "Target didn't custom lower this node!"); 1531 // A call within a calling sequence must be legalized to something 1532 // other than the normal CALLSEQ_END. Violating this gets Legalize 1533 // into an infinite loop. 1534 assert ((!IsLegalizingCall || 1535 Node->getOpcode() != ISD::CALL || 1536 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) && 1537 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1538 1539 // The number of incoming and outgoing values should match; unless the final 1540 // outgoing value is a flag. 1541 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() || 1542 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 && 1543 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) == 1544 MVT::Flag)) && 1545 "Lowering call/formal_arguments produced unexpected # results!"); 1546 1547 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1548 // remember that we legalized all of them, so it doesn't get relegalized. 1549 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) { 1550 if (Tmp3.getNode()->getValueType(i) == MVT::Flag) 1551 continue; 1552 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1553 if (Op.getResNo() == i) 1554 Tmp2 = Tmp1; 1555 AddLegalizedOperand(SDValue(Node, i), Tmp1); 1556 } 1557 return Tmp2; 1558 case ISD::EXTRACT_SUBREG: { 1559 Tmp1 = LegalizeOp(Node->getOperand(0)); 1560 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1561 assert(idx && "Operand must be a constant"); 1562 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); 1563 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1564 } 1565 break; 1566 case ISD::INSERT_SUBREG: { 1567 Tmp1 = LegalizeOp(Node->getOperand(0)); 1568 Tmp2 = LegalizeOp(Node->getOperand(1)); 1569 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1570 assert(idx && "Operand must be a constant"); 1571 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); 1572 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1573 } 1574 break; 1575 case ISD::BUILD_VECTOR: 1576 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1577 default: assert(0 && "This action is not supported yet!"); 1578 case TargetLowering::Custom: 1579 Tmp3 = TLI.LowerOperation(Result, DAG); 1580 if (Tmp3.getNode()) { 1581 Result = Tmp3; 1582 break; 1583 } 1584 // FALLTHROUGH 1585 case TargetLowering::Expand: 1586 Result = ExpandBUILD_VECTOR(Result.getNode()); 1587 break; 1588 } 1589 break; 1590 case ISD::INSERT_VECTOR_ELT: 1591 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1592 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1593 1594 // The type of the value to insert may not be legal, even though the vector 1595 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1596 // here. 1597 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1598 default: assert(0 && "Cannot expand insert element operand"); 1599 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1600 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1601 case Expand: 1602 // FIXME: An alternative would be to check to see if the target is not 1603 // going to custom lower this operation, we could bitcast to half elt 1604 // width and perform two inserts at that width, if that is legal. 1605 Tmp2 = Node->getOperand(1); 1606 break; 1607 } 1608 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1609 1610 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1611 Node->getValueType(0))) { 1612 default: assert(0 && "This action is not supported yet!"); 1613 case TargetLowering::Legal: 1614 break; 1615 case TargetLowering::Custom: 1616 Tmp4 = TLI.LowerOperation(Result, DAG); 1617 if (Tmp4.getNode()) { 1618 Result = Tmp4; 1619 break; 1620 } 1621 // FALLTHROUGH 1622 case TargetLowering::Promote: 1623 // Fall thru for vector case 1624 case TargetLowering::Expand: { 1625 // If the insert index is a constant, codegen this as a scalar_to_vector, 1626 // then a shuffle that inserts it into the right position in the vector. 1627 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1628 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1629 // match the element type of the vector being created. 1630 if (Tmp2.getValueType() == 1631 Op.getValueType().getVectorElementType()) { 1632 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1633 Tmp1.getValueType(), Tmp2); 1634 1635 unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); 1636 MVT ShufMaskVT = 1637 MVT::getIntVectorWithNumElements(NumElts); 1638 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType(); 1639 1640 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1641 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1642 // elt 0 of the RHS. 1643 SmallVector<SDValue, 8> ShufOps; 1644 for (unsigned i = 0; i != NumElts; ++i) { 1645 if (i != InsertPos->getZExtValue()) 1646 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1647 else 1648 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1649 } 1650 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1651 &ShufOps[0], ShufOps.size()); 1652 1653 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1654 Tmp1, ScVec, ShufMask); 1655 Result = LegalizeOp(Result); 1656 break; 1657 } 1658 } 1659 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3); 1660 break; 1661 } 1662 } 1663 break; 1664 case ISD::SCALAR_TO_VECTOR: 1665 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1666 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1667 break; 1668 } 1669 1670 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1671 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1672 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1673 Node->getValueType(0))) { 1674 default: assert(0 && "This action is not supported yet!"); 1675 case TargetLowering::Legal: 1676 break; 1677 case TargetLowering::Custom: 1678 Tmp3 = TLI.LowerOperation(Result, DAG); 1679 if (Tmp3.getNode()) { 1680 Result = Tmp3; 1681 break; 1682 } 1683 // FALLTHROUGH 1684 case TargetLowering::Expand: 1685 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1686 break; 1687 } 1688 break; 1689 case ISD::VECTOR_SHUFFLE: 1690 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1691 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1692 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1693 1694 // Allow targets to custom lower the SHUFFLEs they support. 1695 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1696 default: assert(0 && "Unknown operation action!"); 1697 case TargetLowering::Legal: 1698 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1699 "vector shuffle should not be created if not legal!"); 1700 break; 1701 case TargetLowering::Custom: 1702 Tmp3 = TLI.LowerOperation(Result, DAG); 1703 if (Tmp3.getNode()) { 1704 Result = Tmp3; 1705 break; 1706 } 1707 // FALLTHROUGH 1708 case TargetLowering::Expand: { 1709 MVT VT = Node->getValueType(0); 1710 MVT EltVT = VT.getVectorElementType(); 1711 MVT PtrVT = TLI.getPointerTy(); 1712 SDValue Mask = Node->getOperand(2); 1713 unsigned NumElems = Mask.getNumOperands(); 1714 SmallVector<SDValue,8> Ops; 1715 for (unsigned i = 0; i != NumElems; ++i) { 1716 SDValue Arg = Mask.getOperand(i); 1717 if (Arg.getOpcode() == ISD::UNDEF) { 1718 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1719 } else { 1720 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1721 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue(); 1722 if (Idx < NumElems) 1723 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1724 DAG.getConstant(Idx, PtrVT))); 1725 else 1726 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1727 DAG.getConstant(Idx - NumElems, PtrVT))); 1728 } 1729 } 1730 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1731 break; 1732 } 1733 case TargetLowering::Promote: { 1734 // Change base type to a different vector type. 1735 MVT OVT = Node->getValueType(0); 1736 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1737 1738 // Cast the two input vectors. 1739 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1740 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1741 1742 // Convert the shuffle mask to the right # elements. 1743 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1744 assert(Tmp3.getNode() && "Shuffle not legal?"); 1745 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1746 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1747 break; 1748 } 1749 } 1750 break; 1751 1752 case ISD::EXTRACT_VECTOR_ELT: 1753 Tmp1 = Node->getOperand(0); 1754 Tmp2 = LegalizeOp(Node->getOperand(1)); 1755 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1756 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1757 break; 1758 1759 case ISD::EXTRACT_SUBVECTOR: 1760 Tmp1 = Node->getOperand(0); 1761 Tmp2 = LegalizeOp(Node->getOperand(1)); 1762 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1763 Result = ExpandEXTRACT_SUBVECTOR(Result); 1764 break; 1765 1766 case ISD::CONCAT_VECTORS: { 1767 // Use extract/insert/build vector for now. We might try to be 1768 // more clever later. 1769 MVT PtrVT = TLI.getPointerTy(); 1770 SmallVector<SDValue, 8> Ops; 1771 unsigned NumOperands = Node->getNumOperands(); 1772 for (unsigned i=0; i < NumOperands; ++i) { 1773 SDValue SubOp = Node->getOperand(i); 1774 MVT VVT = SubOp.getNode()->getValueType(0); 1775 MVT EltVT = VVT.getVectorElementType(); 1776 unsigned NumSubElem = VVT.getVectorNumElements(); 1777 for (unsigned j=0; j < NumSubElem; ++j) { 1778 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, SubOp, 1779 DAG.getConstant(j, PtrVT))); 1780 } 1781 } 1782 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), 1783 &Ops[0], Ops.size())); 1784 } 1785 1786 case ISD::CALLSEQ_START: { 1787 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1788 1789 // Recursively Legalize all of the inputs of the call end that do not lead 1790 // to this call start. This ensures that any libcalls that need be inserted 1791 // are inserted *before* the CALLSEQ_START. 1792 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1793 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1794 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1795 NodesLeadingTo); 1796 } 1797 1798 // Now that we legalized all of the inputs (which may have inserted 1799 // libcalls) create the new CALLSEQ_START node. 1800 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1801 1802 // Merge in the last call, to ensure that this call start after the last 1803 // call ended. 1804 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1805 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1806 Tmp1 = LegalizeOp(Tmp1); 1807 } 1808 1809 // Do not try to legalize the target-specific arguments (#1+). 1810 if (Tmp1 != Node->getOperand(0)) { 1811 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1812 Ops[0] = Tmp1; 1813 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1814 } 1815 1816 // Remember that the CALLSEQ_START is legalized. 1817 AddLegalizedOperand(Op.getValue(0), Result); 1818 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1819 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1820 1821 // Now that the callseq_start and all of the non-call nodes above this call 1822 // sequence have been legalized, legalize the call itself. During this 1823 // process, no libcalls can/will be inserted, guaranteeing that no calls 1824 // can overlap. 1825 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1826 // Note that we are selecting this call! 1827 LastCALLSEQ_END = SDValue(CallEnd, 0); 1828 IsLegalizingCall = true; 1829 1830 // Legalize the call, starting from the CALLSEQ_END. 1831 LegalizeOp(LastCALLSEQ_END); 1832 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1833 return Result; 1834 } 1835 case ISD::CALLSEQ_END: 1836 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1837 // will cause this node to be legalized as well as handling libcalls right. 1838 if (LastCALLSEQ_END.getNode() != Node) { 1839 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1840 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1841 assert(I != LegalizedNodes.end() && 1842 "Legalizing the call start should have legalized this node!"); 1843 return I->second; 1844 } 1845 1846 // Otherwise, the call start has been legalized and everything is going 1847 // according to plan. Just legalize ourselves normally here. 1848 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1849 // Do not try to legalize the target-specific arguments (#1+), except for 1850 // an optional flag input. 1851 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1852 if (Tmp1 != Node->getOperand(0)) { 1853 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1854 Ops[0] = Tmp1; 1855 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1856 } 1857 } else { 1858 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1859 if (Tmp1 != Node->getOperand(0) || 1860 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1861 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1862 Ops[0] = Tmp1; 1863 Ops.back() = Tmp2; 1864 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1865 } 1866 } 1867 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1868 // This finishes up call legalization. 1869 IsLegalizingCall = false; 1870 1871 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1872 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1873 if (Node->getNumValues() == 2) 1874 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1875 return Result.getValue(Op.getResNo()); 1876 case ISD::DYNAMIC_STACKALLOC: { 1877 MVT VT = Node->getValueType(0); 1878 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1879 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1880 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1881 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1882 1883 Tmp1 = Result.getValue(0); 1884 Tmp2 = Result.getValue(1); 1885 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1886 default: assert(0 && "This action is not supported yet!"); 1887 case TargetLowering::Expand: { 1888 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1889 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1890 " not tell us which reg is the stack pointer!"); 1891 SDValue Chain = Tmp1.getOperand(0); 1892 1893 // Chain the dynamic stack allocation so that it doesn't modify the stack 1894 // pointer when other instructions are using the stack. 1895 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1896 1897 SDValue Size = Tmp2.getOperand(1); 1898 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1899 Chain = SP.getValue(1); 1900 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1901 unsigned StackAlign = 1902 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1903 if (Align > StackAlign) 1904 SP = DAG.getNode(ISD::AND, VT, SP, 1905 DAG.getConstant(-(uint64_t)Align, VT)); 1906 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1907 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1908 1909 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1910 DAG.getIntPtrConstant(0, true), SDValue()); 1911 1912 Tmp1 = LegalizeOp(Tmp1); 1913 Tmp2 = LegalizeOp(Tmp2); 1914 break; 1915 } 1916 case TargetLowering::Custom: 1917 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1918 if (Tmp3.getNode()) { 1919 Tmp1 = LegalizeOp(Tmp3); 1920 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1921 } 1922 break; 1923 case TargetLowering::Legal: 1924 break; 1925 } 1926 // Since this op produce two values, make sure to remember that we 1927 // legalized both of them. 1928 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1929 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1930 return Op.getResNo() ? Tmp2 : Tmp1; 1931 } 1932 case ISD::INLINEASM: { 1933 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1934 bool Changed = false; 1935 // Legalize all of the operands of the inline asm, in case they are nodes 1936 // that need to be expanded or something. Note we skip the asm string and 1937 // all of the TargetConstant flags. 1938 SDValue Op = LegalizeOp(Ops[0]); 1939 Changed = Op != Ops[0]; 1940 Ops[0] = Op; 1941 1942 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1943 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1944 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3; 1945 for (++i; NumVals; ++i, --NumVals) { 1946 SDValue Op = LegalizeOp(Ops[i]); 1947 if (Op != Ops[i]) { 1948 Changed = true; 1949 Ops[i] = Op; 1950 } 1951 } 1952 } 1953 1954 if (HasInFlag) { 1955 Op = LegalizeOp(Ops.back()); 1956 Changed |= Op != Ops.back(); 1957 Ops.back() = Op; 1958 } 1959 1960 if (Changed) 1961 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1962 1963 // INLINE asm returns a chain and flag, make sure to add both to the map. 1964 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1965 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1966 return Result.getValue(Op.getResNo()); 1967 } 1968 case ISD::BR: 1969 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1970 // Ensure that libcalls are emitted before a branch. 1971 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1972 Tmp1 = LegalizeOp(Tmp1); 1973 LastCALLSEQ_END = DAG.getEntryNode(); 1974 1975 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1976 break; 1977 case ISD::BRIND: 1978 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1979 // Ensure that libcalls are emitted before a branch. 1980 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1981 Tmp1 = LegalizeOp(Tmp1); 1982 LastCALLSEQ_END = DAG.getEntryNode(); 1983 1984 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1985 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1986 case Legal: 1987 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1988 break; 1989 } 1990 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1991 break; 1992 case ISD::BR_JT: 1993 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1994 // Ensure that libcalls are emitted before a branch. 1995 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1996 Tmp1 = LegalizeOp(Tmp1); 1997 LastCALLSEQ_END = DAG.getEntryNode(); 1998 1999 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 2000 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2001 2002 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 2003 default: assert(0 && "This action is not supported yet!"); 2004 case TargetLowering::Legal: break; 2005 case TargetLowering::Custom: 2006 Tmp1 = TLI.LowerOperation(Result, DAG); 2007 if (Tmp1.getNode()) Result = Tmp1; 2008 break; 2009 case TargetLowering::Expand: { 2010 SDValue Chain = Result.getOperand(0); 2011 SDValue Table = Result.getOperand(1); 2012 SDValue Index = Result.getOperand(2); 2013 2014 MVT PTy = TLI.getPointerTy(); 2015 MachineFunction &MF = DAG.getMachineFunction(); 2016 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 2017 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 2018 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 2019 2020 MVT MemVT = MVT::getIntegerVT(EntrySize * 8); 2021 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, Chain, Addr, 2022 PseudoSourceValue::getJumpTable(), 0, MemVT); 2023 Addr = LD; 2024 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2025 // For PIC, the sequence is: 2026 // BRIND(load(Jumptable + index) + RelocBase) 2027 // RelocBase can be JumpTable, GOT or some sort of global base. 2028 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 2029 TLI.getPICJumpTableRelocBase(Table, DAG)); 2030 } 2031 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 2032 } 2033 } 2034 break; 2035 case ISD::BRCOND: 2036 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2037 // Ensure that libcalls are emitted before a return. 2038 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2039 Tmp1 = LegalizeOp(Tmp1); 2040 LastCALLSEQ_END = DAG.getEntryNode(); 2041 2042 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2043 case Expand: assert(0 && "It's impossible to expand bools"); 2044 case Legal: 2045 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 2046 break; 2047 case Promote: { 2048 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 2049 2050 // The top bits of the promoted condition are not necessarily zero, ensure 2051 // that the value is properly zero extended. 2052 unsigned BitWidth = Tmp2.getValueSizeInBits(); 2053 if (!DAG.MaskedValueIsZero(Tmp2, 2054 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2055 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 2056 break; 2057 } 2058 } 2059 2060 // Basic block destination (Op#2) is always legal. 2061 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2062 2063 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 2064 default: assert(0 && "This action is not supported yet!"); 2065 case TargetLowering::Legal: break; 2066 case TargetLowering::Custom: 2067 Tmp1 = TLI.LowerOperation(Result, DAG); 2068 if (Tmp1.getNode()) Result = Tmp1; 2069 break; 2070 case TargetLowering::Expand: 2071 // Expand brcond's setcc into its constituent parts and create a BR_CC 2072 // Node. 2073 if (Tmp2.getOpcode() == ISD::SETCC) { 2074 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 2075 Tmp2.getOperand(0), Tmp2.getOperand(1), 2076 Node->getOperand(2)); 2077 } else { 2078 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 2079 DAG.getCondCode(ISD::SETNE), Tmp2, 2080 DAG.getConstant(0, Tmp2.getValueType()), 2081 Node->getOperand(2)); 2082 } 2083 break; 2084 } 2085 break; 2086 case ISD::BR_CC: 2087 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2088 // Ensure that libcalls are emitted before a branch. 2089 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2090 Tmp1 = LegalizeOp(Tmp1); 2091 Tmp2 = Node->getOperand(2); // LHS 2092 Tmp3 = Node->getOperand(3); // RHS 2093 Tmp4 = Node->getOperand(1); // CC 2094 2095 LegalizeSetCC(TLI.getSetCCResultType(Tmp2), Tmp2, Tmp3, Tmp4); 2096 LastCALLSEQ_END = DAG.getEntryNode(); 2097 2098 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 2099 // the LHS is a legal SETCC itself. In this case, we need to compare 2100 // the result against zero to select between true and false values. 2101 if (Tmp3.getNode() == 0) { 2102 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 2103 Tmp4 = DAG.getCondCode(ISD::SETNE); 2104 } 2105 2106 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 2107 Node->getOperand(4)); 2108 2109 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 2110 default: assert(0 && "Unexpected action for BR_CC!"); 2111 case TargetLowering::Legal: break; 2112 case TargetLowering::Custom: 2113 Tmp4 = TLI.LowerOperation(Result, DAG); 2114 if (Tmp4.getNode()) Result = Tmp4; 2115 break; 2116 } 2117 break; 2118 case ISD::LOAD: { 2119 LoadSDNode *LD = cast<LoadSDNode>(Node); 2120 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 2121 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 2122 2123 ISD::LoadExtType ExtType = LD->getExtensionType(); 2124 if (ExtType == ISD::NON_EXTLOAD) { 2125 MVT VT = Node->getValueType(0); 2126 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2127 Tmp3 = Result.getValue(0); 2128 Tmp4 = Result.getValue(1); 2129 2130 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 2131 default: assert(0 && "This action is not supported yet!"); 2132 case TargetLowering::Legal: 2133 // If this is an unaligned load and the target doesn't support it, 2134 // expand it. 2135 if (!TLI.allowsUnalignedMemoryAccesses()) { 2136 unsigned ABIAlignment = TLI.getTargetData()-> 2137 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2138 if (LD->getAlignment() < ABIAlignment){ 2139 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 2140 TLI); 2141 Tmp3 = Result.getOperand(0); 2142 Tmp4 = Result.getOperand(1); 2143 Tmp3 = LegalizeOp(Tmp3); 2144 Tmp4 = LegalizeOp(Tmp4); 2145 } 2146 } 2147 break; 2148 case TargetLowering::Custom: 2149 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 2150 if (Tmp1.getNode()) { 2151 Tmp3 = LegalizeOp(Tmp1); 2152 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 2153 } 2154 break; 2155 case TargetLowering::Promote: { 2156 // Only promote a load of vector type to another. 2157 assert(VT.isVector() && "Cannot promote this load!"); 2158 // Change base type to a different vector type. 2159 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 2160 2161 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 2162 LD->getSrcValueOffset(), 2163 LD->isVolatile(), LD->getAlignment()); 2164 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 2165 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 2166 break; 2167 } 2168 } 2169 // Since loads produce two values, make sure to remember that we 2170 // legalized both of them. 2171 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 2172 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 2173 return Op.getResNo() ? Tmp4 : Tmp3; 2174 } else { 2175 MVT SrcVT = LD->getMemoryVT(); 2176 unsigned SrcWidth = SrcVT.getSizeInBits(); 2177 int SVOffset = LD->getSrcValueOffset(); 2178 unsigned Alignment = LD->getAlignment(); 2179 bool isVolatile = LD->isVolatile(); 2180 2181 if (SrcWidth != SrcVT.getStoreSizeInBits() && 2182 // Some targets pretend to have an i1 loading operation, and actually 2183 // load an i8. This trick is correct for ZEXTLOAD because the top 7 2184 // bits are guaranteed to be zero; it helps the optimizers understand 2185 // that these bits are zero. It is also useful for EXTLOAD, since it 2186 // tells the optimizers that those bits are undefined. It would be 2187 // nice to have an effective generic way of getting these benefits... 2188 // Until such a way is found, don't insist on promoting i1 here. 2189 (SrcVT != MVT::i1 || 2190 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 2191 // Promote to a byte-sized load if not loading an integral number of 2192 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 2193 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 2194 MVT NVT = MVT::getIntegerVT(NewWidth); 2195 SDValue Ch; 2196 2197 // The extra bits are guaranteed to be zero, since we stored them that 2198 // way. A zext load from NVT thus automatically gives zext from SrcVT. 2199 2200 ISD::LoadExtType NewExtType = 2201 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 2202 2203 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), 2204 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 2205 NVT, isVolatile, Alignment); 2206 2207 Ch = Result.getValue(1); // The chain. 2208 2209 if (ExtType == ISD::SEXTLOAD) 2210 // Having the top bits zero doesn't help when sign extending. 2211 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2212 Result, DAG.getValueType(SrcVT)); 2213 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 2214 // All the top bits are guaranteed to be zero - inform the optimizers. 2215 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, 2216 DAG.getValueType(SrcVT)); 2217 2218 Tmp1 = LegalizeOp(Result); 2219 Tmp2 = LegalizeOp(Ch); 2220 } else if (SrcWidth & (SrcWidth - 1)) { 2221 // If not loading a power-of-2 number of bits, expand as two loads. 2222 assert(SrcVT.isExtended() && !SrcVT.isVector() && 2223 "Unsupported extload!"); 2224 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 2225 assert(RoundWidth < SrcWidth); 2226 unsigned ExtraWidth = SrcWidth - RoundWidth; 2227 assert(ExtraWidth < RoundWidth); 2228 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2229 "Load size not an integral number of bytes!"); 2230 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2231 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2232 SDValue Lo, Hi, Ch; 2233 unsigned IncrementSize; 2234 2235 if (TLI.isLittleEndian()) { 2236 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2237 // Load the bottom RoundWidth bits. 2238 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2239 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2240 Alignment); 2241 2242 // Load the remaining ExtraWidth bits. 2243 IncrementSize = RoundWidth / 8; 2244 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2245 DAG.getIntPtrConstant(IncrementSize)); 2246 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2247 LD->getSrcValue(), SVOffset + IncrementSize, 2248 ExtraVT, isVolatile, 2249 MinAlign(Alignment, IncrementSize)); 2250 2251 // Build a factor node to remember that this load is independent of the 2252 // other one. 2253 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2254 Hi.getValue(1)); 2255 2256 // Move the top bits to the right place. 2257 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2258 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2259 2260 // Join the hi and lo parts. 2261 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2262 } else { 2263 // Big endian - avoid unaligned loads. 2264 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2265 // Load the top RoundWidth bits. 2266 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2267 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2268 Alignment); 2269 2270 // Load the remaining ExtraWidth bits. 2271 IncrementSize = RoundWidth / 8; 2272 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2273 DAG.getIntPtrConstant(IncrementSize)); 2274 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2275 LD->getSrcValue(), SVOffset + IncrementSize, 2276 ExtraVT, isVolatile, 2277 MinAlign(Alignment, IncrementSize)); 2278 2279 // Build a factor node to remember that this load is independent of the 2280 // other one. 2281 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2282 Hi.getValue(1)); 2283 2284 // Move the top bits to the right place. 2285 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2286 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2287 2288 // Join the hi and lo parts. 2289 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2290 } 2291 2292 Tmp1 = LegalizeOp(Result); 2293 Tmp2 = LegalizeOp(Ch); 2294 } else { 2295 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 2296 default: assert(0 && "This action is not supported yet!"); 2297 case TargetLowering::Custom: 2298 isCustom = true; 2299 // FALLTHROUGH 2300 case TargetLowering::Legal: 2301 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2302 Tmp1 = Result.getValue(0); 2303 Tmp2 = Result.getValue(1); 2304 2305 if (isCustom) { 2306 Tmp3 = TLI.LowerOperation(Result, DAG); 2307 if (Tmp3.getNode()) { 2308 Tmp1 = LegalizeOp(Tmp3); 2309 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2310 } 2311 } else { 2312 // If this is an unaligned load and the target doesn't support it, 2313 // expand it. 2314 if (!TLI.allowsUnalignedMemoryAccesses()) { 2315 unsigned ABIAlignment = TLI.getTargetData()-> 2316 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2317 if (LD->getAlignment() < ABIAlignment){ 2318 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 2319 TLI); 2320 Tmp1 = Result.getOperand(0); 2321 Tmp2 = Result.getOperand(1); 2322 Tmp1 = LegalizeOp(Tmp1); 2323 Tmp2 = LegalizeOp(Tmp2); 2324 } 2325 } 2326 } 2327 break; 2328 case TargetLowering::Expand: 2329 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2330 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2331 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 2332 LD->getSrcValueOffset(), 2333 LD->isVolatile(), LD->getAlignment()); 2334 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 2335 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2336 Tmp2 = LegalizeOp(Load.getValue(1)); 2337 break; 2338 } 2339 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2340 // Turn the unsupported load into an EXTLOAD followed by an explicit 2341 // zero/sign extend inreg. 2342 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2343 Tmp1, Tmp2, LD->getSrcValue(), 2344 LD->getSrcValueOffset(), SrcVT, 2345 LD->isVolatile(), LD->getAlignment()); 2346 SDValue ValRes; 2347 if (ExtType == ISD::SEXTLOAD) 2348 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2349 Result, DAG.getValueType(SrcVT)); 2350 else 2351 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 2352 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2353 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2354 break; 2355 } 2356 } 2357 2358 // Since loads produce two values, make sure to remember that we legalized 2359 // both of them. 2360 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2361 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2362 return Op.getResNo() ? Tmp2 : Tmp1; 2363 } 2364 } 2365 case ISD::EXTRACT_ELEMENT: { 2366 MVT OpTy = Node->getOperand(0).getValueType(); 2367 switch (getTypeAction(OpTy)) { 2368 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2369 case Legal: 2370 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2371 // 1 -> Hi 2372 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 2373 DAG.getConstant(OpTy.getSizeInBits()/2, 2374 TLI.getShiftAmountTy())); 2375 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 2376 } else { 2377 // 0 -> Lo 2378 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 2379 Node->getOperand(0)); 2380 } 2381 break; 2382 case Expand: 2383 // Get both the low and high parts. 2384 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2385 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) 2386 Result = Tmp2; // 1 -> Hi 2387 else 2388 Result = Tmp1; // 0 -> Lo 2389 break; 2390 } 2391 break; 2392 } 2393 2394 case ISD::CopyToReg: 2395 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2396 2397 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2398 "Register type must be legal!"); 2399 // Legalize the incoming value (must be a legal type). 2400 Tmp2 = LegalizeOp(Node->getOperand(2)); 2401 if (Node->getNumValues() == 1) { 2402 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2403 } else { 2404 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2405 if (Node->getNumOperands() == 4) { 2406 Tmp3 = LegalizeOp(Node->getOperand(3)); 2407 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2408 Tmp3); 2409 } else { 2410 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2411 } 2412 2413 // Since this produces two values, make sure to remember that we legalized 2414 // both of them. 2415 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 2416 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 2417 return Result; 2418 } 2419 break; 2420 2421 case ISD::RET: 2422 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2423 2424 // Ensure that libcalls are emitted before a return. 2425 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2426 Tmp1 = LegalizeOp(Tmp1); 2427 LastCALLSEQ_END = DAG.getEntryNode(); 2428 2429 switch (Node->getNumOperands()) { 2430 case 3: // ret val 2431 Tmp2 = Node->getOperand(1); 2432 Tmp3 = Node->getOperand(2); // Signness 2433 switch (getTypeAction(Tmp2.getValueType())) { 2434 case Legal: 2435 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2436 break; 2437 case Expand: 2438 if (!Tmp2.getValueType().isVector()) { 2439 SDValue Lo, Hi; 2440 ExpandOp(Tmp2, Lo, Hi); 2441 2442 // Big endian systems want the hi reg first. 2443 if (TLI.isBigEndian()) 2444 std::swap(Lo, Hi); 2445 2446 if (Hi.getNode()) 2447 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2448 else 2449 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 2450 Result = LegalizeOp(Result); 2451 } else { 2452 SDNode *InVal = Tmp2.getNode(); 2453 int InIx = Tmp2.getResNo(); 2454 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 2455 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 2456 2457 // Figure out if there is a simple type corresponding to this Vector 2458 // type. If so, convert to the vector type. 2459 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2460 if (TLI.isTypeLegal(TVT)) { 2461 // Turn this into a return of the vector type. 2462 Tmp2 = LegalizeOp(Tmp2); 2463 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2464 } else if (NumElems == 1) { 2465 // Turn this into a return of the scalar type. 2466 Tmp2 = ScalarizeVectorOp(Tmp2); 2467 Tmp2 = LegalizeOp(Tmp2); 2468 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2469 2470 // FIXME: Returns of gcc generic vectors smaller than a legal type 2471 // should be returned in integer registers! 2472 2473 // The scalarized value type may not be legal, e.g. it might require 2474 // promotion or expansion. Relegalize the return. 2475 Result = LegalizeOp(Result); 2476 } else { 2477 // FIXME: Returns of gcc generic vectors larger than a legal vector 2478 // type should be returned by reference! 2479 SDValue Lo, Hi; 2480 SplitVectorOp(Tmp2, Lo, Hi); 2481 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2482 Result = LegalizeOp(Result); 2483 } 2484 } 2485 break; 2486 case Promote: 2487 Tmp2 = PromoteOp(Node->getOperand(1)); 2488 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2489 Result = LegalizeOp(Result); 2490 break; 2491 } 2492 break; 2493 case 1: // ret void 2494 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2495 break; 2496 default: { // ret <values> 2497 SmallVector<SDValue, 8> NewValues; 2498 NewValues.push_back(Tmp1); 2499 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2500 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2501 case Legal: 2502 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2503 NewValues.push_back(Node->getOperand(i+1)); 2504 break; 2505 case Expand: { 2506 SDValue Lo, Hi; 2507 assert(!Node->getOperand(i).getValueType().isExtended() && 2508 "FIXME: TODO: implement returning non-legal vector types!"); 2509 ExpandOp(Node->getOperand(i), Lo, Hi); 2510 NewValues.push_back(Lo); 2511 NewValues.push_back(Node->getOperand(i+1)); 2512 if (Hi.getNode()) { 2513 NewValues.push_back(Hi); 2514 NewValues.push_back(Node->getOperand(i+1)); 2515 } 2516 break; 2517 } 2518 case Promote: 2519 assert(0 && "Can't promote multiple return value yet!"); 2520 } 2521 2522 if (NewValues.size() == Node->getNumOperands()) 2523 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2524 else 2525 Result = DAG.getNode(ISD::RET, MVT::Other, 2526 &NewValues[0], NewValues.size()); 2527 break; 2528 } 2529 } 2530 2531 if (Result.getOpcode() == ISD::RET) { 2532 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2533 default: assert(0 && "This action is not supported yet!"); 2534 case TargetLowering::Legal: break; 2535 case TargetLowering::Custom: 2536 Tmp1 = TLI.LowerOperation(Result, DAG); 2537 if (Tmp1.getNode()) Result = Tmp1; 2538 break; 2539 } 2540 } 2541 break; 2542 case ISD::STORE: { 2543 StoreSDNode *ST = cast<StoreSDNode>(Node); 2544 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2545 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2546 int SVOffset = ST->getSrcValueOffset(); 2547 unsigned Alignment = ST->getAlignment(); 2548 bool isVolatile = ST->isVolatile(); 2549 2550 if (!ST->isTruncatingStore()) { 2551 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2552 // FIXME: We shouldn't do this for TargetConstantFP's. 2553 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2554 // to phase ordering between legalized code and the dag combiner. This 2555 // probably means that we need to integrate dag combiner and legalizer 2556 // together. 2557 // We generally can't do this one for long doubles. 2558 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2559 if (CFP->getValueType(0) == MVT::f32 && 2560 getTypeAction(MVT::i32) == Legal) { 2561 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2562 bitcastToAPInt().zextOrTrunc(32), 2563 MVT::i32); 2564 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2565 SVOffset, isVolatile, Alignment); 2566 break; 2567 } else if (CFP->getValueType(0) == MVT::f64) { 2568 // If this target supports 64-bit registers, do a single 64-bit store. 2569 if (getTypeAction(MVT::i64) == Legal) { 2570 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 2571 zextOrTrunc(64), MVT::i64); 2572 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2573 SVOffset, isVolatile, Alignment); 2574 break; 2575 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 2576 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2577 // stores. If the target supports neither 32- nor 64-bits, this 2578 // xform is certainly not worth it. 2579 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 2580 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2581 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2582 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2583 2584 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2585 SVOffset, isVolatile, Alignment); 2586 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2587 DAG.getIntPtrConstant(4)); 2588 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2589 isVolatile, MinAlign(Alignment, 4U)); 2590 2591 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2592 break; 2593 } 2594 } 2595 } 2596 2597 switch (getTypeAction(ST->getMemoryVT())) { 2598 case Legal: { 2599 Tmp3 = LegalizeOp(ST->getValue()); 2600 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2601 ST->getOffset()); 2602 2603 MVT VT = Tmp3.getValueType(); 2604 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2605 default: assert(0 && "This action is not supported yet!"); 2606 case TargetLowering::Legal: 2607 // If this is an unaligned store and the target doesn't support it, 2608 // expand it. 2609 if (!TLI.allowsUnalignedMemoryAccesses()) { 2610 unsigned ABIAlignment = TLI.getTargetData()-> 2611 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2612 if (ST->getAlignment() < ABIAlignment) 2613 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 2614 TLI); 2615 } 2616 break; 2617 case TargetLowering::Custom: 2618 Tmp1 = TLI.LowerOperation(Result, DAG); 2619 if (Tmp1.getNode()) Result = Tmp1; 2620 break; 2621 case TargetLowering::Promote: 2622 assert(VT.isVector() && "Unknown legal promote case!"); 2623 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2624 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2625 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2626 ST->getSrcValue(), SVOffset, isVolatile, 2627 Alignment); 2628 break; 2629 } 2630 break; 2631 } 2632 case Promote: 2633 if (!ST->getMemoryVT().isVector()) { 2634 // Truncate the value and store the result. 2635 Tmp3 = PromoteOp(ST->getValue()); 2636 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2637 SVOffset, ST->getMemoryVT(), 2638 isVolatile, Alignment); 2639 break; 2640 } 2641 // Fall thru to expand for vector 2642 case Expand: { 2643 unsigned IncrementSize = 0; 2644 SDValue Lo, Hi; 2645 2646 // If this is a vector type, then we have to calculate the increment as 2647 // the product of the element size in bytes, and the number of elements 2648 // in the high half of the vector. 2649 if (ST->getValue().getValueType().isVector()) { 2650 SDNode *InVal = ST->getValue().getNode(); 2651 int InIx = ST->getValue().getResNo(); 2652 MVT InVT = InVal->getValueType(InIx); 2653 unsigned NumElems = InVT.getVectorNumElements(); 2654 MVT EVT = InVT.getVectorElementType(); 2655 2656 // Figure out if there is a simple type corresponding to this Vector 2657 // type. If so, convert to the vector type. 2658 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2659 if (TLI.isTypeLegal(TVT)) { 2660 // Turn this into a normal store of the vector type. 2661 Tmp3 = LegalizeOp(ST->getValue()); 2662 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2663 SVOffset, isVolatile, Alignment); 2664 Result = LegalizeOp(Result); 2665 break; 2666 } else if (NumElems == 1) { 2667 // Turn this into a normal store of the scalar type. 2668 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2669 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2670 SVOffset, isVolatile, Alignment); 2671 // The scalarized value type may not be legal, e.g. it might require 2672 // promotion or expansion. Relegalize the scalar store. 2673 Result = LegalizeOp(Result); 2674 break; 2675 } else { 2676 // Check if we have widen this node with another value 2677 std::map<SDValue, SDValue>::iterator I = 2678 WidenNodes.find(ST->getValue()); 2679 if (I != WidenNodes.end()) { 2680 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2); 2681 break; 2682 } 2683 else { 2684 SplitVectorOp(ST->getValue(), Lo, Hi); 2685 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() * 2686 EVT.getSizeInBits()/8; 2687 } 2688 } 2689 } else { 2690 ExpandOp(ST->getValue(), Lo, Hi); 2691 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0; 2692 2693 if (Hi.getNode() && TLI.isBigEndian()) 2694 std::swap(Lo, Hi); 2695 } 2696 2697 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2698 SVOffset, isVolatile, Alignment); 2699 2700 if (Hi.getNode() == NULL) { 2701 // Must be int <-> float one-to-one expansion. 2702 Result = Lo; 2703 break; 2704 } 2705 2706 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2707 DAG.getIntPtrConstant(IncrementSize)); 2708 assert(isTypeLegal(Tmp2.getValueType()) && 2709 "Pointers must be legal!"); 2710 SVOffset += IncrementSize; 2711 Alignment = MinAlign(Alignment, IncrementSize); 2712 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2713 SVOffset, isVolatile, Alignment); 2714 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2715 break; 2716 } // case Expand 2717 } 2718 } else { 2719 switch (getTypeAction(ST->getValue().getValueType())) { 2720 case Legal: 2721 Tmp3 = LegalizeOp(ST->getValue()); 2722 break; 2723 case Promote: 2724 if (!ST->getValue().getValueType().isVector()) { 2725 // We can promote the value, the truncstore will still take care of it. 2726 Tmp3 = PromoteOp(ST->getValue()); 2727 break; 2728 } 2729 // Vector case falls through to expand 2730 case Expand: 2731 // Just store the low part. This may become a non-trunc store, so make 2732 // sure to use getTruncStore, not UpdateNodeOperands below. 2733 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2734 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2735 SVOffset, MVT::i8, isVolatile, Alignment); 2736 } 2737 2738 MVT StVT = ST->getMemoryVT(); 2739 unsigned StWidth = StVT.getSizeInBits(); 2740 2741 if (StWidth != StVT.getStoreSizeInBits()) { 2742 // Promote to a byte-sized store with upper bits zero if not 2743 // storing an integral number of bytes. For example, promote 2744 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2745 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 2746 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); 2747 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2748 SVOffset, NVT, isVolatile, Alignment); 2749 } else if (StWidth & (StWidth - 1)) { 2750 // If not storing a power-of-2 number of bits, expand as two stores. 2751 assert(StVT.isExtended() && !StVT.isVector() && 2752 "Unsupported truncstore!"); 2753 unsigned RoundWidth = 1 << Log2_32(StWidth); 2754 assert(RoundWidth < StWidth); 2755 unsigned ExtraWidth = StWidth - RoundWidth; 2756 assert(ExtraWidth < RoundWidth); 2757 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2758 "Store size not an integral number of bytes!"); 2759 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2760 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2761 SDValue Lo, Hi; 2762 unsigned IncrementSize; 2763 2764 if (TLI.isLittleEndian()) { 2765 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2766 // Store the bottom RoundWidth bits. 2767 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2768 SVOffset, RoundVT, 2769 isVolatile, Alignment); 2770 2771 // Store the remaining ExtraWidth bits. 2772 IncrementSize = RoundWidth / 8; 2773 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2774 DAG.getIntPtrConstant(IncrementSize)); 2775 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2776 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2777 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2778 SVOffset + IncrementSize, ExtraVT, isVolatile, 2779 MinAlign(Alignment, IncrementSize)); 2780 } else { 2781 // Big endian - avoid unaligned stores. 2782 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2783 // Store the top RoundWidth bits. 2784 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2785 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2786 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, 2787 RoundVT, isVolatile, Alignment); 2788 2789 // Store the remaining ExtraWidth bits. 2790 IncrementSize = RoundWidth / 8; 2791 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2792 DAG.getIntPtrConstant(IncrementSize)); 2793 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2794 SVOffset + IncrementSize, ExtraVT, isVolatile, 2795 MinAlign(Alignment, IncrementSize)); 2796 } 2797 2798 // The order of the stores doesn't matter. 2799 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2800 } else { 2801 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2802 Tmp2 != ST->getBasePtr()) 2803 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2804 ST->getOffset()); 2805 2806 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2807 default: assert(0 && "This action is not supported yet!"); 2808 case TargetLowering::Legal: 2809 // If this is an unaligned store and the target doesn't support it, 2810 // expand it. 2811 if (!TLI.allowsUnalignedMemoryAccesses()) { 2812 unsigned ABIAlignment = TLI.getTargetData()-> 2813 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2814 if (ST->getAlignment() < ABIAlignment) 2815 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 2816 TLI); 2817 } 2818 break; 2819 case TargetLowering::Custom: 2820 Result = TLI.LowerOperation(Result, DAG); 2821 break; 2822 case Expand: 2823 // TRUNCSTORE:i16 i32 -> STORE i16 2824 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2825 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); 2826 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, 2827 isVolatile, Alignment); 2828 break; 2829 } 2830 } 2831 } 2832 break; 2833 } 2834 case ISD::PCMARKER: 2835 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2836 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2837 break; 2838 case ISD::STACKSAVE: 2839 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2840 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2841 Tmp1 = Result.getValue(0); 2842 Tmp2 = Result.getValue(1); 2843 2844 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2845 default: assert(0 && "This action is not supported yet!"); 2846 case TargetLowering::Legal: break; 2847 case TargetLowering::Custom: 2848 Tmp3 = TLI.LowerOperation(Result, DAG); 2849 if (Tmp3.getNode()) { 2850 Tmp1 = LegalizeOp(Tmp3); 2851 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2852 } 2853 break; 2854 case TargetLowering::Expand: 2855 // Expand to CopyFromReg if the target set 2856 // StackPointerRegisterToSaveRestore. 2857 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2858 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2859 Node->getValueType(0)); 2860 Tmp2 = Tmp1.getValue(1); 2861 } else { 2862 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2863 Tmp2 = Node->getOperand(0); 2864 } 2865 break; 2866 } 2867 2868 // Since stacksave produce two values, make sure to remember that we 2869 // legalized both of them. 2870 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2871 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2872 return Op.getResNo() ? Tmp2 : Tmp1; 2873 2874 case ISD::STACKRESTORE: 2875 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2876 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2877 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2878 2879 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2880 default: assert(0 && "This action is not supported yet!"); 2881 case TargetLowering::Legal: break; 2882 case TargetLowering::Custom: 2883 Tmp1 = TLI.LowerOperation(Result, DAG); 2884 if (Tmp1.getNode()) Result = Tmp1; 2885 break; 2886 case TargetLowering::Expand: 2887 // Expand to CopyToReg if the target set 2888 // StackPointerRegisterToSaveRestore. 2889 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2890 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2891 } else { 2892 Result = Tmp1; 2893 } 2894 break; 2895 } 2896 break; 2897 2898 case ISD::READCYCLECOUNTER: 2899 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2900 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2901 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2902 Node->getValueType(0))) { 2903 default: assert(0 && "This action is not supported yet!"); 2904 case TargetLowering::Legal: 2905 Tmp1 = Result.getValue(0); 2906 Tmp2 = Result.getValue(1); 2907 break; 2908 case TargetLowering::Custom: 2909 Result = TLI.LowerOperation(Result, DAG); 2910 Tmp1 = LegalizeOp(Result.getValue(0)); 2911 Tmp2 = LegalizeOp(Result.getValue(1)); 2912 break; 2913 } 2914 2915 // Since rdcc produce two values, make sure to remember that we legalized 2916 // both of them. 2917 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2918 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2919 return Result; 2920 2921 case ISD::SELECT: 2922 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2923 case Expand: assert(0 && "It's impossible to expand bools"); 2924 case Legal: 2925 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2926 break; 2927 case Promote: { 2928 assert(!Node->getOperand(0).getValueType().isVector() && "not possible"); 2929 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2930 // Make sure the condition is either zero or one. 2931 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2932 if (!DAG.MaskedValueIsZero(Tmp1, 2933 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2934 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2935 break; 2936 } 2937 } 2938 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2939 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2940 2941 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2942 2943 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2944 default: assert(0 && "This action is not supported yet!"); 2945 case TargetLowering::Legal: break; 2946 case TargetLowering::Custom: { 2947 Tmp1 = TLI.LowerOperation(Result, DAG); 2948 if (Tmp1.getNode()) Result = Tmp1; 2949 break; 2950 } 2951 case TargetLowering::Expand: 2952 if (Tmp1.getOpcode() == ISD::SETCC) { 2953 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2954 Tmp2, Tmp3, 2955 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2956 } else { 2957 Result = DAG.getSelectCC(Tmp1, 2958 DAG.getConstant(0, Tmp1.getValueType()), 2959 Tmp2, Tmp3, ISD::SETNE); 2960 } 2961 break; 2962 case TargetLowering::Promote: { 2963 MVT NVT = 2964 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2965 unsigned ExtOp, TruncOp; 2966 if (Tmp2.getValueType().isVector()) { 2967 ExtOp = ISD::BIT_CONVERT; 2968 TruncOp = ISD::BIT_CONVERT; 2969 } else if (Tmp2.getValueType().isInteger()) { 2970 ExtOp = ISD::ANY_EXTEND; 2971 TruncOp = ISD::TRUNCATE; 2972 } else { 2973 ExtOp = ISD::FP_EXTEND; 2974 TruncOp = ISD::FP_ROUND; 2975 } 2976 // Promote each of the values to the new type. 2977 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2978 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2979 // Perform the larger operation, then round down. 2980 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2981 if (TruncOp != ISD::FP_ROUND) 2982 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2983 else 2984 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2985 DAG.getIntPtrConstant(0)); 2986 break; 2987 } 2988 } 2989 break; 2990 case ISD::SELECT_CC: { 2991 Tmp1 = Node->getOperand(0); // LHS 2992 Tmp2 = Node->getOperand(1); // RHS 2993 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2994 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2995 SDValue CC = Node->getOperand(4); 2996 2997 LegalizeSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, CC); 2998 2999 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 3000 // the LHS is a legal SETCC itself. In this case, we need to compare 3001 // the result against zero to select between true and false values. 3002 if (Tmp2.getNode() == 0) { 3003 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3004 CC = DAG.getCondCode(ISD::SETNE); 3005 } 3006 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 3007 3008 // Everything is legal, see if we should expand this op or something. 3009 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 3010 default: assert(0 && "This action is not supported yet!"); 3011 case TargetLowering::Legal: break; 3012 case TargetLowering::Custom: 3013 Tmp1 = TLI.LowerOperation(Result, DAG); 3014 if (Tmp1.getNode()) Result = Tmp1; 3015 break; 3016 } 3017 break; 3018 } 3019 case ISD::SETCC: 3020 Tmp1 = Node->getOperand(0); 3021 Tmp2 = Node->getOperand(1); 3022 Tmp3 = Node->getOperand(2); 3023 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3); 3024 3025 // If we had to Expand the SetCC operands into a SELECT node, then it may 3026 // not always be possible to return a true LHS & RHS. In this case, just 3027 // return the value we legalized, returned in the LHS 3028 if (Tmp2.getNode() == 0) { 3029 Result = Tmp1; 3030 break; 3031 } 3032 3033 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 3034 default: assert(0 && "Cannot handle this action for SETCC yet!"); 3035 case TargetLowering::Custom: 3036 isCustom = true; 3037 // FALLTHROUGH. 3038 case TargetLowering::Legal: 3039 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3040 if (isCustom) { 3041 Tmp4 = TLI.LowerOperation(Result, DAG); 3042 if (Tmp4.getNode()) Result = Tmp4; 3043 } 3044 break; 3045 case TargetLowering::Promote: { 3046 // First step, figure out the appropriate operation to use. 3047 // Allow SETCC to not be supported for all legal data types 3048 // Mostly this targets FP 3049 MVT NewInTy = Node->getOperand(0).getValueType(); 3050 MVT OldVT = NewInTy; OldVT = OldVT; 3051 3052 // Scan for the appropriate larger type to use. 3053 while (1) { 3054 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 3055 3056 assert(NewInTy.isInteger() == OldVT.isInteger() && 3057 "Fell off of the edge of the integer world"); 3058 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 3059 "Fell off of the edge of the floating point world"); 3060 3061 // If the target supports SETCC of this type, use it. 3062 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 3063 break; 3064 } 3065 if (NewInTy.isInteger()) 3066 assert(0 && "Cannot promote Legal Integer SETCC yet"); 3067 else { 3068 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 3069 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 3070 } 3071 Tmp1 = LegalizeOp(Tmp1); 3072 Tmp2 = LegalizeOp(Tmp2); 3073 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3074 Result = LegalizeOp(Result); 3075 break; 3076 } 3077 case TargetLowering::Expand: 3078 // Expand a setcc node into a select_cc of the same condition, lhs, and 3079 // rhs that selects between const 1 (true) and const 0 (false). 3080 MVT VT = Node->getValueType(0); 3081 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 3082 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3083 Tmp3); 3084 break; 3085 } 3086 break; 3087 case ISD::VSETCC: { 3088 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3089 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3090 SDValue CC = Node->getOperand(2); 3091 3092 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC); 3093 3094 // Everything is legal, see if we should expand this op or something. 3095 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) { 3096 default: assert(0 && "This action is not supported yet!"); 3097 case TargetLowering::Legal: break; 3098 case TargetLowering::Custom: 3099 Tmp1 = TLI.LowerOperation(Result, DAG); 3100 if (Tmp1.getNode()) Result = Tmp1; 3101 break; 3102 case TargetLowering::Expand: { 3103 // Unroll into a nasty set of scalar code for now. 3104 MVT VT = Node->getValueType(0); 3105 unsigned NumElems = VT.getVectorNumElements(); 3106 MVT EltVT = VT.getVectorElementType(); 3107 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType(); 3108 SmallVector<SDValue, 8> Ops(NumElems); 3109 for (unsigned i = 0; i < NumElems; ++i) { 3110 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT, 3111 Tmp1, DAG.getIntPtrConstant(i)); 3112 Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(In1), In1, 3113 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT, 3114 Tmp2, DAG.getIntPtrConstant(i)), 3115 CC); 3116 Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i], 3117 DAG.getConstant(EltVT.getIntegerVTBitMask(),EltVT), 3118 DAG.getConstant(0, EltVT)); 3119 } 3120 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElems); 3121 break; 3122 } 3123 } 3124 break; 3125 } 3126 3127 case ISD::SHL_PARTS: 3128 case ISD::SRA_PARTS: 3129 case ISD::SRL_PARTS: { 3130 SmallVector<SDValue, 8> Ops; 3131 bool Changed = false; 3132 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3133 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3134 Changed |= Ops.back() != Node->getOperand(i); 3135 } 3136 if (Changed) 3137 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 3138 3139 switch (TLI.getOperationAction(Node->getOpcode(), 3140 Node->getValueType(0))) { 3141 default: assert(0 && "This action is not supported yet!"); 3142 case TargetLowering::Legal: break; 3143 case TargetLowering::Custom: 3144 Tmp1 = TLI.LowerOperation(Result, DAG); 3145 if (Tmp1.getNode()) { 3146 SDValue Tmp2, RetVal(0, 0); 3147 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 3148 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 3149 AddLegalizedOperand(SDValue(Node, i), Tmp2); 3150 if (i == Op.getResNo()) 3151 RetVal = Tmp2; 3152 } 3153 assert(RetVal.getNode() && "Illegal result number"); 3154 return RetVal; 3155 } 3156 break; 3157 } 3158 3159 // Since these produce multiple values, make sure to remember that we 3160 // legalized all of them. 3161 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3162 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i)); 3163 return Result.getValue(Op.getResNo()); 3164 } 3165 3166 // Binary operators 3167 case ISD::ADD: 3168 case ISD::SUB: 3169 case ISD::MUL: 3170 case ISD::MULHS: 3171 case ISD::MULHU: 3172 case ISD::UDIV: 3173 case ISD::SDIV: 3174 case ISD::AND: 3175 case ISD::OR: 3176 case ISD::XOR: 3177 case ISD::SHL: 3178 case ISD::SRL: 3179 case ISD::SRA: 3180 case ISD::FADD: 3181 case ISD::FSUB: 3182 case ISD::FMUL: 3183 case ISD::FDIV: 3184 case ISD::FPOW: 3185 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3186 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3187 case Expand: assert(0 && "Not possible"); 3188 case Legal: 3189 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3190 break; 3191 case Promote: 3192 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3193 break; 3194 } 3195 3196 if ((Node->getOpcode() == ISD::SHL || 3197 Node->getOpcode() == ISD::SRL || 3198 Node->getOpcode() == ISD::SRA) && 3199 !Node->getValueType(0).isVector()) { 3200 Tmp2 = LegalizeShiftAmount(Tmp2); 3201 } 3202 3203 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3204 3205 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3206 default: assert(0 && "BinOp legalize operation not supported"); 3207 case TargetLowering::Legal: break; 3208 case TargetLowering::Custom: 3209 Tmp1 = TLI.LowerOperation(Result, DAG); 3210 if (Tmp1.getNode()) { 3211 Result = Tmp1; 3212 break; 3213 } 3214 // Fall through if the custom lower can't deal with the operation 3215 case TargetLowering::Expand: { 3216 MVT VT = Op.getValueType(); 3217 3218 // See if multiply or divide can be lowered using two-result operations. 3219 SDVTList VTs = DAG.getVTList(VT, VT); 3220 if (Node->getOpcode() == ISD::MUL) { 3221 // We just need the low half of the multiply; try both the signed 3222 // and unsigned forms. If the target supports both SMUL_LOHI and 3223 // UMUL_LOHI, form a preference by checking which forms of plain 3224 // MULH it supports. 3225 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 3226 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 3227 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 3228 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 3229 unsigned OpToUse = 0; 3230 if (HasSMUL_LOHI && !HasMULHS) { 3231 OpToUse = ISD::SMUL_LOHI; 3232 } else if (HasUMUL_LOHI && !HasMULHU) { 3233 OpToUse = ISD::UMUL_LOHI; 3234 } else if (HasSMUL_LOHI) { 3235 OpToUse = ISD::SMUL_LOHI; 3236 } else if (HasUMUL_LOHI) { 3237 OpToUse = ISD::UMUL_LOHI; 3238 } 3239 if (OpToUse) { 3240 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0); 3241 break; 3242 } 3243 } 3244 if (Node->getOpcode() == ISD::MULHS && 3245 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 3246 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 3247 1); 3248 break; 3249 } 3250 if (Node->getOpcode() == ISD::MULHU && 3251 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 3252 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 3253 1); 3254 break; 3255 } 3256 if (Node->getOpcode() == ISD::SDIV && 3257 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3258 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 3259 0); 3260 break; 3261 } 3262 if (Node->getOpcode() == ISD::UDIV && 3263 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3264 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 3265 0); 3266 break; 3267 } 3268 3269 // Check to see if we have a libcall for this operator. 3270 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3271 bool isSigned = false; 3272 switch (Node->getOpcode()) { 3273 case ISD::UDIV: 3274 case ISD::SDIV: 3275 if (VT == MVT::i32) { 3276 LC = Node->getOpcode() == ISD::UDIV 3277 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3278 isSigned = Node->getOpcode() == ISD::SDIV; 3279 } 3280 break; 3281 case ISD::MUL: 3282 if (VT == MVT::i32) 3283 LC = RTLIB::MUL_I32; 3284 else if (VT == MVT::i64) 3285 LC = RTLIB::MUL_I64; 3286 break; 3287 case ISD::FPOW: 3288 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3289 RTLIB::POW_PPCF128); 3290 break; 3291 default: break; 3292 } 3293 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3294 SDValue Dummy; 3295 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3296 break; 3297 } 3298 3299 assert(Node->getValueType(0).isVector() && 3300 "Cannot expand this binary operator!"); 3301 // Expand the operation into a bunch of nasty scalar code. 3302 Result = LegalizeOp(UnrollVectorOp(Op)); 3303 break; 3304 } 3305 case TargetLowering::Promote: { 3306 switch (Node->getOpcode()) { 3307 default: assert(0 && "Do not know how to promote this BinOp!"); 3308 case ISD::AND: 3309 case ISD::OR: 3310 case ISD::XOR: { 3311 MVT OVT = Node->getValueType(0); 3312 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3313 assert(OVT.isVector() && "Cannot promote this BinOp!"); 3314 // Bit convert each of the values to the new type. 3315 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 3316 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 3317 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3318 // Bit convert the result back the original type. 3319 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 3320 break; 3321 } 3322 } 3323 } 3324 } 3325 break; 3326 3327 case ISD::SMUL_LOHI: 3328 case ISD::UMUL_LOHI: 3329 case ISD::SDIVREM: 3330 case ISD::UDIVREM: 3331 // These nodes will only be produced by target-specific lowering, so 3332 // they shouldn't be here if they aren't legal. 3333 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3334 "This must be legal!"); 3335 3336 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3337 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3338 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3339 break; 3340 3341 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3342 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3343 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3344 case Expand: assert(0 && "Not possible"); 3345 case Legal: 3346 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3347 break; 3348 case Promote: 3349 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3350 break; 3351 } 3352 3353 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3354 3355 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3356 default: assert(0 && "Operation not supported"); 3357 case TargetLowering::Custom: 3358 Tmp1 = TLI.LowerOperation(Result, DAG); 3359 if (Tmp1.getNode()) Result = Tmp1; 3360 break; 3361 case TargetLowering::Legal: break; 3362 case TargetLowering::Expand: { 3363 // If this target supports fabs/fneg natively and select is cheap, 3364 // do this efficiently. 3365 if (!TLI.isSelectExpensive() && 3366 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3367 TargetLowering::Legal && 3368 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3369 TargetLowering::Legal) { 3370 // Get the sign bit of the RHS. 3371 MVT IVT = 3372 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3373 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 3374 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), 3375 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3376 // Get the absolute value of the result. 3377 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 3378 // Select between the nabs and abs value based on the sign bit of 3379 // the input. 3380 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 3381 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3382 AbsVal), 3383 AbsVal); 3384 Result = LegalizeOp(Result); 3385 break; 3386 } 3387 3388 // Otherwise, do bitwise ops! 3389 MVT NVT = 3390 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3391 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3392 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 3393 Result = LegalizeOp(Result); 3394 break; 3395 } 3396 } 3397 break; 3398 3399 case ISD::ADDC: 3400 case ISD::SUBC: 3401 Tmp1 = LegalizeOp(Node->getOperand(0)); 3402 Tmp2 = LegalizeOp(Node->getOperand(1)); 3403 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3404 Tmp3 = Result.getValue(0); 3405 Tmp4 = Result.getValue(1); 3406 3407 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3408 default: assert(0 && "This action is not supported yet!"); 3409 case TargetLowering::Legal: 3410 break; 3411 case TargetLowering::Custom: 3412 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 3413 if (Tmp1.getNode() != NULL) { 3414 Tmp3 = LegalizeOp(Tmp1); 3415 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 3416 } 3417 break; 3418 } 3419 // Since this produces two values, make sure to remember that we legalized 3420 // both of them. 3421 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 3422 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 3423 return Op.getResNo() ? Tmp4 : Tmp3; 3424 3425 case ISD::ADDE: 3426 case ISD::SUBE: 3427 Tmp1 = LegalizeOp(Node->getOperand(0)); 3428 Tmp2 = LegalizeOp(Node->getOperand(1)); 3429 Tmp3 = LegalizeOp(Node->getOperand(2)); 3430 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3431 Tmp3 = Result.getValue(0); 3432 Tmp4 = Result.getValue(1); 3433 3434 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3435 default: assert(0 && "This action is not supported yet!"); 3436 case TargetLowering::Legal: 3437 break; 3438 case TargetLowering::Custom: 3439 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 3440 if (Tmp1.getNode() != NULL) { 3441 Tmp3 = LegalizeOp(Tmp1); 3442 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 3443 } 3444 break; 3445 } 3446 // Since this produces two values, make sure to remember that we legalized 3447 // both of them. 3448 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 3449 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 3450 return Op.getResNo() ? Tmp4 : Tmp3; 3451 3452 case ISD::BUILD_PAIR: { 3453 MVT PairTy = Node->getValueType(0); 3454 // TODO: handle the case where the Lo and Hi operands are not of legal type 3455 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3456 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3457 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3458 case TargetLowering::Promote: 3459 case TargetLowering::Custom: 3460 assert(0 && "Cannot promote/custom this yet!"); 3461 case TargetLowering::Legal: 3462 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3463 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 3464 break; 3465 case TargetLowering::Expand: 3466 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 3467 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 3468 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 3469 DAG.getConstant(PairTy.getSizeInBits()/2, 3470 TLI.getShiftAmountTy())); 3471 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 3472 break; 3473 } 3474 break; 3475 } 3476 3477 case ISD::UREM: 3478 case ISD::SREM: 3479 case ISD::FREM: 3480 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3481 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3482 3483 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3484 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3485 case TargetLowering::Custom: 3486 isCustom = true; 3487 // FALLTHROUGH 3488 case TargetLowering::Legal: 3489 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3490 if (isCustom) { 3491 Tmp1 = TLI.LowerOperation(Result, DAG); 3492 if (Tmp1.getNode()) Result = Tmp1; 3493 } 3494 break; 3495 case TargetLowering::Expand: { 3496 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3497 bool isSigned = DivOpc == ISD::SDIV; 3498 MVT VT = Node->getValueType(0); 3499 3500 // See if remainder can be lowered using two-result operations. 3501 SDVTList VTs = DAG.getVTList(VT, VT); 3502 if (Node->getOpcode() == ISD::SREM && 3503 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3504 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1); 3505 break; 3506 } 3507 if (Node->getOpcode() == ISD::UREM && 3508 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3509 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1); 3510 break; 3511 } 3512 3513 if (VT.isInteger()) { 3514 if (TLI.getOperationAction(DivOpc, VT) == 3515 TargetLowering::Legal) { 3516 // X % Y -> X-X/Y*Y 3517 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3518 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3519 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3520 } else if (VT.isVector()) { 3521 Result = LegalizeOp(UnrollVectorOp(Op)); 3522 } else { 3523 assert(VT == MVT::i32 && 3524 "Cannot expand this binary operator!"); 3525 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3526 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3527 SDValue Dummy; 3528 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3529 } 3530 } else { 3531 assert(VT.isFloatingPoint() && 3532 "remainder op must have integer or floating-point type"); 3533 if (VT.isVector()) { 3534 Result = LegalizeOp(UnrollVectorOp(Op)); 3535 } else { 3536 // Floating point mod -> fmod libcall. 3537 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3538 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3539 SDValue Dummy; 3540 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3541 } 3542 } 3543 break; 3544 } 3545 } 3546 break; 3547 case ISD::VAARG: { 3548 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3549 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3550 3551 MVT VT = Node->getValueType(0); 3552 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3553 default: assert(0 && "This action is not supported yet!"); 3554 case TargetLowering::Custom: 3555 isCustom = true; 3556 // FALLTHROUGH 3557 case TargetLowering::Legal: 3558 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3559 Result = Result.getValue(0); 3560 Tmp1 = Result.getValue(1); 3561 3562 if (isCustom) { 3563 Tmp2 = TLI.LowerOperation(Result, DAG); 3564 if (Tmp2.getNode()) { 3565 Result = LegalizeOp(Tmp2); 3566 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3567 } 3568 } 3569 break; 3570 case TargetLowering::Expand: { 3571 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3572 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 3573 // Increment the pointer, VAList, to the next vaarg 3574 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3575 DAG.getConstant(TLI.getTargetData()->getABITypeSize(VT.getTypeForMVT()), 3576 TLI.getPointerTy())); 3577 // Store the incremented VAList to the legalized pointer 3578 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 3579 // Load the actual argument out of the pointer VAList 3580 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3581 Tmp1 = LegalizeOp(Result.getValue(1)); 3582 Result = LegalizeOp(Result); 3583 break; 3584 } 3585 } 3586 // Since VAARG produces two values, make sure to remember that we 3587 // legalized both of them. 3588 AddLegalizedOperand(SDValue(Node, 0), Result); 3589 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 3590 return Op.getResNo() ? Tmp1 : Result; 3591 } 3592 3593 case ISD::VACOPY: 3594 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3595 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3596 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3597 3598 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3599 default: assert(0 && "This action is not supported yet!"); 3600 case TargetLowering::Custom: 3601 isCustom = true; 3602 // FALLTHROUGH 3603 case TargetLowering::Legal: 3604 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3605 Node->getOperand(3), Node->getOperand(4)); 3606 if (isCustom) { 3607 Tmp1 = TLI.LowerOperation(Result, DAG); 3608 if (Tmp1.getNode()) Result = Tmp1; 3609 } 3610 break; 3611 case TargetLowering::Expand: 3612 // This defaults to loading a pointer from the input and storing it to the 3613 // output, returning the chain. 3614 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3615 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3616 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0); 3617 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0); 3618 break; 3619 } 3620 break; 3621 3622 case ISD::VAEND: 3623 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3624 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3625 3626 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3627 default: assert(0 && "This action is not supported yet!"); 3628 case TargetLowering::Custom: 3629 isCustom = true; 3630 // FALLTHROUGH 3631 case TargetLowering::Legal: 3632 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3633 if (isCustom) { 3634 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3635 if (Tmp1.getNode()) Result = Tmp1; 3636 } 3637 break; 3638 case TargetLowering::Expand: 3639 Result = Tmp1; // Default to a no-op, return the chain 3640 break; 3641 } 3642 break; 3643 3644 case ISD::VASTART: 3645 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3646 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3647 3648 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3649 3650 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3651 default: assert(0 && "This action is not supported yet!"); 3652 case TargetLowering::Legal: break; 3653 case TargetLowering::Custom: 3654 Tmp1 = TLI.LowerOperation(Result, DAG); 3655 if (Tmp1.getNode()) Result = Tmp1; 3656 break; 3657 } 3658 break; 3659 3660 case ISD::ROTL: 3661 case ISD::ROTR: 3662 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3663 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3664 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3665 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3666 default: 3667 assert(0 && "ROTL/ROTR legalize operation not supported"); 3668 break; 3669 case TargetLowering::Legal: 3670 break; 3671 case TargetLowering::Custom: 3672 Tmp1 = TLI.LowerOperation(Result, DAG); 3673 if (Tmp1.getNode()) Result = Tmp1; 3674 break; 3675 case TargetLowering::Promote: 3676 assert(0 && "Do not know how to promote ROTL/ROTR"); 3677 break; 3678 case TargetLowering::Expand: 3679 assert(0 && "Do not know how to expand ROTL/ROTR"); 3680 break; 3681 } 3682 break; 3683 3684 case ISD::BSWAP: 3685 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3686 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3687 case TargetLowering::Custom: 3688 assert(0 && "Cannot custom legalize this yet!"); 3689 case TargetLowering::Legal: 3690 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3691 break; 3692 case TargetLowering::Promote: { 3693 MVT OVT = Tmp1.getValueType(); 3694 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3695 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3696 3697 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3698 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3699 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3700 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3701 break; 3702 } 3703 case TargetLowering::Expand: 3704 Result = ExpandBSWAP(Tmp1); 3705 break; 3706 } 3707 break; 3708 3709 case ISD::CTPOP: 3710 case ISD::CTTZ: 3711 case ISD::CTLZ: 3712 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3713 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3714 case TargetLowering::Custom: 3715 case TargetLowering::Legal: 3716 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3717 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3718 TargetLowering::Custom) { 3719 Tmp1 = TLI.LowerOperation(Result, DAG); 3720 if (Tmp1.getNode()) { 3721 Result = Tmp1; 3722 } 3723 } 3724 break; 3725 case TargetLowering::Promote: { 3726 MVT OVT = Tmp1.getValueType(); 3727 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3728 3729 // Zero extend the argument. 3730 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3731 // Perform the larger operation, then subtract if needed. 3732 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3733 switch (Node->getOpcode()) { 3734 case ISD::CTPOP: 3735 Result = Tmp1; 3736 break; 3737 case ISD::CTTZ: 3738 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3739 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 3740 DAG.getConstant(NVT.getSizeInBits(), NVT), 3741 ISD::SETEQ); 3742 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3743 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3744 break; 3745 case ISD::CTLZ: 3746 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3747 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3748 DAG.getConstant(NVT.getSizeInBits() - 3749 OVT.getSizeInBits(), NVT)); 3750 break; 3751 } 3752 break; 3753 } 3754 case TargetLowering::Expand: 3755 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3756 break; 3757 } 3758 break; 3759 3760 // Unary operators 3761 case ISD::FABS: 3762 case ISD::FNEG: 3763 case ISD::FSQRT: 3764 case ISD::FSIN: 3765 case ISD::FCOS: 3766 case ISD::FLOG: 3767 case ISD::FLOG2: 3768 case ISD::FLOG10: 3769 case ISD::FEXP: 3770 case ISD::FEXP2: 3771 case ISD::FTRUNC: 3772 case ISD::FFLOOR: 3773 case ISD::FCEIL: 3774 case ISD::FRINT: 3775 case ISD::FNEARBYINT: 3776 Tmp1 = LegalizeOp(Node->getOperand(0)); 3777 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3778 case TargetLowering::Promote: 3779 case TargetLowering::Custom: 3780 isCustom = true; 3781 // FALLTHROUGH 3782 case TargetLowering::Legal: 3783 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3784 if (isCustom) { 3785 Tmp1 = TLI.LowerOperation(Result, DAG); 3786 if (Tmp1.getNode()) Result = Tmp1; 3787 } 3788 break; 3789 case TargetLowering::Expand: 3790 switch (Node->getOpcode()) { 3791 default: assert(0 && "Unreachable!"); 3792 case ISD::FNEG: 3793 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3794 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3795 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3796 break; 3797 case ISD::FABS: { 3798 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3799 MVT VT = Node->getValueType(0); 3800 Tmp2 = DAG.getConstantFP(0.0, VT); 3801 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 3802 ISD::SETUGT); 3803 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3804 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3805 break; 3806 } 3807 case ISD::FSQRT: 3808 case ISD::FSIN: 3809 case ISD::FCOS: 3810 case ISD::FLOG: 3811 case ISD::FLOG2: 3812 case ISD::FLOG10: 3813 case ISD::FEXP: 3814 case ISD::FEXP2: 3815 case ISD::FTRUNC: 3816 case ISD::FFLOOR: 3817 case ISD::FCEIL: 3818 case ISD::FRINT: 3819 case ISD::FNEARBYINT: { 3820 MVT VT = Node->getValueType(0); 3821 3822 // Expand unsupported unary vector operators by unrolling them. 3823 if (VT.isVector()) { 3824 Result = LegalizeOp(UnrollVectorOp(Op)); 3825 break; 3826 } 3827 3828 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3829 switch(Node->getOpcode()) { 3830 case ISD::FSQRT: 3831 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3832 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3833 break; 3834 case ISD::FSIN: 3835 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3836 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3837 break; 3838 case ISD::FCOS: 3839 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3840 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3841 break; 3842 case ISD::FLOG: 3843 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64, 3844 RTLIB::LOG_F80, RTLIB::LOG_PPCF128); 3845 break; 3846 case ISD::FLOG2: 3847 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 3848 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128); 3849 break; 3850 case ISD::FLOG10: 3851 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 3852 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128); 3853 break; 3854 case ISD::FEXP: 3855 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64, 3856 RTLIB::EXP_F80, RTLIB::EXP_PPCF128); 3857 break; 3858 case ISD::FEXP2: 3859 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 3860 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128); 3861 break; 3862 case ISD::FTRUNC: 3863 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 3864 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 3865 break; 3866 case ISD::FFLOOR: 3867 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 3868 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 3869 break; 3870 case ISD::FCEIL: 3871 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 3872 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 3873 break; 3874 case ISD::FRINT: 3875 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 3876 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 3877 break; 3878 case ISD::FNEARBYINT: 3879 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 3880 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 3881 break; 3882 break; 3883 default: assert(0 && "Unreachable!"); 3884 } 3885 SDValue Dummy; 3886 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3887 break; 3888 } 3889 } 3890 break; 3891 } 3892 break; 3893 case ISD::FPOWI: { 3894 MVT VT = Node->getValueType(0); 3895 3896 // Expand unsupported unary vector operators by unrolling them. 3897 if (VT.isVector()) { 3898 Result = LegalizeOp(UnrollVectorOp(Op)); 3899 break; 3900 } 3901 3902 // We always lower FPOWI into a libcall. No target support for it yet. 3903 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3904 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3905 SDValue Dummy; 3906 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3907 break; 3908 } 3909 case ISD::BIT_CONVERT: 3910 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3911 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3912 Node->getValueType(0)); 3913 } else if (Op.getOperand(0).getValueType().isVector()) { 3914 // The input has to be a vector type, we have to either scalarize it, pack 3915 // it, or convert it based on whether the input vector type is legal. 3916 SDNode *InVal = Node->getOperand(0).getNode(); 3917 int InIx = Node->getOperand(0).getResNo(); 3918 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 3919 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 3920 3921 // Figure out if there is a simple type corresponding to this Vector 3922 // type. If so, convert to the vector type. 3923 MVT TVT = MVT::getVectorVT(EVT, NumElems); 3924 if (TLI.isTypeLegal(TVT)) { 3925 // Turn this into a bit convert of the vector input. 3926 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3927 LegalizeOp(Node->getOperand(0))); 3928 break; 3929 } else if (NumElems == 1) { 3930 // Turn this into a bit convert of the scalar input. 3931 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3932 ScalarizeVectorOp(Node->getOperand(0))); 3933 break; 3934 } else { 3935 // FIXME: UNIMP! Store then reload 3936 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3937 } 3938 } else { 3939 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3940 Node->getOperand(0).getValueType())) { 3941 default: assert(0 && "Unknown operation action!"); 3942 case TargetLowering::Expand: 3943 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3944 Node->getValueType(0)); 3945 break; 3946 case TargetLowering::Legal: 3947 Tmp1 = LegalizeOp(Node->getOperand(0)); 3948 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3949 break; 3950 } 3951 } 3952 break; 3953 case ISD::CONVERT_RNDSAT: { 3954 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 3955 switch (CvtCode) { 3956 default: assert(0 && "Unknown cvt code!"); 3957 case ISD::CVT_SF: 3958 case ISD::CVT_UF: 3959 case ISD::CVT_FF: 3960 break; 3961 case ISD::CVT_FS: 3962 case ISD::CVT_FU: 3963 case ISD::CVT_SS: 3964 case ISD::CVT_SU: 3965 case ISD::CVT_US: 3966 case ISD::CVT_UU: { 3967 SDValue DTyOp = Node->getOperand(1); 3968 SDValue STyOp = Node->getOperand(2); 3969 SDValue RndOp = Node->getOperand(3); 3970 SDValue SatOp = Node->getOperand(4); 3971 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3972 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3973 case Legal: 3974 Tmp1 = LegalizeOp(Node->getOperand(0)); 3975 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp, 3976 RndOp, SatOp); 3977 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3978 TargetLowering::Custom) { 3979 Tmp1 = TLI.LowerOperation(Result, DAG); 3980 if (Tmp1.getNode()) Result = Tmp1; 3981 } 3982 break; 3983 case Promote: 3984 Result = PromoteOp(Node->getOperand(0)); 3985 // For FP, make Op1 a i32 3986 3987 Result = DAG.getConvertRndSat(Op.getValueType(), Result, 3988 DTyOp, STyOp, RndOp, SatOp, CvtCode); 3989 break; 3990 } 3991 break; 3992 } 3993 } // end switch CvtCode 3994 break; 3995 } 3996 // Conversion operators. The source and destination have different types. 3997 case ISD::SINT_TO_FP: 3998 case ISD::UINT_TO_FP: { 3999 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 4000 Result = LegalizeINT_TO_FP(Result, isSigned, 4001 Node->getValueType(0), Node->getOperand(0)); 4002 break; 4003 } 4004 case ISD::TRUNCATE: 4005 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4006 case Legal: 4007 Tmp1 = LegalizeOp(Node->getOperand(0)); 4008 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 4009 default: assert(0 && "Unknown TRUNCATE legalization operation action!"); 4010 case TargetLowering::Custom: 4011 isCustom = true; 4012 // FALLTHROUGH 4013 case TargetLowering::Legal: 4014 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4015 if (isCustom) { 4016 Tmp1 = TLI.LowerOperation(Result, DAG); 4017 if (Tmp1.getNode()) Result = Tmp1; 4018 } 4019 break; 4020 case TargetLowering::Expand: 4021 assert(Result.getValueType().isVector() && "must be vector type"); 4022 // Unroll the truncate. We should do better. 4023 Result = LegalizeOp(UnrollVectorOp(Result)); 4024 } 4025 break; 4026 case Expand: 4027 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4028 4029 // Since the result is legal, we should just be able to truncate the low 4030 // part of the source. 4031 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 4032 break; 4033 case Promote: 4034 Result = PromoteOp(Node->getOperand(0)); 4035 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 4036 break; 4037 } 4038 break; 4039 4040 case ISD::FP_TO_SINT: 4041 case ISD::FP_TO_UINT: 4042 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4043 case Legal: 4044 Tmp1 = LegalizeOp(Node->getOperand(0)); 4045 4046 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 4047 default: assert(0 && "Unknown operation action!"); 4048 case TargetLowering::Custom: 4049 isCustom = true; 4050 // FALLTHROUGH 4051 case TargetLowering::Legal: 4052 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4053 if (isCustom) { 4054 Tmp1 = TLI.LowerOperation(Result, DAG); 4055 if (Tmp1.getNode()) Result = Tmp1; 4056 } 4057 break; 4058 case TargetLowering::Promote: 4059 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 4060 Node->getOpcode() == ISD::FP_TO_SINT); 4061 break; 4062 case TargetLowering::Expand: 4063 if (Node->getOpcode() == ISD::FP_TO_UINT) { 4064 SDValue True, False; 4065 MVT VT = Node->getOperand(0).getValueType(); 4066 MVT NVT = Node->getValueType(0); 4067 const uint64_t zero[] = {0, 0}; 4068 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 4069 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 4070 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 4071 Tmp2 = DAG.getConstantFP(apf, VT); 4072 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)), 4073 Node->getOperand(0), Tmp2, ISD::SETLT); 4074 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 4075 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 4076 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 4077 Tmp2)); 4078 False = DAG.getNode(ISD::XOR, NVT, False, 4079 DAG.getConstant(x, NVT)); 4080 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 4081 break; 4082 } else { 4083 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 4084 } 4085 break; 4086 } 4087 break; 4088 case Expand: { 4089 MVT VT = Op.getValueType(); 4090 MVT OVT = Node->getOperand(0).getValueType(); 4091 // Convert ppcf128 to i32 4092 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 4093 if (Node->getOpcode() == ISD::FP_TO_SINT) { 4094 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 4095 Node->getOperand(0), DAG.getValueType(MVT::f64)); 4096 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 4097 DAG.getIntPtrConstant(1)); 4098 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 4099 } else { 4100 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 4101 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 4102 Tmp2 = DAG.getConstantFP(apf, OVT); 4103 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 4104 // FIXME: generated code sucks. 4105 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 4106 DAG.getNode(ISD::ADD, MVT::i32, 4107 DAG.getNode(ISD::FP_TO_SINT, VT, 4108 DAG.getNode(ISD::FSUB, OVT, 4109 Node->getOperand(0), Tmp2)), 4110 DAG.getConstant(0x80000000, MVT::i32)), 4111 DAG.getNode(ISD::FP_TO_SINT, VT, 4112 Node->getOperand(0)), 4113 DAG.getCondCode(ISD::SETGE)); 4114 } 4115 break; 4116 } 4117 // Convert f32 / f64 to i32 / i64 / i128. 4118 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ? 4119 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT); 4120 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!"); 4121 SDValue Dummy; 4122 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 4123 break; 4124 } 4125 case Promote: 4126 Tmp1 = PromoteOp(Node->getOperand(0)); 4127 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 4128 Result = LegalizeOp(Result); 4129 break; 4130 } 4131 break; 4132 4133 case ISD::FP_EXTEND: { 4134 MVT DstVT = Op.getValueType(); 4135 MVT SrcVT = Op.getOperand(0).getValueType(); 4136 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 4137 // The only other way we can lower this is to turn it into a STORE, 4138 // LOAD pair, targetting a temporary location (a stack slot). 4139 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 4140 break; 4141 } 4142 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4143 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4144 case Legal: 4145 Tmp1 = LegalizeOp(Node->getOperand(0)); 4146 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4147 break; 4148 case Promote: 4149 Tmp1 = PromoteOp(Node->getOperand(0)); 4150 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 4151 break; 4152 } 4153 break; 4154 } 4155 case ISD::FP_ROUND: { 4156 MVT DstVT = Op.getValueType(); 4157 MVT SrcVT = Op.getOperand(0).getValueType(); 4158 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 4159 if (SrcVT == MVT::ppcf128) { 4160 SDValue Lo; 4161 ExpandOp(Node->getOperand(0), Lo, Result); 4162 // Round it the rest of the way (e.g. to f32) if needed. 4163 if (DstVT!=MVT::f64) 4164 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 4165 break; 4166 } 4167 // The only other way we can lower this is to turn it into a STORE, 4168 // LOAD pair, targetting a temporary location (a stack slot). 4169 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 4170 break; 4171 } 4172 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4173 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4174 case Legal: 4175 Tmp1 = LegalizeOp(Node->getOperand(0)); 4176 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 4177 break; 4178 case Promote: 4179 Tmp1 = PromoteOp(Node->getOperand(0)); 4180 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 4181 Node->getOperand(1)); 4182 break; 4183 } 4184 break; 4185 } 4186 case ISD::ANY_EXTEND: 4187 case ISD::ZERO_EXTEND: 4188 case ISD::SIGN_EXTEND: 4189 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4190 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4191 case Legal: 4192 Tmp1 = LegalizeOp(Node->getOperand(0)); 4193 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4194 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 4195 TargetLowering::Custom) { 4196 Tmp1 = TLI.LowerOperation(Result, DAG); 4197 if (Tmp1.getNode()) Result = Tmp1; 4198 } 4199 break; 4200 case Promote: 4201 switch (Node->getOpcode()) { 4202 case ISD::ANY_EXTEND: 4203 Tmp1 = PromoteOp(Node->getOperand(0)); 4204 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 4205 break; 4206 case ISD::ZERO_EXTEND: 4207 Result = PromoteOp(Node->getOperand(0)); 4208 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 4209 Result = DAG.getZeroExtendInReg(Result, 4210 Node->getOperand(0).getValueType()); 4211 break; 4212 case ISD::SIGN_EXTEND: 4213 Result = PromoteOp(Node->getOperand(0)); 4214 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 4215 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4216 Result, 4217 DAG.getValueType(Node->getOperand(0).getValueType())); 4218 break; 4219 } 4220 } 4221 break; 4222 case ISD::FP_ROUND_INREG: 4223 case ISD::SIGN_EXTEND_INREG: { 4224 Tmp1 = LegalizeOp(Node->getOperand(0)); 4225 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 4226 4227 // If this operation is not supported, convert it to a shl/shr or load/store 4228 // pair. 4229 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 4230 default: assert(0 && "This action not supported for this op yet!"); 4231 case TargetLowering::Legal: 4232 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 4233 break; 4234 case TargetLowering::Expand: 4235 // If this is an integer extend and shifts are supported, do that. 4236 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 4237 // NOTE: we could fall back on load/store here too for targets without 4238 // SAR. However, it is doubtful that any exist. 4239 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 4240 ExtraVT.getSizeInBits(); 4241 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 4242 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 4243 Node->getOperand(0), ShiftCst); 4244 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 4245 Result, ShiftCst); 4246 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 4247 // The only way we can lower this is to turn it into a TRUNCSTORE, 4248 // EXTLOAD pair, targetting a temporary location (a stack slot). 4249 4250 // NOTE: there is a choice here between constantly creating new stack 4251 // slots and always reusing the same one. We currently always create 4252 // new ones, as reuse may inhibit scheduling. 4253 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 4254 Node->getValueType(0)); 4255 } else { 4256 assert(0 && "Unknown op"); 4257 } 4258 break; 4259 } 4260 break; 4261 } 4262 case ISD::TRAMPOLINE: { 4263 SDValue Ops[6]; 4264 for (unsigned i = 0; i != 6; ++i) 4265 Ops[i] = LegalizeOp(Node->getOperand(i)); 4266 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 4267 // The only option for this node is to custom lower it. 4268 Result = TLI.LowerOperation(Result, DAG); 4269 assert(Result.getNode() && "Should always custom lower!"); 4270 4271 // Since trampoline produces two values, make sure to remember that we 4272 // legalized both of them. 4273 Tmp1 = LegalizeOp(Result.getValue(1)); 4274 Result = LegalizeOp(Result); 4275 AddLegalizedOperand(SDValue(Node, 0), Result); 4276 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 4277 return Op.getResNo() ? Tmp1 : Result; 4278 } 4279 case ISD::FLT_ROUNDS_: { 4280 MVT VT = Node->getValueType(0); 4281 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4282 default: assert(0 && "This action not supported for this op yet!"); 4283 case TargetLowering::Custom: 4284 Result = TLI.LowerOperation(Op, DAG); 4285 if (Result.getNode()) break; 4286 // Fall Thru 4287 case TargetLowering::Legal: 4288 // If this operation is not supported, lower it to constant 1 4289 Result = DAG.getConstant(1, VT); 4290 break; 4291 } 4292 break; 4293 } 4294 case ISD::TRAP: { 4295 MVT VT = Node->getValueType(0); 4296 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4297 default: assert(0 && "This action not supported for this op yet!"); 4298 case TargetLowering::Legal: 4299 Tmp1 = LegalizeOp(Node->getOperand(0)); 4300 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4301 break; 4302 case TargetLowering::Custom: 4303 Result = TLI.LowerOperation(Op, DAG); 4304 if (Result.getNode()) break; 4305 // Fall Thru 4306 case TargetLowering::Expand: 4307 // If this operation is not supported, lower it to 'abort()' call 4308 Tmp1 = LegalizeOp(Node->getOperand(0)); 4309 TargetLowering::ArgListTy Args; 4310 std::pair<SDValue,SDValue> CallResult = 4311 TLI.LowerCallTo(Tmp1, Type::VoidTy, 4312 false, false, false, false, CallingConv::C, false, 4313 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 4314 Args, DAG); 4315 Result = CallResult.second; 4316 break; 4317 } 4318 break; 4319 } 4320 4321 case ISD::SADDO: 4322 case ISD::SSUBO: { 4323 MVT VT = Node->getValueType(0); 4324 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4325 default: assert(0 && "This action not supported for this op yet!"); 4326 case TargetLowering::Custom: 4327 Result = TLI.LowerOperation(Op, DAG); 4328 if (Result.getNode()) break; 4329 // FALLTHROUGH 4330 case TargetLowering::Legal: { 4331 SDValue LHS = LegalizeOp(Node->getOperand(0)); 4332 SDValue RHS = LegalizeOp(Node->getOperand(1)); 4333 4334 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 4335 ISD::ADD : ISD::SUB, LHS.getValueType(), 4336 LHS, RHS); 4337 MVT OType = Node->getValueType(1); 4338 4339 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 4340 4341 // LHSSign -> LHS >= 0 4342 // RHSSign -> RHS >= 0 4343 // SumSign -> Sum >= 0 4344 // 4345 // Add: 4346 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 4347 // Sub: 4348 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 4349 // 4350 SDValue LHSSign = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE); 4351 SDValue RHSSign = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE); 4352 SDValue SignsMatch = DAG.getSetCC(OType, LHSSign, RHSSign, 4353 Node->getOpcode() == ISD::SADDO ? 4354 ISD::SETEQ : ISD::SETNE); 4355 4356 SDValue SumSign = DAG.getSetCC(OType, Sum, Zero, ISD::SETGE); 4357 SDValue SumSignNE = DAG.getSetCC(OType, LHSSign, SumSign, ISD::SETNE); 4358 4359 SDValue Cmp = DAG.getNode(ISD::AND, OType, SignsMatch, SumSignNE); 4360 4361 MVT ValueVTs[] = { LHS.getValueType(), OType }; 4362 SDValue Ops[] = { Sum, Cmp }; 4363 4364 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2), 4365 &Ops[0], 2); 4366 SDNode *RNode = Result.getNode(); 4367 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0)); 4368 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1)); 4369 break; 4370 } 4371 } 4372 4373 break; 4374 } 4375 case ISD::UADDO: 4376 case ISD::USUBO: { 4377 MVT VT = Node->getValueType(0); 4378 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4379 default: assert(0 && "This action not supported for this op yet!"); 4380 case TargetLowering::Custom: 4381 Result = TLI.LowerOperation(Op, DAG); 4382 if (Result.getNode()) break; 4383 // FALLTHROUGH 4384 case TargetLowering::Legal: { 4385 SDValue LHS = LegalizeOp(Node->getOperand(0)); 4386 SDValue RHS = LegalizeOp(Node->getOperand(1)); 4387 4388 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 4389 ISD::ADD : ISD::SUB, LHS.getValueType(), 4390 LHS, RHS); 4391 MVT OType = Node->getValueType(1); 4392 SDValue Cmp = DAG.getSetCC(OType, Sum, LHS, 4393 Node->getOpcode () == ISD::UADDO ? 4394 ISD::SETULT : ISD::SETUGT); 4395 4396 MVT ValueVTs[] = { LHS.getValueType(), OType }; 4397 SDValue Ops[] = { Sum, Cmp }; 4398 4399 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2), 4400 &Ops[0], 2); 4401 SDNode *RNode = Result.getNode(); 4402 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0)); 4403 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1)); 4404 break; 4405 } 4406 } 4407 4408 break; 4409 } 4410 case ISD::SMULO: 4411 case ISD::UMULO: { 4412 MVT VT = Node->getValueType(0); 4413 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4414 default: assert(0 && "This action is not supported at all!"); 4415 case TargetLowering::Custom: 4416 Result = TLI.LowerOperation(Op, DAG); 4417 if (Result.getNode()) break; 4418 // Fall Thru 4419 case TargetLowering::Legal: 4420 // FIXME: According to Hacker's Delight, this can be implemented in 4421 // target independent lowering, but it would be inefficient, since it 4422 // requires a division + a branch. 4423 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!"); 4424 break; 4425 } 4426 break; 4427 } 4428 4429 } 4430 4431 assert(Result.getValueType() == Op.getValueType() && 4432 "Bad legalization!"); 4433 4434 // Make sure that the generated code is itself legal. 4435 if (Result != Op) 4436 Result = LegalizeOp(Result); 4437 4438 // Note that LegalizeOp may be reentered even from single-use nodes, which 4439 // means that we always must cache transformed nodes. 4440 AddLegalizedOperand(Op, Result); 4441 return Result; 4442} 4443 4444/// PromoteOp - Given an operation that produces a value in an invalid type, 4445/// promote it to compute the value into a larger type. The produced value will 4446/// have the correct bits for the low portion of the register, but no guarantee 4447/// is made about the top bits: it may be zero, sign-extended, or garbage. 4448SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { 4449 MVT VT = Op.getValueType(); 4450 MVT NVT = TLI.getTypeToTransformTo(VT); 4451 assert(getTypeAction(VT) == Promote && 4452 "Caller should expand or legalize operands that are not promotable!"); 4453 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() && 4454 "Cannot promote to smaller type!"); 4455 4456 SDValue Tmp1, Tmp2, Tmp3; 4457 SDValue Result; 4458 SDNode *Node = Op.getNode(); 4459 4460 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op); 4461 if (I != PromotedNodes.end()) return I->second; 4462 4463 switch (Node->getOpcode()) { 4464 case ISD::CopyFromReg: 4465 assert(0 && "CopyFromReg must be legal!"); 4466 default: 4467#ifndef NDEBUG 4468 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4469#endif 4470 assert(0 && "Do not know how to promote this operator!"); 4471 abort(); 4472 case ISD::UNDEF: 4473 Result = DAG.getNode(ISD::UNDEF, NVT); 4474 break; 4475 case ISD::Constant: 4476 if (VT != MVT::i1) 4477 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 4478 else 4479 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 4480 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4481 break; 4482 case ISD::ConstantFP: 4483 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 4484 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4485 break; 4486 4487 case ISD::SETCC: 4488 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0))) 4489 && "SetCC type is not legal??"); 4490 Result = DAG.getNode(ISD::SETCC, 4491 TLI.getSetCCResultType(Node->getOperand(0)), 4492 Node->getOperand(0), Node->getOperand(1), 4493 Node->getOperand(2)); 4494 break; 4495 4496 case ISD::TRUNCATE: 4497 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4498 case Legal: 4499 Result = LegalizeOp(Node->getOperand(0)); 4500 assert(Result.getValueType().bitsGE(NVT) && 4501 "This truncation doesn't make sense!"); 4502 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT 4503 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 4504 break; 4505 case Promote: 4506 // The truncation is not required, because we don't guarantee anything 4507 // about high bits anyway. 4508 Result = PromoteOp(Node->getOperand(0)); 4509 break; 4510 case Expand: 4511 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4512 // Truncate the low part of the expanded value to the result type 4513 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 4514 } 4515 break; 4516 case ISD::SIGN_EXTEND: 4517 case ISD::ZERO_EXTEND: 4518 case ISD::ANY_EXTEND: 4519 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4520 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4521 case Legal: 4522 // Input is legal? Just do extend all the way to the larger type. 4523 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4524 break; 4525 case Promote: 4526 // Promote the reg if it's smaller. 4527 Result = PromoteOp(Node->getOperand(0)); 4528 // The high bits are not guaranteed to be anything. Insert an extend. 4529 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4530 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4531 DAG.getValueType(Node->getOperand(0).getValueType())); 4532 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4533 Result = DAG.getZeroExtendInReg(Result, 4534 Node->getOperand(0).getValueType()); 4535 break; 4536 } 4537 break; 4538 case ISD::CONVERT_RNDSAT: { 4539 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 4540 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 4541 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 4542 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 4543 "can only promote integers"); 4544 Result = DAG.getConvertRndSat(NVT, Node->getOperand(0), 4545 Node->getOperand(1), Node->getOperand(2), 4546 Node->getOperand(3), Node->getOperand(4), 4547 CvtCode); 4548 break; 4549 4550 } 4551 case ISD::BIT_CONVERT: 4552 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4553 Node->getValueType(0)); 4554 Result = PromoteOp(Result); 4555 break; 4556 4557 case ISD::FP_EXTEND: 4558 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4559 case ISD::FP_ROUND: 4560 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4561 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4562 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4563 case Legal: 4564 if (Node->getConstantOperandVal(1) == 0) { 4565 // Input is legal? Do an FP_ROUND_INREG. 4566 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 4567 DAG.getValueType(VT)); 4568 } else { 4569 // Just remove the truncate, it isn't affecting the value. 4570 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 4571 Node->getOperand(1)); 4572 } 4573 break; 4574 } 4575 break; 4576 case ISD::SINT_TO_FP: 4577 case ISD::UINT_TO_FP: 4578 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4579 case Legal: 4580 // No extra round required here. 4581 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4582 break; 4583 4584 case Promote: 4585 Result = PromoteOp(Node->getOperand(0)); 4586 if (Node->getOpcode() == ISD::SINT_TO_FP) 4587 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4588 Result, 4589 DAG.getValueType(Node->getOperand(0).getValueType())); 4590 else 4591 Result = DAG.getZeroExtendInReg(Result, 4592 Node->getOperand(0).getValueType()); 4593 // No extra round required here. 4594 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 4595 break; 4596 case Expand: 4597 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4598 Node->getOperand(0)); 4599 // Round if we cannot tolerate excess precision. 4600 if (NoExcessFPPrecision) 4601 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4602 DAG.getValueType(VT)); 4603 break; 4604 } 4605 break; 4606 4607 case ISD::SIGN_EXTEND_INREG: 4608 Result = PromoteOp(Node->getOperand(0)); 4609 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4610 Node->getOperand(1)); 4611 break; 4612 case ISD::FP_TO_SINT: 4613 case ISD::FP_TO_UINT: 4614 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4615 case Legal: 4616 case Expand: 4617 Tmp1 = Node->getOperand(0); 4618 break; 4619 case Promote: 4620 // The input result is prerounded, so we don't have to do anything 4621 // special. 4622 Tmp1 = PromoteOp(Node->getOperand(0)); 4623 break; 4624 } 4625 // If we're promoting a UINT to a larger size, check to see if the new node 4626 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4627 // we can use that instead. This allows us to generate better code for 4628 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4629 // legal, such as PowerPC. 4630 if (Node->getOpcode() == ISD::FP_TO_UINT && 4631 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 4632 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 4633 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4634 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 4635 } else { 4636 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4637 } 4638 break; 4639 4640 case ISD::FABS: 4641 case ISD::FNEG: 4642 Tmp1 = PromoteOp(Node->getOperand(0)); 4643 assert(Tmp1.getValueType() == NVT); 4644 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4645 // NOTE: we do not have to do any extra rounding here for 4646 // NoExcessFPPrecision, because we know the input will have the appropriate 4647 // precision, and these operations don't modify precision at all. 4648 break; 4649 4650 case ISD::FLOG: 4651 case ISD::FLOG2: 4652 case ISD::FLOG10: 4653 case ISD::FEXP: 4654 case ISD::FEXP2: 4655 case ISD::FSQRT: 4656 case ISD::FSIN: 4657 case ISD::FCOS: 4658 case ISD::FTRUNC: 4659 case ISD::FFLOOR: 4660 case ISD::FCEIL: 4661 case ISD::FRINT: 4662 case ISD::FNEARBYINT: 4663 Tmp1 = PromoteOp(Node->getOperand(0)); 4664 assert(Tmp1.getValueType() == NVT); 4665 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4666 if (NoExcessFPPrecision) 4667 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4668 DAG.getValueType(VT)); 4669 break; 4670 4671 case ISD::FPOW: 4672 case ISD::FPOWI: { 4673 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall 4674 // directly as well, which may be better. 4675 Tmp1 = PromoteOp(Node->getOperand(0)); 4676 Tmp2 = Node->getOperand(1); 4677 if (Node->getOpcode() == ISD::FPOW) 4678 Tmp2 = PromoteOp(Tmp2); 4679 assert(Tmp1.getValueType() == NVT); 4680 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4681 if (NoExcessFPPrecision) 4682 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4683 DAG.getValueType(VT)); 4684 break; 4685 } 4686 4687 case ISD::ATOMIC_CMP_SWAP: { 4688 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4689 Tmp2 = PromoteOp(Node->getOperand(2)); 4690 Tmp3 = PromoteOp(Node->getOperand(3)); 4691 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(), 4692 AtomNode->getChain(), 4693 AtomNode->getBasePtr(), Tmp2, Tmp3, 4694 AtomNode->getSrcValue(), 4695 AtomNode->getAlignment()); 4696 // Remember that we legalized the chain. 4697 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4698 break; 4699 } 4700 case ISD::ATOMIC_LOAD_ADD: 4701 case ISD::ATOMIC_LOAD_SUB: 4702 case ISD::ATOMIC_LOAD_AND: 4703 case ISD::ATOMIC_LOAD_OR: 4704 case ISD::ATOMIC_LOAD_XOR: 4705 case ISD::ATOMIC_LOAD_NAND: 4706 case ISD::ATOMIC_LOAD_MIN: 4707 case ISD::ATOMIC_LOAD_MAX: 4708 case ISD::ATOMIC_LOAD_UMIN: 4709 case ISD::ATOMIC_LOAD_UMAX: 4710 case ISD::ATOMIC_SWAP: { 4711 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4712 Tmp2 = PromoteOp(Node->getOperand(2)); 4713 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(), 4714 AtomNode->getChain(), 4715 AtomNode->getBasePtr(), Tmp2, 4716 AtomNode->getSrcValue(), 4717 AtomNode->getAlignment()); 4718 // Remember that we legalized the chain. 4719 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4720 break; 4721 } 4722 4723 case ISD::AND: 4724 case ISD::OR: 4725 case ISD::XOR: 4726 case ISD::ADD: 4727 case ISD::SUB: 4728 case ISD::MUL: 4729 // The input may have strange things in the top bits of the registers, but 4730 // these operations don't care. They may have weird bits going out, but 4731 // that too is okay if they are integer operations. 4732 Tmp1 = PromoteOp(Node->getOperand(0)); 4733 Tmp2 = PromoteOp(Node->getOperand(1)); 4734 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4735 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4736 break; 4737 case ISD::FADD: 4738 case ISD::FSUB: 4739 case ISD::FMUL: 4740 Tmp1 = PromoteOp(Node->getOperand(0)); 4741 Tmp2 = PromoteOp(Node->getOperand(1)); 4742 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4743 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4744 4745 // Floating point operations will give excess precision that we may not be 4746 // able to tolerate. If we DO allow excess precision, just leave it, 4747 // otherwise excise it. 4748 // FIXME: Why would we need to round FP ops more than integer ones? 4749 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4750 if (NoExcessFPPrecision) 4751 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4752 DAG.getValueType(VT)); 4753 break; 4754 4755 case ISD::SDIV: 4756 case ISD::SREM: 4757 // These operators require that their input be sign extended. 4758 Tmp1 = PromoteOp(Node->getOperand(0)); 4759 Tmp2 = PromoteOp(Node->getOperand(1)); 4760 if (NVT.isInteger()) { 4761 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4762 DAG.getValueType(VT)); 4763 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4764 DAG.getValueType(VT)); 4765 } 4766 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4767 4768 // Perform FP_ROUND: this is probably overly pessimistic. 4769 if (NVT.isFloatingPoint() && NoExcessFPPrecision) 4770 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4771 DAG.getValueType(VT)); 4772 break; 4773 case ISD::FDIV: 4774 case ISD::FREM: 4775 case ISD::FCOPYSIGN: 4776 // These operators require that their input be fp extended. 4777 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4778 case Expand: assert(0 && "not implemented"); 4779 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4780 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4781 } 4782 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4783 case Expand: assert(0 && "not implemented"); 4784 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4785 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4786 } 4787 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4788 4789 // Perform FP_ROUND: this is probably overly pessimistic. 4790 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4791 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4792 DAG.getValueType(VT)); 4793 break; 4794 4795 case ISD::UDIV: 4796 case ISD::UREM: 4797 // These operators require that their input be zero extended. 4798 Tmp1 = PromoteOp(Node->getOperand(0)); 4799 Tmp2 = PromoteOp(Node->getOperand(1)); 4800 assert(NVT.isInteger() && "Operators don't apply to FP!"); 4801 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4802 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4803 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4804 break; 4805 4806 case ISD::SHL: 4807 Tmp1 = PromoteOp(Node->getOperand(0)); 4808 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4809 break; 4810 case ISD::SRA: 4811 // The input value must be properly sign extended. 4812 Tmp1 = PromoteOp(Node->getOperand(0)); 4813 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4814 DAG.getValueType(VT)); 4815 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4816 break; 4817 case ISD::SRL: 4818 // The input value must be properly zero extended. 4819 Tmp1 = PromoteOp(Node->getOperand(0)); 4820 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4821 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4822 break; 4823 4824 case ISD::VAARG: 4825 Tmp1 = Node->getOperand(0); // Get the chain. 4826 Tmp2 = Node->getOperand(1); // Get the pointer. 4827 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4828 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4829 Result = TLI.LowerOperation(Tmp3, DAG); 4830 } else { 4831 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4832 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 4833 // Increment the pointer, VAList, to the next vaarg 4834 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4835 DAG.getConstant(VT.getSizeInBits()/8, 4836 TLI.getPointerTy())); 4837 // Store the incremented VAList to the legalized pointer 4838 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 4839 // Load the actual argument out of the pointer VAList 4840 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4841 } 4842 // Remember that we legalized the chain. 4843 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4844 break; 4845 4846 case ISD::LOAD: { 4847 LoadSDNode *LD = cast<LoadSDNode>(Node); 4848 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4849 ? ISD::EXTLOAD : LD->getExtensionType(); 4850 Result = DAG.getExtLoad(ExtType, NVT, 4851 LD->getChain(), LD->getBasePtr(), 4852 LD->getSrcValue(), LD->getSrcValueOffset(), 4853 LD->getMemoryVT(), 4854 LD->isVolatile(), 4855 LD->getAlignment()); 4856 // Remember that we legalized the chain. 4857 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4858 break; 4859 } 4860 case ISD::SELECT: { 4861 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4862 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4863 4864 MVT VT2 = Tmp2.getValueType(); 4865 assert(VT2 == Tmp3.getValueType() 4866 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); 4867 // Ensure that the resulting node is at least the same size as the operands' 4868 // value types, because we cannot assume that TLI.getSetCCValueType() is 4869 // constant. 4870 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3); 4871 break; 4872 } 4873 case ISD::SELECT_CC: 4874 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4875 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4876 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4877 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4878 break; 4879 case ISD::BSWAP: 4880 Tmp1 = Node->getOperand(0); 4881 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4882 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4883 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4884 DAG.getConstant(NVT.getSizeInBits() - 4885 VT.getSizeInBits(), 4886 TLI.getShiftAmountTy())); 4887 break; 4888 case ISD::CTPOP: 4889 case ISD::CTTZ: 4890 case ISD::CTLZ: 4891 // Zero extend the argument 4892 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4893 // Perform the larger operation, then subtract if needed. 4894 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4895 switch(Node->getOpcode()) { 4896 case ISD::CTPOP: 4897 Result = Tmp1; 4898 break; 4899 case ISD::CTTZ: 4900 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4901 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 4902 DAG.getConstant(NVT.getSizeInBits(), NVT), 4903 ISD::SETEQ); 4904 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4905 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); 4906 break; 4907 case ISD::CTLZ: 4908 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4909 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4910 DAG.getConstant(NVT.getSizeInBits() - 4911 VT.getSizeInBits(), NVT)); 4912 break; 4913 } 4914 break; 4915 case ISD::EXTRACT_SUBVECTOR: 4916 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4917 break; 4918 case ISD::EXTRACT_VECTOR_ELT: 4919 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4920 break; 4921 } 4922 4923 assert(Result.getNode() && "Didn't set a result!"); 4924 4925 // Make sure the result is itself legal. 4926 Result = LegalizeOp(Result); 4927 4928 // Remember that we promoted this! 4929 AddPromotedOperand(Op, Result); 4930 return Result; 4931} 4932 4933/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4934/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4935/// based on the vector type. The return type of this matches the element type 4936/// of the vector, which may not be legal for the target. 4937SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) { 4938 // We know that operand #0 is the Vec vector. If the index is a constant 4939 // or if the invec is a supported hardware type, we can use it. Otherwise, 4940 // lower to a store then an indexed load. 4941 SDValue Vec = Op.getOperand(0); 4942 SDValue Idx = Op.getOperand(1); 4943 4944 MVT TVT = Vec.getValueType(); 4945 unsigned NumElems = TVT.getVectorNumElements(); 4946 4947 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4948 default: assert(0 && "This action is not supported yet!"); 4949 case TargetLowering::Custom: { 4950 Vec = LegalizeOp(Vec); 4951 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4952 SDValue Tmp3 = TLI.LowerOperation(Op, DAG); 4953 if (Tmp3.getNode()) 4954 return Tmp3; 4955 break; 4956 } 4957 case TargetLowering::Legal: 4958 if (isTypeLegal(TVT)) { 4959 Vec = LegalizeOp(Vec); 4960 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4961 return Op; 4962 } 4963 break; 4964 case TargetLowering::Promote: 4965 assert(TVT.isVector() && "not vector type"); 4966 // fall thru to expand since vectors are by default are promote 4967 case TargetLowering::Expand: 4968 break; 4969 } 4970 4971 if (NumElems == 1) { 4972 // This must be an access of the only element. Return it. 4973 Op = ScalarizeVectorOp(Vec); 4974 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4975 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 4976 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4977 SDValue Lo, Hi; 4978 SplitVectorOp(Vec, Lo, Hi); 4979 if (CIdx->getZExtValue() < NumLoElts) { 4980 Vec = Lo; 4981 } else { 4982 Vec = Hi; 4983 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts, 4984 Idx.getValueType()); 4985 } 4986 4987 // It's now an extract from the appropriate high or low part. Recurse. 4988 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4989 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4990 } else { 4991 // Store the value to a temporary stack slot, then LOAD the scalar 4992 // element back out. 4993 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4994 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4995 4996 // Add the offset to the index. 4997 unsigned EltSize = Op.getValueType().getSizeInBits()/8; 4998 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4999 DAG.getConstant(EltSize, Idx.getValueType())); 5000 5001 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 5002 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 5003 else 5004 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 5005 5006 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 5007 5008 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 5009 } 5010 return Op; 5011} 5012 5013/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 5014/// we assume the operation can be split if it is not already legal. 5015SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) { 5016 // We know that operand #0 is the Vec vector. For now we assume the index 5017 // is a constant and that the extracted result is a supported hardware type. 5018 SDValue Vec = Op.getOperand(0); 5019 SDValue Idx = LegalizeOp(Op.getOperand(1)); 5020 5021 unsigned NumElems = Vec.getValueType().getVectorNumElements(); 5022 5023 if (NumElems == Op.getValueType().getVectorNumElements()) { 5024 // This must be an access of the desired vector length. Return it. 5025 return Vec; 5026 } 5027 5028 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 5029 SDValue Lo, Hi; 5030 SplitVectorOp(Vec, Lo, Hi); 5031 if (CIdx->getZExtValue() < NumElems/2) { 5032 Vec = Lo; 5033 } else { 5034 Vec = Hi; 5035 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2, 5036 Idx.getValueType()); 5037 } 5038 5039 // It's now an extract from the appropriate high or low part. Recurse. 5040 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 5041 return ExpandEXTRACT_SUBVECTOR(Op); 5042} 5043 5044/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 5045/// with condition CC on the current target. This usually involves legalizing 5046/// or promoting the arguments. In the case where LHS and RHS must be expanded, 5047/// there may be no choice but to create a new SetCC node to represent the 5048/// legalized value of setcc lhs, rhs. In this case, the value is returned in 5049/// LHS, and the SDValue returned in RHS has a nil SDNode value. 5050void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS, 5051 SDValue &RHS, 5052 SDValue &CC) { 5053 SDValue Tmp1, Tmp2, Tmp3, Result; 5054 5055 switch (getTypeAction(LHS.getValueType())) { 5056 case Legal: 5057 Tmp1 = LegalizeOp(LHS); // LHS 5058 Tmp2 = LegalizeOp(RHS); // RHS 5059 break; 5060 case Promote: 5061 Tmp1 = PromoteOp(LHS); // LHS 5062 Tmp2 = PromoteOp(RHS); // RHS 5063 5064 // If this is an FP compare, the operands have already been extended. 5065 if (LHS.getValueType().isInteger()) { 5066 MVT VT = LHS.getValueType(); 5067 MVT NVT = TLI.getTypeToTransformTo(VT); 5068 5069 // Otherwise, we have to insert explicit sign or zero extends. Note 5070 // that we could insert sign extends for ALL conditions, but zero extend 5071 // is cheaper on many machines (an AND instead of two shifts), so prefer 5072 // it. 5073 switch (cast<CondCodeSDNode>(CC)->get()) { 5074 default: assert(0 && "Unknown integer comparison!"); 5075 case ISD::SETEQ: 5076 case ISD::SETNE: 5077 case ISD::SETUGE: 5078 case ISD::SETUGT: 5079 case ISD::SETULE: 5080 case ISD::SETULT: 5081 // ALL of these operations will work if we either sign or zero extend 5082 // the operands (including the unsigned comparisons!). Zero extend is 5083 // usually a simpler/cheaper operation, so prefer it. 5084 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 5085 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 5086 break; 5087 case ISD::SETGE: 5088 case ISD::SETGT: 5089 case ISD::SETLT: 5090 case ISD::SETLE: 5091 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 5092 DAG.getValueType(VT)); 5093 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 5094 DAG.getValueType(VT)); 5095 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes. 5096 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes. 5097 break; 5098 } 5099 } 5100 break; 5101 case Expand: { 5102 MVT VT = LHS.getValueType(); 5103 if (VT == MVT::f32 || VT == MVT::f64) { 5104 // Expand into one or more soft-fp libcall(s). 5105 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; 5106 switch (cast<CondCodeSDNode>(CC)->get()) { 5107 case ISD::SETEQ: 5108 case ISD::SETOEQ: 5109 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 5110 break; 5111 case ISD::SETNE: 5112 case ISD::SETUNE: 5113 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 5114 break; 5115 case ISD::SETGE: 5116 case ISD::SETOGE: 5117 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 5118 break; 5119 case ISD::SETLT: 5120 case ISD::SETOLT: 5121 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 5122 break; 5123 case ISD::SETLE: 5124 case ISD::SETOLE: 5125 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 5126 break; 5127 case ISD::SETGT: 5128 case ISD::SETOGT: 5129 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 5130 break; 5131 case ISD::SETUO: 5132 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 5133 break; 5134 case ISD::SETO: 5135 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 5136 break; 5137 default: 5138 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 5139 switch (cast<CondCodeSDNode>(CC)->get()) { 5140 case ISD::SETONE: 5141 // SETONE = SETOLT | SETOGT 5142 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 5143 // Fallthrough 5144 case ISD::SETUGT: 5145 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 5146 break; 5147 case ISD::SETUGE: 5148 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 5149 break; 5150 case ISD::SETULT: 5151 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 5152 break; 5153 case ISD::SETULE: 5154 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 5155 break; 5156 case ISD::SETUEQ: 5157 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 5158 break; 5159 default: assert(0 && "Unsupported FP setcc!"); 5160 } 5161 } 5162 5163 SDValue Dummy; 5164 SDValue Ops[2] = { LHS, RHS }; 5165 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(), 5166 false /*sign irrelevant*/, Dummy); 5167 Tmp2 = DAG.getConstant(0, MVT::i32); 5168 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 5169 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 5170 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 5171 CC); 5172 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(), 5173 false /*sign irrelevant*/, Dummy); 5174 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2, 5175 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 5176 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 5177 Tmp2 = SDValue(); 5178 } 5179 LHS = LegalizeOp(Tmp1); 5180 RHS = Tmp2; 5181 return; 5182 } 5183 5184 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 5185 ExpandOp(LHS, LHSLo, LHSHi); 5186 ExpandOp(RHS, RHSLo, RHSHi); 5187 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 5188 5189 if (VT==MVT::ppcf128) { 5190 // FIXME: This generated code sucks. We want to generate 5191 // FCMPU crN, hi1, hi2 5192 // BNE crN, L: 5193 // FCMPU crN, lo1, lo2 5194 // The following can be improved, but not that much. 5195 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 5196 ISD::SETOEQ); 5197 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode); 5198 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 5199 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 5200 ISD::SETUNE); 5201 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode); 5202 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 5203 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 5204 Tmp2 = SDValue(); 5205 break; 5206 } 5207 5208 switch (CCCode) { 5209 case ISD::SETEQ: 5210 case ISD::SETNE: 5211 if (RHSLo == RHSHi) 5212 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 5213 if (RHSCST->isAllOnesValue()) { 5214 // Comparison to -1. 5215 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 5216 Tmp2 = RHSLo; 5217 break; 5218 } 5219 5220 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 5221 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 5222 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 5223 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 5224 break; 5225 default: 5226 // If this is a comparison of the sign bit, just look at the top part. 5227 // X > -1, x < 0 5228 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 5229 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 5230 CST->isNullValue()) || // X < 0 5231 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 5232 CST->isAllOnesValue())) { // X > -1 5233 Tmp1 = LHSHi; 5234 Tmp2 = RHSHi; 5235 break; 5236 } 5237 5238 // FIXME: This generated code sucks. 5239 ISD::CondCode LowCC; 5240 switch (CCCode) { 5241 default: assert(0 && "Unknown integer setcc!"); 5242 case ISD::SETLT: 5243 case ISD::SETULT: LowCC = ISD::SETULT; break; 5244 case ISD::SETGT: 5245 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 5246 case ISD::SETLE: 5247 case ISD::SETULE: LowCC = ISD::SETULE; break; 5248 case ISD::SETGE: 5249 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 5250 } 5251 5252 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 5253 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 5254 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 5255 5256 // NOTE: on targets without efficient SELECT of bools, we can always use 5257 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 5258 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 5259 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, 5260 LowCC, false, DagCombineInfo); 5261 if (!Tmp1.getNode()) 5262 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 5263 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 5264 CCCode, false, DagCombineInfo); 5265 if (!Tmp2.getNode()) 5266 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, 5267 RHSHi,CC); 5268 5269 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 5270 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 5271 if ((Tmp1C && Tmp1C->isNullValue()) || 5272 (Tmp2C && Tmp2C->isNullValue() && 5273 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 5274 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 5275 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 5276 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 5277 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 5278 // low part is known false, returns high part. 5279 // For LE / GE, if high part is known false, ignore the low part. 5280 // For LT / GT, if high part is known true, ignore the low part. 5281 Tmp1 = Tmp2; 5282 Tmp2 = SDValue(); 5283 } else { 5284 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 5285 ISD::SETEQ, false, DagCombineInfo); 5286 if (!Result.getNode()) 5287 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 5288 ISD::SETEQ); 5289 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 5290 Result, Tmp1, Tmp2)); 5291 Tmp1 = Result; 5292 Tmp2 = SDValue(); 5293 } 5294 } 5295 } 5296 } 5297 LHS = Tmp1; 5298 RHS = Tmp2; 5299} 5300 5301/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 5302/// condition code CC on the current target. This routine assumes LHS and rHS 5303/// have already been legalized by LegalizeSetCCOperands. It expands SETCC with 5304/// illegal condition code into AND / OR of multiple SETCC values. 5305void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, 5306 SDValue &LHS, SDValue &RHS, 5307 SDValue &CC) { 5308 MVT OpVT = LHS.getValueType(); 5309 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 5310 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 5311 default: assert(0 && "Unknown condition code action!"); 5312 case TargetLowering::Legal: 5313 // Nothing to do. 5314 break; 5315 case TargetLowering::Expand: { 5316 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 5317 unsigned Opc = 0; 5318 switch (CCCode) { 5319 default: assert(0 && "Don't know how to expand this condition!"); abort(); 5320 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 5321 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 5322 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 5323 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 5324 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 5325 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 5326 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5327 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5328 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5329 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5330 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5331 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5332 // FIXME: Implement more expansions. 5333 } 5334 5335 SDValue SetCC1 = DAG.getSetCC(VT, LHS, RHS, CC1); 5336 SDValue SetCC2 = DAG.getSetCC(VT, LHS, RHS, CC2); 5337 LHS = DAG.getNode(Opc, VT, SetCC1, SetCC2); 5338 RHS = SDValue(); 5339 CC = SDValue(); 5340 break; 5341 } 5342 } 5343} 5344 5345/// EmitStackConvert - Emit a store/load combination to the stack. This stores 5346/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 5347/// a load from the stack slot to DestVT, extending it if needed. 5348/// The resultant code need not be legal. 5349SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 5350 MVT SlotVT, 5351 MVT DestVT) { 5352 // Create the stack frame object. 5353 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment( 5354 SrcOp.getValueType().getTypeForMVT()); 5355 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 5356 5357 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 5358 int SPFI = StackPtrFI->getIndex(); 5359 5360 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 5361 unsigned SlotSize = SlotVT.getSizeInBits(); 5362 unsigned DestSize = DestVT.getSizeInBits(); 5363 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment( 5364 DestVT.getTypeForMVT()); 5365 5366 // Emit a store to the stack slot. Use a truncstore if the input value is 5367 // later than DestVT. 5368 SDValue Store; 5369 5370 if (SrcSize > SlotSize) 5371 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, 5372 PseudoSourceValue::getFixedStack(SPFI), 0, 5373 SlotVT, false, SrcAlign); 5374 else { 5375 assert(SrcSize == SlotSize && "Invalid store"); 5376 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, 5377 PseudoSourceValue::getFixedStack(SPFI), 0, 5378 false, SrcAlign); 5379 } 5380 5381 // Result is a load from the stack slot. 5382 if (SlotSize == DestSize) 5383 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign); 5384 5385 assert(SlotSize < DestSize && "Unknown extension!"); 5386 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT, 5387 false, DestAlign); 5388} 5389 5390SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 5391 // Create a vector sized/aligned stack slot, store the value to element #0, 5392 // then load the whole vector back out. 5393 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 5394 5395 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 5396 int SPFI = StackPtrFI->getIndex(); 5397 5398 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 5399 PseudoSourceValue::getFixedStack(SPFI), 0); 5400 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, 5401 PseudoSourceValue::getFixedStack(SPFI), 0); 5402} 5403 5404 5405/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 5406/// support the operation, but do support the resultant vector type. 5407SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 5408 5409 // If the only non-undef value is the low element, turn this into a 5410 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 5411 unsigned NumElems = Node->getNumOperands(); 5412 bool isOnlyLowElement = true; 5413 SDValue SplatValue = Node->getOperand(0); 5414 5415 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t> 5416 // and use a bitmask instead of a list of elements. 5417 std::map<SDValue, std::vector<unsigned> > Values; 5418 Values[SplatValue].push_back(0); 5419 bool isConstant = true; 5420 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 5421 SplatValue.getOpcode() != ISD::UNDEF) 5422 isConstant = false; 5423 5424 for (unsigned i = 1; i < NumElems; ++i) { 5425 SDValue V = Node->getOperand(i); 5426 Values[V].push_back(i); 5427 if (V.getOpcode() != ISD::UNDEF) 5428 isOnlyLowElement = false; 5429 if (SplatValue != V) 5430 SplatValue = SDValue(0,0); 5431 5432 // If this isn't a constant element or an undef, we can't use a constant 5433 // pool load. 5434 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 5435 V.getOpcode() != ISD::UNDEF) 5436 isConstant = false; 5437 } 5438 5439 if (isOnlyLowElement) { 5440 // If the low element is an undef too, then this whole things is an undef. 5441 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 5442 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 5443 // Otherwise, turn this into a scalar_to_vector node. 5444 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 5445 Node->getOperand(0)); 5446 } 5447 5448 // If all elements are constants, create a load from the constant pool. 5449 if (isConstant) { 5450 MVT VT = Node->getValueType(0); 5451 std::vector<Constant*> CV; 5452 for (unsigned i = 0, e = NumElems; i != e; ++i) { 5453 if (ConstantFPSDNode *V = 5454 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 5455 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 5456 } else if (ConstantSDNode *V = 5457 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 5458 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 5459 } else { 5460 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 5461 const Type *OpNTy = 5462 Node->getOperand(0).getValueType().getTypeForMVT(); 5463 CV.push_back(UndefValue::get(OpNTy)); 5464 } 5465 } 5466 Constant *CP = ConstantVector::get(CV); 5467 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 5468 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5469 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 5470 PseudoSourceValue::getConstantPool(), 0, 5471 false, Alignment); 5472 } 5473 5474 if (SplatValue.getNode()) { // Splat of one value? 5475 // Build the shuffle constant vector: <0, 0, 0, 0> 5476 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5477 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); 5478 std::vector<SDValue> ZeroVec(NumElems, Zero); 5479 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5480 &ZeroVec[0], ZeroVec.size()); 5481 5482 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 5483 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 5484 // Get the splatted value into the low element of a vector register. 5485 SDValue LowValVec = 5486 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 5487 5488 // Return shuffle(LowValVec, undef, <0,0,0,0>) 5489 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 5490 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 5491 SplatMask); 5492 } 5493 } 5494 5495 // If there are only two unique elements, we may be able to turn this into a 5496 // vector shuffle. 5497 if (Values.size() == 2) { 5498 // Get the two values in deterministic order. 5499 SDValue Val1 = Node->getOperand(1); 5500 SDValue Val2; 5501 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin(); 5502 if (MI->first != Val1) 5503 Val2 = MI->first; 5504 else 5505 Val2 = (++MI)->first; 5506 5507 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our 5508 // vector shuffle has the undef vector on the RHS. 5509 if (Val1.getOpcode() == ISD::UNDEF) 5510 std::swap(Val1, Val2); 5511 5512 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 5513 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5514 MVT MaskEltVT = MaskVT.getVectorElementType(); 5515 std::vector<SDValue> MaskVec(NumElems); 5516 5517 // Set elements of the shuffle mask for Val1. 5518 std::vector<unsigned> &Val1Elts = Values[Val1]; 5519 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 5520 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT); 5521 5522 // Set elements of the shuffle mask for Val2. 5523 std::vector<unsigned> &Val2Elts = Values[Val2]; 5524 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 5525 if (Val2.getOpcode() != ISD::UNDEF) 5526 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); 5527 else 5528 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); 5529 5530 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5531 &MaskVec[0], MaskVec.size()); 5532 5533 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 5534 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 5535 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 5536 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); 5537 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); 5538 SDValue Ops[] = { Val1, Val2, ShuffleMask }; 5539 5540 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 5541 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); 5542 } 5543 } 5544 5545 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5546 // aligned object on the stack, store each element into it, then load 5547 // the result as a vector. 5548 MVT VT = Node->getValueType(0); 5549 // Create the stack frame object. 5550 SDValue FIPtr = DAG.CreateStackTemporary(VT); 5551 5552 // Emit a store of each element to the stack slot. 5553 SmallVector<SDValue, 8> Stores; 5554 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8; 5555 // Store (in the right endianness) the elements to memory. 5556 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5557 // Ignore undef elements. 5558 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5559 5560 unsigned Offset = TypeByteSize*i; 5561 5562 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5563 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 5564 5565 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 5566 NULL, 0)); 5567 } 5568 5569 SDValue StoreChain; 5570 if (!Stores.empty()) // Not all undef elements? 5571 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5572 &Stores[0], Stores.size()); 5573 else 5574 StoreChain = DAG.getEntryNode(); 5575 5576 // Result is a load from the stack slot. 5577 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 5578} 5579 5580void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5581 SDValue Op, SDValue Amt, 5582 SDValue &Lo, SDValue &Hi) { 5583 // Expand the subcomponents. 5584 SDValue LHSL, LHSH; 5585 ExpandOp(Op, LHSL, LHSH); 5586 5587 SDValue Ops[] = { LHSL, LHSH, Amt }; 5588 MVT VT = LHSL.getValueType(); 5589 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5590 Hi = Lo.getValue(1); 5591} 5592 5593 5594/// ExpandShift - Try to find a clever way to expand this shift operation out to 5595/// smaller elements. If we can't find a way that is more efficient than a 5596/// libcall on this target, return false. Otherwise, return true with the 5597/// low-parts expanded into Lo and Hi. 5598bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, 5599 SDValue &Lo, SDValue &Hi) { 5600 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5601 "This is not a shift!"); 5602 5603 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5604 SDValue ShAmt = LegalizeOp(Amt); 5605 MVT ShTy = ShAmt.getValueType(); 5606 unsigned ShBits = ShTy.getSizeInBits(); 5607 unsigned VTBits = Op.getValueType().getSizeInBits(); 5608 unsigned NVTBits = NVT.getSizeInBits(); 5609 5610 // Handle the case when Amt is an immediate. 5611 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) { 5612 unsigned Cst = CN->getZExtValue(); 5613 // Expand the incoming operand to be shifted, so that we have its parts 5614 SDValue InL, InH; 5615 ExpandOp(Op, InL, InH); 5616 switch(Opc) { 5617 case ISD::SHL: 5618 if (Cst > VTBits) { 5619 Lo = DAG.getConstant(0, NVT); 5620 Hi = DAG.getConstant(0, NVT); 5621 } else if (Cst > NVTBits) { 5622 Lo = DAG.getConstant(0, NVT); 5623 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5624 } else if (Cst == NVTBits) { 5625 Lo = DAG.getConstant(0, NVT); 5626 Hi = InL; 5627 } else { 5628 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 5629 Hi = DAG.getNode(ISD::OR, NVT, 5630 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 5631 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 5632 } 5633 return true; 5634 case ISD::SRL: 5635 if (Cst > VTBits) { 5636 Lo = DAG.getConstant(0, NVT); 5637 Hi = DAG.getConstant(0, NVT); 5638 } else if (Cst > NVTBits) { 5639 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5640 Hi = DAG.getConstant(0, NVT); 5641 } else if (Cst == NVTBits) { 5642 Lo = InH; 5643 Hi = DAG.getConstant(0, NVT); 5644 } else { 5645 Lo = DAG.getNode(ISD::OR, NVT, 5646 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5647 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5648 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 5649 } 5650 return true; 5651 case ISD::SRA: 5652 if (Cst > VTBits) { 5653 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 5654 DAG.getConstant(NVTBits-1, ShTy)); 5655 } else if (Cst > NVTBits) { 5656 Lo = DAG.getNode(ISD::SRA, NVT, InH, 5657 DAG.getConstant(Cst-NVTBits, ShTy)); 5658 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5659 DAG.getConstant(NVTBits-1, ShTy)); 5660 } else if (Cst == NVTBits) { 5661 Lo = InH; 5662 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5663 DAG.getConstant(NVTBits-1, ShTy)); 5664 } else { 5665 Lo = DAG.getNode(ISD::OR, NVT, 5666 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5667 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5668 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 5669 } 5670 return true; 5671 } 5672 } 5673 5674 // Okay, the shift amount isn't constant. However, if we can tell that it is 5675 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5676 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5677 APInt KnownZero, KnownOne; 5678 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5679 5680 // If we know that if any of the high bits of the shift amount are one, then 5681 // we can do this as a couple of simple shifts. 5682 if (KnownOne.intersects(Mask)) { 5683 // Mask out the high bit, which we know is set. 5684 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 5685 DAG.getConstant(~Mask, Amt.getValueType())); 5686 5687 // Expand the incoming operand to be shifted, so that we have its parts 5688 SDValue InL, InH; 5689 ExpandOp(Op, InL, InH); 5690 switch(Opc) { 5691 case ISD::SHL: 5692 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5693 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 5694 return true; 5695 case ISD::SRL: 5696 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5697 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 5698 return true; 5699 case ISD::SRA: 5700 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 5701 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5702 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 5703 return true; 5704 } 5705 } 5706 5707 // If we know that the high bits of the shift amount are all zero, then we can 5708 // do this as a couple of simple shifts. 5709 if ((KnownZero & Mask) == Mask) { 5710 // Compute 32-amt. 5711 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 5712 DAG.getConstant(NVTBits, Amt.getValueType()), 5713 Amt); 5714 5715 // Expand the incoming operand to be shifted, so that we have its parts 5716 SDValue InL, InH; 5717 ExpandOp(Op, InL, InH); 5718 switch(Opc) { 5719 case ISD::SHL: 5720 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 5721 Hi = DAG.getNode(ISD::OR, NVT, 5722 DAG.getNode(ISD::SHL, NVT, InH, Amt), 5723 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 5724 return true; 5725 case ISD::SRL: 5726 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 5727 Lo = DAG.getNode(ISD::OR, NVT, 5728 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5729 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5730 return true; 5731 case ISD::SRA: 5732 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 5733 Lo = DAG.getNode(ISD::OR, NVT, 5734 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5735 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5736 return true; 5737 } 5738 } 5739 5740 return false; 5741} 5742 5743 5744// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5745// does not fit into a register, return the lo part and set the hi part to the 5746// by-reg argument. If it does fit into a single register, return the result 5747// and leave the Hi part unset. 5748SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 5749 bool isSigned, SDValue &Hi) { 5750 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5751 // The input chain to this libcall is the entry node of the function. 5752 // Legalizing the call will automatically add the previous call to the 5753 // dependence. 5754 SDValue InChain = DAG.getEntryNode(); 5755 5756 TargetLowering::ArgListTy Args; 5757 TargetLowering::ArgListEntry Entry; 5758 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5759 MVT ArgVT = Node->getOperand(i).getValueType(); 5760 const Type *ArgTy = ArgVT.getTypeForMVT(); 5761 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5762 Entry.isSExt = isSigned; 5763 Entry.isZExt = !isSigned; 5764 Args.push_back(Entry); 5765 } 5766 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 5767 TLI.getPointerTy()); 5768 5769 // Splice the libcall in wherever FindInputOutputChains tells us to. 5770 const Type *RetTy = Node->getValueType(0).getTypeForMVT(); 5771 std::pair<SDValue,SDValue> CallInfo = 5772 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 5773 CallingConv::C, false, Callee, Args, DAG); 5774 5775 // Legalize the call sequence, starting with the chain. This will advance 5776 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5777 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5778 LegalizeOp(CallInfo.second); 5779 SDValue Result; 5780 switch (getTypeAction(CallInfo.first.getValueType())) { 5781 default: assert(0 && "Unknown thing"); 5782 case Legal: 5783 Result = CallInfo.first; 5784 break; 5785 case Expand: 5786 ExpandOp(CallInfo.first, Result, Hi); 5787 break; 5788 } 5789 return Result; 5790} 5791 5792/// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation. 5793/// 5794SDValue SelectionDAGLegalize:: 5795LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) { 5796 bool isCustom = false; 5797 SDValue Tmp1; 5798 switch (getTypeAction(Op.getValueType())) { 5799 case Legal: 5800 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5801 Op.getValueType())) { 5802 default: assert(0 && "Unknown operation action!"); 5803 case TargetLowering::Custom: 5804 isCustom = true; 5805 // FALLTHROUGH 5806 case TargetLowering::Legal: 5807 Tmp1 = LegalizeOp(Op); 5808 if (Result.getNode()) 5809 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5810 else 5811 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5812 DestTy, Tmp1); 5813 if (isCustom) { 5814 Tmp1 = TLI.LowerOperation(Result, DAG); 5815 if (Tmp1.getNode()) Result = Tmp1; 5816 } 5817 break; 5818 case TargetLowering::Expand: 5819 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy); 5820 break; 5821 case TargetLowering::Promote: 5822 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned); 5823 break; 5824 } 5825 break; 5826 case Expand: 5827 Result = ExpandIntToFP(isSigned, DestTy, Op); 5828 break; 5829 case Promote: 5830 Tmp1 = PromoteOp(Op); 5831 if (isSigned) { 5832 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 5833 Tmp1, DAG.getValueType(Op.getValueType())); 5834 } else { 5835 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 5836 Op.getValueType()); 5837 } 5838 if (Result.getNode()) 5839 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5840 else 5841 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5842 DestTy, Tmp1); 5843 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 5844 break; 5845 } 5846 return Result; 5847} 5848 5849/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5850/// 5851SDValue SelectionDAGLegalize:: 5852ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) { 5853 MVT SourceVT = Source.getValueType(); 5854 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5855 5856 // Expand unsupported int-to-fp vector casts by unrolling them. 5857 if (DestTy.isVector()) { 5858 if (!ExpandSource) 5859 return LegalizeOp(UnrollVectorOp(Source)); 5860 MVT DestEltTy = DestTy.getVectorElementType(); 5861 if (DestTy.getVectorNumElements() == 1) { 5862 SDValue Scalar = ScalarizeVectorOp(Source); 5863 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned, 5864 DestEltTy, Scalar); 5865 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result); 5866 } 5867 SDValue Lo, Hi; 5868 SplitVectorOp(Source, Lo, Hi); 5869 MVT SplitDestTy = MVT::getVectorVT(DestEltTy, 5870 DestTy.getVectorNumElements() / 2); 5871 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo); 5872 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi); 5873 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult, 5874 HiResult)); 5875 } 5876 5877 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. 5878 if (!isSigned && SourceVT != MVT::i32) { 5879 // The integer value loaded will be incorrectly if the 'sign bit' of the 5880 // incoming integer is set. To handle this, we dynamically test to see if 5881 // it is set, and, if so, add a fudge factor. 5882 SDValue Hi; 5883 if (ExpandSource) { 5884 SDValue Lo; 5885 ExpandOp(Source, Lo, Hi); 5886 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi); 5887 } else { 5888 // The comparison for the sign bit will use the entire operand. 5889 Hi = Source; 5890 } 5891 5892 // Check to see if the target has a custom way to lower this. If so, use 5893 // it. (Note we've already expanded the operand in this case.) 5894 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) { 5895 default: assert(0 && "This action not implemented for this operation!"); 5896 case TargetLowering::Legal: 5897 case TargetLowering::Expand: 5898 break; // This case is handled below. 5899 case TargetLowering::Custom: { 5900 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy, 5901 Source), DAG); 5902 if (NV.getNode()) 5903 return LegalizeOp(NV); 5904 break; // The target decided this was legal after all 5905 } 5906 } 5907 5908 // If this is unsigned, and not supported, first perform the conversion to 5909 // signed, then adjust the result if the sign bit is set. 5910 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source); 5911 5912 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 5913 DAG.getConstant(0, Hi.getValueType()), 5914 ISD::SETLT); 5915 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5916 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5917 SignSet, Four, Zero); 5918 uint64_t FF = 0x5f800000ULL; 5919 if (TLI.isLittleEndian()) FF <<= 32; 5920 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5921 5922 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5923 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5924 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5925 Alignment = std::min(Alignment, 4u); 5926 SDValue FudgeInReg; 5927 if (DestTy == MVT::f32) 5928 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5929 PseudoSourceValue::getConstantPool(), 0, 5930 false, Alignment); 5931 else if (DestTy.bitsGT(MVT::f32)) 5932 // FIXME: Avoid the extend by construction the right constantpool? 5933 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5934 CPIdx, 5935 PseudoSourceValue::getConstantPool(), 0, 5936 MVT::f32, false, Alignment); 5937 else 5938 assert(0 && "Unexpected conversion"); 5939 5940 MVT SCVT = SignedConv.getValueType(); 5941 if (SCVT != DestTy) { 5942 // Destination type needs to be expanded as well. The FADD now we are 5943 // constructing will be expanded into a libcall. 5944 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { 5945 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); 5946 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, 5947 SignedConv, SignedConv.getValue(1)); 5948 } 5949 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5950 } 5951 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5952 } 5953 5954 // Check to see if the target has a custom way to lower this. If so, use it. 5955 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 5956 default: assert(0 && "This action not implemented for this operation!"); 5957 case TargetLowering::Legal: 5958 case TargetLowering::Expand: 5959 break; // This case is handled below. 5960 case TargetLowering::Custom: { 5961 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5962 Source), DAG); 5963 if (NV.getNode()) 5964 return LegalizeOp(NV); 5965 break; // The target decided this was legal after all 5966 } 5967 } 5968 5969 // Expand the source, then glue it back together for the call. We must expand 5970 // the source in case it is shared (this pass of legalize must traverse it). 5971 if (ExpandSource) { 5972 SDValue SrcLo, SrcHi; 5973 ExpandOp(Source, SrcLo, SrcHi); 5974 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); 5975 } 5976 5977 RTLIB::Libcall LC = isSigned ? 5978 RTLIB::getSINTTOFP(SourceVT, DestTy) : 5979 RTLIB::getUINTTOFP(SourceVT, DestTy); 5980 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type"); 5981 5982 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5983 SDValue HiPart; 5984 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart); 5985 if (Result.getValueType() != DestTy && HiPart.getNode()) 5986 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart); 5987 return Result; 5988} 5989 5990/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5991/// INT_TO_FP operation of the specified operand when the target requests that 5992/// we expand it. At this point, we know that the result and operand types are 5993/// legal for the target. 5994SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5995 SDValue Op0, 5996 MVT DestVT) { 5997 if (Op0.getValueType() == MVT::i32) { 5998 // simple 32-bit [signed|unsigned] integer to float/double expansion 5999 6000 // Get the stack frame index of a 8 byte buffer. 6001 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 6002 6003 // word offset constant for Hi/Lo address computation 6004 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 6005 // set up Hi and Lo (into buffer) address based on endian 6006 SDValue Hi = StackSlot; 6007 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 6008 if (TLI.isLittleEndian()) 6009 std::swap(Hi, Lo); 6010 6011 // if signed map to unsigned space 6012 SDValue Op0Mapped; 6013 if (isSigned) { 6014 // constant used to invert sign bit (signed to unsigned mapping) 6015 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 6016 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 6017 } else { 6018 Op0Mapped = Op0; 6019 } 6020 // store the lo of the constructed double - based on integer input 6021 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), 6022 Op0Mapped, Lo, NULL, 0); 6023 // initial hi portion of constructed double 6024 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 6025 // store the hi of the constructed double - biased exponent 6026 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 6027 // load the constructed double 6028 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 6029 // FP constant to bias correct the final result 6030 SDValue Bias = DAG.getConstantFP(isSigned ? 6031 BitsToDouble(0x4330000080000000ULL) 6032 : BitsToDouble(0x4330000000000000ULL), 6033 MVT::f64); 6034 // subtract the bias 6035 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 6036 // final result 6037 SDValue Result; 6038 // handle final rounding 6039 if (DestVT == MVT::f64) { 6040 // do nothing 6041 Result = Sub; 6042 } else if (DestVT.bitsLT(MVT::f64)) { 6043 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 6044 DAG.getIntPtrConstant(0)); 6045 } else if (DestVT.bitsGT(MVT::f64)) { 6046 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 6047 } 6048 return Result; 6049 } 6050 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 6051 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 6052 6053 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0, 6054 DAG.getConstant(0, Op0.getValueType()), 6055 ISD::SETLT); 6056 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 6057 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 6058 SignSet, Four, Zero); 6059 6060 // If the sign bit of the integer is set, the large number will be treated 6061 // as a negative number. To counteract this, the dynamic code adds an 6062 // offset depending on the data type. 6063 uint64_t FF; 6064 switch (Op0.getValueType().getSimpleVT()) { 6065 default: assert(0 && "Unsupported integer type!"); 6066 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 6067 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 6068 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 6069 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 6070 } 6071 if (TLI.isLittleEndian()) FF <<= 32; 6072 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 6073 6074 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 6075 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6076 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 6077 Alignment = std::min(Alignment, 4u); 6078 SDValue FudgeInReg; 6079 if (DestVT == MVT::f32) 6080 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 6081 PseudoSourceValue::getConstantPool(), 0, 6082 false, Alignment); 6083 else { 6084 FudgeInReg = 6085 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 6086 DAG.getEntryNode(), CPIdx, 6087 PseudoSourceValue::getConstantPool(), 0, 6088 MVT::f32, false, Alignment)); 6089 } 6090 6091 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 6092} 6093 6094/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 6095/// *INT_TO_FP operation of the specified operand when the target requests that 6096/// we promote it. At this point, we know that the result and operand types are 6097/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 6098/// operation that takes a larger input. 6099SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 6100 MVT DestVT, 6101 bool isSigned) { 6102 // First step, figure out the appropriate *INT_TO_FP operation to use. 6103 MVT NewInTy = LegalOp.getValueType(); 6104 6105 unsigned OpToUse = 0; 6106 6107 // Scan for the appropriate larger type to use. 6108 while (1) { 6109 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 6110 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 6111 6112 // If the target supports SINT_TO_FP of this type, use it. 6113 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 6114 default: break; 6115 case TargetLowering::Legal: 6116 if (!TLI.isTypeLegal(NewInTy)) 6117 break; // Can't use this datatype. 6118 // FALL THROUGH. 6119 case TargetLowering::Custom: 6120 OpToUse = ISD::SINT_TO_FP; 6121 break; 6122 } 6123 if (OpToUse) break; 6124 if (isSigned) continue; 6125 6126 // If the target supports UINT_TO_FP of this type, use it. 6127 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 6128 default: break; 6129 case TargetLowering::Legal: 6130 if (!TLI.isTypeLegal(NewInTy)) 6131 break; // Can't use this datatype. 6132 // FALL THROUGH. 6133 case TargetLowering::Custom: 6134 OpToUse = ISD::UINT_TO_FP; 6135 break; 6136 } 6137 if (OpToUse) break; 6138 6139 // Otherwise, try a larger type. 6140 } 6141 6142 // Okay, we found the operation and type to use. Zero extend our input to the 6143 // desired type then run the operation on it. 6144 return DAG.getNode(OpToUse, DestVT, 6145 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 6146 NewInTy, LegalOp)); 6147} 6148 6149/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 6150/// FP_TO_*INT operation of the specified operand when the target requests that 6151/// we promote it. At this point, we know that the result and operand types are 6152/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 6153/// operation that returns a larger result. 6154SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 6155 MVT DestVT, 6156 bool isSigned) { 6157 // First step, figure out the appropriate FP_TO*INT operation to use. 6158 MVT NewOutTy = DestVT; 6159 6160 unsigned OpToUse = 0; 6161 6162 // Scan for the appropriate larger type to use. 6163 while (1) { 6164 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 6165 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 6166 6167 // If the target supports FP_TO_SINT returning this type, use it. 6168 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 6169 default: break; 6170 case TargetLowering::Legal: 6171 if (!TLI.isTypeLegal(NewOutTy)) 6172 break; // Can't use this datatype. 6173 // FALL THROUGH. 6174 case TargetLowering::Custom: 6175 OpToUse = ISD::FP_TO_SINT; 6176 break; 6177 } 6178 if (OpToUse) break; 6179 6180 // If the target supports FP_TO_UINT of this type, use it. 6181 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 6182 default: break; 6183 case TargetLowering::Legal: 6184 if (!TLI.isTypeLegal(NewOutTy)) 6185 break; // Can't use this datatype. 6186 // FALL THROUGH. 6187 case TargetLowering::Custom: 6188 OpToUse = ISD::FP_TO_UINT; 6189 break; 6190 } 6191 if (OpToUse) break; 6192 6193 // Otherwise, try a larger type. 6194 } 6195 6196 6197 // Okay, we found the operation and type to use. 6198 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 6199 6200 // If the operation produces an invalid type, it must be custom lowered. Use 6201 // the target lowering hooks to expand it. Just keep the low part of the 6202 // expanded operation, we know that we're truncating anyway. 6203 if (getTypeAction(NewOutTy) == Expand) { 6204 SmallVector<SDValue, 2> Results; 6205 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG); 6206 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!"); 6207 Operation = Results[0]; 6208 } 6209 6210 // Truncate the result of the extended FP_TO_*INT operation to the desired 6211 // size. 6212 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 6213} 6214 6215/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 6216/// 6217SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) { 6218 MVT VT = Op.getValueType(); 6219 MVT SHVT = TLI.getShiftAmountTy(); 6220 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 6221 switch (VT.getSimpleVT()) { 6222 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 6223 case MVT::i16: 6224 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 6225 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 6226 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 6227 case MVT::i32: 6228 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 6229 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 6230 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 6231 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 6232 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 6233 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 6234 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 6235 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 6236 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 6237 case MVT::i64: 6238 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 6239 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 6240 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 6241 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 6242 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 6243 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 6244 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 6245 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 6246 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 6247 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 6248 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 6249 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 6250 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 6251 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 6252 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 6253 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 6254 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 6255 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 6256 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 6257 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 6258 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 6259 } 6260} 6261 6262/// ExpandBitCount - Expand the specified bitcount instruction into operations. 6263/// 6264SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) { 6265 switch (Opc) { 6266 default: assert(0 && "Cannot expand this yet!"); 6267 case ISD::CTPOP: { 6268 static const uint64_t mask[6] = { 6269 0x5555555555555555ULL, 0x3333333333333333ULL, 6270 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 6271 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 6272 }; 6273 MVT VT = Op.getValueType(); 6274 MVT ShVT = TLI.getShiftAmountTy(); 6275 unsigned len = VT.getSizeInBits(); 6276 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 6277 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 6278 SDValue Tmp2 = DAG.getConstant(mask[i], VT); 6279 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 6280 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 6281 DAG.getNode(ISD::AND, VT, 6282 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 6283 } 6284 return Op; 6285 } 6286 case ISD::CTLZ: { 6287 // for now, we do this: 6288 // x = x | (x >> 1); 6289 // x = x | (x >> 2); 6290 // ... 6291 // x = x | (x >>16); 6292 // x = x | (x >>32); // for 64-bit input 6293 // return popcount(~x); 6294 // 6295 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 6296 MVT VT = Op.getValueType(); 6297 MVT ShVT = TLI.getShiftAmountTy(); 6298 unsigned len = VT.getSizeInBits(); 6299 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 6300 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 6301 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 6302 } 6303 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 6304 return DAG.getNode(ISD::CTPOP, VT, Op); 6305 } 6306 case ISD::CTTZ: { 6307 // for now, we use: { return popcount(~x & (x - 1)); } 6308 // unless the target has ctlz but not ctpop, in which case we use: 6309 // { return 32 - nlz(~x & (x-1)); } 6310 // see also http://www.hackersdelight.org/HDcode/ntz.cc 6311 MVT VT = Op.getValueType(); 6312 SDValue Tmp2 = DAG.getConstant(~0ULL, VT); 6313 SDValue Tmp3 = DAG.getNode(ISD::AND, VT, 6314 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 6315 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 6316 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 6317 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 6318 TLI.isOperationLegal(ISD::CTLZ, VT)) 6319 return DAG.getNode(ISD::SUB, VT, 6320 DAG.getConstant(VT.getSizeInBits(), VT), 6321 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 6322 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 6323 } 6324 } 6325} 6326 6327/// ExpandOp - Expand the specified SDValue into its two component pieces 6328/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 6329/// LegalizedNodes map is filled in for any results that are not expanded, the 6330/// ExpandedNodes map is filled in for any results that are expanded, and the 6331/// Lo/Hi values are returned. 6332void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){ 6333 MVT VT = Op.getValueType(); 6334 MVT NVT = TLI.getTypeToTransformTo(VT); 6335 SDNode *Node = Op.getNode(); 6336 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 6337 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() || 6338 VT.isVector()) && "Cannot expand to FP value or to larger int value!"); 6339 6340 // See if we already expanded it. 6341 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I 6342 = ExpandedNodes.find(Op); 6343 if (I != ExpandedNodes.end()) { 6344 Lo = I->second.first; 6345 Hi = I->second.second; 6346 return; 6347 } 6348 6349 switch (Node->getOpcode()) { 6350 case ISD::CopyFromReg: 6351 assert(0 && "CopyFromReg must be legal!"); 6352 case ISD::FP_ROUND_INREG: 6353 if (VT == MVT::ppcf128 && 6354 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 6355 TargetLowering::Custom) { 6356 SDValue SrcLo, SrcHi, Src; 6357 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 6358 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 6359 SDValue Result = TLI.LowerOperation( 6360 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 6361 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR); 6362 Lo = Result.getNode()->getOperand(0); 6363 Hi = Result.getNode()->getOperand(1); 6364 break; 6365 } 6366 // fall through 6367 default: 6368#ifndef NDEBUG 6369 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 6370#endif 6371 assert(0 && "Do not know how to expand this operator!"); 6372 abort(); 6373 case ISD::EXTRACT_ELEMENT: 6374 ExpandOp(Node->getOperand(0), Lo, Hi); 6375 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) 6376 return ExpandOp(Hi, Lo, Hi); 6377 return ExpandOp(Lo, Lo, Hi); 6378 case ISD::EXTRACT_VECTOR_ELT: 6379 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 6380 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 6381 return ExpandOp(Lo, Lo, Hi); 6382 case ISD::UNDEF: 6383 Lo = DAG.getNode(ISD::UNDEF, NVT); 6384 Hi = DAG.getNode(ISD::UNDEF, NVT); 6385 break; 6386 case ISD::Constant: { 6387 unsigned NVTBits = NVT.getSizeInBits(); 6388 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 6389 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 6390 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 6391 break; 6392 } 6393 case ISD::ConstantFP: { 6394 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 6395 if (CFP->getValueType(0) == MVT::ppcf128) { 6396 APInt api = CFP->getValueAPF().bitcastToAPInt(); 6397 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 6398 MVT::f64); 6399 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 6400 MVT::f64); 6401 break; 6402 } 6403 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 6404 if (getTypeAction(Lo.getValueType()) == Expand) 6405 ExpandOp(Lo, Lo, Hi); 6406 break; 6407 } 6408 case ISD::BUILD_PAIR: 6409 // Return the operands. 6410 Lo = Node->getOperand(0); 6411 Hi = Node->getOperand(1); 6412 break; 6413 6414 case ISD::MERGE_VALUES: 6415 if (Node->getNumValues() == 1) { 6416 ExpandOp(Op.getOperand(0), Lo, Hi); 6417 break; 6418 } 6419 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 6420 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 && 6421 Op.getValue(1).getValueType() == MVT::Other && 6422 "unhandled MERGE_VALUES"); 6423 ExpandOp(Op.getOperand(0), Lo, Hi); 6424 // Remember that we legalized the chain. 6425 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 6426 break; 6427 6428 case ISD::SIGN_EXTEND_INREG: 6429 ExpandOp(Node->getOperand(0), Lo, Hi); 6430 // sext_inreg the low part if needed. 6431 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 6432 6433 // The high part gets the sign extension from the lo-part. This handles 6434 // things like sextinreg V:i64 from i8. 6435 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6436 DAG.getConstant(NVT.getSizeInBits()-1, 6437 TLI.getShiftAmountTy())); 6438 break; 6439 6440 case ISD::BSWAP: { 6441 ExpandOp(Node->getOperand(0), Lo, Hi); 6442 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 6443 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 6444 Lo = TempLo; 6445 break; 6446 } 6447 6448 case ISD::CTPOP: 6449 ExpandOp(Node->getOperand(0), Lo, Hi); 6450 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 6451 DAG.getNode(ISD::CTPOP, NVT, Lo), 6452 DAG.getNode(ISD::CTPOP, NVT, Hi)); 6453 Hi = DAG.getConstant(0, NVT); 6454 break; 6455 6456 case ISD::CTLZ: { 6457 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 6458 ExpandOp(Node->getOperand(0), Lo, Hi); 6459 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 6460 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 6461 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC, 6462 ISD::SETNE); 6463 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 6464 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 6465 6466 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 6467 Hi = DAG.getConstant(0, NVT); 6468 break; 6469 } 6470 6471 case ISD::CTTZ: { 6472 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 6473 ExpandOp(Node->getOperand(0), Lo, Hi); 6474 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 6475 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 6476 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC, 6477 ISD::SETNE); 6478 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 6479 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 6480 6481 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 6482 Hi = DAG.getConstant(0, NVT); 6483 break; 6484 } 6485 6486 case ISD::VAARG: { 6487 SDValue Ch = Node->getOperand(0); // Legalize the chain. 6488 SDValue Ptr = Node->getOperand(1); // Legalize the pointer. 6489 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 6490 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 6491 6492 // Remember that we legalized the chain. 6493 Hi = LegalizeOp(Hi); 6494 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 6495 if (TLI.isBigEndian()) 6496 std::swap(Lo, Hi); 6497 break; 6498 } 6499 6500 case ISD::LOAD: { 6501 LoadSDNode *LD = cast<LoadSDNode>(Node); 6502 SDValue Ch = LD->getChain(); // Legalize the chain. 6503 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer. 6504 ISD::LoadExtType ExtType = LD->getExtensionType(); 6505 const Value *SV = LD->getSrcValue(); 6506 int SVOffset = LD->getSrcValueOffset(); 6507 unsigned Alignment = LD->getAlignment(); 6508 bool isVolatile = LD->isVolatile(); 6509 6510 if (ExtType == ISD::NON_EXTLOAD) { 6511 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset, 6512 isVolatile, Alignment); 6513 if (VT == MVT::f32 || VT == MVT::f64) { 6514 // f32->i32 or f64->i64 one to one expansion. 6515 // Remember that we legalized the chain. 6516 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 6517 // Recursively expand the new load. 6518 if (getTypeAction(NVT) == Expand) 6519 ExpandOp(Lo, Lo, Hi); 6520 break; 6521 } 6522 6523 // Increment the pointer to the other half. 6524 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; 6525 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6526 DAG.getIntPtrConstant(IncrementSize)); 6527 SVOffset += IncrementSize; 6528 Alignment = MinAlign(Alignment, IncrementSize); 6529 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset, 6530 isVolatile, Alignment); 6531 6532 // Build a factor node to remember that this load is independent of the 6533 // other one. 6534 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6535 Hi.getValue(1)); 6536 6537 // Remember that we legalized the chain. 6538 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6539 if (TLI.isBigEndian()) 6540 std::swap(Lo, Hi); 6541 } else { 6542 MVT EVT = LD->getMemoryVT(); 6543 6544 if ((VT == MVT::f64 && EVT == MVT::f32) || 6545 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 6546 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 6547 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV, 6548 SVOffset, isVolatile, Alignment); 6549 // Remember that we legalized the chain. 6550 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1))); 6551 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 6552 break; 6553 } 6554 6555 if (EVT == NVT) 6556 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, 6557 SVOffset, isVolatile, Alignment); 6558 else 6559 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV, 6560 SVOffset, EVT, isVolatile, 6561 Alignment); 6562 6563 // Remember that we legalized the chain. 6564 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 6565 6566 if (ExtType == ISD::SEXTLOAD) { 6567 // The high part is obtained by SRA'ing all but one of the bits of the 6568 // lo part. 6569 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6570 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6571 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6572 } else if (ExtType == ISD::ZEXTLOAD) { 6573 // The high part is just a zero. 6574 Hi = DAG.getConstant(0, NVT); 6575 } else /* if (ExtType == ISD::EXTLOAD) */ { 6576 // The high part is undefined. 6577 Hi = DAG.getNode(ISD::UNDEF, NVT); 6578 } 6579 } 6580 break; 6581 } 6582 case ISD::AND: 6583 case ISD::OR: 6584 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 6585 SDValue LL, LH, RL, RH; 6586 ExpandOp(Node->getOperand(0), LL, LH); 6587 ExpandOp(Node->getOperand(1), RL, RH); 6588 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 6589 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 6590 break; 6591 } 6592 case ISD::SELECT: { 6593 SDValue LL, LH, RL, RH; 6594 ExpandOp(Node->getOperand(1), LL, LH); 6595 ExpandOp(Node->getOperand(2), RL, RH); 6596 if (getTypeAction(NVT) == Expand) 6597 NVT = TLI.getTypeToExpandTo(NVT); 6598 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 6599 if (VT != MVT::f32) 6600 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 6601 break; 6602 } 6603 case ISD::SELECT_CC: { 6604 SDValue TL, TH, FL, FH; 6605 ExpandOp(Node->getOperand(2), TL, TH); 6606 ExpandOp(Node->getOperand(3), FL, FH); 6607 if (getTypeAction(NVT) == Expand) 6608 NVT = TLI.getTypeToExpandTo(NVT); 6609 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6610 Node->getOperand(1), TL, FL, Node->getOperand(4)); 6611 if (VT != MVT::f32) 6612 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6613 Node->getOperand(1), TH, FH, Node->getOperand(4)); 6614 break; 6615 } 6616 case ISD::ANY_EXTEND: 6617 // The low part is any extension of the input (which degenerates to a copy). 6618 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 6619 // The high part is undefined. 6620 Hi = DAG.getNode(ISD::UNDEF, NVT); 6621 break; 6622 case ISD::SIGN_EXTEND: { 6623 // The low part is just a sign extension of the input (which degenerates to 6624 // a copy). 6625 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 6626 6627 // The high part is obtained by SRA'ing all but one of the bits of the lo 6628 // part. 6629 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6630 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6631 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6632 break; 6633 } 6634 case ISD::ZERO_EXTEND: 6635 // The low part is just a zero extension of the input (which degenerates to 6636 // a copy). 6637 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 6638 6639 // The high part is just a zero. 6640 Hi = DAG.getConstant(0, NVT); 6641 break; 6642 6643 case ISD::TRUNCATE: { 6644 // The input value must be larger than this value. Expand *it*. 6645 SDValue NewLo; 6646 ExpandOp(Node->getOperand(0), NewLo, Hi); 6647 6648 // The low part is now either the right size, or it is closer. If not the 6649 // right size, make an illegal truncate so we recursively expand it. 6650 if (NewLo.getValueType() != Node->getValueType(0)) 6651 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 6652 ExpandOp(NewLo, Lo, Hi); 6653 break; 6654 } 6655 6656 case ISD::BIT_CONVERT: { 6657 SDValue Tmp; 6658 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6659 // If the target wants to, allow it to lower this itself. 6660 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6661 case Expand: assert(0 && "cannot expand FP!"); 6662 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6663 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6664 } 6665 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 6666 } 6667 6668 // f32 / f64 must be expanded to i32 / i64. 6669 if (VT == MVT::f32 || VT == MVT::f64) { 6670 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6671 if (getTypeAction(NVT) == Expand) 6672 ExpandOp(Lo, Lo, Hi); 6673 break; 6674 } 6675 6676 // If source operand will be expanded to the same type as VT, i.e. 6677 // i64 <- f64, i32 <- f32, expand the source operand instead. 6678 MVT VT0 = Node->getOperand(0).getValueType(); 6679 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6680 ExpandOp(Node->getOperand(0), Lo, Hi); 6681 break; 6682 } 6683 6684 // Turn this into a load/store pair by default. 6685 if (Tmp.getNode() == 0) 6686 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 6687 6688 ExpandOp(Tmp, Lo, Hi); 6689 break; 6690 } 6691 6692 case ISD::READCYCLECOUNTER: { 6693 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6694 TargetLowering::Custom && 6695 "Must custom expand ReadCycleCounter"); 6696 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6697 assert(Tmp.getNode() && "Node must be custom expanded!"); 6698 ExpandOp(Tmp.getValue(0), Lo, Hi); 6699 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6700 LegalizeOp(Tmp.getValue(1))); 6701 break; 6702 } 6703 6704 case ISD::ATOMIC_CMP_SWAP: { 6705 // This operation does not need a loop. 6706 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6707 assert(Tmp.getNode() && "Node must be custom expanded!"); 6708 ExpandOp(Tmp.getValue(0), Lo, Hi); 6709 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6710 LegalizeOp(Tmp.getValue(1))); 6711 break; 6712 } 6713 6714 case ISD::ATOMIC_LOAD_ADD: 6715 case ISD::ATOMIC_LOAD_SUB: 6716 case ISD::ATOMIC_LOAD_AND: 6717 case ISD::ATOMIC_LOAD_OR: 6718 case ISD::ATOMIC_LOAD_XOR: 6719 case ISD::ATOMIC_LOAD_NAND: 6720 case ISD::ATOMIC_SWAP: { 6721 // These operations require a loop to be generated. We can't do that yet, 6722 // so substitute a target-dependent pseudo and expand that later. 6723 SDValue In2Lo, In2Hi, In2; 6724 ExpandOp(Op.getOperand(2), In2Lo, In2Hi); 6725 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi); 6726 AtomicSDNode* Anode = cast<AtomicSDNode>(Node); 6727 SDValue Replace = 6728 DAG.getAtomic(Op.getOpcode(), Anode->getMemoryVT(), 6729 Op.getOperand(0), Op.getOperand(1), In2, 6730 Anode->getSrcValue(), Anode->getAlignment()); 6731 SDValue Result = TLI.LowerOperation(Replace, DAG); 6732 ExpandOp(Result.getValue(0), Lo, Hi); 6733 // Remember that we legalized the chain. 6734 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1))); 6735 break; 6736 } 6737 6738 // These operators cannot be expanded directly, emit them as calls to 6739 // library functions. 6740 case ISD::FP_TO_SINT: { 6741 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6742 SDValue Op; 6743 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6744 case Expand: assert(0 && "cannot expand FP!"); 6745 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6746 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6747 } 6748 6749 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 6750 6751 // Now that the custom expander is done, expand the result, which is still 6752 // VT. 6753 if (Op.getNode()) { 6754 ExpandOp(Op, Lo, Hi); 6755 break; 6756 } 6757 } 6758 6759 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(), 6760 VT); 6761 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!"); 6762 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6763 break; 6764 } 6765 6766 case ISD::FP_TO_UINT: { 6767 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6768 SDValue Op; 6769 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6770 case Expand: assert(0 && "cannot expand FP!"); 6771 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6772 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6773 } 6774 6775 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 6776 6777 // Now that the custom expander is done, expand the result. 6778 if (Op.getNode()) { 6779 ExpandOp(Op, Lo, Hi); 6780 break; 6781 } 6782 } 6783 6784 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(), 6785 VT); 6786 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 6787 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6788 break; 6789 } 6790 6791 case ISD::SHL: { 6792 // If the target wants custom lowering, do so. 6793 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6794 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6795 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 6796 Op = TLI.LowerOperation(Op, DAG); 6797 if (Op.getNode()) { 6798 // Now that the custom expander is done, expand the result, which is 6799 // still VT. 6800 ExpandOp(Op, Lo, Hi); 6801 break; 6802 } 6803 } 6804 6805 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6806 // this X << 1 as X+X. 6807 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6808 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 6809 TLI.isOperationLegal(ISD::ADDE, NVT)) { 6810 SDValue LoOps[2], HiOps[3]; 6811 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6812 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6813 LoOps[1] = LoOps[0]; 6814 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6815 6816 HiOps[1] = HiOps[0]; 6817 HiOps[2] = Lo.getValue(1); 6818 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6819 break; 6820 } 6821 } 6822 6823 // If we can emit an efficient shift operation, do so now. 6824 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6825 break; 6826 6827 // If this target supports SHL_PARTS, use it. 6828 TargetLowering::LegalizeAction Action = 6829 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6830 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6831 Action == TargetLowering::Custom) { 6832 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6833 break; 6834 } 6835 6836 // Otherwise, emit a libcall. 6837 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi); 6838 break; 6839 } 6840 6841 case ISD::SRA: { 6842 // If the target wants custom lowering, do so. 6843 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6844 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6845 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6846 Op = TLI.LowerOperation(Op, DAG); 6847 if (Op.getNode()) { 6848 // Now that the custom expander is done, expand the result, which is 6849 // still VT. 6850 ExpandOp(Op, Lo, Hi); 6851 break; 6852 } 6853 } 6854 6855 // If we can emit an efficient shift operation, do so now. 6856 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6857 break; 6858 6859 // If this target supports SRA_PARTS, use it. 6860 TargetLowering::LegalizeAction Action = 6861 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6862 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6863 Action == TargetLowering::Custom) { 6864 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6865 break; 6866 } 6867 6868 // Otherwise, emit a libcall. 6869 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi); 6870 break; 6871 } 6872 6873 case ISD::SRL: { 6874 // If the target wants custom lowering, do so. 6875 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6876 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6877 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 6878 Op = TLI.LowerOperation(Op, DAG); 6879 if (Op.getNode()) { 6880 // Now that the custom expander is done, expand the result, which is 6881 // still VT. 6882 ExpandOp(Op, Lo, Hi); 6883 break; 6884 } 6885 } 6886 6887 // If we can emit an efficient shift operation, do so now. 6888 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6889 break; 6890 6891 // If this target supports SRL_PARTS, use it. 6892 TargetLowering::LegalizeAction Action = 6893 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6894 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6895 Action == TargetLowering::Custom) { 6896 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6897 break; 6898 } 6899 6900 // Otherwise, emit a libcall. 6901 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi); 6902 break; 6903 } 6904 6905 case ISD::ADD: 6906 case ISD::SUB: { 6907 // If the target wants to custom expand this, let them. 6908 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6909 TargetLowering::Custom) { 6910 SDValue Result = TLI.LowerOperation(Op, DAG); 6911 if (Result.getNode()) { 6912 ExpandOp(Result, Lo, Hi); 6913 break; 6914 } 6915 } 6916 // Expand the subcomponents. 6917 SDValue LHSL, LHSH, RHSL, RHSH; 6918 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6919 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6920 SDValue LoOps[2], HiOps[3]; 6921 LoOps[0] = LHSL; 6922 LoOps[1] = RHSL; 6923 HiOps[0] = LHSH; 6924 HiOps[1] = RHSH; 6925 6926 //cascaded check to see if any smaller size has a a carry flag. 6927 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC; 6928 bool hasCarry = false; 6929 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) { 6930 MVT AVT = MVT::getIntegerVT(BitSize); 6931 if (TLI.isOperationLegal(OpV, AVT)) { 6932 hasCarry = true; 6933 break; 6934 } 6935 } 6936 6937 if(hasCarry) { 6938 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6939 if (Node->getOpcode() == ISD::ADD) { 6940 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6941 HiOps[2] = Lo.getValue(1); 6942 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6943 } else { 6944 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6945 HiOps[2] = Lo.getValue(1); 6946 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6947 } 6948 break; 6949 } else { 6950 if (Node->getOpcode() == ISD::ADD) { 6951 Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2); 6952 Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2); 6953 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), 6954 Lo, LoOps[0], ISD::SETULT); 6955 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1, 6956 DAG.getConstant(1, NVT), 6957 DAG.getConstant(0, NVT)); 6958 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), 6959 Lo, LoOps[1], ISD::SETULT); 6960 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2, 6961 DAG.getConstant(1, NVT), 6962 Carry1); 6963 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2); 6964 } else { 6965 Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2); 6966 Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2); 6967 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT); 6968 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp, 6969 DAG.getConstant(1, NVT), 6970 DAG.getConstant(0, NVT)); 6971 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow); 6972 } 6973 break; 6974 } 6975 } 6976 6977 case ISD::ADDC: 6978 case ISD::SUBC: { 6979 // Expand the subcomponents. 6980 SDValue LHSL, LHSH, RHSL, RHSH; 6981 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6982 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6983 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6984 SDValue LoOps[2] = { LHSL, RHSL }; 6985 SDValue HiOps[3] = { LHSH, RHSH }; 6986 6987 if (Node->getOpcode() == ISD::ADDC) { 6988 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6989 HiOps[2] = Lo.getValue(1); 6990 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6991 } else { 6992 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6993 HiOps[2] = Lo.getValue(1); 6994 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6995 } 6996 // Remember that we legalized the flag. 6997 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6998 break; 6999 } 7000 case ISD::ADDE: 7001 case ISD::SUBE: { 7002 // Expand the subcomponents. 7003 SDValue LHSL, LHSH, RHSL, RHSH; 7004 ExpandOp(Node->getOperand(0), LHSL, LHSH); 7005 ExpandOp(Node->getOperand(1), RHSL, RHSH); 7006 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 7007 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 7008 SDValue HiOps[3] = { LHSH, RHSH }; 7009 7010 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 7011 HiOps[2] = Lo.getValue(1); 7012 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 7013 7014 // Remember that we legalized the flag. 7015 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 7016 break; 7017 } 7018 case ISD::MUL: { 7019 // If the target wants to custom expand this, let them. 7020 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 7021 SDValue New = TLI.LowerOperation(Op, DAG); 7022 if (New.getNode()) { 7023 ExpandOp(New, Lo, Hi); 7024 break; 7025 } 7026 } 7027 7028 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 7029 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 7030 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 7031 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 7032 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 7033 SDValue LL, LH, RL, RH; 7034 ExpandOp(Node->getOperand(0), LL, LH); 7035 ExpandOp(Node->getOperand(1), RL, RH); 7036 unsigned OuterBitSize = Op.getValueSizeInBits(); 7037 unsigned InnerBitSize = RH.getValueSizeInBits(); 7038 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 7039 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 7040 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 7041 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 7042 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 7043 // The inputs are both zero-extended. 7044 if (HasUMUL_LOHI) { 7045 // We can emit a umul_lohi. 7046 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 7047 Hi = SDValue(Lo.getNode(), 1); 7048 break; 7049 } 7050 if (HasMULHU) { 7051 // We can emit a mulhu+mul. 7052 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 7053 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 7054 break; 7055 } 7056 } 7057 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 7058 // The input values are both sign-extended. 7059 if (HasSMUL_LOHI) { 7060 // We can emit a smul_lohi. 7061 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 7062 Hi = SDValue(Lo.getNode(), 1); 7063 break; 7064 } 7065 if (HasMULHS) { 7066 // We can emit a mulhs+mul. 7067 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 7068 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 7069 break; 7070 } 7071 } 7072 if (HasUMUL_LOHI) { 7073 // Lo,Hi = umul LHS, RHS. 7074 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 7075 DAG.getVTList(NVT, NVT), LL, RL); 7076 Lo = UMulLOHI; 7077 Hi = UMulLOHI.getValue(1); 7078 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 7079 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 7080 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 7081 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 7082 break; 7083 } 7084 if (HasMULHU) { 7085 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 7086 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 7087 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 7088 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 7089 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 7090 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 7091 break; 7092 } 7093 } 7094 7095 // If nothing else, we can make a libcall. 7096 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi); 7097 break; 7098 } 7099 case ISD::SDIV: 7100 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi); 7101 break; 7102 case ISD::UDIV: 7103 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi); 7104 break; 7105 case ISD::SREM: 7106 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi); 7107 break; 7108 case ISD::UREM: 7109 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi); 7110 break; 7111 7112 case ISD::FADD: 7113 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32, 7114 RTLIB::ADD_F64, 7115 RTLIB::ADD_F80, 7116 RTLIB::ADD_PPCF128), 7117 Node, false, Hi); 7118 break; 7119 case ISD::FSUB: 7120 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32, 7121 RTLIB::SUB_F64, 7122 RTLIB::SUB_F80, 7123 RTLIB::SUB_PPCF128), 7124 Node, false, Hi); 7125 break; 7126 case ISD::FMUL: 7127 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32, 7128 RTLIB::MUL_F64, 7129 RTLIB::MUL_F80, 7130 RTLIB::MUL_PPCF128), 7131 Node, false, Hi); 7132 break; 7133 case ISD::FDIV: 7134 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32, 7135 RTLIB::DIV_F64, 7136 RTLIB::DIV_F80, 7137 RTLIB::DIV_PPCF128), 7138 Node, false, Hi); 7139 break; 7140 case ISD::FP_EXTEND: { 7141 if (VT == MVT::ppcf128) { 7142 assert(Node->getOperand(0).getValueType()==MVT::f32 || 7143 Node->getOperand(0).getValueType()==MVT::f64); 7144 const uint64_t zero = 0; 7145 if (Node->getOperand(0).getValueType()==MVT::f32) 7146 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 7147 else 7148 Hi = Node->getOperand(0); 7149 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 7150 break; 7151 } 7152 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT); 7153 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!"); 7154 Lo = ExpandLibCall(LC, Node, true, Hi); 7155 break; 7156 } 7157 case ISD::FP_ROUND: { 7158 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(), 7159 VT); 7160 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!"); 7161 Lo = ExpandLibCall(LC, Node, true, Hi); 7162 break; 7163 } 7164 case ISD::FSQRT: 7165 case ISD::FSIN: 7166 case ISD::FCOS: 7167 case ISD::FLOG: 7168 case ISD::FLOG2: 7169 case ISD::FLOG10: 7170 case ISD::FEXP: 7171 case ISD::FEXP2: 7172 case ISD::FTRUNC: 7173 case ISD::FFLOOR: 7174 case ISD::FCEIL: 7175 case ISD::FRINT: 7176 case ISD::FNEARBYINT: 7177 case ISD::FPOW: 7178 case ISD::FPOWI: { 7179 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 7180 switch(Node->getOpcode()) { 7181 case ISD::FSQRT: 7182 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 7183 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 7184 break; 7185 case ISD::FSIN: 7186 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 7187 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 7188 break; 7189 case ISD::FCOS: 7190 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 7191 RTLIB::COS_F80, RTLIB::COS_PPCF128); 7192 break; 7193 case ISD::FLOG: 7194 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64, 7195 RTLIB::LOG_F80, RTLIB::LOG_PPCF128); 7196 break; 7197 case ISD::FLOG2: 7198 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 7199 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128); 7200 break; 7201 case ISD::FLOG10: 7202 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 7203 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128); 7204 break; 7205 case ISD::FEXP: 7206 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64, 7207 RTLIB::EXP_F80, RTLIB::EXP_PPCF128); 7208 break; 7209 case ISD::FEXP2: 7210 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 7211 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128); 7212 break; 7213 case ISD::FTRUNC: 7214 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 7215 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 7216 break; 7217 case ISD::FFLOOR: 7218 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 7219 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 7220 break; 7221 case ISD::FCEIL: 7222 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 7223 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 7224 break; 7225 case ISD::FRINT: 7226 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 7227 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 7228 break; 7229 case ISD::FNEARBYINT: 7230 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 7231 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 7232 break; 7233 case ISD::FPOW: 7234 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 7235 RTLIB::POW_PPCF128); 7236 break; 7237 case ISD::FPOWI: 7238 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80, 7239 RTLIB::POWI_PPCF128); 7240 break; 7241 default: assert(0 && "Unreachable!"); 7242 } 7243 Lo = ExpandLibCall(LC, Node, false, Hi); 7244 break; 7245 } 7246 case ISD::FABS: { 7247 if (VT == MVT::ppcf128) { 7248 SDValue Tmp; 7249 ExpandOp(Node->getOperand(0), Lo, Tmp); 7250 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 7251 // lo = hi==fabs(hi) ? lo : -lo; 7252 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 7253 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 7254 DAG.getCondCode(ISD::SETEQ)); 7255 break; 7256 } 7257 SDValue Mask = (VT == MVT::f64) 7258 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 7259 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 7260 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 7261 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 7262 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 7263 if (getTypeAction(NVT) == Expand) 7264 ExpandOp(Lo, Lo, Hi); 7265 break; 7266 } 7267 case ISD::FNEG: { 7268 if (VT == MVT::ppcf128) { 7269 ExpandOp(Node->getOperand(0), Lo, Hi); 7270 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 7271 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 7272 break; 7273 } 7274 SDValue Mask = (VT == MVT::f64) 7275 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 7276 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 7277 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 7278 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 7279 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 7280 if (getTypeAction(NVT) == Expand) 7281 ExpandOp(Lo, Lo, Hi); 7282 break; 7283 } 7284 case ISD::FCOPYSIGN: { 7285 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 7286 if (getTypeAction(NVT) == Expand) 7287 ExpandOp(Lo, Lo, Hi); 7288 break; 7289 } 7290 case ISD::SINT_TO_FP: 7291 case ISD::UINT_TO_FP: { 7292 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 7293 MVT SrcVT = Node->getOperand(0).getValueType(); 7294 7295 // Promote the operand if needed. Do this before checking for 7296 // ppcf128 so conversions of i16 and i8 work. 7297 if (getTypeAction(SrcVT) == Promote) { 7298 SDValue Tmp = PromoteOp(Node->getOperand(0)); 7299 Tmp = isSigned 7300 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 7301 DAG.getValueType(SrcVT)) 7302 : DAG.getZeroExtendInReg(Tmp, SrcVT); 7303 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode(); 7304 SrcVT = Node->getOperand(0).getValueType(); 7305 } 7306 7307 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 7308 static const uint64_t zero = 0; 7309 if (isSigned) { 7310 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 7311 Node->getOperand(0))); 7312 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 7313 } else { 7314 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 7315 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 7316 Node->getOperand(0))); 7317 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 7318 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 7319 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 7320 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 7321 DAG.getConstant(0, MVT::i32), 7322 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 7323 DAG.getConstantFP( 7324 APFloat(APInt(128, 2, TwoE32)), 7325 MVT::ppcf128)), 7326 Hi, 7327 DAG.getCondCode(ISD::SETLT)), 7328 Lo, Hi); 7329 } 7330 break; 7331 } 7332 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 7333 // si64->ppcf128 done by libcall, below 7334 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 7335 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 7336 Lo, Hi); 7337 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 7338 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 7339 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 7340 DAG.getConstant(0, MVT::i64), 7341 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 7342 DAG.getConstantFP( 7343 APFloat(APInt(128, 2, TwoE64)), 7344 MVT::ppcf128)), 7345 Hi, 7346 DAG.getCondCode(ISD::SETLT)), 7347 Lo, Hi); 7348 break; 7349 } 7350 7351 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 7352 Node->getOperand(0)); 7353 if (getTypeAction(Lo.getValueType()) == Expand) 7354 // float to i32 etc. can be 'expanded' to a single node. 7355 ExpandOp(Lo, Lo, Hi); 7356 break; 7357 } 7358 } 7359 7360 // Make sure the resultant values have been legalized themselves, unless this 7361 // is a type that requires multi-step expansion. 7362 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 7363 Lo = LegalizeOp(Lo); 7364 if (Hi.getNode()) 7365 // Don't legalize the high part if it is expanded to a single node. 7366 Hi = LegalizeOp(Hi); 7367 } 7368 7369 // Remember in a map if the values will be reused later. 7370 bool isNew = 7371 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7372 assert(isNew && "Value already expanded?!?"); 7373 isNew = isNew; 7374} 7375 7376/// SplitVectorOp - Given an operand of vector type, break it down into 7377/// two smaller values, still of vector type. 7378void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo, 7379 SDValue &Hi) { 7380 assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); 7381 SDNode *Node = Op.getNode(); 7382 unsigned NumElements = Op.getValueType().getVectorNumElements(); 7383 assert(NumElements > 1 && "Cannot split a single element vector!"); 7384 7385 MVT NewEltVT = Op.getValueType().getVectorElementType(); 7386 7387 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 7388 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 7389 7390 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); 7391 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); 7392 7393 // See if we already split it. 7394 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I 7395 = SplitNodes.find(Op); 7396 if (I != SplitNodes.end()) { 7397 Lo = I->second.first; 7398 Hi = I->second.second; 7399 return; 7400 } 7401 7402 switch (Node->getOpcode()) { 7403 default: 7404#ifndef NDEBUG 7405 Node->dump(&DAG); 7406#endif 7407 assert(0 && "Unhandled operation in SplitVectorOp!"); 7408 case ISD::UNDEF: 7409 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 7410 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 7411 break; 7412 case ISD::BUILD_PAIR: 7413 Lo = Node->getOperand(0); 7414 Hi = Node->getOperand(1); 7415 break; 7416 case ISD::INSERT_VECTOR_ELT: { 7417 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 7418 SplitVectorOp(Node->getOperand(0), Lo, Hi); 7419 unsigned Index = Idx->getZExtValue(); 7420 SDValue ScalarOp = Node->getOperand(1); 7421 if (Index < NewNumElts_Lo) 7422 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 7423 DAG.getIntPtrConstant(Index)); 7424 else 7425 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 7426 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 7427 break; 7428 } 7429 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), 7430 Node->getOperand(1), 7431 Node->getOperand(2)); 7432 SplitVectorOp(Tmp, Lo, Hi); 7433 break; 7434 } 7435 case ISD::VECTOR_SHUFFLE: { 7436 // Build the low part. 7437 SDValue Mask = Node->getOperand(2); 7438 SmallVector<SDValue, 8> Ops; 7439 MVT PtrVT = TLI.getPointerTy(); 7440 7441 // Insert all of the elements from the input that are needed. We use 7442 // buildvector of extractelement here because the input vectors will have 7443 // to be legalized, so this makes the code simpler. 7444 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 7445 SDValue IdxNode = Mask.getOperand(i); 7446 if (IdxNode.getOpcode() == ISD::UNDEF) { 7447 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 7448 continue; 7449 } 7450 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue(); 7451 SDValue InVec = Node->getOperand(0); 7452 if (Idx >= NumElements) { 7453 InVec = Node->getOperand(1); 7454 Idx -= NumElements; 7455 } 7456 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 7457 DAG.getConstant(Idx, PtrVT))); 7458 } 7459 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 7460 Ops.clear(); 7461 7462 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 7463 SDValue IdxNode = Mask.getOperand(i); 7464 if (IdxNode.getOpcode() == ISD::UNDEF) { 7465 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 7466 continue; 7467 } 7468 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue(); 7469 SDValue InVec = Node->getOperand(0); 7470 if (Idx >= NumElements) { 7471 InVec = Node->getOperand(1); 7472 Idx -= NumElements; 7473 } 7474 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 7475 DAG.getConstant(Idx, PtrVT))); 7476 } 7477 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size()); 7478 break; 7479 } 7480 case ISD::BUILD_VECTOR: { 7481 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 7482 Node->op_begin()+NewNumElts_Lo); 7483 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 7484 7485 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 7486 Node->op_end()); 7487 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 7488 break; 7489 } 7490 case ISD::CONCAT_VECTORS: { 7491 // FIXME: Handle non-power-of-two vectors? 7492 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 7493 if (NewNumSubvectors == 1) { 7494 Lo = Node->getOperand(0); 7495 Hi = Node->getOperand(1); 7496 } else { 7497 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 7498 Node->op_begin()+NewNumSubvectors); 7499 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 7500 7501 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors, 7502 Node->op_end()); 7503 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 7504 } 7505 break; 7506 } 7507 case ISD::EXTRACT_SUBVECTOR: { 7508 SDValue Vec = Op.getOperand(0); 7509 SDValue Idx = Op.getOperand(1); 7510 MVT IdxVT = Idx.getValueType(); 7511 7512 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Lo, Vec, Idx); 7513 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx); 7514 if (CIdx) { 7515 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, 7516 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo, 7517 IdxVT)); 7518 } else { 7519 Idx = DAG.getNode(ISD::ADD, IdxVT, Idx, 7520 DAG.getConstant(NewNumElts_Lo, IdxVT)); 7521 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, Idx); 7522 } 7523 break; 7524 } 7525 case ISD::SELECT: { 7526 SDValue Cond = Node->getOperand(0); 7527 7528 SDValue LL, LH, RL, RH; 7529 SplitVectorOp(Node->getOperand(1), LL, LH); 7530 SplitVectorOp(Node->getOperand(2), RL, RH); 7531 7532 if (Cond.getValueType().isVector()) { 7533 // Handle a vector merge. 7534 SDValue CL, CH; 7535 SplitVectorOp(Cond, CL, CH); 7536 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 7537 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 7538 } else { 7539 // Handle a simple select with vector operands. 7540 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 7541 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 7542 } 7543 break; 7544 } 7545 case ISD::SELECT_CC: { 7546 SDValue CondLHS = Node->getOperand(0); 7547 SDValue CondRHS = Node->getOperand(1); 7548 SDValue CondCode = Node->getOperand(4); 7549 7550 SDValue LL, LH, RL, RH; 7551 SplitVectorOp(Node->getOperand(2), LL, LH); 7552 SplitVectorOp(Node->getOperand(3), RL, RH); 7553 7554 // Handle a simple select with vector operands. 7555 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS, 7556 LL, RL, CondCode); 7557 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS, 7558 LH, RH, CondCode); 7559 break; 7560 } 7561 case ISD::VSETCC: { 7562 SDValue LL, LH, RL, RH; 7563 SplitVectorOp(Node->getOperand(0), LL, LH); 7564 SplitVectorOp(Node->getOperand(1), RL, RH); 7565 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2)); 7566 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2)); 7567 break; 7568 } 7569 case ISD::ADD: 7570 case ISD::SUB: 7571 case ISD::MUL: 7572 case ISD::FADD: 7573 case ISD::FSUB: 7574 case ISD::FMUL: 7575 case ISD::SDIV: 7576 case ISD::UDIV: 7577 case ISD::FDIV: 7578 case ISD::FPOW: 7579 case ISD::AND: 7580 case ISD::OR: 7581 case ISD::XOR: 7582 case ISD::UREM: 7583 case ISD::SREM: 7584 case ISD::FREM: 7585 case ISD::SHL: 7586 case ISD::SRA: 7587 case ISD::SRL: { 7588 SDValue LL, LH, RL, RH; 7589 SplitVectorOp(Node->getOperand(0), LL, LH); 7590 SplitVectorOp(Node->getOperand(1), RL, RH); 7591 7592 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 7593 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 7594 break; 7595 } 7596 case ISD::FP_ROUND: 7597 case ISD::FPOWI: { 7598 SDValue L, H; 7599 SplitVectorOp(Node->getOperand(0), L, H); 7600 7601 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 7602 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 7603 break; 7604 } 7605 case ISD::CTTZ: 7606 case ISD::CTLZ: 7607 case ISD::CTPOP: 7608 case ISD::FNEG: 7609 case ISD::FABS: 7610 case ISD::FSQRT: 7611 case ISD::FSIN: 7612 case ISD::FCOS: 7613 case ISD::FLOG: 7614 case ISD::FLOG2: 7615 case ISD::FLOG10: 7616 case ISD::FEXP: 7617 case ISD::FEXP2: 7618 case ISD::FP_TO_SINT: 7619 case ISD::FP_TO_UINT: 7620 case ISD::SINT_TO_FP: 7621 case ISD::UINT_TO_FP: 7622 case ISD::TRUNCATE: 7623 case ISD::ANY_EXTEND: 7624 case ISD::SIGN_EXTEND: 7625 case ISD::ZERO_EXTEND: 7626 case ISD::FP_EXTEND: { 7627 SDValue L, H; 7628 SplitVectorOp(Node->getOperand(0), L, H); 7629 7630 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 7631 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 7632 break; 7633 } 7634 case ISD::CONVERT_RNDSAT: { 7635 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 7636 SDValue L, H; 7637 SplitVectorOp(Node->getOperand(0), L, H); 7638 SDValue DTyOpL = DAG.getValueType(NewVT_Lo); 7639 SDValue DTyOpH = DAG.getValueType(NewVT_Hi); 7640 SDValue STyOpL = DAG.getValueType(L.getValueType()); 7641 SDValue STyOpH = DAG.getValueType(H.getValueType()); 7642 7643 SDValue RndOp = Node->getOperand(3); 7644 SDValue SatOp = Node->getOperand(4); 7645 7646 Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL, 7647 RndOp, SatOp, CvtCode); 7648 Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH, 7649 RndOp, SatOp, CvtCode); 7650 break; 7651 } 7652 case ISD::LOAD: { 7653 LoadSDNode *LD = cast<LoadSDNode>(Node); 7654 SDValue Ch = LD->getChain(); 7655 SDValue Ptr = LD->getBasePtr(); 7656 ISD::LoadExtType ExtType = LD->getExtensionType(); 7657 const Value *SV = LD->getSrcValue(); 7658 int SVOffset = LD->getSrcValueOffset(); 7659 MVT MemoryVT = LD->getMemoryVT(); 7660 unsigned Alignment = LD->getAlignment(); 7661 bool isVolatile = LD->isVolatile(); 7662 7663 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 7664 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); 7665 7666 MVT MemNewEltVT = MemoryVT.getVectorElementType(); 7667 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo); 7668 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi); 7669 7670 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, 7671 NewVT_Lo, Ch, Ptr, Offset, 7672 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment); 7673 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8; 7674 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 7675 DAG.getIntPtrConstant(IncrementSize)); 7676 SVOffset += IncrementSize; 7677 Alignment = MinAlign(Alignment, IncrementSize); 7678 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, 7679 NewVT_Hi, Ch, Ptr, Offset, 7680 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment); 7681 7682 // Build a factor node to remember that this load is independent of the 7683 // other one. 7684 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 7685 Hi.getValue(1)); 7686 7687 // Remember that we legalized the chain. 7688 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 7689 break; 7690 } 7691 case ISD::BIT_CONVERT: { 7692 // We know the result is a vector. The input may be either a vector or a 7693 // scalar value. 7694 SDValue InOp = Node->getOperand(0); 7695 if (!InOp.getValueType().isVector() || 7696 InOp.getValueType().getVectorNumElements() == 1) { 7697 // The input is a scalar or single-element vector. 7698 // Lower to a store/load so that it can be split. 7699 // FIXME: this could be improved probably. 7700 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment( 7701 Op.getValueType().getTypeForMVT()); 7702 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign); 7703 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex(); 7704 7705 SDValue St = DAG.getStore(DAG.getEntryNode(), 7706 InOp, Ptr, 7707 PseudoSourceValue::getFixedStack(FI), 0); 7708 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, 7709 PseudoSourceValue::getFixedStack(FI), 0); 7710 } 7711 // Split the vector and convert each of the pieces now. 7712 SplitVectorOp(InOp, Lo, Hi); 7713 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 7714 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 7715 break; 7716 } 7717 } 7718 7719 // Remember in a map if the values will be reused later. 7720 bool isNew = 7721 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7722 assert(isNew && "Value already split?!?"); 7723 isNew = isNew; 7724} 7725 7726 7727/// ScalarizeVectorOp - Given an operand of single-element vector type 7728/// (e.g. v1f32), convert it into the equivalent operation that returns a 7729/// scalar (e.g. f32) value. 7730SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) { 7731 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); 7732 SDNode *Node = Op.getNode(); 7733 MVT NewVT = Op.getValueType().getVectorElementType(); 7734 assert(Op.getValueType().getVectorNumElements() == 1); 7735 7736 // See if we already scalarized it. 7737 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op); 7738 if (I != ScalarizedNodes.end()) return I->second; 7739 7740 SDValue Result; 7741 switch (Node->getOpcode()) { 7742 default: 7743#ifndef NDEBUG 7744 Node->dump(&DAG); cerr << "\n"; 7745#endif 7746 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 7747 case ISD::ADD: 7748 case ISD::FADD: 7749 case ISD::SUB: 7750 case ISD::FSUB: 7751 case ISD::MUL: 7752 case ISD::FMUL: 7753 case ISD::SDIV: 7754 case ISD::UDIV: 7755 case ISD::FDIV: 7756 case ISD::SREM: 7757 case ISD::UREM: 7758 case ISD::FREM: 7759 case ISD::FPOW: 7760 case ISD::AND: 7761 case ISD::OR: 7762 case ISD::XOR: 7763 Result = DAG.getNode(Node->getOpcode(), 7764 NewVT, 7765 ScalarizeVectorOp(Node->getOperand(0)), 7766 ScalarizeVectorOp(Node->getOperand(1))); 7767 break; 7768 case ISD::FNEG: 7769 case ISD::FABS: 7770 case ISD::FSQRT: 7771 case ISD::FSIN: 7772 case ISD::FCOS: 7773 case ISD::FLOG: 7774 case ISD::FLOG2: 7775 case ISD::FLOG10: 7776 case ISD::FEXP: 7777 case ISD::FEXP2: 7778 case ISD::FP_TO_SINT: 7779 case ISD::FP_TO_UINT: 7780 case ISD::SINT_TO_FP: 7781 case ISD::UINT_TO_FP: 7782 case ISD::SIGN_EXTEND: 7783 case ISD::ZERO_EXTEND: 7784 case ISD::ANY_EXTEND: 7785 case ISD::TRUNCATE: 7786 case ISD::FP_EXTEND: 7787 Result = DAG.getNode(Node->getOpcode(), 7788 NewVT, 7789 ScalarizeVectorOp(Node->getOperand(0))); 7790 break; 7791 case ISD::CONVERT_RNDSAT: { 7792 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0)); 7793 Result = DAG.getConvertRndSat(NewVT, Op0, 7794 DAG.getValueType(NewVT), 7795 DAG.getValueType(Op0.getValueType()), 7796 Node->getOperand(3), 7797 Node->getOperand(4), 7798 cast<CvtRndSatSDNode>(Node)->getCvtCode()); 7799 break; 7800 } 7801 case ISD::FPOWI: 7802 case ISD::FP_ROUND: 7803 Result = DAG.getNode(Node->getOpcode(), 7804 NewVT, 7805 ScalarizeVectorOp(Node->getOperand(0)), 7806 Node->getOperand(1)); 7807 break; 7808 case ISD::LOAD: { 7809 LoadSDNode *LD = cast<LoadSDNode>(Node); 7810 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 7811 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 7812 ISD::LoadExtType ExtType = LD->getExtensionType(); 7813 const Value *SV = LD->getSrcValue(); 7814 int SVOffset = LD->getSrcValueOffset(); 7815 MVT MemoryVT = LD->getMemoryVT(); 7816 unsigned Alignment = LD->getAlignment(); 7817 bool isVolatile = LD->isVolatile(); 7818 7819 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 7820 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); 7821 7822 Result = DAG.getLoad(ISD::UNINDEXED, ExtType, 7823 NewVT, Ch, Ptr, Offset, SV, SVOffset, 7824 MemoryVT.getVectorElementType(), 7825 isVolatile, Alignment); 7826 7827 // Remember that we legalized the chain. 7828 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 7829 break; 7830 } 7831 case ISD::BUILD_VECTOR: 7832 Result = Node->getOperand(0); 7833 break; 7834 case ISD::INSERT_VECTOR_ELT: 7835 // Returning the inserted scalar element. 7836 Result = Node->getOperand(1); 7837 break; 7838 case ISD::CONCAT_VECTORS: 7839 assert(Node->getOperand(0).getValueType() == NewVT && 7840 "Concat of non-legal vectors not yet supported!"); 7841 Result = Node->getOperand(0); 7842 break; 7843 case ISD::VECTOR_SHUFFLE: { 7844 // Figure out if the scalar is the LHS or RHS and return it. 7845 SDValue EltNum = Node->getOperand(2).getOperand(0); 7846 if (cast<ConstantSDNode>(EltNum)->getZExtValue()) 7847 Result = ScalarizeVectorOp(Node->getOperand(1)); 7848 else 7849 Result = ScalarizeVectorOp(Node->getOperand(0)); 7850 break; 7851 } 7852 case ISD::EXTRACT_SUBVECTOR: 7853 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, Node->getOperand(0), 7854 Node->getOperand(1)); 7855 break; 7856 case ISD::BIT_CONVERT: { 7857 SDValue Op0 = Op.getOperand(0); 7858 if (Op0.getValueType().getVectorNumElements() == 1) 7859 Op0 = ScalarizeVectorOp(Op0); 7860 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0); 7861 break; 7862 } 7863 case ISD::SELECT: 7864 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 7865 ScalarizeVectorOp(Op.getOperand(1)), 7866 ScalarizeVectorOp(Op.getOperand(2))); 7867 break; 7868 case ISD::SELECT_CC: 7869 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0), 7870 Node->getOperand(1), 7871 ScalarizeVectorOp(Op.getOperand(2)), 7872 ScalarizeVectorOp(Op.getOperand(3)), 7873 Node->getOperand(4)); 7874 break; 7875 case ISD::VSETCC: { 7876 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0)); 7877 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1)); 7878 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1, 7879 Op.getOperand(2)); 7880 Result = DAG.getNode(ISD::SELECT, NewVT, Result, 7881 DAG.getConstant(-1ULL, NewVT), 7882 DAG.getConstant(0ULL, NewVT)); 7883 break; 7884 } 7885 } 7886 7887 if (TLI.isTypeLegal(NewVT)) 7888 Result = LegalizeOp(Result); 7889 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7890 assert(isNew && "Value already scalarized?"); 7891 isNew = isNew; 7892 return Result; 7893} 7894 7895 7896SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) { 7897 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op); 7898 if (I != WidenNodes.end()) return I->second; 7899 7900 MVT VT = Op.getValueType(); 7901 assert(VT.isVector() && "Cannot widen non-vector type!"); 7902 7903 SDValue Result; 7904 SDNode *Node = Op.getNode(); 7905 MVT EVT = VT.getVectorElementType(); 7906 7907 unsigned NumElts = VT.getVectorNumElements(); 7908 unsigned NewNumElts = WidenVT.getVectorNumElements(); 7909 assert(NewNumElts > NumElts && "Cannot widen to smaller type!"); 7910 assert(NewNumElts < 17); 7911 7912 // When widen is called, it is assumed that it is more efficient to use a 7913 // wide type. The default action is to widen to operation to a wider legal 7914 // vector type and then do the operation if it is legal by calling LegalizeOp 7915 // again. If there is no vector equivalent, we will unroll the operation, do 7916 // it, and rebuild the vector. If most of the operations are vectorizible to 7917 // the legal type, the resulting code will be more efficient. If this is not 7918 // the case, the resulting code will preform badly as we end up generating 7919 // code to pack/unpack the results. It is the function that calls widen 7920 // that is responsible for seeing this doesn't happen. 7921 switch (Node->getOpcode()) { 7922 default: 7923#ifndef NDEBUG 7924 Node->dump(&DAG); 7925#endif 7926 assert(0 && "Unexpected operation in WidenVectorOp!"); 7927 break; 7928 case ISD::CopyFromReg: 7929 assert(0 && "CopyFromReg doesn't need widening!"); 7930 case ISD::Constant: 7931 case ISD::ConstantFP: 7932 // To build a vector of these elements, clients should call BuildVector 7933 // and with each element instead of creating a node with a vector type 7934 assert(0 && "Unexpected operation in WidenVectorOp!"); 7935 case ISD::VAARG: 7936 // Variable Arguments with vector types doesn't make any sense to me 7937 assert(0 && "Unexpected operation in WidenVectorOp!"); 7938 break; 7939 case ISD::UNDEF: 7940 Result = DAG.getNode(ISD::UNDEF, WidenVT); 7941 break; 7942 case ISD::BUILD_VECTOR: { 7943 // Build a vector with undefined for the new nodes 7944 SDValueVector NewOps(Node->op_begin(), Node->op_end()); 7945 for (unsigned i = NumElts; i < NewNumElts; ++i) { 7946 NewOps.push_back(DAG.getNode(ISD::UNDEF,EVT)); 7947 } 7948 Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size()); 7949 break; 7950 } 7951 case ISD::INSERT_VECTOR_ELT: { 7952 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 7953 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, WidenVT, Tmp1, 7954 Node->getOperand(1), Node->getOperand(2)); 7955 break; 7956 } 7957 case ISD::VECTOR_SHUFFLE: { 7958 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 7959 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT); 7960 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is 7961 // used as permutation array. We build the vector here instead of widening 7962 // because we don't want to legalize and have it turned to something else. 7963 SDValue PermOp = Node->getOperand(2); 7964 SDValueVector NewOps; 7965 MVT PVT = PermOp.getValueType().getVectorElementType(); 7966 for (unsigned i = 0; i < NumElts; ++i) { 7967 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) { 7968 NewOps.push_back(PermOp.getOperand(i)); 7969 } else { 7970 unsigned Idx = 7971 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue(); 7972 if (Idx < NumElts) { 7973 NewOps.push_back(PermOp.getOperand(i)); 7974 } 7975 else { 7976 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts, 7977 PermOp.getOperand(i).getValueType())); 7978 } 7979 } 7980 } 7981 for (unsigned i = NumElts; i < NewNumElts; ++i) { 7982 NewOps.push_back(DAG.getNode(ISD::UNDEF,PVT)); 7983 } 7984 7985 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, 7986 MVT::getVectorVT(PVT, NewOps.size()), 7987 &NewOps[0], NewOps.size()); 7988 7989 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, Tmp1, Tmp2, Tmp3); 7990 break; 7991 } 7992 case ISD::LOAD: { 7993 // If the load widen returns true, we can use a single load for the 7994 // vector. Otherwise, it is returning a token factor for multiple 7995 // loads. 7996 SDValue TFOp; 7997 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT)) 7998 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1))); 7999 else 8000 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0))); 8001 break; 8002 } 8003 8004 case ISD::BIT_CONVERT: { 8005 SDValue Tmp1 = Node->getOperand(0); 8006 // Converts between two different types so we need to determine 8007 // the correct widen type for the input operand. 8008 MVT InVT = Tmp1.getValueType(); 8009 unsigned WidenSize = WidenVT.getSizeInBits(); 8010 if (InVT.isVector()) { 8011 MVT InEltVT = InVT.getVectorElementType(); 8012 unsigned InEltSize = InEltVT.getSizeInBits(); 8013 assert(WidenSize % InEltSize == 0 && 8014 "can not widen bit convert that are not multiple of element type"); 8015 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize); 8016 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT); 8017 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits()); 8018 Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Tmp1); 8019 } else { 8020 // If the result size is a multiple of the input size, widen the input 8021 // and then convert. 8022 unsigned InSize = InVT.getSizeInBits(); 8023 assert(WidenSize % InSize == 0 && 8024 "can not widen bit convert that are not multiple of element type"); 8025 unsigned NewNumElts = WidenSize / InSize; 8026 SmallVector<SDValue, 16> Ops(NewNumElts); 8027 SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT); 8028 Ops[0] = Tmp1; 8029 for (unsigned i = 1; i < NewNumElts; ++i) 8030 Ops[i] = UndefVal; 8031 8032 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts); 8033 Result = DAG.getNode(ISD::BUILD_VECTOR, NewInVT, &Ops[0], NewNumElts); 8034 Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Result); 8035 } 8036 break; 8037 } 8038 8039 case ISD::SINT_TO_FP: 8040 case ISD::UINT_TO_FP: 8041 case ISD::FP_TO_SINT: 8042 case ISD::FP_TO_UINT: 8043 case ISD::FP_ROUND: { 8044 SDValue Tmp1 = Node->getOperand(0); 8045 // Converts between two different types so we need to determine 8046 // the correct widen type for the input operand. 8047 MVT TVT = Tmp1.getValueType(); 8048 assert(TVT.isVector() && "can not widen non vector type"); 8049 MVT TEVT = TVT.getVectorElementType(); 8050 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts); 8051 Tmp1 = WidenVectorOp(Tmp1, TWidenVT); 8052 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts); 8053 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1); 8054 break; 8055 } 8056 8057 case ISD::FP_EXTEND: 8058 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 8059 case ISD::TRUNCATE: 8060 case ISD::SIGN_EXTEND: 8061 case ISD::ZERO_EXTEND: 8062 case ISD::ANY_EXTEND: 8063 case ISD::SIGN_EXTEND_INREG: 8064 case ISD::FABS: 8065 case ISD::FNEG: 8066 case ISD::FSQRT: 8067 case ISD::FSIN: 8068 case ISD::FCOS: 8069 case ISD::CTPOP: 8070 case ISD::CTTZ: 8071 case ISD::CTLZ: { 8072 // Unary op widening 8073 SDValue Tmp1; 8074 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8075 assert(Tmp1.getValueType() == WidenVT); 8076 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1); 8077 break; 8078 } 8079 case ISD::CONVERT_RNDSAT: { 8080 SDValue RndOp = Node->getOperand(3); 8081 SDValue SatOp = Node->getOperand(4); 8082 SDValue SrcOp = Node->getOperand(0); 8083 8084 // Converts between two different types so we need to determine 8085 // the correct widen type for the input operand. 8086 MVT SVT = SrcOp.getValueType(); 8087 assert(SVT.isVector() && "can not widen non vector type"); 8088 MVT SEVT = SVT.getVectorElementType(); 8089 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts); 8090 8091 SrcOp = WidenVectorOp(SrcOp, SWidenVT); 8092 assert(SrcOp.getValueType() == WidenVT); 8093 SDValue DTyOp = DAG.getValueType(WidenVT); 8094 SDValue STyOp = DAG.getValueType(SrcOp.getValueType()); 8095 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 8096 8097 Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp, 8098 RndOp, SatOp, CvtCode); 8099 break; 8100 } 8101 case ISD::FPOW: 8102 case ISD::FPOWI: 8103 case ISD::ADD: 8104 case ISD::SUB: 8105 case ISD::MUL: 8106 case ISD::MULHS: 8107 case ISD::MULHU: 8108 case ISD::AND: 8109 case ISD::OR: 8110 case ISD::XOR: 8111 case ISD::FADD: 8112 case ISD::FSUB: 8113 case ISD::FMUL: 8114 case ISD::SDIV: 8115 case ISD::SREM: 8116 case ISD::FDIV: 8117 case ISD::FREM: 8118 case ISD::FCOPYSIGN: 8119 case ISD::UDIV: 8120 case ISD::UREM: 8121 case ISD::BSWAP: { 8122 // Binary op widening 8123 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8124 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT); 8125 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT); 8126 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2); 8127 break; 8128 } 8129 8130 case ISD::SHL: 8131 case ISD::SRA: 8132 case ISD::SRL: { 8133 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8134 assert(Tmp1.getValueType() == WidenVT); 8135 SDValue ShOp = Node->getOperand(1); 8136 MVT ShVT = ShOp.getValueType(); 8137 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(), 8138 WidenVT.getVectorNumElements()); 8139 ShOp = WidenVectorOp(ShOp, NewShVT); 8140 assert(ShOp.getValueType() == NewShVT); 8141 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, ShOp); 8142 break; 8143 } 8144 8145 case ISD::EXTRACT_VECTOR_ELT: { 8146 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8147 assert(Tmp1.getValueType() == WidenVT); 8148 Result = DAG.getNode(Node->getOpcode(), EVT, Tmp1, Node->getOperand(1)); 8149 break; 8150 } 8151 case ISD::CONCAT_VECTORS: { 8152 // We concurrently support only widen on a multiple of the incoming vector. 8153 // We could widen on a multiple of the incoming operand if necessary. 8154 unsigned NumConcat = NewNumElts / NumElts; 8155 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector"); 8156 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT); 8157 SmallVector<SDValue, 8> MOps; 8158 MOps.push_back(Op); 8159 for (unsigned i = 1; i != NumConcat; ++i) { 8160 MOps.push_back(UndefVal); 8161 } 8162 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT, 8163 &MOps[0], MOps.size())); 8164 break; 8165 } 8166 case ISD::EXTRACT_SUBVECTOR: { 8167 SDValue Tmp1 = Node->getOperand(0); 8168 SDValue Idx = Node->getOperand(1); 8169 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx); 8170 if (CIdx && CIdx->getZExtValue() == 0) { 8171 // Since we are access the start of the vector, the incoming 8172 // vector type might be the proper. 8173 MVT Tmp1VT = Tmp1.getValueType(); 8174 if (Tmp1VT == WidenVT) 8175 return Tmp1; 8176 else { 8177 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements(); 8178 if (Tmp1VTNumElts < NewNumElts) 8179 Result = WidenVectorOp(Tmp1, WidenVT); 8180 else 8181 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, WidenVT, Tmp1, Idx); 8182 } 8183 } else if (NewNumElts % NumElts == 0) { 8184 // Widen the extracted subvector. 8185 unsigned NumConcat = NewNumElts / NumElts; 8186 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT); 8187 SmallVector<SDValue, 8> MOps; 8188 MOps.push_back(Op); 8189 for (unsigned i = 1; i != NumConcat; ++i) { 8190 MOps.push_back(UndefVal); 8191 } 8192 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT, 8193 &MOps[0], MOps.size())); 8194 } else { 8195 assert(0 && "can not widen extract subvector"); 8196 // This could be implemented using insert and build vector but I would 8197 // like to see when this happens. 8198 } 8199 break; 8200 } 8201 8202 case ISD::SELECT: { 8203 // Determine new condition widen type and widen 8204 SDValue Cond1 = Node->getOperand(0); 8205 MVT CondVT = Cond1.getValueType(); 8206 assert(CondVT.isVector() && "can not widen non vector type"); 8207 MVT CondEVT = CondVT.getVectorElementType(); 8208 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts); 8209 Cond1 = WidenVectorOp(Cond1, CondWidenVT); 8210 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen"); 8211 8212 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT); 8213 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT); 8214 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT); 8215 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Tmp1, Tmp2); 8216 break; 8217 } 8218 8219 case ISD::SELECT_CC: { 8220 // Determine new condition widen type and widen 8221 SDValue Cond1 = Node->getOperand(0); 8222 SDValue Cond2 = Node->getOperand(1); 8223 MVT CondVT = Cond1.getValueType(); 8224 assert(CondVT.isVector() && "can not widen non vector type"); 8225 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs"); 8226 MVT CondEVT = CondVT.getVectorElementType(); 8227 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts); 8228 Cond1 = WidenVectorOp(Cond1, CondWidenVT); 8229 Cond2 = WidenVectorOp(Cond2, CondWidenVT); 8230 assert(Cond1.getValueType() == CondWidenVT && 8231 Cond2.getValueType() == CondWidenVT && "condition not widen"); 8232 8233 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT); 8234 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT); 8235 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT && 8236 "operands not widen"); 8237 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Cond2, Tmp1, 8238 Tmp2, Node->getOperand(4)); 8239 break; 8240 } 8241 case ISD::VSETCC: { 8242 // Determine widen for the operand 8243 SDValue Tmp1 = Node->getOperand(0); 8244 MVT TmpVT = Tmp1.getValueType(); 8245 assert(TmpVT.isVector() && "can not widen non vector type"); 8246 MVT TmpEVT = TmpVT.getVectorElementType(); 8247 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts); 8248 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT); 8249 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT); 8250 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2, 8251 Node->getOperand(2)); 8252 break; 8253 } 8254 case ISD::ATOMIC_CMP_SWAP: 8255 case ISD::ATOMIC_LOAD_ADD: 8256 case ISD::ATOMIC_LOAD_SUB: 8257 case ISD::ATOMIC_LOAD_AND: 8258 case ISD::ATOMIC_LOAD_OR: 8259 case ISD::ATOMIC_LOAD_XOR: 8260 case ISD::ATOMIC_LOAD_NAND: 8261 case ISD::ATOMIC_LOAD_MIN: 8262 case ISD::ATOMIC_LOAD_MAX: 8263 case ISD::ATOMIC_LOAD_UMIN: 8264 case ISD::ATOMIC_LOAD_UMAX: 8265 case ISD::ATOMIC_SWAP: { 8266 // For now, we assume that using vectors for these operations don't make 8267 // much sense so we just split it. We return an empty result 8268 SDValue X, Y; 8269 SplitVectorOp(Op, X, Y); 8270 return Result; 8271 break; 8272 } 8273 8274 } // end switch (Node->getOpcode()) 8275 8276 assert(Result.getNode() && "Didn't set a result!"); 8277 if (Result != Op) 8278 Result = LegalizeOp(Result); 8279 8280 AddWidenedOperand(Op, Result); 8281 return Result; 8282} 8283 8284// Utility function to find a legal vector type and its associated element 8285// type from a preferred width and whose vector type must be the same size 8286// as the VVT. 8287// TLI: Target lowering used to determine legal types 8288// Width: Preferred width of element type 8289// VVT: Vector value type whose size we must match. 8290// Returns VecEVT and EVT - the vector type and its associated element type 8291static void FindWidenVecType(TargetLowering &TLI, unsigned Width, MVT VVT, 8292 MVT& EVT, MVT& VecEVT) { 8293 // We start with the preferred width, make it a power of 2 and see if 8294 // we can find a vector type of that width. If not, we reduce it by 8295 // another power of 2. If we have widen the type, a vector of bytes should 8296 // always be legal. 8297 assert(TLI.isTypeLegal(VVT)); 8298 unsigned EWidth = Width + 1; 8299 do { 8300 assert(EWidth > 0); 8301 EWidth = (1 << Log2_32(EWidth-1)); 8302 EVT = MVT::getIntegerVT(EWidth); 8303 unsigned NumEVT = VVT.getSizeInBits()/EWidth; 8304 VecEVT = MVT::getVectorVT(EVT, NumEVT); 8305 } while (!TLI.isTypeLegal(VecEVT) || 8306 VVT.getSizeInBits() != VecEVT.getSizeInBits()); 8307} 8308 8309SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain, 8310 SDValue Chain, 8311 SDValue BasePtr, 8312 const Value *SV, 8313 int SVOffset, 8314 unsigned Alignment, 8315 bool isVolatile, 8316 unsigned LdWidth, 8317 MVT ResType) { 8318 // We assume that we have good rules to handle loading power of two loads so 8319 // we break down the operations to power of 2 loads. The strategy is to 8320 // load the largest power of 2 that we can easily transform to a legal vector 8321 // and then insert into that vector, and the cast the result into the legal 8322 // vector that we want. This avoids unnecessary stack converts. 8323 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and 8324 // the load is nonvolatile, we an use a wider load for the value. 8325 // Find a vector length we can load a large chunk 8326 MVT EVT, VecEVT; 8327 unsigned EVTWidth; 8328 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT); 8329 EVTWidth = EVT.getSizeInBits(); 8330 8331 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, SVOffset, 8332 isVolatile, Alignment); 8333 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecEVT, LdOp); 8334 LdChain.push_back(LdOp.getValue(1)); 8335 8336 // Check if we can load the element with one instruction 8337 if (LdWidth == EVTWidth) { 8338 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp); 8339 } 8340 8341 // The vector element order is endianness dependent. 8342 unsigned Idx = 1; 8343 LdWidth -= EVTWidth; 8344 unsigned Offset = 0; 8345 8346 while (LdWidth > 0) { 8347 unsigned Increment = EVTWidth / 8; 8348 Offset += Increment; 8349 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr, 8350 DAG.getIntPtrConstant(Increment)); 8351 8352 if (LdWidth < EVTWidth) { 8353 // Our current type we are using is too large, use a smaller size by 8354 // using a smaller power of 2 8355 unsigned oEVTWidth = EVTWidth; 8356 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT); 8357 EVTWidth = EVT.getSizeInBits(); 8358 // Readjust position and vector position based on new load type 8359 Idx = Idx * (oEVTWidth/EVTWidth); 8360 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp); 8361 } 8362 8363 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, 8364 SVOffset+Offset, isVolatile, 8365 MinAlign(Alignment, Offset)); 8366 LdChain.push_back(LdOp.getValue(1)); 8367 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, VecEVT, VecOp, LdOp, 8368 DAG.getIntPtrConstant(Idx++)); 8369 8370 LdWidth -= EVTWidth; 8371 } 8372 8373 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp); 8374} 8375 8376bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result, 8377 SDValue& TFOp, 8378 SDValue Op, 8379 MVT NVT) { 8380 // TODO: Add support for ConcatVec and the ability to load many vector 8381 // types (e.g., v4i8). This will not work when a vector register 8382 // to memory mapping is strange (e.g., vector elements are not 8383 // stored in some sequential order). 8384 8385 // It must be true that the widen vector type is bigger than where 8386 // we need to load from. 8387 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); 8388 MVT LdVT = LD->getMemoryVT(); 8389 assert(LdVT.isVector() && NVT.isVector()); 8390 assert(LdVT.getVectorElementType() == NVT.getVectorElementType()); 8391 8392 // Load information 8393 SDValue Chain = LD->getChain(); 8394 SDValue BasePtr = LD->getBasePtr(); 8395 int SVOffset = LD->getSrcValueOffset(); 8396 unsigned Alignment = LD->getAlignment(); 8397 bool isVolatile = LD->isVolatile(); 8398 const Value *SV = LD->getSrcValue(); 8399 unsigned int LdWidth = LdVT.getSizeInBits(); 8400 8401 // Load value as a large register 8402 SDValueVector LdChain; 8403 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset, 8404 Alignment, isVolatile, LdWidth, NVT); 8405 8406 if (LdChain.size() == 1) { 8407 TFOp = LdChain[0]; 8408 return true; 8409 } 8410 else { 8411 TFOp=DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0], LdChain.size()); 8412 return false; 8413 } 8414} 8415 8416 8417void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain, 8418 SDValue Chain, 8419 SDValue BasePtr, 8420 const Value *SV, 8421 int SVOffset, 8422 unsigned Alignment, 8423 bool isVolatile, 8424 SDValue ValOp, 8425 unsigned StWidth) { 8426 // Breaks the stores into a series of power of 2 width stores. For any 8427 // width, we convert the vector to the vector of element size that we 8428 // want to store. This avoids requiring a stack convert. 8429 8430 // Find a width of the element type we can store with 8431 MVT VVT = ValOp.getValueType(); 8432 MVT EVT, VecEVT; 8433 unsigned EVTWidth; 8434 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT); 8435 EVTWidth = EVT.getSizeInBits(); 8436 8437 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, ValOp); 8438 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp, 8439 DAG.getIntPtrConstant(0)); 8440 SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset, 8441 isVolatile, Alignment); 8442 StChain.push_back(StOp); 8443 8444 // Check if we are done 8445 if (StWidth == EVTWidth) { 8446 return; 8447 } 8448 8449 unsigned Idx = 1; 8450 StWidth -= EVTWidth; 8451 unsigned Offset = 0; 8452 8453 while (StWidth > 0) { 8454 unsigned Increment = EVTWidth / 8; 8455 Offset += Increment; 8456 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr, 8457 DAG.getIntPtrConstant(Increment)); 8458 8459 if (StWidth < EVTWidth) { 8460 // Our current type we are using is too large, use a smaller size by 8461 // using a smaller power of 2 8462 unsigned oEVTWidth = EVTWidth; 8463 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT); 8464 EVTWidth = EVT.getSizeInBits(); 8465 // Readjust position and vector position based on new load type 8466 Idx = Idx * (oEVTWidth/EVTWidth); 8467 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp); 8468 } 8469 8470 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp, 8471 DAG.getIntPtrConstant(Idx++)); 8472 StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV, 8473 SVOffset + Offset, isVolatile, 8474 MinAlign(Alignment, Offset))); 8475 StWidth -= EVTWidth; 8476 } 8477} 8478 8479 8480SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST, 8481 SDValue Chain, 8482 SDValue BasePtr) { 8483 // TODO: It might be cleaner if we can use SplitVector and have more legal 8484 // vector types that can be stored into memory (e.g., v4xi8 can 8485 // be stored as a word). This will not work when a vector register 8486 // to memory mapping is strange (e.g., vector elements are not 8487 // stored in some sequential order). 8488 8489 MVT StVT = ST->getMemoryVT(); 8490 SDValue ValOp = ST->getValue(); 8491 8492 // Check if we have widen this node with another value 8493 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp); 8494 if (I != WidenNodes.end()) 8495 ValOp = I->second; 8496 8497 MVT VVT = ValOp.getValueType(); 8498 8499 // It must be true that we the widen vector type is bigger than where 8500 // we need to store. 8501 assert(StVT.isVector() && VVT.isVector()); 8502 assert(StVT.getSizeInBits() < VVT.getSizeInBits()); 8503 assert(StVT.getVectorElementType() == VVT.getVectorElementType()); 8504 8505 // Store value 8506 SDValueVector StChain; 8507 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(), 8508 ST->getSrcValueOffset(), ST->getAlignment(), 8509 ST->isVolatile(), ValOp, StVT.getSizeInBits()); 8510 if (StChain.size() == 1) 8511 return StChain[0]; 8512 else 8513 return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size()); 8514} 8515 8516 8517// SelectionDAG::Legalize - This is the entry point for the file. 8518// 8519void SelectionDAG::Legalize(bool TypesNeedLegalizing) { 8520 /// run - This is the main entry point to this class. 8521 /// 8522 SelectionDAGLegalize(*this, TypesNeedLegalizing).LegalizeDAG(); 8523} 8524 8525