LegalizeDAG.cpp revision 899c5cfbecf4221a3268384e417e85c29c130594
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/DwarfWriter.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/CodeGen/PseudoSourceValue.h" 22#include "llvm/Target/TargetFrameInfo.h" 23#include "llvm/Target/TargetLowering.h" 24#include "llvm/Target/TargetData.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Target/TargetSubtarget.h" 28#include "llvm/CallingConv.h" 29#include "llvm/Constants.h" 30#include "llvm/DerivedTypes.h" 31#include "llvm/Function.h" 32#include "llvm/GlobalVariable.h" 33#include "llvm/LLVMContext.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include "llvm/ADT/DenseMap.h" 40#include "llvm/ADT/SmallVector.h" 41#include "llvm/ADT/SmallPtrSet.h" 42#include <map> 43using namespace llvm; 44 45//===----------------------------------------------------------------------===// 46/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 47/// hacks on it until the target machine can handle it. This involves 48/// eliminating value sizes the machine cannot handle (promoting small sizes to 49/// large sizes or splitting up large values into small values) as well as 50/// eliminating operations the machine cannot handle. 51/// 52/// This code also does a small amount of optimization and recognition of idioms 53/// as part of its processing. For example, if a target does not support a 54/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 55/// will attempt merge setcc and brc instructions into brcc's. 56/// 57namespace { 58class SelectionDAGLegalize { 59 TargetLowering &TLI; 60 SelectionDAG &DAG; 61 CodeGenOpt::Level OptLevel; 62 63 // Libcall insertion helpers. 64 65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 66 /// legalized. We use this to ensure that calls are properly serialized 67 /// against each other, including inserted libcalls. 68 SDValue LastCALLSEQ_END; 69 70 /// IsLegalizingCall - This member is used *only* for purposes of providing 71 /// helpful assertions that a libcall isn't created while another call is 72 /// being legalized (which could lead to non-serialized call sequences). 73 bool IsLegalizingCall; 74 75 enum LegalizeAction { 76 Legal, // The target natively supports this operation. 77 Promote, // This operation should be executed in a larger type. 78 Expand // Try to expand this to other ops, otherwise use a libcall. 79 }; 80 81 /// ValueTypeActions - This is a bitvector that contains two bits for each 82 /// value type, where the two bits correspond to the LegalizeAction enum. 83 /// This can be queried with "getTypeAction(VT)". 84 TargetLowering::ValueTypeActionImpl ValueTypeActions; 85 86 /// LegalizedNodes - For nodes that are of legal width, and that have more 87 /// than one use, this map indicates what regularized operand to use. This 88 /// allows us to avoid legalizing the same thing more than once. 89 DenseMap<SDValue, SDValue> LegalizedNodes; 90 91 void AddLegalizedOperand(SDValue From, SDValue To) { 92 LegalizedNodes.insert(std::make_pair(From, To)); 93 // If someone requests legalization of the new node, return itself. 94 if (From != To) 95 LegalizedNodes.insert(std::make_pair(To, To)); 96 } 97 98public: 99 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 100 101 /// getTypeAction - Return how we should legalize values of this type, either 102 /// it is already legal or we need to expand it into multiple registers of 103 /// smaller integer type, or we need to promote it to a larger type. 104 LegalizeAction getTypeAction(EVT VT) const { 105 return 106 (LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT); 107 } 108 109 /// isTypeLegal - Return true if this type is legal on this target. 110 /// 111 bool isTypeLegal(EVT VT) const { 112 return getTypeAction(VT) == Legal; 113 } 114 115 void LegalizeDAG(); 116 117private: 118 /// LegalizeOp - We know that the specified value has a legal type. 119 /// Recursively ensure that the operands have legal types, then return the 120 /// result. 121 SDValue LegalizeOp(SDValue O); 122 123 SDValue OptimizeFloatStore(StoreSDNode *ST); 124 125 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 126 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 127 /// is necessary to spill the vector being inserted into to memory, perform 128 /// the insert there, and then read the result back. 129 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 130 SDValue Idx, DebugLoc dl); 131 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 132 SDValue Idx, DebugLoc dl); 133 134 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 135 /// performs the same shuffe in terms of order or result bytes, but on a type 136 /// whose vector element type is narrower than the original shuffle type. 137 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 138 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 139 SDValue N1, SDValue N2, 140 SmallVectorImpl<int> &Mask) const; 141 142 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 143 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 144 145 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 146 DebugLoc dl); 147 148 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 149 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 150 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 151 RTLIB::Libcall Call_PPCF128); 152 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 153 RTLIB::Libcall Call_I8, 154 RTLIB::Libcall Call_I16, 155 RTLIB::Libcall Call_I32, 156 RTLIB::Libcall Call_I64, 157 RTLIB::Libcall Call_I128); 158 159 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 160 SDValue ExpandBUILD_VECTOR(SDNode *Node); 161 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 162 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 163 SmallVectorImpl<SDValue> &Results); 164 SDValue ExpandFCOPYSIGN(SDNode *Node); 165 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 166 DebugLoc dl); 167 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 168 DebugLoc dl); 169 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 170 DebugLoc dl); 171 172 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 173 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 174 175 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 176 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 177 178 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 179 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 180}; 181} 182 183/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 184/// performs the same shuffe in terms of order or result bytes, but on a type 185/// whose vector element type is narrower than the original shuffle type. 186/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 187SDValue 188SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 189 SDValue N1, SDValue N2, 190 SmallVectorImpl<int> &Mask) const { 191 unsigned NumMaskElts = VT.getVectorNumElements(); 192 unsigned NumDestElts = NVT.getVectorNumElements(); 193 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 194 195 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 196 197 if (NumEltsGrowth == 1) 198 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 199 200 SmallVector<int, 8> NewMask; 201 for (unsigned i = 0; i != NumMaskElts; ++i) { 202 int Idx = Mask[i]; 203 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 204 if (Idx < 0) 205 NewMask.push_back(-1); 206 else 207 NewMask.push_back(Idx * NumEltsGrowth + j); 208 } 209 } 210 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 211 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 213} 214 215SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 216 CodeGenOpt::Level ol) 217 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), 218 ValueTypeActions(TLI.getValueTypeActions()) { 219 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 220 "Too many value types for ValueTypeActions to hold!"); 221} 222 223void SelectionDAGLegalize::LegalizeDAG() { 224 LastCALLSEQ_END = DAG.getEntryNode(); 225 IsLegalizingCall = false; 226 227 // The legalize process is inherently a bottom-up recursive process (users 228 // legalize their uses before themselves). Given infinite stack space, we 229 // could just start legalizing on the root and traverse the whole graph. In 230 // practice however, this causes us to run out of stack space on large basic 231 // blocks. To avoid this problem, compute an ordering of the nodes where each 232 // node is only legalized after all of its operands are legalized. 233 DAG.AssignTopologicalOrder(); 234 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 235 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 236 LegalizeOp(SDValue(I, 0)); 237 238 // Finally, it's possible the root changed. Get the new root. 239 SDValue OldRoot = DAG.getRoot(); 240 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 241 DAG.setRoot(LegalizedNodes[OldRoot]); 242 243 LegalizedNodes.clear(); 244 245 // Remove dead nodes now. 246 DAG.RemoveDeadNodes(); 247} 248 249 250/// FindCallEndFromCallStart - Given a chained node that is part of a call 251/// sequence, find the CALLSEQ_END node that terminates the call sequence. 252static SDNode *FindCallEndFromCallStart(SDNode *Node) { 253 if (Node->getOpcode() == ISD::CALLSEQ_END) 254 return Node; 255 if (Node->use_empty()) 256 return 0; // No CallSeqEnd 257 258 // The chain is usually at the end. 259 SDValue TheChain(Node, Node->getNumValues()-1); 260 if (TheChain.getValueType() != MVT::Other) { 261 // Sometimes it's at the beginning. 262 TheChain = SDValue(Node, 0); 263 if (TheChain.getValueType() != MVT::Other) { 264 // Otherwise, hunt for it. 265 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 266 if (Node->getValueType(i) == MVT::Other) { 267 TheChain = SDValue(Node, i); 268 break; 269 } 270 271 // Otherwise, we walked into a node without a chain. 272 if (TheChain.getValueType() != MVT::Other) 273 return 0; 274 } 275 } 276 277 for (SDNode::use_iterator UI = Node->use_begin(), 278 E = Node->use_end(); UI != E; ++UI) { 279 280 // Make sure to only follow users of our token chain. 281 SDNode *User = *UI; 282 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 283 if (User->getOperand(i) == TheChain) 284 if (SDNode *Result = FindCallEndFromCallStart(User)) 285 return Result; 286 } 287 return 0; 288} 289 290/// FindCallStartFromCallEnd - Given a chained node that is part of a call 291/// sequence, find the CALLSEQ_START node that initiates the call sequence. 292static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 293 assert(Node && "Didn't find callseq_start for a call??"); 294 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 295 296 assert(Node->getOperand(0).getValueType() == MVT::Other && 297 "Node doesn't have a token chain argument!"); 298 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 299} 300 301/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 302/// see if any uses can reach Dest. If no dest operands can get to dest, 303/// legalize them, legalize ourself, and return false, otherwise, return true. 304/// 305/// Keep track of the nodes we fine that actually do lead to Dest in 306/// NodesLeadingTo. This avoids retraversing them exponential number of times. 307/// 308bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 309 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 310 if (N == Dest) return true; // N certainly leads to Dest :) 311 312 // If we've already processed this node and it does lead to Dest, there is no 313 // need to reprocess it. 314 if (NodesLeadingTo.count(N)) return true; 315 316 // If the first result of this node has been already legalized, then it cannot 317 // reach N. 318 if (LegalizedNodes.count(SDValue(N, 0))) return false; 319 320 // Okay, this node has not already been legalized. Check and legalize all 321 // operands. If none lead to Dest, then we can legalize this node. 322 bool OperandsLeadToDest = false; 323 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 324 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 325 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 326 327 if (OperandsLeadToDest) { 328 NodesLeadingTo.insert(N); 329 return true; 330 } 331 332 // Okay, this node looks safe, legalize it and return false. 333 LegalizeOp(SDValue(N, 0)); 334 return false; 335} 336 337/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 338/// a load from the constant pool. 339static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 340 SelectionDAG &DAG, const TargetLowering &TLI) { 341 bool Extend = false; 342 DebugLoc dl = CFP->getDebugLoc(); 343 344 // If a FP immediate is precise when represented as a float and if the 345 // target can do an extending load from float to double, we put it into 346 // the constant pool as a float, even if it's is statically typed as a 347 // double. This shrinks FP constants and canonicalizes them for targets where 348 // an FP extending load is the same cost as a normal load (such as on the x87 349 // fp stack or PPC FP unit). 350 EVT VT = CFP->getValueType(0); 351 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 352 if (!UseCP) { 353 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 354 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 355 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 356 } 357 358 EVT OrigVT = VT; 359 EVT SVT = VT; 360 while (SVT != MVT::f32) { 361 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 362 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 363 // Only do this if the target has a native EXTLOAD instruction from 364 // smaller type. 365 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 366 TLI.ShouldShrinkFPConstant(OrigVT)) { 367 const Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 368 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 369 VT = SVT; 370 Extend = true; 371 } 372 } 373 374 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 375 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 376 if (Extend) 377 return DAG.getExtLoad(ISD::EXTLOAD, dl, 378 OrigVT, DAG.getEntryNode(), 379 CPIdx, PseudoSourceValue::getConstantPool(), 380 0, VT, false, false, Alignment); 381 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 382 PseudoSourceValue::getConstantPool(), 0, false, false, 383 Alignment); 384} 385 386/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 387static 388SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 389 const TargetLowering &TLI) { 390 SDValue Chain = ST->getChain(); 391 SDValue Ptr = ST->getBasePtr(); 392 SDValue Val = ST->getValue(); 393 EVT VT = Val.getValueType(); 394 int Alignment = ST->getAlignment(); 395 int SVOffset = ST->getSrcValueOffset(); 396 DebugLoc dl = ST->getDebugLoc(); 397 if (ST->getMemoryVT().isFloatingPoint() || 398 ST->getMemoryVT().isVector()) { 399 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 400 if (TLI.isTypeLegal(intVT)) { 401 // Expand to a bitconvert of the value to the integer type of the 402 // same size, then a (misaligned) int store. 403 // FIXME: Does not handle truncating floating point stores! 404 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 405 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 406 SVOffset, ST->isVolatile(), ST->isNonTemporal(), 407 Alignment); 408 } else { 409 // Do a (aligned) store to a stack slot, then copy from the stack slot 410 // to the final destination using (unaligned) integer loads and stores. 411 EVT StoredVT = ST->getMemoryVT(); 412 EVT RegVT = 413 TLI.getRegisterType(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), StoredVT.getSizeInBits())); 414 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 415 unsigned RegBytes = RegVT.getSizeInBits() / 8; 416 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 417 418 // Make sure the stack slot is also aligned for the register type. 419 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 420 421 // Perform the original store, only redirected to the stack slot. 422 SDValue Store = DAG.getTruncStore(Chain, dl, 423 Val, StackPtr, NULL, 0, StoredVT, 424 false, false, 0); 425 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 426 SmallVector<SDValue, 8> Stores; 427 unsigned Offset = 0; 428 429 // Do all but one copies using the full register width. 430 for (unsigned i = 1; i < NumRegs; i++) { 431 // Load one integer register's worth from the stack slot. 432 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0, 433 false, false, 0); 434 // Store it to the final location. Remember the store. 435 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 436 ST->getSrcValue(), SVOffset + Offset, 437 ST->isVolatile(), ST->isNonTemporal(), 438 MinAlign(ST->getAlignment(), Offset))); 439 // Increment the pointers. 440 Offset += RegBytes; 441 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 442 Increment); 443 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 444 } 445 446 // The last store may be partial. Do a truncating store. On big-endian 447 // machines this requires an extending load from the stack slot to ensure 448 // that the bits are in the right place. 449 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset)); 450 451 // Load from the stack slot. 452 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 453 NULL, 0, MemVT, false, false, 0); 454 455 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 456 ST->getSrcValue(), SVOffset + Offset, 457 MemVT, ST->isVolatile(), 458 ST->isNonTemporal(), 459 MinAlign(ST->getAlignment(), Offset))); 460 // The order of the stores doesn't matter - say it with a TokenFactor. 461 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 462 Stores.size()); 463 } 464 } 465 assert(ST->getMemoryVT().isInteger() && 466 !ST->getMemoryVT().isVector() && 467 "Unaligned store of unknown type."); 468 // Get the half-size VT 469 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 470 int NumBits = NewStoredVT.getSizeInBits(); 471 int IncrementSize = NumBits / 8; 472 473 // Divide the stored value in two parts. 474 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 475 SDValue Lo = Val; 476 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 477 478 // Store the two parts 479 SDValue Store1, Store2; 480 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 481 ST->getSrcValue(), SVOffset, NewStoredVT, 482 ST->isVolatile(), ST->isNonTemporal(), Alignment); 483 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 484 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 485 Alignment = MinAlign(Alignment, IncrementSize); 486 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 487 ST->getSrcValue(), SVOffset + IncrementSize, 488 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 489 Alignment); 490 491 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 492} 493 494/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 495static 496SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 497 const TargetLowering &TLI) { 498 int SVOffset = LD->getSrcValueOffset(); 499 SDValue Chain = LD->getChain(); 500 SDValue Ptr = LD->getBasePtr(); 501 EVT VT = LD->getValueType(0); 502 EVT LoadedVT = LD->getMemoryVT(); 503 DebugLoc dl = LD->getDebugLoc(); 504 if (VT.isFloatingPoint() || VT.isVector()) { 505 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 506 if (TLI.isTypeLegal(intVT)) { 507 // Expand to a (misaligned) integer load of the same size, 508 // then bitconvert to floating point or vector. 509 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 510 SVOffset, LD->isVolatile(), 511 LD->isNonTemporal(), LD->getAlignment()); 512 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 513 if (VT.isFloatingPoint() && LoadedVT != VT) 514 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 515 516 SDValue Ops[] = { Result, Chain }; 517 return DAG.getMergeValues(Ops, 2, dl); 518 } else { 519 // Copy the value to a (aligned) stack slot using (unaligned) integer 520 // loads and stores, then do a (aligned) load from the stack slot. 521 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 522 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 523 unsigned RegBytes = RegVT.getSizeInBits() / 8; 524 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 525 526 // Make sure the stack slot is also aligned for the register type. 527 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 528 529 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 530 SmallVector<SDValue, 8> Stores; 531 SDValue StackPtr = StackBase; 532 unsigned Offset = 0; 533 534 // Do all but one copies using the full register width. 535 for (unsigned i = 1; i < NumRegs; i++) { 536 // Load one integer register's worth from the original location. 537 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 538 SVOffset + Offset, LD->isVolatile(), 539 LD->isNonTemporal(), 540 MinAlign(LD->getAlignment(), Offset)); 541 // Follow the load with a store to the stack slot. Remember the store. 542 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 543 NULL, 0, false, false, 0)); 544 // Increment the pointers. 545 Offset += RegBytes; 546 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 547 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 548 Increment); 549 } 550 551 // The last copy may be partial. Do an extending load. 552 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (LoadedBytes - Offset)); 553 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 554 LD->getSrcValue(), SVOffset + Offset, 555 MemVT, LD->isVolatile(), 556 LD->isNonTemporal(), 557 MinAlign(LD->getAlignment(), Offset)); 558 // Follow the load with a store to the stack slot. Remember the store. 559 // On big-endian machines this requires a truncating store to ensure 560 // that the bits end up in the right place. 561 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 562 NULL, 0, MemVT, false, false, 0)); 563 564 // The order of the stores doesn't matter - say it with a TokenFactor. 565 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 566 Stores.size()); 567 568 // Finally, perform the original load only redirected to the stack slot. 569 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 570 NULL, 0, LoadedVT, false, false, 0); 571 572 // Callers expect a MERGE_VALUES node. 573 SDValue Ops[] = { Load, TF }; 574 return DAG.getMergeValues(Ops, 2, dl); 575 } 576 } 577 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 578 "Unaligned load of unsupported type."); 579 580 // Compute the new VT that is half the size of the old one. This is an 581 // integer MVT. 582 unsigned NumBits = LoadedVT.getSizeInBits(); 583 EVT NewLoadedVT; 584 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 585 NumBits >>= 1; 586 587 unsigned Alignment = LD->getAlignment(); 588 unsigned IncrementSize = NumBits / 8; 589 ISD::LoadExtType HiExtType = LD->getExtensionType(); 590 591 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 592 if (HiExtType == ISD::NON_EXTLOAD) 593 HiExtType = ISD::ZEXTLOAD; 594 595 // Load the value in two parts 596 SDValue Lo, Hi; 597 if (TLI.isLittleEndian()) { 598 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 599 SVOffset, NewLoadedVT, LD->isVolatile(), 600 LD->isNonTemporal(), Alignment); 601 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 602 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 603 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 604 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 605 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize)); 606 } else { 607 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 608 SVOffset, NewLoadedVT, LD->isVolatile(), 609 LD->isNonTemporal(), Alignment); 610 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 611 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 612 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 613 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 614 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize)); 615 } 616 617 // aggregate the two parts 618 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 619 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 620 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 621 622 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 623 Hi.getValue(1)); 624 625 SDValue Ops[] = { Result, TF }; 626 return DAG.getMergeValues(Ops, 2, dl); 627} 628 629/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 630/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 631/// is necessary to spill the vector being inserted into to memory, perform 632/// the insert there, and then read the result back. 633SDValue SelectionDAGLegalize:: 634PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 635 DebugLoc dl) { 636 SDValue Tmp1 = Vec; 637 SDValue Tmp2 = Val; 638 SDValue Tmp3 = Idx; 639 640 // If the target doesn't support this, we have to spill the input vector 641 // to a temporary stack slot, update the element, then reload it. This is 642 // badness. We could also load the value into a vector register (either 643 // with a "move to register" or "extload into register" instruction, then 644 // permute it into place, if the idx is a constant and if the idx is 645 // supported by the target. 646 EVT VT = Tmp1.getValueType(); 647 EVT EltVT = VT.getVectorElementType(); 648 EVT IdxVT = Tmp3.getValueType(); 649 EVT PtrVT = TLI.getPointerTy(); 650 SDValue StackPtr = DAG.CreateStackTemporary(VT); 651 652 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 653 654 // Store the vector. 655 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 656 PseudoSourceValue::getFixedStack(SPFI), 0, 657 false, false, 0); 658 659 // Truncate or zero extend offset to target pointer type. 660 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 661 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 662 // Add the offset to the index. 663 unsigned EltSize = EltVT.getSizeInBits()/8; 664 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 665 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 666 // Store the scalar value. 667 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 668 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT, 669 false, false, 0); 670 // Load the updated vector. 671 return DAG.getLoad(VT, dl, Ch, StackPtr, 672 PseudoSourceValue::getFixedStack(SPFI), 0, 673 false, false, 0); 674} 675 676 677SDValue SelectionDAGLegalize:: 678ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 679 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 680 // SCALAR_TO_VECTOR requires that the type of the value being inserted 681 // match the element type of the vector being created, except for 682 // integers in which case the inserted value can be over width. 683 EVT EltVT = Vec.getValueType().getVectorElementType(); 684 if (Val.getValueType() == EltVT || 685 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 686 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 687 Vec.getValueType(), Val); 688 689 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 690 // We generate a shuffle of InVec and ScVec, so the shuffle mask 691 // should be 0,1,2,3,4,5... with the appropriate element replaced with 692 // elt 0 of the RHS. 693 SmallVector<int, 8> ShufOps; 694 for (unsigned i = 0; i != NumElts; ++i) 695 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 696 697 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 698 &ShufOps[0]); 699 } 700 } 701 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 702} 703 704SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 705 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 706 // FIXME: We shouldn't do this for TargetConstantFP's. 707 // FIXME: move this to the DAG Combiner! Note that we can't regress due 708 // to phase ordering between legalized code and the dag combiner. This 709 // probably means that we need to integrate dag combiner and legalizer 710 // together. 711 // We generally can't do this one for long doubles. 712 SDValue Tmp1 = ST->getChain(); 713 SDValue Tmp2 = ST->getBasePtr(); 714 SDValue Tmp3; 715 int SVOffset = ST->getSrcValueOffset(); 716 unsigned Alignment = ST->getAlignment(); 717 bool isVolatile = ST->isVolatile(); 718 bool isNonTemporal = ST->isNonTemporal(); 719 DebugLoc dl = ST->getDebugLoc(); 720 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 721 if (CFP->getValueType(0) == MVT::f32 && 722 getTypeAction(MVT::i32) == Legal) { 723 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 724 bitcastToAPInt().zextOrTrunc(32), 725 MVT::i32); 726 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 727 SVOffset, isVolatile, isNonTemporal, Alignment); 728 } else if (CFP->getValueType(0) == MVT::f64) { 729 // If this target supports 64-bit registers, do a single 64-bit store. 730 if (getTypeAction(MVT::i64) == Legal) { 731 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 732 zextOrTrunc(64), MVT::i64); 733 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 734 SVOffset, isVolatile, isNonTemporal, Alignment); 735 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 736 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 737 // stores. If the target supports neither 32- nor 64-bits, this 738 // xform is certainly not worth it. 739 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 740 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 741 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 742 if (TLI.isBigEndian()) std::swap(Lo, Hi); 743 744 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 745 SVOffset, isVolatile, isNonTemporal, Alignment); 746 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 747 DAG.getIntPtrConstant(4)); 748 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 749 isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); 750 751 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 752 } 753 } 754 } 755 return SDValue(); 756} 757 758/// LegalizeOp - We know that the specified value has a legal type, and 759/// that its operands are legal. Now ensure that the operation itself 760/// is legal, recursively ensuring that the operands' operations remain 761/// legal. 762SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 763 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 764 return Op; 765 766 SDNode *Node = Op.getNode(); 767 DebugLoc dl = Node->getDebugLoc(); 768 769 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 770 assert(getTypeAction(Node->getValueType(i)) == Legal && 771 "Unexpected illegal type!"); 772 773 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 774 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 775 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 776 "Unexpected illegal type!"); 777 778 // Note that LegalizeOp may be reentered even from single-use nodes, which 779 // means that we always must cache transformed nodes. 780 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 781 if (I != LegalizedNodes.end()) return I->second; 782 783 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 784 SDValue Result = Op; 785 bool isCustom = false; 786 787 // Figure out the correct action; the way to query this varies by opcode 788 TargetLowering::LegalizeAction Action; 789 bool SimpleFinishLegalizing = true; 790 switch (Node->getOpcode()) { 791 case ISD::INTRINSIC_W_CHAIN: 792 case ISD::INTRINSIC_WO_CHAIN: 793 case ISD::INTRINSIC_VOID: 794 case ISD::VAARG: 795 case ISD::STACKSAVE: 796 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 797 break; 798 case ISD::SINT_TO_FP: 799 case ISD::UINT_TO_FP: 800 case ISD::EXTRACT_VECTOR_ELT: 801 Action = TLI.getOperationAction(Node->getOpcode(), 802 Node->getOperand(0).getValueType()); 803 break; 804 case ISD::FP_ROUND_INREG: 805 case ISD::SIGN_EXTEND_INREG: { 806 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 807 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 808 break; 809 } 810 case ISD::SELECT_CC: 811 case ISD::SETCC: 812 case ISD::BR_CC: { 813 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 814 Node->getOpcode() == ISD::SETCC ? 2 : 1; 815 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 816 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 817 ISD::CondCode CCCode = 818 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 819 Action = TLI.getCondCodeAction(CCCode, OpVT); 820 if (Action == TargetLowering::Legal) { 821 if (Node->getOpcode() == ISD::SELECT_CC) 822 Action = TLI.getOperationAction(Node->getOpcode(), 823 Node->getValueType(0)); 824 else 825 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 826 } 827 break; 828 } 829 case ISD::LOAD: 830 case ISD::STORE: 831 // FIXME: Model these properly. LOAD and STORE are complicated, and 832 // STORE expects the unlegalized operand in some cases. 833 SimpleFinishLegalizing = false; 834 break; 835 case ISD::CALLSEQ_START: 836 case ISD::CALLSEQ_END: 837 // FIXME: This shouldn't be necessary. These nodes have special properties 838 // dealing with the recursive nature of legalization. Removing this 839 // special case should be done as part of making LegalizeDAG non-recursive. 840 SimpleFinishLegalizing = false; 841 break; 842 case ISD::EXTRACT_ELEMENT: 843 case ISD::FLT_ROUNDS_: 844 case ISD::SADDO: 845 case ISD::SSUBO: 846 case ISD::UADDO: 847 case ISD::USUBO: 848 case ISD::SMULO: 849 case ISD::UMULO: 850 case ISD::FPOWI: 851 case ISD::MERGE_VALUES: 852 case ISD::EH_RETURN: 853 case ISD::FRAME_TO_ARGS_OFFSET: 854 case ISD::FP16_TO_FP32: 855 case ISD::FP32_TO_FP16: 856 // These operations lie about being legal: when they claim to be legal, 857 // they should actually be expanded. 858 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 859 if (Action == TargetLowering::Legal) 860 Action = TargetLowering::Expand; 861 break; 862 case ISD::TRAMPOLINE: 863 case ISD::FRAMEADDR: 864 case ISD::RETURNADDR: 865 // These operations lie about being legal: when they claim to be legal, 866 // they should actually be custom-lowered. 867 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 868 if (Action == TargetLowering::Legal) 869 Action = TargetLowering::Custom; 870 break; 871 case ISD::BUILD_VECTOR: 872 // A weird case: legalization for BUILD_VECTOR never legalizes the 873 // operands! 874 // FIXME: This really sucks... changing it isn't semantically incorrect, 875 // but it massively pessimizes the code for floating-point BUILD_VECTORs 876 // because ConstantFP operands get legalized into constant pool loads 877 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 878 // though, because BUILD_VECTORS usually get lowered into other nodes 879 // which get legalized properly. 880 SimpleFinishLegalizing = false; 881 break; 882 default: 883 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 884 Action = TargetLowering::Legal; 885 } else { 886 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 887 } 888 break; 889 } 890 891 if (SimpleFinishLegalizing) { 892 SmallVector<SDValue, 8> Ops, ResultVals; 893 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 894 Ops.push_back(LegalizeOp(Node->getOperand(i))); 895 switch (Node->getOpcode()) { 896 default: break; 897 case ISD::BR: 898 case ISD::BRIND: 899 case ISD::BR_JT: 900 case ISD::BR_CC: 901 case ISD::BRCOND: 902 // Branches tweak the chain to include LastCALLSEQ_END 903 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 904 LastCALLSEQ_END); 905 Ops[0] = LegalizeOp(Ops[0]); 906 LastCALLSEQ_END = DAG.getEntryNode(); 907 break; 908 case ISD::SHL: 909 case ISD::SRL: 910 case ISD::SRA: 911 case ISD::ROTL: 912 case ISD::ROTR: 913 // Legalizing shifts/rotates requires adjusting the shift amount 914 // to the appropriate width. 915 if (!Ops[1].getValueType().isVector()) 916 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 917 break; 918 case ISD::SRL_PARTS: 919 case ISD::SRA_PARTS: 920 case ISD::SHL_PARTS: 921 // Legalizing shifts/rotates requires adjusting the shift amount 922 // to the appropriate width. 923 if (!Ops[2].getValueType().isVector()) 924 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2])); 925 break; 926 } 927 928 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(), 929 Ops.size()); 930 switch (Action) { 931 case TargetLowering::Legal: 932 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 933 ResultVals.push_back(Result.getValue(i)); 934 break; 935 case TargetLowering::Custom: 936 // FIXME: The handling for custom lowering with multiple results is 937 // a complete mess. 938 Tmp1 = TLI.LowerOperation(Result, DAG); 939 if (Tmp1.getNode()) { 940 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 941 if (e == 1) 942 ResultVals.push_back(Tmp1); 943 else 944 ResultVals.push_back(Tmp1.getValue(i)); 945 } 946 break; 947 } 948 949 // FALL THROUGH 950 case TargetLowering::Expand: 951 ExpandNode(Result.getNode(), ResultVals); 952 break; 953 case TargetLowering::Promote: 954 PromoteNode(Result.getNode(), ResultVals); 955 break; 956 } 957 if (!ResultVals.empty()) { 958 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 959 if (ResultVals[i] != SDValue(Node, i)) 960 ResultVals[i] = LegalizeOp(ResultVals[i]); 961 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 962 } 963 return ResultVals[Op.getResNo()]; 964 } 965 } 966 967 switch (Node->getOpcode()) { 968 default: 969#ifndef NDEBUG 970 dbgs() << "NODE: "; 971 Node->dump( &DAG); 972 dbgs() << "\n"; 973#endif 974 llvm_unreachable("Do not know how to legalize this operator!"); 975 976 case ISD::BUILD_VECTOR: 977 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 978 default: llvm_unreachable("This action is not supported yet!"); 979 case TargetLowering::Custom: 980 Tmp3 = TLI.LowerOperation(Result, DAG); 981 if (Tmp3.getNode()) { 982 Result = Tmp3; 983 break; 984 } 985 // FALLTHROUGH 986 case TargetLowering::Expand: 987 Result = ExpandBUILD_VECTOR(Result.getNode()); 988 break; 989 } 990 break; 991 case ISD::CALLSEQ_START: { 992 SDNode *CallEnd = FindCallEndFromCallStart(Node); 993 994 // Recursively Legalize all of the inputs of the call end that do not lead 995 // to this call start. This ensures that any libcalls that need be inserted 996 // are inserted *before* the CALLSEQ_START. 997 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 998 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 999 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1000 NodesLeadingTo); 1001 } 1002 1003 // Now that we legalized all of the inputs (which may have inserted 1004 // libcalls) create the new CALLSEQ_START node. 1005 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1006 1007 // Merge in the last call, to ensure that this call start after the last 1008 // call ended. 1009 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1010 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1011 Tmp1, LastCALLSEQ_END); 1012 Tmp1 = LegalizeOp(Tmp1); 1013 } 1014 1015 // Do not try to legalize the target-specific arguments (#1+). 1016 if (Tmp1 != Node->getOperand(0)) { 1017 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1018 Ops[0] = Tmp1; 1019 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1020 } 1021 1022 // Remember that the CALLSEQ_START is legalized. 1023 AddLegalizedOperand(Op.getValue(0), Result); 1024 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1025 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1026 1027 // Now that the callseq_start and all of the non-call nodes above this call 1028 // sequence have been legalized, legalize the call itself. During this 1029 // process, no libcalls can/will be inserted, guaranteeing that no calls 1030 // can overlap. 1031 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1032 // Note that we are selecting this call! 1033 LastCALLSEQ_END = SDValue(CallEnd, 0); 1034 IsLegalizingCall = true; 1035 1036 // Legalize the call, starting from the CALLSEQ_END. 1037 LegalizeOp(LastCALLSEQ_END); 1038 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1039 return Result; 1040 } 1041 case ISD::CALLSEQ_END: 1042 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1043 // will cause this node to be legalized as well as handling libcalls right. 1044 if (LastCALLSEQ_END.getNode() != Node) { 1045 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1046 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1047 assert(I != LegalizedNodes.end() && 1048 "Legalizing the call start should have legalized this node!"); 1049 return I->second; 1050 } 1051 1052 // Otherwise, the call start has been legalized and everything is going 1053 // according to plan. Just legalize ourselves normally here. 1054 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1055 // Do not try to legalize the target-specific arguments (#1+), except for 1056 // an optional flag input. 1057 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1058 if (Tmp1 != Node->getOperand(0)) { 1059 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1060 Ops[0] = Tmp1; 1061 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1062 } 1063 } else { 1064 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1065 if (Tmp1 != Node->getOperand(0) || 1066 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1067 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1068 Ops[0] = Tmp1; 1069 Ops.back() = Tmp2; 1070 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1071 } 1072 } 1073 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1074 // This finishes up call legalization. 1075 IsLegalizingCall = false; 1076 1077 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1078 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1079 if (Node->getNumValues() == 2) 1080 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1081 return Result.getValue(Op.getResNo()); 1082 case ISD::LOAD: { 1083 LoadSDNode *LD = cast<LoadSDNode>(Node); 1084 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1085 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1086 1087 ISD::LoadExtType ExtType = LD->getExtensionType(); 1088 if (ExtType == ISD::NON_EXTLOAD) { 1089 EVT VT = Node->getValueType(0); 1090 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1091 Tmp3 = Result.getValue(0); 1092 Tmp4 = Result.getValue(1); 1093 1094 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1095 default: llvm_unreachable("This action is not supported yet!"); 1096 case TargetLowering::Legal: 1097 // If this is an unaligned load and the target doesn't support it, 1098 // expand it. 1099 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1100 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1101 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1102 if (LD->getAlignment() < ABIAlignment){ 1103 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1104 DAG, TLI); 1105 Tmp3 = Result.getOperand(0); 1106 Tmp4 = Result.getOperand(1); 1107 Tmp3 = LegalizeOp(Tmp3); 1108 Tmp4 = LegalizeOp(Tmp4); 1109 } 1110 } 1111 break; 1112 case TargetLowering::Custom: 1113 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1114 if (Tmp1.getNode()) { 1115 Tmp3 = LegalizeOp(Tmp1); 1116 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1117 } 1118 break; 1119 case TargetLowering::Promote: { 1120 // Only promote a load of vector type to another. 1121 assert(VT.isVector() && "Cannot promote this load!"); 1122 // Change base type to a different vector type. 1123 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1124 1125 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1126 LD->getSrcValueOffset(), 1127 LD->isVolatile(), LD->isNonTemporal(), 1128 LD->getAlignment()); 1129 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1130 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1131 break; 1132 } 1133 } 1134 // Since loads produce two values, make sure to remember that we 1135 // legalized both of them. 1136 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1137 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1138 return Op.getResNo() ? Tmp4 : Tmp3; 1139 } else { 1140 EVT SrcVT = LD->getMemoryVT(); 1141 unsigned SrcWidth = SrcVT.getSizeInBits(); 1142 int SVOffset = LD->getSrcValueOffset(); 1143 unsigned Alignment = LD->getAlignment(); 1144 bool isVolatile = LD->isVolatile(); 1145 bool isNonTemporal = LD->isNonTemporal(); 1146 1147 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1148 // Some targets pretend to have an i1 loading operation, and actually 1149 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1150 // bits are guaranteed to be zero; it helps the optimizers understand 1151 // that these bits are zero. It is also useful for EXTLOAD, since it 1152 // tells the optimizers that those bits are undefined. It would be 1153 // nice to have an effective generic way of getting these benefits... 1154 // Until such a way is found, don't insist on promoting i1 here. 1155 (SrcVT != MVT::i1 || 1156 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1157 // Promote to a byte-sized load if not loading an integral number of 1158 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1159 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1160 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 1161 SDValue Ch; 1162 1163 // The extra bits are guaranteed to be zero, since we stored them that 1164 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1165 1166 ISD::LoadExtType NewExtType = 1167 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1168 1169 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 1170 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1171 NVT, isVolatile, isNonTemporal, Alignment); 1172 1173 Ch = Result.getValue(1); // The chain. 1174 1175 if (ExtType == ISD::SEXTLOAD) 1176 // Having the top bits zero doesn't help when sign extending. 1177 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1178 Result.getValueType(), 1179 Result, DAG.getValueType(SrcVT)); 1180 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1181 // All the top bits are guaranteed to be zero - inform the optimizers. 1182 Result = DAG.getNode(ISD::AssertZext, dl, 1183 Result.getValueType(), Result, 1184 DAG.getValueType(SrcVT)); 1185 1186 Tmp1 = LegalizeOp(Result); 1187 Tmp2 = LegalizeOp(Ch); 1188 } else if (SrcWidth & (SrcWidth - 1)) { 1189 // If not loading a power-of-2 number of bits, expand as two loads. 1190 assert(!SrcVT.isVector() && "Unsupported extload!"); 1191 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1192 assert(RoundWidth < SrcWidth); 1193 unsigned ExtraWidth = SrcWidth - RoundWidth; 1194 assert(ExtraWidth < RoundWidth); 1195 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1196 "Load size not an integral number of bytes!"); 1197 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1198 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1199 SDValue Lo, Hi, Ch; 1200 unsigned IncrementSize; 1201 1202 if (TLI.isLittleEndian()) { 1203 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1204 // Load the bottom RoundWidth bits. 1205 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1206 Node->getValueType(0), Tmp1, Tmp2, 1207 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1208 isNonTemporal, Alignment); 1209 1210 // Load the remaining ExtraWidth bits. 1211 IncrementSize = RoundWidth / 8; 1212 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1213 DAG.getIntPtrConstant(IncrementSize)); 1214 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1215 LD->getSrcValue(), SVOffset + IncrementSize, 1216 ExtraVT, isVolatile, isNonTemporal, 1217 MinAlign(Alignment, IncrementSize)); 1218 1219 // Build a factor node to remember that this load is independent of the 1220 // other one. 1221 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1222 Hi.getValue(1)); 1223 1224 // Move the top bits to the right place. 1225 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1226 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1227 1228 // Join the hi and lo parts. 1229 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1230 } else { 1231 // Big endian - avoid unaligned loads. 1232 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1233 // Load the top RoundWidth bits. 1234 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1235 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1236 isNonTemporal, Alignment); 1237 1238 // Load the remaining ExtraWidth bits. 1239 IncrementSize = RoundWidth / 8; 1240 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1241 DAG.getIntPtrConstant(IncrementSize)); 1242 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1243 Node->getValueType(0), Tmp1, Tmp2, 1244 LD->getSrcValue(), SVOffset + IncrementSize, 1245 ExtraVT, isVolatile, isNonTemporal, 1246 MinAlign(Alignment, IncrementSize)); 1247 1248 // Build a factor node to remember that this load is independent of the 1249 // other one. 1250 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1251 Hi.getValue(1)); 1252 1253 // Move the top bits to the right place. 1254 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1255 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1256 1257 // Join the hi and lo parts. 1258 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1259 } 1260 1261 Tmp1 = LegalizeOp(Result); 1262 Tmp2 = LegalizeOp(Ch); 1263 } else { 1264 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1265 default: llvm_unreachable("This action is not supported yet!"); 1266 case TargetLowering::Custom: 1267 isCustom = true; 1268 // FALLTHROUGH 1269 case TargetLowering::Legal: 1270 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1271 Tmp1 = Result.getValue(0); 1272 Tmp2 = Result.getValue(1); 1273 1274 if (isCustom) { 1275 Tmp3 = TLI.LowerOperation(Result, DAG); 1276 if (Tmp3.getNode()) { 1277 Tmp1 = LegalizeOp(Tmp3); 1278 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1279 } 1280 } else { 1281 // If this is an unaligned load and the target doesn't support it, 1282 // expand it. 1283 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1284 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1285 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1286 if (LD->getAlignment() < ABIAlignment){ 1287 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1288 DAG, TLI); 1289 Tmp1 = Result.getOperand(0); 1290 Tmp2 = Result.getOperand(1); 1291 Tmp1 = LegalizeOp(Tmp1); 1292 Tmp2 = LegalizeOp(Tmp2); 1293 } 1294 } 1295 } 1296 break; 1297 case TargetLowering::Expand: 1298 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1299 // f128 = EXTLOAD {f32,f64} too 1300 if ((SrcVT == MVT::f32 && (Node->getValueType(0) == MVT::f64 || 1301 Node->getValueType(0) == MVT::f128)) || 1302 (SrcVT == MVT::f64 && Node->getValueType(0) == MVT::f128)) { 1303 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1304 LD->getSrcValueOffset(), 1305 LD->isVolatile(), LD->isNonTemporal(), 1306 LD->getAlignment()); 1307 Result = DAG.getNode(ISD::FP_EXTEND, dl, 1308 Node->getValueType(0), Load); 1309 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1310 Tmp2 = LegalizeOp(Load.getValue(1)); 1311 break; 1312 } 1313 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1314 // Turn the unsupported load into an EXTLOAD followed by an explicit 1315 // zero/sign extend inreg. 1316 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1317 Tmp1, Tmp2, LD->getSrcValue(), 1318 LD->getSrcValueOffset(), SrcVT, 1319 LD->isVolatile(), LD->isNonTemporal(), 1320 LD->getAlignment()); 1321 SDValue ValRes; 1322 if (ExtType == ISD::SEXTLOAD) 1323 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1324 Result.getValueType(), 1325 Result, DAG.getValueType(SrcVT)); 1326 else 1327 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1328 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1329 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1330 break; 1331 } 1332 } 1333 1334 // Since loads produce two values, make sure to remember that we legalized 1335 // both of them. 1336 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1337 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1338 return Op.getResNo() ? Tmp2 : Tmp1; 1339 } 1340 } 1341 case ISD::STORE: { 1342 StoreSDNode *ST = cast<StoreSDNode>(Node); 1343 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1344 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1345 int SVOffset = ST->getSrcValueOffset(); 1346 unsigned Alignment = ST->getAlignment(); 1347 bool isVolatile = ST->isVolatile(); 1348 bool isNonTemporal = ST->isNonTemporal(); 1349 1350 if (!ST->isTruncatingStore()) { 1351 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1352 Result = SDValue(OptStore, 0); 1353 break; 1354 } 1355 1356 { 1357 Tmp3 = LegalizeOp(ST->getValue()); 1358 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1359 ST->getOffset()); 1360 1361 EVT VT = Tmp3.getValueType(); 1362 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1363 default: llvm_unreachable("This action is not supported yet!"); 1364 case TargetLowering::Legal: 1365 // If this is an unaligned store and the target doesn't support it, 1366 // expand it. 1367 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1368 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1369 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1370 if (ST->getAlignment() < ABIAlignment) 1371 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1372 DAG, TLI); 1373 } 1374 break; 1375 case TargetLowering::Custom: 1376 Tmp1 = TLI.LowerOperation(Result, DAG); 1377 if (Tmp1.getNode()) Result = Tmp1; 1378 break; 1379 case TargetLowering::Promote: 1380 assert(VT.isVector() && "Unknown legal promote case!"); 1381 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1382 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1383 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1384 ST->getSrcValue(), SVOffset, isVolatile, 1385 isNonTemporal, Alignment); 1386 break; 1387 } 1388 break; 1389 } 1390 } else { 1391 Tmp3 = LegalizeOp(ST->getValue()); 1392 1393 EVT StVT = ST->getMemoryVT(); 1394 unsigned StWidth = StVT.getSizeInBits(); 1395 1396 if (StWidth != StVT.getStoreSizeInBits()) { 1397 // Promote to a byte-sized store with upper bits zero if not 1398 // storing an integral number of bytes. For example, promote 1399 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1400 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StVT.getStoreSizeInBits()); 1401 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1402 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1403 SVOffset, NVT, isVolatile, isNonTemporal, 1404 Alignment); 1405 } else if (StWidth & (StWidth - 1)) { 1406 // If not storing a power-of-2 number of bits, expand as two stores. 1407 assert(!StVT.isVector() && "Unsupported truncstore!"); 1408 unsigned RoundWidth = 1 << Log2_32(StWidth); 1409 assert(RoundWidth < StWidth); 1410 unsigned ExtraWidth = StWidth - RoundWidth; 1411 assert(ExtraWidth < RoundWidth); 1412 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1413 "Store size not an integral number of bytes!"); 1414 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1415 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1416 SDValue Lo, Hi; 1417 unsigned IncrementSize; 1418 1419 if (TLI.isLittleEndian()) { 1420 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1421 // Store the bottom RoundWidth bits. 1422 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1423 SVOffset, RoundVT, 1424 isVolatile, isNonTemporal, Alignment); 1425 1426 // Store the remaining ExtraWidth bits. 1427 IncrementSize = RoundWidth / 8; 1428 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1429 DAG.getIntPtrConstant(IncrementSize)); 1430 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1431 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1432 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1433 SVOffset + IncrementSize, ExtraVT, isVolatile, 1434 isNonTemporal, 1435 MinAlign(Alignment, IncrementSize)); 1436 } else { 1437 // Big endian - avoid unaligned stores. 1438 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1439 // Store the top RoundWidth bits. 1440 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1441 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1442 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1443 SVOffset, RoundVT, isVolatile, isNonTemporal, 1444 Alignment); 1445 1446 // Store the remaining ExtraWidth bits. 1447 IncrementSize = RoundWidth / 8; 1448 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1449 DAG.getIntPtrConstant(IncrementSize)); 1450 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1451 SVOffset + IncrementSize, ExtraVT, isVolatile, 1452 isNonTemporal, 1453 MinAlign(Alignment, IncrementSize)); 1454 } 1455 1456 // The order of the stores doesn't matter. 1457 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1458 } else { 1459 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1460 Tmp2 != ST->getBasePtr()) 1461 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1462 ST->getOffset()); 1463 1464 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1465 default: llvm_unreachable("This action is not supported yet!"); 1466 case TargetLowering::Legal: 1467 // If this is an unaligned store and the target doesn't support it, 1468 // expand it. 1469 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1470 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1471 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1472 if (ST->getAlignment() < ABIAlignment) 1473 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1474 DAG, TLI); 1475 } 1476 break; 1477 case TargetLowering::Custom: 1478 Result = TLI.LowerOperation(Result, DAG); 1479 break; 1480 case Expand: 1481 // TRUNCSTORE:i16 i32 -> STORE i16 1482 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1483 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1484 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1485 SVOffset, isVolatile, isNonTemporal, 1486 Alignment); 1487 break; 1488 } 1489 } 1490 } 1491 break; 1492 } 1493 } 1494 assert(Result.getValueType() == Op.getValueType() && 1495 "Bad legalization!"); 1496 1497 // Make sure that the generated code is itself legal. 1498 if (Result != Op) 1499 Result = LegalizeOp(Result); 1500 1501 // Note that LegalizeOp may be reentered even from single-use nodes, which 1502 // means that we always must cache transformed nodes. 1503 AddLegalizedOperand(Op, Result); 1504 return Result; 1505} 1506 1507SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1508 SDValue Vec = Op.getOperand(0); 1509 SDValue Idx = Op.getOperand(1); 1510 DebugLoc dl = Op.getDebugLoc(); 1511 // Store the value to a temporary stack slot, then LOAD the returned part. 1512 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1513 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0, 1514 false, false, 0); 1515 1516 // Add the offset to the index. 1517 unsigned EltSize = 1518 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1519 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1520 DAG.getConstant(EltSize, Idx.getValueType())); 1521 1522 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1523 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1524 else 1525 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1526 1527 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1528 1529 if (Op.getValueType().isVector()) 1530 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0, 1531 false, false, 0); 1532 else 1533 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1534 NULL, 0, Vec.getValueType().getVectorElementType(), 1535 false, false, 0); 1536} 1537 1538SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1539 // We can't handle this case efficiently. Allocate a sufficiently 1540 // aligned object on the stack, store each element into it, then load 1541 // the result as a vector. 1542 // Create the stack frame object. 1543 EVT VT = Node->getValueType(0); 1544 EVT EltVT = VT.getVectorElementType(); 1545 DebugLoc dl = Node->getDebugLoc(); 1546 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1547 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1548 const Value *SV = PseudoSourceValue::getFixedStack(FI); 1549 1550 // Emit a store of each element to the stack slot. 1551 SmallVector<SDValue, 8> Stores; 1552 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1553 // Store (in the right endianness) the elements to memory. 1554 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1555 // Ignore undef elements. 1556 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1557 1558 unsigned Offset = TypeByteSize*i; 1559 1560 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1561 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1562 1563 // If the destination vector element type is narrower than the source 1564 // element type, only store the bits necessary. 1565 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1566 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1567 Node->getOperand(i), Idx, SV, Offset, 1568 EltVT, false, false, 0)); 1569 } else 1570 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1571 Node->getOperand(i), Idx, SV, Offset, 1572 false, false, 0)); 1573 } 1574 1575 SDValue StoreChain; 1576 if (!Stores.empty()) // Not all undef elements? 1577 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1578 &Stores[0], Stores.size()); 1579 else 1580 StoreChain = DAG.getEntryNode(); 1581 1582 // Result is a load from the stack slot. 1583 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0, false, false, 0); 1584} 1585 1586SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1587 DebugLoc dl = Node->getDebugLoc(); 1588 SDValue Tmp1 = Node->getOperand(0); 1589 SDValue Tmp2 = Node->getOperand(1); 1590 1591 // Get the sign bit of the RHS. First obtain a value that has the same 1592 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1593 SDValue SignBit; 1594 EVT FloatVT = Tmp2.getValueType(); 1595 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1596 if (isTypeLegal(IVT)) { 1597 // Convert to an integer with the same sign bit. 1598 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 1599 } else { 1600 // Store the float to memory, then load the sign part out as an integer. 1601 MVT LoadTy = TLI.getPointerTy(); 1602 // First create a temporary that is aligned for both the load and store. 1603 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1604 // Then store the float to it. 1605 SDValue Ch = 1606 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, NULL, 0, 1607 false, false, 0); 1608 if (TLI.isBigEndian()) { 1609 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1610 // Load out a legal integer with the same sign bit as the float. 1611 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, NULL, 0, false, false, 0); 1612 } else { // Little endian 1613 SDValue LoadPtr = StackPtr; 1614 // The float may be wider than the integer we are going to load. Advance 1615 // the pointer so that the loaded integer will contain the sign bit. 1616 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1617 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1618 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1619 LoadPtr, DAG.getIntPtrConstant(ByteOffset)); 1620 // Load a legal integer containing the sign bit. 1621 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, NULL, 0, false, false, 0); 1622 // Move the sign bit to the top bit of the loaded integer. 1623 unsigned BitShift = LoadTy.getSizeInBits() - 1624 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1625 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1626 if (BitShift) 1627 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1628 DAG.getConstant(BitShift,TLI.getShiftAmountTy())); 1629 } 1630 } 1631 // Now get the sign bit proper, by seeing whether the value is negative. 1632 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1633 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1634 ISD::SETLT); 1635 // Get the absolute value of the result. 1636 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1637 // Select between the nabs and abs value based on the sign bit of 1638 // the input. 1639 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1640 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1641 AbsVal); 1642} 1643 1644void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1645 SmallVectorImpl<SDValue> &Results) { 1646 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1647 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1648 " not tell us which reg is the stack pointer!"); 1649 DebugLoc dl = Node->getDebugLoc(); 1650 EVT VT = Node->getValueType(0); 1651 SDValue Tmp1 = SDValue(Node, 0); 1652 SDValue Tmp2 = SDValue(Node, 1); 1653 SDValue Tmp3 = Node->getOperand(2); 1654 SDValue Chain = Tmp1.getOperand(0); 1655 1656 // Chain the dynamic stack allocation so that it doesn't modify the stack 1657 // pointer when other instructions are using the stack. 1658 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1659 1660 SDValue Size = Tmp2.getOperand(1); 1661 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1662 Chain = SP.getValue(1); 1663 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1664 unsigned StackAlign = 1665 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1666 if (Align > StackAlign) 1667 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1668 DAG.getConstant(-(uint64_t)Align, VT)); 1669 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1670 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1671 1672 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1673 DAG.getIntPtrConstant(0, true), SDValue()); 1674 1675 Results.push_back(Tmp1); 1676 Results.push_back(Tmp2); 1677} 1678 1679/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1680/// condition code CC on the current target. This routine expands SETCC with 1681/// illegal condition code into AND / OR of multiple SETCC values. 1682void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1683 SDValue &LHS, SDValue &RHS, 1684 SDValue &CC, 1685 DebugLoc dl) { 1686 EVT OpVT = LHS.getValueType(); 1687 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1688 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1689 default: llvm_unreachable("Unknown condition code action!"); 1690 case TargetLowering::Legal: 1691 // Nothing to do. 1692 break; 1693 case TargetLowering::Expand: { 1694 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1695 unsigned Opc = 0; 1696 switch (CCCode) { 1697 default: llvm_unreachable("Don't know how to expand this condition!"); 1698 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1699 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1700 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1701 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1702 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1703 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1704 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1705 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1706 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1707 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1708 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1709 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1710 // FIXME: Implement more expansions. 1711 } 1712 1713 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1714 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1715 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1716 RHS = SDValue(); 1717 CC = SDValue(); 1718 break; 1719 } 1720 } 1721} 1722 1723/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1724/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1725/// a load from the stack slot to DestVT, extending it if needed. 1726/// The resultant code need not be legal. 1727SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1728 EVT SlotVT, 1729 EVT DestVT, 1730 DebugLoc dl) { 1731 // Create the stack frame object. 1732 unsigned SrcAlign = 1733 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1734 getTypeForEVT(*DAG.getContext())); 1735 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1736 1737 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1738 int SPFI = StackPtrFI->getIndex(); 1739 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1740 1741 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1742 unsigned SlotSize = SlotVT.getSizeInBits(); 1743 unsigned DestSize = DestVT.getSizeInBits(); 1744 unsigned DestAlign = 1745 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT(*DAG.getContext())); 1746 1747 // Emit a store to the stack slot. Use a truncstore if the input value is 1748 // later than DestVT. 1749 SDValue Store; 1750 1751 if (SrcSize > SlotSize) 1752 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1753 SV, 0, SlotVT, false, false, SrcAlign); 1754 else { 1755 assert(SrcSize == SlotSize && "Invalid store"); 1756 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1757 SV, 0, false, false, SrcAlign); 1758 } 1759 1760 // Result is a load from the stack slot. 1761 if (SlotSize == DestSize) 1762 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, false, 1763 DestAlign); 1764 1765 assert(SlotSize < DestSize && "Unknown extension!"); 1766 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, 1767 false, false, DestAlign); 1768} 1769 1770SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1771 DebugLoc dl = Node->getDebugLoc(); 1772 // Create a vector sized/aligned stack slot, store the value to element #0, 1773 // then load the whole vector back out. 1774 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1775 1776 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1777 int SPFI = StackPtrFI->getIndex(); 1778 1779 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1780 StackPtr, 1781 PseudoSourceValue::getFixedStack(SPFI), 0, 1782 Node->getValueType(0).getVectorElementType(), 1783 false, false, 0); 1784 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1785 PseudoSourceValue::getFixedStack(SPFI), 0, 1786 false, false, 0); 1787} 1788 1789 1790/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1791/// support the operation, but do support the resultant vector type. 1792SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1793 unsigned NumElems = Node->getNumOperands(); 1794 SDValue Value1, Value2; 1795 DebugLoc dl = Node->getDebugLoc(); 1796 EVT VT = Node->getValueType(0); 1797 EVT OpVT = Node->getOperand(0).getValueType(); 1798 EVT EltVT = VT.getVectorElementType(); 1799 1800 // If the only non-undef value is the low element, turn this into a 1801 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1802 bool isOnlyLowElement = true; 1803 bool MoreThanTwoValues = false; 1804 bool isConstant = true; 1805 for (unsigned i = 0; i < NumElems; ++i) { 1806 SDValue V = Node->getOperand(i); 1807 if (V.getOpcode() == ISD::UNDEF) 1808 continue; 1809 if (i > 0) 1810 isOnlyLowElement = false; 1811 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1812 isConstant = false; 1813 1814 if (!Value1.getNode()) { 1815 Value1 = V; 1816 } else if (!Value2.getNode()) { 1817 if (V != Value1) 1818 Value2 = V; 1819 } else if (V != Value1 && V != Value2) { 1820 MoreThanTwoValues = true; 1821 } 1822 } 1823 1824 if (!Value1.getNode()) 1825 return DAG.getUNDEF(VT); 1826 1827 if (isOnlyLowElement) 1828 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1829 1830 // If all elements are constants, create a load from the constant pool. 1831 if (isConstant) { 1832 std::vector<Constant*> CV; 1833 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1834 if (ConstantFPSDNode *V = 1835 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1836 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1837 } else if (ConstantSDNode *V = 1838 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1839 if (OpVT==EltVT) 1840 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1841 else { 1842 // If OpVT and EltVT don't match, EltVT is not legal and the 1843 // element values have been promoted/truncated earlier. Undo this; 1844 // we don't want a v16i8 to become a v16i32 for example. 1845 const ConstantInt *CI = V->getConstantIntValue(); 1846 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1847 CI->getZExtValue())); 1848 } 1849 } else { 1850 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1851 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1852 CV.push_back(UndefValue::get(OpNTy)); 1853 } 1854 } 1855 Constant *CP = ConstantVector::get(CV); 1856 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1857 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1858 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1859 PseudoSourceValue::getConstantPool(), 0, 1860 false, false, Alignment); 1861 } 1862 1863 if (!MoreThanTwoValues) { 1864 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1865 for (unsigned i = 0; i < NumElems; ++i) { 1866 SDValue V = Node->getOperand(i); 1867 if (V.getOpcode() == ISD::UNDEF) 1868 continue; 1869 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1870 } 1871 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1872 // Get the splatted value into the low element of a vector register. 1873 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1874 SDValue Vec2; 1875 if (Value2.getNode()) 1876 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1877 else 1878 Vec2 = DAG.getUNDEF(VT); 1879 1880 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1881 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1882 } 1883 } 1884 1885 // Otherwise, we can't handle this case efficiently. 1886 return ExpandVectorBuildThroughStack(Node); 1887} 1888 1889// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1890// does not fit into a register, return the lo part and set the hi part to the 1891// by-reg argument. If it does fit into a single register, return the result 1892// and leave the Hi part unset. 1893SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1894 bool isSigned) { 1895 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1896 // The input chain to this libcall is the entry node of the function. 1897 // Legalizing the call will automatically add the previous call to the 1898 // dependence. 1899 SDValue InChain = DAG.getEntryNode(); 1900 1901 TargetLowering::ArgListTy Args; 1902 TargetLowering::ArgListEntry Entry; 1903 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1904 EVT ArgVT = Node->getOperand(i).getValueType(); 1905 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1906 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1907 Entry.isSExt = isSigned; 1908 Entry.isZExt = !isSigned; 1909 Args.push_back(Entry); 1910 } 1911 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1912 TLI.getPointerTy()); 1913 1914 // Splice the libcall in wherever FindInputOutputChains tells us to. 1915 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1916 std::pair<SDValue, SDValue> CallInfo = 1917 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1918 0, TLI.getLibcallCallingConv(LC), false, 1919 /*isReturnValueUsed=*/true, 1920 Callee, Args, DAG, Node->getDebugLoc()); 1921 1922 // Legalize the call sequence, starting with the chain. This will advance 1923 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1924 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1925 LegalizeOp(CallInfo.second); 1926 return CallInfo.first; 1927} 1928 1929SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 1930 RTLIB::Libcall Call_F32, 1931 RTLIB::Libcall Call_F64, 1932 RTLIB::Libcall Call_F80, 1933 RTLIB::Libcall Call_PPCF128) { 1934 RTLIB::Libcall LC; 1935 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1936 default: llvm_unreachable("Unexpected request for libcall!"); 1937 case MVT::f32: LC = Call_F32; break; 1938 case MVT::f64: LC = Call_F64; break; 1939 case MVT::f80: LC = Call_F80; break; 1940 case MVT::ppcf128: LC = Call_PPCF128; break; 1941 } 1942 return ExpandLibCall(LC, Node, false); 1943} 1944 1945SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 1946 RTLIB::Libcall Call_I8, 1947 RTLIB::Libcall Call_I16, 1948 RTLIB::Libcall Call_I32, 1949 RTLIB::Libcall Call_I64, 1950 RTLIB::Libcall Call_I128) { 1951 RTLIB::Libcall LC; 1952 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1953 default: llvm_unreachable("Unexpected request for libcall!"); 1954 case MVT::i8: LC = Call_I8; break; 1955 case MVT::i16: LC = Call_I16; break; 1956 case MVT::i32: LC = Call_I32; break; 1957 case MVT::i64: LC = Call_I64; break; 1958 case MVT::i128: LC = Call_I128; break; 1959 } 1960 return ExpandLibCall(LC, Node, isSigned); 1961} 1962 1963/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 1964/// INT_TO_FP operation of the specified operand when the target requests that 1965/// we expand it. At this point, we know that the result and operand types are 1966/// legal for the target. 1967SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 1968 SDValue Op0, 1969 EVT DestVT, 1970 DebugLoc dl) { 1971 if (Op0.getValueType() == MVT::i32) { 1972 // simple 32-bit [signed|unsigned] integer to float/double expansion 1973 1974 // Get the stack frame index of a 8 byte buffer. 1975 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 1976 1977 // word offset constant for Hi/Lo address computation 1978 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 1979 // set up Hi and Lo (into buffer) address based on endian 1980 SDValue Hi = StackSlot; 1981 SDValue Lo = DAG.getNode(ISD::ADD, dl, 1982 TLI.getPointerTy(), StackSlot, WordOff); 1983 if (TLI.isLittleEndian()) 1984 std::swap(Hi, Lo); 1985 1986 // if signed map to unsigned space 1987 SDValue Op0Mapped; 1988 if (isSigned) { 1989 // constant used to invert sign bit (signed to unsigned mapping) 1990 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 1991 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 1992 } else { 1993 Op0Mapped = Op0; 1994 } 1995 // store the lo of the constructed double - based on integer input 1996 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 1997 Op0Mapped, Lo, NULL, 0, 1998 false, false, 0); 1999 // initial hi portion of constructed double 2000 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 2001 // store the hi of the constructed double - biased exponent 2002 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0, 2003 false, false, 0); 2004 // load the constructed double 2005 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0, 2006 false, false, 0); 2007 // FP constant to bias correct the final result 2008 SDValue Bias = DAG.getConstantFP(isSigned ? 2009 BitsToDouble(0x4330000080000000ULL) : 2010 BitsToDouble(0x4330000000000000ULL), 2011 MVT::f64); 2012 // subtract the bias 2013 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2014 // final result 2015 SDValue Result; 2016 // handle final rounding 2017 if (DestVT == MVT::f64) { 2018 // do nothing 2019 Result = Sub; 2020 } else if (DestVT.bitsLT(MVT::f64)) { 2021 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2022 DAG.getIntPtrConstant(0)); 2023 } else if (DestVT.bitsGT(MVT::f64)) { 2024 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2025 } 2026 return Result; 2027 } 2028 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2029 2030 // Implementation of unsigned i64 to f64 following the algorithm in 2031 // __floatundidf in compiler_rt. This implementation has the advantage 2032 // of performing rounding correctly, both in the default rounding mode 2033 // and in all alternate rounding modes. 2034 // TODO: Generalize this for use with other types. 2035 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2036 SDValue TwoP52 = 2037 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2038 SDValue TwoP84PlusTwoP52 = 2039 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2040 SDValue TwoP84 = 2041 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2042 2043 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2044 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2045 DAG.getConstant(32, MVT::i64)); 2046 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2047 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2048 SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr); 2049 SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr); 2050 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, TwoP84PlusTwoP52); 2051 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2052 } 2053 2054 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2055 2056 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2057 Op0, DAG.getConstant(0, Op0.getValueType()), 2058 ISD::SETLT); 2059 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2060 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2061 SignSet, Four, Zero); 2062 2063 // If the sign bit of the integer is set, the large number will be treated 2064 // as a negative number. To counteract this, the dynamic code adds an 2065 // offset depending on the data type. 2066 uint64_t FF; 2067 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2068 default: llvm_unreachable("Unsupported integer type!"); 2069 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2070 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2071 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2072 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2073 } 2074 if (TLI.isLittleEndian()) FF <<= 32; 2075 Constant *FudgeFactor = ConstantInt::get( 2076 Type::getInt64Ty(*DAG.getContext()), FF); 2077 2078 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2079 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2080 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2081 Alignment = std::min(Alignment, 4u); 2082 SDValue FudgeInReg; 2083 if (DestVT == MVT::f32) 2084 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2085 PseudoSourceValue::getConstantPool(), 0, 2086 false, false, Alignment); 2087 else { 2088 FudgeInReg = 2089 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2090 DAG.getEntryNode(), CPIdx, 2091 PseudoSourceValue::getConstantPool(), 0, 2092 MVT::f32, false, false, Alignment)); 2093 } 2094 2095 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2096} 2097 2098/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2099/// *INT_TO_FP operation of the specified operand when the target requests that 2100/// we promote it. At this point, we know that the result and operand types are 2101/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2102/// operation that takes a larger input. 2103SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2104 EVT DestVT, 2105 bool isSigned, 2106 DebugLoc dl) { 2107 // First step, figure out the appropriate *INT_TO_FP operation to use. 2108 EVT NewInTy = LegalOp.getValueType(); 2109 2110 unsigned OpToUse = 0; 2111 2112 // Scan for the appropriate larger type to use. 2113 while (1) { 2114 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2115 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2116 2117 // If the target supports SINT_TO_FP of this type, use it. 2118 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2119 OpToUse = ISD::SINT_TO_FP; 2120 break; 2121 } 2122 if (isSigned) continue; 2123 2124 // If the target supports UINT_TO_FP of this type, use it. 2125 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2126 OpToUse = ISD::UINT_TO_FP; 2127 break; 2128 } 2129 2130 // Otherwise, try a larger type. 2131 } 2132 2133 // Okay, we found the operation and type to use. Zero extend our input to the 2134 // desired type then run the operation on it. 2135 return DAG.getNode(OpToUse, dl, DestVT, 2136 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2137 dl, NewInTy, LegalOp)); 2138} 2139 2140/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2141/// FP_TO_*INT operation of the specified operand when the target requests that 2142/// we promote it. At this point, we know that the result and operand types are 2143/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2144/// operation that returns a larger result. 2145SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2146 EVT DestVT, 2147 bool isSigned, 2148 DebugLoc dl) { 2149 // First step, figure out the appropriate FP_TO*INT operation to use. 2150 EVT NewOutTy = DestVT; 2151 2152 unsigned OpToUse = 0; 2153 2154 // Scan for the appropriate larger type to use. 2155 while (1) { 2156 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2157 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2158 2159 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2160 OpToUse = ISD::FP_TO_SINT; 2161 break; 2162 } 2163 2164 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2165 OpToUse = ISD::FP_TO_UINT; 2166 break; 2167 } 2168 2169 // Otherwise, try a larger type. 2170 } 2171 2172 2173 // Okay, we found the operation and type to use. 2174 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2175 2176 // Truncate the result of the extended FP_TO_*INT operation to the desired 2177 // size. 2178 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2179} 2180 2181/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2182/// 2183SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2184 EVT VT = Op.getValueType(); 2185 EVT SHVT = TLI.getShiftAmountTy(); 2186 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2187 switch (VT.getSimpleVT().SimpleTy) { 2188 default: llvm_unreachable("Unhandled Expand type in BSWAP!"); 2189 case MVT::i16: 2190 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2191 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2192 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2193 case MVT::i32: 2194 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2195 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2196 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2197 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2198 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2199 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2200 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2201 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2202 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2203 case MVT::i64: 2204 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2205 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2206 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2207 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2208 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2209 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2210 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2211 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2212 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2213 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2214 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2215 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2216 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2217 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2218 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2219 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2220 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2221 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2222 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2223 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2224 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2225 } 2226} 2227 2228/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2229/// 2230SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2231 DebugLoc dl) { 2232 switch (Opc) { 2233 default: llvm_unreachable("Cannot expand this yet!"); 2234 case ISD::CTPOP: { 2235 static const uint64_t mask[6] = { 2236 0x5555555555555555ULL, 0x3333333333333333ULL, 2237 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2238 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2239 }; 2240 EVT VT = Op.getValueType(); 2241 EVT ShVT = TLI.getShiftAmountTy(); 2242 unsigned len = VT.getSizeInBits(); 2243 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2244 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2245 unsigned EltSize = VT.isVector() ? 2246 VT.getVectorElementType().getSizeInBits() : len; 2247 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2248 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2249 Op = DAG.getNode(ISD::ADD, dl, VT, 2250 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2251 DAG.getNode(ISD::AND, dl, VT, 2252 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2253 Tmp2)); 2254 } 2255 return Op; 2256 } 2257 case ISD::CTLZ: { 2258 // for now, we do this: 2259 // x = x | (x >> 1); 2260 // x = x | (x >> 2); 2261 // ... 2262 // x = x | (x >>16); 2263 // x = x | (x >>32); // for 64-bit input 2264 // return popcount(~x); 2265 // 2266 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2267 EVT VT = Op.getValueType(); 2268 EVT ShVT = TLI.getShiftAmountTy(); 2269 unsigned len = VT.getSizeInBits(); 2270 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2271 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2272 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2273 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2274 } 2275 Op = DAG.getNOT(dl, Op, VT); 2276 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2277 } 2278 case ISD::CTTZ: { 2279 // for now, we use: { return popcount(~x & (x - 1)); } 2280 // unless the target has ctlz but not ctpop, in which case we use: 2281 // { return 32 - nlz(~x & (x-1)); } 2282 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2283 EVT VT = Op.getValueType(); 2284 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2285 DAG.getNOT(dl, Op, VT), 2286 DAG.getNode(ISD::SUB, dl, VT, Op, 2287 DAG.getConstant(1, VT))); 2288 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2289 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2290 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2291 return DAG.getNode(ISD::SUB, dl, VT, 2292 DAG.getConstant(VT.getSizeInBits(), VT), 2293 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2294 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2295 } 2296 } 2297} 2298 2299void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2300 SmallVectorImpl<SDValue> &Results) { 2301 DebugLoc dl = Node->getDebugLoc(); 2302 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2303 switch (Node->getOpcode()) { 2304 case ISD::CTPOP: 2305 case ISD::CTLZ: 2306 case ISD::CTTZ: 2307 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2308 Results.push_back(Tmp1); 2309 break; 2310 case ISD::BSWAP: 2311 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2312 break; 2313 case ISD::FRAMEADDR: 2314 case ISD::RETURNADDR: 2315 case ISD::FRAME_TO_ARGS_OFFSET: 2316 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2317 break; 2318 case ISD::FLT_ROUNDS_: 2319 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2320 break; 2321 case ISD::EH_RETURN: 2322 case ISD::EH_LABEL: 2323 case ISD::PREFETCH: 2324 case ISD::MEMBARRIER: 2325 case ISD::VAEND: 2326 Results.push_back(Node->getOperand(0)); 2327 break; 2328 case ISD::DYNAMIC_STACKALLOC: 2329 ExpandDYNAMIC_STACKALLOC(Node, Results); 2330 break; 2331 case ISD::MERGE_VALUES: 2332 for (unsigned i = 0; i < Node->getNumValues(); i++) 2333 Results.push_back(Node->getOperand(i)); 2334 break; 2335 case ISD::UNDEF: { 2336 EVT VT = Node->getValueType(0); 2337 if (VT.isInteger()) 2338 Results.push_back(DAG.getConstant(0, VT)); 2339 else if (VT.isFloatingPoint()) 2340 Results.push_back(DAG.getConstantFP(0, VT)); 2341 else 2342 llvm_unreachable("Unknown value type!"); 2343 break; 2344 } 2345 case ISD::TRAP: { 2346 // If this operation is not supported, lower it to 'abort()' call 2347 TargetLowering::ArgListTy Args; 2348 std::pair<SDValue, SDValue> CallResult = 2349 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2350 false, false, false, false, 0, CallingConv::C, false, 2351 /*isReturnValueUsed=*/true, 2352 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2353 Args, DAG, dl); 2354 Results.push_back(CallResult.second); 2355 break; 2356 } 2357 case ISD::FP_ROUND: 2358 case ISD::BIT_CONVERT: 2359 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2360 Node->getValueType(0), dl); 2361 Results.push_back(Tmp1); 2362 break; 2363 case ISD::FP_EXTEND: 2364 Tmp1 = EmitStackConvert(Node->getOperand(0), 2365 Node->getOperand(0).getValueType(), 2366 Node->getValueType(0), dl); 2367 Results.push_back(Tmp1); 2368 break; 2369 case ISD::SIGN_EXTEND_INREG: { 2370 // NOTE: we could fall back on load/store here too for targets without 2371 // SAR. However, it is doubtful that any exist. 2372 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2373 EVT VT = Node->getValueType(0); 2374 EVT ShiftAmountTy = TLI.getShiftAmountTy(); 2375 if (VT.isVector()) 2376 ShiftAmountTy = VT; 2377 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2378 ExtraVT.getScalarType().getSizeInBits(); 2379 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2380 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2381 Node->getOperand(0), ShiftCst); 2382 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2383 Results.push_back(Tmp1); 2384 break; 2385 } 2386 case ISD::FP_ROUND_INREG: { 2387 // The only way we can lower this is to turn it into a TRUNCSTORE, 2388 // EXTLOAD pair, targetting a temporary location (a stack slot). 2389 2390 // NOTE: there is a choice here between constantly creating new stack 2391 // slots and always reusing the same one. We currently always create 2392 // new ones, as reuse may inhibit scheduling. 2393 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2394 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2395 Node->getValueType(0), dl); 2396 Results.push_back(Tmp1); 2397 break; 2398 } 2399 case ISD::SINT_TO_FP: 2400 case ISD::UINT_TO_FP: 2401 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2402 Node->getOperand(0), Node->getValueType(0), dl); 2403 Results.push_back(Tmp1); 2404 break; 2405 case ISD::FP_TO_UINT: { 2406 SDValue True, False; 2407 EVT VT = Node->getOperand(0).getValueType(); 2408 EVT NVT = Node->getValueType(0); 2409 const uint64_t zero[] = {0, 0}; 2410 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 2411 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2412 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2413 Tmp1 = DAG.getConstantFP(apf, VT); 2414 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2415 Node->getOperand(0), 2416 Tmp1, ISD::SETLT); 2417 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2418 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2419 DAG.getNode(ISD::FSUB, dl, VT, 2420 Node->getOperand(0), Tmp1)); 2421 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2422 DAG.getConstant(x, NVT)); 2423 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2424 Results.push_back(Tmp1); 2425 break; 2426 } 2427 case ISD::VAARG: { 2428 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2429 EVT VT = Node->getValueType(0); 2430 Tmp1 = Node->getOperand(0); 2431 Tmp2 = Node->getOperand(1); 2432 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0, 2433 false, false, 0); 2434 // Increment the pointer, VAList, to the next vaarg 2435 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2436 DAG.getConstant(TLI.getTargetData()-> 2437 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2438 TLI.getPointerTy())); 2439 // Store the incremented VAList to the legalized pointer 2440 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0, 2441 false, false, 0); 2442 // Load the actual argument out of the pointer VAList 2443 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0, 2444 false, false, 0)); 2445 Results.push_back(Results[0].getValue(1)); 2446 break; 2447 } 2448 case ISD::VACOPY: { 2449 // This defaults to loading a pointer from the input and storing it to the 2450 // output, returning the chain. 2451 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2452 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2453 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2454 Node->getOperand(2), VS, 0, false, false, 0); 2455 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0, 2456 false, false, 0); 2457 Results.push_back(Tmp1); 2458 break; 2459 } 2460 case ISD::EXTRACT_VECTOR_ELT: 2461 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2462 // This must be an access of the only element. Return it. 2463 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 2464 Node->getOperand(0)); 2465 else 2466 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2467 Results.push_back(Tmp1); 2468 break; 2469 case ISD::EXTRACT_SUBVECTOR: 2470 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2471 break; 2472 case ISD::CONCAT_VECTORS: { 2473 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2474 break; 2475 } 2476 case ISD::SCALAR_TO_VECTOR: 2477 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2478 break; 2479 case ISD::INSERT_VECTOR_ELT: 2480 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2481 Node->getOperand(1), 2482 Node->getOperand(2), dl)); 2483 break; 2484 case ISD::VECTOR_SHUFFLE: { 2485 SmallVector<int, 8> Mask; 2486 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2487 2488 EVT VT = Node->getValueType(0); 2489 EVT EltVT = VT.getVectorElementType(); 2490 unsigned NumElems = VT.getVectorNumElements(); 2491 SmallVector<SDValue, 8> Ops; 2492 for (unsigned i = 0; i != NumElems; ++i) { 2493 if (Mask[i] < 0) { 2494 Ops.push_back(DAG.getUNDEF(EltVT)); 2495 continue; 2496 } 2497 unsigned Idx = Mask[i]; 2498 if (Idx < NumElems) 2499 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2500 Node->getOperand(0), 2501 DAG.getIntPtrConstant(Idx))); 2502 else 2503 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2504 Node->getOperand(1), 2505 DAG.getIntPtrConstant(Idx - NumElems))); 2506 } 2507 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2508 Results.push_back(Tmp1); 2509 break; 2510 } 2511 case ISD::EXTRACT_ELEMENT: { 2512 EVT OpTy = Node->getOperand(0).getValueType(); 2513 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2514 // 1 -> Hi 2515 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2516 DAG.getConstant(OpTy.getSizeInBits()/2, 2517 TLI.getShiftAmountTy())); 2518 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2519 } else { 2520 // 0 -> Lo 2521 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2522 Node->getOperand(0)); 2523 } 2524 Results.push_back(Tmp1); 2525 break; 2526 } 2527 case ISD::STACKSAVE: 2528 // Expand to CopyFromReg if the target set 2529 // StackPointerRegisterToSaveRestore. 2530 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2531 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2532 Node->getValueType(0))); 2533 Results.push_back(Results[0].getValue(1)); 2534 } else { 2535 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2536 Results.push_back(Node->getOperand(0)); 2537 } 2538 break; 2539 case ISD::STACKRESTORE: 2540 // Expand to CopyToReg if the target set 2541 // StackPointerRegisterToSaveRestore. 2542 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2543 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2544 Node->getOperand(1))); 2545 } else { 2546 Results.push_back(Node->getOperand(0)); 2547 } 2548 break; 2549 case ISD::FCOPYSIGN: 2550 Results.push_back(ExpandFCOPYSIGN(Node)); 2551 break; 2552 case ISD::FNEG: 2553 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2554 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2555 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2556 Node->getOperand(0)); 2557 Results.push_back(Tmp1); 2558 break; 2559 case ISD::FABS: { 2560 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2561 EVT VT = Node->getValueType(0); 2562 Tmp1 = Node->getOperand(0); 2563 Tmp2 = DAG.getConstantFP(0.0, VT); 2564 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2565 Tmp1, Tmp2, ISD::SETUGT); 2566 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2567 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2568 Results.push_back(Tmp1); 2569 break; 2570 } 2571 case ISD::FSQRT: 2572 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2573 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2574 break; 2575 case ISD::FSIN: 2576 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2577 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2578 break; 2579 case ISD::FCOS: 2580 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2581 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2582 break; 2583 case ISD::FLOG: 2584 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2585 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2586 break; 2587 case ISD::FLOG2: 2588 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2589 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2590 break; 2591 case ISD::FLOG10: 2592 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2593 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2594 break; 2595 case ISD::FEXP: 2596 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2597 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2598 break; 2599 case ISD::FEXP2: 2600 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2601 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2602 break; 2603 case ISD::FTRUNC: 2604 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2605 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2606 break; 2607 case ISD::FFLOOR: 2608 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2609 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2610 break; 2611 case ISD::FCEIL: 2612 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2613 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2614 break; 2615 case ISD::FRINT: 2616 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2617 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2618 break; 2619 case ISD::FNEARBYINT: 2620 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2621 RTLIB::NEARBYINT_F64, 2622 RTLIB::NEARBYINT_F80, 2623 RTLIB::NEARBYINT_PPCF128)); 2624 break; 2625 case ISD::FPOWI: 2626 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2627 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2628 break; 2629 case ISD::FPOW: 2630 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 2631 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 2632 break; 2633 case ISD::FDIV: 2634 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 2635 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 2636 break; 2637 case ISD::FREM: 2638 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 2639 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 2640 break; 2641 case ISD::FP16_TO_FP32: 2642 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 2643 break; 2644 case ISD::FP32_TO_FP16: 2645 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 2646 break; 2647 case ISD::ConstantFP: { 2648 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 2649 // Check to see if this FP immediate is already legal. 2650 // If this is a legal constant, turn it into a TargetConstantFP node. 2651 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 2652 Results.push_back(SDValue(Node, 0)); 2653 else 2654 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 2655 break; 2656 } 2657 case ISD::EHSELECTION: { 2658 unsigned Reg = TLI.getExceptionSelectorRegister(); 2659 assert(Reg && "Can't expand to unknown register!"); 2660 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 2661 Node->getValueType(0))); 2662 Results.push_back(Results[0].getValue(1)); 2663 break; 2664 } 2665 case ISD::EXCEPTIONADDR: { 2666 unsigned Reg = TLI.getExceptionAddressRegister(); 2667 assert(Reg && "Can't expand to unknown register!"); 2668 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 2669 Node->getValueType(0))); 2670 Results.push_back(Results[0].getValue(1)); 2671 break; 2672 } 2673 case ISD::SUB: { 2674 EVT VT = Node->getValueType(0); 2675 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 2676 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 2677 "Don't know how to expand this subtraction!"); 2678 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 2679 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 2680 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 2681 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 2682 break; 2683 } 2684 case ISD::UREM: 2685 case ISD::SREM: { 2686 EVT VT = Node->getValueType(0); 2687 SDVTList VTs = DAG.getVTList(VT, VT); 2688 bool isSigned = Node->getOpcode() == ISD::SREM; 2689 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 2690 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2691 Tmp2 = Node->getOperand(0); 2692 Tmp3 = Node->getOperand(1); 2693 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 2694 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 2695 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 2696 // X % Y -> X-X/Y*Y 2697 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 2698 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 2699 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 2700 } else if (isSigned) { 2701 Tmp1 = ExpandIntLibCall(Node, true, 2702 RTLIB::SREM_I8, 2703 RTLIB::SREM_I16, RTLIB::SREM_I32, 2704 RTLIB::SREM_I64, RTLIB::SREM_I128); 2705 } else { 2706 Tmp1 = ExpandIntLibCall(Node, false, 2707 RTLIB::UREM_I8, 2708 RTLIB::UREM_I16, RTLIB::UREM_I32, 2709 RTLIB::UREM_I64, RTLIB::UREM_I128); 2710 } 2711 Results.push_back(Tmp1); 2712 break; 2713 } 2714 case ISD::UDIV: 2715 case ISD::SDIV: { 2716 bool isSigned = Node->getOpcode() == ISD::SDIV; 2717 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2718 EVT VT = Node->getValueType(0); 2719 SDVTList VTs = DAG.getVTList(VT, VT); 2720 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 2721 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 2722 Node->getOperand(1)); 2723 else if (isSigned) 2724 Tmp1 = ExpandIntLibCall(Node, true, 2725 RTLIB::SDIV_I8, 2726 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 2727 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 2728 else 2729 Tmp1 = ExpandIntLibCall(Node, false, 2730 RTLIB::UDIV_I8, 2731 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 2732 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 2733 Results.push_back(Tmp1); 2734 break; 2735 } 2736 case ISD::MULHU: 2737 case ISD::MULHS: { 2738 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 2739 ISD::SMUL_LOHI; 2740 EVT VT = Node->getValueType(0); 2741 SDVTList VTs = DAG.getVTList(VT, VT); 2742 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 2743 "If this wasn't legal, it shouldn't have been created!"); 2744 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 2745 Node->getOperand(1)); 2746 Results.push_back(Tmp1.getValue(1)); 2747 break; 2748 } 2749 case ISD::MUL: { 2750 EVT VT = Node->getValueType(0); 2751 SDVTList VTs = DAG.getVTList(VT, VT); 2752 // See if multiply or divide can be lowered using two-result operations. 2753 // We just need the low half of the multiply; try both the signed 2754 // and unsigned forms. If the target supports both SMUL_LOHI and 2755 // UMUL_LOHI, form a preference by checking which forms of plain 2756 // MULH it supports. 2757 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 2758 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 2759 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 2760 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 2761 unsigned OpToUse = 0; 2762 if (HasSMUL_LOHI && !HasMULHS) { 2763 OpToUse = ISD::SMUL_LOHI; 2764 } else if (HasUMUL_LOHI && !HasMULHU) { 2765 OpToUse = ISD::UMUL_LOHI; 2766 } else if (HasSMUL_LOHI) { 2767 OpToUse = ISD::SMUL_LOHI; 2768 } else if (HasUMUL_LOHI) { 2769 OpToUse = ISD::UMUL_LOHI; 2770 } 2771 if (OpToUse) { 2772 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 2773 Node->getOperand(1))); 2774 break; 2775 } 2776 Tmp1 = ExpandIntLibCall(Node, false, 2777 RTLIB::MUL_I8, 2778 RTLIB::MUL_I16, RTLIB::MUL_I32, 2779 RTLIB::MUL_I64, RTLIB::MUL_I128); 2780 Results.push_back(Tmp1); 2781 break; 2782 } 2783 case ISD::SADDO: 2784 case ISD::SSUBO: { 2785 SDValue LHS = Node->getOperand(0); 2786 SDValue RHS = Node->getOperand(1); 2787 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 2788 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2789 LHS, RHS); 2790 Results.push_back(Sum); 2791 EVT OType = Node->getValueType(1); 2792 2793 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 2794 2795 // LHSSign -> LHS >= 0 2796 // RHSSign -> RHS >= 0 2797 // SumSign -> Sum >= 0 2798 // 2799 // Add: 2800 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 2801 // Sub: 2802 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 2803 // 2804 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 2805 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 2806 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 2807 Node->getOpcode() == ISD::SADDO ? 2808 ISD::SETEQ : ISD::SETNE); 2809 2810 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 2811 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 2812 2813 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 2814 Results.push_back(Cmp); 2815 break; 2816 } 2817 case ISD::UADDO: 2818 case ISD::USUBO: { 2819 SDValue LHS = Node->getOperand(0); 2820 SDValue RHS = Node->getOperand(1); 2821 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 2822 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2823 LHS, RHS); 2824 Results.push_back(Sum); 2825 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 2826 Node->getOpcode () == ISD::UADDO ? 2827 ISD::SETULT : ISD::SETUGT)); 2828 break; 2829 } 2830 case ISD::UMULO: 2831 case ISD::SMULO: { 2832 EVT VT = Node->getValueType(0); 2833 SDValue LHS = Node->getOperand(0); 2834 SDValue RHS = Node->getOperand(1); 2835 SDValue BottomHalf; 2836 SDValue TopHalf; 2837 static const unsigned Ops[2][3] = 2838 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 2839 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 2840 bool isSigned = Node->getOpcode() == ISD::SMULO; 2841 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 2842 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 2843 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 2844 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 2845 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 2846 RHS); 2847 TopHalf = BottomHalf.getValue(1); 2848 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2))) { 2849 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 2850 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 2851 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 2852 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 2853 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2854 DAG.getIntPtrConstant(0)); 2855 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2856 DAG.getIntPtrConstant(1)); 2857 } else { 2858 // FIXME: We should be able to fall back to a libcall with an illegal 2859 // type in some cases. 2860 // Also, we can fall back to a division in some cases, but that's a big 2861 // performance hit in the general case. 2862 llvm_unreachable("Don't know how to expand this operation yet!"); 2863 } 2864 if (isSigned) { 2865 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); 2866 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 2867 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 2868 ISD::SETNE); 2869 } else { 2870 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 2871 DAG.getConstant(0, VT), ISD::SETNE); 2872 } 2873 Results.push_back(BottomHalf); 2874 Results.push_back(TopHalf); 2875 break; 2876 } 2877 case ISD::BUILD_PAIR: { 2878 EVT PairTy = Node->getValueType(0); 2879 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 2880 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 2881 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 2882 DAG.getConstant(PairTy.getSizeInBits()/2, 2883 TLI.getShiftAmountTy())); 2884 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 2885 break; 2886 } 2887 case ISD::SELECT: 2888 Tmp1 = Node->getOperand(0); 2889 Tmp2 = Node->getOperand(1); 2890 Tmp3 = Node->getOperand(2); 2891 if (Tmp1.getOpcode() == ISD::SETCC) { 2892 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 2893 Tmp2, Tmp3, 2894 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2895 } else { 2896 Tmp1 = DAG.getSelectCC(dl, Tmp1, 2897 DAG.getConstant(0, Tmp1.getValueType()), 2898 Tmp2, Tmp3, ISD::SETNE); 2899 } 2900 Results.push_back(Tmp1); 2901 break; 2902 case ISD::BR_JT: { 2903 SDValue Chain = Node->getOperand(0); 2904 SDValue Table = Node->getOperand(1); 2905 SDValue Index = Node->getOperand(2); 2906 2907 EVT PTy = TLI.getPointerTy(); 2908 2909 const TargetData &TD = *TLI.getTargetData(); 2910 unsigned EntrySize = 2911 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 2912 2913 Index = DAG.getNode(ISD::MUL, dl, PTy, 2914 Index, DAG.getConstant(EntrySize, PTy)); 2915 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2916 2917 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 2918 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 2919 PseudoSourceValue::getJumpTable(), 0, MemVT, 2920 false, false, 0); 2921 Addr = LD; 2922 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2923 // For PIC, the sequence is: 2924 // BRIND(load(Jumptable + index) + RelocBase) 2925 // RelocBase can be JumpTable, GOT or some sort of global base. 2926 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 2927 TLI.getPICJumpTableRelocBase(Table, DAG)); 2928 } 2929 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 2930 Results.push_back(Tmp1); 2931 break; 2932 } 2933 case ISD::BRCOND: 2934 // Expand brcond's setcc into its constituent parts and create a BR_CC 2935 // Node. 2936 Tmp1 = Node->getOperand(0); 2937 Tmp2 = Node->getOperand(1); 2938 if (Tmp2.getOpcode() == ISD::SETCC) { 2939 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 2940 Tmp1, Tmp2.getOperand(2), 2941 Tmp2.getOperand(0), Tmp2.getOperand(1), 2942 Node->getOperand(2)); 2943 } else { 2944 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 2945 DAG.getCondCode(ISD::SETNE), Tmp2, 2946 DAG.getConstant(0, Tmp2.getValueType()), 2947 Node->getOperand(2)); 2948 } 2949 Results.push_back(Tmp1); 2950 break; 2951 case ISD::SETCC: { 2952 Tmp1 = Node->getOperand(0); 2953 Tmp2 = Node->getOperand(1); 2954 Tmp3 = Node->getOperand(2); 2955 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 2956 2957 // If we expanded the SETCC into an AND/OR, return the new node 2958 if (Tmp2.getNode() == 0) { 2959 Results.push_back(Tmp1); 2960 break; 2961 } 2962 2963 // Otherwise, SETCC for the given comparison type must be completely 2964 // illegal; expand it into a SELECT_CC. 2965 EVT VT = Node->getValueType(0); 2966 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 2967 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 2968 Results.push_back(Tmp1); 2969 break; 2970 } 2971 case ISD::SELECT_CC: { 2972 Tmp1 = Node->getOperand(0); // LHS 2973 Tmp2 = Node->getOperand(1); // RHS 2974 Tmp3 = Node->getOperand(2); // True 2975 Tmp4 = Node->getOperand(3); // False 2976 SDValue CC = Node->getOperand(4); 2977 2978 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 2979 Tmp1, Tmp2, CC, dl); 2980 2981 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 2982 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2983 CC = DAG.getCondCode(ISD::SETNE); 2984 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 2985 Tmp3, Tmp4, CC); 2986 Results.push_back(Tmp1); 2987 break; 2988 } 2989 case ISD::BR_CC: { 2990 Tmp1 = Node->getOperand(0); // Chain 2991 Tmp2 = Node->getOperand(2); // LHS 2992 Tmp3 = Node->getOperand(3); // RHS 2993 Tmp4 = Node->getOperand(1); // CC 2994 2995 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 2996 Tmp2, Tmp3, Tmp4, dl); 2997 LastCALLSEQ_END = DAG.getEntryNode(); 2998 2999 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 3000 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 3001 Tmp4 = DAG.getCondCode(ISD::SETNE); 3002 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 3003 Tmp3, Node->getOperand(4)); 3004 Results.push_back(Tmp1); 3005 break; 3006 } 3007 case ISD::GLOBAL_OFFSET_TABLE: 3008 case ISD::GlobalAddress: 3009 case ISD::GlobalTLSAddress: 3010 case ISD::ExternalSymbol: 3011 case ISD::ConstantPool: 3012 case ISD::JumpTable: 3013 case ISD::INTRINSIC_W_CHAIN: 3014 case ISD::INTRINSIC_WO_CHAIN: 3015 case ISD::INTRINSIC_VOID: 3016 // FIXME: Custom lowering for these operations shouldn't return null! 3017 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3018 Results.push_back(SDValue(Node, i)); 3019 break; 3020 } 3021} 3022void SelectionDAGLegalize::PromoteNode(SDNode *Node, 3023 SmallVectorImpl<SDValue> &Results) { 3024 EVT OVT = Node->getValueType(0); 3025 if (Node->getOpcode() == ISD::UINT_TO_FP || 3026 Node->getOpcode() == ISD::SINT_TO_FP || 3027 Node->getOpcode() == ISD::SETCC) { 3028 OVT = Node->getOperand(0).getValueType(); 3029 } 3030 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3031 DebugLoc dl = Node->getDebugLoc(); 3032 SDValue Tmp1, Tmp2, Tmp3; 3033 switch (Node->getOpcode()) { 3034 case ISD::CTTZ: 3035 case ISD::CTLZ: 3036 case ISD::CTPOP: 3037 // Zero extend the argument. 3038 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3039 // Perform the larger operation. 3040 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3041 if (Node->getOpcode() == ISD::CTTZ) { 3042 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3043 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 3044 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3045 ISD::SETEQ); 3046 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3047 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3048 } else if (Node->getOpcode() == ISD::CTLZ) { 3049 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3050 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3051 DAG.getConstant(NVT.getSizeInBits() - 3052 OVT.getSizeInBits(), NVT)); 3053 } 3054 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3055 break; 3056 case ISD::BSWAP: { 3057 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3058 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3059 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3060 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3061 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3062 Results.push_back(Tmp1); 3063 break; 3064 } 3065 case ISD::FP_TO_UINT: 3066 case ISD::FP_TO_SINT: 3067 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3068 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3069 Results.push_back(Tmp1); 3070 break; 3071 case ISD::UINT_TO_FP: 3072 case ISD::SINT_TO_FP: 3073 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3074 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3075 Results.push_back(Tmp1); 3076 break; 3077 case ISD::AND: 3078 case ISD::OR: 3079 case ISD::XOR: { 3080 unsigned ExtOp, TruncOp; 3081 if (OVT.isVector()) { 3082 ExtOp = ISD::BIT_CONVERT; 3083 TruncOp = ISD::BIT_CONVERT; 3084 } else if (OVT.isInteger()) { 3085 ExtOp = ISD::ANY_EXTEND; 3086 TruncOp = ISD::TRUNCATE; 3087 } else { 3088 llvm_report_error("Cannot promote logic operation"); 3089 } 3090 // Promote each of the values to the new type. 3091 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3092 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3093 // Perform the larger operation, then convert back 3094 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3095 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3096 break; 3097 } 3098 case ISD::SELECT: { 3099 unsigned ExtOp, TruncOp; 3100 if (Node->getValueType(0).isVector()) { 3101 ExtOp = ISD::BIT_CONVERT; 3102 TruncOp = ISD::BIT_CONVERT; 3103 } else if (Node->getValueType(0).isInteger()) { 3104 ExtOp = ISD::ANY_EXTEND; 3105 TruncOp = ISD::TRUNCATE; 3106 } else { 3107 ExtOp = ISD::FP_EXTEND; 3108 TruncOp = ISD::FP_ROUND; 3109 } 3110 Tmp1 = Node->getOperand(0); 3111 // Promote each of the values to the new type. 3112 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3113 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3114 // Perform the larger operation, then round down. 3115 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3116 if (TruncOp != ISD::FP_ROUND) 3117 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3118 else 3119 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3120 DAG.getIntPtrConstant(0)); 3121 Results.push_back(Tmp1); 3122 break; 3123 } 3124 case ISD::VECTOR_SHUFFLE: { 3125 SmallVector<int, 8> Mask; 3126 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3127 3128 // Cast the two input vectors. 3129 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3130 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3131 3132 // Convert the shuffle mask to the right # elements. 3133 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3134 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); 3135 Results.push_back(Tmp1); 3136 break; 3137 } 3138 case ISD::SETCC: { 3139 unsigned ExtOp = ISD::FP_EXTEND; 3140 if (NVT.isInteger()) { 3141 ISD::CondCode CCCode = 3142 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3143 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3144 } 3145 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3146 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3147 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3148 Tmp1, Tmp2, Node->getOperand(2))); 3149 break; 3150 } 3151 } 3152} 3153 3154// SelectionDAG::Legalize - This is the entry point for the file. 3155// 3156void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) { 3157 /// run - This is the main entry point to this class. 3158 /// 3159 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3160} 3161 3162