LegalizeDAG.cpp revision 8b9430cbf64da05fcefd445f6a997260ba7fbc28
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/Analysis/DebugInfo.h" 20#include "llvm/CodeGen/PseudoSourceValue.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetOptions.h" 26#include "llvm/Target/TargetSubtarget.h" 27#include "llvm/CallingConv.h" 28#include "llvm/Constants.h" 29#include "llvm/DerivedTypes.h" 30#include "llvm/Function.h" 31#include "llvm/GlobalVariable.h" 32#include "llvm/LLVMContext.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/raw_ostream.h" 38#include "llvm/ADT/DenseMap.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/ADT/SmallPtrSet.h" 41#include <map> 42using namespace llvm; 43 44//===----------------------------------------------------------------------===// 45/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 46/// hacks on it until the target machine can handle it. This involves 47/// eliminating value sizes the machine cannot handle (promoting small sizes to 48/// large sizes or splitting up large values into small values) as well as 49/// eliminating operations the machine cannot handle. 50/// 51/// This code also does a small amount of optimization and recognition of idioms 52/// as part of its processing. For example, if a target does not support a 53/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 54/// will attempt merge setcc and brc instructions into brcc's. 55/// 56namespace { 57class SelectionDAGLegalize { 58 TargetLowering &TLI; 59 SelectionDAG &DAG; 60 CodeGenOpt::Level OptLevel; 61 62 // Libcall insertion helpers. 63 64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 65 /// legalized. We use this to ensure that calls are properly serialized 66 /// against each other, including inserted libcalls. 67 SDValue LastCALLSEQ_END; 68 69 /// IsLegalizingCall - This member is used *only* for purposes of providing 70 /// helpful assertions that a libcall isn't created while another call is 71 /// being legalized (which could lead to non-serialized call sequences). 72 bool IsLegalizingCall; 73 74 enum LegalizeAction { 75 Legal, // The target natively supports this operation. 76 Promote, // This operation should be executed in a larger type. 77 Expand // Try to expand this to other ops, otherwise use a libcall. 78 }; 79 80 /// ValueTypeActions - This is a bitvector that contains two bits for each 81 /// value type, where the two bits correspond to the LegalizeAction enum. 82 /// This can be queried with "getTypeAction(VT)". 83 TargetLowering::ValueTypeActionImpl ValueTypeActions; 84 85 /// LegalizedNodes - For nodes that are of legal width, and that have more 86 /// than one use, this map indicates what regularized operand to use. This 87 /// allows us to avoid legalizing the same thing more than once. 88 DenseMap<SDValue, SDValue> LegalizedNodes; 89 90 void AddLegalizedOperand(SDValue From, SDValue To) { 91 LegalizedNodes.insert(std::make_pair(From, To)); 92 // If someone requests legalization of the new node, return itself. 93 if (From != To) 94 LegalizedNodes.insert(std::make_pair(To, To)); 95 } 96 97public: 98 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 99 100 /// getTypeAction - Return how we should legalize values of this type, either 101 /// it is already legal or we need to expand it into multiple registers of 102 /// smaller integer type, or we need to promote it to a larger type. 103 LegalizeAction getTypeAction(EVT VT) const { 104 return 105 (LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT); 106 } 107 108 /// isTypeLegal - Return true if this type is legal on this target. 109 /// 110 bool isTypeLegal(EVT VT) const { 111 return getTypeAction(VT) == Legal; 112 } 113 114 void LegalizeDAG(); 115 116private: 117 /// LegalizeOp - We know that the specified value has a legal type. 118 /// Recursively ensure that the operands have legal types, then return the 119 /// result. 120 SDValue LegalizeOp(SDValue O); 121 122 SDValue OptimizeFloatStore(StoreSDNode *ST); 123 124 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 125 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 126 /// is necessary to spill the vector being inserted into to memory, perform 127 /// the insert there, and then read the result back. 128 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 129 SDValue Idx, DebugLoc dl); 130 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 131 SDValue Idx, DebugLoc dl); 132 133 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 134 /// performs the same shuffe in terms of order or result bytes, but on a type 135 /// whose vector element type is narrower than the original shuffle type. 136 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 137 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 138 SDValue N1, SDValue N2, 139 SmallVectorImpl<int> &Mask) const; 140 141 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 142 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 143 144 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 145 DebugLoc dl); 146 147 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 148 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 149 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 150 RTLIB::Libcall Call_PPCF128); 151 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 152 RTLIB::Libcall Call_I8, 153 RTLIB::Libcall Call_I16, 154 RTLIB::Libcall Call_I32, 155 RTLIB::Libcall Call_I64, 156 RTLIB::Libcall Call_I128); 157 158 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 159 SDValue ExpandBUILD_VECTOR(SDNode *Node); 160 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 161 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 162 SmallVectorImpl<SDValue> &Results); 163 SDValue ExpandFCOPYSIGN(SDNode *Node); 164 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 165 DebugLoc dl); 166 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 167 DebugLoc dl); 168 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 169 DebugLoc dl); 170 171 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 172 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 173 174 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 175 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 176 177 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 178 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 179}; 180} 181 182/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 183/// performs the same shuffe in terms of order or result bytes, but on a type 184/// whose vector element type is narrower than the original shuffle type. 185/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 186SDValue 187SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 188 SDValue N1, SDValue N2, 189 SmallVectorImpl<int> &Mask) const { 190 unsigned NumMaskElts = VT.getVectorNumElements(); 191 unsigned NumDestElts = NVT.getVectorNumElements(); 192 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 193 194 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 195 196 if (NumEltsGrowth == 1) 197 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 198 199 SmallVector<int, 8> NewMask; 200 for (unsigned i = 0; i != NumMaskElts; ++i) { 201 int Idx = Mask[i]; 202 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 203 if (Idx < 0) 204 NewMask.push_back(-1); 205 else 206 NewMask.push_back(Idx * NumEltsGrowth + j); 207 } 208 } 209 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 210 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 211 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 212} 213 214SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 215 CodeGenOpt::Level ol) 216 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), 217 ValueTypeActions(TLI.getValueTypeActions()) { 218 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 219 "Too many value types for ValueTypeActions to hold!"); 220} 221 222void SelectionDAGLegalize::LegalizeDAG() { 223 LastCALLSEQ_END = DAG.getEntryNode(); 224 IsLegalizingCall = false; 225 226 // The legalize process is inherently a bottom-up recursive process (users 227 // legalize their uses before themselves). Given infinite stack space, we 228 // could just start legalizing on the root and traverse the whole graph. In 229 // practice however, this causes us to run out of stack space on large basic 230 // blocks. To avoid this problem, compute an ordering of the nodes where each 231 // node is only legalized after all of its operands are legalized. 232 DAG.AssignTopologicalOrder(); 233 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 234 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 235 LegalizeOp(SDValue(I, 0)); 236 237 // Finally, it's possible the root changed. Get the new root. 238 SDValue OldRoot = DAG.getRoot(); 239 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 240 DAG.setRoot(LegalizedNodes[OldRoot]); 241 242 LegalizedNodes.clear(); 243 244 // Remove dead nodes now. 245 DAG.RemoveDeadNodes(); 246} 247 248 249/// FindCallEndFromCallStart - Given a chained node that is part of a call 250/// sequence, find the CALLSEQ_END node that terminates the call sequence. 251static SDNode *FindCallEndFromCallStart(SDNode *Node) { 252 if (Node->getOpcode() == ISD::CALLSEQ_END) 253 return Node; 254 if (Node->use_empty()) 255 return 0; // No CallSeqEnd 256 257 // The chain is usually at the end. 258 SDValue TheChain(Node, Node->getNumValues()-1); 259 if (TheChain.getValueType() != MVT::Other) { 260 // Sometimes it's at the beginning. 261 TheChain = SDValue(Node, 0); 262 if (TheChain.getValueType() != MVT::Other) { 263 // Otherwise, hunt for it. 264 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 265 if (Node->getValueType(i) == MVT::Other) { 266 TheChain = SDValue(Node, i); 267 break; 268 } 269 270 // Otherwise, we walked into a node without a chain. 271 if (TheChain.getValueType() != MVT::Other) 272 return 0; 273 } 274 } 275 276 for (SDNode::use_iterator UI = Node->use_begin(), 277 E = Node->use_end(); UI != E; ++UI) { 278 279 // Make sure to only follow users of our token chain. 280 SDNode *User = *UI; 281 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 282 if (User->getOperand(i) == TheChain) 283 if (SDNode *Result = FindCallEndFromCallStart(User)) 284 return Result; 285 } 286 return 0; 287} 288 289/// FindCallStartFromCallEnd - Given a chained node that is part of a call 290/// sequence, find the CALLSEQ_START node that initiates the call sequence. 291static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 292 assert(Node && "Didn't find callseq_start for a call??"); 293 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 294 295 assert(Node->getOperand(0).getValueType() == MVT::Other && 296 "Node doesn't have a token chain argument!"); 297 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 298} 299 300/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 301/// see if any uses can reach Dest. If no dest operands can get to dest, 302/// legalize them, legalize ourself, and return false, otherwise, return true. 303/// 304/// Keep track of the nodes we fine that actually do lead to Dest in 305/// NodesLeadingTo. This avoids retraversing them exponential number of times. 306/// 307bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 308 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 309 if (N == Dest) return true; // N certainly leads to Dest :) 310 311 // If we've already processed this node and it does lead to Dest, there is no 312 // need to reprocess it. 313 if (NodesLeadingTo.count(N)) return true; 314 315 // If the first result of this node has been already legalized, then it cannot 316 // reach N. 317 if (LegalizedNodes.count(SDValue(N, 0))) return false; 318 319 // Okay, this node has not already been legalized. Check and legalize all 320 // operands. If none lead to Dest, then we can legalize this node. 321 bool OperandsLeadToDest = false; 322 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 323 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 324 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 325 326 if (OperandsLeadToDest) { 327 NodesLeadingTo.insert(N); 328 return true; 329 } 330 331 // Okay, this node looks safe, legalize it and return false. 332 LegalizeOp(SDValue(N, 0)); 333 return false; 334} 335 336/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 337/// a load from the constant pool. 338static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 339 SelectionDAG &DAG, const TargetLowering &TLI) { 340 bool Extend = false; 341 DebugLoc dl = CFP->getDebugLoc(); 342 343 // If a FP immediate is precise when represented as a float and if the 344 // target can do an extending load from float to double, we put it into 345 // the constant pool as a float, even if it's is statically typed as a 346 // double. This shrinks FP constants and canonicalizes them for targets where 347 // an FP extending load is the same cost as a normal load (such as on the x87 348 // fp stack or PPC FP unit). 349 EVT VT = CFP->getValueType(0); 350 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 351 if (!UseCP) { 352 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 353 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 354 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 355 } 356 357 EVT OrigVT = VT; 358 EVT SVT = VT; 359 while (SVT != MVT::f32) { 360 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 361 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 362 // Only do this if the target has a native EXTLOAD instruction from 363 // smaller type. 364 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 365 TLI.ShouldShrinkFPConstant(OrigVT)) { 366 const Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 367 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 368 VT = SVT; 369 Extend = true; 370 } 371 } 372 373 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 374 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 375 if (Extend) 376 return DAG.getExtLoad(ISD::EXTLOAD, dl, 377 OrigVT, DAG.getEntryNode(), 378 CPIdx, PseudoSourceValue::getConstantPool(), 379 0, VT, false, false, Alignment); 380 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 381 PseudoSourceValue::getConstantPool(), 0, false, false, 382 Alignment); 383} 384 385/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 386static 387SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 388 const TargetLowering &TLI) { 389 SDValue Chain = ST->getChain(); 390 SDValue Ptr = ST->getBasePtr(); 391 SDValue Val = ST->getValue(); 392 EVT VT = Val.getValueType(); 393 int Alignment = ST->getAlignment(); 394 int SVOffset = ST->getSrcValueOffset(); 395 DebugLoc dl = ST->getDebugLoc(); 396 if (ST->getMemoryVT().isFloatingPoint() || 397 ST->getMemoryVT().isVector()) { 398 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 399 if (TLI.isTypeLegal(intVT)) { 400 // Expand to a bitconvert of the value to the integer type of the 401 // same size, then a (misaligned) int store. 402 // FIXME: Does not handle truncating floating point stores! 403 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 404 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 405 SVOffset, ST->isVolatile(), ST->isNonTemporal(), 406 Alignment); 407 } else { 408 // Do a (aligned) store to a stack slot, then copy from the stack slot 409 // to the final destination using (unaligned) integer loads and stores. 410 EVT StoredVT = ST->getMemoryVT(); 411 EVT RegVT = 412 TLI.getRegisterType(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), StoredVT.getSizeInBits())); 413 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 414 unsigned RegBytes = RegVT.getSizeInBits() / 8; 415 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 416 417 // Make sure the stack slot is also aligned for the register type. 418 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 419 420 // Perform the original store, only redirected to the stack slot. 421 SDValue Store = DAG.getTruncStore(Chain, dl, 422 Val, StackPtr, NULL, 0, StoredVT, 423 false, false, 0); 424 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 425 SmallVector<SDValue, 8> Stores; 426 unsigned Offset = 0; 427 428 // Do all but one copies using the full register width. 429 for (unsigned i = 1; i < NumRegs; i++) { 430 // Load one integer register's worth from the stack slot. 431 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0, 432 false, false, 0); 433 // Store it to the final location. Remember the store. 434 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 435 ST->getSrcValue(), SVOffset + Offset, 436 ST->isVolatile(), ST->isNonTemporal(), 437 MinAlign(ST->getAlignment(), Offset))); 438 // Increment the pointers. 439 Offset += RegBytes; 440 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 441 Increment); 442 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 443 } 444 445 // The last store may be partial. Do a truncating store. On big-endian 446 // machines this requires an extending load from the stack slot to ensure 447 // that the bits are in the right place. 448 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset)); 449 450 // Load from the stack slot. 451 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 452 NULL, 0, MemVT, false, false, 0); 453 454 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 455 ST->getSrcValue(), SVOffset + Offset, 456 MemVT, ST->isVolatile(), 457 ST->isNonTemporal(), 458 MinAlign(ST->getAlignment(), Offset))); 459 // The order of the stores doesn't matter - say it with a TokenFactor. 460 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 461 Stores.size()); 462 } 463 } 464 assert(ST->getMemoryVT().isInteger() && 465 !ST->getMemoryVT().isVector() && 466 "Unaligned store of unknown type."); 467 // Get the half-size VT 468 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 469 int NumBits = NewStoredVT.getSizeInBits(); 470 int IncrementSize = NumBits / 8; 471 472 // Divide the stored value in two parts. 473 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 474 SDValue Lo = Val; 475 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 476 477 // Store the two parts 478 SDValue Store1, Store2; 479 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 480 ST->getSrcValue(), SVOffset, NewStoredVT, 481 ST->isVolatile(), ST->isNonTemporal(), Alignment); 482 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 483 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 484 Alignment = MinAlign(Alignment, IncrementSize); 485 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 486 ST->getSrcValue(), SVOffset + IncrementSize, 487 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 488 Alignment); 489 490 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 491} 492 493/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 494static 495SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 496 const TargetLowering &TLI) { 497 int SVOffset = LD->getSrcValueOffset(); 498 SDValue Chain = LD->getChain(); 499 SDValue Ptr = LD->getBasePtr(); 500 EVT VT = LD->getValueType(0); 501 EVT LoadedVT = LD->getMemoryVT(); 502 DebugLoc dl = LD->getDebugLoc(); 503 if (VT.isFloatingPoint() || VT.isVector()) { 504 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 505 if (TLI.isTypeLegal(intVT)) { 506 // Expand to a (misaligned) integer load of the same size, 507 // then bitconvert to floating point or vector. 508 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 509 SVOffset, LD->isVolatile(), 510 LD->isNonTemporal(), LD->getAlignment()); 511 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 512 if (VT.isFloatingPoint() && LoadedVT != VT) 513 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 514 515 SDValue Ops[] = { Result, Chain }; 516 return DAG.getMergeValues(Ops, 2, dl); 517 } else { 518 // Copy the value to a (aligned) stack slot using (unaligned) integer 519 // loads and stores, then do a (aligned) load from the stack slot. 520 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 521 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 522 unsigned RegBytes = RegVT.getSizeInBits() / 8; 523 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 524 525 // Make sure the stack slot is also aligned for the register type. 526 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 527 528 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 529 SmallVector<SDValue, 8> Stores; 530 SDValue StackPtr = StackBase; 531 unsigned Offset = 0; 532 533 // Do all but one copies using the full register width. 534 for (unsigned i = 1; i < NumRegs; i++) { 535 // Load one integer register's worth from the original location. 536 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 537 SVOffset + Offset, LD->isVolatile(), 538 LD->isNonTemporal(), 539 MinAlign(LD->getAlignment(), Offset)); 540 // Follow the load with a store to the stack slot. Remember the store. 541 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 542 NULL, 0, false, false, 0)); 543 // Increment the pointers. 544 Offset += RegBytes; 545 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 546 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 547 Increment); 548 } 549 550 // The last copy may be partial. Do an extending load. 551 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (LoadedBytes - Offset)); 552 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 553 LD->getSrcValue(), SVOffset + Offset, 554 MemVT, LD->isVolatile(), 555 LD->isNonTemporal(), 556 MinAlign(LD->getAlignment(), Offset)); 557 // Follow the load with a store to the stack slot. Remember the store. 558 // On big-endian machines this requires a truncating store to ensure 559 // that the bits end up in the right place. 560 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 561 NULL, 0, MemVT, false, false, 0)); 562 563 // The order of the stores doesn't matter - say it with a TokenFactor. 564 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 565 Stores.size()); 566 567 // Finally, perform the original load only redirected to the stack slot. 568 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 569 NULL, 0, LoadedVT, false, false, 0); 570 571 // Callers expect a MERGE_VALUES node. 572 SDValue Ops[] = { Load, TF }; 573 return DAG.getMergeValues(Ops, 2, dl); 574 } 575 } 576 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 577 "Unaligned load of unsupported type."); 578 579 // Compute the new VT that is half the size of the old one. This is an 580 // integer MVT. 581 unsigned NumBits = LoadedVT.getSizeInBits(); 582 EVT NewLoadedVT; 583 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 584 NumBits >>= 1; 585 586 unsigned Alignment = LD->getAlignment(); 587 unsigned IncrementSize = NumBits / 8; 588 ISD::LoadExtType HiExtType = LD->getExtensionType(); 589 590 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 591 if (HiExtType == ISD::NON_EXTLOAD) 592 HiExtType = ISD::ZEXTLOAD; 593 594 // Load the value in two parts 595 SDValue Lo, Hi; 596 if (TLI.isLittleEndian()) { 597 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 598 SVOffset, NewLoadedVT, LD->isVolatile(), 599 LD->isNonTemporal(), Alignment); 600 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 601 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 602 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 603 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 604 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize)); 605 } else { 606 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 607 SVOffset, NewLoadedVT, LD->isVolatile(), 608 LD->isNonTemporal(), Alignment); 609 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 610 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 611 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 612 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 613 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize)); 614 } 615 616 // aggregate the two parts 617 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 618 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 619 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 620 621 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 622 Hi.getValue(1)); 623 624 SDValue Ops[] = { Result, TF }; 625 return DAG.getMergeValues(Ops, 2, dl); 626} 627 628/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 629/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 630/// is necessary to spill the vector being inserted into to memory, perform 631/// the insert there, and then read the result back. 632SDValue SelectionDAGLegalize:: 633PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 634 DebugLoc dl) { 635 SDValue Tmp1 = Vec; 636 SDValue Tmp2 = Val; 637 SDValue Tmp3 = Idx; 638 639 // If the target doesn't support this, we have to spill the input vector 640 // to a temporary stack slot, update the element, then reload it. This is 641 // badness. We could also load the value into a vector register (either 642 // with a "move to register" or "extload into register" instruction, then 643 // permute it into place, if the idx is a constant and if the idx is 644 // supported by the target. 645 EVT VT = Tmp1.getValueType(); 646 EVT EltVT = VT.getVectorElementType(); 647 EVT IdxVT = Tmp3.getValueType(); 648 EVT PtrVT = TLI.getPointerTy(); 649 SDValue StackPtr = DAG.CreateStackTemporary(VT); 650 651 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 652 653 // Store the vector. 654 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 655 PseudoSourceValue::getFixedStack(SPFI), 0, 656 false, false, 0); 657 658 // Truncate or zero extend offset to target pointer type. 659 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 660 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 661 // Add the offset to the index. 662 unsigned EltSize = EltVT.getSizeInBits()/8; 663 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 664 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 665 // Store the scalar value. 666 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 667 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT, 668 false, false, 0); 669 // Load the updated vector. 670 return DAG.getLoad(VT, dl, Ch, StackPtr, 671 PseudoSourceValue::getFixedStack(SPFI), 0, 672 false, false, 0); 673} 674 675 676SDValue SelectionDAGLegalize:: 677ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 678 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 679 // SCALAR_TO_VECTOR requires that the type of the value being inserted 680 // match the element type of the vector being created, except for 681 // integers in which case the inserted value can be over width. 682 EVT EltVT = Vec.getValueType().getVectorElementType(); 683 if (Val.getValueType() == EltVT || 684 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 685 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 686 Vec.getValueType(), Val); 687 688 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 689 // We generate a shuffle of InVec and ScVec, so the shuffle mask 690 // should be 0,1,2,3,4,5... with the appropriate element replaced with 691 // elt 0 of the RHS. 692 SmallVector<int, 8> ShufOps; 693 for (unsigned i = 0; i != NumElts; ++i) 694 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 695 696 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 697 &ShufOps[0]); 698 } 699 } 700 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 701} 702 703SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 704 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 705 // FIXME: We shouldn't do this for TargetConstantFP's. 706 // FIXME: move this to the DAG Combiner! Note that we can't regress due 707 // to phase ordering between legalized code and the dag combiner. This 708 // probably means that we need to integrate dag combiner and legalizer 709 // together. 710 // We generally can't do this one for long doubles. 711 SDValue Tmp1 = ST->getChain(); 712 SDValue Tmp2 = ST->getBasePtr(); 713 SDValue Tmp3; 714 int SVOffset = ST->getSrcValueOffset(); 715 unsigned Alignment = ST->getAlignment(); 716 bool isVolatile = ST->isVolatile(); 717 bool isNonTemporal = ST->isNonTemporal(); 718 DebugLoc dl = ST->getDebugLoc(); 719 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 720 if (CFP->getValueType(0) == MVT::f32 && 721 getTypeAction(MVT::i32) == Legal) { 722 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 723 bitcastToAPInt().zextOrTrunc(32), 724 MVT::i32); 725 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 726 SVOffset, isVolatile, isNonTemporal, Alignment); 727 } else if (CFP->getValueType(0) == MVT::f64) { 728 // If this target supports 64-bit registers, do a single 64-bit store. 729 if (getTypeAction(MVT::i64) == Legal) { 730 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 731 zextOrTrunc(64), MVT::i64); 732 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 733 SVOffset, isVolatile, isNonTemporal, Alignment); 734 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 735 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 736 // stores. If the target supports neither 32- nor 64-bits, this 737 // xform is certainly not worth it. 738 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 739 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 740 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 741 if (TLI.isBigEndian()) std::swap(Lo, Hi); 742 743 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 744 SVOffset, isVolatile, isNonTemporal, Alignment); 745 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 746 DAG.getIntPtrConstant(4)); 747 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 748 isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); 749 750 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 751 } 752 } 753 } 754 return SDValue(); 755} 756 757/// LegalizeOp - We know that the specified value has a legal type, and 758/// that its operands are legal. Now ensure that the operation itself 759/// is legal, recursively ensuring that the operands' operations remain 760/// legal. 761SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 762 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 763 return Op; 764 765 SDNode *Node = Op.getNode(); 766 DebugLoc dl = Node->getDebugLoc(); 767 768 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 769 assert(getTypeAction(Node->getValueType(i)) == Legal && 770 "Unexpected illegal type!"); 771 772 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 773 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 774 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 775 "Unexpected illegal type!"); 776 777 // Note that LegalizeOp may be reentered even from single-use nodes, which 778 // means that we always must cache transformed nodes. 779 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 780 if (I != LegalizedNodes.end()) return I->second; 781 782 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 783 SDValue Result = Op; 784 bool isCustom = false; 785 786 // Figure out the correct action; the way to query this varies by opcode 787 TargetLowering::LegalizeAction Action; 788 bool SimpleFinishLegalizing = true; 789 switch (Node->getOpcode()) { 790 case ISD::INTRINSIC_W_CHAIN: 791 case ISD::INTRINSIC_WO_CHAIN: 792 case ISD::INTRINSIC_VOID: 793 case ISD::VAARG: 794 case ISD::STACKSAVE: 795 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 796 break; 797 case ISD::SINT_TO_FP: 798 case ISD::UINT_TO_FP: 799 case ISD::EXTRACT_VECTOR_ELT: 800 Action = TLI.getOperationAction(Node->getOpcode(), 801 Node->getOperand(0).getValueType()); 802 break; 803 case ISD::FP_ROUND_INREG: 804 case ISD::SIGN_EXTEND_INREG: { 805 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 806 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 807 break; 808 } 809 case ISD::SELECT_CC: 810 case ISD::SETCC: 811 case ISD::BR_CC: { 812 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 813 Node->getOpcode() == ISD::SETCC ? 2 : 1; 814 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 815 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 816 ISD::CondCode CCCode = 817 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 818 Action = TLI.getCondCodeAction(CCCode, OpVT); 819 if (Action == TargetLowering::Legal) { 820 if (Node->getOpcode() == ISD::SELECT_CC) 821 Action = TLI.getOperationAction(Node->getOpcode(), 822 Node->getValueType(0)); 823 else 824 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 825 } 826 break; 827 } 828 case ISD::LOAD: 829 case ISD::STORE: 830 // FIXME: Model these properly. LOAD and STORE are complicated, and 831 // STORE expects the unlegalized operand in some cases. 832 SimpleFinishLegalizing = false; 833 break; 834 case ISD::CALLSEQ_START: 835 case ISD::CALLSEQ_END: 836 // FIXME: This shouldn't be necessary. These nodes have special properties 837 // dealing with the recursive nature of legalization. Removing this 838 // special case should be done as part of making LegalizeDAG non-recursive. 839 SimpleFinishLegalizing = false; 840 break; 841 case ISD::EXTRACT_ELEMENT: 842 case ISD::FLT_ROUNDS_: 843 case ISD::SADDO: 844 case ISD::SSUBO: 845 case ISD::UADDO: 846 case ISD::USUBO: 847 case ISD::SMULO: 848 case ISD::UMULO: 849 case ISD::FPOWI: 850 case ISD::MERGE_VALUES: 851 case ISD::EH_RETURN: 852 case ISD::FRAME_TO_ARGS_OFFSET: 853 // These operations lie about being legal: when they claim to be legal, 854 // they should actually be expanded. 855 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 856 if (Action == TargetLowering::Legal) 857 Action = TargetLowering::Expand; 858 break; 859 case ISD::TRAMPOLINE: 860 case ISD::FRAMEADDR: 861 case ISD::RETURNADDR: 862 // These operations lie about being legal: when they claim to be legal, 863 // they should actually be custom-lowered. 864 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 865 if (Action == TargetLowering::Legal) 866 Action = TargetLowering::Custom; 867 break; 868 case ISD::BUILD_VECTOR: 869 // A weird case: legalization for BUILD_VECTOR never legalizes the 870 // operands! 871 // FIXME: This really sucks... changing it isn't semantically incorrect, 872 // but it massively pessimizes the code for floating-point BUILD_VECTORs 873 // because ConstantFP operands get legalized into constant pool loads 874 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 875 // though, because BUILD_VECTORS usually get lowered into other nodes 876 // which get legalized properly. 877 SimpleFinishLegalizing = false; 878 break; 879 default: 880 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 881 Action = TargetLowering::Legal; 882 } else { 883 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 884 } 885 break; 886 } 887 888 if (SimpleFinishLegalizing) { 889 SmallVector<SDValue, 8> Ops, ResultVals; 890 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 891 Ops.push_back(LegalizeOp(Node->getOperand(i))); 892 switch (Node->getOpcode()) { 893 default: break; 894 case ISD::BR: 895 case ISD::BRIND: 896 case ISD::BR_JT: 897 case ISD::BR_CC: 898 case ISD::BRCOND: 899 // Branches tweak the chain to include LastCALLSEQ_END 900 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 901 LastCALLSEQ_END); 902 Ops[0] = LegalizeOp(Ops[0]); 903 LastCALLSEQ_END = DAG.getEntryNode(); 904 break; 905 case ISD::SHL: 906 case ISD::SRL: 907 case ISD::SRA: 908 case ISD::ROTL: 909 case ISD::ROTR: 910 // Legalizing shifts/rotates requires adjusting the shift amount 911 // to the appropriate width. 912 if (!Ops[1].getValueType().isVector()) 913 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 914 break; 915 case ISD::SRL_PARTS: 916 case ISD::SRA_PARTS: 917 case ISD::SHL_PARTS: 918 // Legalizing shifts/rotates requires adjusting the shift amount 919 // to the appropriate width. 920 if (!Ops[2].getValueType().isVector()) 921 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2])); 922 break; 923 } 924 925 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(), 926 Ops.size()); 927 switch (Action) { 928 case TargetLowering::Legal: 929 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 930 ResultVals.push_back(Result.getValue(i)); 931 break; 932 case TargetLowering::Custom: 933 // FIXME: The handling for custom lowering with multiple results is 934 // a complete mess. 935 Tmp1 = TLI.LowerOperation(Result, DAG); 936 if (Tmp1.getNode()) { 937 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 938 if (e == 1) 939 ResultVals.push_back(Tmp1); 940 else 941 ResultVals.push_back(Tmp1.getValue(i)); 942 } 943 break; 944 } 945 946 // FALL THROUGH 947 case TargetLowering::Expand: 948 ExpandNode(Result.getNode(), ResultVals); 949 break; 950 case TargetLowering::Promote: 951 PromoteNode(Result.getNode(), ResultVals); 952 break; 953 } 954 if (!ResultVals.empty()) { 955 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 956 if (ResultVals[i] != SDValue(Node, i)) 957 ResultVals[i] = LegalizeOp(ResultVals[i]); 958 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 959 } 960 return ResultVals[Op.getResNo()]; 961 } 962 } 963 964 switch (Node->getOpcode()) { 965 default: 966#ifndef NDEBUG 967 dbgs() << "NODE: "; 968 Node->dump( &DAG); 969 dbgs() << "\n"; 970#endif 971 llvm_unreachable("Do not know how to legalize this operator!"); 972 973 case ISD::BUILD_VECTOR: 974 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 975 default: llvm_unreachable("This action is not supported yet!"); 976 case TargetLowering::Custom: 977 Tmp3 = TLI.LowerOperation(Result, DAG); 978 if (Tmp3.getNode()) { 979 Result = Tmp3; 980 break; 981 } 982 // FALLTHROUGH 983 case TargetLowering::Expand: 984 Result = ExpandBUILD_VECTOR(Result.getNode()); 985 break; 986 } 987 break; 988 case ISD::CALLSEQ_START: { 989 SDNode *CallEnd = FindCallEndFromCallStart(Node); 990 991 // Recursively Legalize all of the inputs of the call end that do not lead 992 // to this call start. This ensures that any libcalls that need be inserted 993 // are inserted *before* the CALLSEQ_START. 994 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 995 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 996 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 997 NodesLeadingTo); 998 } 999 1000 // Now that we legalized all of the inputs (which may have inserted 1001 // libcalls) create the new CALLSEQ_START node. 1002 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1003 1004 // Merge in the last call, to ensure that this call start after the last 1005 // call ended. 1006 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1007 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1008 Tmp1, LastCALLSEQ_END); 1009 Tmp1 = LegalizeOp(Tmp1); 1010 } 1011 1012 // Do not try to legalize the target-specific arguments (#1+). 1013 if (Tmp1 != Node->getOperand(0)) { 1014 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1015 Ops[0] = Tmp1; 1016 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1017 } 1018 1019 // Remember that the CALLSEQ_START is legalized. 1020 AddLegalizedOperand(Op.getValue(0), Result); 1021 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1022 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1023 1024 // Now that the callseq_start and all of the non-call nodes above this call 1025 // sequence have been legalized, legalize the call itself. During this 1026 // process, no libcalls can/will be inserted, guaranteeing that no calls 1027 // can overlap. 1028 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1029 // Note that we are selecting this call! 1030 LastCALLSEQ_END = SDValue(CallEnd, 0); 1031 IsLegalizingCall = true; 1032 1033 // Legalize the call, starting from the CALLSEQ_END. 1034 LegalizeOp(LastCALLSEQ_END); 1035 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1036 return Result; 1037 } 1038 case ISD::CALLSEQ_END: 1039 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1040 // will cause this node to be legalized as well as handling libcalls right. 1041 if (LastCALLSEQ_END.getNode() != Node) { 1042 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1043 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1044 assert(I != LegalizedNodes.end() && 1045 "Legalizing the call start should have legalized this node!"); 1046 return I->second; 1047 } 1048 1049 // Otherwise, the call start has been legalized and everything is going 1050 // according to plan. Just legalize ourselves normally here. 1051 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1052 // Do not try to legalize the target-specific arguments (#1+), except for 1053 // an optional flag input. 1054 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1055 if (Tmp1 != Node->getOperand(0)) { 1056 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1057 Ops[0] = Tmp1; 1058 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1059 } 1060 } else { 1061 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1062 if (Tmp1 != Node->getOperand(0) || 1063 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1064 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1065 Ops[0] = Tmp1; 1066 Ops.back() = Tmp2; 1067 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1068 } 1069 } 1070 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1071 // This finishes up call legalization. 1072 IsLegalizingCall = false; 1073 1074 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1075 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1076 if (Node->getNumValues() == 2) 1077 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1078 return Result.getValue(Op.getResNo()); 1079 case ISD::LOAD: { 1080 LoadSDNode *LD = cast<LoadSDNode>(Node); 1081 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1082 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1083 1084 ISD::LoadExtType ExtType = LD->getExtensionType(); 1085 if (ExtType == ISD::NON_EXTLOAD) { 1086 EVT VT = Node->getValueType(0); 1087 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1088 Tmp3 = Result.getValue(0); 1089 Tmp4 = Result.getValue(1); 1090 1091 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1092 default: llvm_unreachable("This action is not supported yet!"); 1093 case TargetLowering::Legal: 1094 // If this is an unaligned load and the target doesn't support it, 1095 // expand it. 1096 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1097 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1098 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1099 if (LD->getAlignment() < ABIAlignment){ 1100 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1101 DAG, TLI); 1102 Tmp3 = Result.getOperand(0); 1103 Tmp4 = Result.getOperand(1); 1104 Tmp3 = LegalizeOp(Tmp3); 1105 Tmp4 = LegalizeOp(Tmp4); 1106 } 1107 } 1108 break; 1109 case TargetLowering::Custom: 1110 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1111 if (Tmp1.getNode()) { 1112 Tmp3 = LegalizeOp(Tmp1); 1113 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1114 } 1115 break; 1116 case TargetLowering::Promote: { 1117 // Only promote a load of vector type to another. 1118 assert(VT.isVector() && "Cannot promote this load!"); 1119 // Change base type to a different vector type. 1120 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1121 1122 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1123 LD->getSrcValueOffset(), 1124 LD->isVolatile(), LD->isNonTemporal(), 1125 LD->getAlignment()); 1126 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1127 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1128 break; 1129 } 1130 } 1131 // Since loads produce two values, make sure to remember that we 1132 // legalized both of them. 1133 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1134 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1135 return Op.getResNo() ? Tmp4 : Tmp3; 1136 } else { 1137 EVT SrcVT = LD->getMemoryVT(); 1138 unsigned SrcWidth = SrcVT.getSizeInBits(); 1139 int SVOffset = LD->getSrcValueOffset(); 1140 unsigned Alignment = LD->getAlignment(); 1141 bool isVolatile = LD->isVolatile(); 1142 bool isNonTemporal = LD->isNonTemporal(); 1143 1144 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1145 // Some targets pretend to have an i1 loading operation, and actually 1146 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1147 // bits are guaranteed to be zero; it helps the optimizers understand 1148 // that these bits are zero. It is also useful for EXTLOAD, since it 1149 // tells the optimizers that those bits are undefined. It would be 1150 // nice to have an effective generic way of getting these benefits... 1151 // Until such a way is found, don't insist on promoting i1 here. 1152 (SrcVT != MVT::i1 || 1153 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1154 // Promote to a byte-sized load if not loading an integral number of 1155 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1156 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1157 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 1158 SDValue Ch; 1159 1160 // The extra bits are guaranteed to be zero, since we stored them that 1161 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1162 1163 ISD::LoadExtType NewExtType = 1164 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1165 1166 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 1167 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1168 NVT, isVolatile, isNonTemporal, Alignment); 1169 1170 Ch = Result.getValue(1); // The chain. 1171 1172 if (ExtType == ISD::SEXTLOAD) 1173 // Having the top bits zero doesn't help when sign extending. 1174 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1175 Result.getValueType(), 1176 Result, DAG.getValueType(SrcVT)); 1177 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1178 // All the top bits are guaranteed to be zero - inform the optimizers. 1179 Result = DAG.getNode(ISD::AssertZext, dl, 1180 Result.getValueType(), Result, 1181 DAG.getValueType(SrcVT)); 1182 1183 Tmp1 = LegalizeOp(Result); 1184 Tmp2 = LegalizeOp(Ch); 1185 } else if (SrcWidth & (SrcWidth - 1)) { 1186 // If not loading a power-of-2 number of bits, expand as two loads. 1187 assert(!SrcVT.isVector() && "Unsupported extload!"); 1188 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1189 assert(RoundWidth < SrcWidth); 1190 unsigned ExtraWidth = SrcWidth - RoundWidth; 1191 assert(ExtraWidth < RoundWidth); 1192 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1193 "Load size not an integral number of bytes!"); 1194 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1195 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1196 SDValue Lo, Hi, Ch; 1197 unsigned IncrementSize; 1198 1199 if (TLI.isLittleEndian()) { 1200 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1201 // Load the bottom RoundWidth bits. 1202 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1203 Node->getValueType(0), Tmp1, Tmp2, 1204 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1205 isNonTemporal, Alignment); 1206 1207 // Load the remaining ExtraWidth bits. 1208 IncrementSize = RoundWidth / 8; 1209 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1210 DAG.getIntPtrConstant(IncrementSize)); 1211 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1212 LD->getSrcValue(), SVOffset + IncrementSize, 1213 ExtraVT, isVolatile, isNonTemporal, 1214 MinAlign(Alignment, IncrementSize)); 1215 1216 // Build a factor node to remember that this load is independent of the 1217 // other one. 1218 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1219 Hi.getValue(1)); 1220 1221 // Move the top bits to the right place. 1222 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1223 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1224 1225 // Join the hi and lo parts. 1226 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1227 } else { 1228 // Big endian - avoid unaligned loads. 1229 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1230 // Load the top RoundWidth bits. 1231 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1232 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1233 isNonTemporal, Alignment); 1234 1235 // Load the remaining ExtraWidth bits. 1236 IncrementSize = RoundWidth / 8; 1237 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1238 DAG.getIntPtrConstant(IncrementSize)); 1239 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1240 Node->getValueType(0), Tmp1, Tmp2, 1241 LD->getSrcValue(), SVOffset + IncrementSize, 1242 ExtraVT, isVolatile, isNonTemporal, 1243 MinAlign(Alignment, IncrementSize)); 1244 1245 // Build a factor node to remember that this load is independent of the 1246 // other one. 1247 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1248 Hi.getValue(1)); 1249 1250 // Move the top bits to the right place. 1251 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1252 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1253 1254 // Join the hi and lo parts. 1255 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1256 } 1257 1258 Tmp1 = LegalizeOp(Result); 1259 Tmp2 = LegalizeOp(Ch); 1260 } else { 1261 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1262 default: llvm_unreachable("This action is not supported yet!"); 1263 case TargetLowering::Custom: 1264 isCustom = true; 1265 // FALLTHROUGH 1266 case TargetLowering::Legal: 1267 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1268 Tmp1 = Result.getValue(0); 1269 Tmp2 = Result.getValue(1); 1270 1271 if (isCustom) { 1272 Tmp3 = TLI.LowerOperation(Result, DAG); 1273 if (Tmp3.getNode()) { 1274 Tmp1 = LegalizeOp(Tmp3); 1275 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1276 } 1277 } else { 1278 // If this is an unaligned load and the target doesn't support it, 1279 // expand it. 1280 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1281 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1282 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1283 if (LD->getAlignment() < ABIAlignment){ 1284 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1285 DAG, TLI); 1286 Tmp1 = Result.getOperand(0); 1287 Tmp2 = Result.getOperand(1); 1288 Tmp1 = LegalizeOp(Tmp1); 1289 Tmp2 = LegalizeOp(Tmp2); 1290 } 1291 } 1292 } 1293 break; 1294 case TargetLowering::Expand: 1295 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1296 // f128 = EXTLOAD {f32,f64} too 1297 if ((SrcVT == MVT::f32 && (Node->getValueType(0) == MVT::f64 || 1298 Node->getValueType(0) == MVT::f128)) || 1299 (SrcVT == MVT::f64 && Node->getValueType(0) == MVT::f128)) { 1300 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1301 LD->getSrcValueOffset(), 1302 LD->isVolatile(), LD->isNonTemporal(), 1303 LD->getAlignment()); 1304 Result = DAG.getNode(ISD::FP_EXTEND, dl, 1305 Node->getValueType(0), Load); 1306 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1307 Tmp2 = LegalizeOp(Load.getValue(1)); 1308 break; 1309 } 1310 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1311 // Turn the unsupported load into an EXTLOAD followed by an explicit 1312 // zero/sign extend inreg. 1313 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1314 Tmp1, Tmp2, LD->getSrcValue(), 1315 LD->getSrcValueOffset(), SrcVT, 1316 LD->isVolatile(), LD->isNonTemporal(), 1317 LD->getAlignment()); 1318 SDValue ValRes; 1319 if (ExtType == ISD::SEXTLOAD) 1320 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1321 Result.getValueType(), 1322 Result, DAG.getValueType(SrcVT)); 1323 else 1324 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1325 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1326 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1327 break; 1328 } 1329 } 1330 1331 // Since loads produce two values, make sure to remember that we legalized 1332 // both of them. 1333 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1334 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1335 return Op.getResNo() ? Tmp2 : Tmp1; 1336 } 1337 } 1338 case ISD::STORE: { 1339 StoreSDNode *ST = cast<StoreSDNode>(Node); 1340 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1341 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1342 int SVOffset = ST->getSrcValueOffset(); 1343 unsigned Alignment = ST->getAlignment(); 1344 bool isVolatile = ST->isVolatile(); 1345 bool isNonTemporal = ST->isNonTemporal(); 1346 1347 if (!ST->isTruncatingStore()) { 1348 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1349 Result = SDValue(OptStore, 0); 1350 break; 1351 } 1352 1353 { 1354 Tmp3 = LegalizeOp(ST->getValue()); 1355 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1356 ST->getOffset()); 1357 1358 EVT VT = Tmp3.getValueType(); 1359 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1360 default: llvm_unreachable("This action is not supported yet!"); 1361 case TargetLowering::Legal: 1362 // If this is an unaligned store and the target doesn't support it, 1363 // expand it. 1364 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1365 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1366 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1367 if (ST->getAlignment() < ABIAlignment) 1368 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1369 DAG, TLI); 1370 } 1371 break; 1372 case TargetLowering::Custom: 1373 Tmp1 = TLI.LowerOperation(Result, DAG); 1374 if (Tmp1.getNode()) Result = Tmp1; 1375 break; 1376 case TargetLowering::Promote: 1377 assert(VT.isVector() && "Unknown legal promote case!"); 1378 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1379 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1380 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1381 ST->getSrcValue(), SVOffset, isVolatile, 1382 isNonTemporal, Alignment); 1383 break; 1384 } 1385 break; 1386 } 1387 } else { 1388 Tmp3 = LegalizeOp(ST->getValue()); 1389 1390 EVT StVT = ST->getMemoryVT(); 1391 unsigned StWidth = StVT.getSizeInBits(); 1392 1393 if (StWidth != StVT.getStoreSizeInBits()) { 1394 // Promote to a byte-sized store with upper bits zero if not 1395 // storing an integral number of bytes. For example, promote 1396 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1397 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StVT.getStoreSizeInBits()); 1398 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1399 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1400 SVOffset, NVT, isVolatile, isNonTemporal, 1401 Alignment); 1402 } else if (StWidth & (StWidth - 1)) { 1403 // If not storing a power-of-2 number of bits, expand as two stores. 1404 assert(!StVT.isVector() && "Unsupported truncstore!"); 1405 unsigned RoundWidth = 1 << Log2_32(StWidth); 1406 assert(RoundWidth < StWidth); 1407 unsigned ExtraWidth = StWidth - RoundWidth; 1408 assert(ExtraWidth < RoundWidth); 1409 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1410 "Store size not an integral number of bytes!"); 1411 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1412 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1413 SDValue Lo, Hi; 1414 unsigned IncrementSize; 1415 1416 if (TLI.isLittleEndian()) { 1417 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1418 // Store the bottom RoundWidth bits. 1419 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1420 SVOffset, RoundVT, 1421 isVolatile, isNonTemporal, Alignment); 1422 1423 // Store the remaining ExtraWidth bits. 1424 IncrementSize = RoundWidth / 8; 1425 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1426 DAG.getIntPtrConstant(IncrementSize)); 1427 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1428 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1429 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1430 SVOffset + IncrementSize, ExtraVT, isVolatile, 1431 isNonTemporal, 1432 MinAlign(Alignment, IncrementSize)); 1433 } else { 1434 // Big endian - avoid unaligned stores. 1435 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1436 // Store the top RoundWidth bits. 1437 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1438 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1439 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1440 SVOffset, RoundVT, isVolatile, isNonTemporal, 1441 Alignment); 1442 1443 // Store the remaining ExtraWidth bits. 1444 IncrementSize = RoundWidth / 8; 1445 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1446 DAG.getIntPtrConstant(IncrementSize)); 1447 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1448 SVOffset + IncrementSize, ExtraVT, isVolatile, 1449 isNonTemporal, 1450 MinAlign(Alignment, IncrementSize)); 1451 } 1452 1453 // The order of the stores doesn't matter. 1454 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1455 } else { 1456 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1457 Tmp2 != ST->getBasePtr()) 1458 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1459 ST->getOffset()); 1460 1461 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1462 default: llvm_unreachable("This action is not supported yet!"); 1463 case TargetLowering::Legal: 1464 // If this is an unaligned store and the target doesn't support it, 1465 // expand it. 1466 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1467 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1468 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1469 if (ST->getAlignment() < ABIAlignment) 1470 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1471 DAG, TLI); 1472 } 1473 break; 1474 case TargetLowering::Custom: 1475 Result = TLI.LowerOperation(Result, DAG); 1476 break; 1477 case Expand: 1478 // TRUNCSTORE:i16 i32 -> STORE i16 1479 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1480 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1481 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1482 SVOffset, isVolatile, isNonTemporal, 1483 Alignment); 1484 break; 1485 } 1486 } 1487 } 1488 break; 1489 } 1490 } 1491 assert(Result.getValueType() == Op.getValueType() && 1492 "Bad legalization!"); 1493 1494 // Make sure that the generated code is itself legal. 1495 if (Result != Op) 1496 Result = LegalizeOp(Result); 1497 1498 // Note that LegalizeOp may be reentered even from single-use nodes, which 1499 // means that we always must cache transformed nodes. 1500 AddLegalizedOperand(Op, Result); 1501 return Result; 1502} 1503 1504SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1505 SDValue Vec = Op.getOperand(0); 1506 SDValue Idx = Op.getOperand(1); 1507 DebugLoc dl = Op.getDebugLoc(); 1508 // Store the value to a temporary stack slot, then LOAD the returned part. 1509 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1510 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0, 1511 false, false, 0); 1512 1513 // Add the offset to the index. 1514 unsigned EltSize = 1515 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1516 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1517 DAG.getConstant(EltSize, Idx.getValueType())); 1518 1519 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1520 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1521 else 1522 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1523 1524 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1525 1526 if (Op.getValueType().isVector()) 1527 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0, 1528 false, false, 0); 1529 else 1530 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1531 NULL, 0, Vec.getValueType().getVectorElementType(), 1532 false, false, 0); 1533} 1534 1535SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1536 // We can't handle this case efficiently. Allocate a sufficiently 1537 // aligned object on the stack, store each element into it, then load 1538 // the result as a vector. 1539 // Create the stack frame object. 1540 EVT VT = Node->getValueType(0); 1541 EVT EltVT = VT.getVectorElementType(); 1542 DebugLoc dl = Node->getDebugLoc(); 1543 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1544 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1545 const Value *SV = PseudoSourceValue::getFixedStack(FI); 1546 1547 // Emit a store of each element to the stack slot. 1548 SmallVector<SDValue, 8> Stores; 1549 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1550 // Store (in the right endianness) the elements to memory. 1551 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1552 // Ignore undef elements. 1553 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1554 1555 unsigned Offset = TypeByteSize*i; 1556 1557 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1558 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1559 1560 // If the destination vector element type is narrower than the source 1561 // element type, only store the bits necessary. 1562 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1563 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1564 Node->getOperand(i), Idx, SV, Offset, 1565 EltVT, false, false, 0)); 1566 } else 1567 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1568 Node->getOperand(i), Idx, SV, Offset, 1569 false, false, 0)); 1570 } 1571 1572 SDValue StoreChain; 1573 if (!Stores.empty()) // Not all undef elements? 1574 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1575 &Stores[0], Stores.size()); 1576 else 1577 StoreChain = DAG.getEntryNode(); 1578 1579 // Result is a load from the stack slot. 1580 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0, false, false, 0); 1581} 1582 1583SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1584 DebugLoc dl = Node->getDebugLoc(); 1585 SDValue Tmp1 = Node->getOperand(0); 1586 SDValue Tmp2 = Node->getOperand(1); 1587 1588 // Get the sign bit of the RHS. First obtain a value that has the same 1589 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1590 SDValue SignBit; 1591 EVT FloatVT = Tmp2.getValueType(); 1592 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1593 if (isTypeLegal(IVT)) { 1594 // Convert to an integer with the same sign bit. 1595 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 1596 } else { 1597 // Store the float to memory, then load the sign part out as an integer. 1598 MVT LoadTy = TLI.getPointerTy(); 1599 // First create a temporary that is aligned for both the load and store. 1600 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1601 // Then store the float to it. 1602 SDValue Ch = 1603 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, NULL, 0, 1604 false, false, 0); 1605 if (TLI.isBigEndian()) { 1606 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1607 // Load out a legal integer with the same sign bit as the float. 1608 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, NULL, 0, false, false, 0); 1609 } else { // Little endian 1610 SDValue LoadPtr = StackPtr; 1611 // The float may be wider than the integer we are going to load. Advance 1612 // the pointer so that the loaded integer will contain the sign bit. 1613 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1614 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1615 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1616 LoadPtr, DAG.getIntPtrConstant(ByteOffset)); 1617 // Load a legal integer containing the sign bit. 1618 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, NULL, 0, false, false, 0); 1619 // Move the sign bit to the top bit of the loaded integer. 1620 unsigned BitShift = LoadTy.getSizeInBits() - 1621 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1622 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1623 if (BitShift) 1624 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1625 DAG.getConstant(BitShift,TLI.getShiftAmountTy())); 1626 } 1627 } 1628 // Now get the sign bit proper, by seeing whether the value is negative. 1629 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1630 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1631 ISD::SETLT); 1632 // Get the absolute value of the result. 1633 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1634 // Select between the nabs and abs value based on the sign bit of 1635 // the input. 1636 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1637 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1638 AbsVal); 1639} 1640 1641void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1642 SmallVectorImpl<SDValue> &Results) { 1643 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1644 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1645 " not tell us which reg is the stack pointer!"); 1646 DebugLoc dl = Node->getDebugLoc(); 1647 EVT VT = Node->getValueType(0); 1648 SDValue Tmp1 = SDValue(Node, 0); 1649 SDValue Tmp2 = SDValue(Node, 1); 1650 SDValue Tmp3 = Node->getOperand(2); 1651 SDValue Chain = Tmp1.getOperand(0); 1652 1653 // Chain the dynamic stack allocation so that it doesn't modify the stack 1654 // pointer when other instructions are using the stack. 1655 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1656 1657 SDValue Size = Tmp2.getOperand(1); 1658 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1659 Chain = SP.getValue(1); 1660 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1661 unsigned StackAlign = 1662 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1663 if (Align > StackAlign) 1664 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1665 DAG.getConstant(-(uint64_t)Align, VT)); 1666 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1667 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1668 1669 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1670 DAG.getIntPtrConstant(0, true), SDValue()); 1671 1672 Results.push_back(Tmp1); 1673 Results.push_back(Tmp2); 1674} 1675 1676/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1677/// condition code CC on the current target. This routine expands SETCC with 1678/// illegal condition code into AND / OR of multiple SETCC values. 1679void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1680 SDValue &LHS, SDValue &RHS, 1681 SDValue &CC, 1682 DebugLoc dl) { 1683 EVT OpVT = LHS.getValueType(); 1684 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1685 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1686 default: llvm_unreachable("Unknown condition code action!"); 1687 case TargetLowering::Legal: 1688 // Nothing to do. 1689 break; 1690 case TargetLowering::Expand: { 1691 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1692 unsigned Opc = 0; 1693 switch (CCCode) { 1694 default: llvm_unreachable("Don't know how to expand this condition!"); 1695 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1696 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1697 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1698 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1699 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1700 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1701 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1702 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1703 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1704 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1705 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1706 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1707 // FIXME: Implement more expansions. 1708 } 1709 1710 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1711 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1712 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1713 RHS = SDValue(); 1714 CC = SDValue(); 1715 break; 1716 } 1717 } 1718} 1719 1720/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1721/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1722/// a load from the stack slot to DestVT, extending it if needed. 1723/// The resultant code need not be legal. 1724SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1725 EVT SlotVT, 1726 EVT DestVT, 1727 DebugLoc dl) { 1728 // Create the stack frame object. 1729 unsigned SrcAlign = 1730 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1731 getTypeForEVT(*DAG.getContext())); 1732 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1733 1734 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1735 int SPFI = StackPtrFI->getIndex(); 1736 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1737 1738 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1739 unsigned SlotSize = SlotVT.getSizeInBits(); 1740 unsigned DestSize = DestVT.getSizeInBits(); 1741 unsigned DestAlign = 1742 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT(*DAG.getContext())); 1743 1744 // Emit a store to the stack slot. Use a truncstore if the input value is 1745 // later than DestVT. 1746 SDValue Store; 1747 1748 if (SrcSize > SlotSize) 1749 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1750 SV, 0, SlotVT, false, false, SrcAlign); 1751 else { 1752 assert(SrcSize == SlotSize && "Invalid store"); 1753 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1754 SV, 0, false, false, SrcAlign); 1755 } 1756 1757 // Result is a load from the stack slot. 1758 if (SlotSize == DestSize) 1759 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, false, 1760 DestAlign); 1761 1762 assert(SlotSize < DestSize && "Unknown extension!"); 1763 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, 1764 false, false, DestAlign); 1765} 1766 1767SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1768 DebugLoc dl = Node->getDebugLoc(); 1769 // Create a vector sized/aligned stack slot, store the value to element #0, 1770 // then load the whole vector back out. 1771 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1772 1773 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1774 int SPFI = StackPtrFI->getIndex(); 1775 1776 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1777 StackPtr, 1778 PseudoSourceValue::getFixedStack(SPFI), 0, 1779 Node->getValueType(0).getVectorElementType(), 1780 false, false, 0); 1781 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1782 PseudoSourceValue::getFixedStack(SPFI), 0, 1783 false, false, 0); 1784} 1785 1786 1787/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1788/// support the operation, but do support the resultant vector type. 1789SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1790 unsigned NumElems = Node->getNumOperands(); 1791 SDValue Value1, Value2; 1792 DebugLoc dl = Node->getDebugLoc(); 1793 EVT VT = Node->getValueType(0); 1794 EVT OpVT = Node->getOperand(0).getValueType(); 1795 EVT EltVT = VT.getVectorElementType(); 1796 1797 // If the only non-undef value is the low element, turn this into a 1798 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1799 bool isOnlyLowElement = true; 1800 bool MoreThanTwoValues = false; 1801 bool isConstant = true; 1802 for (unsigned i = 0; i < NumElems; ++i) { 1803 SDValue V = Node->getOperand(i); 1804 if (V.getOpcode() == ISD::UNDEF) 1805 continue; 1806 if (i > 0) 1807 isOnlyLowElement = false; 1808 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1809 isConstant = false; 1810 1811 if (!Value1.getNode()) { 1812 Value1 = V; 1813 } else if (!Value2.getNode()) { 1814 if (V != Value1) 1815 Value2 = V; 1816 } else if (V != Value1 && V != Value2) { 1817 MoreThanTwoValues = true; 1818 } 1819 } 1820 1821 if (!Value1.getNode()) 1822 return DAG.getUNDEF(VT); 1823 1824 if (isOnlyLowElement) 1825 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1826 1827 // If all elements are constants, create a load from the constant pool. 1828 if (isConstant) { 1829 std::vector<Constant*> CV; 1830 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1831 if (ConstantFPSDNode *V = 1832 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1833 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1834 } else if (ConstantSDNode *V = 1835 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1836 if (OpVT==EltVT) 1837 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1838 else { 1839 // If OpVT and EltVT don't match, EltVT is not legal and the 1840 // element values have been promoted/truncated earlier. Undo this; 1841 // we don't want a v16i8 to become a v16i32 for example. 1842 const ConstantInt *CI = V->getConstantIntValue(); 1843 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1844 CI->getZExtValue())); 1845 } 1846 } else { 1847 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1848 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1849 CV.push_back(UndefValue::get(OpNTy)); 1850 } 1851 } 1852 Constant *CP = ConstantVector::get(CV); 1853 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1854 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1855 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1856 PseudoSourceValue::getConstantPool(), 0, 1857 false, false, Alignment); 1858 } 1859 1860 if (!MoreThanTwoValues) { 1861 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1862 for (unsigned i = 0; i < NumElems; ++i) { 1863 SDValue V = Node->getOperand(i); 1864 if (V.getOpcode() == ISD::UNDEF) 1865 continue; 1866 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1867 } 1868 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1869 // Get the splatted value into the low element of a vector register. 1870 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1871 SDValue Vec2; 1872 if (Value2.getNode()) 1873 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1874 else 1875 Vec2 = DAG.getUNDEF(VT); 1876 1877 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1878 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1879 } 1880 } 1881 1882 // Otherwise, we can't handle this case efficiently. 1883 return ExpandVectorBuildThroughStack(Node); 1884} 1885 1886// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1887// does not fit into a register, return the lo part and set the hi part to the 1888// by-reg argument. If it does fit into a single register, return the result 1889// and leave the Hi part unset. 1890SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1891 bool isSigned) { 1892 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1893 // The input chain to this libcall is the entry node of the function. 1894 // Legalizing the call will automatically add the previous call to the 1895 // dependence. 1896 SDValue InChain = DAG.getEntryNode(); 1897 1898 TargetLowering::ArgListTy Args; 1899 TargetLowering::ArgListEntry Entry; 1900 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1901 EVT ArgVT = Node->getOperand(i).getValueType(); 1902 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1903 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1904 Entry.isSExt = isSigned; 1905 Entry.isZExt = !isSigned; 1906 Args.push_back(Entry); 1907 } 1908 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1909 TLI.getPointerTy()); 1910 1911 // Splice the libcall in wherever FindInputOutputChains tells us to. 1912 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1913 std::pair<SDValue, SDValue> CallInfo = 1914 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1915 0, TLI.getLibcallCallingConv(LC), false, 1916 /*isReturnValueUsed=*/true, 1917 Callee, Args, DAG, Node->getDebugLoc()); 1918 1919 // Legalize the call sequence, starting with the chain. This will advance 1920 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1921 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1922 LegalizeOp(CallInfo.second); 1923 return CallInfo.first; 1924} 1925 1926SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 1927 RTLIB::Libcall Call_F32, 1928 RTLIB::Libcall Call_F64, 1929 RTLIB::Libcall Call_F80, 1930 RTLIB::Libcall Call_PPCF128) { 1931 RTLIB::Libcall LC; 1932 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1933 default: llvm_unreachable("Unexpected request for libcall!"); 1934 case MVT::f32: LC = Call_F32; break; 1935 case MVT::f64: LC = Call_F64; break; 1936 case MVT::f80: LC = Call_F80; break; 1937 case MVT::ppcf128: LC = Call_PPCF128; break; 1938 } 1939 return ExpandLibCall(LC, Node, false); 1940} 1941 1942SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 1943 RTLIB::Libcall Call_I8, 1944 RTLIB::Libcall Call_I16, 1945 RTLIB::Libcall Call_I32, 1946 RTLIB::Libcall Call_I64, 1947 RTLIB::Libcall Call_I128) { 1948 RTLIB::Libcall LC; 1949 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1950 default: llvm_unreachable("Unexpected request for libcall!"); 1951 case MVT::i8: LC = Call_I8; break; 1952 case MVT::i16: LC = Call_I16; break; 1953 case MVT::i32: LC = Call_I32; break; 1954 case MVT::i64: LC = Call_I64; break; 1955 case MVT::i128: LC = Call_I128; break; 1956 } 1957 return ExpandLibCall(LC, Node, isSigned); 1958} 1959 1960/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 1961/// INT_TO_FP operation of the specified operand when the target requests that 1962/// we expand it. At this point, we know that the result and operand types are 1963/// legal for the target. 1964SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 1965 SDValue Op0, 1966 EVT DestVT, 1967 DebugLoc dl) { 1968 if (Op0.getValueType() == MVT::i32) { 1969 // simple 32-bit [signed|unsigned] integer to float/double expansion 1970 1971 // Get the stack frame index of a 8 byte buffer. 1972 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 1973 1974 // word offset constant for Hi/Lo address computation 1975 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 1976 // set up Hi and Lo (into buffer) address based on endian 1977 SDValue Hi = StackSlot; 1978 SDValue Lo = DAG.getNode(ISD::ADD, dl, 1979 TLI.getPointerTy(), StackSlot, WordOff); 1980 if (TLI.isLittleEndian()) 1981 std::swap(Hi, Lo); 1982 1983 // if signed map to unsigned space 1984 SDValue Op0Mapped; 1985 if (isSigned) { 1986 // constant used to invert sign bit (signed to unsigned mapping) 1987 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 1988 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 1989 } else { 1990 Op0Mapped = Op0; 1991 } 1992 // store the lo of the constructed double - based on integer input 1993 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 1994 Op0Mapped, Lo, NULL, 0, 1995 false, false, 0); 1996 // initial hi portion of constructed double 1997 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 1998 // store the hi of the constructed double - biased exponent 1999 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0, 2000 false, false, 0); 2001 // load the constructed double 2002 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0, 2003 false, false, 0); 2004 // FP constant to bias correct the final result 2005 SDValue Bias = DAG.getConstantFP(isSigned ? 2006 BitsToDouble(0x4330000080000000ULL) : 2007 BitsToDouble(0x4330000000000000ULL), 2008 MVT::f64); 2009 // subtract the bias 2010 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2011 // final result 2012 SDValue Result; 2013 // handle final rounding 2014 if (DestVT == MVT::f64) { 2015 // do nothing 2016 Result = Sub; 2017 } else if (DestVT.bitsLT(MVT::f64)) { 2018 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2019 DAG.getIntPtrConstant(0)); 2020 } else if (DestVT.bitsGT(MVT::f64)) { 2021 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2022 } 2023 return Result; 2024 } 2025 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2026 2027 // Implementation of unsigned i64 to f64 following the algorithm in 2028 // __floatundidf in compiler_rt. This implementation has the advantage 2029 // of performing rounding correctly, both in the default rounding mode 2030 // and in all alternate rounding modes. 2031 // TODO: Generalize this for use with other types. 2032 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2033 SDValue TwoP52 = 2034 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2035 SDValue TwoP84PlusTwoP52 = 2036 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2037 SDValue TwoP84 = 2038 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2039 2040 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2041 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2042 DAG.getConstant(32, MVT::i64)); 2043 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2044 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2045 SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr); 2046 SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr); 2047 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, TwoP84PlusTwoP52); 2048 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2049 } 2050 2051 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2052 2053 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2054 Op0, DAG.getConstant(0, Op0.getValueType()), 2055 ISD::SETLT); 2056 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2057 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2058 SignSet, Four, Zero); 2059 2060 // If the sign bit of the integer is set, the large number will be treated 2061 // as a negative number. To counteract this, the dynamic code adds an 2062 // offset depending on the data type. 2063 uint64_t FF; 2064 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2065 default: llvm_unreachable("Unsupported integer type!"); 2066 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2067 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2068 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2069 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2070 } 2071 if (TLI.isLittleEndian()) FF <<= 32; 2072 Constant *FudgeFactor = ConstantInt::get( 2073 Type::getInt64Ty(*DAG.getContext()), FF); 2074 2075 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2076 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2077 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2078 Alignment = std::min(Alignment, 4u); 2079 SDValue FudgeInReg; 2080 if (DestVT == MVT::f32) 2081 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2082 PseudoSourceValue::getConstantPool(), 0, 2083 false, false, Alignment); 2084 else { 2085 FudgeInReg = 2086 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2087 DAG.getEntryNode(), CPIdx, 2088 PseudoSourceValue::getConstantPool(), 0, 2089 MVT::f32, false, false, Alignment)); 2090 } 2091 2092 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2093} 2094 2095/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2096/// *INT_TO_FP operation of the specified operand when the target requests that 2097/// we promote it. At this point, we know that the result and operand types are 2098/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2099/// operation that takes a larger input. 2100SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2101 EVT DestVT, 2102 bool isSigned, 2103 DebugLoc dl) { 2104 // First step, figure out the appropriate *INT_TO_FP operation to use. 2105 EVT NewInTy = LegalOp.getValueType(); 2106 2107 unsigned OpToUse = 0; 2108 2109 // Scan for the appropriate larger type to use. 2110 while (1) { 2111 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2112 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2113 2114 // If the target supports SINT_TO_FP of this type, use it. 2115 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2116 OpToUse = ISD::SINT_TO_FP; 2117 break; 2118 } 2119 if (isSigned) continue; 2120 2121 // If the target supports UINT_TO_FP of this type, use it. 2122 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2123 OpToUse = ISD::UINT_TO_FP; 2124 break; 2125 } 2126 2127 // Otherwise, try a larger type. 2128 } 2129 2130 // Okay, we found the operation and type to use. Zero extend our input to the 2131 // desired type then run the operation on it. 2132 return DAG.getNode(OpToUse, dl, DestVT, 2133 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2134 dl, NewInTy, LegalOp)); 2135} 2136 2137/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2138/// FP_TO_*INT operation of the specified operand when the target requests that 2139/// we promote it. At this point, we know that the result and operand types are 2140/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2141/// operation that returns a larger result. 2142SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2143 EVT DestVT, 2144 bool isSigned, 2145 DebugLoc dl) { 2146 // First step, figure out the appropriate FP_TO*INT operation to use. 2147 EVT NewOutTy = DestVT; 2148 2149 unsigned OpToUse = 0; 2150 2151 // Scan for the appropriate larger type to use. 2152 while (1) { 2153 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2154 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2155 2156 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2157 OpToUse = ISD::FP_TO_SINT; 2158 break; 2159 } 2160 2161 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2162 OpToUse = ISD::FP_TO_UINT; 2163 break; 2164 } 2165 2166 // Otherwise, try a larger type. 2167 } 2168 2169 2170 // Okay, we found the operation and type to use. 2171 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2172 2173 // Truncate the result of the extended FP_TO_*INT operation to the desired 2174 // size. 2175 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2176} 2177 2178/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2179/// 2180SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2181 EVT VT = Op.getValueType(); 2182 EVT SHVT = TLI.getShiftAmountTy(); 2183 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2184 switch (VT.getSimpleVT().SimpleTy) { 2185 default: llvm_unreachable("Unhandled Expand type in BSWAP!"); 2186 case MVT::i16: 2187 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2188 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2189 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2190 case MVT::i32: 2191 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2192 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2193 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2194 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2195 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2196 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2197 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2198 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2199 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2200 case MVT::i64: 2201 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2202 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2203 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2204 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2205 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2206 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2207 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2208 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2209 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2210 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2211 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2212 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2213 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2214 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2215 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2216 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2217 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2218 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2219 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2220 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2221 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2222 } 2223} 2224 2225/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2226/// 2227SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2228 DebugLoc dl) { 2229 switch (Opc) { 2230 default: llvm_unreachable("Cannot expand this yet!"); 2231 case ISD::CTPOP: { 2232 static const uint64_t mask[6] = { 2233 0x5555555555555555ULL, 0x3333333333333333ULL, 2234 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2235 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2236 }; 2237 EVT VT = Op.getValueType(); 2238 EVT ShVT = TLI.getShiftAmountTy(); 2239 unsigned len = VT.getSizeInBits(); 2240 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2241 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2242 unsigned EltSize = VT.isVector() ? 2243 VT.getVectorElementType().getSizeInBits() : len; 2244 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2245 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2246 Op = DAG.getNode(ISD::ADD, dl, VT, 2247 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2248 DAG.getNode(ISD::AND, dl, VT, 2249 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2250 Tmp2)); 2251 } 2252 return Op; 2253 } 2254 case ISD::CTLZ: { 2255 // for now, we do this: 2256 // x = x | (x >> 1); 2257 // x = x | (x >> 2); 2258 // ... 2259 // x = x | (x >>16); 2260 // x = x | (x >>32); // for 64-bit input 2261 // return popcount(~x); 2262 // 2263 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2264 EVT VT = Op.getValueType(); 2265 EVT ShVT = TLI.getShiftAmountTy(); 2266 unsigned len = VT.getSizeInBits(); 2267 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2268 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2269 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2270 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2271 } 2272 Op = DAG.getNOT(dl, Op, VT); 2273 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2274 } 2275 case ISD::CTTZ: { 2276 // for now, we use: { return popcount(~x & (x - 1)); } 2277 // unless the target has ctlz but not ctpop, in which case we use: 2278 // { return 32 - nlz(~x & (x-1)); } 2279 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2280 EVT VT = Op.getValueType(); 2281 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2282 DAG.getNOT(dl, Op, VT), 2283 DAG.getNode(ISD::SUB, dl, VT, Op, 2284 DAG.getConstant(1, VT))); 2285 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2286 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2287 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2288 return DAG.getNode(ISD::SUB, dl, VT, 2289 DAG.getConstant(VT.getSizeInBits(), VT), 2290 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2291 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2292 } 2293 } 2294} 2295 2296void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2297 SmallVectorImpl<SDValue> &Results) { 2298 DebugLoc dl = Node->getDebugLoc(); 2299 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2300 switch (Node->getOpcode()) { 2301 case ISD::CTPOP: 2302 case ISD::CTLZ: 2303 case ISD::CTTZ: 2304 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2305 Results.push_back(Tmp1); 2306 break; 2307 case ISD::BSWAP: 2308 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2309 break; 2310 case ISD::FRAMEADDR: 2311 case ISD::RETURNADDR: 2312 case ISD::FRAME_TO_ARGS_OFFSET: 2313 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2314 break; 2315 case ISD::FLT_ROUNDS_: 2316 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2317 break; 2318 case ISD::EH_RETURN: 2319 case ISD::EH_LABEL: 2320 case ISD::PREFETCH: 2321 case ISD::MEMBARRIER: 2322 case ISD::VAEND: 2323 Results.push_back(Node->getOperand(0)); 2324 break; 2325 case ISD::DYNAMIC_STACKALLOC: 2326 ExpandDYNAMIC_STACKALLOC(Node, Results); 2327 break; 2328 case ISD::MERGE_VALUES: 2329 for (unsigned i = 0; i < Node->getNumValues(); i++) 2330 Results.push_back(Node->getOperand(i)); 2331 break; 2332 case ISD::UNDEF: { 2333 EVT VT = Node->getValueType(0); 2334 if (VT.isInteger()) 2335 Results.push_back(DAG.getConstant(0, VT)); 2336 else if (VT.isFloatingPoint()) 2337 Results.push_back(DAG.getConstantFP(0, VT)); 2338 else 2339 llvm_unreachable("Unknown value type!"); 2340 break; 2341 } 2342 case ISD::TRAP: { 2343 // If this operation is not supported, lower it to 'abort()' call 2344 TargetLowering::ArgListTy Args; 2345 std::pair<SDValue, SDValue> CallResult = 2346 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2347 false, false, false, false, 0, CallingConv::C, false, 2348 /*isReturnValueUsed=*/true, 2349 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2350 Args, DAG, dl); 2351 Results.push_back(CallResult.second); 2352 break; 2353 } 2354 case ISD::FP_ROUND: 2355 case ISD::BIT_CONVERT: 2356 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2357 Node->getValueType(0), dl); 2358 Results.push_back(Tmp1); 2359 break; 2360 case ISD::FP_EXTEND: 2361 Tmp1 = EmitStackConvert(Node->getOperand(0), 2362 Node->getOperand(0).getValueType(), 2363 Node->getValueType(0), dl); 2364 Results.push_back(Tmp1); 2365 break; 2366 case ISD::SIGN_EXTEND_INREG: { 2367 // NOTE: we could fall back on load/store here too for targets without 2368 // SAR. However, it is doubtful that any exist. 2369 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2370 EVT VT = Node->getValueType(0); 2371 EVT ShiftAmountTy = TLI.getShiftAmountTy(); 2372 if (VT.isVector()) 2373 ShiftAmountTy = VT; 2374 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2375 ExtraVT.getScalarType().getSizeInBits(); 2376 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2377 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2378 Node->getOperand(0), ShiftCst); 2379 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2380 Results.push_back(Tmp1); 2381 break; 2382 } 2383 case ISD::FP_ROUND_INREG: { 2384 // The only way we can lower this is to turn it into a TRUNCSTORE, 2385 // EXTLOAD pair, targetting a temporary location (a stack slot). 2386 2387 // NOTE: there is a choice here between constantly creating new stack 2388 // slots and always reusing the same one. We currently always create 2389 // new ones, as reuse may inhibit scheduling. 2390 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2391 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2392 Node->getValueType(0), dl); 2393 Results.push_back(Tmp1); 2394 break; 2395 } 2396 case ISD::SINT_TO_FP: 2397 case ISD::UINT_TO_FP: 2398 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2399 Node->getOperand(0), Node->getValueType(0), dl); 2400 Results.push_back(Tmp1); 2401 break; 2402 case ISD::FP_TO_UINT: { 2403 SDValue True, False; 2404 EVT VT = Node->getOperand(0).getValueType(); 2405 EVT NVT = Node->getValueType(0); 2406 const uint64_t zero[] = {0, 0}; 2407 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 2408 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2409 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2410 Tmp1 = DAG.getConstantFP(apf, VT); 2411 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2412 Node->getOperand(0), 2413 Tmp1, ISD::SETLT); 2414 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2415 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2416 DAG.getNode(ISD::FSUB, dl, VT, 2417 Node->getOperand(0), Tmp1)); 2418 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2419 DAG.getConstant(x, NVT)); 2420 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2421 Results.push_back(Tmp1); 2422 break; 2423 } 2424 case ISD::VAARG: { 2425 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2426 EVT VT = Node->getValueType(0); 2427 Tmp1 = Node->getOperand(0); 2428 Tmp2 = Node->getOperand(1); 2429 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0, 2430 false, false, 0); 2431 // Increment the pointer, VAList, to the next vaarg 2432 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2433 DAG.getConstant(TLI.getTargetData()-> 2434 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2435 TLI.getPointerTy())); 2436 // Store the incremented VAList to the legalized pointer 2437 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0, 2438 false, false, 0); 2439 // Load the actual argument out of the pointer VAList 2440 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0, 2441 false, false, 0)); 2442 Results.push_back(Results[0].getValue(1)); 2443 break; 2444 } 2445 case ISD::VACOPY: { 2446 // This defaults to loading a pointer from the input and storing it to the 2447 // output, returning the chain. 2448 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2449 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2450 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2451 Node->getOperand(2), VS, 0, false, false, 0); 2452 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0, 2453 false, false, 0); 2454 Results.push_back(Tmp1); 2455 break; 2456 } 2457 case ISD::EXTRACT_VECTOR_ELT: 2458 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2459 // This must be an access of the only element. Return it. 2460 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 2461 Node->getOperand(0)); 2462 else 2463 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2464 Results.push_back(Tmp1); 2465 break; 2466 case ISD::EXTRACT_SUBVECTOR: 2467 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2468 break; 2469 case ISD::CONCAT_VECTORS: { 2470 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2471 break; 2472 } 2473 case ISD::SCALAR_TO_VECTOR: 2474 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2475 break; 2476 case ISD::INSERT_VECTOR_ELT: 2477 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2478 Node->getOperand(1), 2479 Node->getOperand(2), dl)); 2480 break; 2481 case ISD::VECTOR_SHUFFLE: { 2482 SmallVector<int, 8> Mask; 2483 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2484 2485 EVT VT = Node->getValueType(0); 2486 EVT EltVT = VT.getVectorElementType(); 2487 unsigned NumElems = VT.getVectorNumElements(); 2488 SmallVector<SDValue, 8> Ops; 2489 for (unsigned i = 0; i != NumElems; ++i) { 2490 if (Mask[i] < 0) { 2491 Ops.push_back(DAG.getUNDEF(EltVT)); 2492 continue; 2493 } 2494 unsigned Idx = Mask[i]; 2495 if (Idx < NumElems) 2496 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2497 Node->getOperand(0), 2498 DAG.getIntPtrConstant(Idx))); 2499 else 2500 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2501 Node->getOperand(1), 2502 DAG.getIntPtrConstant(Idx - NumElems))); 2503 } 2504 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2505 Results.push_back(Tmp1); 2506 break; 2507 } 2508 case ISD::EXTRACT_ELEMENT: { 2509 EVT OpTy = Node->getOperand(0).getValueType(); 2510 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2511 // 1 -> Hi 2512 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2513 DAG.getConstant(OpTy.getSizeInBits()/2, 2514 TLI.getShiftAmountTy())); 2515 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2516 } else { 2517 // 0 -> Lo 2518 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2519 Node->getOperand(0)); 2520 } 2521 Results.push_back(Tmp1); 2522 break; 2523 } 2524 case ISD::STACKSAVE: 2525 // Expand to CopyFromReg if the target set 2526 // StackPointerRegisterToSaveRestore. 2527 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2528 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2529 Node->getValueType(0))); 2530 Results.push_back(Results[0].getValue(1)); 2531 } else { 2532 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2533 Results.push_back(Node->getOperand(0)); 2534 } 2535 break; 2536 case ISD::STACKRESTORE: 2537 // Expand to CopyToReg if the target set 2538 // StackPointerRegisterToSaveRestore. 2539 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2540 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2541 Node->getOperand(1))); 2542 } else { 2543 Results.push_back(Node->getOperand(0)); 2544 } 2545 break; 2546 case ISD::FCOPYSIGN: 2547 Results.push_back(ExpandFCOPYSIGN(Node)); 2548 break; 2549 case ISD::FNEG: 2550 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2551 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2552 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2553 Node->getOperand(0)); 2554 Results.push_back(Tmp1); 2555 break; 2556 case ISD::FABS: { 2557 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2558 EVT VT = Node->getValueType(0); 2559 Tmp1 = Node->getOperand(0); 2560 Tmp2 = DAG.getConstantFP(0.0, VT); 2561 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2562 Tmp1, Tmp2, ISD::SETUGT); 2563 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2564 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2565 Results.push_back(Tmp1); 2566 break; 2567 } 2568 case ISD::FSQRT: 2569 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2570 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2571 break; 2572 case ISD::FSIN: 2573 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2574 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2575 break; 2576 case ISD::FCOS: 2577 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2578 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2579 break; 2580 case ISD::FLOG: 2581 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2582 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2583 break; 2584 case ISD::FLOG2: 2585 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2586 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2587 break; 2588 case ISD::FLOG10: 2589 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2590 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2591 break; 2592 case ISD::FEXP: 2593 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2594 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2595 break; 2596 case ISD::FEXP2: 2597 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2598 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2599 break; 2600 case ISD::FTRUNC: 2601 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2602 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2603 break; 2604 case ISD::FFLOOR: 2605 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2606 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2607 break; 2608 case ISD::FCEIL: 2609 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2610 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2611 break; 2612 case ISD::FRINT: 2613 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2614 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2615 break; 2616 case ISD::FNEARBYINT: 2617 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2618 RTLIB::NEARBYINT_F64, 2619 RTLIB::NEARBYINT_F80, 2620 RTLIB::NEARBYINT_PPCF128)); 2621 break; 2622 case ISD::FPOWI: 2623 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2624 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2625 break; 2626 case ISD::FPOW: 2627 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 2628 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 2629 break; 2630 case ISD::FDIV: 2631 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 2632 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 2633 break; 2634 case ISD::FREM: 2635 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 2636 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 2637 break; 2638 case ISD::FP16_TO_FP32: 2639 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 2640 break; 2641 case ISD::FP32_TO_FP16: 2642 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 2643 break; 2644 case ISD::ConstantFP: { 2645 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 2646 // Check to see if this FP immediate is already legal. 2647 // If this is a legal constant, turn it into a TargetConstantFP node. 2648 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 2649 Results.push_back(SDValue(Node, 0)); 2650 else 2651 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 2652 break; 2653 } 2654 case ISD::EHSELECTION: { 2655 unsigned Reg = TLI.getExceptionSelectorRegister(); 2656 assert(Reg && "Can't expand to unknown register!"); 2657 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 2658 Node->getValueType(0))); 2659 Results.push_back(Results[0].getValue(1)); 2660 break; 2661 } 2662 case ISD::EXCEPTIONADDR: { 2663 unsigned Reg = TLI.getExceptionAddressRegister(); 2664 assert(Reg && "Can't expand to unknown register!"); 2665 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 2666 Node->getValueType(0))); 2667 Results.push_back(Results[0].getValue(1)); 2668 break; 2669 } 2670 case ISD::SUB: { 2671 EVT VT = Node->getValueType(0); 2672 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 2673 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 2674 "Don't know how to expand this subtraction!"); 2675 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 2676 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 2677 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 2678 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 2679 break; 2680 } 2681 case ISD::UREM: 2682 case ISD::SREM: { 2683 EVT VT = Node->getValueType(0); 2684 SDVTList VTs = DAG.getVTList(VT, VT); 2685 bool isSigned = Node->getOpcode() == ISD::SREM; 2686 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 2687 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2688 Tmp2 = Node->getOperand(0); 2689 Tmp3 = Node->getOperand(1); 2690 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 2691 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 2692 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 2693 // X % Y -> X-X/Y*Y 2694 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 2695 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 2696 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 2697 } else if (isSigned) { 2698 Tmp1 = ExpandIntLibCall(Node, true, 2699 RTLIB::SREM_I8, 2700 RTLIB::SREM_I16, RTLIB::SREM_I32, 2701 RTLIB::SREM_I64, RTLIB::SREM_I128); 2702 } else { 2703 Tmp1 = ExpandIntLibCall(Node, false, 2704 RTLIB::UREM_I8, 2705 RTLIB::UREM_I16, RTLIB::UREM_I32, 2706 RTLIB::UREM_I64, RTLIB::UREM_I128); 2707 } 2708 Results.push_back(Tmp1); 2709 break; 2710 } 2711 case ISD::UDIV: 2712 case ISD::SDIV: { 2713 bool isSigned = Node->getOpcode() == ISD::SDIV; 2714 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2715 EVT VT = Node->getValueType(0); 2716 SDVTList VTs = DAG.getVTList(VT, VT); 2717 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 2718 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 2719 Node->getOperand(1)); 2720 else if (isSigned) 2721 Tmp1 = ExpandIntLibCall(Node, true, 2722 RTLIB::SDIV_I8, 2723 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 2724 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 2725 else 2726 Tmp1 = ExpandIntLibCall(Node, false, 2727 RTLIB::UDIV_I8, 2728 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 2729 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 2730 Results.push_back(Tmp1); 2731 break; 2732 } 2733 case ISD::MULHU: 2734 case ISD::MULHS: { 2735 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 2736 ISD::SMUL_LOHI; 2737 EVT VT = Node->getValueType(0); 2738 SDVTList VTs = DAG.getVTList(VT, VT); 2739 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 2740 "If this wasn't legal, it shouldn't have been created!"); 2741 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 2742 Node->getOperand(1)); 2743 Results.push_back(Tmp1.getValue(1)); 2744 break; 2745 } 2746 case ISD::MUL: { 2747 EVT VT = Node->getValueType(0); 2748 SDVTList VTs = DAG.getVTList(VT, VT); 2749 // See if multiply or divide can be lowered using two-result operations. 2750 // We just need the low half of the multiply; try both the signed 2751 // and unsigned forms. If the target supports both SMUL_LOHI and 2752 // UMUL_LOHI, form a preference by checking which forms of plain 2753 // MULH it supports. 2754 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 2755 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 2756 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 2757 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 2758 unsigned OpToUse = 0; 2759 if (HasSMUL_LOHI && !HasMULHS) { 2760 OpToUse = ISD::SMUL_LOHI; 2761 } else if (HasUMUL_LOHI && !HasMULHU) { 2762 OpToUse = ISD::UMUL_LOHI; 2763 } else if (HasSMUL_LOHI) { 2764 OpToUse = ISD::SMUL_LOHI; 2765 } else if (HasUMUL_LOHI) { 2766 OpToUse = ISD::UMUL_LOHI; 2767 } 2768 if (OpToUse) { 2769 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 2770 Node->getOperand(1))); 2771 break; 2772 } 2773 Tmp1 = ExpandIntLibCall(Node, false, 2774 RTLIB::MUL_I8, 2775 RTLIB::MUL_I16, RTLIB::MUL_I32, 2776 RTLIB::MUL_I64, RTLIB::MUL_I128); 2777 Results.push_back(Tmp1); 2778 break; 2779 } 2780 case ISD::SADDO: 2781 case ISD::SSUBO: { 2782 SDValue LHS = Node->getOperand(0); 2783 SDValue RHS = Node->getOperand(1); 2784 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 2785 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2786 LHS, RHS); 2787 Results.push_back(Sum); 2788 EVT OType = Node->getValueType(1); 2789 2790 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 2791 2792 // LHSSign -> LHS >= 0 2793 // RHSSign -> RHS >= 0 2794 // SumSign -> Sum >= 0 2795 // 2796 // Add: 2797 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 2798 // Sub: 2799 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 2800 // 2801 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 2802 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 2803 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 2804 Node->getOpcode() == ISD::SADDO ? 2805 ISD::SETEQ : ISD::SETNE); 2806 2807 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 2808 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 2809 2810 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 2811 Results.push_back(Cmp); 2812 break; 2813 } 2814 case ISD::UADDO: 2815 case ISD::USUBO: { 2816 SDValue LHS = Node->getOperand(0); 2817 SDValue RHS = Node->getOperand(1); 2818 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 2819 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2820 LHS, RHS); 2821 Results.push_back(Sum); 2822 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 2823 Node->getOpcode () == ISD::UADDO ? 2824 ISD::SETULT : ISD::SETUGT)); 2825 break; 2826 } 2827 case ISD::UMULO: 2828 case ISD::SMULO: { 2829 EVT VT = Node->getValueType(0); 2830 SDValue LHS = Node->getOperand(0); 2831 SDValue RHS = Node->getOperand(1); 2832 SDValue BottomHalf; 2833 SDValue TopHalf; 2834 static const unsigned Ops[2][3] = 2835 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 2836 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 2837 bool isSigned = Node->getOpcode() == ISD::SMULO; 2838 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 2839 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 2840 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 2841 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 2842 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 2843 RHS); 2844 TopHalf = BottomHalf.getValue(1); 2845 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2))) { 2846 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 2847 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 2848 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 2849 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 2850 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2851 DAG.getIntPtrConstant(0)); 2852 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2853 DAG.getIntPtrConstant(1)); 2854 } else { 2855 // FIXME: We should be able to fall back to a libcall with an illegal 2856 // type in some cases. 2857 // Also, we can fall back to a division in some cases, but that's a big 2858 // performance hit in the general case. 2859 llvm_unreachable("Don't know how to expand this operation yet!"); 2860 } 2861 if (isSigned) { 2862 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); 2863 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 2864 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 2865 ISD::SETNE); 2866 } else { 2867 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 2868 DAG.getConstant(0, VT), ISD::SETNE); 2869 } 2870 Results.push_back(BottomHalf); 2871 Results.push_back(TopHalf); 2872 break; 2873 } 2874 case ISD::BUILD_PAIR: { 2875 EVT PairTy = Node->getValueType(0); 2876 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 2877 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 2878 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 2879 DAG.getConstant(PairTy.getSizeInBits()/2, 2880 TLI.getShiftAmountTy())); 2881 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 2882 break; 2883 } 2884 case ISD::SELECT: 2885 Tmp1 = Node->getOperand(0); 2886 Tmp2 = Node->getOperand(1); 2887 Tmp3 = Node->getOperand(2); 2888 if (Tmp1.getOpcode() == ISD::SETCC) { 2889 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 2890 Tmp2, Tmp3, 2891 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2892 } else { 2893 Tmp1 = DAG.getSelectCC(dl, Tmp1, 2894 DAG.getConstant(0, Tmp1.getValueType()), 2895 Tmp2, Tmp3, ISD::SETNE); 2896 } 2897 Results.push_back(Tmp1); 2898 break; 2899 case ISD::BR_JT: { 2900 SDValue Chain = Node->getOperand(0); 2901 SDValue Table = Node->getOperand(1); 2902 SDValue Index = Node->getOperand(2); 2903 2904 EVT PTy = TLI.getPointerTy(); 2905 2906 const TargetData &TD = *TLI.getTargetData(); 2907 unsigned EntrySize = 2908 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 2909 2910 Index = DAG.getNode(ISD::MUL, dl, PTy, 2911 Index, DAG.getConstant(EntrySize, PTy)); 2912 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2913 2914 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 2915 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 2916 PseudoSourceValue::getJumpTable(), 0, MemVT, 2917 false, false, 0); 2918 Addr = LD; 2919 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2920 // For PIC, the sequence is: 2921 // BRIND(load(Jumptable + index) + RelocBase) 2922 // RelocBase can be JumpTable, GOT or some sort of global base. 2923 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 2924 TLI.getPICJumpTableRelocBase(Table, DAG)); 2925 } 2926 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 2927 Results.push_back(Tmp1); 2928 break; 2929 } 2930 case ISD::BRCOND: 2931 // Expand brcond's setcc into its constituent parts and create a BR_CC 2932 // Node. 2933 Tmp1 = Node->getOperand(0); 2934 Tmp2 = Node->getOperand(1); 2935 if (Tmp2.getOpcode() == ISD::SETCC) { 2936 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 2937 Tmp1, Tmp2.getOperand(2), 2938 Tmp2.getOperand(0), Tmp2.getOperand(1), 2939 Node->getOperand(2)); 2940 } else { 2941 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 2942 DAG.getCondCode(ISD::SETNE), Tmp2, 2943 DAG.getConstant(0, Tmp2.getValueType()), 2944 Node->getOperand(2)); 2945 } 2946 Results.push_back(Tmp1); 2947 break; 2948 case ISD::SETCC: { 2949 Tmp1 = Node->getOperand(0); 2950 Tmp2 = Node->getOperand(1); 2951 Tmp3 = Node->getOperand(2); 2952 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 2953 2954 // If we expanded the SETCC into an AND/OR, return the new node 2955 if (Tmp2.getNode() == 0) { 2956 Results.push_back(Tmp1); 2957 break; 2958 } 2959 2960 // Otherwise, SETCC for the given comparison type must be completely 2961 // illegal; expand it into a SELECT_CC. 2962 EVT VT = Node->getValueType(0); 2963 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 2964 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 2965 Results.push_back(Tmp1); 2966 break; 2967 } 2968 case ISD::SELECT_CC: { 2969 Tmp1 = Node->getOperand(0); // LHS 2970 Tmp2 = Node->getOperand(1); // RHS 2971 Tmp3 = Node->getOperand(2); // True 2972 Tmp4 = Node->getOperand(3); // False 2973 SDValue CC = Node->getOperand(4); 2974 2975 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 2976 Tmp1, Tmp2, CC, dl); 2977 2978 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 2979 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2980 CC = DAG.getCondCode(ISD::SETNE); 2981 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 2982 Tmp3, Tmp4, CC); 2983 Results.push_back(Tmp1); 2984 break; 2985 } 2986 case ISD::BR_CC: { 2987 Tmp1 = Node->getOperand(0); // Chain 2988 Tmp2 = Node->getOperand(2); // LHS 2989 Tmp3 = Node->getOperand(3); // RHS 2990 Tmp4 = Node->getOperand(1); // CC 2991 2992 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 2993 Tmp2, Tmp3, Tmp4, dl); 2994 LastCALLSEQ_END = DAG.getEntryNode(); 2995 2996 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 2997 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 2998 Tmp4 = DAG.getCondCode(ISD::SETNE); 2999 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 3000 Tmp3, Node->getOperand(4)); 3001 Results.push_back(Tmp1); 3002 break; 3003 } 3004 case ISD::GLOBAL_OFFSET_TABLE: 3005 case ISD::GlobalAddress: 3006 case ISD::GlobalTLSAddress: 3007 case ISD::ExternalSymbol: 3008 case ISD::ConstantPool: 3009 case ISD::JumpTable: 3010 case ISD::INTRINSIC_W_CHAIN: 3011 case ISD::INTRINSIC_WO_CHAIN: 3012 case ISD::INTRINSIC_VOID: 3013 // FIXME: Custom lowering for these operations shouldn't return null! 3014 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3015 Results.push_back(SDValue(Node, i)); 3016 break; 3017 } 3018} 3019void SelectionDAGLegalize::PromoteNode(SDNode *Node, 3020 SmallVectorImpl<SDValue> &Results) { 3021 EVT OVT = Node->getValueType(0); 3022 if (Node->getOpcode() == ISD::UINT_TO_FP || 3023 Node->getOpcode() == ISD::SINT_TO_FP || 3024 Node->getOpcode() == ISD::SETCC) { 3025 OVT = Node->getOperand(0).getValueType(); 3026 } 3027 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3028 DebugLoc dl = Node->getDebugLoc(); 3029 SDValue Tmp1, Tmp2, Tmp3; 3030 switch (Node->getOpcode()) { 3031 case ISD::CTTZ: 3032 case ISD::CTLZ: 3033 case ISD::CTPOP: 3034 // Zero extend the argument. 3035 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3036 // Perform the larger operation. 3037 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3038 if (Node->getOpcode() == ISD::CTTZ) { 3039 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3040 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 3041 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3042 ISD::SETEQ); 3043 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3044 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3045 } else if (Node->getOpcode() == ISD::CTLZ) { 3046 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3047 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3048 DAG.getConstant(NVT.getSizeInBits() - 3049 OVT.getSizeInBits(), NVT)); 3050 } 3051 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3052 break; 3053 case ISD::BSWAP: { 3054 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3055 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3056 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3057 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3058 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3059 Results.push_back(Tmp1); 3060 break; 3061 } 3062 case ISD::FP_TO_UINT: 3063 case ISD::FP_TO_SINT: 3064 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3065 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3066 Results.push_back(Tmp1); 3067 break; 3068 case ISD::UINT_TO_FP: 3069 case ISD::SINT_TO_FP: 3070 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3071 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3072 Results.push_back(Tmp1); 3073 break; 3074 case ISD::AND: 3075 case ISD::OR: 3076 case ISD::XOR: { 3077 unsigned ExtOp, TruncOp; 3078 if (OVT.isVector()) { 3079 ExtOp = ISD::BIT_CONVERT; 3080 TruncOp = ISD::BIT_CONVERT; 3081 } else if (OVT.isInteger()) { 3082 ExtOp = ISD::ANY_EXTEND; 3083 TruncOp = ISD::TRUNCATE; 3084 } else { 3085 llvm_report_error("Cannot promote logic operation"); 3086 } 3087 // Promote each of the values to the new type. 3088 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3089 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3090 // Perform the larger operation, then convert back 3091 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3092 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3093 break; 3094 } 3095 case ISD::SELECT: { 3096 unsigned ExtOp, TruncOp; 3097 if (Node->getValueType(0).isVector()) { 3098 ExtOp = ISD::BIT_CONVERT; 3099 TruncOp = ISD::BIT_CONVERT; 3100 } else if (Node->getValueType(0).isInteger()) { 3101 ExtOp = ISD::ANY_EXTEND; 3102 TruncOp = ISD::TRUNCATE; 3103 } else { 3104 ExtOp = ISD::FP_EXTEND; 3105 TruncOp = ISD::FP_ROUND; 3106 } 3107 Tmp1 = Node->getOperand(0); 3108 // Promote each of the values to the new type. 3109 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3110 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3111 // Perform the larger operation, then round down. 3112 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3113 if (TruncOp != ISD::FP_ROUND) 3114 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3115 else 3116 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3117 DAG.getIntPtrConstant(0)); 3118 Results.push_back(Tmp1); 3119 break; 3120 } 3121 case ISD::VECTOR_SHUFFLE: { 3122 SmallVector<int, 8> Mask; 3123 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3124 3125 // Cast the two input vectors. 3126 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3127 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3128 3129 // Convert the shuffle mask to the right # elements. 3130 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3131 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); 3132 Results.push_back(Tmp1); 3133 break; 3134 } 3135 case ISD::SETCC: { 3136 unsigned ExtOp = ISD::FP_EXTEND; 3137 if (NVT.isInteger()) { 3138 ISD::CondCode CCCode = 3139 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3140 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3141 } 3142 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3143 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3144 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3145 Tmp1, Tmp2, Node->getOperand(2))); 3146 break; 3147 } 3148 } 3149} 3150 3151// SelectionDAG::Legalize - This is the entry point for the file. 3152// 3153void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) { 3154 /// run - This is the main entry point to this class. 3155 /// 3156 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3157} 3158 3159