LegalizeDAG.cpp revision 8e23e815ad1136721acdfcce76975a37c8a2c036
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Analysis/DebugInfo.h" 15#include "llvm/CodeGen/Analysis.h" 16#include "llvm/CodeGen/MachineFunction.h" 17#include "llvm/CodeGen/MachineFrameInfo.h" 18#include "llvm/CodeGen/MachineJumpTableInfo.h" 19#include "llvm/CodeGen/MachineModuleInfo.h" 20#include "llvm/CodeGen/PseudoSourceValue.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/Target/TargetFrameLowering.h" 23#include "llvm/Target/TargetLowering.h" 24#include "llvm/Target/TargetData.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/CallingConv.h" 28#include "llvm/Constants.h" 29#include "llvm/DerivedTypes.h" 30#include "llvm/Function.h" 31#include "llvm/GlobalVariable.h" 32#include "llvm/LLVMContext.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/raw_ostream.h" 38#include "llvm/ADT/DenseMap.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/ADT/SmallPtrSet.h" 41using namespace llvm; 42 43//===----------------------------------------------------------------------===// 44/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 45/// hacks on it until the target machine can handle it. This involves 46/// eliminating value sizes the machine cannot handle (promoting small sizes to 47/// large sizes or splitting up large values into small values) as well as 48/// eliminating operations the machine cannot handle. 49/// 50/// This code also does a small amount of optimization and recognition of idioms 51/// as part of its processing. For example, if a target does not support a 52/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 53/// will attempt merge setcc and brc instructions into brcc's. 54/// 55namespace { 56class SelectionDAGLegalize { 57 const TargetMachine &TM; 58 const TargetLowering &TLI; 59 SelectionDAG &DAG; 60 CodeGenOpt::Level OptLevel; 61 62 // Libcall insertion helpers. 63 64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 65 /// legalized. We use this to ensure that calls are properly serialized 66 /// against each other, including inserted libcalls. 67 SDValue LastCALLSEQ_END; 68 69 enum LegalizeAction { 70 Legal, // The target natively supports this operation. 71 Promote, // This operation should be executed in a larger type. 72 Expand // Try to expand this to other ops, otherwise use a libcall. 73 }; 74 75 /// ValueTypeActions - This is a bitvector that contains two bits for each 76 /// value type, where the two bits correspond to the LegalizeAction enum. 77 /// This can be queried with "getTypeAction(VT)". 78 TargetLowering::ValueTypeActionImpl ValueTypeActions; 79 80 /// LegalizedNodes - For nodes that are of legal width, and that have more 81 /// than one use, this map indicates what regularized operand to use. This 82 /// allows us to avoid legalizing the same thing more than once. 83 DenseMap<SDValue, SDValue> LegalizedNodes; 84 85 void AddLegalizedOperand(SDValue From, SDValue To) { 86 LegalizedNodes.insert(std::make_pair(From, To)); 87 // If someone requests legalization of the new node, return itself. 88 if (From != To) 89 LegalizedNodes.insert(std::make_pair(To, To)); 90 91 // Transfer SDDbgValues. 92 DAG.TransferDbgValues(From, To); 93 } 94 95public: 96 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 97 98 /// getTypeAction - Return how we should legalize values of this type, either 99 /// it is already legal or we need to expand it into multiple registers of 100 /// smaller integer type, or we need to promote it to a larger type. 101 LegalizeAction getTypeAction(EVT VT) const { 102 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 103 } 104 105 /// isTypeLegal - Return true if this type is legal on this target. 106 /// 107 bool isTypeLegal(EVT VT) const { 108 return getTypeAction(VT) == Legal; 109 } 110 111 void LegalizeDAG(); 112 113private: 114 /// LegalizeOp - We know that the specified value has a legal type. 115 /// Recursively ensure that the operands have legal types, then return the 116 /// result. 117 SDValue LegalizeOp(SDValue O); 118 119 SDValue OptimizeFloatStore(StoreSDNode *ST); 120 121 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 122 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 123 /// is necessary to spill the vector being inserted into to memory, perform 124 /// the insert there, and then read the result back. 125 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 126 SDValue Idx, DebugLoc dl); 127 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 128 SDValue Idx, DebugLoc dl); 129 130 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 131 /// performs the same shuffe in terms of order or result bytes, but on a type 132 /// whose vector element type is narrower than the original shuffle type. 133 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 134 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 135 SDValue N1, SDValue N2, 136 SmallVectorImpl<int> &Mask) const; 137 138 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 139 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 140 141 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 142 DebugLoc dl); 143 144 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 145 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC, 146 SDNode *Node, bool isSigned); 147 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 148 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 149 RTLIB::Libcall Call_PPCF128); 150 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 151 RTLIB::Libcall Call_I8, 152 RTLIB::Libcall Call_I16, 153 RTLIB::Libcall Call_I32, 154 RTLIB::Libcall Call_I64, 155 RTLIB::Libcall Call_I128); 156 SDValue ExpandDivRemLibCall(SDNode *Node, bool isSigned, bool isDIV); 157 158 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 159 SDValue ExpandBUILD_VECTOR(SDNode *Node); 160 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 161 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 162 SmallVectorImpl<SDValue> &Results); 163 SDValue ExpandFCOPYSIGN(SDNode *Node); 164 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 165 DebugLoc dl); 166 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 167 DebugLoc dl); 168 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 169 DebugLoc dl); 170 171 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 172 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 173 174 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 175 SDValue ExpandInsertToVectorThroughStack(SDValue Op); 176 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 177 178 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node); 179 180 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 181 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 182}; 183} 184 185/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 186/// performs the same shuffe in terms of order or result bytes, but on a type 187/// whose vector element type is narrower than the original shuffle type. 188/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 189SDValue 190SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 191 SDValue N1, SDValue N2, 192 SmallVectorImpl<int> &Mask) const { 193 unsigned NumMaskElts = VT.getVectorNumElements(); 194 unsigned NumDestElts = NVT.getVectorNumElements(); 195 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 196 197 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 198 199 if (NumEltsGrowth == 1) 200 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 201 202 SmallVector<int, 8> NewMask; 203 for (unsigned i = 0; i != NumMaskElts; ++i) { 204 int Idx = Mask[i]; 205 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 206 if (Idx < 0) 207 NewMask.push_back(-1); 208 else 209 NewMask.push_back(Idx * NumEltsGrowth + j); 210 } 211 } 212 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 213 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 214 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 215} 216 217SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 218 CodeGenOpt::Level ol) 219 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 220 DAG(dag), OptLevel(ol), 221 ValueTypeActions(TLI.getValueTypeActions()) { 222 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 223 "Too many value types for ValueTypeActions to hold!"); 224} 225 226void SelectionDAGLegalize::LegalizeDAG() { 227 LastCALLSEQ_END = DAG.getEntryNode(); 228 229 // The legalize process is inherently a bottom-up recursive process (users 230 // legalize their uses before themselves). Given infinite stack space, we 231 // could just start legalizing on the root and traverse the whole graph. In 232 // practice however, this causes us to run out of stack space on large basic 233 // blocks. To avoid this problem, compute an ordering of the nodes where each 234 // node is only legalized after all of its operands are legalized. 235 DAG.AssignTopologicalOrder(); 236 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 237 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 238 LegalizeOp(SDValue(I, 0)); 239 240 // Finally, it's possible the root changed. Get the new root. 241 SDValue OldRoot = DAG.getRoot(); 242 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 243 DAG.setRoot(LegalizedNodes[OldRoot]); 244 245 LegalizedNodes.clear(); 246 247 // Remove dead nodes now. 248 DAG.RemoveDeadNodes(); 249} 250 251 252/// FindCallEndFromCallStart - Given a chained node that is part of a call 253/// sequence, find the CALLSEQ_END node that terminates the call sequence. 254static SDNode *FindCallEndFromCallStart(SDNode *Node, int depth = 0) { 255 // Nested CALLSEQ_START/END constructs aren't yet legal, 256 // but we can DTRT and handle them correctly here. 257 if (Node->getOpcode() == ISD::CALLSEQ_START) 258 depth++; 259 else if (Node->getOpcode() == ISD::CALLSEQ_END) { 260 depth--; 261 if (depth == 0) 262 return Node; 263 } 264 if (Node->use_empty()) 265 return 0; // No CallSeqEnd 266 267 // The chain is usually at the end. 268 SDValue TheChain(Node, Node->getNumValues()-1); 269 if (TheChain.getValueType() != MVT::Other) { 270 // Sometimes it's at the beginning. 271 TheChain = SDValue(Node, 0); 272 if (TheChain.getValueType() != MVT::Other) { 273 // Otherwise, hunt for it. 274 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 275 if (Node->getValueType(i) == MVT::Other) { 276 TheChain = SDValue(Node, i); 277 break; 278 } 279 280 // Otherwise, we walked into a node without a chain. 281 if (TheChain.getValueType() != MVT::Other) 282 return 0; 283 } 284 } 285 286 for (SDNode::use_iterator UI = Node->use_begin(), 287 E = Node->use_end(); UI != E; ++UI) { 288 289 // Make sure to only follow users of our token chain. 290 SDNode *User = *UI; 291 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 292 if (User->getOperand(i) == TheChain) 293 if (SDNode *Result = FindCallEndFromCallStart(User, depth)) 294 return Result; 295 } 296 return 0; 297} 298 299/// FindCallStartFromCallEnd - Given a chained node that is part of a call 300/// sequence, find the CALLSEQ_START node that initiates the call sequence. 301static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 302 int nested = 0; 303 assert(Node && "Didn't find callseq_start for a call??"); 304 while (Node->getOpcode() != ISD::CALLSEQ_START || nested) { 305 Node = Node->getOperand(0).getNode(); 306 assert(Node->getOperand(0).getValueType() == MVT::Other && 307 "Node doesn't have a token chain argument!"); 308 switch (Node->getOpcode()) { 309 default: 310 break; 311 case ISD::CALLSEQ_START: 312 if (!nested) 313 return Node; 314 nested--; 315 break; 316 case ISD::CALLSEQ_END: 317 nested++; 318 break; 319 } 320 } 321 return 0; 322} 323 324/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 325/// see if any uses can reach Dest. If no dest operands can get to dest, 326/// legalize them, legalize ourself, and return false, otherwise, return true. 327/// 328/// Keep track of the nodes we fine that actually do lead to Dest in 329/// NodesLeadingTo. This avoids retraversing them exponential number of times. 330/// 331bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 332 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 333 if (N == Dest) return true; // N certainly leads to Dest :) 334 335 // If we've already processed this node and it does lead to Dest, there is no 336 // need to reprocess it. 337 if (NodesLeadingTo.count(N)) return true; 338 339 // If the first result of this node has been already legalized, then it cannot 340 // reach N. 341 if (LegalizedNodes.count(SDValue(N, 0))) return false; 342 343 // Okay, this node has not already been legalized. Check and legalize all 344 // operands. If none lead to Dest, then we can legalize this node. 345 bool OperandsLeadToDest = false; 346 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 347 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 348 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, 349 NodesLeadingTo); 350 351 if (OperandsLeadToDest) { 352 NodesLeadingTo.insert(N); 353 return true; 354 } 355 356 // Okay, this node looks safe, legalize it and return false. 357 LegalizeOp(SDValue(N, 0)); 358 return false; 359} 360 361/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 362/// a load from the constant pool. 363static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 364 SelectionDAG &DAG, const TargetLowering &TLI) { 365 bool Extend = false; 366 DebugLoc dl = CFP->getDebugLoc(); 367 368 // If a FP immediate is precise when represented as a float and if the 369 // target can do an extending load from float to double, we put it into 370 // the constant pool as a float, even if it's is statically typed as a 371 // double. This shrinks FP constants and canonicalizes them for targets where 372 // an FP extending load is the same cost as a normal load (such as on the x87 373 // fp stack or PPC FP unit). 374 EVT VT = CFP->getValueType(0); 375 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 376 if (!UseCP) { 377 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 378 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 379 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 380 } 381 382 EVT OrigVT = VT; 383 EVT SVT = VT; 384 while (SVT != MVT::f32) { 385 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 386 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) && 387 // Only do this if the target has a native EXTLOAD instruction from 388 // smaller type. 389 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 390 TLI.ShouldShrinkFPConstant(OrigVT)) { 391 const Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 392 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 393 VT = SVT; 394 Extend = true; 395 } 396 } 397 398 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 399 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 400 if (Extend) 401 return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, 402 DAG.getEntryNode(), 403 CPIdx, MachinePointerInfo::getConstantPool(), 404 VT, false, false, Alignment); 405 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 406 MachinePointerInfo::getConstantPool(), false, false, 407 Alignment); 408} 409 410/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 411static 412SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 413 const TargetLowering &TLI) { 414 SDValue Chain = ST->getChain(); 415 SDValue Ptr = ST->getBasePtr(); 416 SDValue Val = ST->getValue(); 417 EVT VT = Val.getValueType(); 418 int Alignment = ST->getAlignment(); 419 DebugLoc dl = ST->getDebugLoc(); 420 if (ST->getMemoryVT().isFloatingPoint() || 421 ST->getMemoryVT().isVector()) { 422 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 423 if (TLI.isTypeLegal(intVT)) { 424 // Expand to a bitconvert of the value to the integer type of the 425 // same size, then a (misaligned) int store. 426 // FIXME: Does not handle truncating floating point stores! 427 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); 428 return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(), 429 ST->isVolatile(), ST->isNonTemporal(), Alignment); 430 } else { 431 // Do a (aligned) store to a stack slot, then copy from the stack slot 432 // to the final destination using (unaligned) integer loads and stores. 433 EVT StoredVT = ST->getMemoryVT(); 434 EVT RegVT = 435 TLI.getRegisterType(*DAG.getContext(), 436 EVT::getIntegerVT(*DAG.getContext(), 437 StoredVT.getSizeInBits())); 438 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 439 unsigned RegBytes = RegVT.getSizeInBits() / 8; 440 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 441 442 // Make sure the stack slot is also aligned for the register type. 443 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 444 445 // Perform the original store, only redirected to the stack slot. 446 SDValue Store = DAG.getTruncStore(Chain, dl, 447 Val, StackPtr, MachinePointerInfo(), 448 StoredVT, false, false, 0); 449 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 450 SmallVector<SDValue, 8> Stores; 451 unsigned Offset = 0; 452 453 // Do all but one copies using the full register width. 454 for (unsigned i = 1; i < NumRegs; i++) { 455 // Load one integer register's worth from the stack slot. 456 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, 457 MachinePointerInfo(), 458 false, false, 0); 459 // Store it to the final location. Remember the store. 460 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 461 ST->getPointerInfo().getWithOffset(Offset), 462 ST->isVolatile(), ST->isNonTemporal(), 463 MinAlign(ST->getAlignment(), Offset))); 464 // Increment the pointers. 465 Offset += RegBytes; 466 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 467 Increment); 468 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 469 } 470 471 // The last store may be partial. Do a truncating store. On big-endian 472 // machines this requires an extending load from the stack slot to ensure 473 // that the bits are in the right place. 474 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 475 8 * (StoredBytes - Offset)); 476 477 // Load from the stack slot. 478 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 479 MachinePointerInfo(), 480 MemVT, false, false, 0); 481 482 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 483 ST->getPointerInfo() 484 .getWithOffset(Offset), 485 MemVT, ST->isVolatile(), 486 ST->isNonTemporal(), 487 MinAlign(ST->getAlignment(), Offset))); 488 // The order of the stores doesn't matter - say it with a TokenFactor. 489 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 490 Stores.size()); 491 } 492 } 493 assert(ST->getMemoryVT().isInteger() && 494 !ST->getMemoryVT().isVector() && 495 "Unaligned store of unknown type."); 496 // Get the half-size VT 497 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 498 int NumBits = NewStoredVT.getSizeInBits(); 499 int IncrementSize = NumBits / 8; 500 501 // Divide the stored value in two parts. 502 SDValue ShiftAmount = DAG.getConstant(NumBits, 503 TLI.getShiftAmountTy(Val.getValueType())); 504 SDValue Lo = Val; 505 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 506 507 // Store the two parts 508 SDValue Store1, Store2; 509 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 510 ST->getPointerInfo(), NewStoredVT, 511 ST->isVolatile(), ST->isNonTemporal(), Alignment); 512 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 513 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 514 Alignment = MinAlign(Alignment, IncrementSize); 515 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 516 ST->getPointerInfo().getWithOffset(IncrementSize), 517 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 518 Alignment); 519 520 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 521} 522 523/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 524static 525SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 526 const TargetLowering &TLI) { 527 SDValue Chain = LD->getChain(); 528 SDValue Ptr = LD->getBasePtr(); 529 EVT VT = LD->getValueType(0); 530 EVT LoadedVT = LD->getMemoryVT(); 531 DebugLoc dl = LD->getDebugLoc(); 532 if (VT.isFloatingPoint() || VT.isVector()) { 533 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 534 if (TLI.isTypeLegal(intVT)) { 535 // Expand to a (misaligned) integer load of the same size, 536 // then bitconvert to floating point or vector. 537 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(), 538 LD->isVolatile(), 539 LD->isNonTemporal(), LD->getAlignment()); 540 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); 541 if (VT.isFloatingPoint() && LoadedVT != VT) 542 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 543 544 SDValue Ops[] = { Result, Chain }; 545 return DAG.getMergeValues(Ops, 2, dl); 546 } 547 548 // Copy the value to a (aligned) stack slot using (unaligned) integer 549 // loads and stores, then do a (aligned) load from the stack slot. 550 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 551 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 552 unsigned RegBytes = RegVT.getSizeInBits() / 8; 553 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 554 555 // Make sure the stack slot is also aligned for the register type. 556 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 557 558 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 559 SmallVector<SDValue, 8> Stores; 560 SDValue StackPtr = StackBase; 561 unsigned Offset = 0; 562 563 // Do all but one copies using the full register width. 564 for (unsigned i = 1; i < NumRegs; i++) { 565 // Load one integer register's worth from the original location. 566 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, 567 LD->getPointerInfo().getWithOffset(Offset), 568 LD->isVolatile(), LD->isNonTemporal(), 569 MinAlign(LD->getAlignment(), Offset)); 570 // Follow the load with a store to the stack slot. Remember the store. 571 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 572 MachinePointerInfo(), false, false, 0)); 573 // Increment the pointers. 574 Offset += RegBytes; 575 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 576 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 577 Increment); 578 } 579 580 // The last copy may be partial. Do an extending load. 581 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 582 8 * (LoadedBytes - Offset)); 583 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 584 LD->getPointerInfo().getWithOffset(Offset), 585 MemVT, LD->isVolatile(), 586 LD->isNonTemporal(), 587 MinAlign(LD->getAlignment(), Offset)); 588 // Follow the load with a store to the stack slot. Remember the store. 589 // On big-endian machines this requires a truncating store to ensure 590 // that the bits end up in the right place. 591 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 592 MachinePointerInfo(), MemVT, 593 false, false, 0)); 594 595 // The order of the stores doesn't matter - say it with a TokenFactor. 596 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 597 Stores.size()); 598 599 // Finally, perform the original load only redirected to the stack slot. 600 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 601 MachinePointerInfo(), LoadedVT, false, false, 0); 602 603 // Callers expect a MERGE_VALUES node. 604 SDValue Ops[] = { Load, TF }; 605 return DAG.getMergeValues(Ops, 2, dl); 606 } 607 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 608 "Unaligned load of unsupported type."); 609 610 // Compute the new VT that is half the size of the old one. This is an 611 // integer MVT. 612 unsigned NumBits = LoadedVT.getSizeInBits(); 613 EVT NewLoadedVT; 614 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 615 NumBits >>= 1; 616 617 unsigned Alignment = LD->getAlignment(); 618 unsigned IncrementSize = NumBits / 8; 619 ISD::LoadExtType HiExtType = LD->getExtensionType(); 620 621 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 622 if (HiExtType == ISD::NON_EXTLOAD) 623 HiExtType = ISD::ZEXTLOAD; 624 625 // Load the value in two parts 626 SDValue Lo, Hi; 627 if (TLI.isLittleEndian()) { 628 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), 629 NewLoadedVT, LD->isVolatile(), 630 LD->isNonTemporal(), Alignment); 631 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 632 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 633 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, 634 LD->getPointerInfo().getWithOffset(IncrementSize), 635 NewLoadedVT, LD->isVolatile(), 636 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 637 } else { 638 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(), 639 NewLoadedVT, LD->isVolatile(), 640 LD->isNonTemporal(), Alignment); 641 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 642 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 643 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, 644 LD->getPointerInfo().getWithOffset(IncrementSize), 645 NewLoadedVT, LD->isVolatile(), 646 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 647 } 648 649 // aggregate the two parts 650 SDValue ShiftAmount = DAG.getConstant(NumBits, 651 TLI.getShiftAmountTy(Hi.getValueType())); 652 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 653 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 654 655 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 656 Hi.getValue(1)); 657 658 SDValue Ops[] = { Result, TF }; 659 return DAG.getMergeValues(Ops, 2, dl); 660} 661 662/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 663/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 664/// is necessary to spill the vector being inserted into to memory, perform 665/// the insert there, and then read the result back. 666SDValue SelectionDAGLegalize:: 667PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 668 DebugLoc dl) { 669 SDValue Tmp1 = Vec; 670 SDValue Tmp2 = Val; 671 SDValue Tmp3 = Idx; 672 673 // If the target doesn't support this, we have to spill the input vector 674 // to a temporary stack slot, update the element, then reload it. This is 675 // badness. We could also load the value into a vector register (either 676 // with a "move to register" or "extload into register" instruction, then 677 // permute it into place, if the idx is a constant and if the idx is 678 // supported by the target. 679 EVT VT = Tmp1.getValueType(); 680 EVT EltVT = VT.getVectorElementType(); 681 EVT IdxVT = Tmp3.getValueType(); 682 EVT PtrVT = TLI.getPointerTy(); 683 SDValue StackPtr = DAG.CreateStackTemporary(VT); 684 685 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 686 687 // Store the vector. 688 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 689 MachinePointerInfo::getFixedStack(SPFI), 690 false, false, 0); 691 692 // Truncate or zero extend offset to target pointer type. 693 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 694 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 695 // Add the offset to the index. 696 unsigned EltSize = EltVT.getSizeInBits()/8; 697 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 698 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 699 // Store the scalar value. 700 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT, 701 false, false, 0); 702 // Load the updated vector. 703 return DAG.getLoad(VT, dl, Ch, StackPtr, 704 MachinePointerInfo::getFixedStack(SPFI), false, false, 0); 705} 706 707 708SDValue SelectionDAGLegalize:: 709ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 710 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 711 // SCALAR_TO_VECTOR requires that the type of the value being inserted 712 // match the element type of the vector being created, except for 713 // integers in which case the inserted value can be over width. 714 EVT EltVT = Vec.getValueType().getVectorElementType(); 715 if (Val.getValueType() == EltVT || 716 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 717 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 718 Vec.getValueType(), Val); 719 720 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 721 // We generate a shuffle of InVec and ScVec, so the shuffle mask 722 // should be 0,1,2,3,4,5... with the appropriate element replaced with 723 // elt 0 of the RHS. 724 SmallVector<int, 8> ShufOps; 725 for (unsigned i = 0; i != NumElts; ++i) 726 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 727 728 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 729 &ShufOps[0]); 730 } 731 } 732 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 733} 734 735SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 736 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 737 // FIXME: We shouldn't do this for TargetConstantFP's. 738 // FIXME: move this to the DAG Combiner! Note that we can't regress due 739 // to phase ordering between legalized code and the dag combiner. This 740 // probably means that we need to integrate dag combiner and legalizer 741 // together. 742 // We generally can't do this one for long doubles. 743 SDValue Tmp1 = ST->getChain(); 744 SDValue Tmp2 = ST->getBasePtr(); 745 SDValue Tmp3; 746 unsigned Alignment = ST->getAlignment(); 747 bool isVolatile = ST->isVolatile(); 748 bool isNonTemporal = ST->isNonTemporal(); 749 DebugLoc dl = ST->getDebugLoc(); 750 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 751 if (CFP->getValueType(0) == MVT::f32 && 752 getTypeAction(MVT::i32) == Legal) { 753 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 754 bitcastToAPInt().zextOrTrunc(32), 755 MVT::i32); 756 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 757 isVolatile, isNonTemporal, Alignment); 758 } 759 760 if (CFP->getValueType(0) == MVT::f64) { 761 // If this target supports 64-bit registers, do a single 64-bit store. 762 if (getTypeAction(MVT::i64) == Legal) { 763 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 764 zextOrTrunc(64), MVT::i64); 765 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 766 isVolatile, isNonTemporal, Alignment); 767 } 768 769 if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 770 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 771 // stores. If the target supports neither 32- nor 64-bits, this 772 // xform is certainly not worth it. 773 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 774 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32); 775 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 776 if (TLI.isBigEndian()) std::swap(Lo, Hi); 777 778 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile, 779 isNonTemporal, Alignment); 780 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 781 DAG.getIntPtrConstant(4)); 782 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, 783 ST->getPointerInfo().getWithOffset(4), 784 isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); 785 786 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 787 } 788 } 789 } 790 return SDValue(0, 0); 791} 792 793/// LegalizeOp - We know that the specified value has a legal type, and 794/// that its operands are legal. Now ensure that the operation itself 795/// is legal, recursively ensuring that the operands' operations remain 796/// legal. 797SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 798 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 799 return Op; 800 801 SDNode *Node = Op.getNode(); 802 DebugLoc dl = Node->getDebugLoc(); 803 804 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 805 assert(getTypeAction(Node->getValueType(i)) == Legal && 806 "Unexpected illegal type!"); 807 808 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 809 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 810 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 811 "Unexpected illegal type!"); 812 813 // Note that LegalizeOp may be reentered even from single-use nodes, which 814 // means that we always must cache transformed nodes. 815 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 816 if (I != LegalizedNodes.end()) return I->second; 817 818 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 819 SDValue Result = Op; 820 bool isCustom = false; 821 822 // Figure out the correct action; the way to query this varies by opcode 823 TargetLowering::LegalizeAction Action = TargetLowering::Legal; 824 bool SimpleFinishLegalizing = true; 825 switch (Node->getOpcode()) { 826 case ISD::INTRINSIC_W_CHAIN: 827 case ISD::INTRINSIC_WO_CHAIN: 828 case ISD::INTRINSIC_VOID: 829 case ISD::VAARG: 830 case ISD::STACKSAVE: 831 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 832 break; 833 case ISD::SINT_TO_FP: 834 case ISD::UINT_TO_FP: 835 case ISD::EXTRACT_VECTOR_ELT: 836 Action = TLI.getOperationAction(Node->getOpcode(), 837 Node->getOperand(0).getValueType()); 838 break; 839 case ISD::FP_ROUND_INREG: 840 case ISD::SIGN_EXTEND_INREG: { 841 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 842 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 843 break; 844 } 845 case ISD::SELECT_CC: 846 case ISD::SETCC: 847 case ISD::BR_CC: { 848 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 849 Node->getOpcode() == ISD::SETCC ? 2 : 1; 850 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 851 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 852 ISD::CondCode CCCode = 853 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 854 Action = TLI.getCondCodeAction(CCCode, OpVT); 855 if (Action == TargetLowering::Legal) { 856 if (Node->getOpcode() == ISD::SELECT_CC) 857 Action = TLI.getOperationAction(Node->getOpcode(), 858 Node->getValueType(0)); 859 else 860 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 861 } 862 break; 863 } 864 case ISD::LOAD: 865 case ISD::STORE: 866 // FIXME: Model these properly. LOAD and STORE are complicated, and 867 // STORE expects the unlegalized operand in some cases. 868 SimpleFinishLegalizing = false; 869 break; 870 case ISD::CALLSEQ_START: 871 case ISD::CALLSEQ_END: 872 // FIXME: This shouldn't be necessary. These nodes have special properties 873 // dealing with the recursive nature of legalization. Removing this 874 // special case should be done as part of making LegalizeDAG non-recursive. 875 SimpleFinishLegalizing = false; 876 break; 877 case ISD::EXTRACT_ELEMENT: 878 case ISD::FLT_ROUNDS_: 879 case ISD::SADDO: 880 case ISD::SSUBO: 881 case ISD::UADDO: 882 case ISD::USUBO: 883 case ISD::SMULO: 884 case ISD::UMULO: 885 case ISD::FPOWI: 886 case ISD::MERGE_VALUES: 887 case ISD::EH_RETURN: 888 case ISD::FRAME_TO_ARGS_OFFSET: 889 case ISD::EH_SJLJ_SETJMP: 890 case ISD::EH_SJLJ_LONGJMP: 891 case ISD::EH_SJLJ_DISPATCHSETUP: 892 // These operations lie about being legal: when they claim to be legal, 893 // they should actually be expanded. 894 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 895 if (Action == TargetLowering::Legal) 896 Action = TargetLowering::Expand; 897 break; 898 case ISD::TRAMPOLINE: 899 case ISD::FRAMEADDR: 900 case ISD::RETURNADDR: 901 // These operations lie about being legal: when they claim to be legal, 902 // they should actually be custom-lowered. 903 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 904 if (Action == TargetLowering::Legal) 905 Action = TargetLowering::Custom; 906 break; 907 case ISD::BUILD_VECTOR: 908 // A weird case: legalization for BUILD_VECTOR never legalizes the 909 // operands! 910 // FIXME: This really sucks... changing it isn't semantically incorrect, 911 // but it massively pessimizes the code for floating-point BUILD_VECTORs 912 // because ConstantFP operands get legalized into constant pool loads 913 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 914 // though, because BUILD_VECTORS usually get lowered into other nodes 915 // which get legalized properly. 916 SimpleFinishLegalizing = false; 917 break; 918 default: 919 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 920 Action = TargetLowering::Legal; 921 } else { 922 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 923 } 924 break; 925 } 926 927 if (SimpleFinishLegalizing) { 928 SmallVector<SDValue, 8> Ops, ResultVals; 929 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 930 Ops.push_back(LegalizeOp(Node->getOperand(i))); 931 switch (Node->getOpcode()) { 932 default: break; 933 case ISD::BR: 934 case ISD::BRIND: 935 case ISD::BR_JT: 936 case ISD::BR_CC: 937 case ISD::BRCOND: 938 // Branches tweak the chain to include LastCALLSEQ_END 939 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 940 LastCALLSEQ_END); 941 Ops[0] = LegalizeOp(Ops[0]); 942 LastCALLSEQ_END = DAG.getEntryNode(); 943 break; 944 case ISD::SHL: 945 case ISD::SRL: 946 case ISD::SRA: 947 case ISD::ROTL: 948 case ISD::ROTR: 949 // Legalizing shifts/rotates requires adjusting the shift amount 950 // to the appropriate width. 951 if (!Ops[1].getValueType().isVector()) 952 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(), 953 Ops[1])); 954 break; 955 case ISD::SRL_PARTS: 956 case ISD::SRA_PARTS: 957 case ISD::SHL_PARTS: 958 // Legalizing shifts/rotates requires adjusting the shift amount 959 // to the appropriate width. 960 if (!Ops[2].getValueType().isVector()) 961 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(), 962 Ops[2])); 963 break; 964 } 965 966 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(), 967 Ops.size()), 0); 968 switch (Action) { 969 case TargetLowering::Legal: 970 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 971 ResultVals.push_back(Result.getValue(i)); 972 break; 973 case TargetLowering::Custom: 974 // FIXME: The handling for custom lowering with multiple results is 975 // a complete mess. 976 Tmp1 = TLI.LowerOperation(Result, DAG); 977 if (Tmp1.getNode()) { 978 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 979 if (e == 1) 980 ResultVals.push_back(Tmp1); 981 else 982 ResultVals.push_back(Tmp1.getValue(i)); 983 } 984 break; 985 } 986 987 // FALL THROUGH 988 case TargetLowering::Expand: 989 ExpandNode(Result.getNode(), ResultVals); 990 break; 991 case TargetLowering::Promote: 992 PromoteNode(Result.getNode(), ResultVals); 993 break; 994 } 995 if (!ResultVals.empty()) { 996 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 997 if (ResultVals[i] != SDValue(Node, i)) 998 ResultVals[i] = LegalizeOp(ResultVals[i]); 999 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 1000 } 1001 return ResultVals[Op.getResNo()]; 1002 } 1003 } 1004 1005 switch (Node->getOpcode()) { 1006 default: 1007#ifndef NDEBUG 1008 dbgs() << "NODE: "; 1009 Node->dump( &DAG); 1010 dbgs() << "\n"; 1011#endif 1012 assert(0 && "Do not know how to legalize this operator!"); 1013 1014 case ISD::BUILD_VECTOR: 1015 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1016 default: assert(0 && "This action is not supported yet!"); 1017 case TargetLowering::Custom: 1018 Tmp3 = TLI.LowerOperation(Result, DAG); 1019 if (Tmp3.getNode()) { 1020 Result = Tmp3; 1021 break; 1022 } 1023 // FALLTHROUGH 1024 case TargetLowering::Expand: 1025 Result = ExpandBUILD_VECTOR(Result.getNode()); 1026 break; 1027 } 1028 break; 1029 case ISD::CALLSEQ_START: { 1030 static int depth = 0; 1031 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1032 1033 // Recursively Legalize all of the inputs of the call end that do not lead 1034 // to this call start. This ensures that any libcalls that need be inserted 1035 // are inserted *before* the CALLSEQ_START. 1036 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1037 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1038 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1039 NodesLeadingTo); 1040 } 1041 1042 // Now that we have legalized all of the inputs (which may have inserted 1043 // libcalls), create the new CALLSEQ_START node. 1044 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1045 1046 // Merge in the last call to ensure that this call starts after the last 1047 // call ended. 1048 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken && depth == 0) { 1049 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1050 Tmp1, LastCALLSEQ_END); 1051 Tmp1 = LegalizeOp(Tmp1); 1052 } 1053 1054 // Do not try to legalize the target-specific arguments (#1+). 1055 if (Tmp1 != Node->getOperand(0)) { 1056 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1057 Ops[0] = Tmp1; 1058 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0], 1059 Ops.size()), Result.getResNo()); 1060 } 1061 1062 // Remember that the CALLSEQ_START is legalized. 1063 AddLegalizedOperand(Op.getValue(0), Result); 1064 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1065 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1066 1067 // Now that the callseq_start and all of the non-call nodes above this call 1068 // sequence have been legalized, legalize the call itself. During this 1069 // process, no libcalls can/will be inserted, guaranteeing that no calls 1070 // can overlap. 1071 1072 SDValue Saved_LastCALLSEQ_END = LastCALLSEQ_END ; 1073 // Note that we are selecting this call! 1074 LastCALLSEQ_END = SDValue(CallEnd, 0); 1075 1076 depth++; 1077 // Legalize the call, starting from the CALLSEQ_END. 1078 LegalizeOp(LastCALLSEQ_END); 1079 depth--; 1080 assert(depth >= 0 && "Un-matched CALLSEQ_START?"); 1081 if (depth > 0) 1082 LastCALLSEQ_END = Saved_LastCALLSEQ_END; 1083 return Result; 1084 } 1085 case ISD::CALLSEQ_END: 1086 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1087 // will cause this node to be legalized as well as handling libcalls right. 1088 if (LastCALLSEQ_END.getNode() != Node) { 1089 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1090 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1091 assert(I != LegalizedNodes.end() && 1092 "Legalizing the call start should have legalized this node!"); 1093 return I->second; 1094 } 1095 1096 // Otherwise, the call start has been legalized and everything is going 1097 // according to plan. Just legalize ourselves normally here. 1098 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1099 // Do not try to legalize the target-specific arguments (#1+), except for 1100 // an optional flag input. 1101 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Glue){ 1102 if (Tmp1 != Node->getOperand(0)) { 1103 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1104 Ops[0] = Tmp1; 1105 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1106 &Ops[0], Ops.size()), 1107 Result.getResNo()); 1108 } 1109 } else { 1110 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1111 if (Tmp1 != Node->getOperand(0) || 1112 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1113 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1114 Ops[0] = Tmp1; 1115 Ops.back() = Tmp2; 1116 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1117 &Ops[0], Ops.size()), 1118 Result.getResNo()); 1119 } 1120 } 1121 // This finishes up call legalization. 1122 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1123 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1124 if (Node->getNumValues() == 2) 1125 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1126 return Result.getValue(Op.getResNo()); 1127 case ISD::LOAD: { 1128 LoadSDNode *LD = cast<LoadSDNode>(Node); 1129 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1130 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1131 1132 ISD::LoadExtType ExtType = LD->getExtensionType(); 1133 if (ExtType == ISD::NON_EXTLOAD) { 1134 EVT VT = Node->getValueType(0); 1135 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1136 Tmp1, Tmp2, LD->getOffset()), 1137 Result.getResNo()); 1138 Tmp3 = Result.getValue(0); 1139 Tmp4 = Result.getValue(1); 1140 1141 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1142 default: assert(0 && "This action is not supported yet!"); 1143 case TargetLowering::Legal: 1144 // If this is an unaligned load and the target doesn't support it, 1145 // expand it. 1146 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1147 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1148 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1149 if (LD->getAlignment() < ABIAlignment){ 1150 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1151 DAG, TLI); 1152 Tmp3 = Result.getOperand(0); 1153 Tmp4 = Result.getOperand(1); 1154 Tmp3 = LegalizeOp(Tmp3); 1155 Tmp4 = LegalizeOp(Tmp4); 1156 } 1157 } 1158 break; 1159 case TargetLowering::Custom: 1160 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1161 if (Tmp1.getNode()) { 1162 Tmp3 = LegalizeOp(Tmp1); 1163 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1164 } 1165 break; 1166 case TargetLowering::Promote: { 1167 // Only promote a load of vector type to another. 1168 assert(VT.isVector() && "Cannot promote this load!"); 1169 // Change base type to a different vector type. 1170 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1171 1172 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(), 1173 LD->isVolatile(), LD->isNonTemporal(), 1174 LD->getAlignment()); 1175 Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1)); 1176 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1177 break; 1178 } 1179 } 1180 // Since loads produce two values, make sure to remember that we 1181 // legalized both of them. 1182 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1183 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1184 return Op.getResNo() ? Tmp4 : Tmp3; 1185 } 1186 1187 EVT SrcVT = LD->getMemoryVT(); 1188 unsigned SrcWidth = SrcVT.getSizeInBits(); 1189 unsigned Alignment = LD->getAlignment(); 1190 bool isVolatile = LD->isVolatile(); 1191 bool isNonTemporal = LD->isNonTemporal(); 1192 1193 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1194 // Some targets pretend to have an i1 loading operation, and actually 1195 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1196 // bits are guaranteed to be zero; it helps the optimizers understand 1197 // that these bits are zero. It is also useful for EXTLOAD, since it 1198 // tells the optimizers that those bits are undefined. It would be 1199 // nice to have an effective generic way of getting these benefits... 1200 // Until such a way is found, don't insist on promoting i1 here. 1201 (SrcVT != MVT::i1 || 1202 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1203 // Promote to a byte-sized load if not loading an integral number of 1204 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1205 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1206 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 1207 SDValue Ch; 1208 1209 // The extra bits are guaranteed to be zero, since we stored them that 1210 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1211 1212 ISD::LoadExtType NewExtType = 1213 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1214 1215 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 1216 Tmp1, Tmp2, LD->getPointerInfo(), 1217 NVT, isVolatile, isNonTemporal, Alignment); 1218 1219 Ch = Result.getValue(1); // The chain. 1220 1221 if (ExtType == ISD::SEXTLOAD) 1222 // Having the top bits zero doesn't help when sign extending. 1223 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1224 Result.getValueType(), 1225 Result, DAG.getValueType(SrcVT)); 1226 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1227 // All the top bits are guaranteed to be zero - inform the optimizers. 1228 Result = DAG.getNode(ISD::AssertZext, dl, 1229 Result.getValueType(), Result, 1230 DAG.getValueType(SrcVT)); 1231 1232 Tmp1 = LegalizeOp(Result); 1233 Tmp2 = LegalizeOp(Ch); 1234 } else if (SrcWidth & (SrcWidth - 1)) { 1235 // If not loading a power-of-2 number of bits, expand as two loads. 1236 assert(!SrcVT.isVector() && "Unsupported extload!"); 1237 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1238 assert(RoundWidth < SrcWidth); 1239 unsigned ExtraWidth = SrcWidth - RoundWidth; 1240 assert(ExtraWidth < RoundWidth); 1241 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1242 "Load size not an integral number of bytes!"); 1243 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1244 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1245 SDValue Lo, Hi, Ch; 1246 unsigned IncrementSize; 1247 1248 if (TLI.isLittleEndian()) { 1249 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1250 // Load the bottom RoundWidth bits. 1251 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), 1252 Tmp1, Tmp2, 1253 LD->getPointerInfo(), RoundVT, isVolatile, 1254 isNonTemporal, Alignment); 1255 1256 // Load the remaining ExtraWidth bits. 1257 IncrementSize = RoundWidth / 8; 1258 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1259 DAG.getIntPtrConstant(IncrementSize)); 1260 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1261 LD->getPointerInfo().getWithOffset(IncrementSize), 1262 ExtraVT, isVolatile, isNonTemporal, 1263 MinAlign(Alignment, IncrementSize)); 1264 1265 // Build a factor node to remember that this load is independent of 1266 // the other one. 1267 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1268 Hi.getValue(1)); 1269 1270 // Move the top bits to the right place. 1271 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1272 DAG.getConstant(RoundWidth, 1273 TLI.getShiftAmountTy(Hi.getValueType()))); 1274 1275 // Join the hi and lo parts. 1276 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1277 } else { 1278 // Big endian - avoid unaligned loads. 1279 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1280 // Load the top RoundWidth bits. 1281 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1282 LD->getPointerInfo(), RoundVT, isVolatile, 1283 isNonTemporal, Alignment); 1284 1285 // Load the remaining ExtraWidth bits. 1286 IncrementSize = RoundWidth / 8; 1287 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1288 DAG.getIntPtrConstant(IncrementSize)); 1289 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, 1290 dl, Node->getValueType(0), Tmp1, Tmp2, 1291 LD->getPointerInfo().getWithOffset(IncrementSize), 1292 ExtraVT, isVolatile, isNonTemporal, 1293 MinAlign(Alignment, IncrementSize)); 1294 1295 // Build a factor node to remember that this load is independent of 1296 // the other one. 1297 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1298 Hi.getValue(1)); 1299 1300 // Move the top bits to the right place. 1301 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1302 DAG.getConstant(ExtraWidth, 1303 TLI.getShiftAmountTy(Hi.getValueType()))); 1304 1305 // Join the hi and lo parts. 1306 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1307 } 1308 1309 Tmp1 = LegalizeOp(Result); 1310 Tmp2 = LegalizeOp(Ch); 1311 } else { 1312 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1313 default: assert(0 && "This action is not supported yet!"); 1314 case TargetLowering::Custom: 1315 isCustom = true; 1316 // FALLTHROUGH 1317 case TargetLowering::Legal: 1318 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1319 Tmp1, Tmp2, LD->getOffset()), 1320 Result.getResNo()); 1321 Tmp1 = Result.getValue(0); 1322 Tmp2 = Result.getValue(1); 1323 1324 if (isCustom) { 1325 Tmp3 = TLI.LowerOperation(Result, DAG); 1326 if (Tmp3.getNode()) { 1327 Tmp1 = LegalizeOp(Tmp3); 1328 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1329 } 1330 } else { 1331 // If this is an unaligned load and the target doesn't support it, 1332 // expand it. 1333 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1334 const Type *Ty = 1335 LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1336 unsigned ABIAlignment = 1337 TLI.getTargetData()->getABITypeAlignment(Ty); 1338 if (LD->getAlignment() < ABIAlignment){ 1339 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1340 DAG, TLI); 1341 Tmp1 = Result.getOperand(0); 1342 Tmp2 = Result.getOperand(1); 1343 Tmp1 = LegalizeOp(Tmp1); 1344 Tmp2 = LegalizeOp(Tmp2); 1345 } 1346 } 1347 } 1348 break; 1349 case TargetLowering::Expand: 1350 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) { 1351 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, 1352 LD->getPointerInfo(), 1353 LD->isVolatile(), LD->isNonTemporal(), 1354 LD->getAlignment()); 1355 unsigned ExtendOp; 1356 switch (ExtType) { 1357 case ISD::EXTLOAD: 1358 ExtendOp = (SrcVT.isFloatingPoint() ? 1359 ISD::FP_EXTEND : ISD::ANY_EXTEND); 1360 break; 1361 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break; 1362 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break; 1363 default: llvm_unreachable("Unexpected extend load type!"); 1364 } 1365 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load); 1366 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1367 Tmp2 = LegalizeOp(Load.getValue(1)); 1368 break; 1369 } 1370 // FIXME: This does not work for vectors on most targets. Sign- and 1371 // zero-extend operations are currently folded into extending loads, 1372 // whether they are legal or not, and then we end up here without any 1373 // support for legalizing them. 1374 assert(ExtType != ISD::EXTLOAD && 1375 "EXTLOAD should always be supported!"); 1376 // Turn the unsupported load into an EXTLOAD followed by an explicit 1377 // zero/sign extend inreg. 1378 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1379 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT, 1380 LD->isVolatile(), LD->isNonTemporal(), 1381 LD->getAlignment()); 1382 SDValue ValRes; 1383 if (ExtType == ISD::SEXTLOAD) 1384 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1385 Result.getValueType(), 1386 Result, DAG.getValueType(SrcVT)); 1387 else 1388 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType()); 1389 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1390 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1391 break; 1392 } 1393 } 1394 1395 // Since loads produce two values, make sure to remember that we legalized 1396 // both of them. 1397 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1398 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1399 return Op.getResNo() ? Tmp2 : Tmp1; 1400 } 1401 case ISD::STORE: { 1402 StoreSDNode *ST = cast<StoreSDNode>(Node); 1403 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1404 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1405 unsigned Alignment = ST->getAlignment(); 1406 bool isVolatile = ST->isVolatile(); 1407 bool isNonTemporal = ST->isNonTemporal(); 1408 1409 if (!ST->isTruncatingStore()) { 1410 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1411 Result = SDValue(OptStore, 0); 1412 break; 1413 } 1414 1415 { 1416 Tmp3 = LegalizeOp(ST->getValue()); 1417 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1418 Tmp1, Tmp3, Tmp2, 1419 ST->getOffset()), 1420 Result.getResNo()); 1421 1422 EVT VT = Tmp3.getValueType(); 1423 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1424 default: assert(0 && "This action is not supported yet!"); 1425 case TargetLowering::Legal: 1426 // If this is an unaligned store and the target doesn't support it, 1427 // expand it. 1428 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1429 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1430 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1431 if (ST->getAlignment() < ABIAlignment) 1432 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1433 DAG, TLI); 1434 } 1435 break; 1436 case TargetLowering::Custom: 1437 Tmp1 = TLI.LowerOperation(Result, DAG); 1438 if (Tmp1.getNode()) Result = Tmp1; 1439 break; 1440 case TargetLowering::Promote: 1441 assert(VT.isVector() && "Unknown legal promote case!"); 1442 Tmp3 = DAG.getNode(ISD::BITCAST, dl, 1443 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1444 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1445 ST->getPointerInfo(), isVolatile, 1446 isNonTemporal, Alignment); 1447 break; 1448 } 1449 break; 1450 } 1451 } else { 1452 Tmp3 = LegalizeOp(ST->getValue()); 1453 1454 EVT StVT = ST->getMemoryVT(); 1455 unsigned StWidth = StVT.getSizeInBits(); 1456 1457 if (StWidth != StVT.getStoreSizeInBits()) { 1458 // Promote to a byte-sized store with upper bits zero if not 1459 // storing an integral number of bytes. For example, promote 1460 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1461 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), 1462 StVT.getStoreSizeInBits()); 1463 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1464 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 1465 NVT, isVolatile, isNonTemporal, Alignment); 1466 } else if (StWidth & (StWidth - 1)) { 1467 // If not storing a power-of-2 number of bits, expand as two stores. 1468 assert(!StVT.isVector() && "Unsupported truncstore!"); 1469 unsigned RoundWidth = 1 << Log2_32(StWidth); 1470 assert(RoundWidth < StWidth); 1471 unsigned ExtraWidth = StWidth - RoundWidth; 1472 assert(ExtraWidth < RoundWidth); 1473 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1474 "Store size not an integral number of bytes!"); 1475 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1476 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1477 SDValue Lo, Hi; 1478 unsigned IncrementSize; 1479 1480 if (TLI.isLittleEndian()) { 1481 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1482 // Store the bottom RoundWidth bits. 1483 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 1484 RoundVT, 1485 isVolatile, isNonTemporal, Alignment); 1486 1487 // Store the remaining ExtraWidth bits. 1488 IncrementSize = RoundWidth / 8; 1489 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1490 DAG.getIntPtrConstant(IncrementSize)); 1491 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1492 DAG.getConstant(RoundWidth, 1493 TLI.getShiftAmountTy(Tmp3.getValueType()))); 1494 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, 1495 ST->getPointerInfo().getWithOffset(IncrementSize), 1496 ExtraVT, isVolatile, isNonTemporal, 1497 MinAlign(Alignment, IncrementSize)); 1498 } else { 1499 // Big endian - avoid unaligned stores. 1500 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1501 // Store the top RoundWidth bits. 1502 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1503 DAG.getConstant(ExtraWidth, 1504 TLI.getShiftAmountTy(Tmp3.getValueType()))); 1505 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(), 1506 RoundVT, isVolatile, isNonTemporal, Alignment); 1507 1508 // Store the remaining ExtraWidth bits. 1509 IncrementSize = RoundWidth / 8; 1510 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1511 DAG.getIntPtrConstant(IncrementSize)); 1512 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, 1513 ST->getPointerInfo().getWithOffset(IncrementSize), 1514 ExtraVT, isVolatile, isNonTemporal, 1515 MinAlign(Alignment, IncrementSize)); 1516 } 1517 1518 // The order of the stores doesn't matter. 1519 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1520 } else { 1521 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1522 Tmp2 != ST->getBasePtr()) 1523 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1524 Tmp1, Tmp3, Tmp2, 1525 ST->getOffset()), 1526 Result.getResNo()); 1527 1528 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1529 default: assert(0 && "This action is not supported yet!"); 1530 case TargetLowering::Legal: 1531 // If this is an unaligned store and the target doesn't support it, 1532 // expand it. 1533 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1534 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1535 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1536 if (ST->getAlignment() < ABIAlignment) 1537 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1538 DAG, TLI); 1539 } 1540 break; 1541 case TargetLowering::Custom: 1542 Result = TLI.LowerOperation(Result, DAG); 1543 break; 1544 case Expand: 1545 // TRUNCSTORE:i16 i32 -> STORE i16 1546 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1547 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1548 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 1549 isVolatile, isNonTemporal, Alignment); 1550 break; 1551 } 1552 } 1553 } 1554 break; 1555 } 1556 } 1557 assert(Result.getValueType() == Op.getValueType() && 1558 "Bad legalization!"); 1559 1560 // Make sure that the generated code is itself legal. 1561 if (Result != Op) 1562 Result = LegalizeOp(Result); 1563 1564 // Note that LegalizeOp may be reentered even from single-use nodes, which 1565 // means that we always must cache transformed nodes. 1566 AddLegalizedOperand(Op, Result); 1567 return Result; 1568} 1569 1570SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1571 SDValue Vec = Op.getOperand(0); 1572 SDValue Idx = Op.getOperand(1); 1573 DebugLoc dl = Op.getDebugLoc(); 1574 // Store the value to a temporary stack slot, then LOAD the returned part. 1575 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1576 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 1577 MachinePointerInfo(), false, false, 0); 1578 1579 // Add the offset to the index. 1580 unsigned EltSize = 1581 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1582 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1583 DAG.getConstant(EltSize, Idx.getValueType())); 1584 1585 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1586 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1587 else 1588 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1589 1590 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1591 1592 if (Op.getValueType().isVector()) 1593 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(), 1594 false, false, 0); 1595 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1596 MachinePointerInfo(), 1597 Vec.getValueType().getVectorElementType(), 1598 false, false, 0); 1599} 1600 1601SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) { 1602 assert(Op.getValueType().isVector() && "Non-vector insert subvector!"); 1603 1604 SDValue Vec = Op.getOperand(0); 1605 SDValue Part = Op.getOperand(1); 1606 SDValue Idx = Op.getOperand(2); 1607 DebugLoc dl = Op.getDebugLoc(); 1608 1609 // Store the value to a temporary stack slot, then LOAD the returned part. 1610 1611 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1612 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 1613 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI); 1614 1615 // First store the whole vector. 1616 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo, 1617 false, false, 0); 1618 1619 // Then store the inserted part. 1620 1621 // Add the offset to the index. 1622 unsigned EltSize = 1623 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1624 1625 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1626 DAG.getConstant(EltSize, Idx.getValueType())); 1627 1628 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1629 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1630 else 1631 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1632 1633 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, 1634 StackPtr); 1635 1636 // Store the subvector. 1637 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr, 1638 MachinePointerInfo(), false, false, 0); 1639 1640 // Finally, load the updated vector. 1641 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo, 1642 false, false, 0); 1643} 1644 1645SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1646 // We can't handle this case efficiently. Allocate a sufficiently 1647 // aligned object on the stack, store each element into it, then load 1648 // the result as a vector. 1649 // Create the stack frame object. 1650 EVT VT = Node->getValueType(0); 1651 EVT EltVT = VT.getVectorElementType(); 1652 DebugLoc dl = Node->getDebugLoc(); 1653 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1654 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1655 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI); 1656 1657 // Emit a store of each element to the stack slot. 1658 SmallVector<SDValue, 8> Stores; 1659 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1660 // Store (in the right endianness) the elements to memory. 1661 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1662 // Ignore undef elements. 1663 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1664 1665 unsigned Offset = TypeByteSize*i; 1666 1667 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1668 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1669 1670 // If the destination vector element type is narrower than the source 1671 // element type, only store the bits necessary. 1672 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1673 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1674 Node->getOperand(i), Idx, 1675 PtrInfo.getWithOffset(Offset), 1676 EltVT, false, false, 0)); 1677 } else 1678 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1679 Node->getOperand(i), Idx, 1680 PtrInfo.getWithOffset(Offset), 1681 false, false, 0)); 1682 } 1683 1684 SDValue StoreChain; 1685 if (!Stores.empty()) // Not all undef elements? 1686 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1687 &Stores[0], Stores.size()); 1688 else 1689 StoreChain = DAG.getEntryNode(); 1690 1691 // Result is a load from the stack slot. 1692 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0); 1693} 1694 1695SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1696 DebugLoc dl = Node->getDebugLoc(); 1697 SDValue Tmp1 = Node->getOperand(0); 1698 SDValue Tmp2 = Node->getOperand(1); 1699 1700 // Get the sign bit of the RHS. First obtain a value that has the same 1701 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1702 SDValue SignBit; 1703 EVT FloatVT = Tmp2.getValueType(); 1704 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1705 if (isTypeLegal(IVT)) { 1706 // Convert to an integer with the same sign bit. 1707 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2); 1708 } else { 1709 // Store the float to memory, then load the sign part out as an integer. 1710 MVT LoadTy = TLI.getPointerTy(); 1711 // First create a temporary that is aligned for both the load and store. 1712 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1713 // Then store the float to it. 1714 SDValue Ch = 1715 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(), 1716 false, false, 0); 1717 if (TLI.isBigEndian()) { 1718 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1719 // Load out a legal integer with the same sign bit as the float. 1720 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(), 1721 false, false, 0); 1722 } else { // Little endian 1723 SDValue LoadPtr = StackPtr; 1724 // The float may be wider than the integer we are going to load. Advance 1725 // the pointer so that the loaded integer will contain the sign bit. 1726 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1727 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1728 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1729 LoadPtr, DAG.getIntPtrConstant(ByteOffset)); 1730 // Load a legal integer containing the sign bit. 1731 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(), 1732 false, false, 0); 1733 // Move the sign bit to the top bit of the loaded integer. 1734 unsigned BitShift = LoadTy.getSizeInBits() - 1735 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1736 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1737 if (BitShift) 1738 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1739 DAG.getConstant(BitShift, 1740 TLI.getShiftAmountTy(SignBit.getValueType()))); 1741 } 1742 } 1743 // Now get the sign bit proper, by seeing whether the value is negative. 1744 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1745 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1746 ISD::SETLT); 1747 // Get the absolute value of the result. 1748 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1749 // Select between the nabs and abs value based on the sign bit of 1750 // the input. 1751 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1752 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1753 AbsVal); 1754} 1755 1756void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1757 SmallVectorImpl<SDValue> &Results) { 1758 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1759 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1760 " not tell us which reg is the stack pointer!"); 1761 DebugLoc dl = Node->getDebugLoc(); 1762 EVT VT = Node->getValueType(0); 1763 SDValue Tmp1 = SDValue(Node, 0); 1764 SDValue Tmp2 = SDValue(Node, 1); 1765 SDValue Tmp3 = Node->getOperand(2); 1766 SDValue Chain = Tmp1.getOperand(0); 1767 1768 // Chain the dynamic stack allocation so that it doesn't modify the stack 1769 // pointer when other instructions are using the stack. 1770 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1771 1772 SDValue Size = Tmp2.getOperand(1); 1773 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1774 Chain = SP.getValue(1); 1775 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1776 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 1777 if (Align > StackAlign) 1778 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1779 DAG.getConstant(-(uint64_t)Align, VT)); 1780 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1781 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1782 1783 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1784 DAG.getIntPtrConstant(0, true), SDValue()); 1785 1786 Results.push_back(Tmp1); 1787 Results.push_back(Tmp2); 1788} 1789 1790/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1791/// condition code CC on the current target. This routine expands SETCC with 1792/// illegal condition code into AND / OR of multiple SETCC values. 1793void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1794 SDValue &LHS, SDValue &RHS, 1795 SDValue &CC, 1796 DebugLoc dl) { 1797 EVT OpVT = LHS.getValueType(); 1798 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1799 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1800 default: assert(0 && "Unknown condition code action!"); 1801 case TargetLowering::Legal: 1802 // Nothing to do. 1803 break; 1804 case TargetLowering::Expand: { 1805 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1806 unsigned Opc = 0; 1807 switch (CCCode) { 1808 default: assert(0 && "Don't know how to expand this condition!"); 1809 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1810 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1811 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1812 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1813 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1814 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1815 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1816 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1817 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1818 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1819 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1820 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1821 // FIXME: Implement more expansions. 1822 } 1823 1824 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1825 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1826 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1827 RHS = SDValue(); 1828 CC = SDValue(); 1829 break; 1830 } 1831 } 1832} 1833 1834/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1835/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1836/// a load from the stack slot to DestVT, extending it if needed. 1837/// The resultant code need not be legal. 1838SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1839 EVT SlotVT, 1840 EVT DestVT, 1841 DebugLoc dl) { 1842 // Create the stack frame object. 1843 unsigned SrcAlign = 1844 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1845 getTypeForEVT(*DAG.getContext())); 1846 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1847 1848 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1849 int SPFI = StackPtrFI->getIndex(); 1850 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI); 1851 1852 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1853 unsigned SlotSize = SlotVT.getSizeInBits(); 1854 unsigned DestSize = DestVT.getSizeInBits(); 1855 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); 1856 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType); 1857 1858 // Emit a store to the stack slot. Use a truncstore if the input value is 1859 // later than DestVT. 1860 SDValue Store; 1861 1862 if (SrcSize > SlotSize) 1863 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1864 PtrInfo, SlotVT, false, false, SrcAlign); 1865 else { 1866 assert(SrcSize == SlotSize && "Invalid store"); 1867 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1868 PtrInfo, false, false, SrcAlign); 1869 } 1870 1871 // Result is a load from the stack slot. 1872 if (SlotSize == DestSize) 1873 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, 1874 false, false, DestAlign); 1875 1876 assert(SlotSize < DestSize && "Unknown extension!"); 1877 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, 1878 PtrInfo, SlotVT, false, false, DestAlign); 1879} 1880 1881SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1882 DebugLoc dl = Node->getDebugLoc(); 1883 // Create a vector sized/aligned stack slot, store the value to element #0, 1884 // then load the whole vector back out. 1885 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1886 1887 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1888 int SPFI = StackPtrFI->getIndex(); 1889 1890 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1891 StackPtr, 1892 MachinePointerInfo::getFixedStack(SPFI), 1893 Node->getValueType(0).getVectorElementType(), 1894 false, false, 0); 1895 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1896 MachinePointerInfo::getFixedStack(SPFI), 1897 false, false, 0); 1898} 1899 1900 1901/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1902/// support the operation, but do support the resultant vector type. 1903SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1904 unsigned NumElems = Node->getNumOperands(); 1905 SDValue Value1, Value2; 1906 DebugLoc dl = Node->getDebugLoc(); 1907 EVT VT = Node->getValueType(0); 1908 EVT OpVT = Node->getOperand(0).getValueType(); 1909 EVT EltVT = VT.getVectorElementType(); 1910 1911 // If the only non-undef value is the low element, turn this into a 1912 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1913 bool isOnlyLowElement = true; 1914 bool MoreThanTwoValues = false; 1915 bool isConstant = true; 1916 for (unsigned i = 0; i < NumElems; ++i) { 1917 SDValue V = Node->getOperand(i); 1918 if (V.getOpcode() == ISD::UNDEF) 1919 continue; 1920 if (i > 0) 1921 isOnlyLowElement = false; 1922 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1923 isConstant = false; 1924 1925 if (!Value1.getNode()) { 1926 Value1 = V; 1927 } else if (!Value2.getNode()) { 1928 if (V != Value1) 1929 Value2 = V; 1930 } else if (V != Value1 && V != Value2) { 1931 MoreThanTwoValues = true; 1932 } 1933 } 1934 1935 if (!Value1.getNode()) 1936 return DAG.getUNDEF(VT); 1937 1938 if (isOnlyLowElement) 1939 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1940 1941 // If all elements are constants, create a load from the constant pool. 1942 if (isConstant) { 1943 std::vector<Constant*> CV; 1944 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1945 if (ConstantFPSDNode *V = 1946 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1947 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1948 } else if (ConstantSDNode *V = 1949 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1950 if (OpVT==EltVT) 1951 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1952 else { 1953 // If OpVT and EltVT don't match, EltVT is not legal and the 1954 // element values have been promoted/truncated earlier. Undo this; 1955 // we don't want a v16i8 to become a v16i32 for example. 1956 const ConstantInt *CI = V->getConstantIntValue(); 1957 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1958 CI->getZExtValue())); 1959 } 1960 } else { 1961 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1962 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1963 CV.push_back(UndefValue::get(OpNTy)); 1964 } 1965 } 1966 Constant *CP = ConstantVector::get(CV); 1967 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1968 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1969 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1970 MachinePointerInfo::getConstantPool(), 1971 false, false, Alignment); 1972 } 1973 1974 if (!MoreThanTwoValues) { 1975 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1976 for (unsigned i = 0; i < NumElems; ++i) { 1977 SDValue V = Node->getOperand(i); 1978 if (V.getOpcode() == ISD::UNDEF) 1979 continue; 1980 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1981 } 1982 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1983 // Get the splatted value into the low element of a vector register. 1984 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1985 SDValue Vec2; 1986 if (Value2.getNode()) 1987 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1988 else 1989 Vec2 = DAG.getUNDEF(VT); 1990 1991 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1992 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1993 } 1994 } 1995 1996 // Otherwise, we can't handle this case efficiently. 1997 return ExpandVectorBuildThroughStack(Node); 1998} 1999 2000// ExpandLibCall - Expand a node into a call to a libcall. If the result value 2001// does not fit into a register, return the lo part and set the hi part to the 2002// by-reg argument. If it does fit into a single register, return the result 2003// and leave the Hi part unset. 2004SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 2005 bool isSigned) { 2006 // The input chain to this libcall is the entry node of the function. 2007 // Legalizing the call will automatically add the previous call to the 2008 // dependence. 2009 SDValue InChain = DAG.getEntryNode(); 2010 2011 TargetLowering::ArgListTy Args; 2012 TargetLowering::ArgListEntry Entry; 2013 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2014 EVT ArgVT = Node->getOperand(i).getValueType(); 2015 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 2016 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 2017 Entry.isSExt = isSigned; 2018 Entry.isZExt = !isSigned; 2019 Args.push_back(Entry); 2020 } 2021 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 2022 TLI.getPointerTy()); 2023 2024 // Splice the libcall in wherever FindInputOutputChains tells us to. 2025 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 2026 2027 // isTailCall may be true since the callee does not reference caller stack 2028 // frame. Check if it's in the right position. 2029 bool isTailCall = isInTailCallPosition(DAG, Node, TLI); 2030 std::pair<SDValue, SDValue> CallInfo = 2031 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 2032 0, TLI.getLibcallCallingConv(LC), isTailCall, 2033 /*isReturnValueUsed=*/true, 2034 Callee, Args, DAG, Node->getDebugLoc()); 2035 2036 if (!CallInfo.second.getNode()) 2037 // It's a tailcall, return the chain (which is the DAG root). 2038 return DAG.getRoot(); 2039 2040 // Legalize the call sequence, starting with the chain. This will advance 2041 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 2042 // was added by LowerCallTo (guaranteeing proper serialization of calls). 2043 LegalizeOp(CallInfo.second); 2044 return CallInfo.first; 2045} 2046 2047// ExpandChainLibCall - Expand a node into a call to a libcall. Similar to 2048// ExpandLibCall except that the first operand is the in-chain. 2049std::pair<SDValue, SDValue> 2050SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC, 2051 SDNode *Node, 2052 bool isSigned) { 2053 SDValue InChain = Node->getOperand(0); 2054 2055 TargetLowering::ArgListTy Args; 2056 TargetLowering::ArgListEntry Entry; 2057 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) { 2058 EVT ArgVT = Node->getOperand(i).getValueType(); 2059 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 2060 Entry.Node = Node->getOperand(i); 2061 Entry.Ty = ArgTy; 2062 Entry.isSExt = isSigned; 2063 Entry.isZExt = !isSigned; 2064 Args.push_back(Entry); 2065 } 2066 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 2067 TLI.getPointerTy()); 2068 2069 // Splice the libcall in wherever FindInputOutputChains tells us to. 2070 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 2071 std::pair<SDValue, SDValue> CallInfo = 2072 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 2073 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false, 2074 /*isReturnValueUsed=*/true, 2075 Callee, Args, DAG, Node->getDebugLoc()); 2076 2077 // Legalize the call sequence, starting with the chain. This will advance 2078 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 2079 // was added by LowerCallTo (guaranteeing proper serialization of calls). 2080 LegalizeOp(CallInfo.second); 2081 return CallInfo; 2082} 2083 2084SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 2085 RTLIB::Libcall Call_F32, 2086 RTLIB::Libcall Call_F64, 2087 RTLIB::Libcall Call_F80, 2088 RTLIB::Libcall Call_PPCF128) { 2089 RTLIB::Libcall LC; 2090 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 2091 default: assert(0 && "Unexpected request for libcall!"); 2092 case MVT::f32: LC = Call_F32; break; 2093 case MVT::f64: LC = Call_F64; break; 2094 case MVT::f80: LC = Call_F80; break; 2095 case MVT::ppcf128: LC = Call_PPCF128; break; 2096 } 2097 return ExpandLibCall(LC, Node, false); 2098} 2099 2100SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 2101 RTLIB::Libcall Call_I8, 2102 RTLIB::Libcall Call_I16, 2103 RTLIB::Libcall Call_I32, 2104 RTLIB::Libcall Call_I64, 2105 RTLIB::Libcall Call_I128) { 2106 RTLIB::Libcall LC; 2107 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 2108 default: assert(0 && "Unexpected request for libcall!"); 2109 case MVT::i8: LC = Call_I8; break; 2110 case MVT::i16: LC = Call_I16; break; 2111 case MVT::i32: LC = Call_I32; break; 2112 case MVT::i64: LC = Call_I64; break; 2113 case MVT::i128: LC = Call_I128; break; 2114 } 2115 return ExpandLibCall(LC, Node, isSigned); 2116} 2117 2118/// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem 2119/// pairs. 2120SDValue SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node, bool isSigned, 2121 bool isDIV) { 2122 RTLIB::Libcall LC; 2123 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 2124 default: assert(0 && "Unexpected request for libcall!"); 2125 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; 2126 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; 2127 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; 2128 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; 2129 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break; 2130 } 2131 2132 if (!TLI.getLibcallName(LC)) 2133 return SDValue(); 2134 2135 // Only issue divrem libcall if both quotient and remainder are needed. 2136 unsigned OtherOpcode = 0; 2137 if (isSigned) { 2138 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV; 2139 } else { 2140 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV; 2141 } 2142 SDNode *OtherNode = 0; 2143 SDValue Op0 = Node->getOperand(0); 2144 SDValue Op1 = Node->getOperand(1); 2145 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(), 2146 UE = Op0.getNode()->use_end(); UI != UE; ++UI) { 2147 SDNode *User = *UI; 2148 if (User == Node) 2149 continue; 2150 if (User->getOpcode() == OtherOpcode && 2151 User->getOperand(0) == Op0 && 2152 User->getOperand(1) == Op1) { 2153 OtherNode = User; 2154 break; 2155 } 2156 } 2157 if (!OtherNode) 2158 return SDValue(); 2159 2160 // If the libcall is already generated, no need to issue it again. 2161 DenseMap<SDValue, SDValue>::iterator I 2162 = LegalizedNodes.find(SDValue(OtherNode,0)); 2163 if (I != LegalizedNodes.end()) { 2164 OtherNode = I->second.getNode(); 2165 SDNode *Chain = OtherNode->getOperand(0).getNode(); 2166 for (SDNode::use_iterator UI = Chain->use_begin(), UE = Chain->use_end(); 2167 UI != UE; ++UI) { 2168 SDNode *User = *UI; 2169 if (User == OtherNode) 2170 continue; 2171 if (isDIV) { 2172 assert(User->getOpcode() == ISD::CopyFromReg); 2173 } else { 2174 assert(User->getOpcode() == ISD::LOAD); 2175 } 2176 return SDValue(User, 0); 2177 } 2178 } 2179 2180 // The input chain to this libcall is the entry node of the function. 2181 // Legalizing the call will automatically add the previous call to the 2182 // dependence. 2183 SDValue InChain = DAG.getEntryNode(); 2184 2185 EVT RetVT = Node->getValueType(0); 2186 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 2187 2188 TargetLowering::ArgListTy Args; 2189 TargetLowering::ArgListEntry Entry; 2190 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2191 EVT ArgVT = Node->getOperand(i).getValueType(); 2192 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 2193 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 2194 Entry.isSExt = isSigned; 2195 Entry.isZExt = !isSigned; 2196 Args.push_back(Entry); 2197 } 2198 2199 // Also pass the return address of the remainder. 2200 SDValue FIPtr = DAG.CreateStackTemporary(RetVT); 2201 Entry.Node = FIPtr; 2202 Entry.Ty = RetTy->getPointerTo(); 2203 Entry.isSExt = isSigned; 2204 Entry.isZExt = !isSigned; 2205 Args.push_back(Entry); 2206 2207 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 2208 TLI.getPointerTy()); 2209 2210 // Splice the libcall in wherever FindInputOutputChains tells us to. 2211 DebugLoc dl = Node->getDebugLoc(); 2212 std::pair<SDValue, SDValue> CallInfo = 2213 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 2214 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false, 2215 /*isReturnValueUsed=*/true, Callee, Args, DAG, dl); 2216 2217 // Legalize the call sequence, starting with the chain. This will advance 2218 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 2219 // was added by LowerCallTo (guaranteeing proper serialization of calls). 2220 LegalizeOp(CallInfo.second); 2221 2222 // Remainder is loaded back from the stack frame. 2223 SDValue Rem = DAG.getLoad(RetVT, dl, LastCALLSEQ_END, FIPtr, 2224 MachinePointerInfo(), false, false, 0); 2225 return isDIV ? CallInfo.first : Rem; 2226} 2227 2228/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 2229/// INT_TO_FP operation of the specified operand when the target requests that 2230/// we expand it. At this point, we know that the result and operand types are 2231/// legal for the target. 2232SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 2233 SDValue Op0, 2234 EVT DestVT, 2235 DebugLoc dl) { 2236 if (Op0.getValueType() == MVT::i32) { 2237 // simple 32-bit [signed|unsigned] integer to float/double expansion 2238 2239 // Get the stack frame index of a 8 byte buffer. 2240 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 2241 2242 // word offset constant for Hi/Lo address computation 2243 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 2244 // set up Hi and Lo (into buffer) address based on endian 2245 SDValue Hi = StackSlot; 2246 SDValue Lo = DAG.getNode(ISD::ADD, dl, 2247 TLI.getPointerTy(), StackSlot, WordOff); 2248 if (TLI.isLittleEndian()) 2249 std::swap(Hi, Lo); 2250 2251 // if signed map to unsigned space 2252 SDValue Op0Mapped; 2253 if (isSigned) { 2254 // constant used to invert sign bit (signed to unsigned mapping) 2255 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 2256 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 2257 } else { 2258 Op0Mapped = Op0; 2259 } 2260 // store the lo of the constructed double - based on integer input 2261 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 2262 Op0Mapped, Lo, MachinePointerInfo(), 2263 false, false, 0); 2264 // initial hi portion of constructed double 2265 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 2266 // store the hi of the constructed double - biased exponent 2267 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi, 2268 MachinePointerInfo(), 2269 false, false, 0); 2270 // load the constructed double 2271 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, 2272 MachinePointerInfo(), false, false, 0); 2273 // FP constant to bias correct the final result 2274 SDValue Bias = DAG.getConstantFP(isSigned ? 2275 BitsToDouble(0x4330000080000000ULL) : 2276 BitsToDouble(0x4330000000000000ULL), 2277 MVT::f64); 2278 // subtract the bias 2279 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2280 // final result 2281 SDValue Result; 2282 // handle final rounding 2283 if (DestVT == MVT::f64) { 2284 // do nothing 2285 Result = Sub; 2286 } else if (DestVT.bitsLT(MVT::f64)) { 2287 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2288 DAG.getIntPtrConstant(0)); 2289 } else if (DestVT.bitsGT(MVT::f64)) { 2290 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2291 } 2292 return Result; 2293 } 2294 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2295 // Code below here assumes !isSigned without checking again. 2296 2297 // Implementation of unsigned i64 to f64 following the algorithm in 2298 // __floatundidf in compiler_rt. This implementation has the advantage 2299 // of performing rounding correctly, both in the default rounding mode 2300 // and in all alternate rounding modes. 2301 // TODO: Generalize this for use with other types. 2302 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2303 SDValue TwoP52 = 2304 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2305 SDValue TwoP84PlusTwoP52 = 2306 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2307 SDValue TwoP84 = 2308 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2309 2310 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2311 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2312 DAG.getConstant(32, MVT::i64)); 2313 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2314 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2315 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr); 2316 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr); 2317 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, 2318 TwoP84PlusTwoP52); 2319 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2320 } 2321 2322 // Implementation of unsigned i64 to f32. 2323 // TODO: Generalize this for use with other types. 2324 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) { 2325 // For unsigned conversions, convert them to signed conversions using the 2326 // algorithm from the x86_64 __floatundidf in compiler_rt. 2327 if (!isSigned) { 2328 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0); 2329 2330 SDValue ShiftConst = 2331 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType())); 2332 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst); 2333 SDValue AndConst = DAG.getConstant(1, MVT::i64); 2334 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst); 2335 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr); 2336 2337 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or); 2338 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt); 2339 2340 // TODO: This really should be implemented using a branch rather than a 2341 // select. We happen to get lucky and machinesink does the right 2342 // thing most of the time. This would be a good candidate for a 2343 //pseudo-op, or, even better, for whole-function isel. 2344 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2345 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT); 2346 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast); 2347 } 2348 2349 // Otherwise, implement the fully general conversion. 2350 2351 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2352 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64)); 2353 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, 2354 DAG.getConstant(UINT64_C(0x800), MVT::i64)); 2355 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2356 DAG.getConstant(UINT64_C(0x7ff), MVT::i64)); 2357 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2358 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); 2359 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0); 2360 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2361 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64), 2362 ISD::SETUGE); 2363 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0); 2364 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType()); 2365 2366 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, 2367 DAG.getConstant(32, SHVT)); 2368 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh); 2369 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); 2370 SDValue TwoP32 = 2371 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64); 2372 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); 2373 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2); 2374 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo); 2375 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); 2376 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, 2377 DAG.getIntPtrConstant(0)); 2378 } 2379 2380 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2381 2382 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2383 Op0, DAG.getConstant(0, Op0.getValueType()), 2384 ISD::SETLT); 2385 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2386 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2387 SignSet, Four, Zero); 2388 2389 // If the sign bit of the integer is set, the large number will be treated 2390 // as a negative number. To counteract this, the dynamic code adds an 2391 // offset depending on the data type. 2392 uint64_t FF; 2393 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2394 default: assert(0 && "Unsupported integer type!"); 2395 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2396 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2397 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2398 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2399 } 2400 if (TLI.isLittleEndian()) FF <<= 32; 2401 Constant *FudgeFactor = ConstantInt::get( 2402 Type::getInt64Ty(*DAG.getContext()), FF); 2403 2404 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2405 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2406 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2407 Alignment = std::min(Alignment, 4u); 2408 SDValue FudgeInReg; 2409 if (DestVT == MVT::f32) 2410 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2411 MachinePointerInfo::getConstantPool(), 2412 false, false, Alignment); 2413 else { 2414 FudgeInReg = 2415 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2416 DAG.getEntryNode(), CPIdx, 2417 MachinePointerInfo::getConstantPool(), 2418 MVT::f32, false, false, Alignment)); 2419 } 2420 2421 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2422} 2423 2424/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2425/// *INT_TO_FP operation of the specified operand when the target requests that 2426/// we promote it. At this point, we know that the result and operand types are 2427/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2428/// operation that takes a larger input. 2429SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2430 EVT DestVT, 2431 bool isSigned, 2432 DebugLoc dl) { 2433 // First step, figure out the appropriate *INT_TO_FP operation to use. 2434 EVT NewInTy = LegalOp.getValueType(); 2435 2436 unsigned OpToUse = 0; 2437 2438 // Scan for the appropriate larger type to use. 2439 while (1) { 2440 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2441 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2442 2443 // If the target supports SINT_TO_FP of this type, use it. 2444 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2445 OpToUse = ISD::SINT_TO_FP; 2446 break; 2447 } 2448 if (isSigned) continue; 2449 2450 // If the target supports UINT_TO_FP of this type, use it. 2451 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2452 OpToUse = ISD::UINT_TO_FP; 2453 break; 2454 } 2455 2456 // Otherwise, try a larger type. 2457 } 2458 2459 // Okay, we found the operation and type to use. Zero extend our input to the 2460 // desired type then run the operation on it. 2461 return DAG.getNode(OpToUse, dl, DestVT, 2462 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2463 dl, NewInTy, LegalOp)); 2464} 2465 2466/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2467/// FP_TO_*INT operation of the specified operand when the target requests that 2468/// we promote it. At this point, we know that the result and operand types are 2469/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2470/// operation that returns a larger result. 2471SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2472 EVT DestVT, 2473 bool isSigned, 2474 DebugLoc dl) { 2475 // First step, figure out the appropriate FP_TO*INT operation to use. 2476 EVT NewOutTy = DestVT; 2477 2478 unsigned OpToUse = 0; 2479 2480 // Scan for the appropriate larger type to use. 2481 while (1) { 2482 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2483 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2484 2485 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2486 OpToUse = ISD::FP_TO_SINT; 2487 break; 2488 } 2489 2490 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2491 OpToUse = ISD::FP_TO_UINT; 2492 break; 2493 } 2494 2495 // Otherwise, try a larger type. 2496 } 2497 2498 2499 // Okay, we found the operation and type to use. 2500 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2501 2502 // Truncate the result of the extended FP_TO_*INT operation to the desired 2503 // size. 2504 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2505} 2506 2507/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2508/// 2509SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2510 EVT VT = Op.getValueType(); 2511 EVT SHVT = TLI.getShiftAmountTy(VT); 2512 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2513 switch (VT.getSimpleVT().SimpleTy) { 2514 default: assert(0 && "Unhandled Expand type in BSWAP!"); 2515 case MVT::i16: 2516 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2517 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2518 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2519 case MVT::i32: 2520 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2521 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2522 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2523 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2524 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2525 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2526 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2527 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2528 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2529 case MVT::i64: 2530 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2531 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2532 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2533 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2534 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2535 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2536 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2537 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2538 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2539 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2540 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2541 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2542 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2543 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2544 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2545 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2546 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2547 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2548 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2549 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2550 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2551 } 2552} 2553 2554/// SplatByte - Distribute ByteVal over NumBits bits. 2555// FIXME: Move this helper to a common place. 2556static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) { 2557 APInt Val = APInt(NumBits, ByteVal); 2558 unsigned Shift = 8; 2559 for (unsigned i = NumBits; i > 8; i >>= 1) { 2560 Val = (Val << Shift) | Val; 2561 Shift <<= 1; 2562 } 2563 return Val; 2564} 2565 2566/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2567/// 2568SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2569 DebugLoc dl) { 2570 switch (Opc) { 2571 default: assert(0 && "Cannot expand this yet!"); 2572 case ISD::CTPOP: { 2573 EVT VT = Op.getValueType(); 2574 EVT ShVT = TLI.getShiftAmountTy(VT); 2575 unsigned Len = VT.getSizeInBits(); 2576 2577 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 && 2578 "CTPOP not implemented for this type."); 2579 2580 // This is the "best" algorithm from 2581 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel 2582 2583 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT); 2584 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT); 2585 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT); 2586 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT); 2587 2588 // v = v - ((v >> 1) & 0x55555555...) 2589 Op = DAG.getNode(ISD::SUB, dl, VT, Op, 2590 DAG.getNode(ISD::AND, dl, VT, 2591 DAG.getNode(ISD::SRL, dl, VT, Op, 2592 DAG.getConstant(1, ShVT)), 2593 Mask55)); 2594 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...) 2595 Op = DAG.getNode(ISD::ADD, dl, VT, 2596 DAG.getNode(ISD::AND, dl, VT, Op, Mask33), 2597 DAG.getNode(ISD::AND, dl, VT, 2598 DAG.getNode(ISD::SRL, dl, VT, Op, 2599 DAG.getConstant(2, ShVT)), 2600 Mask33)); 2601 // v = (v + (v >> 4)) & 0x0F0F0F0F... 2602 Op = DAG.getNode(ISD::AND, dl, VT, 2603 DAG.getNode(ISD::ADD, dl, VT, Op, 2604 DAG.getNode(ISD::SRL, dl, VT, Op, 2605 DAG.getConstant(4, ShVT))), 2606 Mask0F); 2607 // v = (v * 0x01010101...) >> (Len - 8) 2608 Op = DAG.getNode(ISD::SRL, dl, VT, 2609 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01), 2610 DAG.getConstant(Len - 8, ShVT)); 2611 2612 return Op; 2613 } 2614 case ISD::CTLZ: { 2615 // for now, we do this: 2616 // x = x | (x >> 1); 2617 // x = x | (x >> 2); 2618 // ... 2619 // x = x | (x >>16); 2620 // x = x | (x >>32); // for 64-bit input 2621 // return popcount(~x); 2622 // 2623 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2624 EVT VT = Op.getValueType(); 2625 EVT ShVT = TLI.getShiftAmountTy(VT); 2626 unsigned len = VT.getSizeInBits(); 2627 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2628 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2629 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2630 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2631 } 2632 Op = DAG.getNOT(dl, Op, VT); 2633 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2634 } 2635 case ISD::CTTZ: { 2636 // for now, we use: { return popcount(~x & (x - 1)); } 2637 // unless the target has ctlz but not ctpop, in which case we use: 2638 // { return 32 - nlz(~x & (x-1)); } 2639 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2640 EVT VT = Op.getValueType(); 2641 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2642 DAG.getNOT(dl, Op, VT), 2643 DAG.getNode(ISD::SUB, dl, VT, Op, 2644 DAG.getConstant(1, VT))); 2645 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2646 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2647 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2648 return DAG.getNode(ISD::SUB, dl, VT, 2649 DAG.getConstant(VT.getSizeInBits(), VT), 2650 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2651 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2652 } 2653 } 2654} 2655 2656std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) { 2657 unsigned Opc = Node->getOpcode(); 2658 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 2659 RTLIB::Libcall LC; 2660 2661 switch (Opc) { 2662 default: 2663 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 2664 break; 2665 case ISD::ATOMIC_SWAP: 2666 switch (VT.SimpleTy) { 2667 default: llvm_unreachable("Unexpected value type for atomic!"); 2668 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; 2669 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 2670 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; 2671 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; 2672 } 2673 break; 2674 case ISD::ATOMIC_CMP_SWAP: 2675 switch (VT.SimpleTy) { 2676 default: llvm_unreachable("Unexpected value type for atomic!"); 2677 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 2678 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 2679 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 2680 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 2681 } 2682 break; 2683 case ISD::ATOMIC_LOAD_ADD: 2684 switch (VT.SimpleTy) { 2685 default: llvm_unreachable("Unexpected value type for atomic!"); 2686 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 2687 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 2688 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 2689 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 2690 } 2691 break; 2692 case ISD::ATOMIC_LOAD_SUB: 2693 switch (VT.SimpleTy) { 2694 default: llvm_unreachable("Unexpected value type for atomic!"); 2695 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 2696 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 2697 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 2698 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 2699 } 2700 break; 2701 case ISD::ATOMIC_LOAD_AND: 2702 switch (VT.SimpleTy) { 2703 default: llvm_unreachable("Unexpected value type for atomic!"); 2704 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 2705 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 2706 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 2707 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 2708 } 2709 break; 2710 case ISD::ATOMIC_LOAD_OR: 2711 switch (VT.SimpleTy) { 2712 default: llvm_unreachable("Unexpected value type for atomic!"); 2713 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 2714 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 2715 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 2716 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 2717 } 2718 break; 2719 case ISD::ATOMIC_LOAD_XOR: 2720 switch (VT.SimpleTy) { 2721 default: llvm_unreachable("Unexpected value type for atomic!"); 2722 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 2723 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 2724 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 2725 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 2726 } 2727 break; 2728 case ISD::ATOMIC_LOAD_NAND: 2729 switch (VT.SimpleTy) { 2730 default: llvm_unreachable("Unexpected value type for atomic!"); 2731 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 2732 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 2733 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 2734 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 2735 } 2736 break; 2737 } 2738 2739 return ExpandChainLibCall(LC, Node, false); 2740} 2741 2742void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2743 SmallVectorImpl<SDValue> &Results) { 2744 DebugLoc dl = Node->getDebugLoc(); 2745 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2746 switch (Node->getOpcode()) { 2747 case ISD::CTPOP: 2748 case ISD::CTLZ: 2749 case ISD::CTTZ: 2750 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2751 Results.push_back(Tmp1); 2752 break; 2753 case ISD::BSWAP: 2754 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2755 break; 2756 case ISD::FRAMEADDR: 2757 case ISD::RETURNADDR: 2758 case ISD::FRAME_TO_ARGS_OFFSET: 2759 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2760 break; 2761 case ISD::FLT_ROUNDS_: 2762 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2763 break; 2764 case ISD::EH_RETURN: 2765 case ISD::EH_LABEL: 2766 case ISD::PREFETCH: 2767 case ISD::VAEND: 2768 case ISD::EH_SJLJ_LONGJMP: 2769 case ISD::EH_SJLJ_DISPATCHSETUP: 2770 // If the target didn't expand these, there's nothing to do, so just 2771 // preserve the chain and be done. 2772 Results.push_back(Node->getOperand(0)); 2773 break; 2774 case ISD::EH_SJLJ_SETJMP: 2775 // If the target didn't expand this, just return 'zero' and preserve the 2776 // chain. 2777 Results.push_back(DAG.getConstant(0, MVT::i32)); 2778 Results.push_back(Node->getOperand(0)); 2779 break; 2780 case ISD::MEMBARRIER: { 2781 // If the target didn't lower this, lower it to '__sync_synchronize()' call 2782 TargetLowering::ArgListTy Args; 2783 std::pair<SDValue, SDValue> CallResult = 2784 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2785 false, false, false, false, 0, CallingConv::C, 2786 /*isTailCall=*/false, 2787 /*isReturnValueUsed=*/true, 2788 DAG.getExternalSymbol("__sync_synchronize", 2789 TLI.getPointerTy()), 2790 Args, DAG, dl); 2791 Results.push_back(CallResult.second); 2792 break; 2793 } 2794 // By default, atomic intrinsics are marked Legal and lowered. Targets 2795 // which don't support them directly, however, may want libcalls, in which 2796 // case they mark them Expand, and we get here. 2797 case ISD::ATOMIC_SWAP: 2798 case ISD::ATOMIC_LOAD_ADD: 2799 case ISD::ATOMIC_LOAD_SUB: 2800 case ISD::ATOMIC_LOAD_AND: 2801 case ISD::ATOMIC_LOAD_OR: 2802 case ISD::ATOMIC_LOAD_XOR: 2803 case ISD::ATOMIC_LOAD_NAND: 2804 case ISD::ATOMIC_LOAD_MIN: 2805 case ISD::ATOMIC_LOAD_MAX: 2806 case ISD::ATOMIC_LOAD_UMIN: 2807 case ISD::ATOMIC_LOAD_UMAX: 2808 case ISD::ATOMIC_CMP_SWAP: { 2809 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node); 2810 Results.push_back(Tmp.first); 2811 Results.push_back(Tmp.second); 2812 break; 2813 } 2814 case ISD::DYNAMIC_STACKALLOC: 2815 ExpandDYNAMIC_STACKALLOC(Node, Results); 2816 break; 2817 case ISD::MERGE_VALUES: 2818 for (unsigned i = 0; i < Node->getNumValues(); i++) 2819 Results.push_back(Node->getOperand(i)); 2820 break; 2821 case ISD::UNDEF: { 2822 EVT VT = Node->getValueType(0); 2823 if (VT.isInteger()) 2824 Results.push_back(DAG.getConstant(0, VT)); 2825 else { 2826 assert(VT.isFloatingPoint() && "Unknown value type!"); 2827 Results.push_back(DAG.getConstantFP(0, VT)); 2828 } 2829 break; 2830 } 2831 case ISD::TRAP: { 2832 // If this operation is not supported, lower it to 'abort()' call 2833 TargetLowering::ArgListTy Args; 2834 std::pair<SDValue, SDValue> CallResult = 2835 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2836 false, false, false, false, 0, CallingConv::C, 2837 /*isTailCall=*/false, 2838 /*isReturnValueUsed=*/true, 2839 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2840 Args, DAG, dl); 2841 Results.push_back(CallResult.second); 2842 break; 2843 } 2844 case ISD::FP_ROUND: 2845 case ISD::BITCAST: 2846 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2847 Node->getValueType(0), dl); 2848 Results.push_back(Tmp1); 2849 break; 2850 case ISD::FP_EXTEND: 2851 Tmp1 = EmitStackConvert(Node->getOperand(0), 2852 Node->getOperand(0).getValueType(), 2853 Node->getValueType(0), dl); 2854 Results.push_back(Tmp1); 2855 break; 2856 case ISD::SIGN_EXTEND_INREG: { 2857 // NOTE: we could fall back on load/store here too for targets without 2858 // SAR. However, it is doubtful that any exist. 2859 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2860 EVT VT = Node->getValueType(0); 2861 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT); 2862 if (VT.isVector()) 2863 ShiftAmountTy = VT; 2864 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2865 ExtraVT.getScalarType().getSizeInBits(); 2866 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2867 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2868 Node->getOperand(0), ShiftCst); 2869 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2870 Results.push_back(Tmp1); 2871 break; 2872 } 2873 case ISD::FP_ROUND_INREG: { 2874 // The only way we can lower this is to turn it into a TRUNCSTORE, 2875 // EXTLOAD pair, targetting a temporary location (a stack slot). 2876 2877 // NOTE: there is a choice here between constantly creating new stack 2878 // slots and always reusing the same one. We currently always create 2879 // new ones, as reuse may inhibit scheduling. 2880 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2881 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2882 Node->getValueType(0), dl); 2883 Results.push_back(Tmp1); 2884 break; 2885 } 2886 case ISD::SINT_TO_FP: 2887 case ISD::UINT_TO_FP: 2888 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2889 Node->getOperand(0), Node->getValueType(0), dl); 2890 Results.push_back(Tmp1); 2891 break; 2892 case ISD::FP_TO_UINT: { 2893 SDValue True, False; 2894 EVT VT = Node->getOperand(0).getValueType(); 2895 EVT NVT = Node->getValueType(0); 2896 APFloat apf(APInt::getNullValue(VT.getSizeInBits())); 2897 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2898 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2899 Tmp1 = DAG.getConstantFP(apf, VT); 2900 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2901 Node->getOperand(0), 2902 Tmp1, ISD::SETLT); 2903 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2904 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2905 DAG.getNode(ISD::FSUB, dl, VT, 2906 Node->getOperand(0), Tmp1)); 2907 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2908 DAG.getConstant(x, NVT)); 2909 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2910 Results.push_back(Tmp1); 2911 break; 2912 } 2913 case ISD::VAARG: { 2914 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2915 EVT VT = Node->getValueType(0); 2916 Tmp1 = Node->getOperand(0); 2917 Tmp2 = Node->getOperand(1); 2918 unsigned Align = Node->getConstantOperandVal(3); 2919 2920 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, 2921 MachinePointerInfo(V), false, false, 0); 2922 SDValue VAList = VAListLoad; 2923 2924 if (Align > TLI.getMinStackArgumentAlignment()) { 2925 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2926 2927 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2928 DAG.getConstant(Align - 1, 2929 TLI.getPointerTy())); 2930 2931 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList, 2932 DAG.getConstant(-(int64_t)Align, 2933 TLI.getPointerTy())); 2934 } 2935 2936 // Increment the pointer, VAList, to the next vaarg 2937 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2938 DAG.getConstant(TLI.getTargetData()-> 2939 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2940 TLI.getPointerTy())); 2941 // Store the incremented VAList to the legalized pointer 2942 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, 2943 MachinePointerInfo(V), false, false, 0); 2944 // Load the actual argument out of the pointer VAList 2945 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(), 2946 false, false, 0)); 2947 Results.push_back(Results[0].getValue(1)); 2948 break; 2949 } 2950 case ISD::VACOPY: { 2951 // This defaults to loading a pointer from the input and storing it to the 2952 // output, returning the chain. 2953 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2954 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2955 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2956 Node->getOperand(2), MachinePointerInfo(VS), 2957 false, false, 0); 2958 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), 2959 MachinePointerInfo(VD), false, false, 0); 2960 Results.push_back(Tmp1); 2961 break; 2962 } 2963 case ISD::EXTRACT_VECTOR_ELT: 2964 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2965 // This must be an access of the only element. Return it. 2966 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), 2967 Node->getOperand(0)); 2968 else 2969 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2970 Results.push_back(Tmp1); 2971 break; 2972 case ISD::EXTRACT_SUBVECTOR: 2973 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2974 break; 2975 case ISD::INSERT_SUBVECTOR: 2976 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0))); 2977 break; 2978 case ISD::CONCAT_VECTORS: { 2979 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2980 break; 2981 } 2982 case ISD::SCALAR_TO_VECTOR: 2983 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2984 break; 2985 case ISD::INSERT_VECTOR_ELT: 2986 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2987 Node->getOperand(1), 2988 Node->getOperand(2), dl)); 2989 break; 2990 case ISD::VECTOR_SHUFFLE: { 2991 SmallVector<int, 8> Mask; 2992 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2993 2994 EVT VT = Node->getValueType(0); 2995 EVT EltVT = VT.getVectorElementType(); 2996 if (getTypeAction(EltVT) == Promote) 2997 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT); 2998 unsigned NumElems = VT.getVectorNumElements(); 2999 SmallVector<SDValue, 8> Ops; 3000 for (unsigned i = 0; i != NumElems; ++i) { 3001 if (Mask[i] < 0) { 3002 Ops.push_back(DAG.getUNDEF(EltVT)); 3003 continue; 3004 } 3005 unsigned Idx = Mask[i]; 3006 if (Idx < NumElems) 3007 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 3008 Node->getOperand(0), 3009 DAG.getIntPtrConstant(Idx))); 3010 else 3011 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 3012 Node->getOperand(1), 3013 DAG.getIntPtrConstant(Idx - NumElems))); 3014 } 3015 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 3016 Results.push_back(Tmp1); 3017 break; 3018 } 3019 case ISD::EXTRACT_ELEMENT: { 3020 EVT OpTy = Node->getOperand(0).getValueType(); 3021 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 3022 // 1 -> Hi 3023 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 3024 DAG.getConstant(OpTy.getSizeInBits()/2, 3025 TLI.getShiftAmountTy(Node->getOperand(0).getValueType()))); 3026 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 3027 } else { 3028 // 0 -> Lo 3029 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 3030 Node->getOperand(0)); 3031 } 3032 Results.push_back(Tmp1); 3033 break; 3034 } 3035 case ISD::STACKSAVE: 3036 // Expand to CopyFromReg if the target set 3037 // StackPointerRegisterToSaveRestore. 3038 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 3039 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 3040 Node->getValueType(0))); 3041 Results.push_back(Results[0].getValue(1)); 3042 } else { 3043 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 3044 Results.push_back(Node->getOperand(0)); 3045 } 3046 break; 3047 case ISD::STACKRESTORE: 3048 // Expand to CopyToReg if the target set 3049 // StackPointerRegisterToSaveRestore. 3050 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 3051 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 3052 Node->getOperand(1))); 3053 } else { 3054 Results.push_back(Node->getOperand(0)); 3055 } 3056 break; 3057 case ISD::FCOPYSIGN: 3058 Results.push_back(ExpandFCOPYSIGN(Node)); 3059 break; 3060 case ISD::FNEG: 3061 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3062 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3063 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 3064 Node->getOperand(0)); 3065 Results.push_back(Tmp1); 3066 break; 3067 case ISD::FABS: { 3068 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3069 EVT VT = Node->getValueType(0); 3070 Tmp1 = Node->getOperand(0); 3071 Tmp2 = DAG.getConstantFP(0.0, VT); 3072 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 3073 Tmp1, Tmp2, ISD::SETUGT); 3074 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 3075 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 3076 Results.push_back(Tmp1); 3077 break; 3078 } 3079 case ISD::FSQRT: 3080 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3081 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 3082 break; 3083 case ISD::FSIN: 3084 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 3085 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 3086 break; 3087 case ISD::FCOS: 3088 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 3089 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 3090 break; 3091 case ISD::FLOG: 3092 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 3093 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 3094 break; 3095 case ISD::FLOG2: 3096 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 3097 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 3098 break; 3099 case ISD::FLOG10: 3100 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 3101 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 3102 break; 3103 case ISD::FEXP: 3104 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 3105 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 3106 break; 3107 case ISD::FEXP2: 3108 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 3109 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 3110 break; 3111 case ISD::FTRUNC: 3112 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 3113 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 3114 break; 3115 case ISD::FFLOOR: 3116 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 3117 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 3118 break; 3119 case ISD::FCEIL: 3120 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 3121 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 3122 break; 3123 case ISD::FRINT: 3124 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 3125 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 3126 break; 3127 case ISD::FNEARBYINT: 3128 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 3129 RTLIB::NEARBYINT_F64, 3130 RTLIB::NEARBYINT_F80, 3131 RTLIB::NEARBYINT_PPCF128)); 3132 break; 3133 case ISD::FPOWI: 3134 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 3135 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 3136 break; 3137 case ISD::FPOW: 3138 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 3139 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 3140 break; 3141 case ISD::FDIV: 3142 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 3143 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 3144 break; 3145 case ISD::FREM: 3146 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 3147 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 3148 break; 3149 case ISD::FP16_TO_FP32: 3150 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 3151 break; 3152 case ISD::FP32_TO_FP16: 3153 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 3154 break; 3155 case ISD::ConstantFP: { 3156 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 3157 // Check to see if this FP immediate is already legal. 3158 // If this is a legal constant, turn it into a TargetConstantFP node. 3159 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 3160 Results.push_back(SDValue(Node, 0)); 3161 else 3162 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 3163 break; 3164 } 3165 case ISD::EHSELECTION: { 3166 unsigned Reg = TLI.getExceptionSelectorRegister(); 3167 assert(Reg && "Can't expand to unknown register!"); 3168 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 3169 Node->getValueType(0))); 3170 Results.push_back(Results[0].getValue(1)); 3171 break; 3172 } 3173 case ISD::EXCEPTIONADDR: { 3174 unsigned Reg = TLI.getExceptionAddressRegister(); 3175 assert(Reg && "Can't expand to unknown register!"); 3176 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 3177 Node->getValueType(0))); 3178 Results.push_back(Results[0].getValue(1)); 3179 break; 3180 } 3181 case ISD::SUB: { 3182 EVT VT = Node->getValueType(0); 3183 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 3184 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 3185 "Don't know how to expand this subtraction!"); 3186 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 3187 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 3188 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 3189 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 3190 break; 3191 } 3192 case ISD::UREM: 3193 case ISD::SREM: { 3194 EVT VT = Node->getValueType(0); 3195 SDVTList VTs = DAG.getVTList(VT, VT); 3196 bool isSigned = Node->getOpcode() == ISD::SREM; 3197 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 3198 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 3199 Tmp2 = Node->getOperand(0); 3200 Tmp3 = Node->getOperand(1); 3201 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 3202 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 3203 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 3204 // X % Y -> X-X/Y*Y 3205 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 3206 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 3207 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 3208 } else if (isSigned) { 3209 Tmp1 = ExpandDivRemLibCall(Node, true, false); 3210 if (!Tmp1.getNode()) 3211 Tmp1 = ExpandIntLibCall(Node, true, 3212 RTLIB::SREM_I8, 3213 RTLIB::SREM_I16, RTLIB::SREM_I32, 3214 RTLIB::SREM_I64, RTLIB::SREM_I128); 3215 } else { 3216 Tmp1 = ExpandDivRemLibCall(Node, false, false); 3217 if (!Tmp1.getNode()) 3218 Tmp1 = ExpandIntLibCall(Node, false, 3219 RTLIB::UREM_I8, 3220 RTLIB::UREM_I16, RTLIB::UREM_I32, 3221 RTLIB::UREM_I64, RTLIB::UREM_I128); 3222 } 3223 Results.push_back(Tmp1); 3224 break; 3225 } 3226 case ISD::UDIV: 3227 case ISD::SDIV: { 3228 bool isSigned = Node->getOpcode() == ISD::SDIV; 3229 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 3230 EVT VT = Node->getValueType(0); 3231 SDVTList VTs = DAG.getVTList(VT, VT); 3232 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 3233 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 3234 Node->getOperand(1)); 3235 else if (isSigned) { 3236 Tmp1 = ExpandDivRemLibCall(Node, true, true); 3237 if (!Tmp1.getNode()) { 3238 Tmp1 = ExpandIntLibCall(Node, true, 3239 RTLIB::SDIV_I8, 3240 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 3241 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 3242 } 3243 } else { 3244 Tmp1 = ExpandDivRemLibCall(Node, false, true); 3245 if (!Tmp1.getNode()) { 3246 Tmp1 = ExpandIntLibCall(Node, false, 3247 RTLIB::UDIV_I8, 3248 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 3249 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 3250 } 3251 } 3252 Results.push_back(Tmp1); 3253 break; 3254 } 3255 case ISD::MULHU: 3256 case ISD::MULHS: { 3257 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 3258 ISD::SMUL_LOHI; 3259 EVT VT = Node->getValueType(0); 3260 SDVTList VTs = DAG.getVTList(VT, VT); 3261 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 3262 "If this wasn't legal, it shouldn't have been created!"); 3263 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 3264 Node->getOperand(1)); 3265 Results.push_back(Tmp1.getValue(1)); 3266 break; 3267 } 3268 case ISD::MUL: { 3269 EVT VT = Node->getValueType(0); 3270 SDVTList VTs = DAG.getVTList(VT, VT); 3271 // See if multiply or divide can be lowered using two-result operations. 3272 // We just need the low half of the multiply; try both the signed 3273 // and unsigned forms. If the target supports both SMUL_LOHI and 3274 // UMUL_LOHI, form a preference by checking which forms of plain 3275 // MULH it supports. 3276 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 3277 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 3278 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 3279 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 3280 unsigned OpToUse = 0; 3281 if (HasSMUL_LOHI && !HasMULHS) { 3282 OpToUse = ISD::SMUL_LOHI; 3283 } else if (HasUMUL_LOHI && !HasMULHU) { 3284 OpToUse = ISD::UMUL_LOHI; 3285 } else if (HasSMUL_LOHI) { 3286 OpToUse = ISD::SMUL_LOHI; 3287 } else if (HasUMUL_LOHI) { 3288 OpToUse = ISD::UMUL_LOHI; 3289 } 3290 if (OpToUse) { 3291 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 3292 Node->getOperand(1))); 3293 break; 3294 } 3295 Tmp1 = ExpandIntLibCall(Node, false, 3296 RTLIB::MUL_I8, 3297 RTLIB::MUL_I16, RTLIB::MUL_I32, 3298 RTLIB::MUL_I64, RTLIB::MUL_I128); 3299 Results.push_back(Tmp1); 3300 break; 3301 } 3302 case ISD::SADDO: 3303 case ISD::SSUBO: { 3304 SDValue LHS = Node->getOperand(0); 3305 SDValue RHS = Node->getOperand(1); 3306 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 3307 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3308 LHS, RHS); 3309 Results.push_back(Sum); 3310 EVT OType = Node->getValueType(1); 3311 3312 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 3313 3314 // LHSSign -> LHS >= 0 3315 // RHSSign -> RHS >= 0 3316 // SumSign -> Sum >= 0 3317 // 3318 // Add: 3319 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 3320 // Sub: 3321 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 3322 // 3323 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 3324 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 3325 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 3326 Node->getOpcode() == ISD::SADDO ? 3327 ISD::SETEQ : ISD::SETNE); 3328 3329 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 3330 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 3331 3332 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 3333 Results.push_back(Cmp); 3334 break; 3335 } 3336 case ISD::UADDO: 3337 case ISD::USUBO: { 3338 SDValue LHS = Node->getOperand(0); 3339 SDValue RHS = Node->getOperand(1); 3340 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 3341 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3342 LHS, RHS); 3343 Results.push_back(Sum); 3344 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 3345 Node->getOpcode () == ISD::UADDO ? 3346 ISD::SETULT : ISD::SETUGT)); 3347 break; 3348 } 3349 case ISD::UMULO: 3350 case ISD::SMULO: { 3351 EVT VT = Node->getValueType(0); 3352 SDValue LHS = Node->getOperand(0); 3353 SDValue RHS = Node->getOperand(1); 3354 SDValue BottomHalf; 3355 SDValue TopHalf; 3356 static const unsigned Ops[2][3] = 3357 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 3358 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 3359 bool isSigned = Node->getOpcode() == ISD::SMULO; 3360 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 3361 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 3362 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 3363 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 3364 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 3365 RHS); 3366 TopHalf = BottomHalf.getValue(1); 3367 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), 3368 VT.getSizeInBits() * 2))) { 3369 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 3370 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 3371 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 3372 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 3373 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3374 DAG.getIntPtrConstant(0)); 3375 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3376 DAG.getIntPtrConstant(1)); 3377 } else { 3378 // We can fall back to a libcall with an illegal type for the MUL if we 3379 // have a libcall big enough. 3380 // Also, we can fall back to a division in some cases, but that's a big 3381 // performance hit in the general case. 3382 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 3383 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3384 if (WideVT == MVT::i16) 3385 LC = RTLIB::MUL_I16; 3386 else if (WideVT == MVT::i32) 3387 LC = RTLIB::MUL_I32; 3388 else if (WideVT == MVT::i64) 3389 LC = RTLIB::MUL_I64; 3390 else if (WideVT == MVT::i128) 3391 LC = RTLIB::MUL_I128; 3392 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!"); 3393 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 3394 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 3395 3396 SDValue Ret = ExpandLibCall(LC, Node, isSigned); 3397 BottomHalf = DAG.getNode(ISD::TRUNCATE, dl, VT, Ret); 3398 TopHalf = DAG.getNode(ISD::SRL, dl, Ret.getValueType(), Ret, 3399 DAG.getConstant(VT.getSizeInBits(), TLI.getPointerTy())); 3400 TopHalf = DAG.getNode(ISD::TRUNCATE, dl, VT, TopHalf); 3401 } 3402 if (isSigned) { 3403 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, 3404 TLI.getShiftAmountTy(BottomHalf.getValueType())); 3405 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 3406 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 3407 ISD::SETNE); 3408 } else { 3409 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 3410 DAG.getConstant(0, VT), ISD::SETNE); 3411 } 3412 Results.push_back(BottomHalf); 3413 Results.push_back(TopHalf); 3414 break; 3415 } 3416 case ISD::BUILD_PAIR: { 3417 EVT PairTy = Node->getValueType(0); 3418 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 3419 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 3420 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 3421 DAG.getConstant(PairTy.getSizeInBits()/2, 3422 TLI.getShiftAmountTy(PairTy))); 3423 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 3424 break; 3425 } 3426 case ISD::SELECT: 3427 Tmp1 = Node->getOperand(0); 3428 Tmp2 = Node->getOperand(1); 3429 Tmp3 = Node->getOperand(2); 3430 if (Tmp1.getOpcode() == ISD::SETCC) { 3431 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 3432 Tmp2, Tmp3, 3433 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 3434 } else { 3435 Tmp1 = DAG.getSelectCC(dl, Tmp1, 3436 DAG.getConstant(0, Tmp1.getValueType()), 3437 Tmp2, Tmp3, ISD::SETNE); 3438 } 3439 Results.push_back(Tmp1); 3440 break; 3441 case ISD::BR_JT: { 3442 SDValue Chain = Node->getOperand(0); 3443 SDValue Table = Node->getOperand(1); 3444 SDValue Index = Node->getOperand(2); 3445 3446 EVT PTy = TLI.getPointerTy(); 3447 3448 const TargetData &TD = *TLI.getTargetData(); 3449 unsigned EntrySize = 3450 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 3451 3452 Index = DAG.getNode(ISD::MUL, dl, PTy, 3453 Index, DAG.getConstant(EntrySize, PTy)); 3454 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 3455 3456 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 3457 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 3458 MachinePointerInfo::getJumpTable(), MemVT, 3459 false, false, 0); 3460 Addr = LD; 3461 if (TM.getRelocationModel() == Reloc::PIC_) { 3462 // For PIC, the sequence is: 3463 // BRIND(load(Jumptable + index) + RelocBase) 3464 // RelocBase can be JumpTable, GOT or some sort of global base. 3465 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 3466 TLI.getPICJumpTableRelocBase(Table, DAG)); 3467 } 3468 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 3469 Results.push_back(Tmp1); 3470 break; 3471 } 3472 case ISD::BRCOND: 3473 // Expand brcond's setcc into its constituent parts and create a BR_CC 3474 // Node. 3475 Tmp1 = Node->getOperand(0); 3476 Tmp2 = Node->getOperand(1); 3477 if (Tmp2.getOpcode() == ISD::SETCC) { 3478 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 3479 Tmp1, Tmp2.getOperand(2), 3480 Tmp2.getOperand(0), Tmp2.getOperand(1), 3481 Node->getOperand(2)); 3482 } else { 3483 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 3484 DAG.getCondCode(ISD::SETNE), Tmp2, 3485 DAG.getConstant(0, Tmp2.getValueType()), 3486 Node->getOperand(2)); 3487 } 3488 Results.push_back(Tmp1); 3489 break; 3490 case ISD::SETCC: { 3491 Tmp1 = Node->getOperand(0); 3492 Tmp2 = Node->getOperand(1); 3493 Tmp3 = Node->getOperand(2); 3494 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 3495 3496 // If we expanded the SETCC into an AND/OR, return the new node 3497 if (Tmp2.getNode() == 0) { 3498 Results.push_back(Tmp1); 3499 break; 3500 } 3501 3502 // Otherwise, SETCC for the given comparison type must be completely 3503 // illegal; expand it into a SELECT_CC. 3504 EVT VT = Node->getValueType(0); 3505 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3506 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 3507 Results.push_back(Tmp1); 3508 break; 3509 } 3510 case ISD::SELECT_CC: { 3511 Tmp1 = Node->getOperand(0); // LHS 3512 Tmp2 = Node->getOperand(1); // RHS 3513 Tmp3 = Node->getOperand(2); // True 3514 Tmp4 = Node->getOperand(3); // False 3515 SDValue CC = Node->getOperand(4); 3516 3517 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 3518 Tmp1, Tmp2, CC, dl); 3519 3520 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 3521 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3522 CC = DAG.getCondCode(ISD::SETNE); 3523 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 3524 Tmp3, Tmp4, CC); 3525 Results.push_back(Tmp1); 3526 break; 3527 } 3528 case ISD::BR_CC: { 3529 Tmp1 = Node->getOperand(0); // Chain 3530 Tmp2 = Node->getOperand(2); // LHS 3531 Tmp3 = Node->getOperand(3); // RHS 3532 Tmp4 = Node->getOperand(1); // CC 3533 3534 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 3535 Tmp2, Tmp3, Tmp4, dl); 3536 LastCALLSEQ_END = DAG.getEntryNode(); 3537 3538 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 3539 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 3540 Tmp4 = DAG.getCondCode(ISD::SETNE); 3541 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 3542 Tmp3, Node->getOperand(4)); 3543 Results.push_back(Tmp1); 3544 break; 3545 } 3546 case ISD::GLOBAL_OFFSET_TABLE: 3547 case ISD::GlobalAddress: 3548 case ISD::GlobalTLSAddress: 3549 case ISD::ExternalSymbol: 3550 case ISD::ConstantPool: 3551 case ISD::JumpTable: 3552 case ISD::INTRINSIC_W_CHAIN: 3553 case ISD::INTRINSIC_WO_CHAIN: 3554 case ISD::INTRINSIC_VOID: 3555 // FIXME: Custom lowering for these operations shouldn't return null! 3556 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3557 Results.push_back(SDValue(Node, i)); 3558 break; 3559 } 3560} 3561void SelectionDAGLegalize::PromoteNode(SDNode *Node, 3562 SmallVectorImpl<SDValue> &Results) { 3563 EVT OVT = Node->getValueType(0); 3564 if (Node->getOpcode() == ISD::UINT_TO_FP || 3565 Node->getOpcode() == ISD::SINT_TO_FP || 3566 Node->getOpcode() == ISD::SETCC) { 3567 OVT = Node->getOperand(0).getValueType(); 3568 } 3569 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3570 DebugLoc dl = Node->getDebugLoc(); 3571 SDValue Tmp1, Tmp2, Tmp3; 3572 switch (Node->getOpcode()) { 3573 case ISD::CTTZ: 3574 case ISD::CTLZ: 3575 case ISD::CTPOP: 3576 // Zero extend the argument. 3577 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3578 // Perform the larger operation. 3579 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3580 if (Node->getOpcode() == ISD::CTTZ) { 3581 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3582 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 3583 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3584 ISD::SETEQ); 3585 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3586 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3587 } else if (Node->getOpcode() == ISD::CTLZ) { 3588 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3589 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3590 DAG.getConstant(NVT.getSizeInBits() - 3591 OVT.getSizeInBits(), NVT)); 3592 } 3593 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3594 break; 3595 case ISD::BSWAP: { 3596 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3597 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3598 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3599 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3600 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT))); 3601 Results.push_back(Tmp1); 3602 break; 3603 } 3604 case ISD::FP_TO_UINT: 3605 case ISD::FP_TO_SINT: 3606 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3607 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3608 Results.push_back(Tmp1); 3609 break; 3610 case ISD::UINT_TO_FP: 3611 case ISD::SINT_TO_FP: 3612 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3613 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3614 Results.push_back(Tmp1); 3615 break; 3616 case ISD::AND: 3617 case ISD::OR: 3618 case ISD::XOR: { 3619 unsigned ExtOp, TruncOp; 3620 if (OVT.isVector()) { 3621 ExtOp = ISD::BITCAST; 3622 TruncOp = ISD::BITCAST; 3623 } else { 3624 assert(OVT.isInteger() && "Cannot promote logic operation"); 3625 ExtOp = ISD::ANY_EXTEND; 3626 TruncOp = ISD::TRUNCATE; 3627 } 3628 // Promote each of the values to the new type. 3629 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3630 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3631 // Perform the larger operation, then convert back 3632 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3633 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3634 break; 3635 } 3636 case ISD::SELECT: { 3637 unsigned ExtOp, TruncOp; 3638 if (Node->getValueType(0).isVector()) { 3639 ExtOp = ISD::BITCAST; 3640 TruncOp = ISD::BITCAST; 3641 } else if (Node->getValueType(0).isInteger()) { 3642 ExtOp = ISD::ANY_EXTEND; 3643 TruncOp = ISD::TRUNCATE; 3644 } else { 3645 ExtOp = ISD::FP_EXTEND; 3646 TruncOp = ISD::FP_ROUND; 3647 } 3648 Tmp1 = Node->getOperand(0); 3649 // Promote each of the values to the new type. 3650 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3651 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3652 // Perform the larger operation, then round down. 3653 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3654 if (TruncOp != ISD::FP_ROUND) 3655 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3656 else 3657 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3658 DAG.getIntPtrConstant(0)); 3659 Results.push_back(Tmp1); 3660 break; 3661 } 3662 case ISD::VECTOR_SHUFFLE: { 3663 SmallVector<int, 8> Mask; 3664 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3665 3666 // Cast the two input vectors. 3667 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0)); 3668 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1)); 3669 3670 // Convert the shuffle mask to the right # elements. 3671 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3672 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1); 3673 Results.push_back(Tmp1); 3674 break; 3675 } 3676 case ISD::SETCC: { 3677 unsigned ExtOp = ISD::FP_EXTEND; 3678 if (NVT.isInteger()) { 3679 ISD::CondCode CCCode = 3680 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3681 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3682 } 3683 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3684 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3685 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3686 Tmp1, Tmp2, Node->getOperand(2))); 3687 break; 3688 } 3689 } 3690} 3691 3692// SelectionDAG::Legalize - This is the entry point for the file. 3693// 3694void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) { 3695 /// run - This is the main entry point to this class. 3696 /// 3697 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3698} 3699 3700