LegalizeDAG.cpp revision 92c439168b552f73b1459d8ce1e31975cdca6d2a
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetFrameInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/Target/TargetSubtarget.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Compiler.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/ADT/DenseMap.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/SmallPtrSet.h" 35#include <map> 36using namespace llvm; 37 38#ifndef NDEBUG 39static cl::opt<bool> 40ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 41 cl::desc("Pop up a window to show dags before legalize")); 42#else 43static const bool ViewLegalizeDAGs = 0; 44#endif 45 46//===----------------------------------------------------------------------===// 47/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 48/// hacks on it until the target machine can handle it. This involves 49/// eliminating value sizes the machine cannot handle (promoting small sizes to 50/// large sizes or splitting up large values into small values) as well as 51/// eliminating operations the machine cannot handle. 52/// 53/// This code also does a small amount of optimization and recognition of idioms 54/// as part of its processing. For example, if a target does not support a 55/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 56/// will attempt merge setcc and brc instructions into brcc's. 57/// 58namespace { 59class VISIBILITY_HIDDEN SelectionDAGLegalize { 60 TargetLowering &TLI; 61 SelectionDAG &DAG; 62 63 // Libcall insertion helpers. 64 65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 66 /// legalized. We use this to ensure that calls are properly serialized 67 /// against each other, including inserted libcalls. 68 SDOperand LastCALLSEQ_END; 69 70 /// IsLegalizingCall - This member is used *only* for purposes of providing 71 /// helpful assertions that a libcall isn't created while another call is 72 /// being legalized (which could lead to non-serialized call sequences). 73 bool IsLegalizingCall; 74 75 enum LegalizeAction { 76 Legal, // The target natively supports this operation. 77 Promote, // This operation should be executed in a larger type. 78 Expand // Try to expand this to other ops, otherwise use a libcall. 79 }; 80 81 /// ValueTypeActions - This is a bitvector that contains two bits for each 82 /// value type, where the two bits correspond to the LegalizeAction enum. 83 /// This can be queried with "getTypeAction(VT)". 84 TargetLowering::ValueTypeActionImpl ValueTypeActions; 85 86 /// LegalizedNodes - For nodes that are of legal width, and that have more 87 /// than one use, this map indicates what regularized operand to use. This 88 /// allows us to avoid legalizing the same thing more than once. 89 DenseMap<SDOperand, SDOperand> LegalizedNodes; 90 91 /// PromotedNodes - For nodes that are below legal width, and that have more 92 /// than one use, this map indicates what promoted value to use. This allows 93 /// us to avoid promoting the same thing more than once. 94 DenseMap<SDOperand, SDOperand> PromotedNodes; 95 96 /// ExpandedNodes - For nodes that need to be expanded this map indicates 97 /// which which operands are the expanded version of the input. This allows 98 /// us to avoid expanding the same node more than once. 99 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 100 101 /// SplitNodes - For vector nodes that need to be split, this map indicates 102 /// which which operands are the split version of the input. This allows us 103 /// to avoid splitting the same node more than once. 104 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 105 106 /// ScalarizedNodes - For nodes that need to be converted from vector types to 107 /// scalar types, this contains the mapping of ones we have already 108 /// processed to the result. 109 std::map<SDOperand, SDOperand> ScalarizedNodes; 110 111 void AddLegalizedOperand(SDOperand From, SDOperand To) { 112 LegalizedNodes.insert(std::make_pair(From, To)); 113 // If someone requests legalization of the new node, return itself. 114 if (From != To) 115 LegalizedNodes.insert(std::make_pair(To, To)); 116 } 117 void AddPromotedOperand(SDOperand From, SDOperand To) { 118 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 119 assert(isNew && "Got into the map somehow?"); 120 // If someone requests legalization of the new node, return itself. 121 LegalizedNodes.insert(std::make_pair(To, To)); 122 } 123 124public: 125 126 SelectionDAGLegalize(SelectionDAG &DAG); 127 128 /// getTypeAction - Return how we should legalize values of this type, either 129 /// it is already legal or we need to expand it into multiple registers of 130 /// smaller integer type, or we need to promote it to a larger type. 131 LegalizeAction getTypeAction(MVT VT) const { 132 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 133 } 134 135 /// isTypeLegal - Return true if this type is legal on this target. 136 /// 137 bool isTypeLegal(MVT VT) const { 138 return getTypeAction(VT) == Legal; 139 } 140 141 void LegalizeDAG(); 142 143private: 144 /// HandleOp - Legalize, Promote, or Expand the specified operand as 145 /// appropriate for its type. 146 void HandleOp(SDOperand Op); 147 148 /// LegalizeOp - We know that the specified value has a legal type. 149 /// Recursively ensure that the operands have legal types, then return the 150 /// result. 151 SDOperand LegalizeOp(SDOperand O); 152 153 /// UnrollVectorOp - We know that the given vector has a legal type, however 154 /// the operation it performs is not legal and is an operation that we have 155 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 156 /// operating on each element individually. 157 SDOperand UnrollVectorOp(SDOperand O); 158 159 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 160 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 161 /// is necessary to spill the vector being inserted into to memory, perform 162 /// the insert there, and then read the result back. 163 SDOperand PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, 164 SDOperand Idx); 165 166 /// PromoteOp - Given an operation that produces a value in an invalid type, 167 /// promote it to compute the value into a larger type. The produced value 168 /// will have the correct bits for the low portion of the register, but no 169 /// guarantee is made about the top bits: it may be zero, sign-extended, or 170 /// garbage. 171 SDOperand PromoteOp(SDOperand O); 172 173 /// ExpandOp - Expand the specified SDOperand into its two component pieces 174 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 175 /// the LegalizeNodes map is filled in for any results that are not expanded, 176 /// the ExpandedNodes map is filled in for any results that are expanded, and 177 /// the Lo/Hi values are returned. This applies to integer types and Vector 178 /// types. 179 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 180 181 /// SplitVectorOp - Given an operand of vector type, break it down into 182 /// two smaller values. 183 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 184 185 /// ScalarizeVectorOp - Given an operand of single-element vector type 186 /// (e.g. v1f32), convert it into the equivalent operation that returns a 187 /// scalar (e.g. f32) value. 188 SDOperand ScalarizeVectorOp(SDOperand O); 189 190 /// isShuffleLegal - Return true if a vector shuffle is legal with the 191 /// specified mask and type. Targets can specify exactly which masks they 192 /// support and the code generator is tasked with not creating illegal masks. 193 /// 194 /// Note that this will also return true for shuffles that are promoted to a 195 /// different type. 196 /// 197 /// If this is a legal shuffle, this method returns the (possibly promoted) 198 /// build_vector Mask. If it's not a legal shuffle, it returns null. 199 SDNode *isShuffleLegal(MVT VT, SDOperand Mask) const; 200 201 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 202 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 203 204 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 205 206 SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, 207 SDOperand &Hi); 208 SDOperand ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source); 209 210 SDOperand EmitStackConvert(SDOperand SrcOp, MVT SlotVT, MVT DestVT); 211 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 212 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 213 SDOperand ExpandLegalINT_TO_FP(bool isSigned, SDOperand LegalOp, MVT DestVT); 214 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT DestVT, bool isSigned); 215 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT DestVT, bool isSigned); 216 217 SDOperand ExpandBSWAP(SDOperand Op); 218 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 219 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 220 SDOperand &Lo, SDOperand &Hi); 221 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 222 SDOperand &Lo, SDOperand &Hi); 223 224 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 225 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 226}; 227} 228 229/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 230/// specified mask and type. Targets can specify exactly which masks they 231/// support and the code generator is tasked with not creating illegal masks. 232/// 233/// Note that this will also return true for shuffles that are promoted to a 234/// different type. 235SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const { 236 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 237 default: return 0; 238 case TargetLowering::Legal: 239 case TargetLowering::Custom: 240 break; 241 case TargetLowering::Promote: { 242 // If this is promoted to a different type, convert the shuffle mask and 243 // ask if it is legal in the promoted type! 244 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 245 246 // If we changed # elements, change the shuffle mask. 247 unsigned NumEltsGrowth = 248 NVT.getVectorNumElements() / VT.getVectorNumElements(); 249 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 250 if (NumEltsGrowth > 1) { 251 // Renumber the elements. 252 SmallVector<SDOperand, 8> Ops; 253 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 254 SDOperand InOp = Mask.getOperand(i); 255 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 256 if (InOp.getOpcode() == ISD::UNDEF) 257 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 258 else { 259 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 260 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 261 } 262 } 263 } 264 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 265 } 266 VT = NVT; 267 break; 268 } 269 } 270 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 271} 272 273SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 274 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 275 ValueTypeActions(TLI.getValueTypeActions()) { 276 assert(MVT::LAST_VALUETYPE <= 32 && 277 "Too many value types for ValueTypeActions to hold!"); 278} 279 280/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 281/// contains all of a nodes operands before it contains the node. 282static void ComputeTopDownOrdering(SelectionDAG &DAG, 283 SmallVector<SDNode*, 64> &Order) { 284 285 DenseMap<SDNode*, unsigned> Visited; 286 std::vector<SDNode*> Worklist; 287 Worklist.reserve(128); 288 289 // Compute ordering from all of the leaves in the graphs, those (like the 290 // entry node) that have no operands. 291 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 292 E = DAG.allnodes_end(); I != E; ++I) { 293 if (I->getNumOperands() == 0) { 294 Visited[I] = 0 - 1U; 295 Worklist.push_back(I); 296 } 297 } 298 299 while (!Worklist.empty()) { 300 SDNode *N = Worklist.back(); 301 Worklist.pop_back(); 302 303 if (++Visited[N] != N->getNumOperands()) 304 continue; // Haven't visited all operands yet 305 306 Order.push_back(N); 307 308 // Now that we have N in, add anything that uses it if all of their operands 309 // are now done. 310 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 311 UI != E; ++UI) 312 Worklist.push_back(UI->getUser()); 313 } 314 315 assert(Order.size() == Visited.size() && 316 Order.size() == 317 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 318 "Error: DAG is cyclic!"); 319} 320 321 322void SelectionDAGLegalize::LegalizeDAG() { 323 LastCALLSEQ_END = DAG.getEntryNode(); 324 IsLegalizingCall = false; 325 326 // The legalize process is inherently a bottom-up recursive process (users 327 // legalize their uses before themselves). Given infinite stack space, we 328 // could just start legalizing on the root and traverse the whole graph. In 329 // practice however, this causes us to run out of stack space on large basic 330 // blocks. To avoid this problem, compute an ordering of the nodes where each 331 // node is only legalized after all of its operands are legalized. 332 SmallVector<SDNode*, 64> Order; 333 ComputeTopDownOrdering(DAG, Order); 334 335 for (unsigned i = 0, e = Order.size(); i != e; ++i) 336 HandleOp(SDOperand(Order[i], 0)); 337 338 // Finally, it's possible the root changed. Get the new root. 339 SDOperand OldRoot = DAG.getRoot(); 340 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 341 DAG.setRoot(LegalizedNodes[OldRoot]); 342 343 ExpandedNodes.clear(); 344 LegalizedNodes.clear(); 345 PromotedNodes.clear(); 346 SplitNodes.clear(); 347 ScalarizedNodes.clear(); 348 349 // Remove dead nodes now. 350 DAG.RemoveDeadNodes(); 351} 352 353 354/// FindCallEndFromCallStart - Given a chained node that is part of a call 355/// sequence, find the CALLSEQ_END node that terminates the call sequence. 356static SDNode *FindCallEndFromCallStart(SDNode *Node) { 357 if (Node->getOpcode() == ISD::CALLSEQ_END) 358 return Node; 359 if (Node->use_empty()) 360 return 0; // No CallSeqEnd 361 362 // The chain is usually at the end. 363 SDOperand TheChain(Node, Node->getNumValues()-1); 364 if (TheChain.getValueType() != MVT::Other) { 365 // Sometimes it's at the beginning. 366 TheChain = SDOperand(Node, 0); 367 if (TheChain.getValueType() != MVT::Other) { 368 // Otherwise, hunt for it. 369 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 370 if (Node->getValueType(i) == MVT::Other) { 371 TheChain = SDOperand(Node, i); 372 break; 373 } 374 375 // Otherwise, we walked into a node without a chain. 376 if (TheChain.getValueType() != MVT::Other) 377 return 0; 378 } 379 } 380 381 for (SDNode::use_iterator UI = Node->use_begin(), 382 E = Node->use_end(); UI != E; ++UI) { 383 384 // Make sure to only follow users of our token chain. 385 SDNode *User = UI->getUser(); 386 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 387 if (User->getOperand(i) == TheChain) 388 if (SDNode *Result = FindCallEndFromCallStart(User)) 389 return Result; 390 } 391 return 0; 392} 393 394/// FindCallStartFromCallEnd - Given a chained node that is part of a call 395/// sequence, find the CALLSEQ_START node that initiates the call sequence. 396static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 397 assert(Node && "Didn't find callseq_start for a call??"); 398 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 399 400 assert(Node->getOperand(0).getValueType() == MVT::Other && 401 "Node doesn't have a token chain argument!"); 402 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 403} 404 405/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 406/// see if any uses can reach Dest. If no dest operands can get to dest, 407/// legalize them, legalize ourself, and return false, otherwise, return true. 408/// 409/// Keep track of the nodes we fine that actually do lead to Dest in 410/// NodesLeadingTo. This avoids retraversing them exponential number of times. 411/// 412bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 413 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 414 if (N == Dest) return true; // N certainly leads to Dest :) 415 416 // If we've already processed this node and it does lead to Dest, there is no 417 // need to reprocess it. 418 if (NodesLeadingTo.count(N)) return true; 419 420 // If the first result of this node has been already legalized, then it cannot 421 // reach N. 422 switch (getTypeAction(N->getValueType(0))) { 423 case Legal: 424 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 425 break; 426 case Promote: 427 if (PromotedNodes.count(SDOperand(N, 0))) return false; 428 break; 429 case Expand: 430 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 431 break; 432 } 433 434 // Okay, this node has not already been legalized. Check and legalize all 435 // operands. If none lead to Dest, then we can legalize this node. 436 bool OperandsLeadToDest = false; 437 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 438 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 439 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 440 441 if (OperandsLeadToDest) { 442 NodesLeadingTo.insert(N); 443 return true; 444 } 445 446 // Okay, this node looks safe, legalize it and return false. 447 HandleOp(SDOperand(N, 0)); 448 return false; 449} 450 451/// HandleOp - Legalize, Promote, or Expand the specified operand as 452/// appropriate for its type. 453void SelectionDAGLegalize::HandleOp(SDOperand Op) { 454 MVT VT = Op.getValueType(); 455 switch (getTypeAction(VT)) { 456 default: assert(0 && "Bad type action!"); 457 case Legal: (void)LegalizeOp(Op); break; 458 case Promote: (void)PromoteOp(Op); break; 459 case Expand: 460 if (!VT.isVector()) { 461 // If this is an illegal scalar, expand it into its two component 462 // pieces. 463 SDOperand X, Y; 464 if (Op.getOpcode() == ISD::TargetConstant) 465 break; // Allow illegal target nodes. 466 ExpandOp(Op, X, Y); 467 } else if (VT.getVectorNumElements() == 1) { 468 // If this is an illegal single element vector, convert it to a 469 // scalar operation. 470 (void)ScalarizeVectorOp(Op); 471 } else { 472 // Otherwise, this is an illegal multiple element vector. 473 // Split it in half and legalize both parts. 474 SDOperand X, Y; 475 SplitVectorOp(Op, X, Y); 476 } 477 break; 478 } 479} 480 481/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 482/// a load from the constant pool. 483static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 484 SelectionDAG &DAG, TargetLowering &TLI) { 485 bool Extend = false; 486 487 // If a FP immediate is precise when represented as a float and if the 488 // target can do an extending load from float to double, we put it into 489 // the constant pool as a float, even if it's is statically typed as a 490 // double. This shrinks FP constants and canonicalizes them for targets where 491 // an FP extending load is the same cost as a normal load (such as on the x87 492 // fp stack or PPC FP unit). 493 MVT VT = CFP->getValueType(0); 494 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF()); 495 if (!UseCP) { 496 if (VT!=MVT::f64 && VT!=MVT::f32) 497 assert(0 && "Invalid type expansion"); 498 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(), 499 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 500 } 501 502 MVT OrigVT = VT; 503 MVT SVT = VT; 504 while (SVT != MVT::f32) { 505 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 506 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 507 // Only do this if the target has a native EXTLOAD instruction from 508 // smaller type. 509 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) && 510 TLI.ShouldShrinkFPConstant(OrigVT)) { 511 const Type *SType = SVT.getTypeForMVT(); 512 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 513 VT = SVT; 514 Extend = true; 515 } 516 } 517 518 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 519 if (Extend) 520 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), 521 CPIdx, PseudoSourceValue::getConstantPool(), 522 0, VT); 523 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, 524 PseudoSourceValue::getConstantPool(), 0); 525} 526 527 528/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 529/// operations. 530static 531SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, 532 SelectionDAG &DAG, TargetLowering &TLI) { 533 MVT VT = Node->getValueType(0); 534 MVT SrcVT = Node->getOperand(1).getValueType(); 535 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 536 "fcopysign expansion only supported for f32 and f64"); 537 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 538 539 // First get the sign bit of second operand. 540 SDOperand Mask1 = (SrcVT == MVT::f64) 541 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 542 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 543 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 544 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 545 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 546 // Shift right or sign-extend it if the two operands have different types. 547 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); 548 if (SizeDiff > 0) { 549 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 550 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 551 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 552 } else if (SizeDiff < 0) 553 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 554 555 // Clear the sign bit of first operand. 556 SDOperand Mask2 = (VT == MVT::f64) 557 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 558 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 559 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 560 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 561 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 562 563 // Or the value with the sign bit. 564 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 565 return Result; 566} 567 568/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 569static 570SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 571 TargetLowering &TLI) { 572 SDOperand Chain = ST->getChain(); 573 SDOperand Ptr = ST->getBasePtr(); 574 SDOperand Val = ST->getValue(); 575 MVT VT = Val.getValueType(); 576 int Alignment = ST->getAlignment(); 577 int SVOffset = ST->getSrcValueOffset(); 578 if (ST->getMemoryVT().isFloatingPoint() || 579 ST->getMemoryVT().isVector()) { 580 // Expand to a bitconvert of the value to the integer type of the 581 // same size, then a (misaligned) int store. 582 MVT intVT; 583 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128) 584 intVT = MVT::i128; 585 else if (VT.is64BitVector() || VT==MVT::f64) 586 intVT = MVT::i64; 587 else if (VT==MVT::f32) 588 intVT = MVT::i32; 589 else 590 assert(0 && "Unaligned store of unsupported type"); 591 592 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 593 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 594 SVOffset, ST->isVolatile(), Alignment); 595 } 596 assert(ST->getMemoryVT().isInteger() && 597 !ST->getMemoryVT().isVector() && 598 "Unaligned store of unknown type."); 599 // Get the half-size VT 600 MVT NewStoredVT = 601 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 602 int NumBits = NewStoredVT.getSizeInBits(); 603 int IncrementSize = NumBits / 8; 604 605 // Divide the stored value in two parts. 606 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 607 SDOperand Lo = Val; 608 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 609 610 // Store the two parts 611 SDOperand Store1, Store2; 612 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 613 ST->getSrcValue(), SVOffset, NewStoredVT, 614 ST->isVolatile(), Alignment); 615 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 616 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 617 Alignment = MinAlign(Alignment, IncrementSize); 618 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 619 ST->getSrcValue(), SVOffset + IncrementSize, 620 NewStoredVT, ST->isVolatile(), Alignment); 621 622 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 623} 624 625/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 626static 627SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 628 TargetLowering &TLI) { 629 int SVOffset = LD->getSrcValueOffset(); 630 SDOperand Chain = LD->getChain(); 631 SDOperand Ptr = LD->getBasePtr(); 632 MVT VT = LD->getValueType(0); 633 MVT LoadedVT = LD->getMemoryVT(); 634 if (VT.isFloatingPoint() || VT.isVector()) { 635 // Expand to a (misaligned) integer load of the same size, 636 // then bitconvert to floating point or vector. 637 MVT intVT; 638 if (LoadedVT.is128BitVector() || 639 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128) 640 intVT = MVT::i128; 641 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64) 642 intVT = MVT::i64; 643 else if (LoadedVT == MVT::f32) 644 intVT = MVT::i32; 645 else 646 assert(0 && "Unaligned load of unsupported type"); 647 648 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 649 SVOffset, LD->isVolatile(), 650 LD->getAlignment()); 651 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 652 if (VT.isFloatingPoint() && LoadedVT != VT) 653 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 654 655 SDOperand Ops[] = { Result, Chain }; 656 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 657 Ops, 2); 658 } 659 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 660 "Unaligned load of unsupported type."); 661 662 // Compute the new VT that is half the size of the old one. This is an 663 // integer MVT. 664 unsigned NumBits = LoadedVT.getSizeInBits(); 665 MVT NewLoadedVT; 666 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 667 NumBits >>= 1; 668 669 unsigned Alignment = LD->getAlignment(); 670 unsigned IncrementSize = NumBits / 8; 671 ISD::LoadExtType HiExtType = LD->getExtensionType(); 672 673 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 674 if (HiExtType == ISD::NON_EXTLOAD) 675 HiExtType = ISD::ZEXTLOAD; 676 677 // Load the value in two parts 678 SDOperand Lo, Hi; 679 if (TLI.isLittleEndian()) { 680 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 681 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 682 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 683 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 684 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 685 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 686 MinAlign(Alignment, IncrementSize)); 687 } else { 688 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 689 NewLoadedVT,LD->isVolatile(), Alignment); 690 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 691 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 692 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 693 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 694 MinAlign(Alignment, IncrementSize)); 695 } 696 697 // aggregate the two parts 698 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 699 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 700 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 701 702 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 703 Hi.getValue(1)); 704 705 SDOperand Ops[] = { Result, TF }; 706 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 707} 708 709/// UnrollVectorOp - We know that the given vector has a legal type, however 710/// the operation it performs is not legal and is an operation that we have 711/// no way of lowering. "Unroll" the vector, splitting out the scalars and 712/// operating on each element individually. 713SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { 714 MVT VT = Op.getValueType(); 715 assert(isTypeLegal(VT) && 716 "Caller should expand or promote operands that are not legal!"); 717 assert(Op.Val->getNumValues() == 1 && 718 "Can't unroll a vector with multiple results!"); 719 unsigned NE = VT.getVectorNumElements(); 720 MVT EltVT = VT.getVectorElementType(); 721 722 SmallVector<SDOperand, 8> Scalars; 723 SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); 724 for (unsigned i = 0; i != NE; ++i) { 725 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 726 SDOperand Operand = Op.getOperand(j); 727 MVT OperandVT = Operand.getValueType(); 728 if (OperandVT.isVector()) { 729 // A vector operand; extract a single element. 730 MVT OperandEltVT = OperandVT.getVectorElementType(); 731 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 732 OperandEltVT, 733 Operand, 734 DAG.getConstant(i, MVT::i32)); 735 } else { 736 // A scalar operand; just use it as is. 737 Operands[j] = Operand; 738 } 739 } 740 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 741 &Operands[0], Operands.size())); 742 } 743 744 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 745} 746 747/// GetFPLibCall - Return the right libcall for the given floating point type. 748static RTLIB::Libcall GetFPLibCall(MVT VT, 749 RTLIB::Libcall Call_F32, 750 RTLIB::Libcall Call_F64, 751 RTLIB::Libcall Call_F80, 752 RTLIB::Libcall Call_PPCF128) { 753 return 754 VT == MVT::f32 ? Call_F32 : 755 VT == MVT::f64 ? Call_F64 : 756 VT == MVT::f80 ? Call_F80 : 757 VT == MVT::ppcf128 ? Call_PPCF128 : 758 RTLIB::UNKNOWN_LIBCALL; 759} 760 761/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 762/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 763/// is necessary to spill the vector being inserted into to memory, perform 764/// the insert there, and then read the result back. 765SDOperand SelectionDAGLegalize:: 766PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) { 767 SDOperand Tmp1 = Vec; 768 SDOperand Tmp2 = Val; 769 SDOperand Tmp3 = Idx; 770 771 // If the target doesn't support this, we have to spill the input vector 772 // to a temporary stack slot, update the element, then reload it. This is 773 // badness. We could also load the value into a vector register (either 774 // with a "move to register" or "extload into register" instruction, then 775 // permute it into place, if the idx is a constant and if the idx is 776 // supported by the target. 777 MVT VT = Tmp1.getValueType(); 778 MVT EltVT = VT.getVectorElementType(); 779 MVT IdxVT = Tmp3.getValueType(); 780 MVT PtrVT = TLI.getPointerTy(); 781 SDOperand StackPtr = DAG.CreateStackTemporary(VT); 782 783 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val); 784 int SPFI = StackPtrFI->getIndex(); 785 786 // Store the vector. 787 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, 788 PseudoSourceValue::getFixedStack(), 789 SPFI); 790 791 // Truncate or zero extend offset to target pointer type. 792 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 793 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 794 // Add the offset to the index. 795 unsigned EltSize = EltVT.getSizeInBits()/8; 796 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 797 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 798 // Store the scalar value. 799 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, 800 PseudoSourceValue::getFixedStack(), SPFI, EltVT); 801 // Load the updated vector. 802 return DAG.getLoad(VT, Ch, StackPtr, PseudoSourceValue::getFixedStack(),SPFI); 803} 804 805/// LegalizeOp - We know that the specified value has a legal type, and 806/// that its operands are legal. Now ensure that the operation itself 807/// is legal, recursively ensuring that the operands' operations remain 808/// legal. 809SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 810 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 811 return Op; 812 813 assert(isTypeLegal(Op.getValueType()) && 814 "Caller should expand or promote operands that are not legal!"); 815 SDNode *Node = Op.Val; 816 817 // If this operation defines any values that cannot be represented in a 818 // register on this target, make sure to expand or promote them. 819 if (Node->getNumValues() > 1) { 820 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 821 if (getTypeAction(Node->getValueType(i)) != Legal) { 822 HandleOp(Op.getValue(i)); 823 assert(LegalizedNodes.count(Op) && 824 "Handling didn't add legal operands!"); 825 return LegalizedNodes[Op]; 826 } 827 } 828 829 // Note that LegalizeOp may be reentered even from single-use nodes, which 830 // means that we always must cache transformed nodes. 831 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 832 if (I != LegalizedNodes.end()) return I->second; 833 834 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 835 SDOperand Result = Op; 836 bool isCustom = false; 837 838 switch (Node->getOpcode()) { 839 case ISD::FrameIndex: 840 case ISD::EntryToken: 841 case ISD::Register: 842 case ISD::BasicBlock: 843 case ISD::TargetFrameIndex: 844 case ISD::TargetJumpTable: 845 case ISD::TargetConstant: 846 case ISD::TargetConstantFP: 847 case ISD::TargetConstantPool: 848 case ISD::TargetGlobalAddress: 849 case ISD::TargetGlobalTLSAddress: 850 case ISD::TargetExternalSymbol: 851 case ISD::VALUETYPE: 852 case ISD::SRCVALUE: 853 case ISD::MEMOPERAND: 854 case ISD::STRING: 855 case ISD::CONDCODE: 856 case ISD::ARG_FLAGS: 857 // Primitives must all be legal. 858 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 859 "This must be legal!"); 860 break; 861 default: 862 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 863 // If this is a target node, legalize it by legalizing the operands then 864 // passing it through. 865 SmallVector<SDOperand, 8> Ops; 866 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 867 Ops.push_back(LegalizeOp(Node->getOperand(i))); 868 869 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 870 871 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 872 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 873 return Result.getValue(Op.ResNo); 874 } 875 // Otherwise this is an unhandled builtin node. splat. 876#ifndef NDEBUG 877 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 878#endif 879 assert(0 && "Do not know how to legalize this operator!"); 880 abort(); 881 case ISD::GLOBAL_OFFSET_TABLE: 882 case ISD::GlobalAddress: 883 case ISD::GlobalTLSAddress: 884 case ISD::ExternalSymbol: 885 case ISD::ConstantPool: 886 case ISD::JumpTable: // Nothing to do. 887 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 888 default: assert(0 && "This action is not supported yet!"); 889 case TargetLowering::Custom: 890 Tmp1 = TLI.LowerOperation(Op, DAG); 891 if (Tmp1.Val) Result = Tmp1; 892 // FALLTHROUGH if the target doesn't want to lower this op after all. 893 case TargetLowering::Legal: 894 break; 895 } 896 break; 897 case ISD::FRAMEADDR: 898 case ISD::RETURNADDR: 899 // The only option for these nodes is to custom lower them. If the target 900 // does not custom lower them, then return zero. 901 Tmp1 = TLI.LowerOperation(Op, DAG); 902 if (Tmp1.Val) 903 Result = Tmp1; 904 else 905 Result = DAG.getConstant(0, TLI.getPointerTy()); 906 break; 907 case ISD::FRAME_TO_ARGS_OFFSET: { 908 MVT VT = Node->getValueType(0); 909 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 910 default: assert(0 && "This action is not supported yet!"); 911 case TargetLowering::Custom: 912 Result = TLI.LowerOperation(Op, DAG); 913 if (Result.Val) break; 914 // Fall Thru 915 case TargetLowering::Legal: 916 Result = DAG.getConstant(0, VT); 917 break; 918 } 919 } 920 break; 921 case ISD::EXCEPTIONADDR: { 922 Tmp1 = LegalizeOp(Node->getOperand(0)); 923 MVT VT = Node->getValueType(0); 924 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 925 default: assert(0 && "This action is not supported yet!"); 926 case TargetLowering::Expand: { 927 unsigned Reg = TLI.getExceptionAddressRegister(); 928 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 929 } 930 break; 931 case TargetLowering::Custom: 932 Result = TLI.LowerOperation(Op, DAG); 933 if (Result.Val) break; 934 // Fall Thru 935 case TargetLowering::Legal: { 936 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 937 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 938 Ops, 2); 939 break; 940 } 941 } 942 } 943 if (Result.Val->getNumValues() == 1) break; 944 945 assert(Result.Val->getNumValues() == 2 && 946 "Cannot return more than two values!"); 947 948 // Since we produced two values, make sure to remember that we 949 // legalized both of them. 950 Tmp1 = LegalizeOp(Result); 951 Tmp2 = LegalizeOp(Result.getValue(1)); 952 AddLegalizedOperand(Op.getValue(0), Tmp1); 953 AddLegalizedOperand(Op.getValue(1), Tmp2); 954 return Op.ResNo ? Tmp2 : Tmp1; 955 case ISD::EHSELECTION: { 956 Tmp1 = LegalizeOp(Node->getOperand(0)); 957 Tmp2 = LegalizeOp(Node->getOperand(1)); 958 MVT VT = Node->getValueType(0); 959 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 960 default: assert(0 && "This action is not supported yet!"); 961 case TargetLowering::Expand: { 962 unsigned Reg = TLI.getExceptionSelectorRegister(); 963 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 964 } 965 break; 966 case TargetLowering::Custom: 967 Result = TLI.LowerOperation(Op, DAG); 968 if (Result.Val) break; 969 // Fall Thru 970 case TargetLowering::Legal: { 971 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 972 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 973 Ops, 2); 974 break; 975 } 976 } 977 } 978 if (Result.Val->getNumValues() == 1) break; 979 980 assert(Result.Val->getNumValues() == 2 && 981 "Cannot return more than two values!"); 982 983 // Since we produced two values, make sure to remember that we 984 // legalized both of them. 985 Tmp1 = LegalizeOp(Result); 986 Tmp2 = LegalizeOp(Result.getValue(1)); 987 AddLegalizedOperand(Op.getValue(0), Tmp1); 988 AddLegalizedOperand(Op.getValue(1), Tmp2); 989 return Op.ResNo ? Tmp2 : Tmp1; 990 case ISD::EH_RETURN: { 991 MVT VT = Node->getValueType(0); 992 // The only "good" option for this node is to custom lower it. 993 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 994 default: assert(0 && "This action is not supported at all!"); 995 case TargetLowering::Custom: 996 Result = TLI.LowerOperation(Op, DAG); 997 if (Result.Val) break; 998 // Fall Thru 999 case TargetLowering::Legal: 1000 // Target does not know, how to lower this, lower to noop 1001 Result = LegalizeOp(Node->getOperand(0)); 1002 break; 1003 } 1004 } 1005 break; 1006 case ISD::AssertSext: 1007 case ISD::AssertZext: 1008 Tmp1 = LegalizeOp(Node->getOperand(0)); 1009 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1010 break; 1011 case ISD::MERGE_VALUES: 1012 // Legalize eliminates MERGE_VALUES nodes. 1013 Result = Node->getOperand(Op.ResNo); 1014 break; 1015 case ISD::CopyFromReg: 1016 Tmp1 = LegalizeOp(Node->getOperand(0)); 1017 Result = Op.getValue(0); 1018 if (Node->getNumValues() == 2) { 1019 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1020 } else { 1021 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 1022 if (Node->getNumOperands() == 3) { 1023 Tmp2 = LegalizeOp(Node->getOperand(2)); 1024 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1025 } else { 1026 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1027 } 1028 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 1029 } 1030 // Since CopyFromReg produces two values, make sure to remember that we 1031 // legalized both of them. 1032 AddLegalizedOperand(Op.getValue(0), Result); 1033 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1034 return Result.getValue(Op.ResNo); 1035 case ISD::UNDEF: { 1036 MVT VT = Op.getValueType(); 1037 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 1038 default: assert(0 && "This action is not supported yet!"); 1039 case TargetLowering::Expand: 1040 if (VT.isInteger()) 1041 Result = DAG.getConstant(0, VT); 1042 else if (VT.isFloatingPoint()) 1043 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), 1044 VT); 1045 else 1046 assert(0 && "Unknown value type!"); 1047 break; 1048 case TargetLowering::Legal: 1049 break; 1050 } 1051 break; 1052 } 1053 1054 case ISD::INTRINSIC_W_CHAIN: 1055 case ISD::INTRINSIC_WO_CHAIN: 1056 case ISD::INTRINSIC_VOID: { 1057 SmallVector<SDOperand, 8> Ops; 1058 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1059 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1060 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1061 1062 // Allow the target to custom lower its intrinsics if it wants to. 1063 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1064 TargetLowering::Custom) { 1065 Tmp3 = TLI.LowerOperation(Result, DAG); 1066 if (Tmp3.Val) Result = Tmp3; 1067 } 1068 1069 if (Result.Val->getNumValues() == 1) break; 1070 1071 // Must have return value and chain result. 1072 assert(Result.Val->getNumValues() == 2 && 1073 "Cannot return more than two values!"); 1074 1075 // Since loads produce two values, make sure to remember that we 1076 // legalized both of them. 1077 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1078 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1079 return Result.getValue(Op.ResNo); 1080 } 1081 1082 case ISD::LOCATION: 1083 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 1084 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1085 1086 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 1087 case TargetLowering::Promote: 1088 default: assert(0 && "This action is not supported yet!"); 1089 case TargetLowering::Expand: { 1090 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1091 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1092 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 1093 1094 if (MMI && (useDEBUG_LOC || useLABEL)) { 1095 const std::string &FName = 1096 cast<StringSDNode>(Node->getOperand(3))->getValue(); 1097 const std::string &DirName = 1098 cast<StringSDNode>(Node->getOperand(4))->getValue(); 1099 unsigned SrcFile = MMI->RecordSource(DirName, FName); 1100 1101 SmallVector<SDOperand, 8> Ops; 1102 Ops.push_back(Tmp1); // chain 1103 SDOperand LineOp = Node->getOperand(1); 1104 SDOperand ColOp = Node->getOperand(2); 1105 1106 if (useDEBUG_LOC) { 1107 Ops.push_back(LineOp); // line # 1108 Ops.push_back(ColOp); // col # 1109 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 1110 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 1111 } else { 1112 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 1113 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 1114 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); 1115 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 1116 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label 1117 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size()); 1118 } 1119 } else { 1120 Result = Tmp1; // chain 1121 } 1122 break; 1123 } 1124 case TargetLowering::Legal: 1125 if (Tmp1 != Node->getOperand(0) || 1126 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 1127 SmallVector<SDOperand, 8> Ops; 1128 Ops.push_back(Tmp1); 1129 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 1130 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1131 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1132 } else { 1133 // Otherwise promote them. 1134 Ops.push_back(PromoteOp(Node->getOperand(1))); 1135 Ops.push_back(PromoteOp(Node->getOperand(2))); 1136 } 1137 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1138 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1139 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1140 } 1141 break; 1142 } 1143 break; 1144 1145 case ISD::DECLARE: 1146 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1147 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1148 default: assert(0 && "This action is not supported yet!"); 1149 case TargetLowering::Legal: 1150 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1151 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1152 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1153 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1154 break; 1155 case TargetLowering::Expand: 1156 Result = LegalizeOp(Node->getOperand(0)); 1157 break; 1158 } 1159 break; 1160 1161 case ISD::DEBUG_LOC: 1162 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1163 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1164 default: assert(0 && "This action is not supported yet!"); 1165 case TargetLowering::Legal: 1166 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1167 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1168 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1169 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1170 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1171 break; 1172 } 1173 break; 1174 1175 case ISD::LABEL: 1176 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!"); 1177 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 1178 default: assert(0 && "This action is not supported yet!"); 1179 case TargetLowering::Legal: 1180 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1181 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 1182 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand. 1183 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1184 break; 1185 case TargetLowering::Expand: 1186 Result = LegalizeOp(Node->getOperand(0)); 1187 break; 1188 } 1189 break; 1190 1191 case ISD::PREFETCH: 1192 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1193 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1194 default: assert(0 && "This action is not supported yet!"); 1195 case TargetLowering::Legal: 1196 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1197 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1198 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1199 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1200 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1201 break; 1202 case TargetLowering::Expand: 1203 // It's a noop. 1204 Result = LegalizeOp(Node->getOperand(0)); 1205 break; 1206 } 1207 break; 1208 1209 case ISD::MEMBARRIER: { 1210 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1211 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1212 default: assert(0 && "This action is not supported yet!"); 1213 case TargetLowering::Legal: { 1214 SDOperand Ops[6]; 1215 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1216 for (int x = 1; x < 6; ++x) { 1217 Ops[x] = Node->getOperand(x); 1218 if (!isTypeLegal(Ops[x].getValueType())) 1219 Ops[x] = PromoteOp(Ops[x]); 1220 } 1221 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1222 break; 1223 } 1224 case TargetLowering::Expand: 1225 //There is no libgcc call for this op 1226 Result = Node->getOperand(0); // Noop 1227 break; 1228 } 1229 break; 1230 } 1231 1232 case ISD::ATOMIC_LCS: { 1233 unsigned int num_operands = 4; 1234 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1235 SDOperand Ops[4]; 1236 for (unsigned int x = 0; x < num_operands; ++x) 1237 Ops[x] = LegalizeOp(Node->getOperand(x)); 1238 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1239 1240 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1241 default: assert(0 && "This action is not supported yet!"); 1242 case TargetLowering::Custom: 1243 Result = TLI.LowerOperation(Result, DAG); 1244 break; 1245 case TargetLowering::Legal: 1246 break; 1247 } 1248 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1249 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1250 return Result.getValue(Op.ResNo); 1251 } 1252 case ISD::ATOMIC_LAS: 1253 case ISD::ATOMIC_LSS: 1254 case ISD::ATOMIC_LOAD_AND: 1255 case ISD::ATOMIC_LOAD_OR: 1256 case ISD::ATOMIC_LOAD_XOR: 1257 case ISD::ATOMIC_LOAD_MIN: 1258 case ISD::ATOMIC_LOAD_MAX: 1259 case ISD::ATOMIC_LOAD_UMIN: 1260 case ISD::ATOMIC_LOAD_UMAX: 1261 case ISD::ATOMIC_SWAP: { 1262 unsigned int num_operands = 3; 1263 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1264 SDOperand Ops[3]; 1265 for (unsigned int x = 0; x < num_operands; ++x) 1266 Ops[x] = LegalizeOp(Node->getOperand(x)); 1267 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1268 1269 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1270 default: assert(0 && "This action is not supported yet!"); 1271 case TargetLowering::Custom: 1272 Result = TLI.LowerOperation(Result, DAG); 1273 break; 1274 case TargetLowering::Expand: 1275 Result = SDOperand(TLI.ExpandOperationResult(Op.Val, DAG),0); 1276 break; 1277 case TargetLowering::Legal: 1278 break; 1279 } 1280 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1281 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1282 return Result.getValue(Op.ResNo); 1283 } 1284 case ISD::Constant: { 1285 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1286 unsigned opAction = 1287 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1288 1289 // We know we don't need to expand constants here, constants only have one 1290 // value and we check that it is fine above. 1291 1292 if (opAction == TargetLowering::Custom) { 1293 Tmp1 = TLI.LowerOperation(Result, DAG); 1294 if (Tmp1.Val) 1295 Result = Tmp1; 1296 } 1297 break; 1298 } 1299 case ISD::ConstantFP: { 1300 // Spill FP immediates to the constant pool if the target cannot directly 1301 // codegen them. Targets often have some immediate values that can be 1302 // efficiently generated into an FP register without a load. We explicitly 1303 // leave these constants as ConstantFP nodes for the target to deal with. 1304 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1305 1306 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1307 default: assert(0 && "This action is not supported yet!"); 1308 case TargetLowering::Legal: 1309 break; 1310 case TargetLowering::Custom: 1311 Tmp3 = TLI.LowerOperation(Result, DAG); 1312 if (Tmp3.Val) { 1313 Result = Tmp3; 1314 break; 1315 } 1316 // FALLTHROUGH 1317 case TargetLowering::Expand: { 1318 // Check to see if this FP immediate is already legal. 1319 bool isLegal = false; 1320 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1321 E = TLI.legal_fpimm_end(); I != E; ++I) { 1322 if (CFP->isExactlyValue(*I)) { 1323 isLegal = true; 1324 break; 1325 } 1326 } 1327 // If this is a legal constant, turn it into a TargetConstantFP node. 1328 if (isLegal) 1329 break; 1330 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1331 } 1332 } 1333 break; 1334 } 1335 case ISD::TokenFactor: 1336 if (Node->getNumOperands() == 2) { 1337 Tmp1 = LegalizeOp(Node->getOperand(0)); 1338 Tmp2 = LegalizeOp(Node->getOperand(1)); 1339 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1340 } else if (Node->getNumOperands() == 3) { 1341 Tmp1 = LegalizeOp(Node->getOperand(0)); 1342 Tmp2 = LegalizeOp(Node->getOperand(1)); 1343 Tmp3 = LegalizeOp(Node->getOperand(2)); 1344 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1345 } else { 1346 SmallVector<SDOperand, 8> Ops; 1347 // Legalize the operands. 1348 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1349 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1350 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1351 } 1352 break; 1353 1354 case ISD::FORMAL_ARGUMENTS: 1355 case ISD::CALL: 1356 // The only option for this is to custom lower it. 1357 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1358 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1359 // A call within a calling sequence must be legalized to something 1360 // other than the normal CALLSEQ_END. Violating this gets Legalize 1361 // into an infinite loop. 1362 assert ((!IsLegalizingCall || 1363 Node->getOpcode() != ISD::CALL || 1364 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) && 1365 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1366 1367 // The number of incoming and outgoing values should match; unless the final 1368 // outgoing value is a flag. 1369 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || 1370 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && 1371 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == 1372 MVT::Flag)) && 1373 "Lowering call/formal_arguments produced unexpected # results!"); 1374 1375 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1376 // remember that we legalized all of them, so it doesn't get relegalized. 1377 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1378 if (Tmp3.Val->getValueType(i) == MVT::Flag) 1379 continue; 1380 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1381 if (Op.ResNo == i) 1382 Tmp2 = Tmp1; 1383 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1384 } 1385 return Tmp2; 1386 case ISD::EXTRACT_SUBREG: { 1387 Tmp1 = LegalizeOp(Node->getOperand(0)); 1388 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1389 assert(idx && "Operand must be a constant"); 1390 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1391 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1392 } 1393 break; 1394 case ISD::INSERT_SUBREG: { 1395 Tmp1 = LegalizeOp(Node->getOperand(0)); 1396 Tmp2 = LegalizeOp(Node->getOperand(1)); 1397 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1398 assert(idx && "Operand must be a constant"); 1399 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1400 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1401 } 1402 break; 1403 case ISD::BUILD_VECTOR: 1404 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1405 default: assert(0 && "This action is not supported yet!"); 1406 case TargetLowering::Custom: 1407 Tmp3 = TLI.LowerOperation(Result, DAG); 1408 if (Tmp3.Val) { 1409 Result = Tmp3; 1410 break; 1411 } 1412 // FALLTHROUGH 1413 case TargetLowering::Expand: 1414 Result = ExpandBUILD_VECTOR(Result.Val); 1415 break; 1416 } 1417 break; 1418 case ISD::INSERT_VECTOR_ELT: 1419 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1420 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1421 1422 // The type of the value to insert may not be legal, even though the vector 1423 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1424 // here. 1425 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1426 default: assert(0 && "Cannot expand insert element operand"); 1427 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1428 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1429 } 1430 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1431 1432 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1433 Node->getValueType(0))) { 1434 default: assert(0 && "This action is not supported yet!"); 1435 case TargetLowering::Legal: 1436 break; 1437 case TargetLowering::Custom: 1438 Tmp4 = TLI.LowerOperation(Result, DAG); 1439 if (Tmp4.Val) { 1440 Result = Tmp4; 1441 break; 1442 } 1443 // FALLTHROUGH 1444 case TargetLowering::Expand: { 1445 // If the insert index is a constant, codegen this as a scalar_to_vector, 1446 // then a shuffle that inserts it into the right position in the vector. 1447 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1448 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1449 // match the element type of the vector being created. 1450 if (Tmp2.getValueType() == 1451 Op.getValueType().getVectorElementType()) { 1452 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1453 Tmp1.getValueType(), Tmp2); 1454 1455 unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); 1456 MVT ShufMaskVT = 1457 MVT::getIntVectorWithNumElements(NumElts); 1458 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType(); 1459 1460 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1461 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1462 // elt 0 of the RHS. 1463 SmallVector<SDOperand, 8> ShufOps; 1464 for (unsigned i = 0; i != NumElts; ++i) { 1465 if (i != InsertPos->getValue()) 1466 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1467 else 1468 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1469 } 1470 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1471 &ShufOps[0], ShufOps.size()); 1472 1473 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1474 Tmp1, ScVec, ShufMask); 1475 Result = LegalizeOp(Result); 1476 break; 1477 } 1478 } 1479 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3); 1480 break; 1481 } 1482 } 1483 break; 1484 case ISD::SCALAR_TO_VECTOR: 1485 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1486 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1487 break; 1488 } 1489 1490 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1491 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1492 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1493 Node->getValueType(0))) { 1494 default: assert(0 && "This action is not supported yet!"); 1495 case TargetLowering::Legal: 1496 break; 1497 case TargetLowering::Custom: 1498 Tmp3 = TLI.LowerOperation(Result, DAG); 1499 if (Tmp3.Val) { 1500 Result = Tmp3; 1501 break; 1502 } 1503 // FALLTHROUGH 1504 case TargetLowering::Expand: 1505 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1506 break; 1507 } 1508 break; 1509 case ISD::VECTOR_SHUFFLE: 1510 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1511 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1512 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1513 1514 // Allow targets to custom lower the SHUFFLEs they support. 1515 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1516 default: assert(0 && "Unknown operation action!"); 1517 case TargetLowering::Legal: 1518 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1519 "vector shuffle should not be created if not legal!"); 1520 break; 1521 case TargetLowering::Custom: 1522 Tmp3 = TLI.LowerOperation(Result, DAG); 1523 if (Tmp3.Val) { 1524 Result = Tmp3; 1525 break; 1526 } 1527 // FALLTHROUGH 1528 case TargetLowering::Expand: { 1529 MVT VT = Node->getValueType(0); 1530 MVT EltVT = VT.getVectorElementType(); 1531 MVT PtrVT = TLI.getPointerTy(); 1532 SDOperand Mask = Node->getOperand(2); 1533 unsigned NumElems = Mask.getNumOperands(); 1534 SmallVector<SDOperand,8> Ops; 1535 for (unsigned i = 0; i != NumElems; ++i) { 1536 SDOperand Arg = Mask.getOperand(i); 1537 if (Arg.getOpcode() == ISD::UNDEF) { 1538 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1539 } else { 1540 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1541 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1542 if (Idx < NumElems) 1543 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1544 DAG.getConstant(Idx, PtrVT))); 1545 else 1546 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1547 DAG.getConstant(Idx - NumElems, PtrVT))); 1548 } 1549 } 1550 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1551 break; 1552 } 1553 case TargetLowering::Promote: { 1554 // Change base type to a different vector type. 1555 MVT OVT = Node->getValueType(0); 1556 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1557 1558 // Cast the two input vectors. 1559 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1560 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1561 1562 // Convert the shuffle mask to the right # elements. 1563 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1564 assert(Tmp3.Val && "Shuffle not legal?"); 1565 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1566 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1567 break; 1568 } 1569 } 1570 break; 1571 1572 case ISD::EXTRACT_VECTOR_ELT: 1573 Tmp1 = Node->getOperand(0); 1574 Tmp2 = LegalizeOp(Node->getOperand(1)); 1575 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1576 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1577 break; 1578 1579 case ISD::EXTRACT_SUBVECTOR: 1580 Tmp1 = Node->getOperand(0); 1581 Tmp2 = LegalizeOp(Node->getOperand(1)); 1582 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1583 Result = ExpandEXTRACT_SUBVECTOR(Result); 1584 break; 1585 1586 case ISD::CALLSEQ_START: { 1587 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1588 1589 // Recursively Legalize all of the inputs of the call end that do not lead 1590 // to this call start. This ensures that any libcalls that need be inserted 1591 // are inserted *before* the CALLSEQ_START. 1592 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1593 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1594 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1595 NodesLeadingTo); 1596 } 1597 1598 // Now that we legalized all of the inputs (which may have inserted 1599 // libcalls) create the new CALLSEQ_START node. 1600 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1601 1602 // Merge in the last call, to ensure that this call start after the last 1603 // call ended. 1604 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1605 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1606 Tmp1 = LegalizeOp(Tmp1); 1607 } 1608 1609 // Do not try to legalize the target-specific arguments (#1+). 1610 if (Tmp1 != Node->getOperand(0)) { 1611 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1612 Ops[0] = Tmp1; 1613 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1614 } 1615 1616 // Remember that the CALLSEQ_START is legalized. 1617 AddLegalizedOperand(Op.getValue(0), Result); 1618 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1619 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1620 1621 // Now that the callseq_start and all of the non-call nodes above this call 1622 // sequence have been legalized, legalize the call itself. During this 1623 // process, no libcalls can/will be inserted, guaranteeing that no calls 1624 // can overlap. 1625 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1626 // Note that we are selecting this call! 1627 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1628 IsLegalizingCall = true; 1629 1630 // Legalize the call, starting from the CALLSEQ_END. 1631 LegalizeOp(LastCALLSEQ_END); 1632 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1633 return Result; 1634 } 1635 case ISD::CALLSEQ_END: 1636 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1637 // will cause this node to be legalized as well as handling libcalls right. 1638 if (LastCALLSEQ_END.Val != Node) { 1639 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1640 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1641 assert(I != LegalizedNodes.end() && 1642 "Legalizing the call start should have legalized this node!"); 1643 return I->second; 1644 } 1645 1646 // Otherwise, the call start has been legalized and everything is going 1647 // according to plan. Just legalize ourselves normally here. 1648 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1649 // Do not try to legalize the target-specific arguments (#1+), except for 1650 // an optional flag input. 1651 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1652 if (Tmp1 != Node->getOperand(0)) { 1653 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1654 Ops[0] = Tmp1; 1655 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1656 } 1657 } else { 1658 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1659 if (Tmp1 != Node->getOperand(0) || 1660 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1661 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1662 Ops[0] = Tmp1; 1663 Ops.back() = Tmp2; 1664 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1665 } 1666 } 1667 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1668 // This finishes up call legalization. 1669 IsLegalizingCall = false; 1670 1671 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1672 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1673 if (Node->getNumValues() == 2) 1674 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1675 return Result.getValue(Op.ResNo); 1676 case ISD::DYNAMIC_STACKALLOC: { 1677 MVT VT = Node->getValueType(0); 1678 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1679 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1680 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1681 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1682 1683 Tmp1 = Result.getValue(0); 1684 Tmp2 = Result.getValue(1); 1685 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1686 default: assert(0 && "This action is not supported yet!"); 1687 case TargetLowering::Expand: { 1688 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1689 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1690 " not tell us which reg is the stack pointer!"); 1691 SDOperand Chain = Tmp1.getOperand(0); 1692 1693 // Chain the dynamic stack allocation so that it doesn't modify the stack 1694 // pointer when other instructions are using the stack. 1695 Chain = DAG.getCALLSEQ_START(Chain, 1696 DAG.getConstant(0, TLI.getPointerTy())); 1697 1698 SDOperand Size = Tmp2.getOperand(1); 1699 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1700 Chain = SP.getValue(1); 1701 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1702 unsigned StackAlign = 1703 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1704 if (Align > StackAlign) 1705 SP = DAG.getNode(ISD::AND, VT, SP, 1706 DAG.getConstant(-(uint64_t)Align, VT)); 1707 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1708 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1709 1710 Tmp2 = 1711 DAG.getCALLSEQ_END(Chain, 1712 DAG.getConstant(0, TLI.getPointerTy()), 1713 DAG.getConstant(0, TLI.getPointerTy()), 1714 SDOperand()); 1715 1716 Tmp1 = LegalizeOp(Tmp1); 1717 Tmp2 = LegalizeOp(Tmp2); 1718 break; 1719 } 1720 case TargetLowering::Custom: 1721 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1722 if (Tmp3.Val) { 1723 Tmp1 = LegalizeOp(Tmp3); 1724 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1725 } 1726 break; 1727 case TargetLowering::Legal: 1728 break; 1729 } 1730 // Since this op produce two values, make sure to remember that we 1731 // legalized both of them. 1732 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1733 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1734 return Op.ResNo ? Tmp2 : Tmp1; 1735 } 1736 case ISD::INLINEASM: { 1737 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1738 bool Changed = false; 1739 // Legalize all of the operands of the inline asm, in case they are nodes 1740 // that need to be expanded or something. Note we skip the asm string and 1741 // all of the TargetConstant flags. 1742 SDOperand Op = LegalizeOp(Ops[0]); 1743 Changed = Op != Ops[0]; 1744 Ops[0] = Op; 1745 1746 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1747 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1748 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1749 for (++i; NumVals; ++i, --NumVals) { 1750 SDOperand Op = LegalizeOp(Ops[i]); 1751 if (Op != Ops[i]) { 1752 Changed = true; 1753 Ops[i] = Op; 1754 } 1755 } 1756 } 1757 1758 if (HasInFlag) { 1759 Op = LegalizeOp(Ops.back()); 1760 Changed |= Op != Ops.back(); 1761 Ops.back() = Op; 1762 } 1763 1764 if (Changed) 1765 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1766 1767 // INLINE asm returns a chain and flag, make sure to add both to the map. 1768 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1769 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1770 return Result.getValue(Op.ResNo); 1771 } 1772 case ISD::BR: 1773 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1774 // Ensure that libcalls are emitted before a branch. 1775 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1776 Tmp1 = LegalizeOp(Tmp1); 1777 LastCALLSEQ_END = DAG.getEntryNode(); 1778 1779 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1780 break; 1781 case ISD::BRIND: 1782 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1783 // Ensure that libcalls are emitted before a branch. 1784 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1785 Tmp1 = LegalizeOp(Tmp1); 1786 LastCALLSEQ_END = DAG.getEntryNode(); 1787 1788 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1789 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1790 case Legal: 1791 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1792 break; 1793 } 1794 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1795 break; 1796 case ISD::BR_JT: 1797 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1798 // Ensure that libcalls are emitted before a branch. 1799 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1800 Tmp1 = LegalizeOp(Tmp1); 1801 LastCALLSEQ_END = DAG.getEntryNode(); 1802 1803 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1804 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1805 1806 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1807 default: assert(0 && "This action is not supported yet!"); 1808 case TargetLowering::Legal: break; 1809 case TargetLowering::Custom: 1810 Tmp1 = TLI.LowerOperation(Result, DAG); 1811 if (Tmp1.Val) Result = Tmp1; 1812 break; 1813 case TargetLowering::Expand: { 1814 SDOperand Chain = Result.getOperand(0); 1815 SDOperand Table = Result.getOperand(1); 1816 SDOperand Index = Result.getOperand(2); 1817 1818 MVT PTy = TLI.getPointerTy(); 1819 MachineFunction &MF = DAG.getMachineFunction(); 1820 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1821 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1822 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1823 1824 SDOperand LD; 1825 switch (EntrySize) { 1826 default: assert(0 && "Size of jump table not supported yet."); break; 1827 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, 1828 PseudoSourceValue::getJumpTable(), 0); break; 1829 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, 1830 PseudoSourceValue::getJumpTable(), 0); break; 1831 } 1832 1833 Addr = LD; 1834 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1835 // For PIC, the sequence is: 1836 // BRIND(load(Jumptable + index) + RelocBase) 1837 // RelocBase can be JumpTable, GOT or some sort of global base. 1838 if (PTy != MVT::i32) 1839 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1840 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1841 TLI.getPICJumpTableRelocBase(Table, DAG)); 1842 } 1843 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1844 } 1845 } 1846 break; 1847 case ISD::BRCOND: 1848 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1849 // Ensure that libcalls are emitted before a return. 1850 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1851 Tmp1 = LegalizeOp(Tmp1); 1852 LastCALLSEQ_END = DAG.getEntryNode(); 1853 1854 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1855 case Expand: assert(0 && "It's impossible to expand bools"); 1856 case Legal: 1857 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1858 break; 1859 case Promote: { 1860 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1861 1862 // The top bits of the promoted condition are not necessarily zero, ensure 1863 // that the value is properly zero extended. 1864 unsigned BitWidth = Tmp2.getValueSizeInBits(); 1865 if (!DAG.MaskedValueIsZero(Tmp2, 1866 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 1867 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1868 break; 1869 } 1870 } 1871 1872 // Basic block destination (Op#2) is always legal. 1873 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1874 1875 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1876 default: assert(0 && "This action is not supported yet!"); 1877 case TargetLowering::Legal: break; 1878 case TargetLowering::Custom: 1879 Tmp1 = TLI.LowerOperation(Result, DAG); 1880 if (Tmp1.Val) Result = Tmp1; 1881 break; 1882 case TargetLowering::Expand: 1883 // Expand brcond's setcc into its constituent parts and create a BR_CC 1884 // Node. 1885 if (Tmp2.getOpcode() == ISD::SETCC) { 1886 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1887 Tmp2.getOperand(0), Tmp2.getOperand(1), 1888 Node->getOperand(2)); 1889 } else { 1890 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1891 DAG.getCondCode(ISD::SETNE), Tmp2, 1892 DAG.getConstant(0, Tmp2.getValueType()), 1893 Node->getOperand(2)); 1894 } 1895 break; 1896 } 1897 break; 1898 case ISD::BR_CC: 1899 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1900 // Ensure that libcalls are emitted before a branch. 1901 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1902 Tmp1 = LegalizeOp(Tmp1); 1903 Tmp2 = Node->getOperand(2); // LHS 1904 Tmp3 = Node->getOperand(3); // RHS 1905 Tmp4 = Node->getOperand(1); // CC 1906 1907 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1908 LastCALLSEQ_END = DAG.getEntryNode(); 1909 1910 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1911 // the LHS is a legal SETCC itself. In this case, we need to compare 1912 // the result against zero to select between true and false values. 1913 if (Tmp3.Val == 0) { 1914 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1915 Tmp4 = DAG.getCondCode(ISD::SETNE); 1916 } 1917 1918 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1919 Node->getOperand(4)); 1920 1921 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1922 default: assert(0 && "Unexpected action for BR_CC!"); 1923 case TargetLowering::Legal: break; 1924 case TargetLowering::Custom: 1925 Tmp4 = TLI.LowerOperation(Result, DAG); 1926 if (Tmp4.Val) Result = Tmp4; 1927 break; 1928 } 1929 break; 1930 case ISD::LOAD: { 1931 LoadSDNode *LD = cast<LoadSDNode>(Node); 1932 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1933 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1934 1935 ISD::LoadExtType ExtType = LD->getExtensionType(); 1936 if (ExtType == ISD::NON_EXTLOAD) { 1937 MVT VT = Node->getValueType(0); 1938 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1939 Tmp3 = Result.getValue(0); 1940 Tmp4 = Result.getValue(1); 1941 1942 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1943 default: assert(0 && "This action is not supported yet!"); 1944 case TargetLowering::Legal: 1945 // If this is an unaligned load and the target doesn't support it, 1946 // expand it. 1947 if (!TLI.allowsUnalignedMemoryAccesses()) { 1948 unsigned ABIAlignment = TLI.getTargetData()-> 1949 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 1950 if (LD->getAlignment() < ABIAlignment){ 1951 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1952 TLI); 1953 Tmp3 = Result.getOperand(0); 1954 Tmp4 = Result.getOperand(1); 1955 Tmp3 = LegalizeOp(Tmp3); 1956 Tmp4 = LegalizeOp(Tmp4); 1957 } 1958 } 1959 break; 1960 case TargetLowering::Custom: 1961 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1962 if (Tmp1.Val) { 1963 Tmp3 = LegalizeOp(Tmp1); 1964 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1965 } 1966 break; 1967 case TargetLowering::Promote: { 1968 // Only promote a load of vector type to another. 1969 assert(VT.isVector() && "Cannot promote this load!"); 1970 // Change base type to a different vector type. 1971 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1972 1973 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1974 LD->getSrcValueOffset(), 1975 LD->isVolatile(), LD->getAlignment()); 1976 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1977 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1978 break; 1979 } 1980 } 1981 // Since loads produce two values, make sure to remember that we 1982 // legalized both of them. 1983 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1984 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1985 return Op.ResNo ? Tmp4 : Tmp3; 1986 } else { 1987 MVT SrcVT = LD->getMemoryVT(); 1988 unsigned SrcWidth = SrcVT.getSizeInBits(); 1989 int SVOffset = LD->getSrcValueOffset(); 1990 unsigned Alignment = LD->getAlignment(); 1991 bool isVolatile = LD->isVolatile(); 1992 1993 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1994 // Some targets pretend to have an i1 loading operation, and actually 1995 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1996 // bits are guaranteed to be zero; it helps the optimizers understand 1997 // that these bits are zero. It is also useful for EXTLOAD, since it 1998 // tells the optimizers that those bits are undefined. It would be 1999 // nice to have an effective generic way of getting these benefits... 2000 // Until such a way is found, don't insist on promoting i1 here. 2001 (SrcVT != MVT::i1 || 2002 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 2003 // Promote to a byte-sized load if not loading an integral number of 2004 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 2005 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 2006 MVT NVT = MVT::getIntegerVT(NewWidth); 2007 SDOperand Ch; 2008 2009 // The extra bits are guaranteed to be zero, since we stored them that 2010 // way. A zext load from NVT thus automatically gives zext from SrcVT. 2011 2012 ISD::LoadExtType NewExtType = 2013 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 2014 2015 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), 2016 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 2017 NVT, isVolatile, Alignment); 2018 2019 Ch = Result.getValue(1); // The chain. 2020 2021 if (ExtType == ISD::SEXTLOAD) 2022 // Having the top bits zero doesn't help when sign extending. 2023 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2024 Result, DAG.getValueType(SrcVT)); 2025 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 2026 // All the top bits are guaranteed to be zero - inform the optimizers. 2027 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, 2028 DAG.getValueType(SrcVT)); 2029 2030 Tmp1 = LegalizeOp(Result); 2031 Tmp2 = LegalizeOp(Ch); 2032 } else if (SrcWidth & (SrcWidth - 1)) { 2033 // If not loading a power-of-2 number of bits, expand as two loads. 2034 assert(SrcVT.isExtended() && !SrcVT.isVector() && 2035 "Unsupported extload!"); 2036 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 2037 assert(RoundWidth < SrcWidth); 2038 unsigned ExtraWidth = SrcWidth - RoundWidth; 2039 assert(ExtraWidth < RoundWidth); 2040 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2041 "Load size not an integral number of bytes!"); 2042 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2043 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2044 SDOperand Lo, Hi, Ch; 2045 unsigned IncrementSize; 2046 2047 if (TLI.isLittleEndian()) { 2048 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2049 // Load the bottom RoundWidth bits. 2050 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2051 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2052 Alignment); 2053 2054 // Load the remaining ExtraWidth bits. 2055 IncrementSize = RoundWidth / 8; 2056 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2057 DAG.getIntPtrConstant(IncrementSize)); 2058 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2059 LD->getSrcValue(), SVOffset + IncrementSize, 2060 ExtraVT, isVolatile, 2061 MinAlign(Alignment, IncrementSize)); 2062 2063 // Build a factor node to remember that this load is independent of the 2064 // other one. 2065 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2066 Hi.getValue(1)); 2067 2068 // Move the top bits to the right place. 2069 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2070 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2071 2072 // Join the hi and lo parts. 2073 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2074 } else { 2075 // Big endian - avoid unaligned loads. 2076 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2077 // Load the top RoundWidth bits. 2078 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2079 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2080 Alignment); 2081 2082 // Load the remaining ExtraWidth bits. 2083 IncrementSize = RoundWidth / 8; 2084 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2085 DAG.getIntPtrConstant(IncrementSize)); 2086 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2087 LD->getSrcValue(), SVOffset + IncrementSize, 2088 ExtraVT, isVolatile, 2089 MinAlign(Alignment, IncrementSize)); 2090 2091 // Build a factor node to remember that this load is independent of the 2092 // other one. 2093 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2094 Hi.getValue(1)); 2095 2096 // Move the top bits to the right place. 2097 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2098 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2099 2100 // Join the hi and lo parts. 2101 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2102 } 2103 2104 Tmp1 = LegalizeOp(Result); 2105 Tmp2 = LegalizeOp(Ch); 2106 } else { 2107 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 2108 default: assert(0 && "This action is not supported yet!"); 2109 case TargetLowering::Custom: 2110 isCustom = true; 2111 // FALLTHROUGH 2112 case TargetLowering::Legal: 2113 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2114 Tmp1 = Result.getValue(0); 2115 Tmp2 = Result.getValue(1); 2116 2117 if (isCustom) { 2118 Tmp3 = TLI.LowerOperation(Result, DAG); 2119 if (Tmp3.Val) { 2120 Tmp1 = LegalizeOp(Tmp3); 2121 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2122 } 2123 } else { 2124 // If this is an unaligned load and the target doesn't support it, 2125 // expand it. 2126 if (!TLI.allowsUnalignedMemoryAccesses()) { 2127 unsigned ABIAlignment = TLI.getTargetData()-> 2128 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2129 if (LD->getAlignment() < ABIAlignment){ 2130 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 2131 TLI); 2132 Tmp1 = Result.getOperand(0); 2133 Tmp2 = Result.getOperand(1); 2134 Tmp1 = LegalizeOp(Tmp1); 2135 Tmp2 = LegalizeOp(Tmp2); 2136 } 2137 } 2138 } 2139 break; 2140 case TargetLowering::Expand: 2141 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2142 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2143 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 2144 LD->getSrcValueOffset(), 2145 LD->isVolatile(), LD->getAlignment()); 2146 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 2147 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2148 Tmp2 = LegalizeOp(Load.getValue(1)); 2149 break; 2150 } 2151 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2152 // Turn the unsupported load into an EXTLOAD followed by an explicit 2153 // zero/sign extend inreg. 2154 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2155 Tmp1, Tmp2, LD->getSrcValue(), 2156 LD->getSrcValueOffset(), SrcVT, 2157 LD->isVolatile(), LD->getAlignment()); 2158 SDOperand ValRes; 2159 if (ExtType == ISD::SEXTLOAD) 2160 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2161 Result, DAG.getValueType(SrcVT)); 2162 else 2163 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 2164 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2165 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2166 break; 2167 } 2168 } 2169 2170 // Since loads produce two values, make sure to remember that we legalized 2171 // both of them. 2172 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2173 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2174 return Op.ResNo ? Tmp2 : Tmp1; 2175 } 2176 } 2177 case ISD::EXTRACT_ELEMENT: { 2178 MVT OpTy = Node->getOperand(0).getValueType(); 2179 switch (getTypeAction(OpTy)) { 2180 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2181 case Legal: 2182 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 2183 // 1 -> Hi 2184 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 2185 DAG.getConstant(OpTy.getSizeInBits()/2, 2186 TLI.getShiftAmountTy())); 2187 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 2188 } else { 2189 // 0 -> Lo 2190 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 2191 Node->getOperand(0)); 2192 } 2193 break; 2194 case Expand: 2195 // Get both the low and high parts. 2196 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2197 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 2198 Result = Tmp2; // 1 -> Hi 2199 else 2200 Result = Tmp1; // 0 -> Lo 2201 break; 2202 } 2203 break; 2204 } 2205 2206 case ISD::CopyToReg: 2207 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2208 2209 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2210 "Register type must be legal!"); 2211 // Legalize the incoming value (must be a legal type). 2212 Tmp2 = LegalizeOp(Node->getOperand(2)); 2213 if (Node->getNumValues() == 1) { 2214 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2215 } else { 2216 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2217 if (Node->getNumOperands() == 4) { 2218 Tmp3 = LegalizeOp(Node->getOperand(3)); 2219 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2220 Tmp3); 2221 } else { 2222 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2223 } 2224 2225 // Since this produces two values, make sure to remember that we legalized 2226 // both of them. 2227 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2228 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2229 return Result; 2230 } 2231 break; 2232 2233 case ISD::RET: 2234 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2235 2236 // Ensure that libcalls are emitted before a return. 2237 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2238 Tmp1 = LegalizeOp(Tmp1); 2239 LastCALLSEQ_END = DAG.getEntryNode(); 2240 2241 switch (Node->getNumOperands()) { 2242 case 3: // ret val 2243 Tmp2 = Node->getOperand(1); 2244 Tmp3 = Node->getOperand(2); // Signness 2245 switch (getTypeAction(Tmp2.getValueType())) { 2246 case Legal: 2247 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2248 break; 2249 case Expand: 2250 if (!Tmp2.getValueType().isVector()) { 2251 SDOperand Lo, Hi; 2252 ExpandOp(Tmp2, Lo, Hi); 2253 2254 // Big endian systems want the hi reg first. 2255 if (TLI.isBigEndian()) 2256 std::swap(Lo, Hi); 2257 2258 if (Hi.Val) 2259 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2260 else 2261 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 2262 Result = LegalizeOp(Result); 2263 } else { 2264 SDNode *InVal = Tmp2.Val; 2265 int InIx = Tmp2.ResNo; 2266 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 2267 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 2268 2269 // Figure out if there is a simple type corresponding to this Vector 2270 // type. If so, convert to the vector type. 2271 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2272 if (TLI.isTypeLegal(TVT)) { 2273 // Turn this into a return of the vector type. 2274 Tmp2 = LegalizeOp(Tmp2); 2275 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2276 } else if (NumElems == 1) { 2277 // Turn this into a return of the scalar type. 2278 Tmp2 = ScalarizeVectorOp(Tmp2); 2279 Tmp2 = LegalizeOp(Tmp2); 2280 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2281 2282 // FIXME: Returns of gcc generic vectors smaller than a legal type 2283 // should be returned in integer registers! 2284 2285 // The scalarized value type may not be legal, e.g. it might require 2286 // promotion or expansion. Relegalize the return. 2287 Result = LegalizeOp(Result); 2288 } else { 2289 // FIXME: Returns of gcc generic vectors larger than a legal vector 2290 // type should be returned by reference! 2291 SDOperand Lo, Hi; 2292 SplitVectorOp(Tmp2, Lo, Hi); 2293 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2294 Result = LegalizeOp(Result); 2295 } 2296 } 2297 break; 2298 case Promote: 2299 Tmp2 = PromoteOp(Node->getOperand(1)); 2300 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2301 Result = LegalizeOp(Result); 2302 break; 2303 } 2304 break; 2305 case 1: // ret void 2306 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2307 break; 2308 default: { // ret <values> 2309 SmallVector<SDOperand, 8> NewValues; 2310 NewValues.push_back(Tmp1); 2311 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2312 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2313 case Legal: 2314 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2315 NewValues.push_back(Node->getOperand(i+1)); 2316 break; 2317 case Expand: { 2318 SDOperand Lo, Hi; 2319 assert(!Node->getOperand(i).getValueType().isExtended() && 2320 "FIXME: TODO: implement returning non-legal vector types!"); 2321 ExpandOp(Node->getOperand(i), Lo, Hi); 2322 NewValues.push_back(Lo); 2323 NewValues.push_back(Node->getOperand(i+1)); 2324 if (Hi.Val) { 2325 NewValues.push_back(Hi); 2326 NewValues.push_back(Node->getOperand(i+1)); 2327 } 2328 break; 2329 } 2330 case Promote: 2331 assert(0 && "Can't promote multiple return value yet!"); 2332 } 2333 2334 if (NewValues.size() == Node->getNumOperands()) 2335 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2336 else 2337 Result = DAG.getNode(ISD::RET, MVT::Other, 2338 &NewValues[0], NewValues.size()); 2339 break; 2340 } 2341 } 2342 2343 if (Result.getOpcode() == ISD::RET) { 2344 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2345 default: assert(0 && "This action is not supported yet!"); 2346 case TargetLowering::Legal: break; 2347 case TargetLowering::Custom: 2348 Tmp1 = TLI.LowerOperation(Result, DAG); 2349 if (Tmp1.Val) Result = Tmp1; 2350 break; 2351 } 2352 } 2353 break; 2354 case ISD::STORE: { 2355 StoreSDNode *ST = cast<StoreSDNode>(Node); 2356 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2357 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2358 int SVOffset = ST->getSrcValueOffset(); 2359 unsigned Alignment = ST->getAlignment(); 2360 bool isVolatile = ST->isVolatile(); 2361 2362 if (!ST->isTruncatingStore()) { 2363 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2364 // FIXME: We shouldn't do this for TargetConstantFP's. 2365 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2366 // to phase ordering between legalized code and the dag combiner. This 2367 // probably means that we need to integrate dag combiner and legalizer 2368 // together. 2369 // We generally can't do this one for long doubles. 2370 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2371 if (CFP->getValueType(0) == MVT::f32 && 2372 getTypeAction(MVT::i32) == Legal) { 2373 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2374 convertToAPInt().zextOrTrunc(32), 2375 MVT::i32); 2376 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2377 SVOffset, isVolatile, Alignment); 2378 break; 2379 } else if (CFP->getValueType(0) == MVT::f64) { 2380 // If this target supports 64-bit registers, do a single 64-bit store. 2381 if (getTypeAction(MVT::i64) == Legal) { 2382 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2383 zextOrTrunc(64), MVT::i64); 2384 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2385 SVOffset, isVolatile, Alignment); 2386 break; 2387 } else if (getTypeAction(MVT::i32) == Legal) { 2388 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2389 // stores. If the target supports neither 32- nor 64-bits, this 2390 // xform is certainly not worth it. 2391 const APInt &IntVal =CFP->getValueAPF().convertToAPInt(); 2392 SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2393 SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2394 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2395 2396 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2397 SVOffset, isVolatile, Alignment); 2398 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2399 DAG.getIntPtrConstant(4)); 2400 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2401 isVolatile, MinAlign(Alignment, 4U)); 2402 2403 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2404 break; 2405 } 2406 } 2407 } 2408 2409 switch (getTypeAction(ST->getMemoryVT())) { 2410 case Legal: { 2411 Tmp3 = LegalizeOp(ST->getValue()); 2412 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2413 ST->getOffset()); 2414 2415 MVT VT = Tmp3.getValueType(); 2416 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2417 default: assert(0 && "This action is not supported yet!"); 2418 case TargetLowering::Legal: 2419 // If this is an unaligned store and the target doesn't support it, 2420 // expand it. 2421 if (!TLI.allowsUnalignedMemoryAccesses()) { 2422 unsigned ABIAlignment = TLI.getTargetData()-> 2423 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2424 if (ST->getAlignment() < ABIAlignment) 2425 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2426 TLI); 2427 } 2428 break; 2429 case TargetLowering::Custom: 2430 Tmp1 = TLI.LowerOperation(Result, DAG); 2431 if (Tmp1.Val) Result = Tmp1; 2432 break; 2433 case TargetLowering::Promote: 2434 assert(VT.isVector() && "Unknown legal promote case!"); 2435 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2436 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2437 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2438 ST->getSrcValue(), SVOffset, isVolatile, 2439 Alignment); 2440 break; 2441 } 2442 break; 2443 } 2444 case Promote: 2445 // Truncate the value and store the result. 2446 Tmp3 = PromoteOp(ST->getValue()); 2447 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2448 SVOffset, ST->getMemoryVT(), 2449 isVolatile, Alignment); 2450 break; 2451 2452 case Expand: 2453 unsigned IncrementSize = 0; 2454 SDOperand Lo, Hi; 2455 2456 // If this is a vector type, then we have to calculate the increment as 2457 // the product of the element size in bytes, and the number of elements 2458 // in the high half of the vector. 2459 if (ST->getValue().getValueType().isVector()) { 2460 SDNode *InVal = ST->getValue().Val; 2461 int InIx = ST->getValue().ResNo; 2462 MVT InVT = InVal->getValueType(InIx); 2463 unsigned NumElems = InVT.getVectorNumElements(); 2464 MVT EVT = InVT.getVectorElementType(); 2465 2466 // Figure out if there is a simple type corresponding to this Vector 2467 // type. If so, convert to the vector type. 2468 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2469 if (TLI.isTypeLegal(TVT)) { 2470 // Turn this into a normal store of the vector type. 2471 Tmp3 = LegalizeOp(ST->getValue()); 2472 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2473 SVOffset, isVolatile, Alignment); 2474 Result = LegalizeOp(Result); 2475 break; 2476 } else if (NumElems == 1) { 2477 // Turn this into a normal store of the scalar type. 2478 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2479 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2480 SVOffset, isVolatile, Alignment); 2481 // The scalarized value type may not be legal, e.g. it might require 2482 // promotion or expansion. Relegalize the scalar store. 2483 Result = LegalizeOp(Result); 2484 break; 2485 } else { 2486 SplitVectorOp(ST->getValue(), Lo, Hi); 2487 IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() * 2488 EVT.getSizeInBits()/8; 2489 } 2490 } else { 2491 ExpandOp(ST->getValue(), Lo, Hi); 2492 IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0; 2493 2494 if (TLI.isBigEndian()) 2495 std::swap(Lo, Hi); 2496 } 2497 2498 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2499 SVOffset, isVolatile, Alignment); 2500 2501 if (Hi.Val == NULL) { 2502 // Must be int <-> float one-to-one expansion. 2503 Result = Lo; 2504 break; 2505 } 2506 2507 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2508 DAG.getIntPtrConstant(IncrementSize)); 2509 assert(isTypeLegal(Tmp2.getValueType()) && 2510 "Pointers must be legal!"); 2511 SVOffset += IncrementSize; 2512 Alignment = MinAlign(Alignment, IncrementSize); 2513 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2514 SVOffset, isVolatile, Alignment); 2515 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2516 break; 2517 } 2518 } else { 2519 switch (getTypeAction(ST->getValue().getValueType())) { 2520 case Legal: 2521 Tmp3 = LegalizeOp(ST->getValue()); 2522 break; 2523 case Promote: 2524 // We can promote the value, the truncstore will still take care of it. 2525 Tmp3 = PromoteOp(ST->getValue()); 2526 break; 2527 case Expand: 2528 // Just store the low part. This may become a non-trunc store, so make 2529 // sure to use getTruncStore, not UpdateNodeOperands below. 2530 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2531 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2532 SVOffset, MVT::i8, isVolatile, Alignment); 2533 } 2534 2535 MVT StVT = ST->getMemoryVT(); 2536 unsigned StWidth = StVT.getSizeInBits(); 2537 2538 if (StWidth != StVT.getStoreSizeInBits()) { 2539 // Promote to a byte-sized store with upper bits zero if not 2540 // storing an integral number of bytes. For example, promote 2541 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2542 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 2543 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); 2544 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2545 SVOffset, NVT, isVolatile, Alignment); 2546 } else if (StWidth & (StWidth - 1)) { 2547 // If not storing a power-of-2 number of bits, expand as two stores. 2548 assert(StVT.isExtended() && !StVT.isVector() && 2549 "Unsupported truncstore!"); 2550 unsigned RoundWidth = 1 << Log2_32(StWidth); 2551 assert(RoundWidth < StWidth); 2552 unsigned ExtraWidth = StWidth - RoundWidth; 2553 assert(ExtraWidth < RoundWidth); 2554 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2555 "Store size not an integral number of bytes!"); 2556 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2557 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2558 SDOperand Lo, Hi; 2559 unsigned IncrementSize; 2560 2561 if (TLI.isLittleEndian()) { 2562 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2563 // Store the bottom RoundWidth bits. 2564 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2565 SVOffset, RoundVT, 2566 isVolatile, Alignment); 2567 2568 // Store the remaining ExtraWidth bits. 2569 IncrementSize = RoundWidth / 8; 2570 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2571 DAG.getIntPtrConstant(IncrementSize)); 2572 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2573 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2574 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2575 SVOffset + IncrementSize, ExtraVT, isVolatile, 2576 MinAlign(Alignment, IncrementSize)); 2577 } else { 2578 // Big endian - avoid unaligned stores. 2579 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2580 // Store the top RoundWidth bits. 2581 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2582 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2583 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, 2584 RoundVT, isVolatile, Alignment); 2585 2586 // Store the remaining ExtraWidth bits. 2587 IncrementSize = RoundWidth / 8; 2588 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2589 DAG.getIntPtrConstant(IncrementSize)); 2590 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2591 SVOffset + IncrementSize, ExtraVT, isVolatile, 2592 MinAlign(Alignment, IncrementSize)); 2593 } 2594 2595 // The order of the stores doesn't matter. 2596 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2597 } else { 2598 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2599 Tmp2 != ST->getBasePtr()) 2600 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2601 ST->getOffset()); 2602 2603 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2604 default: assert(0 && "This action is not supported yet!"); 2605 case TargetLowering::Legal: 2606 // If this is an unaligned store and the target doesn't support it, 2607 // expand it. 2608 if (!TLI.allowsUnalignedMemoryAccesses()) { 2609 unsigned ABIAlignment = TLI.getTargetData()-> 2610 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2611 if (ST->getAlignment() < ABIAlignment) 2612 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2613 TLI); 2614 } 2615 break; 2616 case TargetLowering::Custom: 2617 Result = TLI.LowerOperation(Result, DAG); 2618 break; 2619 case Expand: 2620 // TRUNCSTORE:i16 i32 -> STORE i16 2621 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2622 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); 2623 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, 2624 isVolatile, Alignment); 2625 break; 2626 } 2627 } 2628 } 2629 break; 2630 } 2631 case ISD::PCMARKER: 2632 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2633 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2634 break; 2635 case ISD::STACKSAVE: 2636 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2637 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2638 Tmp1 = Result.getValue(0); 2639 Tmp2 = Result.getValue(1); 2640 2641 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2642 default: assert(0 && "This action is not supported yet!"); 2643 case TargetLowering::Legal: break; 2644 case TargetLowering::Custom: 2645 Tmp3 = TLI.LowerOperation(Result, DAG); 2646 if (Tmp3.Val) { 2647 Tmp1 = LegalizeOp(Tmp3); 2648 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2649 } 2650 break; 2651 case TargetLowering::Expand: 2652 // Expand to CopyFromReg if the target set 2653 // StackPointerRegisterToSaveRestore. 2654 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2655 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2656 Node->getValueType(0)); 2657 Tmp2 = Tmp1.getValue(1); 2658 } else { 2659 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2660 Tmp2 = Node->getOperand(0); 2661 } 2662 break; 2663 } 2664 2665 // Since stacksave produce two values, make sure to remember that we 2666 // legalized both of them. 2667 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2668 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2669 return Op.ResNo ? Tmp2 : Tmp1; 2670 2671 case ISD::STACKRESTORE: 2672 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2673 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2674 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2675 2676 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2677 default: assert(0 && "This action is not supported yet!"); 2678 case TargetLowering::Legal: break; 2679 case TargetLowering::Custom: 2680 Tmp1 = TLI.LowerOperation(Result, DAG); 2681 if (Tmp1.Val) Result = Tmp1; 2682 break; 2683 case TargetLowering::Expand: 2684 // Expand to CopyToReg if the target set 2685 // StackPointerRegisterToSaveRestore. 2686 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2687 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2688 } else { 2689 Result = Tmp1; 2690 } 2691 break; 2692 } 2693 break; 2694 2695 case ISD::READCYCLECOUNTER: 2696 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2697 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2698 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2699 Node->getValueType(0))) { 2700 default: assert(0 && "This action is not supported yet!"); 2701 case TargetLowering::Legal: 2702 Tmp1 = Result.getValue(0); 2703 Tmp2 = Result.getValue(1); 2704 break; 2705 case TargetLowering::Custom: 2706 Result = TLI.LowerOperation(Result, DAG); 2707 Tmp1 = LegalizeOp(Result.getValue(0)); 2708 Tmp2 = LegalizeOp(Result.getValue(1)); 2709 break; 2710 } 2711 2712 // Since rdcc produce two values, make sure to remember that we legalized 2713 // both of them. 2714 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2715 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2716 return Result; 2717 2718 case ISD::SELECT: 2719 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2720 case Expand: assert(0 && "It's impossible to expand bools"); 2721 case Legal: 2722 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2723 break; 2724 case Promote: { 2725 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2726 // Make sure the condition is either zero or one. 2727 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2728 if (!DAG.MaskedValueIsZero(Tmp1, 2729 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2730 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2731 break; 2732 } 2733 } 2734 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2735 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2736 2737 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2738 2739 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2740 default: assert(0 && "This action is not supported yet!"); 2741 case TargetLowering::Legal: break; 2742 case TargetLowering::Custom: { 2743 Tmp1 = TLI.LowerOperation(Result, DAG); 2744 if (Tmp1.Val) Result = Tmp1; 2745 break; 2746 } 2747 case TargetLowering::Expand: 2748 if (Tmp1.getOpcode() == ISD::SETCC) { 2749 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2750 Tmp2, Tmp3, 2751 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2752 } else { 2753 Result = DAG.getSelectCC(Tmp1, 2754 DAG.getConstant(0, Tmp1.getValueType()), 2755 Tmp2, Tmp3, ISD::SETNE); 2756 } 2757 break; 2758 case TargetLowering::Promote: { 2759 MVT NVT = 2760 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2761 unsigned ExtOp, TruncOp; 2762 if (Tmp2.getValueType().isVector()) { 2763 ExtOp = ISD::BIT_CONVERT; 2764 TruncOp = ISD::BIT_CONVERT; 2765 } else if (Tmp2.getValueType().isInteger()) { 2766 ExtOp = ISD::ANY_EXTEND; 2767 TruncOp = ISD::TRUNCATE; 2768 } else { 2769 ExtOp = ISD::FP_EXTEND; 2770 TruncOp = ISD::FP_ROUND; 2771 } 2772 // Promote each of the values to the new type. 2773 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2774 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2775 // Perform the larger operation, then round down. 2776 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2777 if (TruncOp != ISD::FP_ROUND) 2778 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2779 else 2780 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2781 DAG.getIntPtrConstant(0)); 2782 break; 2783 } 2784 } 2785 break; 2786 case ISD::SELECT_CC: { 2787 Tmp1 = Node->getOperand(0); // LHS 2788 Tmp2 = Node->getOperand(1); // RHS 2789 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2790 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2791 SDOperand CC = Node->getOperand(4); 2792 2793 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2794 2795 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2796 // the LHS is a legal SETCC itself. In this case, we need to compare 2797 // the result against zero to select between true and false values. 2798 if (Tmp2.Val == 0) { 2799 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2800 CC = DAG.getCondCode(ISD::SETNE); 2801 } 2802 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2803 2804 // Everything is legal, see if we should expand this op or something. 2805 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2806 default: assert(0 && "This action is not supported yet!"); 2807 case TargetLowering::Legal: break; 2808 case TargetLowering::Custom: 2809 Tmp1 = TLI.LowerOperation(Result, DAG); 2810 if (Tmp1.Val) Result = Tmp1; 2811 break; 2812 } 2813 break; 2814 } 2815 case ISD::SETCC: 2816 Tmp1 = Node->getOperand(0); 2817 Tmp2 = Node->getOperand(1); 2818 Tmp3 = Node->getOperand(2); 2819 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2820 2821 // If we had to Expand the SetCC operands into a SELECT node, then it may 2822 // not always be possible to return a true LHS & RHS. In this case, just 2823 // return the value we legalized, returned in the LHS 2824 if (Tmp2.Val == 0) { 2825 Result = Tmp1; 2826 break; 2827 } 2828 2829 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2830 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2831 case TargetLowering::Custom: 2832 isCustom = true; 2833 // FALLTHROUGH. 2834 case TargetLowering::Legal: 2835 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2836 if (isCustom) { 2837 Tmp4 = TLI.LowerOperation(Result, DAG); 2838 if (Tmp4.Val) Result = Tmp4; 2839 } 2840 break; 2841 case TargetLowering::Promote: { 2842 // First step, figure out the appropriate operation to use. 2843 // Allow SETCC to not be supported for all legal data types 2844 // Mostly this targets FP 2845 MVT NewInTy = Node->getOperand(0).getValueType(); 2846 MVT OldVT = NewInTy; OldVT = OldVT; 2847 2848 // Scan for the appropriate larger type to use. 2849 while (1) { 2850 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 2851 2852 assert(NewInTy.isInteger() == OldVT.isInteger() && 2853 "Fell off of the edge of the integer world"); 2854 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 2855 "Fell off of the edge of the floating point world"); 2856 2857 // If the target supports SETCC of this type, use it. 2858 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2859 break; 2860 } 2861 if (NewInTy.isInteger()) 2862 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2863 else { 2864 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2865 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2866 } 2867 Tmp1 = LegalizeOp(Tmp1); 2868 Tmp2 = LegalizeOp(Tmp2); 2869 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2870 Result = LegalizeOp(Result); 2871 break; 2872 } 2873 case TargetLowering::Expand: 2874 // Expand a setcc node into a select_cc of the same condition, lhs, and 2875 // rhs that selects between const 1 (true) and const 0 (false). 2876 MVT VT = Node->getValueType(0); 2877 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2878 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2879 Tmp3); 2880 break; 2881 } 2882 break; 2883 case ISD::VSETCC: { 2884 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2885 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2886 SDOperand CC = Node->getOperand(2); 2887 2888 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC); 2889 2890 // Everything is legal, see if we should expand this op or something. 2891 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) { 2892 default: assert(0 && "This action is not supported yet!"); 2893 case TargetLowering::Legal: break; 2894 case TargetLowering::Custom: 2895 Tmp1 = TLI.LowerOperation(Result, DAG); 2896 if (Tmp1.Val) Result = Tmp1; 2897 break; 2898 } 2899 break; 2900 } 2901 2902 case ISD::SHL_PARTS: 2903 case ISD::SRA_PARTS: 2904 case ISD::SRL_PARTS: { 2905 SmallVector<SDOperand, 8> Ops; 2906 bool Changed = false; 2907 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2908 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2909 Changed |= Ops.back() != Node->getOperand(i); 2910 } 2911 if (Changed) 2912 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2913 2914 switch (TLI.getOperationAction(Node->getOpcode(), 2915 Node->getValueType(0))) { 2916 default: assert(0 && "This action is not supported yet!"); 2917 case TargetLowering::Legal: break; 2918 case TargetLowering::Custom: 2919 Tmp1 = TLI.LowerOperation(Result, DAG); 2920 if (Tmp1.Val) { 2921 SDOperand Tmp2, RetVal(0, 0); 2922 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2923 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2924 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2925 if (i == Op.ResNo) 2926 RetVal = Tmp2; 2927 } 2928 assert(RetVal.Val && "Illegal result number"); 2929 return RetVal; 2930 } 2931 break; 2932 } 2933 2934 // Since these produce multiple values, make sure to remember that we 2935 // legalized all of them. 2936 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2937 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2938 return Result.getValue(Op.ResNo); 2939 } 2940 2941 // Binary operators 2942 case ISD::ADD: 2943 case ISD::SUB: 2944 case ISD::MUL: 2945 case ISD::MULHS: 2946 case ISD::MULHU: 2947 case ISD::UDIV: 2948 case ISD::SDIV: 2949 case ISD::AND: 2950 case ISD::OR: 2951 case ISD::XOR: 2952 case ISD::SHL: 2953 case ISD::SRL: 2954 case ISD::SRA: 2955 case ISD::FADD: 2956 case ISD::FSUB: 2957 case ISD::FMUL: 2958 case ISD::FDIV: 2959 case ISD::FPOW: 2960 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2961 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2962 case Expand: assert(0 && "Not possible"); 2963 case Legal: 2964 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2965 break; 2966 case Promote: 2967 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2968 break; 2969 } 2970 2971 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2972 2973 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2974 default: assert(0 && "BinOp legalize operation not supported"); 2975 case TargetLowering::Legal: break; 2976 case TargetLowering::Custom: 2977 Tmp1 = TLI.LowerOperation(Result, DAG); 2978 if (Tmp1.Val) Result = Tmp1; 2979 break; 2980 case TargetLowering::Expand: { 2981 MVT VT = Op.getValueType(); 2982 2983 // See if multiply or divide can be lowered using two-result operations. 2984 SDVTList VTs = DAG.getVTList(VT, VT); 2985 if (Node->getOpcode() == ISD::MUL) { 2986 // We just need the low half of the multiply; try both the signed 2987 // and unsigned forms. If the target supports both SMUL_LOHI and 2988 // UMUL_LOHI, form a preference by checking which forms of plain 2989 // MULH it supports. 2990 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2991 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2992 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2993 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2994 unsigned OpToUse = 0; 2995 if (HasSMUL_LOHI && !HasMULHS) { 2996 OpToUse = ISD::SMUL_LOHI; 2997 } else if (HasUMUL_LOHI && !HasMULHU) { 2998 OpToUse = ISD::UMUL_LOHI; 2999 } else if (HasSMUL_LOHI) { 3000 OpToUse = ISD::SMUL_LOHI; 3001 } else if (HasUMUL_LOHI) { 3002 OpToUse = ISD::UMUL_LOHI; 3003 } 3004 if (OpToUse) { 3005 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 3006 break; 3007 } 3008 } 3009 if (Node->getOpcode() == ISD::MULHS && 3010 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 3011 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3012 break; 3013 } 3014 if (Node->getOpcode() == ISD::MULHU && 3015 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 3016 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3017 break; 3018 } 3019 if (Node->getOpcode() == ISD::SDIV && 3020 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3021 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3022 break; 3023 } 3024 if (Node->getOpcode() == ISD::UDIV && 3025 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3026 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3027 break; 3028 } 3029 3030 // Check to see if we have a libcall for this operator. 3031 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3032 bool isSigned = false; 3033 switch (Node->getOpcode()) { 3034 case ISD::UDIV: 3035 case ISD::SDIV: 3036 if (VT == MVT::i32) { 3037 LC = Node->getOpcode() == ISD::UDIV 3038 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3039 isSigned = Node->getOpcode() == ISD::SDIV; 3040 } 3041 break; 3042 case ISD::FPOW: 3043 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3044 RTLIB::POW_PPCF128); 3045 break; 3046 default: break; 3047 } 3048 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3049 SDOperand Dummy; 3050 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3051 break; 3052 } 3053 3054 assert(Node->getValueType(0).isVector() && 3055 "Cannot expand this binary operator!"); 3056 // Expand the operation into a bunch of nasty scalar code. 3057 Result = LegalizeOp(UnrollVectorOp(Op)); 3058 break; 3059 } 3060 case TargetLowering::Promote: { 3061 switch (Node->getOpcode()) { 3062 default: assert(0 && "Do not know how to promote this BinOp!"); 3063 case ISD::AND: 3064 case ISD::OR: 3065 case ISD::XOR: { 3066 MVT OVT = Node->getValueType(0); 3067 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3068 assert(OVT.isVector() && "Cannot promote this BinOp!"); 3069 // Bit convert each of the values to the new type. 3070 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 3071 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 3072 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3073 // Bit convert the result back the original type. 3074 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 3075 break; 3076 } 3077 } 3078 } 3079 } 3080 break; 3081 3082 case ISD::SMUL_LOHI: 3083 case ISD::UMUL_LOHI: 3084 case ISD::SDIVREM: 3085 case ISD::UDIVREM: 3086 // These nodes will only be produced by target-specific lowering, so 3087 // they shouldn't be here if they aren't legal. 3088 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3089 "This must be legal!"); 3090 3091 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3092 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3093 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3094 break; 3095 3096 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3097 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3098 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3099 case Expand: assert(0 && "Not possible"); 3100 case Legal: 3101 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3102 break; 3103 case Promote: 3104 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3105 break; 3106 } 3107 3108 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3109 3110 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3111 default: assert(0 && "Operation not supported"); 3112 case TargetLowering::Custom: 3113 Tmp1 = TLI.LowerOperation(Result, DAG); 3114 if (Tmp1.Val) Result = Tmp1; 3115 break; 3116 case TargetLowering::Legal: break; 3117 case TargetLowering::Expand: { 3118 // If this target supports fabs/fneg natively and select is cheap, 3119 // do this efficiently. 3120 if (!TLI.isSelectExpensive() && 3121 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3122 TargetLowering::Legal && 3123 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3124 TargetLowering::Legal) { 3125 // Get the sign bit of the RHS. 3126 MVT IVT = 3127 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3128 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 3129 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), 3130 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3131 // Get the absolute value of the result. 3132 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 3133 // Select between the nabs and abs value based on the sign bit of 3134 // the input. 3135 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 3136 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3137 AbsVal), 3138 AbsVal); 3139 Result = LegalizeOp(Result); 3140 break; 3141 } 3142 3143 // Otherwise, do bitwise ops! 3144 MVT NVT = 3145 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3146 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3147 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 3148 Result = LegalizeOp(Result); 3149 break; 3150 } 3151 } 3152 break; 3153 3154 case ISD::ADDC: 3155 case ISD::SUBC: 3156 Tmp1 = LegalizeOp(Node->getOperand(0)); 3157 Tmp2 = LegalizeOp(Node->getOperand(1)); 3158 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3159 // Since this produces two values, make sure to remember that we legalized 3160 // both of them. 3161 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3162 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3163 return Result; 3164 3165 case ISD::ADDE: 3166 case ISD::SUBE: 3167 Tmp1 = LegalizeOp(Node->getOperand(0)); 3168 Tmp2 = LegalizeOp(Node->getOperand(1)); 3169 Tmp3 = LegalizeOp(Node->getOperand(2)); 3170 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3171 // Since this produces two values, make sure to remember that we legalized 3172 // both of them. 3173 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3174 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3175 return Result; 3176 3177 case ISD::BUILD_PAIR: { 3178 MVT PairTy = Node->getValueType(0); 3179 // TODO: handle the case where the Lo and Hi operands are not of legal type 3180 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3181 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3182 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3183 case TargetLowering::Promote: 3184 case TargetLowering::Custom: 3185 assert(0 && "Cannot promote/custom this yet!"); 3186 case TargetLowering::Legal: 3187 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3188 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 3189 break; 3190 case TargetLowering::Expand: 3191 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 3192 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 3193 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 3194 DAG.getConstant(PairTy.getSizeInBits()/2, 3195 TLI.getShiftAmountTy())); 3196 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 3197 break; 3198 } 3199 break; 3200 } 3201 3202 case ISD::UREM: 3203 case ISD::SREM: 3204 case ISD::FREM: 3205 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3206 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3207 3208 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3209 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3210 case TargetLowering::Custom: 3211 isCustom = true; 3212 // FALLTHROUGH 3213 case TargetLowering::Legal: 3214 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3215 if (isCustom) { 3216 Tmp1 = TLI.LowerOperation(Result, DAG); 3217 if (Tmp1.Val) Result = Tmp1; 3218 } 3219 break; 3220 case TargetLowering::Expand: { 3221 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3222 bool isSigned = DivOpc == ISD::SDIV; 3223 MVT VT = Node->getValueType(0); 3224 3225 // See if remainder can be lowered using two-result operations. 3226 SDVTList VTs = DAG.getVTList(VT, VT); 3227 if (Node->getOpcode() == ISD::SREM && 3228 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3229 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3230 break; 3231 } 3232 if (Node->getOpcode() == ISD::UREM && 3233 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3234 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3235 break; 3236 } 3237 3238 if (VT.isInteger()) { 3239 if (TLI.getOperationAction(DivOpc, VT) == 3240 TargetLowering::Legal) { 3241 // X % Y -> X-X/Y*Y 3242 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3243 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3244 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3245 } else if (VT.isVector()) { 3246 Result = LegalizeOp(UnrollVectorOp(Op)); 3247 } else { 3248 assert(VT == MVT::i32 && 3249 "Cannot expand this binary operator!"); 3250 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3251 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3252 SDOperand Dummy; 3253 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3254 } 3255 } else { 3256 assert(VT.isFloatingPoint() && 3257 "remainder op must have integer or floating-point type"); 3258 if (VT.isVector()) { 3259 Result = LegalizeOp(UnrollVectorOp(Op)); 3260 } else { 3261 // Floating point mod -> fmod libcall. 3262 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3263 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3264 SDOperand Dummy; 3265 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3266 } 3267 } 3268 break; 3269 } 3270 } 3271 break; 3272 case ISD::VAARG: { 3273 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3274 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3275 3276 MVT VT = Node->getValueType(0); 3277 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3278 default: assert(0 && "This action is not supported yet!"); 3279 case TargetLowering::Custom: 3280 isCustom = true; 3281 // FALLTHROUGH 3282 case TargetLowering::Legal: 3283 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3284 Result = Result.getValue(0); 3285 Tmp1 = Result.getValue(1); 3286 3287 if (isCustom) { 3288 Tmp2 = TLI.LowerOperation(Result, DAG); 3289 if (Tmp2.Val) { 3290 Result = LegalizeOp(Tmp2); 3291 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3292 } 3293 } 3294 break; 3295 case TargetLowering::Expand: { 3296 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3297 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 3298 // Increment the pointer, VAList, to the next vaarg 3299 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3300 DAG.getConstant(VT.getSizeInBits()/8, 3301 TLI.getPointerTy())); 3302 // Store the incremented VAList to the legalized pointer 3303 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 3304 // Load the actual argument out of the pointer VAList 3305 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3306 Tmp1 = LegalizeOp(Result.getValue(1)); 3307 Result = LegalizeOp(Result); 3308 break; 3309 } 3310 } 3311 // Since VAARG produces two values, make sure to remember that we 3312 // legalized both of them. 3313 AddLegalizedOperand(SDOperand(Node, 0), Result); 3314 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3315 return Op.ResNo ? Tmp1 : Result; 3316 } 3317 3318 case ISD::VACOPY: 3319 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3320 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3321 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3322 3323 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3324 default: assert(0 && "This action is not supported yet!"); 3325 case TargetLowering::Custom: 3326 isCustom = true; 3327 // FALLTHROUGH 3328 case TargetLowering::Legal: 3329 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3330 Node->getOperand(3), Node->getOperand(4)); 3331 if (isCustom) { 3332 Tmp1 = TLI.LowerOperation(Result, DAG); 3333 if (Tmp1.Val) Result = Tmp1; 3334 } 3335 break; 3336 case TargetLowering::Expand: 3337 // This defaults to loading a pointer from the input and storing it to the 3338 // output, returning the chain. 3339 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3340 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3341 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0); 3342 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0); 3343 break; 3344 } 3345 break; 3346 3347 case ISD::VAEND: 3348 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3349 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3350 3351 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3352 default: assert(0 && "This action is not supported yet!"); 3353 case TargetLowering::Custom: 3354 isCustom = true; 3355 // FALLTHROUGH 3356 case TargetLowering::Legal: 3357 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3358 if (isCustom) { 3359 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3360 if (Tmp1.Val) Result = Tmp1; 3361 } 3362 break; 3363 case TargetLowering::Expand: 3364 Result = Tmp1; // Default to a no-op, return the chain 3365 break; 3366 } 3367 break; 3368 3369 case ISD::VASTART: 3370 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3371 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3372 3373 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3374 3375 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3376 default: assert(0 && "This action is not supported yet!"); 3377 case TargetLowering::Legal: break; 3378 case TargetLowering::Custom: 3379 Tmp1 = TLI.LowerOperation(Result, DAG); 3380 if (Tmp1.Val) Result = Tmp1; 3381 break; 3382 } 3383 break; 3384 3385 case ISD::ROTL: 3386 case ISD::ROTR: 3387 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3388 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3389 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3390 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3391 default: 3392 assert(0 && "ROTL/ROTR legalize operation not supported"); 3393 break; 3394 case TargetLowering::Legal: 3395 break; 3396 case TargetLowering::Custom: 3397 Tmp1 = TLI.LowerOperation(Result, DAG); 3398 if (Tmp1.Val) Result = Tmp1; 3399 break; 3400 case TargetLowering::Promote: 3401 assert(0 && "Do not know how to promote ROTL/ROTR"); 3402 break; 3403 case TargetLowering::Expand: 3404 assert(0 && "Do not know how to expand ROTL/ROTR"); 3405 break; 3406 } 3407 break; 3408 3409 case ISD::BSWAP: 3410 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3411 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3412 case TargetLowering::Custom: 3413 assert(0 && "Cannot custom legalize this yet!"); 3414 case TargetLowering::Legal: 3415 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3416 break; 3417 case TargetLowering::Promote: { 3418 MVT OVT = Tmp1.getValueType(); 3419 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3420 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3421 3422 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3423 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3424 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3425 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3426 break; 3427 } 3428 case TargetLowering::Expand: 3429 Result = ExpandBSWAP(Tmp1); 3430 break; 3431 } 3432 break; 3433 3434 case ISD::CTPOP: 3435 case ISD::CTTZ: 3436 case ISD::CTLZ: 3437 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3438 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3439 case TargetLowering::Custom: 3440 case TargetLowering::Legal: 3441 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3442 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3443 TargetLowering::Custom) { 3444 Tmp1 = TLI.LowerOperation(Result, DAG); 3445 if (Tmp1.Val) { 3446 Result = Tmp1; 3447 } 3448 } 3449 break; 3450 case TargetLowering::Promote: { 3451 MVT OVT = Tmp1.getValueType(); 3452 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3453 3454 // Zero extend the argument. 3455 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3456 // Perform the larger operation, then subtract if needed. 3457 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3458 switch (Node->getOpcode()) { 3459 case ISD::CTPOP: 3460 Result = Tmp1; 3461 break; 3462 case ISD::CTTZ: 3463 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3464 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 3465 DAG.getConstant(NVT.getSizeInBits(), NVT), 3466 ISD::SETEQ); 3467 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3468 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3469 break; 3470 case ISD::CTLZ: 3471 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3472 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3473 DAG.getConstant(NVT.getSizeInBits() - 3474 OVT.getSizeInBits(), NVT)); 3475 break; 3476 } 3477 break; 3478 } 3479 case TargetLowering::Expand: 3480 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3481 break; 3482 } 3483 break; 3484 3485 // Unary operators 3486 case ISD::FABS: 3487 case ISD::FNEG: 3488 case ISD::FSQRT: 3489 case ISD::FSIN: 3490 case ISD::FCOS: 3491 Tmp1 = LegalizeOp(Node->getOperand(0)); 3492 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3493 case TargetLowering::Promote: 3494 case TargetLowering::Custom: 3495 isCustom = true; 3496 // FALLTHROUGH 3497 case TargetLowering::Legal: 3498 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3499 if (isCustom) { 3500 Tmp1 = TLI.LowerOperation(Result, DAG); 3501 if (Tmp1.Val) Result = Tmp1; 3502 } 3503 break; 3504 case TargetLowering::Expand: 3505 switch (Node->getOpcode()) { 3506 default: assert(0 && "Unreachable!"); 3507 case ISD::FNEG: 3508 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3509 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3510 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3511 break; 3512 case ISD::FABS: { 3513 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3514 MVT VT = Node->getValueType(0); 3515 Tmp2 = DAG.getConstantFP(0.0, VT); 3516 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 3517 ISD::SETUGT); 3518 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3519 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3520 break; 3521 } 3522 case ISD::FSQRT: 3523 case ISD::FSIN: 3524 case ISD::FCOS: { 3525 MVT VT = Node->getValueType(0); 3526 3527 // Expand unsupported unary vector operators by unrolling them. 3528 if (VT.isVector()) { 3529 Result = LegalizeOp(UnrollVectorOp(Op)); 3530 break; 3531 } 3532 3533 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3534 switch(Node->getOpcode()) { 3535 case ISD::FSQRT: 3536 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3537 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3538 break; 3539 case ISD::FSIN: 3540 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3541 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3542 break; 3543 case ISD::FCOS: 3544 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3545 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3546 break; 3547 default: assert(0 && "Unreachable!"); 3548 } 3549 SDOperand Dummy; 3550 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3551 break; 3552 } 3553 } 3554 break; 3555 } 3556 break; 3557 case ISD::FPOWI: { 3558 MVT VT = Node->getValueType(0); 3559 3560 // Expand unsupported unary vector operators by unrolling them. 3561 if (VT.isVector()) { 3562 Result = LegalizeOp(UnrollVectorOp(Op)); 3563 break; 3564 } 3565 3566 // We always lower FPOWI into a libcall. No target support for it yet. 3567 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3568 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3569 SDOperand Dummy; 3570 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3571 break; 3572 } 3573 case ISD::BIT_CONVERT: 3574 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3575 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3576 Node->getValueType(0)); 3577 } else if (Op.getOperand(0).getValueType().isVector()) { 3578 // The input has to be a vector type, we have to either scalarize it, pack 3579 // it, or convert it based on whether the input vector type is legal. 3580 SDNode *InVal = Node->getOperand(0).Val; 3581 int InIx = Node->getOperand(0).ResNo; 3582 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 3583 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 3584 3585 // Figure out if there is a simple type corresponding to this Vector 3586 // type. If so, convert to the vector type. 3587 MVT TVT = MVT::getVectorVT(EVT, NumElems); 3588 if (TLI.isTypeLegal(TVT)) { 3589 // Turn this into a bit convert of the vector input. 3590 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3591 LegalizeOp(Node->getOperand(0))); 3592 break; 3593 } else if (NumElems == 1) { 3594 // Turn this into a bit convert of the scalar input. 3595 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3596 ScalarizeVectorOp(Node->getOperand(0))); 3597 break; 3598 } else { 3599 // FIXME: UNIMP! Store then reload 3600 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3601 } 3602 } else { 3603 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3604 Node->getOperand(0).getValueType())) { 3605 default: assert(0 && "Unknown operation action!"); 3606 case TargetLowering::Expand: 3607 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3608 Node->getValueType(0)); 3609 break; 3610 case TargetLowering::Legal: 3611 Tmp1 = LegalizeOp(Node->getOperand(0)); 3612 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3613 break; 3614 } 3615 } 3616 break; 3617 3618 // Conversion operators. The source and destination have different types. 3619 case ISD::SINT_TO_FP: 3620 case ISD::UINT_TO_FP: { 3621 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3622 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3623 case Legal: 3624 switch (TLI.getOperationAction(Node->getOpcode(), 3625 Node->getOperand(0).getValueType())) { 3626 default: assert(0 && "Unknown operation action!"); 3627 case TargetLowering::Custom: 3628 isCustom = true; 3629 // FALLTHROUGH 3630 case TargetLowering::Legal: 3631 Tmp1 = LegalizeOp(Node->getOperand(0)); 3632 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3633 if (isCustom) { 3634 Tmp1 = TLI.LowerOperation(Result, DAG); 3635 if (Tmp1.Val) Result = Tmp1; 3636 } 3637 break; 3638 case TargetLowering::Expand: 3639 Result = ExpandLegalINT_TO_FP(isSigned, 3640 LegalizeOp(Node->getOperand(0)), 3641 Node->getValueType(0)); 3642 break; 3643 case TargetLowering::Promote: 3644 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3645 Node->getValueType(0), 3646 isSigned); 3647 break; 3648 } 3649 break; 3650 case Expand: 3651 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3652 Node->getValueType(0), Node->getOperand(0)); 3653 break; 3654 case Promote: 3655 Tmp1 = PromoteOp(Node->getOperand(0)); 3656 if (isSigned) { 3657 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3658 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3659 } else { 3660 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3661 Node->getOperand(0).getValueType()); 3662 } 3663 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3664 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3665 break; 3666 } 3667 break; 3668 } 3669 case ISD::TRUNCATE: 3670 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3671 case Legal: 3672 Tmp1 = LegalizeOp(Node->getOperand(0)); 3673 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3674 break; 3675 case Expand: 3676 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3677 3678 // Since the result is legal, we should just be able to truncate the low 3679 // part of the source. 3680 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3681 break; 3682 case Promote: 3683 Result = PromoteOp(Node->getOperand(0)); 3684 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3685 break; 3686 } 3687 break; 3688 3689 case ISD::FP_TO_SINT: 3690 case ISD::FP_TO_UINT: 3691 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3692 case Legal: 3693 Tmp1 = LegalizeOp(Node->getOperand(0)); 3694 3695 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3696 default: assert(0 && "Unknown operation action!"); 3697 case TargetLowering::Custom: 3698 isCustom = true; 3699 // FALLTHROUGH 3700 case TargetLowering::Legal: 3701 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3702 if (isCustom) { 3703 Tmp1 = TLI.LowerOperation(Result, DAG); 3704 if (Tmp1.Val) Result = Tmp1; 3705 } 3706 break; 3707 case TargetLowering::Promote: 3708 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3709 Node->getOpcode() == ISD::FP_TO_SINT); 3710 break; 3711 case TargetLowering::Expand: 3712 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3713 SDOperand True, False; 3714 MVT VT = Node->getOperand(0).getValueType(); 3715 MVT NVT = Node->getValueType(0); 3716 const uint64_t zero[] = {0, 0}; 3717 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 3718 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 3719 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 3720 Tmp2 = DAG.getConstantFP(apf, VT); 3721 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)), 3722 Node->getOperand(0), Tmp2, ISD::SETLT); 3723 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3724 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3725 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3726 Tmp2)); 3727 False = DAG.getNode(ISD::XOR, NVT, False, 3728 DAG.getConstant(x, NVT)); 3729 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3730 break; 3731 } else { 3732 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3733 } 3734 break; 3735 } 3736 break; 3737 case Expand: { 3738 MVT VT = Op.getValueType(); 3739 MVT OVT = Node->getOperand(0).getValueType(); 3740 // Convert ppcf128 to i32 3741 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3742 if (Node->getOpcode() == ISD::FP_TO_SINT) { 3743 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 3744 Node->getOperand(0), DAG.getValueType(MVT::f64)); 3745 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 3746 DAG.getIntPtrConstant(1)); 3747 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 3748 } else { 3749 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3750 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3751 Tmp2 = DAG.getConstantFP(apf, OVT); 3752 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3753 // FIXME: generated code sucks. 3754 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3755 DAG.getNode(ISD::ADD, MVT::i32, 3756 DAG.getNode(ISD::FP_TO_SINT, VT, 3757 DAG.getNode(ISD::FSUB, OVT, 3758 Node->getOperand(0), Tmp2)), 3759 DAG.getConstant(0x80000000, MVT::i32)), 3760 DAG.getNode(ISD::FP_TO_SINT, VT, 3761 Node->getOperand(0)), 3762 DAG.getCondCode(ISD::SETGE)); 3763 } 3764 break; 3765 } 3766 // Convert f32 / f64 to i32 / i64 / i128. 3767 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3768 switch (Node->getOpcode()) { 3769 case ISD::FP_TO_SINT: { 3770 if (VT == MVT::i32) { 3771 if (OVT == MVT::f32) 3772 LC = RTLIB::FPTOSINT_F32_I32; 3773 else if (OVT == MVT::f64) 3774 LC = RTLIB::FPTOSINT_F64_I32; 3775 else 3776 assert(0 && "Unexpected i32-to-fp conversion!"); 3777 } else if (VT == MVT::i64) { 3778 if (OVT == MVT::f32) 3779 LC = RTLIB::FPTOSINT_F32_I64; 3780 else if (OVT == MVT::f64) 3781 LC = RTLIB::FPTOSINT_F64_I64; 3782 else if (OVT == MVT::f80) 3783 LC = RTLIB::FPTOSINT_F80_I64; 3784 else if (OVT == MVT::ppcf128) 3785 LC = RTLIB::FPTOSINT_PPCF128_I64; 3786 else 3787 assert(0 && "Unexpected i64-to-fp conversion!"); 3788 } else if (VT == MVT::i128) { 3789 if (OVT == MVT::f32) 3790 LC = RTLIB::FPTOSINT_F32_I128; 3791 else if (OVT == MVT::f64) 3792 LC = RTLIB::FPTOSINT_F64_I128; 3793 else if (OVT == MVT::f80) 3794 LC = RTLIB::FPTOSINT_F80_I128; 3795 else if (OVT == MVT::ppcf128) 3796 LC = RTLIB::FPTOSINT_PPCF128_I128; 3797 else 3798 assert(0 && "Unexpected i128-to-fp conversion!"); 3799 } else { 3800 assert(0 && "Unexpectd int-to-fp conversion!"); 3801 } 3802 break; 3803 } 3804 case ISD::FP_TO_UINT: { 3805 if (VT == MVT::i32) { 3806 if (OVT == MVT::f32) 3807 LC = RTLIB::FPTOUINT_F32_I32; 3808 else if (OVT == MVT::f64) 3809 LC = RTLIB::FPTOUINT_F64_I32; 3810 else if (OVT == MVT::f80) 3811 LC = RTLIB::FPTOUINT_F80_I32; 3812 else 3813 assert(0 && "Unexpected i32-to-fp conversion!"); 3814 } else if (VT == MVT::i64) { 3815 if (OVT == MVT::f32) 3816 LC = RTLIB::FPTOUINT_F32_I64; 3817 else if (OVT == MVT::f64) 3818 LC = RTLIB::FPTOUINT_F64_I64; 3819 else if (OVT == MVT::f80) 3820 LC = RTLIB::FPTOUINT_F80_I64; 3821 else if (OVT == MVT::ppcf128) 3822 LC = RTLIB::FPTOUINT_PPCF128_I64; 3823 else 3824 assert(0 && "Unexpected i64-to-fp conversion!"); 3825 } else if (VT == MVT::i128) { 3826 if (OVT == MVT::f32) 3827 LC = RTLIB::FPTOUINT_F32_I128; 3828 else if (OVT == MVT::f64) 3829 LC = RTLIB::FPTOUINT_F64_I128; 3830 else if (OVT == MVT::f80) 3831 LC = RTLIB::FPTOUINT_F80_I128; 3832 else if (OVT == MVT::ppcf128) 3833 LC = RTLIB::FPTOUINT_PPCF128_I128; 3834 else 3835 assert(0 && "Unexpected i128-to-fp conversion!"); 3836 } else { 3837 assert(0 && "Unexpectd int-to-fp conversion!"); 3838 } 3839 break; 3840 } 3841 default: assert(0 && "Unreachable!"); 3842 } 3843 SDOperand Dummy; 3844 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3845 break; 3846 } 3847 case Promote: 3848 Tmp1 = PromoteOp(Node->getOperand(0)); 3849 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3850 Result = LegalizeOp(Result); 3851 break; 3852 } 3853 break; 3854 3855 case ISD::FP_EXTEND: { 3856 MVT DstVT = Op.getValueType(); 3857 MVT SrcVT = Op.getOperand(0).getValueType(); 3858 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3859 // The only other way we can lower this is to turn it into a STORE, 3860 // LOAD pair, targetting a temporary location (a stack slot). 3861 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 3862 break; 3863 } 3864 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3865 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3866 case Legal: 3867 Tmp1 = LegalizeOp(Node->getOperand(0)); 3868 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3869 break; 3870 case Promote: 3871 Tmp1 = PromoteOp(Node->getOperand(0)); 3872 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 3873 break; 3874 } 3875 break; 3876 } 3877 case ISD::FP_ROUND: { 3878 MVT DstVT = Op.getValueType(); 3879 MVT SrcVT = Op.getOperand(0).getValueType(); 3880 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3881 if (SrcVT == MVT::ppcf128) { 3882 SDOperand Lo; 3883 ExpandOp(Node->getOperand(0), Lo, Result); 3884 // Round it the rest of the way (e.g. to f32) if needed. 3885 if (DstVT!=MVT::f64) 3886 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 3887 break; 3888 } 3889 // The only other way we can lower this is to turn it into a STORE, 3890 // LOAD pair, targetting a temporary location (a stack slot). 3891 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 3892 break; 3893 } 3894 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3895 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3896 case Legal: 3897 Tmp1 = LegalizeOp(Node->getOperand(0)); 3898 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3899 break; 3900 case Promote: 3901 Tmp1 = PromoteOp(Node->getOperand(0)); 3902 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 3903 Node->getOperand(1)); 3904 break; 3905 } 3906 break; 3907 } 3908 case ISD::ANY_EXTEND: 3909 case ISD::ZERO_EXTEND: 3910 case ISD::SIGN_EXTEND: 3911 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3912 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3913 case Legal: 3914 Tmp1 = LegalizeOp(Node->getOperand(0)); 3915 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3916 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3917 TargetLowering::Custom) { 3918 Tmp1 = TLI.LowerOperation(Result, DAG); 3919 if (Tmp1.Val) Result = Tmp1; 3920 } 3921 break; 3922 case Promote: 3923 switch (Node->getOpcode()) { 3924 case ISD::ANY_EXTEND: 3925 Tmp1 = PromoteOp(Node->getOperand(0)); 3926 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3927 break; 3928 case ISD::ZERO_EXTEND: 3929 Result = PromoteOp(Node->getOperand(0)); 3930 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3931 Result = DAG.getZeroExtendInReg(Result, 3932 Node->getOperand(0).getValueType()); 3933 break; 3934 case ISD::SIGN_EXTEND: 3935 Result = PromoteOp(Node->getOperand(0)); 3936 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3937 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3938 Result, 3939 DAG.getValueType(Node->getOperand(0).getValueType())); 3940 break; 3941 } 3942 } 3943 break; 3944 case ISD::FP_ROUND_INREG: 3945 case ISD::SIGN_EXTEND_INREG: { 3946 Tmp1 = LegalizeOp(Node->getOperand(0)); 3947 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3948 3949 // If this operation is not supported, convert it to a shl/shr or load/store 3950 // pair. 3951 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3952 default: assert(0 && "This action not supported for this op yet!"); 3953 case TargetLowering::Legal: 3954 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3955 break; 3956 case TargetLowering::Expand: 3957 // If this is an integer extend and shifts are supported, do that. 3958 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3959 // NOTE: we could fall back on load/store here too for targets without 3960 // SAR. However, it is doubtful that any exist. 3961 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 3962 ExtraVT.getSizeInBits(); 3963 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3964 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3965 Node->getOperand(0), ShiftCst); 3966 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3967 Result, ShiftCst); 3968 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3969 // The only way we can lower this is to turn it into a TRUNCSTORE, 3970 // EXTLOAD pair, targetting a temporary location (a stack slot). 3971 3972 // NOTE: there is a choice here between constantly creating new stack 3973 // slots and always reusing the same one. We currently always create 3974 // new ones, as reuse may inhibit scheduling. 3975 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 3976 Node->getValueType(0)); 3977 } else { 3978 assert(0 && "Unknown op"); 3979 } 3980 break; 3981 } 3982 break; 3983 } 3984 case ISD::TRAMPOLINE: { 3985 SDOperand Ops[6]; 3986 for (unsigned i = 0; i != 6; ++i) 3987 Ops[i] = LegalizeOp(Node->getOperand(i)); 3988 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3989 // The only option for this node is to custom lower it. 3990 Result = TLI.LowerOperation(Result, DAG); 3991 assert(Result.Val && "Should always custom lower!"); 3992 3993 // Since trampoline produces two values, make sure to remember that we 3994 // legalized both of them. 3995 Tmp1 = LegalizeOp(Result.getValue(1)); 3996 Result = LegalizeOp(Result); 3997 AddLegalizedOperand(SDOperand(Node, 0), Result); 3998 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3999 return Op.ResNo ? Tmp1 : Result; 4000 } 4001 case ISD::FLT_ROUNDS_: { 4002 MVT VT = Node->getValueType(0); 4003 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4004 default: assert(0 && "This action not supported for this op yet!"); 4005 case TargetLowering::Custom: 4006 Result = TLI.LowerOperation(Op, DAG); 4007 if (Result.Val) break; 4008 // Fall Thru 4009 case TargetLowering::Legal: 4010 // If this operation is not supported, lower it to constant 1 4011 Result = DAG.getConstant(1, VT); 4012 break; 4013 } 4014 break; 4015 } 4016 case ISD::TRAP: { 4017 MVT VT = Node->getValueType(0); 4018 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4019 default: assert(0 && "This action not supported for this op yet!"); 4020 case TargetLowering::Legal: 4021 Tmp1 = LegalizeOp(Node->getOperand(0)); 4022 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4023 break; 4024 case TargetLowering::Custom: 4025 Result = TLI.LowerOperation(Op, DAG); 4026 if (Result.Val) break; 4027 // Fall Thru 4028 case TargetLowering::Expand: 4029 // If this operation is not supported, lower it to 'abort()' call 4030 Tmp1 = LegalizeOp(Node->getOperand(0)); 4031 TargetLowering::ArgListTy Args; 4032 std::pair<SDOperand,SDOperand> CallResult = 4033 TLI.LowerCallTo(Tmp1, Type::VoidTy, 4034 false, false, false, CallingConv::C, false, 4035 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 4036 Args, DAG); 4037 Result = CallResult.second; 4038 break; 4039 } 4040 break; 4041 } 4042 } 4043 4044 assert(Result.getValueType() == Op.getValueType() && 4045 "Bad legalization!"); 4046 4047 // Make sure that the generated code is itself legal. 4048 if (Result != Op) 4049 Result = LegalizeOp(Result); 4050 4051 // Note that LegalizeOp may be reentered even from single-use nodes, which 4052 // means that we always must cache transformed nodes. 4053 AddLegalizedOperand(Op, Result); 4054 return Result; 4055} 4056 4057/// PromoteOp - Given an operation that produces a value in an invalid type, 4058/// promote it to compute the value into a larger type. The produced value will 4059/// have the correct bits for the low portion of the register, but no guarantee 4060/// is made about the top bits: it may be zero, sign-extended, or garbage. 4061SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 4062 MVT VT = Op.getValueType(); 4063 MVT NVT = TLI.getTypeToTransformTo(VT); 4064 assert(getTypeAction(VT) == Promote && 4065 "Caller should expand or legalize operands that are not promotable!"); 4066 assert(NVT > VT && NVT.isInteger() == VT.isInteger() && 4067 "Cannot promote to smaller type!"); 4068 4069 SDOperand Tmp1, Tmp2, Tmp3; 4070 SDOperand Result; 4071 SDNode *Node = Op.Val; 4072 4073 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 4074 if (I != PromotedNodes.end()) return I->second; 4075 4076 switch (Node->getOpcode()) { 4077 case ISD::CopyFromReg: 4078 assert(0 && "CopyFromReg must be legal!"); 4079 default: 4080#ifndef NDEBUG 4081 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4082#endif 4083 assert(0 && "Do not know how to promote this operator!"); 4084 abort(); 4085 case ISD::UNDEF: 4086 Result = DAG.getNode(ISD::UNDEF, NVT); 4087 break; 4088 case ISD::Constant: 4089 if (VT != MVT::i1) 4090 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 4091 else 4092 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 4093 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4094 break; 4095 case ISD::ConstantFP: 4096 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 4097 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4098 break; 4099 4100 case ISD::SETCC: 4101 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0))) 4102 && "SetCC type is not legal??"); 4103 Result = DAG.getNode(ISD::SETCC, 4104 TLI.getSetCCResultType(Node->getOperand(0)), 4105 Node->getOperand(0), Node->getOperand(1), 4106 Node->getOperand(2)); 4107 break; 4108 4109 case ISD::TRUNCATE: 4110 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4111 case Legal: 4112 Result = LegalizeOp(Node->getOperand(0)); 4113 assert(Result.getValueType() >= NVT && 4114 "This truncation doesn't make sense!"); 4115 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 4116 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 4117 break; 4118 case Promote: 4119 // The truncation is not required, because we don't guarantee anything 4120 // about high bits anyway. 4121 Result = PromoteOp(Node->getOperand(0)); 4122 break; 4123 case Expand: 4124 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4125 // Truncate the low part of the expanded value to the result type 4126 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 4127 } 4128 break; 4129 case ISD::SIGN_EXTEND: 4130 case ISD::ZERO_EXTEND: 4131 case ISD::ANY_EXTEND: 4132 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4133 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4134 case Legal: 4135 // Input is legal? Just do extend all the way to the larger type. 4136 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4137 break; 4138 case Promote: 4139 // Promote the reg if it's smaller. 4140 Result = PromoteOp(Node->getOperand(0)); 4141 // The high bits are not guaranteed to be anything. Insert an extend. 4142 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4143 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4144 DAG.getValueType(Node->getOperand(0).getValueType())); 4145 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4146 Result = DAG.getZeroExtendInReg(Result, 4147 Node->getOperand(0).getValueType()); 4148 break; 4149 } 4150 break; 4151 case ISD::BIT_CONVERT: 4152 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4153 Node->getValueType(0)); 4154 Result = PromoteOp(Result); 4155 break; 4156 4157 case ISD::FP_EXTEND: 4158 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4159 case ISD::FP_ROUND: 4160 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4161 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4162 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4163 case Legal: 4164 if (Node->getConstantOperandVal(1) == 0) { 4165 // Input is legal? Do an FP_ROUND_INREG. 4166 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 4167 DAG.getValueType(VT)); 4168 } else { 4169 // Just remove the truncate, it isn't affecting the value. 4170 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 4171 Node->getOperand(1)); 4172 } 4173 break; 4174 } 4175 break; 4176 case ISD::SINT_TO_FP: 4177 case ISD::UINT_TO_FP: 4178 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4179 case Legal: 4180 // No extra round required here. 4181 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4182 break; 4183 4184 case Promote: 4185 Result = PromoteOp(Node->getOperand(0)); 4186 if (Node->getOpcode() == ISD::SINT_TO_FP) 4187 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4188 Result, 4189 DAG.getValueType(Node->getOperand(0).getValueType())); 4190 else 4191 Result = DAG.getZeroExtendInReg(Result, 4192 Node->getOperand(0).getValueType()); 4193 // No extra round required here. 4194 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 4195 break; 4196 case Expand: 4197 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4198 Node->getOperand(0)); 4199 // Round if we cannot tolerate excess precision. 4200 if (NoExcessFPPrecision) 4201 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4202 DAG.getValueType(VT)); 4203 break; 4204 } 4205 break; 4206 4207 case ISD::SIGN_EXTEND_INREG: 4208 Result = PromoteOp(Node->getOperand(0)); 4209 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4210 Node->getOperand(1)); 4211 break; 4212 case ISD::FP_TO_SINT: 4213 case ISD::FP_TO_UINT: 4214 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4215 case Legal: 4216 case Expand: 4217 Tmp1 = Node->getOperand(0); 4218 break; 4219 case Promote: 4220 // The input result is prerounded, so we don't have to do anything 4221 // special. 4222 Tmp1 = PromoteOp(Node->getOperand(0)); 4223 break; 4224 } 4225 // If we're promoting a UINT to a larger size, check to see if the new node 4226 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4227 // we can use that instead. This allows us to generate better code for 4228 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4229 // legal, such as PowerPC. 4230 if (Node->getOpcode() == ISD::FP_TO_UINT && 4231 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 4232 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 4233 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4234 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 4235 } else { 4236 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4237 } 4238 break; 4239 4240 case ISD::FABS: 4241 case ISD::FNEG: 4242 Tmp1 = PromoteOp(Node->getOperand(0)); 4243 assert(Tmp1.getValueType() == NVT); 4244 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4245 // NOTE: we do not have to do any extra rounding here for 4246 // NoExcessFPPrecision, because we know the input will have the appropriate 4247 // precision, and these operations don't modify precision at all. 4248 break; 4249 4250 case ISD::FSQRT: 4251 case ISD::FSIN: 4252 case ISD::FCOS: 4253 Tmp1 = PromoteOp(Node->getOperand(0)); 4254 assert(Tmp1.getValueType() == NVT); 4255 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4256 if (NoExcessFPPrecision) 4257 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4258 DAG.getValueType(VT)); 4259 break; 4260 4261 case ISD::FPOWI: { 4262 // Promote f32 powi to f64 powi. Note that this could insert a libcall 4263 // directly as well, which may be better. 4264 Tmp1 = PromoteOp(Node->getOperand(0)); 4265 assert(Tmp1.getValueType() == NVT); 4266 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 4267 if (NoExcessFPPrecision) 4268 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4269 DAG.getValueType(VT)); 4270 break; 4271 } 4272 4273 case ISD::ATOMIC_LCS: { 4274 Tmp2 = PromoteOp(Node->getOperand(2)); 4275 Tmp3 = PromoteOp(Node->getOperand(3)); 4276 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0), 4277 Node->getOperand(1), Tmp2, Tmp3, 4278 cast<AtomicSDNode>(Node)->getVT()); 4279 // Remember that we legalized the chain. 4280 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4281 break; 4282 } 4283 case ISD::ATOMIC_LAS: 4284 case ISD::ATOMIC_LSS: 4285 case ISD::ATOMIC_LOAD_AND: 4286 case ISD::ATOMIC_LOAD_OR: 4287 case ISD::ATOMIC_LOAD_XOR: 4288 case ISD::ATOMIC_LOAD_MIN: 4289 case ISD::ATOMIC_LOAD_MAX: 4290 case ISD::ATOMIC_LOAD_UMIN: 4291 case ISD::ATOMIC_LOAD_UMAX: 4292 case ISD::ATOMIC_SWAP: { 4293 Tmp2 = PromoteOp(Node->getOperand(2)); 4294 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0), 4295 Node->getOperand(1), Tmp2, 4296 cast<AtomicSDNode>(Node)->getVT()); 4297 // Remember that we legalized the chain. 4298 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4299 break; 4300 } 4301 4302 case ISD::AND: 4303 case ISD::OR: 4304 case ISD::XOR: 4305 case ISD::ADD: 4306 case ISD::SUB: 4307 case ISD::MUL: 4308 // The input may have strange things in the top bits of the registers, but 4309 // these operations don't care. They may have weird bits going out, but 4310 // that too is okay if they are integer operations. 4311 Tmp1 = PromoteOp(Node->getOperand(0)); 4312 Tmp2 = PromoteOp(Node->getOperand(1)); 4313 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4314 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4315 break; 4316 case ISD::FADD: 4317 case ISD::FSUB: 4318 case ISD::FMUL: 4319 Tmp1 = PromoteOp(Node->getOperand(0)); 4320 Tmp2 = PromoteOp(Node->getOperand(1)); 4321 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4322 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4323 4324 // Floating point operations will give excess precision that we may not be 4325 // able to tolerate. If we DO allow excess precision, just leave it, 4326 // otherwise excise it. 4327 // FIXME: Why would we need to round FP ops more than integer ones? 4328 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4329 if (NoExcessFPPrecision) 4330 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4331 DAG.getValueType(VT)); 4332 break; 4333 4334 case ISD::SDIV: 4335 case ISD::SREM: 4336 // These operators require that their input be sign extended. 4337 Tmp1 = PromoteOp(Node->getOperand(0)); 4338 Tmp2 = PromoteOp(Node->getOperand(1)); 4339 if (NVT.isInteger()) { 4340 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4341 DAG.getValueType(VT)); 4342 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4343 DAG.getValueType(VT)); 4344 } 4345 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4346 4347 // Perform FP_ROUND: this is probably overly pessimistic. 4348 if (NVT.isFloatingPoint() && NoExcessFPPrecision) 4349 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4350 DAG.getValueType(VT)); 4351 break; 4352 case ISD::FDIV: 4353 case ISD::FREM: 4354 case ISD::FCOPYSIGN: 4355 // These operators require that their input be fp extended. 4356 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4357 case Expand: assert(0 && "not implemented"); 4358 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4359 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4360 } 4361 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4362 case Expand: assert(0 && "not implemented"); 4363 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4364 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4365 } 4366 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4367 4368 // Perform FP_ROUND: this is probably overly pessimistic. 4369 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4370 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4371 DAG.getValueType(VT)); 4372 break; 4373 4374 case ISD::UDIV: 4375 case ISD::UREM: 4376 // These operators require that their input be zero extended. 4377 Tmp1 = PromoteOp(Node->getOperand(0)); 4378 Tmp2 = PromoteOp(Node->getOperand(1)); 4379 assert(NVT.isInteger() && "Operators don't apply to FP!"); 4380 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4381 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4382 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4383 break; 4384 4385 case ISD::SHL: 4386 Tmp1 = PromoteOp(Node->getOperand(0)); 4387 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4388 break; 4389 case ISD::SRA: 4390 // The input value must be properly sign extended. 4391 Tmp1 = PromoteOp(Node->getOperand(0)); 4392 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4393 DAG.getValueType(VT)); 4394 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4395 break; 4396 case ISD::SRL: 4397 // The input value must be properly zero extended. 4398 Tmp1 = PromoteOp(Node->getOperand(0)); 4399 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4400 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4401 break; 4402 4403 case ISD::VAARG: 4404 Tmp1 = Node->getOperand(0); // Get the chain. 4405 Tmp2 = Node->getOperand(1); // Get the pointer. 4406 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4407 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4408 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 4409 } else { 4410 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4411 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 4412 // Increment the pointer, VAList, to the next vaarg 4413 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4414 DAG.getConstant(VT.getSizeInBits()/8, 4415 TLI.getPointerTy())); 4416 // Store the incremented VAList to the legalized pointer 4417 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 4418 // Load the actual argument out of the pointer VAList 4419 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4420 } 4421 // Remember that we legalized the chain. 4422 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4423 break; 4424 4425 case ISD::LOAD: { 4426 LoadSDNode *LD = cast<LoadSDNode>(Node); 4427 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4428 ? ISD::EXTLOAD : LD->getExtensionType(); 4429 Result = DAG.getExtLoad(ExtType, NVT, 4430 LD->getChain(), LD->getBasePtr(), 4431 LD->getSrcValue(), LD->getSrcValueOffset(), 4432 LD->getMemoryVT(), 4433 LD->isVolatile(), 4434 LD->getAlignment()); 4435 // Remember that we legalized the chain. 4436 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4437 break; 4438 } 4439 case ISD::SELECT: { 4440 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4441 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4442 4443 MVT VT2 = Tmp2.getValueType(); 4444 assert(VT2 == Tmp3.getValueType() 4445 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); 4446 // Ensure that the resulting node is at least the same size as the operands' 4447 // value types, because we cannot assume that TLI.getSetCCValueType() is 4448 // constant. 4449 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3); 4450 break; 4451 } 4452 case ISD::SELECT_CC: 4453 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4454 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4455 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4456 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4457 break; 4458 case ISD::BSWAP: 4459 Tmp1 = Node->getOperand(0); 4460 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4461 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4462 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4463 DAG.getConstant(NVT.getSizeInBits() - 4464 VT.getSizeInBits(), 4465 TLI.getShiftAmountTy())); 4466 break; 4467 case ISD::CTPOP: 4468 case ISD::CTTZ: 4469 case ISD::CTLZ: 4470 // Zero extend the argument 4471 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4472 // Perform the larger operation, then subtract if needed. 4473 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4474 switch(Node->getOpcode()) { 4475 case ISD::CTPOP: 4476 Result = Tmp1; 4477 break; 4478 case ISD::CTTZ: 4479 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4480 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 4481 DAG.getConstant(NVT.getSizeInBits(), NVT), 4482 ISD::SETEQ); 4483 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4484 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); 4485 break; 4486 case ISD::CTLZ: 4487 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4488 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4489 DAG.getConstant(NVT.getSizeInBits() - 4490 VT.getSizeInBits(), NVT)); 4491 break; 4492 } 4493 break; 4494 case ISD::EXTRACT_SUBVECTOR: 4495 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4496 break; 4497 case ISD::EXTRACT_VECTOR_ELT: 4498 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4499 break; 4500 } 4501 4502 assert(Result.Val && "Didn't set a result!"); 4503 4504 // Make sure the result is itself legal. 4505 Result = LegalizeOp(Result); 4506 4507 // Remember that we promoted this! 4508 AddPromotedOperand(Op, Result); 4509 return Result; 4510} 4511 4512/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4513/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4514/// based on the vector type. The return type of this matches the element type 4515/// of the vector, which may not be legal for the target. 4516SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 4517 // We know that operand #0 is the Vec vector. If the index is a constant 4518 // or if the invec is a supported hardware type, we can use it. Otherwise, 4519 // lower to a store then an indexed load. 4520 SDOperand Vec = Op.getOperand(0); 4521 SDOperand Idx = Op.getOperand(1); 4522 4523 MVT TVT = Vec.getValueType(); 4524 unsigned NumElems = TVT.getVectorNumElements(); 4525 4526 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4527 default: assert(0 && "This action is not supported yet!"); 4528 case TargetLowering::Custom: { 4529 Vec = LegalizeOp(Vec); 4530 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4531 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 4532 if (Tmp3.Val) 4533 return Tmp3; 4534 break; 4535 } 4536 case TargetLowering::Legal: 4537 if (isTypeLegal(TVT)) { 4538 Vec = LegalizeOp(Vec); 4539 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4540 return Op; 4541 } 4542 break; 4543 case TargetLowering::Expand: 4544 break; 4545 } 4546 4547 if (NumElems == 1) { 4548 // This must be an access of the only element. Return it. 4549 Op = ScalarizeVectorOp(Vec); 4550 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4551 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 4552 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4553 SDOperand Lo, Hi; 4554 SplitVectorOp(Vec, Lo, Hi); 4555 if (CIdx->getValue() < NumLoElts) { 4556 Vec = Lo; 4557 } else { 4558 Vec = Hi; 4559 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts, 4560 Idx.getValueType()); 4561 } 4562 4563 // It's now an extract from the appropriate high or low part. Recurse. 4564 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4565 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4566 } else { 4567 // Store the value to a temporary stack slot, then LOAD the scalar 4568 // element back out. 4569 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4570 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4571 4572 // Add the offset to the index. 4573 unsigned EltSize = Op.getValueType().getSizeInBits()/8; 4574 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4575 DAG.getConstant(EltSize, Idx.getValueType())); 4576 4577 if (Idx.getValueType().getSizeInBits() > TLI.getPointerTy().getSizeInBits()) 4578 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4579 else 4580 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4581 4582 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4583 4584 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4585 } 4586 return Op; 4587} 4588 4589/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4590/// we assume the operation can be split if it is not already legal. 4591SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 4592 // We know that operand #0 is the Vec vector. For now we assume the index 4593 // is a constant and that the extracted result is a supported hardware type. 4594 SDOperand Vec = Op.getOperand(0); 4595 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 4596 4597 unsigned NumElems = Vec.getValueType().getVectorNumElements(); 4598 4599 if (NumElems == Op.getValueType().getVectorNumElements()) { 4600 // This must be an access of the desired vector length. Return it. 4601 return Vec; 4602 } 4603 4604 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4605 SDOperand Lo, Hi; 4606 SplitVectorOp(Vec, Lo, Hi); 4607 if (CIdx->getValue() < NumElems/2) { 4608 Vec = Lo; 4609 } else { 4610 Vec = Hi; 4611 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4612 } 4613 4614 // It's now an extract from the appropriate high or low part. Recurse. 4615 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4616 return ExpandEXTRACT_SUBVECTOR(Op); 4617} 4618 4619/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4620/// with condition CC on the current target. This usually involves legalizing 4621/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4622/// there may be no choice but to create a new SetCC node to represent the 4623/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4624/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 4625void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 4626 SDOperand &RHS, 4627 SDOperand &CC) { 4628 SDOperand Tmp1, Tmp2, Tmp3, Result; 4629 4630 switch (getTypeAction(LHS.getValueType())) { 4631 case Legal: 4632 Tmp1 = LegalizeOp(LHS); // LHS 4633 Tmp2 = LegalizeOp(RHS); // RHS 4634 break; 4635 case Promote: 4636 Tmp1 = PromoteOp(LHS); // LHS 4637 Tmp2 = PromoteOp(RHS); // RHS 4638 4639 // If this is an FP compare, the operands have already been extended. 4640 if (LHS.getValueType().isInteger()) { 4641 MVT VT = LHS.getValueType(); 4642 MVT NVT = TLI.getTypeToTransformTo(VT); 4643 4644 // Otherwise, we have to insert explicit sign or zero extends. Note 4645 // that we could insert sign extends for ALL conditions, but zero extend 4646 // is cheaper on many machines (an AND instead of two shifts), so prefer 4647 // it. 4648 switch (cast<CondCodeSDNode>(CC)->get()) { 4649 default: assert(0 && "Unknown integer comparison!"); 4650 case ISD::SETEQ: 4651 case ISD::SETNE: 4652 case ISD::SETUGE: 4653 case ISD::SETUGT: 4654 case ISD::SETULE: 4655 case ISD::SETULT: 4656 // ALL of these operations will work if we either sign or zero extend 4657 // the operands (including the unsigned comparisons!). Zero extend is 4658 // usually a simpler/cheaper operation, so prefer it. 4659 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4660 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4661 break; 4662 case ISD::SETGE: 4663 case ISD::SETGT: 4664 case ISD::SETLT: 4665 case ISD::SETLE: 4666 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4667 DAG.getValueType(VT)); 4668 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4669 DAG.getValueType(VT)); 4670 break; 4671 } 4672 } 4673 break; 4674 case Expand: { 4675 MVT VT = LHS.getValueType(); 4676 if (VT == MVT::f32 || VT == MVT::f64) { 4677 // Expand into one or more soft-fp libcall(s). 4678 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 4679 switch (cast<CondCodeSDNode>(CC)->get()) { 4680 case ISD::SETEQ: 4681 case ISD::SETOEQ: 4682 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4683 break; 4684 case ISD::SETNE: 4685 case ISD::SETUNE: 4686 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4687 break; 4688 case ISD::SETGE: 4689 case ISD::SETOGE: 4690 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4691 break; 4692 case ISD::SETLT: 4693 case ISD::SETOLT: 4694 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4695 break; 4696 case ISD::SETLE: 4697 case ISD::SETOLE: 4698 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4699 break; 4700 case ISD::SETGT: 4701 case ISD::SETOGT: 4702 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4703 break; 4704 case ISD::SETUO: 4705 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4706 break; 4707 case ISD::SETO: 4708 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4709 break; 4710 default: 4711 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4712 switch (cast<CondCodeSDNode>(CC)->get()) { 4713 case ISD::SETONE: 4714 // SETONE = SETOLT | SETOGT 4715 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4716 // Fallthrough 4717 case ISD::SETUGT: 4718 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4719 break; 4720 case ISD::SETUGE: 4721 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4722 break; 4723 case ISD::SETULT: 4724 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4725 break; 4726 case ISD::SETULE: 4727 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4728 break; 4729 case ISD::SETUEQ: 4730 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4731 break; 4732 default: assert(0 && "Unsupported FP setcc!"); 4733 } 4734 } 4735 4736 SDOperand Dummy; 4737 Tmp1 = ExpandLibCall(LC1, 4738 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4739 false /*sign irrelevant*/, Dummy); 4740 Tmp2 = DAG.getConstant(0, MVT::i32); 4741 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4742 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4743 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 4744 CC); 4745 LHS = ExpandLibCall(LC2, 4746 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4747 false /*sign irrelevant*/, Dummy); 4748 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2, 4749 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4750 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4751 Tmp2 = SDOperand(); 4752 } 4753 LHS = Tmp1; 4754 RHS = Tmp2; 4755 return; 4756 } 4757 4758 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4759 ExpandOp(LHS, LHSLo, LHSHi); 4760 ExpandOp(RHS, RHSLo, RHSHi); 4761 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4762 4763 if (VT==MVT::ppcf128) { 4764 // FIXME: This generated code sucks. We want to generate 4765 // FCMP crN, hi1, hi2 4766 // BNE crN, L: 4767 // FCMP crN, lo1, lo2 4768 // The following can be improved, but not that much. 4769 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ); 4770 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode); 4771 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4772 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE); 4773 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode); 4774 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4775 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4776 Tmp2 = SDOperand(); 4777 break; 4778 } 4779 4780 switch (CCCode) { 4781 case ISD::SETEQ: 4782 case ISD::SETNE: 4783 if (RHSLo == RHSHi) 4784 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4785 if (RHSCST->isAllOnesValue()) { 4786 // Comparison to -1. 4787 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4788 Tmp2 = RHSLo; 4789 break; 4790 } 4791 4792 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4793 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4794 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4795 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4796 break; 4797 default: 4798 // If this is a comparison of the sign bit, just look at the top part. 4799 // X > -1, x < 0 4800 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4801 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4802 CST->isNullValue()) || // X < 0 4803 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4804 CST->isAllOnesValue())) { // X > -1 4805 Tmp1 = LHSHi; 4806 Tmp2 = RHSHi; 4807 break; 4808 } 4809 4810 // FIXME: This generated code sucks. 4811 ISD::CondCode LowCC; 4812 switch (CCCode) { 4813 default: assert(0 && "Unknown integer setcc!"); 4814 case ISD::SETLT: 4815 case ISD::SETULT: LowCC = ISD::SETULT; break; 4816 case ISD::SETGT: 4817 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4818 case ISD::SETLE: 4819 case ISD::SETULE: LowCC = ISD::SETULE; break; 4820 case ISD::SETGE: 4821 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4822 } 4823 4824 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4825 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4826 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4827 4828 // NOTE: on targets without efficient SELECT of bools, we can always use 4829 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4830 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4831 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, 4832 LowCC, false, DagCombineInfo); 4833 if (!Tmp1.Val) 4834 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 4835 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4836 CCCode, false, DagCombineInfo); 4837 if (!Tmp2.Val) 4838 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, 4839 RHSHi,CC); 4840 4841 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4842 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4843 if ((Tmp1C && Tmp1C->isNullValue()) || 4844 (Tmp2C && Tmp2C->isNullValue() && 4845 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4846 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4847 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 4848 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4849 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4850 // low part is known false, returns high part. 4851 // For LE / GE, if high part is known false, ignore the low part. 4852 // For LT / GT, if high part is known true, ignore the low part. 4853 Tmp1 = Tmp2; 4854 Tmp2 = SDOperand(); 4855 } else { 4856 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4857 ISD::SETEQ, false, DagCombineInfo); 4858 if (!Result.Val) 4859 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4860 ISD::SETEQ); 4861 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4862 Result, Tmp1, Tmp2)); 4863 Tmp1 = Result; 4864 Tmp2 = SDOperand(); 4865 } 4866 } 4867 } 4868 } 4869 LHS = Tmp1; 4870 RHS = Tmp2; 4871} 4872 4873/// EmitStackConvert - Emit a store/load combination to the stack. This stores 4874/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 4875/// a load from the stack slot to DestVT, extending it if needed. 4876/// The resultant code need not be legal. 4877SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, 4878 MVT SlotVT, 4879 MVT DestVT) { 4880 // Create the stack frame object. 4881 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); 4882 4883 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 4884 int SPFI = StackPtrFI->getIndex(); 4885 4886 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 4887 unsigned SlotSize = SlotVT.getSizeInBits(); 4888 unsigned DestSize = DestVT.getSizeInBits(); 4889 4890 // Emit a store to the stack slot. Use a truncstore if the input value is 4891 // later than DestVT. 4892 SDOperand Store; 4893 if (SrcSize > SlotSize) 4894 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, 4895 PseudoSourceValue::getFixedStack(), 4896 SPFI, SlotVT); 4897 else { 4898 assert(SrcSize == SlotSize && "Invalid store"); 4899 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, 4900 PseudoSourceValue::getFixedStack(), 4901 SPFI); 4902 } 4903 4904 // Result is a load from the stack slot. 4905 if (SlotSize == DestSize) 4906 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4907 4908 assert(SlotSize < DestSize && "Unknown extension!"); 4909 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT); 4910} 4911 4912SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4913 // Create a vector sized/aligned stack slot, store the value to element #0, 4914 // then load the whole vector back out. 4915 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4916 4917 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 4918 int SPFI = StackPtrFI->getIndex(); 4919 4920 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4921 PseudoSourceValue::getFixedStack(), SPFI); 4922 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, 4923 PseudoSourceValue::getFixedStack(), SPFI); 4924} 4925 4926 4927/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4928/// support the operation, but do support the resultant vector type. 4929SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4930 4931 // If the only non-undef value is the low element, turn this into a 4932 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4933 unsigned NumElems = Node->getNumOperands(); 4934 bool isOnlyLowElement = true; 4935 SDOperand SplatValue = Node->getOperand(0); 4936 4937 // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t> 4938 // and use a bitmask instead of a list of elements. 4939 std::map<SDOperand, std::vector<unsigned> > Values; 4940 Values[SplatValue].push_back(0); 4941 bool isConstant = true; 4942 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4943 SplatValue.getOpcode() != ISD::UNDEF) 4944 isConstant = false; 4945 4946 for (unsigned i = 1; i < NumElems; ++i) { 4947 SDOperand V = Node->getOperand(i); 4948 Values[V].push_back(i); 4949 if (V.getOpcode() != ISD::UNDEF) 4950 isOnlyLowElement = false; 4951 if (SplatValue != V) 4952 SplatValue = SDOperand(0,0); 4953 4954 // If this isn't a constant element or an undef, we can't use a constant 4955 // pool load. 4956 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4957 V.getOpcode() != ISD::UNDEF) 4958 isConstant = false; 4959 } 4960 4961 if (isOnlyLowElement) { 4962 // If the low element is an undef too, then this whole things is an undef. 4963 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4964 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4965 // Otherwise, turn this into a scalar_to_vector node. 4966 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4967 Node->getOperand(0)); 4968 } 4969 4970 // If all elements are constants, create a load from the constant pool. 4971 if (isConstant) { 4972 MVT VT = Node->getValueType(0); 4973 std::vector<Constant*> CV; 4974 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4975 if (ConstantFPSDNode *V = 4976 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4977 CV.push_back(ConstantFP::get(V->getValueAPF())); 4978 } else if (ConstantSDNode *V = 4979 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4980 CV.push_back(ConstantInt::get(V->getAPIntValue())); 4981 } else { 4982 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4983 const Type *OpNTy = 4984 Node->getOperand(0).getValueType().getTypeForMVT(); 4985 CV.push_back(UndefValue::get(OpNTy)); 4986 } 4987 } 4988 Constant *CP = ConstantVector::get(CV); 4989 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4990 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4991 PseudoSourceValue::getConstantPool(), 0); 4992 } 4993 4994 if (SplatValue.Val) { // Splat of one value? 4995 // Build the shuffle constant vector: <0, 0, 0, 0> 4996 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 4997 SDOperand Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); 4998 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4999 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5000 &ZeroVec[0], ZeroVec.size()); 5001 5002 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 5003 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 5004 // Get the splatted value into the low element of a vector register. 5005 SDOperand LowValVec = 5006 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 5007 5008 // Return shuffle(LowValVec, undef, <0,0,0,0>) 5009 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 5010 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 5011 SplatMask); 5012 } 5013 } 5014 5015 // If there are only two unique elements, we may be able to turn this into a 5016 // vector shuffle. 5017 if (Values.size() == 2) { 5018 // Get the two values in deterministic order. 5019 SDOperand Val1 = Node->getOperand(1); 5020 SDOperand Val2; 5021 std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin(); 5022 if (MI->first != Val1) 5023 Val2 = MI->first; 5024 else 5025 Val2 = (++MI)->first; 5026 5027 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our 5028 // vector shuffle has the undef vector on the RHS. 5029 if (Val1.getOpcode() == ISD::UNDEF) 5030 std::swap(Val1, Val2); 5031 5032 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 5033 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5034 MVT MaskEltVT = MaskVT.getVectorElementType(); 5035 std::vector<SDOperand> MaskVec(NumElems); 5036 5037 // Set elements of the shuffle mask for Val1. 5038 std::vector<unsigned> &Val1Elts = Values[Val1]; 5039 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 5040 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT); 5041 5042 // Set elements of the shuffle mask for Val2. 5043 std::vector<unsigned> &Val2Elts = Values[Val2]; 5044 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 5045 if (Val2.getOpcode() != ISD::UNDEF) 5046 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); 5047 else 5048 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); 5049 5050 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5051 &MaskVec[0], MaskVec.size()); 5052 5053 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 5054 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 5055 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 5056 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); 5057 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); 5058 SDOperand Ops[] = { Val1, Val2, ShuffleMask }; 5059 5060 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 5061 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); 5062 } 5063 } 5064 5065 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5066 // aligned object on the stack, store each element into it, then load 5067 // the result as a vector. 5068 MVT VT = Node->getValueType(0); 5069 // Create the stack frame object. 5070 SDOperand FIPtr = DAG.CreateStackTemporary(VT); 5071 5072 // Emit a store of each element to the stack slot. 5073 SmallVector<SDOperand, 8> Stores; 5074 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8; 5075 // Store (in the right endianness) the elements to memory. 5076 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5077 // Ignore undef elements. 5078 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5079 5080 unsigned Offset = TypeByteSize*i; 5081 5082 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5083 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 5084 5085 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 5086 NULL, 0)); 5087 } 5088 5089 SDOperand StoreChain; 5090 if (!Stores.empty()) // Not all undef elements? 5091 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5092 &Stores[0], Stores.size()); 5093 else 5094 StoreChain = DAG.getEntryNode(); 5095 5096 // Result is a load from the stack slot. 5097 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 5098} 5099 5100void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5101 SDOperand Op, SDOperand Amt, 5102 SDOperand &Lo, SDOperand &Hi) { 5103 // Expand the subcomponents. 5104 SDOperand LHSL, LHSH; 5105 ExpandOp(Op, LHSL, LHSH); 5106 5107 SDOperand Ops[] = { LHSL, LHSH, Amt }; 5108 MVT VT = LHSL.getValueType(); 5109 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5110 Hi = Lo.getValue(1); 5111} 5112 5113 5114/// ExpandShift - Try to find a clever way to expand this shift operation out to 5115/// smaller elements. If we can't find a way that is more efficient than a 5116/// libcall on this target, return false. Otherwise, return true with the 5117/// low-parts expanded into Lo and Hi. 5118bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 5119 SDOperand &Lo, SDOperand &Hi) { 5120 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5121 "This is not a shift!"); 5122 5123 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5124 SDOperand ShAmt = LegalizeOp(Amt); 5125 MVT ShTy = ShAmt.getValueType(); 5126 unsigned ShBits = ShTy.getSizeInBits(); 5127 unsigned VTBits = Op.getValueType().getSizeInBits(); 5128 unsigned NVTBits = NVT.getSizeInBits(); 5129 5130 // Handle the case when Amt is an immediate. 5131 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 5132 unsigned Cst = CN->getValue(); 5133 // Expand the incoming operand to be shifted, so that we have its parts 5134 SDOperand InL, InH; 5135 ExpandOp(Op, InL, InH); 5136 switch(Opc) { 5137 case ISD::SHL: 5138 if (Cst > VTBits) { 5139 Lo = DAG.getConstant(0, NVT); 5140 Hi = DAG.getConstant(0, NVT); 5141 } else if (Cst > NVTBits) { 5142 Lo = DAG.getConstant(0, NVT); 5143 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5144 } else if (Cst == NVTBits) { 5145 Lo = DAG.getConstant(0, NVT); 5146 Hi = InL; 5147 } else { 5148 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 5149 Hi = DAG.getNode(ISD::OR, NVT, 5150 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 5151 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 5152 } 5153 return true; 5154 case ISD::SRL: 5155 if (Cst > VTBits) { 5156 Lo = DAG.getConstant(0, NVT); 5157 Hi = DAG.getConstant(0, NVT); 5158 } else if (Cst > NVTBits) { 5159 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5160 Hi = DAG.getConstant(0, NVT); 5161 } else if (Cst == NVTBits) { 5162 Lo = InH; 5163 Hi = DAG.getConstant(0, NVT); 5164 } else { 5165 Lo = DAG.getNode(ISD::OR, NVT, 5166 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5167 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5168 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 5169 } 5170 return true; 5171 case ISD::SRA: 5172 if (Cst > VTBits) { 5173 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 5174 DAG.getConstant(NVTBits-1, ShTy)); 5175 } else if (Cst > NVTBits) { 5176 Lo = DAG.getNode(ISD::SRA, NVT, InH, 5177 DAG.getConstant(Cst-NVTBits, ShTy)); 5178 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5179 DAG.getConstant(NVTBits-1, ShTy)); 5180 } else if (Cst == NVTBits) { 5181 Lo = InH; 5182 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5183 DAG.getConstant(NVTBits-1, ShTy)); 5184 } else { 5185 Lo = DAG.getNode(ISD::OR, NVT, 5186 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5187 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5188 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 5189 } 5190 return true; 5191 } 5192 } 5193 5194 // Okay, the shift amount isn't constant. However, if we can tell that it is 5195 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5196 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5197 APInt KnownZero, KnownOne; 5198 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5199 5200 // If we know that if any of the high bits of the shift amount are one, then 5201 // we can do this as a couple of simple shifts. 5202 if (KnownOne.intersects(Mask)) { 5203 // Mask out the high bit, which we know is set. 5204 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 5205 DAG.getConstant(~Mask, Amt.getValueType())); 5206 5207 // Expand the incoming operand to be shifted, so that we have its parts 5208 SDOperand InL, InH; 5209 ExpandOp(Op, InL, InH); 5210 switch(Opc) { 5211 case ISD::SHL: 5212 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5213 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 5214 return true; 5215 case ISD::SRL: 5216 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5217 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 5218 return true; 5219 case ISD::SRA: 5220 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 5221 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5222 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 5223 return true; 5224 } 5225 } 5226 5227 // If we know that the high bits of the shift amount are all zero, then we can 5228 // do this as a couple of simple shifts. 5229 if ((KnownZero & Mask) == Mask) { 5230 // Compute 32-amt. 5231 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 5232 DAG.getConstant(NVTBits, Amt.getValueType()), 5233 Amt); 5234 5235 // Expand the incoming operand to be shifted, so that we have its parts 5236 SDOperand InL, InH; 5237 ExpandOp(Op, InL, InH); 5238 switch(Opc) { 5239 case ISD::SHL: 5240 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 5241 Hi = DAG.getNode(ISD::OR, NVT, 5242 DAG.getNode(ISD::SHL, NVT, InH, Amt), 5243 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 5244 return true; 5245 case ISD::SRL: 5246 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 5247 Lo = DAG.getNode(ISD::OR, NVT, 5248 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5249 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5250 return true; 5251 case ISD::SRA: 5252 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 5253 Lo = DAG.getNode(ISD::OR, NVT, 5254 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5255 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5256 return true; 5257 } 5258 } 5259 5260 return false; 5261} 5262 5263 5264// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5265// does not fit into a register, return the lo part and set the hi part to the 5266// by-reg argument. If it does fit into a single register, return the result 5267// and leave the Hi part unset. 5268SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 5269 bool isSigned, SDOperand &Hi) { 5270 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5271 // The input chain to this libcall is the entry node of the function. 5272 // Legalizing the call will automatically add the previous call to the 5273 // dependence. 5274 SDOperand InChain = DAG.getEntryNode(); 5275 5276 TargetLowering::ArgListTy Args; 5277 TargetLowering::ArgListEntry Entry; 5278 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5279 MVT ArgVT = Node->getOperand(i).getValueType(); 5280 const Type *ArgTy = ArgVT.getTypeForMVT(); 5281 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5282 Entry.isSExt = isSigned; 5283 Entry.isZExt = !isSigned; 5284 Args.push_back(Entry); 5285 } 5286 SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 5287 TLI.getPointerTy()); 5288 5289 // Splice the libcall in wherever FindInputOutputChains tells us to. 5290 const Type *RetTy = Node->getValueType(0).getTypeForMVT(); 5291 std::pair<SDOperand,SDOperand> CallInfo = 5292 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C, 5293 false, Callee, Args, DAG); 5294 5295 // Legalize the call sequence, starting with the chain. This will advance 5296 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5297 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5298 LegalizeOp(CallInfo.second); 5299 SDOperand Result; 5300 switch (getTypeAction(CallInfo.first.getValueType())) { 5301 default: assert(0 && "Unknown thing"); 5302 case Legal: 5303 Result = CallInfo.first; 5304 break; 5305 case Expand: 5306 ExpandOp(CallInfo.first, Result, Hi); 5307 break; 5308 } 5309 return Result; 5310} 5311 5312 5313/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5314/// 5315SDOperand SelectionDAGLegalize:: 5316ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source) { 5317 MVT SourceVT = Source.getValueType(); 5318 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5319 5320 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. 5321 if (!isSigned && SourceVT != MVT::i32) { 5322 // The integer value loaded will be incorrectly if the 'sign bit' of the 5323 // incoming integer is set. To handle this, we dynamically test to see if 5324 // it is set, and, if so, add a fudge factor. 5325 SDOperand Hi; 5326 if (ExpandSource) { 5327 SDOperand Lo; 5328 ExpandOp(Source, Lo, Hi); 5329 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi); 5330 } else { 5331 // The comparison for the sign bit will use the entire operand. 5332 Hi = Source; 5333 } 5334 5335 // If this is unsigned, and not supported, first perform the conversion to 5336 // signed, then adjust the result if the sign bit is set. 5337 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source); 5338 5339 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 5340 DAG.getConstant(0, Hi.getValueType()), 5341 ISD::SETLT); 5342 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5343 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5344 SignSet, Four, Zero); 5345 uint64_t FF = 0x5f800000ULL; 5346 if (TLI.isLittleEndian()) FF <<= 32; 5347 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5348 5349 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5350 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5351 SDOperand FudgeInReg; 5352 if (DestTy == MVT::f32) 5353 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5354 PseudoSourceValue::getConstantPool(), 0); 5355 else if (DestTy.getSizeInBits() > MVT(MVT::f32).getSizeInBits()) 5356 // FIXME: Avoid the extend by construction the right constantpool? 5357 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5358 CPIdx, 5359 PseudoSourceValue::getConstantPool(), 0, 5360 MVT::f32); 5361 else 5362 assert(0 && "Unexpected conversion"); 5363 5364 MVT SCVT = SignedConv.getValueType(); 5365 if (SCVT != DestTy) { 5366 // Destination type needs to be expanded as well. The FADD now we are 5367 // constructing will be expanded into a libcall. 5368 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { 5369 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); 5370 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, 5371 SignedConv, SignedConv.getValue(1)); 5372 } 5373 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5374 } 5375 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5376 } 5377 5378 // Check to see if the target has a custom way to lower this. If so, use it. 5379 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 5380 default: assert(0 && "This action not implemented for this operation!"); 5381 case TargetLowering::Legal: 5382 case TargetLowering::Expand: 5383 break; // This case is handled below. 5384 case TargetLowering::Custom: { 5385 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5386 Source), DAG); 5387 if (NV.Val) 5388 return LegalizeOp(NV); 5389 break; // The target decided this was legal after all 5390 } 5391 } 5392 5393 // Expand the source, then glue it back together for the call. We must expand 5394 // the source in case it is shared (this pass of legalize must traverse it). 5395 if (ExpandSource) { 5396 SDOperand SrcLo, SrcHi; 5397 ExpandOp(Source, SrcLo, SrcHi); 5398 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); 5399 } 5400 5401 RTLIB::Libcall LC; 5402 if (SourceVT == MVT::i32) { 5403 if (DestTy == MVT::f32) 5404 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 5405 else { 5406 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 5407 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 5408 } 5409 } else if (SourceVT == MVT::i64) { 5410 if (DestTy == MVT::f32) 5411 LC = RTLIB::SINTTOFP_I64_F32; 5412 else if (DestTy == MVT::f64) 5413 LC = RTLIB::SINTTOFP_I64_F64; 5414 else if (DestTy == MVT::f80) 5415 LC = RTLIB::SINTTOFP_I64_F80; 5416 else { 5417 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 5418 LC = RTLIB::SINTTOFP_I64_PPCF128; 5419 } 5420 } else if (SourceVT == MVT::i128) { 5421 if (DestTy == MVT::f32) 5422 LC = RTLIB::SINTTOFP_I128_F32; 5423 else if (DestTy == MVT::f64) 5424 LC = RTLIB::SINTTOFP_I128_F64; 5425 else if (DestTy == MVT::f80) 5426 LC = RTLIB::SINTTOFP_I128_F80; 5427 else { 5428 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 5429 LC = RTLIB::SINTTOFP_I128_PPCF128; 5430 } 5431 } else { 5432 assert(0 && "Unknown int value type"); 5433 } 5434 5435 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 5436 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5437 SDOperand HiPart; 5438 SDOperand Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart); 5439 if (Result.getValueType() != DestTy && HiPart.Val) 5440 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart); 5441 return Result; 5442} 5443 5444/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5445/// INT_TO_FP operation of the specified operand when the target requests that 5446/// we expand it. At this point, we know that the result and operand types are 5447/// legal for the target. 5448SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5449 SDOperand Op0, 5450 MVT DestVT) { 5451 if (Op0.getValueType() == MVT::i32) { 5452 // simple 32-bit [signed|unsigned] integer to float/double expansion 5453 5454 // Get the stack frame index of a 8 byte buffer. 5455 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64); 5456 5457 // word offset constant for Hi/Lo address computation 5458 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5459 // set up Hi and Lo (into buffer) address based on endian 5460 SDOperand Hi = StackSlot; 5461 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5462 if (TLI.isLittleEndian()) 5463 std::swap(Hi, Lo); 5464 5465 // if signed map to unsigned space 5466 SDOperand Op0Mapped; 5467 if (isSigned) { 5468 // constant used to invert sign bit (signed to unsigned mapping) 5469 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5470 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5471 } else { 5472 Op0Mapped = Op0; 5473 } 5474 // store the lo of the constructed double - based on integer input 5475 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 5476 Op0Mapped, Lo, NULL, 0); 5477 // initial hi portion of constructed double 5478 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5479 // store the hi of the constructed double - biased exponent 5480 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5481 // load the constructed double 5482 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5483 // FP constant to bias correct the final result 5484 SDOperand Bias = DAG.getConstantFP(isSigned ? 5485 BitsToDouble(0x4330000080000000ULL) 5486 : BitsToDouble(0x4330000000000000ULL), 5487 MVT::f64); 5488 // subtract the bias 5489 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5490 // final result 5491 SDOperand Result; 5492 // handle final rounding 5493 if (DestVT == MVT::f64) { 5494 // do nothing 5495 Result = Sub; 5496 } else if (DestVT.getSizeInBits() < 5497 MVT(MVT::f64).getSizeInBits()) { 5498 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 5499 DAG.getIntPtrConstant(0)); 5500 } else if (DestVT.getSizeInBits() > 5501 MVT(MVT::f64).getSizeInBits()) { 5502 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5503 } 5504 return Result; 5505 } 5506 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5507 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5508 5509 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0, 5510 DAG.getConstant(0, Op0.getValueType()), 5511 ISD::SETLT); 5512 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5513 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5514 SignSet, Four, Zero); 5515 5516 // If the sign bit of the integer is set, the large number will be treated 5517 // as a negative number. To counteract this, the dynamic code adds an 5518 // offset depending on the data type. 5519 uint64_t FF; 5520 switch (Op0.getValueType().getSimpleVT()) { 5521 default: assert(0 && "Unsupported integer type!"); 5522 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5523 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5524 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5525 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5526 } 5527 if (TLI.isLittleEndian()) FF <<= 32; 5528 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5529 5530 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5531 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5532 SDOperand FudgeInReg; 5533 if (DestVT == MVT::f32) 5534 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5535 PseudoSourceValue::getConstantPool(), 0); 5536 else { 5537 FudgeInReg = 5538 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5539 DAG.getEntryNode(), CPIdx, 5540 PseudoSourceValue::getConstantPool(), 0, 5541 MVT::f32)); 5542 } 5543 5544 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5545} 5546 5547/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5548/// *INT_TO_FP operation of the specified operand when the target requests that 5549/// we promote it. At this point, we know that the result and operand types are 5550/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5551/// operation that takes a larger input. 5552SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 5553 MVT DestVT, 5554 bool isSigned) { 5555 // First step, figure out the appropriate *INT_TO_FP operation to use. 5556 MVT NewInTy = LegalOp.getValueType(); 5557 5558 unsigned OpToUse = 0; 5559 5560 // Scan for the appropriate larger type to use. 5561 while (1) { 5562 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 5563 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 5564 5565 // If the target supports SINT_TO_FP of this type, use it. 5566 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5567 default: break; 5568 case TargetLowering::Legal: 5569 if (!TLI.isTypeLegal(NewInTy)) 5570 break; // Can't use this datatype. 5571 // FALL THROUGH. 5572 case TargetLowering::Custom: 5573 OpToUse = ISD::SINT_TO_FP; 5574 break; 5575 } 5576 if (OpToUse) break; 5577 if (isSigned) continue; 5578 5579 // If the target supports UINT_TO_FP of this type, use it. 5580 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5581 default: break; 5582 case TargetLowering::Legal: 5583 if (!TLI.isTypeLegal(NewInTy)) 5584 break; // Can't use this datatype. 5585 // FALL THROUGH. 5586 case TargetLowering::Custom: 5587 OpToUse = ISD::UINT_TO_FP; 5588 break; 5589 } 5590 if (OpToUse) break; 5591 5592 // Otherwise, try a larger type. 5593 } 5594 5595 // Okay, we found the operation and type to use. Zero extend our input to the 5596 // desired type then run the operation on it. 5597 return DAG.getNode(OpToUse, DestVT, 5598 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5599 NewInTy, LegalOp)); 5600} 5601 5602/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5603/// FP_TO_*INT operation of the specified operand when the target requests that 5604/// we promote it. At this point, we know that the result and operand types are 5605/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5606/// operation that returns a larger result. 5607SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 5608 MVT DestVT, 5609 bool isSigned) { 5610 // First step, figure out the appropriate FP_TO*INT operation to use. 5611 MVT NewOutTy = DestVT; 5612 5613 unsigned OpToUse = 0; 5614 5615 // Scan for the appropriate larger type to use. 5616 while (1) { 5617 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 5618 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 5619 5620 // If the target supports FP_TO_SINT returning this type, use it. 5621 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5622 default: break; 5623 case TargetLowering::Legal: 5624 if (!TLI.isTypeLegal(NewOutTy)) 5625 break; // Can't use this datatype. 5626 // FALL THROUGH. 5627 case TargetLowering::Custom: 5628 OpToUse = ISD::FP_TO_SINT; 5629 break; 5630 } 5631 if (OpToUse) break; 5632 5633 // If the target supports FP_TO_UINT of this type, use it. 5634 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5635 default: break; 5636 case TargetLowering::Legal: 5637 if (!TLI.isTypeLegal(NewOutTy)) 5638 break; // Can't use this datatype. 5639 // FALL THROUGH. 5640 case TargetLowering::Custom: 5641 OpToUse = ISD::FP_TO_UINT; 5642 break; 5643 } 5644 if (OpToUse) break; 5645 5646 // Otherwise, try a larger type. 5647 } 5648 5649 5650 // Okay, we found the operation and type to use. 5651 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5652 5653 // If the operation produces an invalid type, it must be custom lowered. Use 5654 // the target lowering hooks to expand it. Just keep the low part of the 5655 // expanded operation, we know that we're truncating anyway. 5656 if (getTypeAction(NewOutTy) == Expand) { 5657 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0); 5658 assert(Operation.Val && "Didn't return anything"); 5659 } 5660 5661 // Truncate the result of the extended FP_TO_*INT operation to the desired 5662 // size. 5663 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5664} 5665 5666/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5667/// 5668SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 5669 MVT VT = Op.getValueType(); 5670 MVT SHVT = TLI.getShiftAmountTy(); 5671 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5672 switch (VT.getSimpleVT()) { 5673 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5674 case MVT::i16: 5675 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5676 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5677 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5678 case MVT::i32: 5679 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5680 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5681 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5682 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5683 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5684 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5685 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5686 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5687 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5688 case MVT::i64: 5689 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5690 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5691 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5692 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5693 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5694 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5695 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5696 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5697 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5698 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5699 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5700 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5701 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5702 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5703 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5704 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5705 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5706 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5707 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5708 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5709 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5710 } 5711} 5712 5713/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5714/// 5715SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 5716 switch (Opc) { 5717 default: assert(0 && "Cannot expand this yet!"); 5718 case ISD::CTPOP: { 5719 static const uint64_t mask[6] = { 5720 0x5555555555555555ULL, 0x3333333333333333ULL, 5721 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5722 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5723 }; 5724 MVT VT = Op.getValueType(); 5725 MVT ShVT = TLI.getShiftAmountTy(); 5726 unsigned len = VT.getSizeInBits(); 5727 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5728 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5729 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 5730 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5731 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5732 DAG.getNode(ISD::AND, VT, 5733 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5734 } 5735 return Op; 5736 } 5737 case ISD::CTLZ: { 5738 // for now, we do this: 5739 // x = x | (x >> 1); 5740 // x = x | (x >> 2); 5741 // ... 5742 // x = x | (x >>16); 5743 // x = x | (x >>32); // for 64-bit input 5744 // return popcount(~x); 5745 // 5746 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5747 MVT VT = Op.getValueType(); 5748 MVT ShVT = TLI.getShiftAmountTy(); 5749 unsigned len = VT.getSizeInBits(); 5750 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5751 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5752 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5753 } 5754 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5755 return DAG.getNode(ISD::CTPOP, VT, Op); 5756 } 5757 case ISD::CTTZ: { 5758 // for now, we use: { return popcount(~x & (x - 1)); } 5759 // unless the target has ctlz but not ctpop, in which case we use: 5760 // { return 32 - nlz(~x & (x-1)); } 5761 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5762 MVT VT = Op.getValueType(); 5763 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 5764 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 5765 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5766 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5767 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5768 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5769 TLI.isOperationLegal(ISD::CTLZ, VT)) 5770 return DAG.getNode(ISD::SUB, VT, 5771 DAG.getConstant(VT.getSizeInBits(), VT), 5772 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5773 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5774 } 5775 } 5776} 5777 5778/// ExpandOp - Expand the specified SDOperand into its two component pieces 5779/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5780/// LegalizeNodes map is filled in for any results that are not expanded, the 5781/// ExpandedNodes map is filled in for any results that are expanded, and the 5782/// Lo/Hi values are returned. 5783void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 5784 MVT VT = Op.getValueType(); 5785 MVT NVT = TLI.getTypeToTransformTo(VT); 5786 SDNode *Node = Op.Val; 5787 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5788 assert(((NVT.isInteger() && NVT < VT) || VT.isFloatingPoint() || 5789 VT.isVector()) && "Cannot expand to FP value or to larger int value!"); 5790 5791 // See if we already expanded it. 5792 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5793 = ExpandedNodes.find(Op); 5794 if (I != ExpandedNodes.end()) { 5795 Lo = I->second.first; 5796 Hi = I->second.second; 5797 return; 5798 } 5799 5800 switch (Node->getOpcode()) { 5801 case ISD::CopyFromReg: 5802 assert(0 && "CopyFromReg must be legal!"); 5803 case ISD::FP_ROUND_INREG: 5804 if (VT == MVT::ppcf128 && 5805 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5806 TargetLowering::Custom) { 5807 SDOperand SrcLo, SrcHi, Src; 5808 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5809 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5810 SDOperand Result = TLI.LowerOperation( 5811 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5812 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5813 Lo = Result.Val->getOperand(0); 5814 Hi = Result.Val->getOperand(1); 5815 break; 5816 } 5817 // fall through 5818 default: 5819#ifndef NDEBUG 5820 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5821#endif 5822 assert(0 && "Do not know how to expand this operator!"); 5823 abort(); 5824 case ISD::EXTRACT_ELEMENT: 5825 ExpandOp(Node->getOperand(0), Lo, Hi); 5826 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 5827 return ExpandOp(Hi, Lo, Hi); 5828 return ExpandOp(Lo, Lo, Hi); 5829 case ISD::EXTRACT_VECTOR_ELT: 5830 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5831 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5832 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5833 return ExpandOp(Lo, Lo, Hi); 5834 case ISD::UNDEF: 5835 NVT = TLI.getTypeToExpandTo(VT); 5836 Lo = DAG.getNode(ISD::UNDEF, NVT); 5837 Hi = DAG.getNode(ISD::UNDEF, NVT); 5838 break; 5839 case ISD::Constant: { 5840 unsigned NVTBits = NVT.getSizeInBits(); 5841 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 5842 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 5843 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 5844 break; 5845 } 5846 case ISD::ConstantFP: { 5847 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5848 if (CFP->getValueType(0) == MVT::ppcf128) { 5849 APInt api = CFP->getValueAPF().convertToAPInt(); 5850 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5851 MVT::f64); 5852 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5853 MVT::f64); 5854 break; 5855 } 5856 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5857 if (getTypeAction(Lo.getValueType()) == Expand) 5858 ExpandOp(Lo, Lo, Hi); 5859 break; 5860 } 5861 case ISD::BUILD_PAIR: 5862 // Return the operands. 5863 Lo = Node->getOperand(0); 5864 Hi = Node->getOperand(1); 5865 break; 5866 5867 case ISD::MERGE_VALUES: 5868 if (Node->getNumValues() == 1) { 5869 ExpandOp(Op.getOperand(0), Lo, Hi); 5870 break; 5871 } 5872 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5873 assert(Op.ResNo == 0 && Node->getNumValues() == 2 && 5874 Op.getValue(1).getValueType() == MVT::Other && 5875 "unhandled MERGE_VALUES"); 5876 ExpandOp(Op.getOperand(0), Lo, Hi); 5877 // Remember that we legalized the chain. 5878 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5879 break; 5880 5881 case ISD::SIGN_EXTEND_INREG: 5882 ExpandOp(Node->getOperand(0), Lo, Hi); 5883 // sext_inreg the low part if needed. 5884 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5885 5886 // The high part gets the sign extension from the lo-part. This handles 5887 // things like sextinreg V:i64 from i8. 5888 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5889 DAG.getConstant(NVT.getSizeInBits()-1, 5890 TLI.getShiftAmountTy())); 5891 break; 5892 5893 case ISD::BSWAP: { 5894 ExpandOp(Node->getOperand(0), Lo, Hi); 5895 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5896 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5897 Lo = TempLo; 5898 break; 5899 } 5900 5901 case ISD::CTPOP: 5902 ExpandOp(Node->getOperand(0), Lo, Hi); 5903 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5904 DAG.getNode(ISD::CTPOP, NVT, Lo), 5905 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5906 Hi = DAG.getConstant(0, NVT); 5907 break; 5908 5909 case ISD::CTLZ: { 5910 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5911 ExpandOp(Node->getOperand(0), Lo, Hi); 5912 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 5913 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5914 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC, 5915 ISD::SETNE); 5916 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5917 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5918 5919 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5920 Hi = DAG.getConstant(0, NVT); 5921 break; 5922 } 5923 5924 case ISD::CTTZ: { 5925 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5926 ExpandOp(Node->getOperand(0), Lo, Hi); 5927 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 5928 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5929 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC, 5930 ISD::SETNE); 5931 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5932 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5933 5934 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5935 Hi = DAG.getConstant(0, NVT); 5936 break; 5937 } 5938 5939 case ISD::VAARG: { 5940 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5941 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5942 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5943 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5944 5945 // Remember that we legalized the chain. 5946 Hi = LegalizeOp(Hi); 5947 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5948 if (TLI.isBigEndian()) 5949 std::swap(Lo, Hi); 5950 break; 5951 } 5952 5953 case ISD::LOAD: { 5954 LoadSDNode *LD = cast<LoadSDNode>(Node); 5955 SDOperand Ch = LD->getChain(); // Legalize the chain. 5956 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5957 ISD::LoadExtType ExtType = LD->getExtensionType(); 5958 int SVOffset = LD->getSrcValueOffset(); 5959 unsigned Alignment = LD->getAlignment(); 5960 bool isVolatile = LD->isVolatile(); 5961 5962 if (ExtType == ISD::NON_EXTLOAD) { 5963 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5964 isVolatile, Alignment); 5965 if (VT == MVT::f32 || VT == MVT::f64) { 5966 // f32->i32 or f64->i64 one to one expansion. 5967 // Remember that we legalized the chain. 5968 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5969 // Recursively expand the new load. 5970 if (getTypeAction(NVT) == Expand) 5971 ExpandOp(Lo, Lo, Hi); 5972 break; 5973 } 5974 5975 // Increment the pointer to the other half. 5976 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; 5977 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5978 DAG.getIntPtrConstant(IncrementSize)); 5979 SVOffset += IncrementSize; 5980 Alignment = MinAlign(Alignment, IncrementSize); 5981 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5982 isVolatile, Alignment); 5983 5984 // Build a factor node to remember that this load is independent of the 5985 // other one. 5986 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5987 Hi.getValue(1)); 5988 5989 // Remember that we legalized the chain. 5990 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5991 if (TLI.isBigEndian()) 5992 std::swap(Lo, Hi); 5993 } else { 5994 MVT EVT = LD->getMemoryVT(); 5995 5996 if ((VT == MVT::f64 && EVT == MVT::f32) || 5997 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 5998 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5999 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 6000 SVOffset, isVolatile, Alignment); 6001 // Remember that we legalized the chain. 6002 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 6003 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 6004 break; 6005 } 6006 6007 if (EVT == NVT) 6008 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 6009 SVOffset, isVolatile, Alignment); 6010 else 6011 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 6012 SVOffset, EVT, isVolatile, 6013 Alignment); 6014 6015 // Remember that we legalized the chain. 6016 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 6017 6018 if (ExtType == ISD::SEXTLOAD) { 6019 // The high part is obtained by SRA'ing all but one of the bits of the 6020 // lo part. 6021 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6022 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6023 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6024 } else if (ExtType == ISD::ZEXTLOAD) { 6025 // The high part is just a zero. 6026 Hi = DAG.getConstant(0, NVT); 6027 } else /* if (ExtType == ISD::EXTLOAD) */ { 6028 // The high part is undefined. 6029 Hi = DAG.getNode(ISD::UNDEF, NVT); 6030 } 6031 } 6032 break; 6033 } 6034 case ISD::AND: 6035 case ISD::OR: 6036 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 6037 SDOperand LL, LH, RL, RH; 6038 ExpandOp(Node->getOperand(0), LL, LH); 6039 ExpandOp(Node->getOperand(1), RL, RH); 6040 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 6041 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 6042 break; 6043 } 6044 case ISD::SELECT: { 6045 SDOperand LL, LH, RL, RH; 6046 ExpandOp(Node->getOperand(1), LL, LH); 6047 ExpandOp(Node->getOperand(2), RL, RH); 6048 if (getTypeAction(NVT) == Expand) 6049 NVT = TLI.getTypeToExpandTo(NVT); 6050 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 6051 if (VT != MVT::f32) 6052 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 6053 break; 6054 } 6055 case ISD::SELECT_CC: { 6056 SDOperand TL, TH, FL, FH; 6057 ExpandOp(Node->getOperand(2), TL, TH); 6058 ExpandOp(Node->getOperand(3), FL, FH); 6059 if (getTypeAction(NVT) == Expand) 6060 NVT = TLI.getTypeToExpandTo(NVT); 6061 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6062 Node->getOperand(1), TL, FL, Node->getOperand(4)); 6063 if (VT != MVT::f32) 6064 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6065 Node->getOperand(1), TH, FH, Node->getOperand(4)); 6066 break; 6067 } 6068 case ISD::ANY_EXTEND: 6069 // The low part is any extension of the input (which degenerates to a copy). 6070 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 6071 // The high part is undefined. 6072 Hi = DAG.getNode(ISD::UNDEF, NVT); 6073 break; 6074 case ISD::SIGN_EXTEND: { 6075 // The low part is just a sign extension of the input (which degenerates to 6076 // a copy). 6077 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 6078 6079 // The high part is obtained by SRA'ing all but one of the bits of the lo 6080 // part. 6081 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6082 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6083 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6084 break; 6085 } 6086 case ISD::ZERO_EXTEND: 6087 // The low part is just a zero extension of the input (which degenerates to 6088 // a copy). 6089 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 6090 6091 // The high part is just a zero. 6092 Hi = DAG.getConstant(0, NVT); 6093 break; 6094 6095 case ISD::TRUNCATE: { 6096 // The input value must be larger than this value. Expand *it*. 6097 SDOperand NewLo; 6098 ExpandOp(Node->getOperand(0), NewLo, Hi); 6099 6100 // The low part is now either the right size, or it is closer. If not the 6101 // right size, make an illegal truncate so we recursively expand it. 6102 if (NewLo.getValueType() != Node->getValueType(0)) 6103 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 6104 ExpandOp(NewLo, Lo, Hi); 6105 break; 6106 } 6107 6108 case ISD::BIT_CONVERT: { 6109 SDOperand Tmp; 6110 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6111 // If the target wants to, allow it to lower this itself. 6112 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6113 case Expand: assert(0 && "cannot expand FP!"); 6114 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6115 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6116 } 6117 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 6118 } 6119 6120 // f32 / f64 must be expanded to i32 / i64. 6121 if (VT == MVT::f32 || VT == MVT::f64) { 6122 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6123 if (getTypeAction(NVT) == Expand) 6124 ExpandOp(Lo, Lo, Hi); 6125 break; 6126 } 6127 6128 // If source operand will be expanded to the same type as VT, i.e. 6129 // i64 <- f64, i32 <- f32, expand the source operand instead. 6130 MVT VT0 = Node->getOperand(0).getValueType(); 6131 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6132 ExpandOp(Node->getOperand(0), Lo, Hi); 6133 break; 6134 } 6135 6136 // Turn this into a load/store pair by default. 6137 if (Tmp.Val == 0) 6138 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 6139 6140 ExpandOp(Tmp, Lo, Hi); 6141 break; 6142 } 6143 6144 case ISD::READCYCLECOUNTER: { 6145 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6146 TargetLowering::Custom && 6147 "Must custom expand ReadCycleCounter"); 6148 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 6149 assert(Tmp.Val && "Node must be custom expanded!"); 6150 ExpandOp(Tmp.getValue(0), Lo, Hi); 6151 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 6152 LegalizeOp(Tmp.getValue(1))); 6153 break; 6154 } 6155 6156 case ISD::ATOMIC_LCS: { 6157 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 6158 assert(Tmp.Val && "Node must be custom expanded!"); 6159 ExpandOp(Tmp.getValue(0), Lo, Hi); 6160 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 6161 LegalizeOp(Tmp.getValue(1))); 6162 break; 6163 } 6164 6165 6166 6167 // These operators cannot be expanded directly, emit them as calls to 6168 // library functions. 6169 case ISD::FP_TO_SINT: { 6170 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6171 SDOperand Op; 6172 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6173 case Expand: assert(0 && "cannot expand FP!"); 6174 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6175 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6176 } 6177 6178 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 6179 6180 // Now that the custom expander is done, expand the result, which is still 6181 // VT. 6182 if (Op.Val) { 6183 ExpandOp(Op, Lo, Hi); 6184 break; 6185 } 6186 } 6187 6188 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6189 if (VT == MVT::i64) { 6190 if (Node->getOperand(0).getValueType() == MVT::f32) 6191 LC = RTLIB::FPTOSINT_F32_I64; 6192 else if (Node->getOperand(0).getValueType() == MVT::f64) 6193 LC = RTLIB::FPTOSINT_F64_I64; 6194 else if (Node->getOperand(0).getValueType() == MVT::f80) 6195 LC = RTLIB::FPTOSINT_F80_I64; 6196 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6197 LC = RTLIB::FPTOSINT_PPCF128_I64; 6198 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6199 } else if (VT == MVT::i128) { 6200 if (Node->getOperand(0).getValueType() == MVT::f32) 6201 LC = RTLIB::FPTOSINT_F32_I128; 6202 else if (Node->getOperand(0).getValueType() == MVT::f64) 6203 LC = RTLIB::FPTOSINT_F64_I128; 6204 else if (Node->getOperand(0).getValueType() == MVT::f80) 6205 LC = RTLIB::FPTOSINT_F80_I128; 6206 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6207 LC = RTLIB::FPTOSINT_PPCF128_I128; 6208 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6209 } else { 6210 assert(0 && "Unexpected uint-to-fp conversion!"); 6211 } 6212 break; 6213 } 6214 6215 case ISD::FP_TO_UINT: { 6216 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6217 SDOperand Op; 6218 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6219 case Expand: assert(0 && "cannot expand FP!"); 6220 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6221 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6222 } 6223 6224 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 6225 6226 // Now that the custom expander is done, expand the result. 6227 if (Op.Val) { 6228 ExpandOp(Op, Lo, Hi); 6229 break; 6230 } 6231 } 6232 6233 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6234 if (VT == MVT::i64) { 6235 if (Node->getOperand(0).getValueType() == MVT::f32) 6236 LC = RTLIB::FPTOUINT_F32_I64; 6237 else if (Node->getOperand(0).getValueType() == MVT::f64) 6238 LC = RTLIB::FPTOUINT_F64_I64; 6239 else if (Node->getOperand(0).getValueType() == MVT::f80) 6240 LC = RTLIB::FPTOUINT_F80_I64; 6241 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6242 LC = RTLIB::FPTOUINT_PPCF128_I64; 6243 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6244 } else if (VT == MVT::i128) { 6245 if (Node->getOperand(0).getValueType() == MVT::f32) 6246 LC = RTLIB::FPTOUINT_F32_I128; 6247 else if (Node->getOperand(0).getValueType() == MVT::f64) 6248 LC = RTLIB::FPTOUINT_F64_I128; 6249 else if (Node->getOperand(0).getValueType() == MVT::f80) 6250 LC = RTLIB::FPTOUINT_F80_I128; 6251 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6252 LC = RTLIB::FPTOUINT_PPCF128_I128; 6253 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6254 } else { 6255 assert(0 && "Unexpected uint-to-fp conversion!"); 6256 } 6257 break; 6258 } 6259 6260 case ISD::SHL: { 6261 // If the target wants custom lowering, do so. 6262 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6263 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6264 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 6265 Op = TLI.LowerOperation(Op, DAG); 6266 if (Op.Val) { 6267 // Now that the custom expander is done, expand the result, which is 6268 // still VT. 6269 ExpandOp(Op, Lo, Hi); 6270 break; 6271 } 6272 } 6273 6274 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6275 // this X << 1 as X+X. 6276 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6277 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 6278 TLI.isOperationLegal(ISD::ADDE, NVT)) { 6279 SDOperand LoOps[2], HiOps[3]; 6280 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6281 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6282 LoOps[1] = LoOps[0]; 6283 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6284 6285 HiOps[1] = HiOps[0]; 6286 HiOps[2] = Lo.getValue(1); 6287 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6288 break; 6289 } 6290 } 6291 6292 // If we can emit an efficient shift operation, do so now. 6293 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6294 break; 6295 6296 // If this target supports SHL_PARTS, use it. 6297 TargetLowering::LegalizeAction Action = 6298 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6299 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6300 Action == TargetLowering::Custom) { 6301 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6302 break; 6303 } 6304 6305 // Otherwise, emit a libcall. 6306 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi); 6307 break; 6308 } 6309 6310 case ISD::SRA: { 6311 // If the target wants custom lowering, do so. 6312 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6313 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6314 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6315 Op = TLI.LowerOperation(Op, DAG); 6316 if (Op.Val) { 6317 // Now that the custom expander is done, expand the result, which is 6318 // still VT. 6319 ExpandOp(Op, Lo, Hi); 6320 break; 6321 } 6322 } 6323 6324 // If we can emit an efficient shift operation, do so now. 6325 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6326 break; 6327 6328 // If this target supports SRA_PARTS, use it. 6329 TargetLowering::LegalizeAction Action = 6330 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6331 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6332 Action == TargetLowering::Custom) { 6333 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6334 break; 6335 } 6336 6337 // Otherwise, emit a libcall. 6338 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi); 6339 break; 6340 } 6341 6342 case ISD::SRL: { 6343 // If the target wants custom lowering, do so. 6344 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6345 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6346 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 6347 Op = TLI.LowerOperation(Op, DAG); 6348 if (Op.Val) { 6349 // Now that the custom expander is done, expand the result, which is 6350 // still VT. 6351 ExpandOp(Op, Lo, Hi); 6352 break; 6353 } 6354 } 6355 6356 // If we can emit an efficient shift operation, do so now. 6357 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6358 break; 6359 6360 // If this target supports SRL_PARTS, use it. 6361 TargetLowering::LegalizeAction Action = 6362 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6363 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6364 Action == TargetLowering::Custom) { 6365 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6366 break; 6367 } 6368 6369 // Otherwise, emit a libcall. 6370 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi); 6371 break; 6372 } 6373 6374 case ISD::ADD: 6375 case ISD::SUB: { 6376 // If the target wants to custom expand this, let them. 6377 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6378 TargetLowering::Custom) { 6379 Op = TLI.LowerOperation(Op, DAG); 6380 if (Op.Val) { 6381 ExpandOp(Op, Lo, Hi); 6382 break; 6383 } 6384 } 6385 6386 // Expand the subcomponents. 6387 SDOperand LHSL, LHSH, RHSL, RHSH; 6388 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6389 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6390 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6391 SDOperand LoOps[2], HiOps[3]; 6392 LoOps[0] = LHSL; 6393 LoOps[1] = RHSL; 6394 HiOps[0] = LHSH; 6395 HiOps[1] = RHSH; 6396 if (Node->getOpcode() == ISD::ADD) { 6397 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6398 HiOps[2] = Lo.getValue(1); 6399 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6400 } else { 6401 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6402 HiOps[2] = Lo.getValue(1); 6403 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6404 } 6405 break; 6406 } 6407 6408 case ISD::ADDC: 6409 case ISD::SUBC: { 6410 // Expand the subcomponents. 6411 SDOperand LHSL, LHSH, RHSL, RHSH; 6412 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6413 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6414 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6415 SDOperand LoOps[2] = { LHSL, RHSL }; 6416 SDOperand HiOps[3] = { LHSH, RHSH }; 6417 6418 if (Node->getOpcode() == ISD::ADDC) { 6419 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6420 HiOps[2] = Lo.getValue(1); 6421 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6422 } else { 6423 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6424 HiOps[2] = Lo.getValue(1); 6425 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6426 } 6427 // Remember that we legalized the flag. 6428 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6429 break; 6430 } 6431 case ISD::ADDE: 6432 case ISD::SUBE: { 6433 // Expand the subcomponents. 6434 SDOperand LHSL, LHSH, RHSL, RHSH; 6435 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6436 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6437 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6438 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 6439 SDOperand HiOps[3] = { LHSH, RHSH }; 6440 6441 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 6442 HiOps[2] = Lo.getValue(1); 6443 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 6444 6445 // Remember that we legalized the flag. 6446 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6447 break; 6448 } 6449 case ISD::MUL: { 6450 // If the target wants to custom expand this, let them. 6451 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 6452 SDOperand New = TLI.LowerOperation(Op, DAG); 6453 if (New.Val) { 6454 ExpandOp(New, Lo, Hi); 6455 break; 6456 } 6457 } 6458 6459 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 6460 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 6461 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 6462 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 6463 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 6464 SDOperand LL, LH, RL, RH; 6465 ExpandOp(Node->getOperand(0), LL, LH); 6466 ExpandOp(Node->getOperand(1), RL, RH); 6467 unsigned OuterBitSize = Op.getValueSizeInBits(); 6468 unsigned InnerBitSize = RH.getValueSizeInBits(); 6469 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 6470 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 6471 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 6472 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 6473 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 6474 // The inputs are both zero-extended. 6475 if (HasUMUL_LOHI) { 6476 // We can emit a umul_lohi. 6477 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6478 Hi = SDOperand(Lo.Val, 1); 6479 break; 6480 } 6481 if (HasMULHU) { 6482 // We can emit a mulhu+mul. 6483 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6484 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6485 break; 6486 } 6487 } 6488 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 6489 // The input values are both sign-extended. 6490 if (HasSMUL_LOHI) { 6491 // We can emit a smul_lohi. 6492 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6493 Hi = SDOperand(Lo.Val, 1); 6494 break; 6495 } 6496 if (HasMULHS) { 6497 // We can emit a mulhs+mul. 6498 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6499 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6500 break; 6501 } 6502 } 6503 if (HasUMUL_LOHI) { 6504 // Lo,Hi = umul LHS, RHS. 6505 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6506 DAG.getVTList(NVT, NVT), LL, RL); 6507 Lo = UMulLOHI; 6508 Hi = UMulLOHI.getValue(1); 6509 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6510 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6511 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6512 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6513 break; 6514 } 6515 if (HasMULHU) { 6516 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6517 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6518 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6519 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6520 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6521 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6522 break; 6523 } 6524 } 6525 6526 // If nothing else, we can make a libcall. 6527 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi); 6528 break; 6529 } 6530 case ISD::SDIV: 6531 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi); 6532 break; 6533 case ISD::UDIV: 6534 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi); 6535 break; 6536 case ISD::SREM: 6537 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi); 6538 break; 6539 case ISD::UREM: 6540 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi); 6541 break; 6542 6543 case ISD::FADD: 6544 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32, 6545 RTLIB::ADD_F64, 6546 RTLIB::ADD_F80, 6547 RTLIB::ADD_PPCF128), 6548 Node, false, Hi); 6549 break; 6550 case ISD::FSUB: 6551 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32, 6552 RTLIB::SUB_F64, 6553 RTLIB::SUB_F80, 6554 RTLIB::SUB_PPCF128), 6555 Node, false, Hi); 6556 break; 6557 case ISD::FMUL: 6558 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32, 6559 RTLIB::MUL_F64, 6560 RTLIB::MUL_F80, 6561 RTLIB::MUL_PPCF128), 6562 Node, false, Hi); 6563 break; 6564 case ISD::FDIV: 6565 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32, 6566 RTLIB::DIV_F64, 6567 RTLIB::DIV_F80, 6568 RTLIB::DIV_PPCF128), 6569 Node, false, Hi); 6570 break; 6571 case ISD::FP_EXTEND: 6572 if (VT == MVT::ppcf128) { 6573 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6574 Node->getOperand(0).getValueType()==MVT::f64); 6575 const uint64_t zero = 0; 6576 if (Node->getOperand(0).getValueType()==MVT::f32) 6577 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6578 else 6579 Hi = Node->getOperand(0); 6580 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6581 break; 6582 } 6583 Lo = ExpandLibCall(RTLIB::FPEXT_F32_F64, Node, true, Hi); 6584 break; 6585 case ISD::FP_ROUND: 6586 Lo = ExpandLibCall(RTLIB::FPROUND_F64_F32, Node, true, Hi); 6587 break; 6588 case ISD::FPOWI: 6589 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32, 6590 RTLIB::POWI_F64, 6591 RTLIB::POWI_F80, 6592 RTLIB::POWI_PPCF128), 6593 Node, false, Hi); 6594 break; 6595 case ISD::FSQRT: 6596 case ISD::FSIN: 6597 case ISD::FCOS: { 6598 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6599 switch(Node->getOpcode()) { 6600 case ISD::FSQRT: 6601 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 6602 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 6603 break; 6604 case ISD::FSIN: 6605 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 6606 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 6607 break; 6608 case ISD::FCOS: 6609 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 6610 RTLIB::COS_F80, RTLIB::COS_PPCF128); 6611 break; 6612 default: assert(0 && "Unreachable!"); 6613 } 6614 Lo = ExpandLibCall(LC, Node, false, Hi); 6615 break; 6616 } 6617 case ISD::FABS: { 6618 if (VT == MVT::ppcf128) { 6619 SDOperand Tmp; 6620 ExpandOp(Node->getOperand(0), Lo, Tmp); 6621 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6622 // lo = hi==fabs(hi) ? lo : -lo; 6623 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6624 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6625 DAG.getCondCode(ISD::SETEQ)); 6626 break; 6627 } 6628 SDOperand Mask = (VT == MVT::f64) 6629 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6630 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6631 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6632 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6633 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6634 if (getTypeAction(NVT) == Expand) 6635 ExpandOp(Lo, Lo, Hi); 6636 break; 6637 } 6638 case ISD::FNEG: { 6639 if (VT == MVT::ppcf128) { 6640 ExpandOp(Node->getOperand(0), Lo, Hi); 6641 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6642 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6643 break; 6644 } 6645 SDOperand Mask = (VT == MVT::f64) 6646 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6647 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6648 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6649 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6650 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6651 if (getTypeAction(NVT) == Expand) 6652 ExpandOp(Lo, Lo, Hi); 6653 break; 6654 } 6655 case ISD::FCOPYSIGN: { 6656 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6657 if (getTypeAction(NVT) == Expand) 6658 ExpandOp(Lo, Lo, Hi); 6659 break; 6660 } 6661 case ISD::SINT_TO_FP: 6662 case ISD::UINT_TO_FP: { 6663 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6664 MVT SrcVT = Node->getOperand(0).getValueType(); 6665 6666 // Promote the operand if needed. Do this before checking for 6667 // ppcf128 so conversions of i16 and i8 work. 6668 if (getTypeAction(SrcVT) == Promote) { 6669 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 6670 Tmp = isSigned 6671 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6672 DAG.getValueType(SrcVT)) 6673 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6674 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6675 SrcVT = Node->getOperand(0).getValueType(); 6676 } 6677 6678 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 6679 static const uint64_t zero = 0; 6680 if (isSigned) { 6681 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6682 Node->getOperand(0))); 6683 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6684 } else { 6685 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6686 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6687 Node->getOperand(0))); 6688 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6689 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6690 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6691 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6692 DAG.getConstant(0, MVT::i32), 6693 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6694 DAG.getConstantFP( 6695 APFloat(APInt(128, 2, TwoE32)), 6696 MVT::ppcf128)), 6697 Hi, 6698 DAG.getCondCode(ISD::SETLT)), 6699 Lo, Hi); 6700 } 6701 break; 6702 } 6703 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6704 // si64->ppcf128 done by libcall, below 6705 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6706 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6707 Lo, Hi); 6708 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6709 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6710 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6711 DAG.getConstant(0, MVT::i64), 6712 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6713 DAG.getConstantFP( 6714 APFloat(APInt(128, 2, TwoE64)), 6715 MVT::ppcf128)), 6716 Hi, 6717 DAG.getCondCode(ISD::SETLT)), 6718 Lo, Hi); 6719 break; 6720 } 6721 6722 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6723 Node->getOperand(0)); 6724 if (getTypeAction(Lo.getValueType()) == Expand) 6725 // float to i32 etc. can be 'expanded' to a single node. 6726 ExpandOp(Lo, Lo, Hi); 6727 break; 6728 } 6729 } 6730 6731 // Make sure the resultant values have been legalized themselves, unless this 6732 // is a type that requires multi-step expansion. 6733 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6734 Lo = LegalizeOp(Lo); 6735 if (Hi.Val) 6736 // Don't legalize the high part if it is expanded to a single node. 6737 Hi = LegalizeOp(Hi); 6738 } 6739 6740 // Remember in a map if the values will be reused later. 6741 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 6742 assert(isNew && "Value already expanded?!?"); 6743} 6744 6745/// SplitVectorOp - Given an operand of vector type, break it down into 6746/// two smaller values, still of vector type. 6747void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 6748 SDOperand &Hi) { 6749 assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); 6750 SDNode *Node = Op.Val; 6751 unsigned NumElements = Op.getValueType().getVectorNumElements(); 6752 assert(NumElements > 1 && "Cannot split a single element vector!"); 6753 6754 MVT NewEltVT = Op.getValueType().getVectorElementType(); 6755 6756 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6757 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6758 6759 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); 6760 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); 6761 6762 // See if we already split it. 6763 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 6764 = SplitNodes.find(Op); 6765 if (I != SplitNodes.end()) { 6766 Lo = I->second.first; 6767 Hi = I->second.second; 6768 return; 6769 } 6770 6771 switch (Node->getOpcode()) { 6772 default: 6773#ifndef NDEBUG 6774 Node->dump(&DAG); 6775#endif 6776 assert(0 && "Unhandled operation in SplitVectorOp!"); 6777 case ISD::UNDEF: 6778 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6779 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6780 break; 6781 case ISD::BUILD_PAIR: 6782 Lo = Node->getOperand(0); 6783 Hi = Node->getOperand(1); 6784 break; 6785 case ISD::INSERT_VECTOR_ELT: { 6786 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 6787 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6788 unsigned Index = Idx->getValue(); 6789 SDOperand ScalarOp = Node->getOperand(1); 6790 if (Index < NewNumElts_Lo) 6791 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6792 DAG.getIntPtrConstant(Index)); 6793 else 6794 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6795 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 6796 break; 6797 } 6798 SDOperand Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), 6799 Node->getOperand(1), 6800 Node->getOperand(2)); 6801 SplitVectorOp(Tmp, Lo, Hi); 6802 break; 6803 } 6804 case ISD::VECTOR_SHUFFLE: { 6805 // Build the low part. 6806 SDOperand Mask = Node->getOperand(2); 6807 SmallVector<SDOperand, 8> Ops; 6808 MVT PtrVT = TLI.getPointerTy(); 6809 6810 // Insert all of the elements from the input that are needed. We use 6811 // buildvector of extractelement here because the input vectors will have 6812 // to be legalized, so this makes the code simpler. 6813 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 6814 SDOperand IdxNode = Mask.getOperand(i); 6815 if (IdxNode.getOpcode() == ISD::UNDEF) { 6816 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6817 continue; 6818 } 6819 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6820 SDOperand InVec = Node->getOperand(0); 6821 if (Idx >= NumElements) { 6822 InVec = Node->getOperand(1); 6823 Idx -= NumElements; 6824 } 6825 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6826 DAG.getConstant(Idx, PtrVT))); 6827 } 6828 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6829 Ops.clear(); 6830 6831 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 6832 SDOperand IdxNode = Mask.getOperand(i); 6833 if (IdxNode.getOpcode() == ISD::UNDEF) { 6834 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6835 continue; 6836 } 6837 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6838 SDOperand InVec = Node->getOperand(0); 6839 if (Idx >= NumElements) { 6840 InVec = Node->getOperand(1); 6841 Idx -= NumElements; 6842 } 6843 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6844 DAG.getConstant(Idx, PtrVT))); 6845 } 6846 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6847 break; 6848 } 6849 case ISD::BUILD_VECTOR: { 6850 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6851 Node->op_begin()+NewNumElts_Lo); 6852 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 6853 6854 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 6855 Node->op_end()); 6856 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 6857 break; 6858 } 6859 case ISD::CONCAT_VECTORS: { 6860 // FIXME: Handle non-power-of-two vectors? 6861 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6862 if (NewNumSubvectors == 1) { 6863 Lo = Node->getOperand(0); 6864 Hi = Node->getOperand(1); 6865 } else { 6866 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6867 Node->op_begin()+NewNumSubvectors); 6868 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 6869 6870 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6871 Node->op_end()); 6872 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 6873 } 6874 break; 6875 } 6876 case ISD::SELECT: { 6877 SDOperand Cond = Node->getOperand(0); 6878 6879 SDOperand LL, LH, RL, RH; 6880 SplitVectorOp(Node->getOperand(1), LL, LH); 6881 SplitVectorOp(Node->getOperand(2), RL, RH); 6882 6883 if (Cond.getValueType().isVector()) { 6884 // Handle a vector merge. 6885 SDOperand CL, CH; 6886 SplitVectorOp(Cond, CL, CH); 6887 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 6888 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 6889 } else { 6890 // Handle a simple select with vector operands. 6891 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 6892 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 6893 } 6894 break; 6895 } 6896 case ISD::VSETCC: { 6897 SDOperand LL, LH, RL, RH; 6898 SplitVectorOp(Node->getOperand(0), LL, LH); 6899 SplitVectorOp(Node->getOperand(1), RL, RH); 6900 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2)); 6901 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2)); 6902 break; 6903 } 6904 case ISD::ADD: 6905 case ISD::SUB: 6906 case ISD::MUL: 6907 case ISD::FADD: 6908 case ISD::FSUB: 6909 case ISD::FMUL: 6910 case ISD::SDIV: 6911 case ISD::UDIV: 6912 case ISD::FDIV: 6913 case ISD::FPOW: 6914 case ISD::AND: 6915 case ISD::OR: 6916 case ISD::XOR: 6917 case ISD::UREM: 6918 case ISD::SREM: 6919 case ISD::FREM: { 6920 SDOperand LL, LH, RL, RH; 6921 SplitVectorOp(Node->getOperand(0), LL, LH); 6922 SplitVectorOp(Node->getOperand(1), RL, RH); 6923 6924 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 6925 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 6926 break; 6927 } 6928 case ISD::FPOWI: { 6929 SDOperand L, H; 6930 SplitVectorOp(Node->getOperand(0), L, H); 6931 6932 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 6933 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 6934 break; 6935 } 6936 case ISD::CTTZ: 6937 case ISD::CTLZ: 6938 case ISD::CTPOP: 6939 case ISD::FNEG: 6940 case ISD::FABS: 6941 case ISD::FSQRT: 6942 case ISD::FSIN: 6943 case ISD::FCOS: 6944 case ISD::FP_TO_SINT: 6945 case ISD::FP_TO_UINT: 6946 case ISD::SINT_TO_FP: 6947 case ISD::UINT_TO_FP: { 6948 SDOperand L, H; 6949 SplitVectorOp(Node->getOperand(0), L, H); 6950 6951 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 6952 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 6953 break; 6954 } 6955 case ISD::LOAD: { 6956 LoadSDNode *LD = cast<LoadSDNode>(Node); 6957 SDOperand Ch = LD->getChain(); 6958 SDOperand Ptr = LD->getBasePtr(); 6959 const Value *SV = LD->getSrcValue(); 6960 int SVOffset = LD->getSrcValueOffset(); 6961 unsigned Alignment = LD->getAlignment(); 6962 bool isVolatile = LD->isVolatile(); 6963 6964 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6965 unsigned IncrementSize = NewNumElts_Lo * NewEltVT.getSizeInBits()/8; 6966 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6967 DAG.getIntPtrConstant(IncrementSize)); 6968 SVOffset += IncrementSize; 6969 Alignment = MinAlign(Alignment, IncrementSize); 6970 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6971 6972 // Build a factor node to remember that this load is independent of the 6973 // other one. 6974 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6975 Hi.getValue(1)); 6976 6977 // Remember that we legalized the chain. 6978 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6979 break; 6980 } 6981 case ISD::BIT_CONVERT: { 6982 // We know the result is a vector. The input may be either a vector or a 6983 // scalar value. 6984 SDOperand InOp = Node->getOperand(0); 6985 if (!InOp.getValueType().isVector() || 6986 InOp.getValueType().getVectorNumElements() == 1) { 6987 // The input is a scalar or single-element vector. 6988 // Lower to a store/load so that it can be split. 6989 // FIXME: this could be improved probably. 6990 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); 6991 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val); 6992 6993 SDOperand St = DAG.getStore(DAG.getEntryNode(), 6994 InOp, Ptr, 6995 PseudoSourceValue::getFixedStack(), 6996 FI->getIndex()); 6997 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, 6998 PseudoSourceValue::getFixedStack(), 6999 FI->getIndex()); 7000 } 7001 // Split the vector and convert each of the pieces now. 7002 SplitVectorOp(InOp, Lo, Hi); 7003 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 7004 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 7005 break; 7006 } 7007 } 7008 7009 // Remember in a map if the values will be reused later. 7010 bool isNew = 7011 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7012 assert(isNew && "Value already split?!?"); 7013} 7014 7015 7016/// ScalarizeVectorOp - Given an operand of single-element vector type 7017/// (e.g. v1f32), convert it into the equivalent operation that returns a 7018/// scalar (e.g. f32) value. 7019SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 7020 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); 7021 SDNode *Node = Op.Val; 7022 MVT NewVT = Op.getValueType().getVectorElementType(); 7023 assert(Op.getValueType().getVectorNumElements() == 1); 7024 7025 // See if we already scalarized it. 7026 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 7027 if (I != ScalarizedNodes.end()) return I->second; 7028 7029 SDOperand Result; 7030 switch (Node->getOpcode()) { 7031 default: 7032#ifndef NDEBUG 7033 Node->dump(&DAG); cerr << "\n"; 7034#endif 7035 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 7036 case ISD::ADD: 7037 case ISD::FADD: 7038 case ISD::SUB: 7039 case ISD::FSUB: 7040 case ISD::MUL: 7041 case ISD::FMUL: 7042 case ISD::SDIV: 7043 case ISD::UDIV: 7044 case ISD::FDIV: 7045 case ISD::SREM: 7046 case ISD::UREM: 7047 case ISD::FREM: 7048 case ISD::FPOW: 7049 case ISD::AND: 7050 case ISD::OR: 7051 case ISD::XOR: 7052 Result = DAG.getNode(Node->getOpcode(), 7053 NewVT, 7054 ScalarizeVectorOp(Node->getOperand(0)), 7055 ScalarizeVectorOp(Node->getOperand(1))); 7056 break; 7057 case ISD::FNEG: 7058 case ISD::FABS: 7059 case ISD::FSQRT: 7060 case ISD::FSIN: 7061 case ISD::FCOS: 7062 Result = DAG.getNode(Node->getOpcode(), 7063 NewVT, 7064 ScalarizeVectorOp(Node->getOperand(0))); 7065 break; 7066 case ISD::FPOWI: 7067 Result = DAG.getNode(Node->getOpcode(), 7068 NewVT, 7069 ScalarizeVectorOp(Node->getOperand(0)), 7070 Node->getOperand(1)); 7071 break; 7072 case ISD::LOAD: { 7073 LoadSDNode *LD = cast<LoadSDNode>(Node); 7074 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 7075 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 7076 7077 const Value *SV = LD->getSrcValue(); 7078 int SVOffset = LD->getSrcValueOffset(); 7079 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 7080 LD->isVolatile(), LD->getAlignment()); 7081 7082 // Remember that we legalized the chain. 7083 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 7084 break; 7085 } 7086 case ISD::BUILD_VECTOR: 7087 Result = Node->getOperand(0); 7088 break; 7089 case ISD::INSERT_VECTOR_ELT: 7090 // Returning the inserted scalar element. 7091 Result = Node->getOperand(1); 7092 break; 7093 case ISD::CONCAT_VECTORS: 7094 assert(Node->getOperand(0).getValueType() == NewVT && 7095 "Concat of non-legal vectors not yet supported!"); 7096 Result = Node->getOperand(0); 7097 break; 7098 case ISD::VECTOR_SHUFFLE: { 7099 // Figure out if the scalar is the LHS or RHS and return it. 7100 SDOperand EltNum = Node->getOperand(2).getOperand(0); 7101 if (cast<ConstantSDNode>(EltNum)->getValue()) 7102 Result = ScalarizeVectorOp(Node->getOperand(1)); 7103 else 7104 Result = ScalarizeVectorOp(Node->getOperand(0)); 7105 break; 7106 } 7107 case ISD::EXTRACT_SUBVECTOR: 7108 Result = Node->getOperand(0); 7109 assert(Result.getValueType() == NewVT); 7110 break; 7111 case ISD::BIT_CONVERT: { 7112 SDOperand Op0 = Op.getOperand(0); 7113 if (Op0.getValueType().getVectorNumElements() == 1) 7114 Op0 = ScalarizeVectorOp(Op0); 7115 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0); 7116 break; 7117 } 7118 case ISD::SELECT: 7119 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 7120 ScalarizeVectorOp(Op.getOperand(1)), 7121 ScalarizeVectorOp(Op.getOperand(2))); 7122 break; 7123 case ISD::VSETCC: { 7124 SDOperand Op0 = ScalarizeVectorOp(Op.getOperand(0)); 7125 SDOperand Op1 = ScalarizeVectorOp(Op.getOperand(1)); 7126 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1, 7127 Op.getOperand(2)); 7128 Result = DAG.getNode(ISD::SELECT, NewVT, Result, 7129 DAG.getConstant(-1ULL, NewVT), 7130 DAG.getConstant(0ULL, NewVT)); 7131 break; 7132 } 7133 } 7134 7135 if (TLI.isTypeLegal(NewVT)) 7136 Result = LegalizeOp(Result); 7137 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7138 assert(isNew && "Value already scalarized?"); 7139 return Result; 7140} 7141 7142 7143// SelectionDAG::Legalize - This is the entry point for the file. 7144// 7145void SelectionDAG::Legalize() { 7146 if (ViewLegalizeDAGs) viewGraph(); 7147 7148 /// run - This is the main entry point to this class. 7149 /// 7150 SelectionDAGLegalize(*this).LegalizeDAG(); 7151} 7152 7153